2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.21"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
79 #define SKY2_EEPROM_MAGIC 0x9955aabb
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93 static int copybreak __read_mostly = 128;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101 static const struct pci_device_id sky2_id_table[] = {
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
142 MODULE_DEVICE_TABLE(pci, sky2_id_table);
144 /* Avoid conditionals by using array */
145 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
147 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
149 /* This driver supports yukon2 chipset only */
150 static const char *yukon2_name[] = {
152 "EC Ultra", /* 0xb4 */
153 "Extreme", /* 0xb5 */
157 "Supreme", /* 0xb9 */
160 static void sky2_set_multicast(struct net_device *dev);
162 /* Access to PHY via serial interconnect */
163 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
167 gma_write16(hw, port, GM_SMI_DATA, val);
168 gma_write16(hw, port, GM_SMI_CTRL,
169 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
171 for (i = 0; i < PHY_RETRIES; i++) {
172 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
176 if (!(ctrl & GM_SMI_CT_BUSY))
182 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
186 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
190 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
194 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
195 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
197 for (i = 0; i < PHY_RETRIES; i++) {
198 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
202 if (ctrl & GM_SMI_CT_RD_VAL) {
203 *val = gma_read16(hw, port, GM_SMI_DATA);
210 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
213 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
217 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
220 __gm_phy_read(hw, port, reg, &v);
225 static void sky2_power_on(struct sky2_hw *hw)
227 /* switch power to VCC (WA for VAUX problem) */
228 sky2_write8(hw, B0_POWER_CTRL,
229 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
231 /* disable Core Clock Division, */
232 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
234 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
235 /* enable bits are inverted */
236 sky2_write8(hw, B2_Y2_CLK_GATE,
237 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
238 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
239 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
241 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
243 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
246 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
248 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
249 /* set all bits to 0 except bits 15..12 and 8 */
250 reg &= P_ASPM_CONTROL_MSK;
251 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
253 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
254 /* set all bits to 0 except bits 28 & 27 */
255 reg &= P_CTL_TIM_VMAIN_AV_MSK;
256 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
258 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
260 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
261 reg = sky2_read32(hw, B2_GP_IO);
262 reg |= GLB_GPIO_STAT_RACE_DIS;
263 sky2_write32(hw, B2_GP_IO, reg);
265 sky2_read32(hw, B2_GP_IO);
269 static void sky2_power_aux(struct sky2_hw *hw)
271 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
272 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
274 /* enable bits are inverted */
275 sky2_write8(hw, B2_Y2_CLK_GATE,
276 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
277 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
278 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
280 /* switch power to VAUX */
281 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
282 sky2_write8(hw, B0_POWER_CTRL,
283 (PC_VAUX_ENA | PC_VCC_ENA |
284 PC_VAUX_ON | PC_VCC_OFF));
287 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
291 /* disable all GMAC IRQ's */
292 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
294 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
295 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
299 reg = gma_read16(hw, port, GM_RX_CTRL);
300 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
301 gma_write16(hw, port, GM_RX_CTRL, reg);
304 /* flow control to advertise bits */
305 static const u16 copper_fc_adv[] = {
307 [FC_TX] = PHY_M_AN_ASP,
308 [FC_RX] = PHY_M_AN_PC,
309 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
312 /* flow control to advertise bits when using 1000BaseX */
313 static const u16 fiber_fc_adv[] = {
314 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
315 [FC_TX] = PHY_M_P_ASYM_MD_X,
316 [FC_RX] = PHY_M_P_SYM_MD_X,
317 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
320 /* flow control to GMA disable bits */
321 static const u16 gm_fc_disable[] = {
322 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
323 [FC_TX] = GM_GPCR_FC_RX_DIS,
324 [FC_RX] = GM_GPCR_FC_TX_DIS,
329 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
331 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
332 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
334 if (sky2->autoneg == AUTONEG_ENABLE &&
335 !(hw->flags & SKY2_HW_NEWER_PHY)) {
336 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
338 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
340 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
342 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
343 if (hw->chip_id == CHIP_ID_YUKON_EC)
344 /* set downshift counter to 3x and enable downshift */
345 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
347 /* set master & slave downshift counter to 1x */
348 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
350 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
354 if (sky2_is_copper(hw)) {
355 if (!(hw->flags & SKY2_HW_GIGABIT)) {
356 /* enable automatic crossover */
357 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
359 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
360 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
363 /* Enable Class A driver for FE+ A0 */
364 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
365 spec |= PHY_M_FESC_SEL_CL_A;
366 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
369 /* disable energy detect */
370 ctrl &= ~PHY_M_PC_EN_DET_MSK;
372 /* enable automatic crossover */
373 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
375 /* downshift on PHY 88E1112 and 88E1149 is changed */
376 if (sky2->autoneg == AUTONEG_ENABLE
377 && (hw->flags & SKY2_HW_NEWER_PHY)) {
378 /* set downshift counter to 3x and enable downshift */
379 ctrl &= ~PHY_M_PC_DSC_MSK;
380 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
384 /* workaround for deviation #4.88 (CRC errors) */
385 /* disable Automatic Crossover */
387 ctrl &= ~PHY_M_PC_MDIX_MSK;
390 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
392 /* special setup for PHY 88E1112 Fiber */
393 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
394 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
396 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
397 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
398 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
399 ctrl &= ~PHY_M_MAC_MD_MSK;
400 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
401 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
403 if (hw->pmd_type == 'P') {
404 /* select page 1 to access Fiber registers */
405 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
407 /* for SFP-module set SIGDET polarity to low */
408 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
409 ctrl |= PHY_M_FIB_SIGD_POL;
410 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
413 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
421 if (sky2->autoneg == AUTONEG_ENABLE) {
422 if (sky2_is_copper(hw)) {
423 if (sky2->advertising & ADVERTISED_1000baseT_Full)
424 ct1000 |= PHY_M_1000C_AFD;
425 if (sky2->advertising & ADVERTISED_1000baseT_Half)
426 ct1000 |= PHY_M_1000C_AHD;
427 if (sky2->advertising & ADVERTISED_100baseT_Full)
428 adv |= PHY_M_AN_100_FD;
429 if (sky2->advertising & ADVERTISED_100baseT_Half)
430 adv |= PHY_M_AN_100_HD;
431 if (sky2->advertising & ADVERTISED_10baseT_Full)
432 adv |= PHY_M_AN_10_FD;
433 if (sky2->advertising & ADVERTISED_10baseT_Half)
434 adv |= PHY_M_AN_10_HD;
436 adv |= copper_fc_adv[sky2->flow_mode];
437 } else { /* special defines for FIBER (88E1040S only) */
438 if (sky2->advertising & ADVERTISED_1000baseT_Full)
439 adv |= PHY_M_AN_1000X_AFD;
440 if (sky2->advertising & ADVERTISED_1000baseT_Half)
441 adv |= PHY_M_AN_1000X_AHD;
443 adv |= fiber_fc_adv[sky2->flow_mode];
446 /* Restart Auto-negotiation */
447 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
449 /* forced speed/duplex settings */
450 ct1000 = PHY_M_1000C_MSE;
452 /* Disable auto update for duplex flow control and speed */
453 reg |= GM_GPCR_AU_ALL_DIS;
455 switch (sky2->speed) {
457 ctrl |= PHY_CT_SP1000;
458 reg |= GM_GPCR_SPEED_1000;
461 ctrl |= PHY_CT_SP100;
462 reg |= GM_GPCR_SPEED_100;
466 if (sky2->duplex == DUPLEX_FULL) {
467 reg |= GM_GPCR_DUP_FULL;
468 ctrl |= PHY_CT_DUP_MD;
469 } else if (sky2->speed < SPEED_1000)
470 sky2->flow_mode = FC_NONE;
473 reg |= gm_fc_disable[sky2->flow_mode];
475 /* Forward pause packets to GMAC? */
476 if (sky2->flow_mode & FC_RX)
477 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
479 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
482 gma_write16(hw, port, GM_GP_CTRL, reg);
484 if (hw->flags & SKY2_HW_GIGABIT)
485 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
487 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
488 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
490 /* Setup Phy LED's */
491 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
494 switch (hw->chip_id) {
495 case CHIP_ID_YUKON_FE:
496 /* on 88E3082 these bits are at 11..9 (shifted left) */
497 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
499 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
501 /* delete ACT LED control bits */
502 ctrl &= ~PHY_M_FELP_LED1_MSK;
503 /* change ACT LED control to blink mode */
504 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
505 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
508 case CHIP_ID_YUKON_FE_P:
509 /* Enable Link Partner Next Page */
510 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
511 ctrl |= PHY_M_PC_ENA_LIP_NP;
513 /* disable Energy Detect and enable scrambler */
514 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
515 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
517 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
518 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
519 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
520 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
522 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
525 case CHIP_ID_YUKON_XL:
526 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
528 /* select page 3 to access LED control register */
529 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
531 /* set LED Function Control register */
532 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
533 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
534 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
535 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
536 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
538 /* set Polarity Control register */
539 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
540 (PHY_M_POLC_LS1_P_MIX(4) |
541 PHY_M_POLC_IS0_P_MIX(4) |
542 PHY_M_POLC_LOS_CTRL(2) |
543 PHY_M_POLC_INIT_CTRL(2) |
544 PHY_M_POLC_STA1_CTRL(2) |
545 PHY_M_POLC_STA0_CTRL(2)));
547 /* restore page register */
548 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
551 case CHIP_ID_YUKON_EC_U:
552 case CHIP_ID_YUKON_EX:
553 case CHIP_ID_YUKON_SUPR:
554 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
556 /* select page 3 to access LED control register */
557 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
559 /* set LED Function Control register */
560 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
561 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
562 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
563 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
564 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
566 /* set Blink Rate in LED Timer Control Register */
567 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
568 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
569 /* restore page register */
570 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
574 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
575 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
577 /* turn off the Rx LED (LED_RX) */
578 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
581 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
582 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
583 /* apply fixes in PHY AFE */
584 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
586 /* increase differential signal amplitude in 10BASE-T */
587 gm_phy_write(hw, port, 0x18, 0xaa99);
588 gm_phy_write(hw, port, 0x17, 0x2011);
590 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
591 gm_phy_write(hw, port, 0x18, 0xa204);
592 gm_phy_write(hw, port, 0x17, 0x2002);
594 /* set page register to 0 */
595 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
596 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
597 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
598 /* apply workaround for integrated resistors calibration */
599 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
600 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
601 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
602 /* no effect on Yukon-XL */
603 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
605 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
606 /* turn on 100 Mbps LED (LED_LINK100) */
607 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
611 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
615 /* Enable phy interrupt on auto-negotiation complete (or link up) */
616 if (sky2->autoneg == AUTONEG_ENABLE)
617 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
619 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
622 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
623 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
625 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
629 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
630 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
631 reg1 &= ~phy_power[port];
633 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
634 reg1 |= coma_mode[port];
636 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
637 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
638 sky2_pci_read32(hw, PCI_DEV_REG1);
641 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
645 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
646 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
647 reg1 |= phy_power[port];
649 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
650 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
653 /* Force a renegotiation */
654 static void sky2_phy_reinit(struct sky2_port *sky2)
656 spin_lock_bh(&sky2->phy_lock);
657 sky2_phy_init(sky2->hw, sky2->port);
658 spin_unlock_bh(&sky2->phy_lock);
661 /* Put device in state to listen for Wake On Lan */
662 static void sky2_wol_init(struct sky2_port *sky2)
664 struct sky2_hw *hw = sky2->hw;
665 unsigned port = sky2->port;
666 enum flow_control save_mode;
670 /* Bring hardware out of reset */
671 sky2_write16(hw, B0_CTST, CS_RST_CLR);
672 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
674 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
675 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
678 * sky2_reset will re-enable on resume
680 save_mode = sky2->flow_mode;
681 ctrl = sky2->advertising;
683 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
684 sky2->flow_mode = FC_NONE;
686 spin_lock_bh(&sky2->phy_lock);
687 sky2_phy_power_up(hw, port);
688 sky2_phy_init(hw, port);
689 spin_unlock_bh(&sky2->phy_lock);
691 sky2->flow_mode = save_mode;
692 sky2->advertising = ctrl;
694 /* Set GMAC to no flow control and auto update for speed/duplex */
695 gma_write16(hw, port, GM_GP_CTRL,
696 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
697 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
699 /* Set WOL address */
700 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
701 sky2->netdev->dev_addr, ETH_ALEN);
703 /* Turn on appropriate WOL control bits */
704 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
706 if (sky2->wol & WAKE_PHY)
707 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
709 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
711 if (sky2->wol & WAKE_MAGIC)
712 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
714 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
716 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
717 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
719 /* Turn on legacy PCI-Express PME mode */
720 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
721 reg1 |= PCI_Y2_PME_LEGACY;
722 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
725 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
729 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
731 struct net_device *dev = hw->dev[port];
733 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
734 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
735 hw->chip_id == CHIP_ID_YUKON_FE_P ||
736 hw->chip_id == CHIP_ID_YUKON_SUPR) {
737 /* Yukon-Extreme B0 and further Extreme devices */
738 /* enable Store & Forward mode for TX */
740 if (dev->mtu <= ETH_DATA_LEN)
741 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
742 TX_JUMBO_DIS | TX_STFW_ENA);
745 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
746 TX_JUMBO_ENA| TX_STFW_ENA);
748 if (dev->mtu <= ETH_DATA_LEN)
749 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
751 /* set Tx GMAC FIFO Almost Empty Threshold */
752 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
753 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
755 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
757 /* Can't do offload because of lack of store/forward */
758 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
763 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
765 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
769 const u8 *addr = hw->dev[port]->dev_addr;
771 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
772 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
774 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
776 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
777 /* WA DEV_472 -- looks like crossed wires on port 2 */
778 /* clear GMAC 1 Control reset */
779 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
781 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
782 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
783 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
784 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
785 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
788 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
790 /* Enable Transmit FIFO Underrun */
791 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
793 spin_lock_bh(&sky2->phy_lock);
794 sky2_phy_power_up(hw, port);
795 sky2_phy_init(hw, port);
796 spin_unlock_bh(&sky2->phy_lock);
799 reg = gma_read16(hw, port, GM_PHY_ADDR);
800 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
802 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
803 gma_read16(hw, port, i);
804 gma_write16(hw, port, GM_PHY_ADDR, reg);
806 /* transmit control */
807 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
809 /* receive control reg: unicast + multicast + no FCS */
810 gma_write16(hw, port, GM_RX_CTRL,
811 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
813 /* transmit flow control */
814 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
816 /* transmit parameter */
817 gma_write16(hw, port, GM_TX_PARAM,
818 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
819 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
820 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
821 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
823 /* serial mode register */
824 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
825 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
827 if (hw->dev[port]->mtu > ETH_DATA_LEN)
828 reg |= GM_SMOD_JUMBO_ENA;
830 gma_write16(hw, port, GM_SERIAL_MODE, reg);
832 /* virtual address for data */
833 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
835 /* physical address: used for pause frames */
836 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
838 /* ignore counter overflows */
839 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
840 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
841 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
843 /* Configure Rx MAC FIFO */
844 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
845 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
846 if (hw->chip_id == CHIP_ID_YUKON_EX ||
847 hw->chip_id == CHIP_ID_YUKON_FE_P)
848 rx_reg |= GMF_RX_OVER_ON;
850 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
852 if (hw->chip_id == CHIP_ID_YUKON_XL) {
853 /* Hardware errata - clear flush mask */
854 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
856 /* Flush Rx MAC FIFO on any flow control or error */
857 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
860 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
861 reg = RX_GMF_FL_THR_DEF + 1;
862 /* Another magic mystery workaround from sk98lin */
863 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
864 hw->chip_rev == CHIP_REV_YU_FE2_A0)
866 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
868 /* Configure Tx MAC FIFO */
869 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
870 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
872 /* On chips without ram buffer, pause is controled by MAC level */
873 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
874 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
875 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
877 sky2_set_tx_stfwd(hw, port);
880 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
881 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
882 /* disable dynamic watermark */
883 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
884 reg &= ~TX_DYN_WM_ENA;
885 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
889 /* Assign Ram Buffer allocation to queue */
890 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
894 /* convert from K bytes to qwords used for hw register */
897 end = start + space - 1;
899 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
900 sky2_write32(hw, RB_ADDR(q, RB_START), start);
901 sky2_write32(hw, RB_ADDR(q, RB_END), end);
902 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
903 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
905 if (q == Q_R1 || q == Q_R2) {
906 u32 tp = space - space/4;
908 /* On receive queue's set the thresholds
909 * give receiver priority when > 3/4 full
910 * send pause when down to 2K
912 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
913 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
916 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
917 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
919 /* Enable store & forward on Tx queue's because
920 * Tx FIFO is only 1K on Yukon
922 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
925 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
926 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
929 /* Setup Bus Memory Interface */
930 static void sky2_qset(struct sky2_hw *hw, u16 q)
932 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
933 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
934 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
935 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
938 /* Setup prefetch unit registers. This is the interface between
939 * hardware and driver list elements
941 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
944 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
945 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
946 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
947 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
948 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
949 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
951 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
954 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
956 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
958 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
963 static void tx_init(struct sky2_port *sky2)
965 struct sky2_tx_le *le;
967 sky2->tx_prod = sky2->tx_cons = 0;
969 sky2->tx_last_mss = 0;
971 le = get_tx_le(sky2);
973 le->opcode = OP_ADDR64 | HW_OWNER;
976 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
977 struct sky2_tx_le *le)
979 return sky2->tx_ring + (le - sky2->tx_le);
982 /* Update chip's next pointer */
983 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
985 /* Make sure write' to descriptors are complete before we tell hardware */
987 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
989 /* Synchronize I/O on since next processor may write to tail */
994 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
996 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
997 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1002 /* Build description to hardware for one receive segment */
1003 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1004 dma_addr_t map, unsigned len)
1006 struct sky2_rx_le *le;
1008 if (sizeof(dma_addr_t) > sizeof(u32)) {
1009 le = sky2_next_rx(sky2);
1010 le->addr = cpu_to_le32(upper_32_bits(map));
1011 le->opcode = OP_ADDR64 | HW_OWNER;
1014 le = sky2_next_rx(sky2);
1015 le->addr = cpu_to_le32((u32) map);
1016 le->length = cpu_to_le16(len);
1017 le->opcode = op | HW_OWNER;
1020 /* Build description to hardware for one possibly fragmented skb */
1021 static void sky2_rx_submit(struct sky2_port *sky2,
1022 const struct rx_ring_info *re)
1026 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1028 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1029 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1033 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1036 struct sk_buff *skb = re->skb;
1039 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1040 pci_unmap_len_set(re, data_size, size);
1042 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1043 re->frag_addr[i] = pci_map_page(pdev,
1044 skb_shinfo(skb)->frags[i].page,
1045 skb_shinfo(skb)->frags[i].page_offset,
1046 skb_shinfo(skb)->frags[i].size,
1047 PCI_DMA_FROMDEVICE);
1050 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1052 struct sk_buff *skb = re->skb;
1055 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1056 PCI_DMA_FROMDEVICE);
1058 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1059 pci_unmap_page(pdev, re->frag_addr[i],
1060 skb_shinfo(skb)->frags[i].size,
1061 PCI_DMA_FROMDEVICE);
1064 /* Tell chip where to start receive checksum.
1065 * Actually has two checksums, but set both same to avoid possible byte
1068 static void rx_set_checksum(struct sky2_port *sky2)
1070 struct sky2_rx_le *le = sky2_next_rx(sky2);
1072 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1074 le->opcode = OP_TCPSTART | HW_OWNER;
1076 sky2_write32(sky2->hw,
1077 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1078 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1082 * The RX Stop command will not work for Yukon-2 if the BMU does not
1083 * reach the end of packet and since we can't make sure that we have
1084 * incoming data, we must reset the BMU while it is not doing a DMA
1085 * transfer. Since it is possible that the RX path is still active,
1086 * the RX RAM buffer will be stopped first, so any possible incoming
1087 * data will not trigger a DMA. After the RAM buffer is stopped, the
1088 * BMU is polled until any DMA in progress is ended and only then it
1091 static void sky2_rx_stop(struct sky2_port *sky2)
1093 struct sky2_hw *hw = sky2->hw;
1094 unsigned rxq = rxqaddr[sky2->port];
1097 /* disable the RAM Buffer receive queue */
1098 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1100 for (i = 0; i < 0xffff; i++)
1101 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1102 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1105 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1106 sky2->netdev->name);
1108 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1110 /* reset the Rx prefetch unit */
1111 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1115 /* Clean out receive buffer area, assumes receiver hardware stopped */
1116 static void sky2_rx_clean(struct sky2_port *sky2)
1120 memset(sky2->rx_le, 0, RX_LE_BYTES);
1121 for (i = 0; i < sky2->rx_pending; i++) {
1122 struct rx_ring_info *re = sky2->rx_ring + i;
1125 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1132 /* Basic MII support */
1133 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1135 struct mii_ioctl_data *data = if_mii(ifr);
1136 struct sky2_port *sky2 = netdev_priv(dev);
1137 struct sky2_hw *hw = sky2->hw;
1138 int err = -EOPNOTSUPP;
1140 if (!netif_running(dev))
1141 return -ENODEV; /* Phy still in reset */
1145 data->phy_id = PHY_ADDR_MARV;
1151 spin_lock_bh(&sky2->phy_lock);
1152 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1153 spin_unlock_bh(&sky2->phy_lock);
1155 data->val_out = val;
1160 if (!capable(CAP_NET_ADMIN))
1163 spin_lock_bh(&sky2->phy_lock);
1164 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1166 spin_unlock_bh(&sky2->phy_lock);
1172 #ifdef SKY2_VLAN_TAG_USED
1173 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1176 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1178 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1181 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1183 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1188 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1190 struct sky2_port *sky2 = netdev_priv(dev);
1191 struct sky2_hw *hw = sky2->hw;
1192 u16 port = sky2->port;
1194 netif_tx_lock_bh(dev);
1195 napi_disable(&hw->napi);
1198 sky2_set_vlan_mode(hw, port, grp != NULL);
1200 sky2_read32(hw, B0_Y2_SP_LISR);
1201 napi_enable(&hw->napi);
1202 netif_tx_unlock_bh(dev);
1207 * Allocate an skb for receiving. If the MTU is large enough
1208 * make the skb non-linear with a fragment list of pages.
1210 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1212 struct sk_buff *skb;
1215 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1216 unsigned char *start;
1218 * Workaround for a bug in FIFO that cause hang
1219 * if the FIFO if the receive buffer is not 64 byte aligned.
1220 * The buffer returned from netdev_alloc_skb is
1221 * aligned except if slab debugging is enabled.
1223 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1226 start = PTR_ALIGN(skb->data, 8);
1227 skb_reserve(skb, start - skb->data);
1229 skb = netdev_alloc_skb(sky2->netdev,
1230 sky2->rx_data_size + NET_IP_ALIGN);
1233 skb_reserve(skb, NET_IP_ALIGN);
1236 for (i = 0; i < sky2->rx_nfrags; i++) {
1237 struct page *page = alloc_page(GFP_ATOMIC);
1241 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1251 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1253 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1257 * Allocate and setup receiver buffer pool.
1258 * Normal case this ends up creating one list element for skb
1259 * in the receive ring. Worst case if using large MTU and each
1260 * allocation falls on a different 64 bit region, that results
1261 * in 6 list elements per ring entry.
1262 * One element is used for checksum enable/disable, and one
1263 * extra to avoid wrap.
1265 static int sky2_rx_start(struct sky2_port *sky2)
1267 struct sky2_hw *hw = sky2->hw;
1268 struct rx_ring_info *re;
1269 unsigned rxq = rxqaddr[sky2->port];
1270 unsigned i, size, thresh;
1272 sky2->rx_put = sky2->rx_next = 0;
1275 /* On PCI express lowering the watermark gives better performance */
1276 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1277 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1279 /* These chips have no ram buffer?
1280 * MAC Rx RAM Read is controlled by hardware */
1281 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1282 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1283 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1284 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1286 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1288 if (!(hw->flags & SKY2_HW_NEW_LE))
1289 rx_set_checksum(sky2);
1291 /* Space needed for frame data + headers rounded up */
1292 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1294 /* Stopping point for hardware truncation */
1295 thresh = (size - 8) / sizeof(u32);
1297 sky2->rx_nfrags = size >> PAGE_SHIFT;
1298 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1300 /* Compute residue after pages */
1301 size -= sky2->rx_nfrags << PAGE_SHIFT;
1303 /* Optimize to handle small packets and headers */
1304 if (size < copybreak)
1306 if (size < ETH_HLEN)
1309 sky2->rx_data_size = size;
1312 for (i = 0; i < sky2->rx_pending; i++) {
1313 re = sky2->rx_ring + i;
1315 re->skb = sky2_rx_alloc(sky2);
1319 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1320 sky2_rx_submit(sky2, re);
1324 * The receiver hangs if it receives frames larger than the
1325 * packet buffer. As a workaround, truncate oversize frames, but
1326 * the register is limited to 9 bits, so if you do frames > 2052
1327 * you better get the MTU right!
1330 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1332 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1333 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1336 /* Tell chip about available buffers */
1337 sky2_rx_update(sky2, rxq);
1340 sky2_rx_clean(sky2);
1344 /* Bring up network interface. */
1345 static int sky2_up(struct net_device *dev)
1347 struct sky2_port *sky2 = netdev_priv(dev);
1348 struct sky2_hw *hw = sky2->hw;
1349 unsigned port = sky2->port;
1351 int cap, err = -ENOMEM;
1352 struct net_device *otherdev = hw->dev[sky2->port^1];
1355 * On dual port PCI-X card, there is an problem where status
1356 * can be received out of order due to split transactions
1358 if (otherdev && netif_running(otherdev) &&
1359 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1362 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1363 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1364 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1368 if (netif_msg_ifup(sky2))
1369 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1371 netif_carrier_off(dev);
1373 /* must be power of 2 */
1374 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1376 sizeof(struct sky2_tx_le),
1381 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1388 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1392 memset(sky2->rx_le, 0, RX_LE_BYTES);
1394 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1399 sky2_mac_init(hw, port);
1401 /* Register is number of 4K blocks on internal RAM buffer. */
1402 ramsize = sky2_read8(hw, B2_E_0) * 4;
1406 hw->flags |= SKY2_HW_RAM_BUFFER;
1407 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1409 rxspace = ramsize / 2;
1411 rxspace = 8 + (2*(ramsize - 16))/3;
1413 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1414 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1416 /* Make sure SyncQ is disabled */
1417 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1421 sky2_qset(hw, txqaddr[port]);
1423 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1424 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1425 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1427 /* Set almost empty threshold */
1428 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1429 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1430 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1432 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1435 #ifdef SKY2_VLAN_TAG_USED
1436 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1439 err = sky2_rx_start(sky2);
1443 /* Enable interrupts from phy/mac for port */
1444 imask = sky2_read32(hw, B0_IMSK);
1445 imask |= portirq_msk[port];
1446 sky2_write32(hw, B0_IMSK, imask);
1448 sky2_set_multicast(dev);
1453 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1454 sky2->rx_le, sky2->rx_le_map);
1458 pci_free_consistent(hw->pdev,
1459 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1460 sky2->tx_le, sky2->tx_le_map);
1463 kfree(sky2->tx_ring);
1464 kfree(sky2->rx_ring);
1466 sky2->tx_ring = NULL;
1467 sky2->rx_ring = NULL;
1471 /* Modular subtraction in ring */
1472 static inline int tx_dist(unsigned tail, unsigned head)
1474 return (head - tail) & (TX_RING_SIZE - 1);
1477 /* Number of list elements available for next tx */
1478 static inline int tx_avail(const struct sky2_port *sky2)
1480 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1483 /* Estimate of number of transmit list elements required */
1484 static unsigned tx_le_req(const struct sk_buff *skb)
1488 count = sizeof(dma_addr_t) / sizeof(u32);
1489 count += skb_shinfo(skb)->nr_frags * count;
1491 if (skb_is_gso(skb))
1494 if (skb->ip_summed == CHECKSUM_PARTIAL)
1501 * Put one packet in ring for transmit.
1502 * A single packet can generate multiple list elements, and
1503 * the number of ring elements will probably be less than the number
1504 * of list elements used.
1506 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1508 struct sky2_port *sky2 = netdev_priv(dev);
1509 struct sky2_hw *hw = sky2->hw;
1510 struct sky2_tx_le *le = NULL;
1511 struct tx_ring_info *re;
1517 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1518 return NETDEV_TX_BUSY;
1520 if (unlikely(netif_msg_tx_queued(sky2)))
1521 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1522 dev->name, sky2->tx_prod, skb->len);
1524 len = skb_headlen(skb);
1525 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1527 /* Send high bits if needed */
1528 if (sizeof(dma_addr_t) > sizeof(u32)) {
1529 le = get_tx_le(sky2);
1530 le->addr = cpu_to_le32(upper_32_bits(mapping));
1531 le->opcode = OP_ADDR64 | HW_OWNER;
1534 /* Check for TCP Segmentation Offload */
1535 mss = skb_shinfo(skb)->gso_size;
1538 if (!(hw->flags & SKY2_HW_NEW_LE))
1539 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1541 if (mss != sky2->tx_last_mss) {
1542 le = get_tx_le(sky2);
1543 le->addr = cpu_to_le32(mss);
1545 if (hw->flags & SKY2_HW_NEW_LE)
1546 le->opcode = OP_MSS | HW_OWNER;
1548 le->opcode = OP_LRGLEN | HW_OWNER;
1549 sky2->tx_last_mss = mss;
1554 #ifdef SKY2_VLAN_TAG_USED
1555 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1556 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1558 le = get_tx_le(sky2);
1560 le->opcode = OP_VLAN|HW_OWNER;
1562 le->opcode |= OP_VLAN;
1563 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1568 /* Handle TCP checksum offload */
1569 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1570 /* On Yukon EX (some versions) encoding change. */
1571 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1572 ctrl |= CALSUM; /* auto checksum */
1574 const unsigned offset = skb_transport_offset(skb);
1577 tcpsum = offset << 16; /* sum start */
1578 tcpsum |= offset + skb->csum_offset; /* sum write */
1580 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1581 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1584 if (tcpsum != sky2->tx_tcpsum) {
1585 sky2->tx_tcpsum = tcpsum;
1587 le = get_tx_le(sky2);
1588 le->addr = cpu_to_le32(tcpsum);
1589 le->length = 0; /* initial checksum value */
1590 le->ctrl = 1; /* one packet */
1591 le->opcode = OP_TCPLISW | HW_OWNER;
1596 le = get_tx_le(sky2);
1597 le->addr = cpu_to_le32((u32) mapping);
1598 le->length = cpu_to_le16(len);
1600 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1602 re = tx_le_re(sky2, le);
1604 pci_unmap_addr_set(re, mapaddr, mapping);
1605 pci_unmap_len_set(re, maplen, len);
1607 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1608 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1610 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1611 frag->size, PCI_DMA_TODEVICE);
1613 if (sizeof(dma_addr_t) > sizeof(u32)) {
1614 le = get_tx_le(sky2);
1615 le->addr = cpu_to_le32(upper_32_bits(mapping));
1617 le->opcode = OP_ADDR64 | HW_OWNER;
1620 le = get_tx_le(sky2);
1621 le->addr = cpu_to_le32((u32) mapping);
1622 le->length = cpu_to_le16(frag->size);
1624 le->opcode = OP_BUFFER | HW_OWNER;
1626 re = tx_le_re(sky2, le);
1628 pci_unmap_addr_set(re, mapaddr, mapping);
1629 pci_unmap_len_set(re, maplen, frag->size);
1634 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1635 netif_stop_queue(dev);
1637 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1639 dev->trans_start = jiffies;
1640 return NETDEV_TX_OK;
1644 * Free ring elements from starting at tx_cons until "done"
1646 * NB: the hardware will tell us about partial completion of multi-part
1647 * buffers so make sure not to free skb to early.
1649 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1651 struct net_device *dev = sky2->netdev;
1652 struct pci_dev *pdev = sky2->hw->pdev;
1655 BUG_ON(done >= TX_RING_SIZE);
1657 for (idx = sky2->tx_cons; idx != done;
1658 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1659 struct sky2_tx_le *le = sky2->tx_le + idx;
1660 struct tx_ring_info *re = sky2->tx_ring + idx;
1662 switch(le->opcode & ~HW_OWNER) {
1665 pci_unmap_single(pdev,
1666 pci_unmap_addr(re, mapaddr),
1667 pci_unmap_len(re, maplen),
1671 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1672 pci_unmap_len(re, maplen),
1677 if (le->ctrl & EOP) {
1678 if (unlikely(netif_msg_tx_done(sky2)))
1679 printk(KERN_DEBUG "%s: tx done %u\n",
1682 dev->stats.tx_packets++;
1683 dev->stats.tx_bytes += re->skb->len;
1685 dev_kfree_skb_any(re->skb);
1686 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1690 sky2->tx_cons = idx;
1693 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1694 netif_wake_queue(dev);
1697 /* Cleanup all untransmitted buffers, assume transmitter not running */
1698 static void sky2_tx_clean(struct net_device *dev)
1700 struct sky2_port *sky2 = netdev_priv(dev);
1702 netif_tx_lock_bh(dev);
1703 sky2_tx_complete(sky2, sky2->tx_prod);
1704 netif_tx_unlock_bh(dev);
1707 /* Network shutdown */
1708 static int sky2_down(struct net_device *dev)
1710 struct sky2_port *sky2 = netdev_priv(dev);
1711 struct sky2_hw *hw = sky2->hw;
1712 unsigned port = sky2->port;
1716 /* Never really got started! */
1720 if (netif_msg_ifdown(sky2))
1721 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1723 /* Stop more packets from being queued */
1724 netif_stop_queue(dev);
1726 /* Disable port IRQ */
1727 imask = sky2_read32(hw, B0_IMSK);
1728 imask &= ~portirq_msk[port];
1729 sky2_write32(hw, B0_IMSK, imask);
1731 synchronize_irq(hw->pdev->irq);
1733 sky2_gmac_reset(hw, port);
1735 /* Stop transmitter */
1736 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1737 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1739 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1740 RB_RST_SET | RB_DIS_OP_MD);
1742 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1743 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1744 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1746 /* Make sure no packets are pending */
1747 napi_synchronize(&hw->napi);
1749 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1751 /* Workaround shared GMAC reset */
1752 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1753 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1754 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1756 /* Disable Force Sync bit and Enable Alloc bit */
1757 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1758 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1760 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1761 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1762 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1764 /* Reset the PCI FIFO of the async Tx queue */
1765 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1766 BMU_RST_SET | BMU_FIFO_RST);
1768 /* Reset the Tx prefetch units */
1769 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1772 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1776 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1777 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1779 sky2_phy_power_down(hw, port);
1781 netif_carrier_off(dev);
1783 /* turn off LED's */
1784 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1787 sky2_rx_clean(sky2);
1789 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1790 sky2->rx_le, sky2->rx_le_map);
1791 kfree(sky2->rx_ring);
1793 pci_free_consistent(hw->pdev,
1794 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1795 sky2->tx_le, sky2->tx_le_map);
1796 kfree(sky2->tx_ring);
1801 sky2->rx_ring = NULL;
1802 sky2->tx_ring = NULL;
1807 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1809 if (hw->flags & SKY2_HW_FIBRE_PHY)
1812 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1813 if (aux & PHY_M_PS_SPEED_100)
1819 switch (aux & PHY_M_PS_SPEED_MSK) {
1820 case PHY_M_PS_SPEED_1000:
1822 case PHY_M_PS_SPEED_100:
1829 static void sky2_link_up(struct sky2_port *sky2)
1831 struct sky2_hw *hw = sky2->hw;
1832 unsigned port = sky2->port;
1834 static const char *fc_name[] = {
1842 reg = gma_read16(hw, port, GM_GP_CTRL);
1843 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1844 gma_write16(hw, port, GM_GP_CTRL, reg);
1846 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1848 netif_carrier_on(sky2->netdev);
1850 mod_timer(&hw->watchdog_timer, jiffies + 1);
1852 /* Turn on link LED */
1853 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1854 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1856 if (netif_msg_link(sky2))
1857 printk(KERN_INFO PFX
1858 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1859 sky2->netdev->name, sky2->speed,
1860 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1861 fc_name[sky2->flow_status]);
1864 static void sky2_link_down(struct sky2_port *sky2)
1866 struct sky2_hw *hw = sky2->hw;
1867 unsigned port = sky2->port;
1870 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1872 reg = gma_read16(hw, port, GM_GP_CTRL);
1873 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1874 gma_write16(hw, port, GM_GP_CTRL, reg);
1876 netif_carrier_off(sky2->netdev);
1878 /* Turn on link LED */
1879 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1881 if (netif_msg_link(sky2))
1882 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1884 sky2_phy_init(hw, port);
1887 static enum flow_control sky2_flow(int rx, int tx)
1890 return tx ? FC_BOTH : FC_RX;
1892 return tx ? FC_TX : FC_NONE;
1895 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1897 struct sky2_hw *hw = sky2->hw;
1898 unsigned port = sky2->port;
1901 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1902 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1903 if (lpa & PHY_M_AN_RF) {
1904 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1908 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1909 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1910 sky2->netdev->name);
1914 sky2->speed = sky2_phy_speed(hw, aux);
1915 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1917 /* Since the pause result bits seem to in different positions on
1918 * different chips. look at registers.
1920 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1921 /* Shift for bits in fiber PHY */
1922 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1923 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1925 if (advert & ADVERTISE_1000XPAUSE)
1926 advert |= ADVERTISE_PAUSE_CAP;
1927 if (advert & ADVERTISE_1000XPSE_ASYM)
1928 advert |= ADVERTISE_PAUSE_ASYM;
1929 if (lpa & LPA_1000XPAUSE)
1930 lpa |= LPA_PAUSE_CAP;
1931 if (lpa & LPA_1000XPAUSE_ASYM)
1932 lpa |= LPA_PAUSE_ASYM;
1935 sky2->flow_status = FC_NONE;
1936 if (advert & ADVERTISE_PAUSE_CAP) {
1937 if (lpa & LPA_PAUSE_CAP)
1938 sky2->flow_status = FC_BOTH;
1939 else if (advert & ADVERTISE_PAUSE_ASYM)
1940 sky2->flow_status = FC_RX;
1941 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1942 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1943 sky2->flow_status = FC_TX;
1946 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1947 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1948 sky2->flow_status = FC_NONE;
1950 if (sky2->flow_status & FC_TX)
1951 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1953 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1958 /* Interrupt from PHY */
1959 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1961 struct net_device *dev = hw->dev[port];
1962 struct sky2_port *sky2 = netdev_priv(dev);
1963 u16 istatus, phystat;
1965 if (!netif_running(dev))
1968 spin_lock(&sky2->phy_lock);
1969 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1970 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1972 if (netif_msg_intr(sky2))
1973 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1974 sky2->netdev->name, istatus, phystat);
1976 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1977 if (sky2_autoneg_done(sky2, phystat) == 0)
1982 if (istatus & PHY_M_IS_LSP_CHANGE)
1983 sky2->speed = sky2_phy_speed(hw, phystat);
1985 if (istatus & PHY_M_IS_DUP_CHANGE)
1987 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1989 if (istatus & PHY_M_IS_LST_CHANGE) {
1990 if (phystat & PHY_M_PS_LINK_UP)
1993 sky2_link_down(sky2);
1996 spin_unlock(&sky2->phy_lock);
1999 /* Transmit timeout is only called if we are running, carrier is up
2000 * and tx queue is full (stopped).
2002 static void sky2_tx_timeout(struct net_device *dev)
2004 struct sky2_port *sky2 = netdev_priv(dev);
2005 struct sky2_hw *hw = sky2->hw;
2007 if (netif_msg_timer(sky2))
2008 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2010 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2011 dev->name, sky2->tx_cons, sky2->tx_prod,
2012 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2013 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2015 /* can't restart safely under softirq */
2016 schedule_work(&hw->restart_work);
2019 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2021 struct sky2_port *sky2 = netdev_priv(dev);
2022 struct sky2_hw *hw = sky2->hw;
2023 unsigned port = sky2->port;
2028 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2031 if (new_mtu > ETH_DATA_LEN &&
2032 (hw->chip_id == CHIP_ID_YUKON_FE ||
2033 hw->chip_id == CHIP_ID_YUKON_FE_P))
2036 if (!netif_running(dev)) {
2041 imask = sky2_read32(hw, B0_IMSK);
2042 sky2_write32(hw, B0_IMSK, 0);
2044 dev->trans_start = jiffies; /* prevent tx timeout */
2045 netif_stop_queue(dev);
2046 napi_disable(&hw->napi);
2048 synchronize_irq(hw->pdev->irq);
2050 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2051 sky2_set_tx_stfwd(hw, port);
2053 ctl = gma_read16(hw, port, GM_GP_CTRL);
2054 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2056 sky2_rx_clean(sky2);
2060 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2061 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2063 if (dev->mtu > ETH_DATA_LEN)
2064 mode |= GM_SMOD_JUMBO_ENA;
2066 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2068 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2070 err = sky2_rx_start(sky2);
2071 sky2_write32(hw, B0_IMSK, imask);
2073 sky2_read32(hw, B0_Y2_SP_LISR);
2074 napi_enable(&hw->napi);
2079 gma_write16(hw, port, GM_GP_CTRL, ctl);
2081 netif_wake_queue(dev);
2087 /* For small just reuse existing skb for next receive */
2088 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2089 const struct rx_ring_info *re,
2092 struct sk_buff *skb;
2094 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2096 skb_reserve(skb, 2);
2097 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2098 length, PCI_DMA_FROMDEVICE);
2099 skb_copy_from_linear_data(re->skb, skb->data, length);
2100 skb->ip_summed = re->skb->ip_summed;
2101 skb->csum = re->skb->csum;
2102 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2103 length, PCI_DMA_FROMDEVICE);
2104 re->skb->ip_summed = CHECKSUM_NONE;
2105 skb_put(skb, length);
2110 /* Adjust length of skb with fragments to match received data */
2111 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2112 unsigned int length)
2117 /* put header into skb */
2118 size = min(length, hdr_space);
2123 num_frags = skb_shinfo(skb)->nr_frags;
2124 for (i = 0; i < num_frags; i++) {
2125 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2128 /* don't need this page */
2129 __free_page(frag->page);
2130 --skb_shinfo(skb)->nr_frags;
2132 size = min(length, (unsigned) PAGE_SIZE);
2135 skb->data_len += size;
2136 skb->truesize += size;
2143 /* Normal packet - take skb from ring element and put in a new one */
2144 static struct sk_buff *receive_new(struct sky2_port *sky2,
2145 struct rx_ring_info *re,
2146 unsigned int length)
2148 struct sk_buff *skb, *nskb;
2149 unsigned hdr_space = sky2->rx_data_size;
2151 /* Don't be tricky about reusing pages (yet) */
2152 nskb = sky2_rx_alloc(sky2);
2153 if (unlikely(!nskb))
2157 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2159 prefetch(skb->data);
2161 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2163 if (skb_shinfo(skb)->nr_frags)
2164 skb_put_frags(skb, hdr_space, length);
2166 skb_put(skb, length);
2171 * Receive one packet.
2172 * For larger packets, get new buffer.
2174 static struct sk_buff *sky2_receive(struct net_device *dev,
2175 u16 length, u32 status)
2177 struct sky2_port *sky2 = netdev_priv(dev);
2178 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2179 struct sk_buff *skb = NULL;
2180 u16 count = (status & GMR_FS_LEN) >> 16;
2182 #ifdef SKY2_VLAN_TAG_USED
2183 /* Account for vlan tag */
2184 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2188 if (unlikely(netif_msg_rx_status(sky2)))
2189 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2190 dev->name, sky2->rx_next, status, length);
2192 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2193 prefetch(sky2->rx_ring + sky2->rx_next);
2195 /* This chip has hardware problems that generates bogus status.
2196 * So do only marginal checking and expect higher level protocols
2197 * to handle crap frames.
2199 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2200 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2204 if (status & GMR_FS_ANY_ERR)
2207 if (!(status & GMR_FS_RX_OK))
2210 /* if length reported by DMA does not match PHY, packet was truncated */
2211 if (length != count)
2215 if (length < copybreak)
2216 skb = receive_copy(sky2, re, length);
2218 skb = receive_new(sky2, re, length);
2220 sky2_rx_submit(sky2, re);
2225 /* Truncation of overlength packets
2226 causes PHY length to not match MAC length */
2227 ++dev->stats.rx_length_errors;
2228 if (netif_msg_rx_err(sky2) && net_ratelimit())
2229 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2230 dev->name, status, length);
2234 ++dev->stats.rx_errors;
2235 if (status & GMR_FS_RX_FF_OV) {
2236 dev->stats.rx_over_errors++;
2240 if (netif_msg_rx_err(sky2) && net_ratelimit())
2241 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2242 dev->name, status, length);
2244 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2245 dev->stats.rx_length_errors++;
2246 if (status & GMR_FS_FRAGMENT)
2247 dev->stats.rx_frame_errors++;
2248 if (status & GMR_FS_CRC_ERR)
2249 dev->stats.rx_crc_errors++;
2254 /* Transmit complete */
2255 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2257 struct sky2_port *sky2 = netdev_priv(dev);
2259 if (netif_running(dev)) {
2261 sky2_tx_complete(sky2, last);
2262 netif_tx_unlock(dev);
2266 /* Process status response ring */
2267 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2270 unsigned rx[2] = { 0, 0 };
2274 struct sky2_port *sky2;
2275 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2277 struct net_device *dev;
2278 struct sk_buff *skb;
2281 u8 opcode = le->opcode;
2283 if (!(opcode & HW_OWNER))
2286 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2288 port = le->css & CSS_LINK_BIT;
2289 dev = hw->dev[port];
2290 sky2 = netdev_priv(dev);
2291 length = le16_to_cpu(le->length);
2292 status = le32_to_cpu(le->status);
2295 switch (opcode & ~HW_OWNER) {
2298 skb = sky2_receive(dev, length, status);
2299 if (unlikely(!skb)) {
2300 dev->stats.rx_dropped++;
2304 /* This chip reports checksum status differently */
2305 if (hw->flags & SKY2_HW_NEW_LE) {
2306 if (sky2->rx_csum &&
2307 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2308 (le->css & CSS_TCPUDPCSOK))
2309 skb->ip_summed = CHECKSUM_UNNECESSARY;
2311 skb->ip_summed = CHECKSUM_NONE;
2314 skb->protocol = eth_type_trans(skb, dev);
2315 dev->stats.rx_packets++;
2316 dev->stats.rx_bytes += skb->len;
2317 dev->last_rx = jiffies;
2319 #ifdef SKY2_VLAN_TAG_USED
2320 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2321 vlan_hwaccel_receive_skb(skb,
2323 be16_to_cpu(sky2->rx_tag));
2326 netif_receive_skb(skb);
2328 /* Stop after net poll weight */
2329 if (++work_done >= to_do)
2333 #ifdef SKY2_VLAN_TAG_USED
2335 sky2->rx_tag = length;
2339 sky2->rx_tag = length;
2346 /* If this happens then driver assuming wrong format */
2347 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2348 if (net_ratelimit())
2349 printk(KERN_NOTICE "%s: unexpected"
2350 " checksum status\n",
2355 /* Both checksum counters are programmed to start at
2356 * the same offset, so unless there is a problem they
2357 * should match. This failure is an early indication that
2358 * hardware receive checksumming won't work.
2360 if (likely(status >> 16 == (status & 0xffff))) {
2361 skb = sky2->rx_ring[sky2->rx_next].skb;
2362 skb->ip_summed = CHECKSUM_COMPLETE;
2363 skb->csum = status & 0xffff;
2365 printk(KERN_NOTICE PFX "%s: hardware receive "
2366 "checksum problem (status = %#x)\n",
2369 sky2_write32(sky2->hw,
2370 Q_ADDR(rxqaddr[port], Q_CSR),
2376 /* TX index reports status for both ports */
2377 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2378 sky2_tx_done(hw->dev[0], status & 0xfff);
2380 sky2_tx_done(hw->dev[1],
2381 ((status >> 24) & 0xff)
2382 | (u16)(length & 0xf) << 8);
2386 if (net_ratelimit())
2387 printk(KERN_WARNING PFX
2388 "unknown status opcode 0x%x\n", opcode);
2390 } while (hw->st_idx != idx);
2392 /* Fully processed status ring so clear irq */
2393 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2397 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2400 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2405 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2407 struct net_device *dev = hw->dev[port];
2409 if (net_ratelimit())
2410 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2413 if (status & Y2_IS_PAR_RD1) {
2414 if (net_ratelimit())
2415 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2418 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2421 if (status & Y2_IS_PAR_WR1) {
2422 if (net_ratelimit())
2423 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2426 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2429 if (status & Y2_IS_PAR_MAC1) {
2430 if (net_ratelimit())
2431 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2432 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2435 if (status & Y2_IS_PAR_RX1) {
2436 if (net_ratelimit())
2437 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2438 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2441 if (status & Y2_IS_TCP_TXA1) {
2442 if (net_ratelimit())
2443 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2445 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2449 static void sky2_hw_intr(struct sky2_hw *hw)
2451 struct pci_dev *pdev = hw->pdev;
2452 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2453 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2457 if (status & Y2_IS_TIST_OV)
2458 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2460 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2463 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2464 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2465 if (net_ratelimit())
2466 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2469 sky2_pci_write16(hw, PCI_STATUS,
2470 pci_err | PCI_STATUS_ERROR_BITS);
2471 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2474 if (status & Y2_IS_PCI_EXP) {
2475 /* PCI-Express uncorrectable Error occurred */
2478 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2479 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2480 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2482 if (net_ratelimit())
2483 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2485 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2486 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2489 if (status & Y2_HWE_L1_MASK)
2490 sky2_hw_error(hw, 0, status);
2492 if (status & Y2_HWE_L1_MASK)
2493 sky2_hw_error(hw, 1, status);
2496 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2498 struct net_device *dev = hw->dev[port];
2499 struct sky2_port *sky2 = netdev_priv(dev);
2500 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2502 if (netif_msg_intr(sky2))
2503 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2506 if (status & GM_IS_RX_CO_OV)
2507 gma_read16(hw, port, GM_RX_IRQ_SRC);
2509 if (status & GM_IS_TX_CO_OV)
2510 gma_read16(hw, port, GM_TX_IRQ_SRC);
2512 if (status & GM_IS_RX_FF_OR) {
2513 ++dev->stats.rx_fifo_errors;
2514 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2517 if (status & GM_IS_TX_FF_UR) {
2518 ++dev->stats.tx_fifo_errors;
2519 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2523 /* This should never happen it is a bug. */
2524 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2525 u16 q, unsigned ring_size)
2527 struct net_device *dev = hw->dev[port];
2528 struct sky2_port *sky2 = netdev_priv(dev);
2530 const u64 *le = (q == Q_R1 || q == Q_R2)
2531 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2533 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2534 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2535 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2536 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2538 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2541 static int sky2_rx_hung(struct net_device *dev)
2543 struct sky2_port *sky2 = netdev_priv(dev);
2544 struct sky2_hw *hw = sky2->hw;
2545 unsigned port = sky2->port;
2546 unsigned rxq = rxqaddr[port];
2547 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2548 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2549 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2550 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2552 /* If idle and MAC or PCI is stuck */
2553 if (sky2->check.last == dev->last_rx &&
2554 ((mac_rp == sky2->check.mac_rp &&
2555 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2556 /* Check if the PCI RX hang */
2557 (fifo_rp == sky2->check.fifo_rp &&
2558 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2559 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2560 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2561 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2564 sky2->check.last = dev->last_rx;
2565 sky2->check.mac_rp = mac_rp;
2566 sky2->check.mac_lev = mac_lev;
2567 sky2->check.fifo_rp = fifo_rp;
2568 sky2->check.fifo_lev = fifo_lev;
2573 static void sky2_watchdog(unsigned long arg)
2575 struct sky2_hw *hw = (struct sky2_hw *) arg;
2577 /* Check for lost IRQ once a second */
2578 if (sky2_read32(hw, B0_ISRC)) {
2579 napi_schedule(&hw->napi);
2583 for (i = 0; i < hw->ports; i++) {
2584 struct net_device *dev = hw->dev[i];
2585 if (!netif_running(dev))
2589 /* For chips with Rx FIFO, check if stuck */
2590 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2591 sky2_rx_hung(dev)) {
2592 pr_info(PFX "%s: receiver hang detected\n",
2594 schedule_work(&hw->restart_work);
2603 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2606 /* Hardware/software error handling */
2607 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2609 if (net_ratelimit())
2610 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2612 if (status & Y2_IS_HW_ERR)
2615 if (status & Y2_IS_IRQ_MAC1)
2616 sky2_mac_intr(hw, 0);
2618 if (status & Y2_IS_IRQ_MAC2)
2619 sky2_mac_intr(hw, 1);
2621 if (status & Y2_IS_CHK_RX1)
2622 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2624 if (status & Y2_IS_CHK_RX2)
2625 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2627 if (status & Y2_IS_CHK_TXA1)
2628 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2630 if (status & Y2_IS_CHK_TXA2)
2631 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2634 static int sky2_poll(struct napi_struct *napi, int work_limit)
2636 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2637 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2641 if (unlikely(status & Y2_IS_ERROR))
2642 sky2_err_intr(hw, status);
2644 if (status & Y2_IS_IRQ_PHY1)
2645 sky2_phy_intr(hw, 0);
2647 if (status & Y2_IS_IRQ_PHY2)
2648 sky2_phy_intr(hw, 1);
2650 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2651 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2653 if (work_done >= work_limit)
2657 /* Bug/Errata workaround?
2658 * Need to kick the TX irq moderation timer.
2660 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2661 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2662 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2664 napi_complete(napi);
2665 sky2_read32(hw, B0_Y2_SP_LISR);
2671 static irqreturn_t sky2_intr(int irq, void *dev_id)
2673 struct sky2_hw *hw = dev_id;
2676 /* Reading this mask interrupts as side effect */
2677 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2678 if (status == 0 || status == ~0)
2681 prefetch(&hw->st_le[hw->st_idx]);
2683 napi_schedule(&hw->napi);
2688 #ifdef CONFIG_NET_POLL_CONTROLLER
2689 static void sky2_netpoll(struct net_device *dev)
2691 struct sky2_port *sky2 = netdev_priv(dev);
2693 napi_schedule(&sky2->hw->napi);
2697 /* Chip internal frequency for clock calculations */
2698 static u32 sky2_mhz(const struct sky2_hw *hw)
2700 switch (hw->chip_id) {
2701 case CHIP_ID_YUKON_EC:
2702 case CHIP_ID_YUKON_EC_U:
2703 case CHIP_ID_YUKON_EX:
2704 case CHIP_ID_YUKON_SUPR:
2707 case CHIP_ID_YUKON_FE:
2710 case CHIP_ID_YUKON_FE_P:
2713 case CHIP_ID_YUKON_XL:
2721 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2723 return sky2_mhz(hw) * us;
2726 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2728 return clk / sky2_mhz(hw);
2732 static int __devinit sky2_init(struct sky2_hw *hw)
2736 /* Enable all clocks and check for bad PCI access */
2737 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2739 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2741 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2742 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2744 switch(hw->chip_id) {
2745 case CHIP_ID_YUKON_XL:
2746 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2749 case CHIP_ID_YUKON_EC_U:
2750 hw->flags = SKY2_HW_GIGABIT
2752 | SKY2_HW_ADV_POWER_CTL;
2755 case CHIP_ID_YUKON_EX:
2756 hw->flags = SKY2_HW_GIGABIT
2759 | SKY2_HW_ADV_POWER_CTL;
2761 /* New transmit checksum */
2762 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2763 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2766 case CHIP_ID_YUKON_EC:
2767 /* This rev is really old, and requires untested workarounds */
2768 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2769 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2772 hw->flags = SKY2_HW_GIGABIT;
2775 case CHIP_ID_YUKON_FE:
2778 case CHIP_ID_YUKON_FE_P:
2779 hw->flags = SKY2_HW_NEWER_PHY
2781 | SKY2_HW_AUTO_TX_SUM
2782 | SKY2_HW_ADV_POWER_CTL;
2785 case CHIP_ID_YUKON_SUPR:
2786 hw->flags = SKY2_HW_GIGABIT
2789 | SKY2_HW_AUTO_TX_SUM
2790 | SKY2_HW_ADV_POWER_CTL;
2794 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2799 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2800 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2801 hw->flags |= SKY2_HW_FIBRE_PHY;
2805 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2806 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2807 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2814 static void sky2_reset(struct sky2_hw *hw)
2816 struct pci_dev *pdev = hw->pdev;
2819 u32 hwe_mask = Y2_HWE_ALL_MASK;
2822 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2823 status = sky2_read16(hw, HCU_CCSR);
2824 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2825 HCU_CCSR_UC_STATE_MSK);
2826 sky2_write16(hw, HCU_CCSR, status);
2828 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2829 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2832 sky2_write8(hw, B0_CTST, CS_RST_SET);
2833 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2835 /* allow writes to PCI config */
2836 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2838 /* clear PCI errors, if any */
2839 status = sky2_pci_read16(hw, PCI_STATUS);
2840 status |= PCI_STATUS_ERROR_BITS;
2841 sky2_pci_write16(hw, PCI_STATUS, status);
2843 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2845 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2847 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2850 /* If error bit is stuck on ignore it */
2851 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2852 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2854 hwe_mask |= Y2_IS_PCI_EXP;
2858 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2860 for (i = 0; i < hw->ports; i++) {
2861 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2862 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2864 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2865 hw->chip_id == CHIP_ID_YUKON_SUPR)
2866 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2867 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2871 /* Clear I2C IRQ noise */
2872 sky2_write32(hw, B2_I2C_IRQ, 1);
2874 /* turn off hardware timer (unused) */
2875 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2876 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2878 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2880 /* Turn off descriptor polling */
2881 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2883 /* Turn off receive timestamp */
2884 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2885 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2887 /* enable the Tx Arbiters */
2888 for (i = 0; i < hw->ports; i++)
2889 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2891 /* Initialize ram interface */
2892 for (i = 0; i < hw->ports; i++) {
2893 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2895 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2896 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2897 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2898 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2899 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2900 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2901 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2902 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2903 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2904 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2905 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2906 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2909 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
2911 for (i = 0; i < hw->ports; i++)
2912 sky2_gmac_reset(hw, i);
2914 memset(hw->st_le, 0, STATUS_LE_BYTES);
2917 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2918 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2920 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2921 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2923 /* Set the list last index */
2924 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2926 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2927 sky2_write8(hw, STAT_FIFO_WM, 16);
2929 /* set Status-FIFO ISR watermark */
2930 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2931 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2933 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2935 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2936 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2937 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2939 /* enable status unit */
2940 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2942 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2943 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2944 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2947 static void sky2_restart(struct work_struct *work)
2949 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2950 struct net_device *dev;
2954 for (i = 0; i < hw->ports; i++) {
2956 if (netif_running(dev))
2960 napi_disable(&hw->napi);
2961 sky2_write32(hw, B0_IMSK, 0);
2963 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2964 napi_enable(&hw->napi);
2966 for (i = 0; i < hw->ports; i++) {
2968 if (netif_running(dev)) {
2971 printk(KERN_INFO PFX "%s: could not restart %d\n",
2981 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2983 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2986 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2988 const struct sky2_port *sky2 = netdev_priv(dev);
2990 wol->supported = sky2_wol_supported(sky2->hw);
2991 wol->wolopts = sky2->wol;
2994 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2996 struct sky2_port *sky2 = netdev_priv(dev);
2997 struct sky2_hw *hw = sky2->hw;
2999 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
3002 sky2->wol = wol->wolopts;
3004 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3005 hw->chip_id == CHIP_ID_YUKON_EX ||
3006 hw->chip_id == CHIP_ID_YUKON_FE_P)
3007 sky2_write32(hw, B0_CTST, sky2->wol
3008 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3010 if (!netif_running(dev))
3011 sky2_wol_init(sky2);
3015 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3017 if (sky2_is_copper(hw)) {
3018 u32 modes = SUPPORTED_10baseT_Half
3019 | SUPPORTED_10baseT_Full
3020 | SUPPORTED_100baseT_Half
3021 | SUPPORTED_100baseT_Full
3022 | SUPPORTED_Autoneg | SUPPORTED_TP;
3024 if (hw->flags & SKY2_HW_GIGABIT)
3025 modes |= SUPPORTED_1000baseT_Half
3026 | SUPPORTED_1000baseT_Full;
3029 return SUPPORTED_1000baseT_Half
3030 | SUPPORTED_1000baseT_Full
3035 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3037 struct sky2_port *sky2 = netdev_priv(dev);
3038 struct sky2_hw *hw = sky2->hw;
3040 ecmd->transceiver = XCVR_INTERNAL;
3041 ecmd->supported = sky2_supported_modes(hw);
3042 ecmd->phy_address = PHY_ADDR_MARV;
3043 if (sky2_is_copper(hw)) {
3044 ecmd->port = PORT_TP;
3045 ecmd->speed = sky2->speed;
3047 ecmd->speed = SPEED_1000;
3048 ecmd->port = PORT_FIBRE;
3051 ecmd->advertising = sky2->advertising;
3052 ecmd->autoneg = sky2->autoneg;
3053 ecmd->duplex = sky2->duplex;
3057 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3059 struct sky2_port *sky2 = netdev_priv(dev);
3060 const struct sky2_hw *hw = sky2->hw;
3061 u32 supported = sky2_supported_modes(hw);
3063 if (ecmd->autoneg == AUTONEG_ENABLE) {
3064 ecmd->advertising = supported;
3070 switch (ecmd->speed) {
3072 if (ecmd->duplex == DUPLEX_FULL)
3073 setting = SUPPORTED_1000baseT_Full;
3074 else if (ecmd->duplex == DUPLEX_HALF)
3075 setting = SUPPORTED_1000baseT_Half;
3080 if (ecmd->duplex == DUPLEX_FULL)
3081 setting = SUPPORTED_100baseT_Full;
3082 else if (ecmd->duplex == DUPLEX_HALF)
3083 setting = SUPPORTED_100baseT_Half;
3089 if (ecmd->duplex == DUPLEX_FULL)
3090 setting = SUPPORTED_10baseT_Full;
3091 else if (ecmd->duplex == DUPLEX_HALF)
3092 setting = SUPPORTED_10baseT_Half;
3100 if ((setting & supported) == 0)
3103 sky2->speed = ecmd->speed;
3104 sky2->duplex = ecmd->duplex;
3107 sky2->autoneg = ecmd->autoneg;
3108 sky2->advertising = ecmd->advertising;
3110 if (netif_running(dev)) {
3111 sky2_phy_reinit(sky2);
3112 sky2_set_multicast(dev);
3118 static void sky2_get_drvinfo(struct net_device *dev,
3119 struct ethtool_drvinfo *info)
3121 struct sky2_port *sky2 = netdev_priv(dev);
3123 strcpy(info->driver, DRV_NAME);
3124 strcpy(info->version, DRV_VERSION);
3125 strcpy(info->fw_version, "N/A");
3126 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3129 static const struct sky2_stat {
3130 char name[ETH_GSTRING_LEN];
3133 { "tx_bytes", GM_TXO_OK_HI },
3134 { "rx_bytes", GM_RXO_OK_HI },
3135 { "tx_broadcast", GM_TXF_BC_OK },
3136 { "rx_broadcast", GM_RXF_BC_OK },
3137 { "tx_multicast", GM_TXF_MC_OK },
3138 { "rx_multicast", GM_RXF_MC_OK },
3139 { "tx_unicast", GM_TXF_UC_OK },
3140 { "rx_unicast", GM_RXF_UC_OK },
3141 { "tx_mac_pause", GM_TXF_MPAUSE },
3142 { "rx_mac_pause", GM_RXF_MPAUSE },
3143 { "collisions", GM_TXF_COL },
3144 { "late_collision",GM_TXF_LAT_COL },
3145 { "aborted", GM_TXF_ABO_COL },
3146 { "single_collisions", GM_TXF_SNG_COL },
3147 { "multi_collisions", GM_TXF_MUL_COL },
3149 { "rx_short", GM_RXF_SHT },
3150 { "rx_runt", GM_RXE_FRAG },
3151 { "rx_64_byte_packets", GM_RXF_64B },
3152 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3153 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3154 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3155 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3156 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3157 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3158 { "rx_too_long", GM_RXF_LNG_ERR },
3159 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3160 { "rx_jabber", GM_RXF_JAB_PKT },
3161 { "rx_fcs_error", GM_RXF_FCS_ERR },
3163 { "tx_64_byte_packets", GM_TXF_64B },
3164 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3165 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3166 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3167 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3168 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3169 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3170 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3173 static u32 sky2_get_rx_csum(struct net_device *dev)
3175 struct sky2_port *sky2 = netdev_priv(dev);
3177 return sky2->rx_csum;
3180 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3182 struct sky2_port *sky2 = netdev_priv(dev);
3184 sky2->rx_csum = data;
3186 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3187 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3192 static u32 sky2_get_msglevel(struct net_device *netdev)
3194 struct sky2_port *sky2 = netdev_priv(netdev);
3195 return sky2->msg_enable;
3198 static int sky2_nway_reset(struct net_device *dev)
3200 struct sky2_port *sky2 = netdev_priv(dev);
3202 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3205 sky2_phy_reinit(sky2);
3206 sky2_set_multicast(dev);
3211 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3213 struct sky2_hw *hw = sky2->hw;
3214 unsigned port = sky2->port;
3217 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3218 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3219 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3220 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3222 for (i = 2; i < count; i++)
3223 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3226 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3228 struct sky2_port *sky2 = netdev_priv(netdev);
3229 sky2->msg_enable = value;
3232 static int sky2_get_sset_count(struct net_device *dev, int sset)
3236 return ARRAY_SIZE(sky2_stats);
3242 static void sky2_get_ethtool_stats(struct net_device *dev,
3243 struct ethtool_stats *stats, u64 * data)
3245 struct sky2_port *sky2 = netdev_priv(dev);
3247 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3250 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3254 switch (stringset) {
3256 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3257 memcpy(data + i * ETH_GSTRING_LEN,
3258 sky2_stats[i].name, ETH_GSTRING_LEN);
3263 static int sky2_set_mac_address(struct net_device *dev, void *p)
3265 struct sky2_port *sky2 = netdev_priv(dev);
3266 struct sky2_hw *hw = sky2->hw;
3267 unsigned port = sky2->port;
3268 const struct sockaddr *addr = p;
3270 if (!is_valid_ether_addr(addr->sa_data))
3271 return -EADDRNOTAVAIL;
3273 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3274 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3275 dev->dev_addr, ETH_ALEN);
3276 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3277 dev->dev_addr, ETH_ALEN);
3279 /* virtual address for data */
3280 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3282 /* physical address: used for pause frames */
3283 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3288 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3292 bit = ether_crc(ETH_ALEN, addr) & 63;
3293 filter[bit >> 3] |= 1 << (bit & 7);
3296 static void sky2_set_multicast(struct net_device *dev)
3298 struct sky2_port *sky2 = netdev_priv(dev);
3299 struct sky2_hw *hw = sky2->hw;
3300 unsigned port = sky2->port;
3301 struct dev_mc_list *list = dev->mc_list;
3305 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3307 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3308 memset(filter, 0, sizeof(filter));
3310 reg = gma_read16(hw, port, GM_RX_CTRL);
3311 reg |= GM_RXCR_UCF_ENA;
3313 if (dev->flags & IFF_PROMISC) /* promiscuous */
3314 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3315 else if (dev->flags & IFF_ALLMULTI)
3316 memset(filter, 0xff, sizeof(filter));
3317 else if (dev->mc_count == 0 && !rx_pause)
3318 reg &= ~GM_RXCR_MCF_ENA;
3321 reg |= GM_RXCR_MCF_ENA;
3324 sky2_add_filter(filter, pause_mc_addr);
3326 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3327 sky2_add_filter(filter, list->dmi_addr);
3330 gma_write16(hw, port, GM_MC_ADDR_H1,
3331 (u16) filter[0] | ((u16) filter[1] << 8));
3332 gma_write16(hw, port, GM_MC_ADDR_H2,
3333 (u16) filter[2] | ((u16) filter[3] << 8));
3334 gma_write16(hw, port, GM_MC_ADDR_H3,
3335 (u16) filter[4] | ((u16) filter[5] << 8));
3336 gma_write16(hw, port, GM_MC_ADDR_H4,
3337 (u16) filter[6] | ((u16) filter[7] << 8));
3339 gma_write16(hw, port, GM_RX_CTRL, reg);
3342 /* Can have one global because blinking is controlled by
3343 * ethtool and that is always under RTNL mutex
3345 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3347 struct sky2_hw *hw = sky2->hw;
3348 unsigned port = sky2->port;
3350 spin_lock_bh(&sky2->phy_lock);
3351 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3352 hw->chip_id == CHIP_ID_YUKON_EX ||
3353 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3355 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3356 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3360 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3361 PHY_M_LEDC_LOS_CTRL(8) |
3362 PHY_M_LEDC_INIT_CTRL(8) |
3363 PHY_M_LEDC_STA1_CTRL(8) |
3364 PHY_M_LEDC_STA0_CTRL(8));
3367 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3368 PHY_M_LEDC_LOS_CTRL(9) |
3369 PHY_M_LEDC_INIT_CTRL(9) |
3370 PHY_M_LEDC_STA1_CTRL(9) |
3371 PHY_M_LEDC_STA0_CTRL(9));
3374 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3375 PHY_M_LEDC_LOS_CTRL(0xa) |
3376 PHY_M_LEDC_INIT_CTRL(0xa) |
3377 PHY_M_LEDC_STA1_CTRL(0xa) |
3378 PHY_M_LEDC_STA0_CTRL(0xa));
3381 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3382 PHY_M_LEDC_LOS_CTRL(1) |
3383 PHY_M_LEDC_INIT_CTRL(8) |
3384 PHY_M_LEDC_STA1_CTRL(7) |
3385 PHY_M_LEDC_STA0_CTRL(7));
3388 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3390 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3391 PHY_M_LED_MO_DUP(mode) |
3392 PHY_M_LED_MO_10(mode) |
3393 PHY_M_LED_MO_100(mode) |
3394 PHY_M_LED_MO_1000(mode) |
3395 PHY_M_LED_MO_RX(mode) |
3396 PHY_M_LED_MO_TX(mode));
3398 spin_unlock_bh(&sky2->phy_lock);
3401 /* blink LED's for finding board */
3402 static int sky2_phys_id(struct net_device *dev, u32 data)
3404 struct sky2_port *sky2 = netdev_priv(dev);
3410 for (i = 0; i < data; i++) {
3411 sky2_led(sky2, MO_LED_ON);
3412 if (msleep_interruptible(500))
3414 sky2_led(sky2, MO_LED_OFF);
3415 if (msleep_interruptible(500))
3418 sky2_led(sky2, MO_LED_NORM);
3423 static void sky2_get_pauseparam(struct net_device *dev,
3424 struct ethtool_pauseparam *ecmd)
3426 struct sky2_port *sky2 = netdev_priv(dev);
3428 switch (sky2->flow_mode) {
3430 ecmd->tx_pause = ecmd->rx_pause = 0;
3433 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3436 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3439 ecmd->tx_pause = ecmd->rx_pause = 1;
3442 ecmd->autoneg = sky2->autoneg;
3445 static int sky2_set_pauseparam(struct net_device *dev,
3446 struct ethtool_pauseparam *ecmd)
3448 struct sky2_port *sky2 = netdev_priv(dev);
3450 sky2->autoneg = ecmd->autoneg;
3451 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3453 if (netif_running(dev))
3454 sky2_phy_reinit(sky2);
3459 static int sky2_get_coalesce(struct net_device *dev,
3460 struct ethtool_coalesce *ecmd)
3462 struct sky2_port *sky2 = netdev_priv(dev);
3463 struct sky2_hw *hw = sky2->hw;
3465 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3466 ecmd->tx_coalesce_usecs = 0;
3468 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3469 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3471 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3473 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3474 ecmd->rx_coalesce_usecs = 0;
3476 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3477 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3479 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3481 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3482 ecmd->rx_coalesce_usecs_irq = 0;
3484 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3485 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3488 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3493 /* Note: this affect both ports */
3494 static int sky2_set_coalesce(struct net_device *dev,
3495 struct ethtool_coalesce *ecmd)
3497 struct sky2_port *sky2 = netdev_priv(dev);
3498 struct sky2_hw *hw = sky2->hw;
3499 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3501 if (ecmd->tx_coalesce_usecs > tmax ||
3502 ecmd->rx_coalesce_usecs > tmax ||
3503 ecmd->rx_coalesce_usecs_irq > tmax)
3506 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3508 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3510 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3513 if (ecmd->tx_coalesce_usecs == 0)
3514 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3516 sky2_write32(hw, STAT_TX_TIMER_INI,
3517 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3518 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3520 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3522 if (ecmd->rx_coalesce_usecs == 0)
3523 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3525 sky2_write32(hw, STAT_LEV_TIMER_INI,
3526 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3527 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3529 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3531 if (ecmd->rx_coalesce_usecs_irq == 0)
3532 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3534 sky2_write32(hw, STAT_ISR_TIMER_INI,
3535 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3536 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3538 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3542 static void sky2_get_ringparam(struct net_device *dev,
3543 struct ethtool_ringparam *ering)
3545 struct sky2_port *sky2 = netdev_priv(dev);
3547 ering->rx_max_pending = RX_MAX_PENDING;
3548 ering->rx_mini_max_pending = 0;
3549 ering->rx_jumbo_max_pending = 0;
3550 ering->tx_max_pending = TX_RING_SIZE - 1;
3552 ering->rx_pending = sky2->rx_pending;
3553 ering->rx_mini_pending = 0;
3554 ering->rx_jumbo_pending = 0;
3555 ering->tx_pending = sky2->tx_pending;
3558 static int sky2_set_ringparam(struct net_device *dev,
3559 struct ethtool_ringparam *ering)
3561 struct sky2_port *sky2 = netdev_priv(dev);
3564 if (ering->rx_pending > RX_MAX_PENDING ||
3565 ering->rx_pending < 8 ||
3566 ering->tx_pending < MAX_SKB_TX_LE ||
3567 ering->tx_pending > TX_RING_SIZE - 1)
3570 if (netif_running(dev))
3573 sky2->rx_pending = ering->rx_pending;
3574 sky2->tx_pending = ering->tx_pending;
3576 if (netif_running(dev)) {
3585 static int sky2_get_regs_len(struct net_device *dev)
3591 * Returns copy of control register region
3592 * Note: ethtool_get_regs always provides full size (16k) buffer
3594 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3597 const struct sky2_port *sky2 = netdev_priv(dev);
3598 const void __iomem *io = sky2->hw->regs;
3603 for (b = 0; b < 128; b++) {
3604 /* This complicated switch statement is to make sure and
3605 * only access regions that are unreserved.
3606 * Some blocks are only valid on dual port cards.
3607 * and block 3 has some special diagnostic registers that
3612 /* skip diagnostic ram region */
3613 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3616 /* dual port cards only */
3617 case 5: /* Tx Arbiter 2 */
3619 case 14 ... 15: /* TX2 */
3620 case 17: case 19: /* Ram Buffer 2 */
3621 case 22 ... 23: /* Tx Ram Buffer 2 */
3622 case 25: /* Rx MAC Fifo 1 */
3623 case 27: /* Tx MAC Fifo 2 */
3624 case 31: /* GPHY 2 */
3625 case 40 ... 47: /* Pattern Ram 2 */
3626 case 52: case 54: /* TCP Segmentation 2 */
3627 case 112 ... 116: /* GMAC 2 */
3628 if (sky2->hw->ports == 1)
3631 case 0: /* Control */
3632 case 2: /* Mac address */
3633 case 4: /* Tx Arbiter 1 */
3634 case 7: /* PCI express reg */
3636 case 12 ... 13: /* TX1 */
3637 case 16: case 18:/* Rx Ram Buffer 1 */
3638 case 20 ... 21: /* Tx Ram Buffer 1 */
3639 case 24: /* Rx MAC Fifo 1 */
3640 case 26: /* Tx MAC Fifo 1 */
3641 case 28 ... 29: /* Descriptor and status unit */
3642 case 30: /* GPHY 1*/
3643 case 32 ... 39: /* Pattern Ram 1 */
3644 case 48: case 50: /* TCP Segmentation 1 */
3645 case 56 ... 60: /* PCI space */
3646 case 80 ... 84: /* GMAC 1 */
3647 memcpy_fromio(p, io, 128);
3659 /* In order to do Jumbo packets on these chips, need to turn off the
3660 * transmit store/forward. Therefore checksum offload won't work.
3662 static int no_tx_offload(struct net_device *dev)
3664 const struct sky2_port *sky2 = netdev_priv(dev);
3665 const struct sky2_hw *hw = sky2->hw;
3667 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3670 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3672 if (data && no_tx_offload(dev))
3675 return ethtool_op_set_tx_csum(dev, data);
3679 static int sky2_set_tso(struct net_device *dev, u32 data)
3681 if (data && no_tx_offload(dev))
3684 return ethtool_op_set_tso(dev, data);
3687 static int sky2_get_eeprom_len(struct net_device *dev)
3689 struct sky2_port *sky2 = netdev_priv(dev);
3690 struct sky2_hw *hw = sky2->hw;
3693 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3694 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3697 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3701 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3704 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3705 } while (!(offset & PCI_VPD_ADDR_F));
3707 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3711 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3713 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3714 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3716 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3717 } while (offset & PCI_VPD_ADDR_F);
3720 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3723 struct sky2_port *sky2 = netdev_priv(dev);
3724 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3725 int length = eeprom->len;
3726 u16 offset = eeprom->offset;
3731 eeprom->magic = SKY2_EEPROM_MAGIC;
3733 while (length > 0) {
3734 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3735 int n = min_t(int, length, sizeof(val));
3737 memcpy(data, &val, n);
3745 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3748 struct sky2_port *sky2 = netdev_priv(dev);
3749 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3750 int length = eeprom->len;
3751 u16 offset = eeprom->offset;
3756 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3759 while (length > 0) {
3761 int n = min_t(int, length, sizeof(val));
3763 if (n < sizeof(val))
3764 val = sky2_vpd_read(sky2->hw, cap, offset);
3765 memcpy(&val, data, n);
3767 sky2_vpd_write(sky2->hw, cap, offset, val);
3777 static const struct ethtool_ops sky2_ethtool_ops = {
3778 .get_settings = sky2_get_settings,
3779 .set_settings = sky2_set_settings,
3780 .get_drvinfo = sky2_get_drvinfo,
3781 .get_wol = sky2_get_wol,
3782 .set_wol = sky2_set_wol,
3783 .get_msglevel = sky2_get_msglevel,
3784 .set_msglevel = sky2_set_msglevel,
3785 .nway_reset = sky2_nway_reset,
3786 .get_regs_len = sky2_get_regs_len,
3787 .get_regs = sky2_get_regs,
3788 .get_link = ethtool_op_get_link,
3789 .get_eeprom_len = sky2_get_eeprom_len,
3790 .get_eeprom = sky2_get_eeprom,
3791 .set_eeprom = sky2_set_eeprom,
3792 .set_sg = ethtool_op_set_sg,
3793 .set_tx_csum = sky2_set_tx_csum,
3794 .set_tso = sky2_set_tso,
3795 .get_rx_csum = sky2_get_rx_csum,
3796 .set_rx_csum = sky2_set_rx_csum,
3797 .get_strings = sky2_get_strings,
3798 .get_coalesce = sky2_get_coalesce,
3799 .set_coalesce = sky2_set_coalesce,
3800 .get_ringparam = sky2_get_ringparam,
3801 .set_ringparam = sky2_set_ringparam,
3802 .get_pauseparam = sky2_get_pauseparam,
3803 .set_pauseparam = sky2_set_pauseparam,
3804 .phys_id = sky2_phys_id,
3805 .get_sset_count = sky2_get_sset_count,
3806 .get_ethtool_stats = sky2_get_ethtool_stats,
3809 #ifdef CONFIG_SKY2_DEBUG
3811 static struct dentry *sky2_debug;
3813 static int sky2_debug_show(struct seq_file *seq, void *v)
3815 struct net_device *dev = seq->private;
3816 const struct sky2_port *sky2 = netdev_priv(dev);
3817 struct sky2_hw *hw = sky2->hw;
3818 unsigned port = sky2->port;
3822 if (!netif_running(dev))
3825 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3826 sky2_read32(hw, B0_ISRC),
3827 sky2_read32(hw, B0_IMSK),
3828 sky2_read32(hw, B0_Y2_SP_ICR));
3830 napi_disable(&hw->napi);
3831 last = sky2_read16(hw, STAT_PUT_IDX);
3833 if (hw->st_idx == last)
3834 seq_puts(seq, "Status ring (empty)\n");
3836 seq_puts(seq, "Status ring\n");
3837 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3838 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3839 const struct sky2_status_le *le = hw->st_le + idx;
3840 seq_printf(seq, "[%d] %#x %d %#x\n",
3841 idx, le->opcode, le->length, le->status);
3843 seq_puts(seq, "\n");
3846 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3847 sky2->tx_cons, sky2->tx_prod,
3848 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3849 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3851 /* Dump contents of tx ring */
3853 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3854 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3855 const struct sky2_tx_le *le = sky2->tx_le + idx;
3856 u32 a = le32_to_cpu(le->addr);
3859 seq_printf(seq, "%u:", idx);
3862 switch(le->opcode & ~HW_OWNER) {
3864 seq_printf(seq, " %#x:", a);
3867 seq_printf(seq, " mtu=%d", a);
3870 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3873 seq_printf(seq, " csum=%#x", a);
3876 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3879 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3882 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3885 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3886 a, le16_to_cpu(le->length));
3889 if (le->ctrl & EOP) {
3890 seq_putc(seq, '\n');
3895 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3896 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3897 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3898 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3900 sky2_read32(hw, B0_Y2_SP_LISR);
3901 napi_enable(&hw->napi);
3905 static int sky2_debug_open(struct inode *inode, struct file *file)
3907 return single_open(file, sky2_debug_show, inode->i_private);
3910 static const struct file_operations sky2_debug_fops = {
3911 .owner = THIS_MODULE,
3912 .open = sky2_debug_open,
3914 .llseek = seq_lseek,
3915 .release = single_release,
3919 * Use network device events to create/remove/rename
3920 * debugfs file entries
3922 static int sky2_device_event(struct notifier_block *unused,
3923 unsigned long event, void *ptr)
3925 struct net_device *dev = ptr;
3926 struct sky2_port *sky2 = netdev_priv(dev);
3928 if (dev->open != sky2_up || !sky2_debug)
3932 case NETDEV_CHANGENAME:
3933 if (sky2->debugfs) {
3934 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3935 sky2_debug, dev->name);
3939 case NETDEV_GOING_DOWN:
3940 if (sky2->debugfs) {
3941 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3943 debugfs_remove(sky2->debugfs);
3944 sky2->debugfs = NULL;
3949 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3952 if (IS_ERR(sky2->debugfs))
3953 sky2->debugfs = NULL;
3959 static struct notifier_block sky2_notifier = {
3960 .notifier_call = sky2_device_event,
3964 static __init void sky2_debug_init(void)
3968 ent = debugfs_create_dir("sky2", NULL);
3969 if (!ent || IS_ERR(ent))
3973 register_netdevice_notifier(&sky2_notifier);
3976 static __exit void sky2_debug_cleanup(void)
3979 unregister_netdevice_notifier(&sky2_notifier);
3980 debugfs_remove(sky2_debug);
3986 #define sky2_debug_init()
3987 #define sky2_debug_cleanup()
3991 /* Initialize network device */
3992 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3994 int highmem, int wol)
3996 struct sky2_port *sky2;
3997 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4000 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4004 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4005 dev->irq = hw->pdev->irq;
4006 dev->open = sky2_up;
4007 dev->stop = sky2_down;
4008 dev->do_ioctl = sky2_ioctl;
4009 dev->hard_start_xmit = sky2_xmit_frame;
4010 dev->set_multicast_list = sky2_set_multicast;
4011 dev->set_mac_address = sky2_set_mac_address;
4012 dev->change_mtu = sky2_change_mtu;
4013 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4014 dev->tx_timeout = sky2_tx_timeout;
4015 dev->watchdog_timeo = TX_WATCHDOG;
4016 #ifdef CONFIG_NET_POLL_CONTROLLER
4018 dev->poll_controller = sky2_netpoll;
4021 sky2 = netdev_priv(dev);
4024 sky2->msg_enable = netif_msg_init(debug, default_msg);
4026 /* Auto speed and flow control */
4027 sky2->autoneg = AUTONEG_ENABLE;
4028 sky2->flow_mode = FC_BOTH;
4032 sky2->advertising = sky2_supported_modes(hw);
4033 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4036 spin_lock_init(&sky2->phy_lock);
4037 sky2->tx_pending = TX_DEF_PENDING;
4038 sky2->rx_pending = RX_DEF_PENDING;
4040 hw->dev[port] = dev;
4044 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4046 dev->features |= NETIF_F_HIGHDMA;
4048 #ifdef SKY2_VLAN_TAG_USED
4049 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4050 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4051 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4052 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4053 dev->vlan_rx_register = sky2_vlan_rx_register;
4057 /* read the mac address */
4058 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4059 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4064 static void __devinit sky2_show_addr(struct net_device *dev)
4066 const struct sky2_port *sky2 = netdev_priv(dev);
4067 DECLARE_MAC_BUF(mac);
4069 if (netif_msg_probe(sky2))
4070 printk(KERN_INFO PFX "%s: addr %s\n",
4071 dev->name, print_mac(mac, dev->dev_addr));
4074 /* Handle software interrupt used during MSI test */
4075 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4077 struct sky2_hw *hw = dev_id;
4078 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4083 if (status & Y2_IS_IRQ_SW) {
4084 hw->flags |= SKY2_HW_USE_MSI;
4085 wake_up(&hw->msi_wait);
4086 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4088 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4093 /* Test interrupt path by forcing a a software IRQ */
4094 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4096 struct pci_dev *pdev = hw->pdev;
4099 init_waitqueue_head (&hw->msi_wait);
4101 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4103 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4105 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4109 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4110 sky2_read8(hw, B0_CTST);
4112 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4114 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4115 /* MSI test failed, go back to INTx mode */
4116 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4117 "switching to INTx mode.\n");
4120 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4123 sky2_write32(hw, B0_IMSK, 0);
4124 sky2_read32(hw, B0_IMSK);
4126 free_irq(pdev->irq, hw);
4131 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4133 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4138 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4140 return value & PCI_PM_CTRL_PME_ENABLE;
4143 static int __devinit sky2_probe(struct pci_dev *pdev,
4144 const struct pci_device_id *ent)
4146 struct net_device *dev;
4148 int err, using_dac = 0, wol_default;
4150 err = pci_enable_device(pdev);
4152 dev_err(&pdev->dev, "cannot enable PCI device\n");
4156 err = pci_request_regions(pdev, DRV_NAME);
4158 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4159 goto err_out_disable;
4162 pci_set_master(pdev);
4164 if (sizeof(dma_addr_t) > sizeof(u32) &&
4165 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4167 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4169 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4170 "for consistent allocations\n");
4171 goto err_out_free_regions;
4174 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4176 dev_err(&pdev->dev, "no usable DMA configuration\n");
4177 goto err_out_free_regions;
4181 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4184 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4186 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4187 goto err_out_free_regions;
4192 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4194 dev_err(&pdev->dev, "cannot map device registers\n");
4195 goto err_out_free_hw;
4199 /* The sk98lin vendor driver uses hardware byte swapping but
4200 * this driver uses software swapping.
4204 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
4205 reg &= ~PCI_REV_DESC;
4206 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4210 /* ring for status responses */
4211 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4213 goto err_out_iounmap;
4215 err = sky2_init(hw);
4217 goto err_out_iounmap;
4219 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4220 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4221 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
4222 hw->chip_id, hw->chip_rev);
4226 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4229 goto err_out_free_pci;
4232 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4233 err = sky2_test_msi(hw);
4234 if (err == -EOPNOTSUPP)
4235 pci_disable_msi(pdev);
4237 goto err_out_free_netdev;
4240 err = register_netdev(dev);
4242 dev_err(&pdev->dev, "cannot register net device\n");
4243 goto err_out_free_netdev;
4246 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4248 err = request_irq(pdev->irq, sky2_intr,
4249 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4252 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4253 goto err_out_unregister;
4255 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4256 napi_enable(&hw->napi);
4258 sky2_show_addr(dev);
4260 if (hw->ports > 1) {
4261 struct net_device *dev1;
4263 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4265 dev_warn(&pdev->dev, "allocation for second device failed\n");
4266 else if ((err = register_netdev(dev1))) {
4267 dev_warn(&pdev->dev,
4268 "register of second port failed (%d)\n", err);
4272 sky2_show_addr(dev1);
4275 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4276 INIT_WORK(&hw->restart_work, sky2_restart);
4278 pci_set_drvdata(pdev, hw);
4283 if (hw->flags & SKY2_HW_USE_MSI)
4284 pci_disable_msi(pdev);
4285 unregister_netdev(dev);
4286 err_out_free_netdev:
4289 sky2_write8(hw, B0_CTST, CS_RST_SET);
4290 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4295 err_out_free_regions:
4296 pci_release_regions(pdev);
4298 pci_disable_device(pdev);
4300 pci_set_drvdata(pdev, NULL);
4304 static void __devexit sky2_remove(struct pci_dev *pdev)
4306 struct sky2_hw *hw = pci_get_drvdata(pdev);
4312 del_timer_sync(&hw->watchdog_timer);
4313 cancel_work_sync(&hw->restart_work);
4315 for (i = hw->ports-1; i >= 0; --i)
4316 unregister_netdev(hw->dev[i]);
4318 sky2_write32(hw, B0_IMSK, 0);
4322 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4323 sky2_write8(hw, B0_CTST, CS_RST_SET);
4324 sky2_read8(hw, B0_CTST);
4326 free_irq(pdev->irq, hw);
4327 if (hw->flags & SKY2_HW_USE_MSI)
4328 pci_disable_msi(pdev);
4329 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4330 pci_release_regions(pdev);
4331 pci_disable_device(pdev);
4333 for (i = hw->ports-1; i >= 0; --i)
4334 free_netdev(hw->dev[i]);
4339 pci_set_drvdata(pdev, NULL);
4343 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4345 struct sky2_hw *hw = pci_get_drvdata(pdev);
4351 del_timer_sync(&hw->watchdog_timer);
4352 cancel_work_sync(&hw->restart_work);
4354 for (i = 0; i < hw->ports; i++) {
4355 struct net_device *dev = hw->dev[i];
4356 struct sky2_port *sky2 = netdev_priv(dev);
4358 netif_device_detach(dev);
4359 if (netif_running(dev))
4363 sky2_wol_init(sky2);
4368 sky2_write32(hw, B0_IMSK, 0);
4369 napi_disable(&hw->napi);
4372 pci_save_state(pdev);
4373 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4374 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4379 static int sky2_resume(struct pci_dev *pdev)
4381 struct sky2_hw *hw = pci_get_drvdata(pdev);
4387 err = pci_set_power_state(pdev, PCI_D0);
4391 err = pci_restore_state(pdev);
4395 pci_enable_wake(pdev, PCI_D0, 0);
4397 /* Re-enable all clocks */
4398 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4399 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4400 hw->chip_id == CHIP_ID_YUKON_FE_P)
4401 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4404 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4405 napi_enable(&hw->napi);
4407 for (i = 0; i < hw->ports; i++) {
4408 struct net_device *dev = hw->dev[i];
4410 netif_device_attach(dev);
4411 if (netif_running(dev)) {
4414 printk(KERN_ERR PFX "%s: could not up: %d\n",
4424 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4425 pci_disable_device(pdev);
4430 static void sky2_shutdown(struct pci_dev *pdev)
4432 struct sky2_hw *hw = pci_get_drvdata(pdev);
4438 del_timer_sync(&hw->watchdog_timer);
4440 for (i = 0; i < hw->ports; i++) {
4441 struct net_device *dev = hw->dev[i];
4442 struct sky2_port *sky2 = netdev_priv(dev);
4446 sky2_wol_init(sky2);
4453 pci_enable_wake(pdev, PCI_D3hot, wol);
4454 pci_enable_wake(pdev, PCI_D3cold, wol);
4456 pci_disable_device(pdev);
4457 pci_set_power_state(pdev, PCI_D3hot);
4461 static struct pci_driver sky2_driver = {
4463 .id_table = sky2_id_table,
4464 .probe = sky2_probe,
4465 .remove = __devexit_p(sky2_remove),
4467 .suspend = sky2_suspend,
4468 .resume = sky2_resume,
4470 .shutdown = sky2_shutdown,
4473 static int __init sky2_init_module(void)
4476 return pci_register_driver(&sky2_driver);
4479 static void __exit sky2_cleanup_module(void)
4481 pci_unregister_driver(&sky2_driver);
4482 sky2_debug_cleanup();
4485 module_init(sky2_init_module);
4486 module_exit(sky2_cleanup_module);
4488 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4489 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4490 MODULE_LICENSE("GPL");
4491 MODULE_VERSION(DRV_VERSION);