2 sis190.c: Silicon Integrated Systems SiS190 ethernet driver
4 Copyright (c) 2003 K.M. Liu <kmliu@sis.com>
5 Copyright (c) 2003, 2004 Jeff Garzik <jgarzik@pobox.com>
6 Copyright (c) 2003, 2004, 2005 Francois Romieu <romieu@fr.zoreil.com>
8 Based on r8169.c, tg3.c, 8139cp.c, skge.c, epic100.c and SiS 190/191
11 This software may be used and distributed according to the terms of
12 the GNU General Public License (GPL), incorporated herein by reference.
13 Drivers based on or derived from this code fall under the GPL and must
14 retain the authorship, copyright and license notice. This file is not
15 a complete program and may only be used when the entire operating
16 system is licensed under the GPL.
18 See the file COPYING in this distribution for more information.
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/netdevice.h>
25 #include <linux/rtnetlink.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/pci.h>
29 #include <linux/mii.h>
30 #include <linux/delay.h>
31 #include <linux/crc32.h>
32 #include <linux/dma-mapping.h>
35 #define net_drv(p, arg...) if (netif_msg_drv(p)) \
37 #define net_probe(p, arg...) if (netif_msg_probe(p)) \
39 #define net_link(p, arg...) if (netif_msg_link(p)) \
41 #define net_intr(p, arg...) if (netif_msg_intr(p)) \
43 #define net_tx_err(p, arg...) if (netif_msg_tx_err(p)) \
46 #define PHY_MAX_ADDR 32
47 #define PHY_ID_ANY 0x1f
48 #define MII_REG_ANY 0x1f
50 #define DRV_VERSION "1.2"
51 #define DRV_NAME "sis190"
52 #define SIS190_DRIVER_NAME DRV_NAME " Gigabit Ethernet driver " DRV_VERSION
53 #define PFX DRV_NAME ": "
55 #define sis190_rx_skb netif_rx
56 #define sis190_rx_quota(count, quota) count
58 #define MAC_ADDR_LEN 6
60 #define NUM_TX_DESC 64 /* [8..1024] */
61 #define NUM_RX_DESC 64 /* [8..8192] */
62 #define TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
63 #define RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
64 #define RX_BUF_SIZE 1536
65 #define RX_BUF_MASK 0xfff8
67 #define SIS190_REGS_SIZE 0x80
68 #define SIS190_TX_TIMEOUT (6*HZ)
69 #define SIS190_PHY_TIMEOUT (10*HZ)
70 #define SIS190_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
71 NETIF_MSG_LINK | NETIF_MSG_IFUP | \
74 /* Enhanced PHY access register bit definitions */
75 #define EhnMIIread 0x0000
76 #define EhnMIIwrite 0x0020
77 #define EhnMIIdataShift 16
78 #define EhnMIIpmdShift 6 /* 7016 only */
79 #define EhnMIIregShift 11
80 #define EhnMIIreq 0x0010
81 #define EhnMIInotDone 0x0010
83 /* Write/read MMIO register */
84 #define SIS_W8(reg, val) writeb ((val), ioaddr + (reg))
85 #define SIS_W16(reg, val) writew ((val), ioaddr + (reg))
86 #define SIS_W32(reg, val) writel ((val), ioaddr + (reg))
87 #define SIS_R8(reg) readb (ioaddr + (reg))
88 #define SIS_R16(reg) readw (ioaddr + (reg))
89 #define SIS_R32(reg) readl (ioaddr + (reg))
91 #define SIS_PCI_COMMIT() SIS_R32(IntrControl)
93 enum sis190_registers {
95 TxDescStartAddr = 0x04,
96 rsv0 = 0x08, // reserved
97 TxSts = 0x0c, // unused (Control/Status)
99 RxDescStartAddr = 0x14,
100 rsv1 = 0x18, // reserved
101 RxSts = 0x1c, // unused
105 IntrTimer = 0x2c, // unused (Interupt Timer)
106 PMControl = 0x30, // unused (Power Mgmt Control/Status)
107 rsv2 = 0x34, // reserved
110 StationControl = 0x40,
112 GIoCR = 0x48, // unused (GMAC IO Compensation)
113 GIoCtrl = 0x4c, // unused (GMAC IO Control)
115 TxLimit = 0x54, // unused (Tx MAC Timer/TryLimit)
116 RGDelay = 0x58, // unused (RGMII Tx Internal Delay)
117 rsv3 = 0x5c, // reserved
121 // Undocumented = 0x6c,
123 RxWolData = 0x74, // unused (Rx WOL Data Access)
124 RxMPSControl = 0x78, // unused (Rx MPS Control)
125 rsv4 = 0x7c, // reserved
128 enum sis190_register_content {
130 SoftInt = 0x40000000, // unused
131 Timeup = 0x20000000, // unused
132 PauseFrame = 0x00080000, // unused
133 MagicPacket = 0x00040000, // unused
134 WakeupFrame = 0x00020000, // unused
135 LinkChange = 0x00010000,
136 RxQEmpty = 0x00000080,
138 TxQ1Empty = 0x00000020, // unused
139 TxQ1Int = 0x00000010,
140 TxQ0Empty = 0x00000008, // unused
141 TxQ0Int = 0x00000004,
147 CmdRxEnb = 0x08, // unused
149 RxBufEmpty = 0x01, // unused
152 Cfg9346_Lock = 0x00, // unused
153 Cfg9346_Unlock = 0xc0, // unused
156 AcceptErr = 0x20, // unused
157 AcceptRunt = 0x10, // unused
158 AcceptBroadcast = 0x0800,
159 AcceptMulticast = 0x0400,
160 AcceptMyPhys = 0x0200,
161 AcceptAllPhys = 0x0100,
165 RxCfgDMAShift = 8, // 0x1a in RxControl ?
168 TxInterFrameGapShift = 24,
169 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
171 LinkStatus = 0x02, // unused
172 FullDup = 0x01, // unused
175 TBILinkOK = 0x02000000, // unused
192 enum _DescStatusBit {
194 OWNbit = 0x80000000, // RXOWN/TXOWN
195 INTbit = 0x40000000, // RXINT/TXINT
196 CRCbit = 0x00020000, // CRCOFF/CRCEN
197 PADbit = 0x00010000, // PREADD/PADEN
199 RingEnd = 0x80000000,
201 LSEN = 0x08000000, // TSO ? -- FR
228 RxDescCountMask = 0x7f000000, // multi-desc pkt when > 1 ? -- FR
237 RxSizeMask = 0x0000ffff
239 * The asic could apparently do vlan, TSO, jumbo (sis191 only) and
240 * provide two (unused with Linux) Tx queues. No publically
241 * available documentation alas.
245 enum sis190_eeprom_access_register_bits {
246 EECS = 0x00000001, // unused
247 EECLK = 0x00000002, // unused
248 EEDO = 0x00000008, // unused
249 EEDI = 0x00000004, // unused
252 EEWOP = 0x00000100 // unused
255 /* EEPROM Addresses */
256 enum sis190_eeprom_address {
257 EEPROMSignature = 0x00,
258 EEPROMCLK = 0x01, // unused
263 enum sis190_feature {
269 struct sis190_private {
270 void __iomem *mmio_addr;
271 struct pci_dev *pci_dev;
272 struct net_device *dev;
273 struct net_device_stats stats;
282 struct RxDesc *RxDescRing;
283 struct TxDesc *TxDescRing;
284 struct sk_buff *Rx_skbuff[NUM_RX_DESC];
285 struct sk_buff *Tx_skbuff[NUM_TX_DESC];
286 struct work_struct phy_task;
287 struct timer_list timer;
289 struct mii_if_info mii_if;
290 struct list_head first_phy;
295 struct list_head list;
302 enum sis190_phy_type {
309 static struct mii_chip_info {
314 } mii_chip_table[] = {
315 { "Broadcom PHY BCM5461", { 0x0020, 0x60c0 }, LAN, F_PHY_BCM5461 },
316 { "Broadcom PHY AC131", { 0x0143, 0xbc70 }, LAN, 0 },
317 { "Agere PHY ET1101B", { 0x0282, 0xf010 }, LAN, 0 },
318 { "Marvell PHY 88E1111", { 0x0141, 0x0cc0 }, LAN, F_PHY_88E1111 },
319 { "Realtek PHY RTL8201", { 0x0000, 0x8200 }, LAN, 0 },
323 static const struct {
325 } sis_chip_info[] = {
326 { "SiS 190 PCI Fast Ethernet adapter" },
327 { "SiS 191 PCI Gigabit Ethernet adapter" },
330 static struct pci_device_id sis190_pci_tbl[] __devinitdata = {
331 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0190), 0, 0, 0 },
332 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0191), 0, 0, 1 },
336 MODULE_DEVICE_TABLE(pci, sis190_pci_tbl);
338 static int rx_copybreak = 200;
344 MODULE_DESCRIPTION("SiS sis190 Gigabit Ethernet driver");
345 module_param(rx_copybreak, int, 0);
346 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
347 module_param_named(debug, debug.msg_enable, int, 0);
348 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
349 MODULE_AUTHOR("K.M. Liu <kmliu@sis.com>, Ueimor <romieu@fr.zoreil.com>");
350 MODULE_VERSION(DRV_VERSION);
351 MODULE_LICENSE("GPL");
353 static const u32 sis190_intr_mask =
354 RxQEmpty | RxQInt | TxQ1Int | TxQ0Int | RxHalt | TxHalt | LinkChange;
357 * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
358 * The chips use a 64 element hash table based on the Ethernet CRC.
360 static const int multicast_filter_limit = 32;
362 static void __mdio_cmd(void __iomem *ioaddr, u32 ctl)
366 SIS_W32(GMIIControl, ctl);
370 for (i = 0; i < 100; i++) {
371 if (!(SIS_R32(GMIIControl) & EhnMIInotDone))
377 printk(KERN_ERR PFX "PHY command failed !\n");
380 static void mdio_write(void __iomem *ioaddr, int phy_id, int reg, int val)
382 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIwrite |
383 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift) |
384 (((u32) val) << EhnMIIdataShift));
387 static int mdio_read(void __iomem *ioaddr, int phy_id, int reg)
389 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIread |
390 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift));
392 return (u16) (SIS_R32(GMIIControl) >> EhnMIIdataShift);
395 static void __mdio_write(struct net_device *dev, int phy_id, int reg, int val)
397 struct sis190_private *tp = netdev_priv(dev);
399 mdio_write(tp->mmio_addr, phy_id, reg, val);
402 static int __mdio_read(struct net_device *dev, int phy_id, int reg)
404 struct sis190_private *tp = netdev_priv(dev);
406 return mdio_read(tp->mmio_addr, phy_id, reg);
409 static u16 mdio_read_latched(void __iomem *ioaddr, int phy_id, int reg)
411 mdio_read(ioaddr, phy_id, reg);
412 return mdio_read(ioaddr, phy_id, reg);
415 static u16 __devinit sis190_read_eeprom(void __iomem *ioaddr, u32 reg)
420 if (!(SIS_R32(ROMControl) & 0x0002))
423 SIS_W32(ROMInterface, EEREQ | EEROP | (reg << 10));
425 for (i = 0; i < 200; i++) {
426 if (!(SIS_R32(ROMInterface) & EEREQ)) {
427 data = (SIS_R32(ROMInterface) & 0xffff0000) >> 16;
436 static void sis190_irq_mask_and_ack(void __iomem *ioaddr)
438 SIS_W32(IntrMask, 0x00);
439 SIS_W32(IntrStatus, 0xffffffff);
443 static void sis190_asic_down(void __iomem *ioaddr)
445 /* Stop the chip's Tx and Rx DMA processes. */
447 SIS_W32(TxControl, 0x1a00);
448 SIS_W32(RxControl, 0x1a00);
450 sis190_irq_mask_and_ack(ioaddr);
453 static void sis190_mark_as_last_descriptor(struct RxDesc *desc)
455 desc->size |= cpu_to_le32(RingEnd);
458 static inline void sis190_give_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
460 u32 eor = le32_to_cpu(desc->size) & RingEnd;
463 desc->size = cpu_to_le32((rx_buf_sz & RX_BUF_MASK) | eor);
465 desc->status = cpu_to_le32(OWNbit | INTbit);
468 static inline void sis190_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
471 desc->addr = cpu_to_le32(mapping);
472 sis190_give_to_asic(desc, rx_buf_sz);
475 static inline void sis190_make_unusable_by_asic(struct RxDesc *desc)
478 desc->addr = 0xdeadbeef;
479 desc->size &= cpu_to_le32(RingEnd);
484 static int sis190_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
485 struct RxDesc *desc, u32 rx_buf_sz)
491 skb = dev_alloc_skb(rx_buf_sz);
497 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
500 sis190_map_to_asic(desc, mapping, rx_buf_sz);
506 sis190_make_unusable_by_asic(desc);
510 static u32 sis190_rx_fill(struct sis190_private *tp, struct net_device *dev,
515 for (cur = start; cur < end; cur++) {
516 int ret, i = cur % NUM_RX_DESC;
518 if (tp->Rx_skbuff[i])
521 ret = sis190_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
522 tp->RxDescRing + i, tp->rx_buf_sz);
529 static inline int sis190_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
530 struct RxDesc *desc, int rx_buf_sz)
534 if (pkt_size < rx_copybreak) {
537 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
539 skb_reserve(skb, NET_IP_ALIGN);
540 skb_copy_to_linear_data(skb, sk_buff[0]->data, pkt_size);
542 sis190_give_to_asic(desc, rx_buf_sz);
549 static inline int sis190_rx_pkt_err(u32 status, struct net_device_stats *stats)
551 #define ErrMask (OVRUN | SHORT | LIMIT | MIIER | NIBON | COLON | ABORT)
553 if ((status & CRCOK) && !(status & ErrMask))
556 if (!(status & CRCOK))
557 stats->rx_crc_errors++;
558 else if (status & OVRUN)
559 stats->rx_over_errors++;
560 else if (status & (SHORT | LIMIT))
561 stats->rx_length_errors++;
562 else if (status & (MIIER | NIBON | COLON))
563 stats->rx_frame_errors++;
569 static int sis190_rx_interrupt(struct net_device *dev,
570 struct sis190_private *tp, void __iomem *ioaddr)
572 struct net_device_stats *stats = &tp->stats;
573 u32 rx_left, cur_rx = tp->cur_rx;
576 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
577 rx_left = sis190_rx_quota(rx_left, (u32) dev->quota);
579 for (; rx_left > 0; rx_left--, cur_rx++) {
580 unsigned int entry = cur_rx % NUM_RX_DESC;
581 struct RxDesc *desc = tp->RxDescRing + entry;
584 if (desc->status & OWNbit)
587 status = le32_to_cpu(desc->PSize);
589 // net_intr(tp, KERN_INFO "%s: Rx PSize = %08x.\n", dev->name,
592 if (sis190_rx_pkt_err(status, stats) < 0)
593 sis190_give_to_asic(desc, tp->rx_buf_sz);
595 struct sk_buff *skb = tp->Rx_skbuff[entry];
596 int pkt_size = (status & RxSizeMask) - 4;
597 void (*pci_action)(struct pci_dev *, dma_addr_t,
598 size_t, int) = pci_dma_sync_single_for_device;
600 if (unlikely(pkt_size > tp->rx_buf_sz)) {
601 net_intr(tp, KERN_INFO
602 "%s: (frag) status = %08x.\n",
605 stats->rx_length_errors++;
606 sis190_give_to_asic(desc, tp->rx_buf_sz);
610 pci_dma_sync_single_for_cpu(tp->pci_dev,
611 le32_to_cpu(desc->addr), tp->rx_buf_sz,
614 if (sis190_try_rx_copy(&skb, pkt_size, desc,
616 pci_action = pci_unmap_single;
617 tp->Rx_skbuff[entry] = NULL;
618 sis190_make_unusable_by_asic(desc);
621 pci_action(tp->pci_dev, le32_to_cpu(desc->addr),
622 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
624 skb_put(skb, pkt_size);
625 skb->protocol = eth_type_trans(skb, dev);
629 dev->last_rx = jiffies;
631 stats->rx_bytes += pkt_size;
632 if ((status & BCAST) == MCAST)
636 count = cur_rx - tp->cur_rx;
639 delta = sis190_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
640 if (!delta && count && netif_msg_intr(tp))
641 printk(KERN_INFO "%s: no Rx buffer allocated.\n", dev->name);
642 tp->dirty_rx += delta;
644 if (((tp->dirty_rx + NUM_RX_DESC) == tp->cur_rx) && netif_msg_intr(tp))
645 printk(KERN_EMERG "%s: Rx buffers exhausted.\n", dev->name);
650 static void sis190_unmap_tx_skb(struct pci_dev *pdev, struct sk_buff *skb,
655 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
657 pci_unmap_single(pdev, le32_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
659 memset(desc, 0x00, sizeof(*desc));
662 static void sis190_tx_interrupt(struct net_device *dev,
663 struct sis190_private *tp, void __iomem *ioaddr)
665 u32 pending, dirty_tx = tp->dirty_tx;
667 * It would not be needed if queueing was allowed to be enabled
668 * again too early (hint: think preempt and unclocked smp systems).
670 unsigned int queue_stopped;
673 pending = tp->cur_tx - dirty_tx;
674 queue_stopped = (pending == NUM_TX_DESC);
676 for (; pending; pending--, dirty_tx++) {
677 unsigned int entry = dirty_tx % NUM_TX_DESC;
678 struct TxDesc *txd = tp->TxDescRing + entry;
681 if (le32_to_cpu(txd->status) & OWNbit)
684 skb = tp->Tx_skbuff[entry];
686 tp->stats.tx_packets++;
687 tp->stats.tx_bytes += skb->len;
689 sis190_unmap_tx_skb(tp->pci_dev, skb, txd);
690 tp->Tx_skbuff[entry] = NULL;
691 dev_kfree_skb_irq(skb);
694 if (tp->dirty_tx != dirty_tx) {
695 tp->dirty_tx = dirty_tx;
698 netif_wake_queue(dev);
703 * The interrupt handler does all of the Rx thread work and cleans up after
706 static irqreturn_t sis190_interrupt(int irq, void *__dev)
708 struct net_device *dev = __dev;
709 struct sis190_private *tp = netdev_priv(dev);
710 void __iomem *ioaddr = tp->mmio_addr;
711 unsigned int handled = 0;
714 status = SIS_R32(IntrStatus);
716 if ((status == 0xffffffff) || !status)
721 if (unlikely(!netif_running(dev))) {
722 sis190_asic_down(ioaddr);
726 SIS_W32(IntrStatus, status);
728 // net_intr(tp, KERN_INFO "%s: status = %08x.\n", dev->name, status);
730 if (status & LinkChange) {
731 net_intr(tp, KERN_INFO "%s: link change.\n", dev->name);
732 schedule_work(&tp->phy_task);
736 sis190_rx_interrupt(dev, tp, ioaddr);
738 if (status & TxQ0Int)
739 sis190_tx_interrupt(dev, tp, ioaddr);
741 return IRQ_RETVAL(handled);
744 #ifdef CONFIG_NET_POLL_CONTROLLER
745 static void sis190_netpoll(struct net_device *dev)
747 struct sis190_private *tp = netdev_priv(dev);
748 struct pci_dev *pdev = tp->pci_dev;
750 disable_irq(pdev->irq);
751 sis190_interrupt(pdev->irq, dev);
752 enable_irq(pdev->irq);
756 static void sis190_free_rx_skb(struct sis190_private *tp,
757 struct sk_buff **sk_buff, struct RxDesc *desc)
759 struct pci_dev *pdev = tp->pci_dev;
761 pci_unmap_single(pdev, le32_to_cpu(desc->addr), tp->rx_buf_sz,
763 dev_kfree_skb(*sk_buff);
765 sis190_make_unusable_by_asic(desc);
768 static void sis190_rx_clear(struct sis190_private *tp)
772 for (i = 0; i < NUM_RX_DESC; i++) {
773 if (!tp->Rx_skbuff[i])
775 sis190_free_rx_skb(tp, tp->Rx_skbuff + i, tp->RxDescRing + i);
779 static void sis190_init_ring_indexes(struct sis190_private *tp)
781 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
784 static int sis190_init_ring(struct net_device *dev)
786 struct sis190_private *tp = netdev_priv(dev);
788 sis190_init_ring_indexes(tp);
790 memset(tp->Tx_skbuff, 0x0, NUM_TX_DESC * sizeof(struct sk_buff *));
791 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
793 if (sis190_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
796 sis190_mark_as_last_descriptor(tp->RxDescRing + NUM_RX_DESC - 1);
805 static void sis190_set_rx_mode(struct net_device *dev)
807 struct sis190_private *tp = netdev_priv(dev);
808 void __iomem *ioaddr = tp->mmio_addr;
810 u32 mc_filter[2]; /* Multicast hash filter */
813 if (dev->flags & IFF_PROMISC) {
815 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
817 mc_filter[1] = mc_filter[0] = 0xffffffff;
818 } else if ((dev->mc_count > multicast_filter_limit) ||
819 (dev->flags & IFF_ALLMULTI)) {
820 /* Too many to filter perfectly -- accept all multicasts. */
821 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
822 mc_filter[1] = mc_filter[0] = 0xffffffff;
824 struct dev_mc_list *mclist;
827 rx_mode = AcceptBroadcast | AcceptMyPhys;
828 mc_filter[1] = mc_filter[0] = 0;
829 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
830 i++, mclist = mclist->next) {
832 ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
833 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
834 rx_mode |= AcceptMulticast;
838 spin_lock_irqsave(&tp->lock, flags);
840 SIS_W16(RxMacControl, rx_mode | 0x2);
841 SIS_W32(RxHashTable, mc_filter[0]);
842 SIS_W32(RxHashTable + 4, mc_filter[1]);
844 spin_unlock_irqrestore(&tp->lock, flags);
847 static void sis190_soft_reset(void __iomem *ioaddr)
849 SIS_W32(IntrControl, 0x8000);
852 SIS_W32(IntrControl, 0x0);
853 sis190_asic_down(ioaddr);
857 static void sis190_hw_start(struct net_device *dev)
859 struct sis190_private *tp = netdev_priv(dev);
860 void __iomem *ioaddr = tp->mmio_addr;
862 sis190_soft_reset(ioaddr);
864 SIS_W32(TxDescStartAddr, tp->tx_dma);
865 SIS_W32(RxDescStartAddr, tp->rx_dma);
867 SIS_W32(IntrStatus, 0xffffffff);
868 SIS_W32(IntrMask, 0x0);
869 SIS_W32(GMIIControl, 0x0);
870 SIS_W32(TxMacControl, 0x60);
871 SIS_W16(RxMacControl, 0x02);
872 SIS_W32(RxHashTable, 0x0);
874 SIS_W32(RxWolCtrl, 0x0);
875 SIS_W32(RxWolData, 0x0);
879 sis190_set_rx_mode(dev);
881 /* Enable all known interrupts by setting the interrupt mask. */
882 SIS_W32(IntrMask, sis190_intr_mask);
884 SIS_W32(TxControl, 0x1a00 | CmdTxEnb);
885 SIS_W32(RxControl, 0x1a1d);
887 netif_start_queue(dev);
890 static void sis190_phy_task(struct work_struct *work)
892 struct sis190_private *tp =
893 container_of(work, struct sis190_private, phy_task);
894 struct net_device *dev = tp->dev;
895 void __iomem *ioaddr = tp->mmio_addr;
896 int phy_id = tp->mii_if.phy_id;
901 if (!netif_running(dev))
904 val = mdio_read(ioaddr, phy_id, MII_BMCR);
905 if (val & BMCR_RESET) {
906 // FIXME: needlessly high ? -- FR 02/07/2005
907 mod_timer(&tp->timer, jiffies + HZ/10);
908 } else if (!(mdio_read_latched(ioaddr, phy_id, MII_BMSR) &
909 BMSR_ANEGCOMPLETE)) {
910 net_link(tp, KERN_WARNING "%s: PHY reset until link up.\n",
912 netif_carrier_off(dev);
913 mdio_write(ioaddr, phy_id, MII_BMCR, val | BMCR_RESET);
914 mod_timer(&tp->timer, jiffies + SIS190_PHY_TIMEOUT);
922 { LPA_1000XFULL | LPA_SLCT, 0x07000c00 | 0x00001000,
923 "1000 Mbps Full Duplex" },
924 { LPA_1000XHALF | LPA_SLCT, 0x07000c00,
925 "1000 Mbps Half Duplex" },
926 { LPA_100FULL, 0x04000800 | 0x00001000,
927 "100 Mbps Full Duplex" },
928 { LPA_100HALF, 0x04000800,
929 "100 Mbps Half Duplex" },
930 { LPA_10FULL, 0x04000400 | 0x00001000,
931 "10 Mbps Full Duplex" },
932 { LPA_10HALF, 0x04000400,
933 "10 Mbps Half Duplex" },
934 { 0, 0x04000400, "unknown" }
938 val = mdio_read(ioaddr, phy_id, 0x1f);
939 net_link(tp, KERN_INFO "%s: mii ext = %04x.\n", dev->name, val);
941 val = mdio_read(ioaddr, phy_id, MII_LPA);
942 adv = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
943 net_link(tp, KERN_INFO "%s: mii lpa = %04x adv = %04x.\n",
944 dev->name, val, adv);
948 for (p = reg31; p->val; p++) {
949 if ((val & p->val) == p->val)
953 p->ctl |= SIS_R32(StationControl) & ~0x0f001c00;
955 if ((tp->features & F_HAS_RGMII) &&
956 (tp->features & F_PHY_BCM5461)) {
957 // Set Tx Delay in RGMII mode.
958 mdio_write(ioaddr, phy_id, 0x18, 0xf1c7);
960 mdio_write(ioaddr, phy_id, 0x1c, 0x8c00);
961 p->ctl |= 0x03000000;
964 SIS_W32(StationControl, p->ctl);
966 if (tp->features & F_HAS_RGMII) {
967 SIS_W32(RGDelay, 0x0441);
968 SIS_W32(RGDelay, 0x0440);
971 net_link(tp, KERN_INFO "%s: link on %s mode.\n", dev->name,
973 netif_carrier_on(dev);
980 static void sis190_phy_timer(unsigned long __opaque)
982 struct net_device *dev = (struct net_device *)__opaque;
983 struct sis190_private *tp = netdev_priv(dev);
985 if (likely(netif_running(dev)))
986 schedule_work(&tp->phy_task);
989 static inline void sis190_delete_timer(struct net_device *dev)
991 struct sis190_private *tp = netdev_priv(dev);
993 del_timer_sync(&tp->timer);
996 static inline void sis190_request_timer(struct net_device *dev)
998 struct sis190_private *tp = netdev_priv(dev);
999 struct timer_list *timer = &tp->timer;
1002 timer->expires = jiffies + SIS190_PHY_TIMEOUT;
1003 timer->data = (unsigned long)dev;
1004 timer->function = sis190_phy_timer;
1008 static void sis190_set_rxbufsize(struct sis190_private *tp,
1009 struct net_device *dev)
1011 unsigned int mtu = dev->mtu;
1013 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1014 /* RxDesc->size has a licence to kill the lower bits */
1015 if (tp->rx_buf_sz & 0x07) {
1017 tp->rx_buf_sz &= RX_BUF_MASK;
1021 static int sis190_open(struct net_device *dev)
1023 struct sis190_private *tp = netdev_priv(dev);
1024 struct pci_dev *pdev = tp->pci_dev;
1027 sis190_set_rxbufsize(tp, dev);
1030 * Rx and Tx descriptors need 256 bytes alignment.
1031 * pci_alloc_consistent() guarantees a stronger alignment.
1033 tp->TxDescRing = pci_alloc_consistent(pdev, TX_RING_BYTES, &tp->tx_dma);
1034 if (!tp->TxDescRing)
1037 tp->RxDescRing = pci_alloc_consistent(pdev, RX_RING_BYTES, &tp->rx_dma);
1038 if (!tp->RxDescRing)
1041 rc = sis190_init_ring(dev);
1045 INIT_WORK(&tp->phy_task, sis190_phy_task);
1047 sis190_request_timer(dev);
1049 rc = request_irq(dev->irq, sis190_interrupt, IRQF_SHARED, dev->name, dev);
1051 goto err_release_timer_2;
1053 sis190_hw_start(dev);
1057 err_release_timer_2:
1058 sis190_delete_timer(dev);
1059 sis190_rx_clear(tp);
1061 pci_free_consistent(tp->pci_dev, RX_RING_BYTES, tp->RxDescRing,
1064 pci_free_consistent(tp->pci_dev, TX_RING_BYTES, tp->TxDescRing,
1069 static void sis190_tx_clear(struct sis190_private *tp)
1073 for (i = 0; i < NUM_TX_DESC; i++) {
1074 struct sk_buff *skb = tp->Tx_skbuff[i];
1079 sis190_unmap_tx_skb(tp->pci_dev, skb, tp->TxDescRing + i);
1080 tp->Tx_skbuff[i] = NULL;
1083 tp->stats.tx_dropped++;
1085 tp->cur_tx = tp->dirty_tx = 0;
1088 static void sis190_down(struct net_device *dev)
1090 struct sis190_private *tp = netdev_priv(dev);
1091 void __iomem *ioaddr = tp->mmio_addr;
1092 unsigned int poll_locked = 0;
1094 sis190_delete_timer(dev);
1096 netif_stop_queue(dev);
1099 spin_lock_irq(&tp->lock);
1101 sis190_asic_down(ioaddr);
1103 spin_unlock_irq(&tp->lock);
1105 synchronize_irq(dev->irq);
1110 synchronize_sched();
1112 } while (SIS_R32(IntrMask));
1114 sis190_tx_clear(tp);
1115 sis190_rx_clear(tp);
1118 static int sis190_close(struct net_device *dev)
1120 struct sis190_private *tp = netdev_priv(dev);
1121 struct pci_dev *pdev = tp->pci_dev;
1125 free_irq(dev->irq, dev);
1127 pci_free_consistent(pdev, TX_RING_BYTES, tp->TxDescRing, tp->tx_dma);
1128 pci_free_consistent(pdev, RX_RING_BYTES, tp->RxDescRing, tp->rx_dma);
1130 tp->TxDescRing = NULL;
1131 tp->RxDescRing = NULL;
1136 static int sis190_start_xmit(struct sk_buff *skb, struct net_device *dev)
1138 struct sis190_private *tp = netdev_priv(dev);
1139 void __iomem *ioaddr = tp->mmio_addr;
1140 u32 len, entry, dirty_tx;
1141 struct TxDesc *desc;
1144 if (unlikely(skb->len < ETH_ZLEN)) {
1145 if (skb_padto(skb, ETH_ZLEN)) {
1146 tp->stats.tx_dropped++;
1154 entry = tp->cur_tx % NUM_TX_DESC;
1155 desc = tp->TxDescRing + entry;
1157 if (unlikely(le32_to_cpu(desc->status) & OWNbit)) {
1158 netif_stop_queue(dev);
1159 net_tx_err(tp, KERN_ERR PFX
1160 "%s: BUG! Tx Ring full when queue awake!\n",
1162 return NETDEV_TX_BUSY;
1165 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1167 tp->Tx_skbuff[entry] = skb;
1169 desc->PSize = cpu_to_le32(len);
1170 desc->addr = cpu_to_le32(mapping);
1172 desc->size = cpu_to_le32(len);
1173 if (entry == (NUM_TX_DESC - 1))
1174 desc->size |= cpu_to_le32(RingEnd);
1178 desc->status = cpu_to_le32(OWNbit | INTbit | DEFbit | CRCbit | PADbit);
1184 SIS_W32(TxControl, 0x1a00 | CmdReset | CmdTxEnb);
1186 dev->trans_start = jiffies;
1188 dirty_tx = tp->dirty_tx;
1189 if ((tp->cur_tx - NUM_TX_DESC) == dirty_tx) {
1190 netif_stop_queue(dev);
1192 if (dirty_tx != tp->dirty_tx)
1193 netif_wake_queue(dev);
1196 return NETDEV_TX_OK;
1199 static struct net_device_stats *sis190_get_stats(struct net_device *dev)
1201 struct sis190_private *tp = netdev_priv(dev);
1206 static void sis190_free_phy(struct list_head *first_phy)
1208 struct sis190_phy *cur, *next;
1210 list_for_each_entry_safe(cur, next, first_phy, list) {
1216 * sis190_default_phy - Select default PHY for sis190 mac.
1217 * @dev: the net device to probe for
1219 * Select first detected PHY with link as default.
1220 * If no one is link on, select PHY whose types is HOME as default.
1221 * If HOME doesn't exist, select LAN.
1223 static u16 sis190_default_phy(struct net_device *dev)
1225 struct sis190_phy *phy, *phy_home, *phy_default, *phy_lan;
1226 struct sis190_private *tp = netdev_priv(dev);
1227 struct mii_if_info *mii_if = &tp->mii_if;
1228 void __iomem *ioaddr = tp->mmio_addr;
1231 phy_home = phy_default = phy_lan = NULL;
1233 list_for_each_entry(phy, &tp->first_phy, list) {
1234 status = mdio_read_latched(ioaddr, phy->phy_id, MII_BMSR);
1236 // Link ON & Not select default PHY & not ghost PHY.
1237 if ((status & BMSR_LSTATUS) &&
1239 (phy->type != UNKNOWN)) {
1242 status = mdio_read(ioaddr, phy->phy_id, MII_BMCR);
1243 mdio_write(ioaddr, phy->phy_id, MII_BMCR,
1244 status | BMCR_ANENABLE | BMCR_ISOLATE);
1245 if (phy->type == HOME)
1247 else if (phy->type == LAN)
1254 phy_default = phy_home;
1256 phy_default = phy_lan;
1258 phy_default = list_entry(&tp->first_phy,
1259 struct sis190_phy, list);
1262 if (mii_if->phy_id != phy_default->phy_id) {
1263 mii_if->phy_id = phy_default->phy_id;
1264 net_probe(tp, KERN_INFO
1265 "%s: Using transceiver at address %d as default.\n",
1266 pci_name(tp->pci_dev), mii_if->phy_id);
1269 status = mdio_read(ioaddr, mii_if->phy_id, MII_BMCR);
1270 status &= (~BMCR_ISOLATE);
1272 mdio_write(ioaddr, mii_if->phy_id, MII_BMCR, status);
1273 status = mdio_read_latched(ioaddr, mii_if->phy_id, MII_BMSR);
1278 static void sis190_init_phy(struct net_device *dev, struct sis190_private *tp,
1279 struct sis190_phy *phy, unsigned int phy_id,
1282 void __iomem *ioaddr = tp->mmio_addr;
1283 struct mii_chip_info *p;
1285 INIT_LIST_HEAD(&phy->list);
1286 phy->status = mii_status;
1287 phy->phy_id = phy_id;
1289 phy->id[0] = mdio_read(ioaddr, phy_id, MII_PHYSID1);
1290 phy->id[1] = mdio_read(ioaddr, phy_id, MII_PHYSID2);
1292 for (p = mii_chip_table; p->type; p++) {
1293 if ((p->id[0] == phy->id[0]) &&
1294 (p->id[1] == (phy->id[1] & 0xfff0))) {
1300 phy->type = (p->type == MIX) ?
1301 ((mii_status & (BMSR_100FULL | BMSR_100HALF)) ?
1302 LAN : HOME) : p->type;
1303 tp->features |= p->feature;
1305 phy->type = UNKNOWN;
1307 net_probe(tp, KERN_INFO "%s: %s transceiver at address %d.\n",
1308 pci_name(tp->pci_dev),
1309 (phy->type == UNKNOWN) ? "Unknown PHY" : p->name, phy_id);
1312 static void sis190_mii_probe_88e1111_fixup(struct sis190_private *tp)
1314 if (tp->features & F_PHY_88E1111) {
1315 void __iomem *ioaddr = tp->mmio_addr;
1316 int phy_id = tp->mii_if.phy_id;
1322 p = (tp->features & F_HAS_RGMII) ? reg[0] : reg[1];
1324 mdio_write(ioaddr, phy_id, 0x1b, p[0]);
1326 mdio_write(ioaddr, phy_id, 0x14, p[1]);
1332 * sis190_mii_probe - Probe MII PHY for sis190
1333 * @dev: the net device to probe for
1335 * Search for total of 32 possible mii phy addresses.
1336 * Identify and set current phy if found one,
1337 * return error if it failed to found.
1339 static int __devinit sis190_mii_probe(struct net_device *dev)
1341 struct sis190_private *tp = netdev_priv(dev);
1342 struct mii_if_info *mii_if = &tp->mii_if;
1343 void __iomem *ioaddr = tp->mmio_addr;
1347 INIT_LIST_HEAD(&tp->first_phy);
1349 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1350 struct sis190_phy *phy;
1353 status = mdio_read_latched(ioaddr, phy_id, MII_BMSR);
1355 // Try next mii if the current one is not accessible.
1356 if (status == 0xffff || status == 0x0000)
1359 phy = kmalloc(sizeof(*phy), GFP_KERNEL);
1361 sis190_free_phy(&tp->first_phy);
1366 sis190_init_phy(dev, tp, phy, phy_id, status);
1368 list_add(&tp->first_phy, &phy->list);
1371 if (list_empty(&tp->first_phy)) {
1372 net_probe(tp, KERN_INFO "%s: No MII transceivers found!\n",
1373 pci_name(tp->pci_dev));
1378 /* Select default PHY for mac */
1379 sis190_default_phy(dev);
1381 sis190_mii_probe_88e1111_fixup(tp);
1384 mii_if->mdio_read = __mdio_read;
1385 mii_if->mdio_write = __mdio_write;
1386 mii_if->phy_id_mask = PHY_ID_ANY;
1387 mii_if->reg_num_mask = MII_REG_ANY;
1392 static void __devexit sis190_mii_remove(struct net_device *dev)
1394 struct sis190_private *tp = netdev_priv(dev);
1396 sis190_free_phy(&tp->first_phy);
1399 static void sis190_release_board(struct pci_dev *pdev)
1401 struct net_device *dev = pci_get_drvdata(pdev);
1402 struct sis190_private *tp = netdev_priv(dev);
1404 iounmap(tp->mmio_addr);
1405 pci_release_regions(pdev);
1406 pci_disable_device(pdev);
1410 static struct net_device * __devinit sis190_init_board(struct pci_dev *pdev)
1412 struct sis190_private *tp;
1413 struct net_device *dev;
1414 void __iomem *ioaddr;
1417 dev = alloc_etherdev(sizeof(*tp));
1419 net_drv(&debug, KERN_ERR PFX "unable to alloc new ethernet\n");
1424 SET_NETDEV_DEV(dev, &pdev->dev);
1426 tp = netdev_priv(dev);
1428 tp->msg_enable = netif_msg_init(debug.msg_enable, SIS190_MSG_DEFAULT);
1430 rc = pci_enable_device(pdev);
1432 net_probe(tp, KERN_ERR "%s: enable failure\n", pci_name(pdev));
1433 goto err_free_dev_1;
1438 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1439 net_probe(tp, KERN_ERR "%s: region #0 is no MMIO resource.\n",
1441 goto err_pci_disable_2;
1443 if (pci_resource_len(pdev, 0) < SIS190_REGS_SIZE) {
1444 net_probe(tp, KERN_ERR "%s: invalid PCI region size(s).\n",
1446 goto err_pci_disable_2;
1449 rc = pci_request_regions(pdev, DRV_NAME);
1451 net_probe(tp, KERN_ERR PFX "%s: could not request regions.\n",
1453 goto err_pci_disable_2;
1456 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1458 net_probe(tp, KERN_ERR "%s: DMA configuration failed.\n",
1460 goto err_free_res_3;
1463 pci_set_master(pdev);
1465 ioaddr = ioremap(pci_resource_start(pdev, 0), SIS190_REGS_SIZE);
1467 net_probe(tp, KERN_ERR "%s: cannot remap MMIO, aborting\n",
1470 goto err_free_res_3;
1474 tp->mmio_addr = ioaddr;
1476 sis190_irq_mask_and_ack(ioaddr);
1478 sis190_soft_reset(ioaddr);
1483 pci_release_regions(pdev);
1485 pci_disable_device(pdev);
1493 static void sis190_tx_timeout(struct net_device *dev)
1495 struct sis190_private *tp = netdev_priv(dev);
1496 void __iomem *ioaddr = tp->mmio_addr;
1499 /* Disable Tx, if not already */
1500 tmp8 = SIS_R8(TxControl);
1501 if (tmp8 & CmdTxEnb)
1502 SIS_W8(TxControl, tmp8 & ~CmdTxEnb);
1505 net_tx_err(tp, KERN_INFO "%s: Transmit timeout, status %08x %08x.\n",
1506 dev->name, SIS_R32(TxControl), SIS_R32(TxSts));
1508 /* Disable interrupts by clearing the interrupt mask. */
1509 SIS_W32(IntrMask, 0x0000);
1511 /* Stop a shared interrupt from scavenging while we are. */
1512 spin_lock_irq(&tp->lock);
1513 sis190_tx_clear(tp);
1514 spin_unlock_irq(&tp->lock);
1516 /* ...and finally, reset everything. */
1517 sis190_hw_start(dev);
1519 netif_wake_queue(dev);
1522 static void sis190_set_rgmii(struct sis190_private *tp, u8 reg)
1524 tp->features |= (reg & 0x80) ? F_HAS_RGMII : 0;
1527 static int __devinit sis190_get_mac_addr_from_eeprom(struct pci_dev *pdev,
1528 struct net_device *dev)
1530 struct sis190_private *tp = netdev_priv(dev);
1531 void __iomem *ioaddr = tp->mmio_addr;
1535 net_probe(tp, KERN_INFO "%s: Read MAC address from EEPROM\n",
1538 /* Check to see if there is a sane EEPROM */
1539 sig = (u16) sis190_read_eeprom(ioaddr, EEPROMSignature);
1541 if ((sig == 0xffff) || (sig == 0x0000)) {
1542 net_probe(tp, KERN_INFO "%s: Error EEPROM read %x.\n",
1543 pci_name(pdev), sig);
1547 /* Get MAC address from EEPROM */
1548 for (i = 0; i < MAC_ADDR_LEN / 2; i++) {
1549 __le16 w = sis190_read_eeprom(ioaddr, EEPROMMACAddr + i);
1551 ((u16 *)dev->dev_addr)[i] = le16_to_cpu(w);
1554 sis190_set_rgmii(tp, sis190_read_eeprom(ioaddr, EEPROMInfo));
1560 * sis190_get_mac_addr_from_apc - Get MAC address for SiS965 model
1562 * @dev: network device to get address for
1564 * SiS965 model, use APC CMOS RAM to store MAC address.
1565 * APC CMOS RAM is accessed through ISA bridge.
1566 * MAC address is read into @net_dev->dev_addr.
1568 static int __devinit sis190_get_mac_addr_from_apc(struct pci_dev *pdev,
1569 struct net_device *dev)
1571 struct sis190_private *tp = netdev_priv(dev);
1572 struct pci_dev *isa_bridge;
1576 net_probe(tp, KERN_INFO "%s: Read MAC address from APC.\n",
1579 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0965, NULL);
1581 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0966, NULL);
1584 net_probe(tp, KERN_INFO "%s: Can not find ISA bridge.\n",
1589 /* Enable port 78h & 79h to access APC Registers. */
1590 pci_read_config_byte(isa_bridge, 0x48, &tmp8);
1591 reg = (tmp8 & ~0x02);
1592 pci_write_config_byte(isa_bridge, 0x48, reg);
1594 pci_read_config_byte(isa_bridge, 0x48, ®);
1596 for (i = 0; i < MAC_ADDR_LEN; i++) {
1597 outb(0x9 + i, 0x78);
1598 dev->dev_addr[i] = inb(0x79);
1604 sis190_set_rgmii(tp, reg);
1606 /* Restore the value to ISA Bridge */
1607 pci_write_config_byte(isa_bridge, 0x48, tmp8);
1608 pci_dev_put(isa_bridge);
1614 * sis190_init_rxfilter - Initialize the Rx filter
1615 * @dev: network device to initialize
1617 * Set receive filter address to our MAC address
1618 * and enable packet filtering.
1620 static inline void sis190_init_rxfilter(struct net_device *dev)
1622 struct sis190_private *tp = netdev_priv(dev);
1623 void __iomem *ioaddr = tp->mmio_addr;
1627 ctl = SIS_R16(RxMacControl);
1629 * Disable packet filtering before setting filter.
1630 * Note: SiS's driver writes 32 bits but RxMacControl is 16 bits
1631 * only and followed by RxMacAddr (6 bytes). Strange. -- FR
1633 SIS_W16(RxMacControl, ctl & ~0x0f00);
1635 for (i = 0; i < MAC_ADDR_LEN; i++)
1636 SIS_W8(RxMacAddr + i, dev->dev_addr[i]);
1638 SIS_W16(RxMacControl, ctl);
1642 static int sis190_get_mac_addr(struct pci_dev *pdev, struct net_device *dev)
1646 pci_read_config_byte(pdev, 0x73, &from);
1648 return (from & 0x00000001) ?
1649 sis190_get_mac_addr_from_apc(pdev, dev) :
1650 sis190_get_mac_addr_from_eeprom(pdev, dev);
1653 static void sis190_set_speed_auto(struct net_device *dev)
1655 struct sis190_private *tp = netdev_priv(dev);
1656 void __iomem *ioaddr = tp->mmio_addr;
1657 int phy_id = tp->mii_if.phy_id;
1660 net_link(tp, KERN_INFO "%s: Enabling Auto-negotiation.\n", dev->name);
1662 val = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
1664 // Enable 10/100 Full/Half Mode, leave MII_ADVERTISE bit4:0
1666 mdio_write(ioaddr, phy_id, MII_ADVERTISE, (val & ADVERTISE_SLCT) |
1667 ADVERTISE_100FULL | ADVERTISE_10FULL |
1668 ADVERTISE_100HALF | ADVERTISE_10HALF);
1670 // Enable 1000 Full Mode.
1671 mdio_write(ioaddr, phy_id, MII_CTRL1000, ADVERTISE_1000FULL);
1673 // Enable auto-negotiation and restart auto-negotiation.
1674 mdio_write(ioaddr, phy_id, MII_BMCR,
1675 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET);
1678 static int sis190_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1680 struct sis190_private *tp = netdev_priv(dev);
1682 return mii_ethtool_gset(&tp->mii_if, cmd);
1685 static int sis190_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1687 struct sis190_private *tp = netdev_priv(dev);
1689 return mii_ethtool_sset(&tp->mii_if, cmd);
1692 static void sis190_get_drvinfo(struct net_device *dev,
1693 struct ethtool_drvinfo *info)
1695 struct sis190_private *tp = netdev_priv(dev);
1697 strcpy(info->driver, DRV_NAME);
1698 strcpy(info->version, DRV_VERSION);
1699 strcpy(info->bus_info, pci_name(tp->pci_dev));
1702 static int sis190_get_regs_len(struct net_device *dev)
1704 return SIS190_REGS_SIZE;
1707 static void sis190_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1710 struct sis190_private *tp = netdev_priv(dev);
1711 unsigned long flags;
1713 if (regs->len > SIS190_REGS_SIZE)
1714 regs->len = SIS190_REGS_SIZE;
1716 spin_lock_irqsave(&tp->lock, flags);
1717 memcpy_fromio(p, tp->mmio_addr, regs->len);
1718 spin_unlock_irqrestore(&tp->lock, flags);
1721 static int sis190_nway_reset(struct net_device *dev)
1723 struct sis190_private *tp = netdev_priv(dev);
1725 return mii_nway_restart(&tp->mii_if);
1728 static u32 sis190_get_msglevel(struct net_device *dev)
1730 struct sis190_private *tp = netdev_priv(dev);
1732 return tp->msg_enable;
1735 static void sis190_set_msglevel(struct net_device *dev, u32 value)
1737 struct sis190_private *tp = netdev_priv(dev);
1739 tp->msg_enable = value;
1742 static const struct ethtool_ops sis190_ethtool_ops = {
1743 .get_settings = sis190_get_settings,
1744 .set_settings = sis190_set_settings,
1745 .get_drvinfo = sis190_get_drvinfo,
1746 .get_regs_len = sis190_get_regs_len,
1747 .get_regs = sis190_get_regs,
1748 .get_link = ethtool_op_get_link,
1749 .get_msglevel = sis190_get_msglevel,
1750 .set_msglevel = sis190_set_msglevel,
1751 .nway_reset = sis190_nway_reset,
1754 static int sis190_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1756 struct sis190_private *tp = netdev_priv(dev);
1758 return !netif_running(dev) ? -EINVAL :
1759 generic_mii_ioctl(&tp->mii_if, if_mii(ifr), cmd, NULL);
1762 static int __devinit sis190_init_one(struct pci_dev *pdev,
1763 const struct pci_device_id *ent)
1765 static int printed_version = 0;
1766 struct sis190_private *tp;
1767 struct net_device *dev;
1768 void __iomem *ioaddr;
1771 if (!printed_version) {
1772 net_drv(&debug, KERN_INFO SIS190_DRIVER_NAME " loaded.\n");
1773 printed_version = 1;
1776 dev = sis190_init_board(pdev);
1782 pci_set_drvdata(pdev, dev);
1784 tp = netdev_priv(dev);
1785 ioaddr = tp->mmio_addr;
1787 rc = sis190_get_mac_addr(pdev, dev);
1789 goto err_release_board;
1791 sis190_init_rxfilter(dev);
1793 INIT_WORK(&tp->phy_task, sis190_phy_task);
1795 dev->open = sis190_open;
1796 dev->stop = sis190_close;
1797 dev->do_ioctl = sis190_ioctl;
1798 dev->get_stats = sis190_get_stats;
1799 dev->tx_timeout = sis190_tx_timeout;
1800 dev->watchdog_timeo = SIS190_TX_TIMEOUT;
1801 dev->hard_start_xmit = sis190_start_xmit;
1802 #ifdef CONFIG_NET_POLL_CONTROLLER
1803 dev->poll_controller = sis190_netpoll;
1805 dev->set_multicast_list = sis190_set_rx_mode;
1806 SET_ETHTOOL_OPS(dev, &sis190_ethtool_ops);
1807 dev->irq = pdev->irq;
1808 dev->base_addr = (unsigned long) 0xdead;
1810 spin_lock_init(&tp->lock);
1812 rc = sis190_mii_probe(dev);
1814 goto err_release_board;
1816 rc = register_netdev(dev);
1818 goto err_remove_mii;
1820 net_probe(tp, KERN_INFO "%s: %s at %p (IRQ: %d), "
1821 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
1822 pci_name(pdev), sis_chip_info[ent->driver_data].name,
1824 dev->dev_addr[0], dev->dev_addr[1],
1825 dev->dev_addr[2], dev->dev_addr[3],
1826 dev->dev_addr[4], dev->dev_addr[5]);
1828 net_probe(tp, KERN_INFO "%s: %s mode.\n", dev->name,
1829 (tp->features & F_HAS_RGMII) ? "RGMII" : "GMII");
1831 netif_carrier_off(dev);
1833 sis190_set_speed_auto(dev);
1838 sis190_mii_remove(dev);
1840 sis190_release_board(pdev);
1844 static void __devexit sis190_remove_one(struct pci_dev *pdev)
1846 struct net_device *dev = pci_get_drvdata(pdev);
1848 sis190_mii_remove(dev);
1849 flush_scheduled_work();
1850 unregister_netdev(dev);
1851 sis190_release_board(pdev);
1852 pci_set_drvdata(pdev, NULL);
1855 static struct pci_driver sis190_pci_driver = {
1857 .id_table = sis190_pci_tbl,
1858 .probe = sis190_init_one,
1859 .remove = __devexit_p(sis190_remove_one),
1862 static int __init sis190_init_module(void)
1864 return pci_register_driver(&sis190_pci_driver);
1867 static void __exit sis190_cleanup_module(void)
1869 pci_unregister_driver(&sis190_pci_driver);
1872 module_init(sis190_init_module);
1873 module_exit(sis190_cleanup_module);