2 sis190.c: Silicon Integrated Systems SiS190 ethernet driver
4 Copyright (c) 2003 K.M. Liu <kmliu@sis.com>
5 Copyright (c) 2003, 2004 Jeff Garzik <jgarzik@pobox.com>
6 Copyright (c) 2003, 2004, 2005 Francois Romieu <romieu@fr.zoreil.com>
8 Based on r8169.c, tg3.c, 8139cp.c, skge.c, epic100.c and SiS 190/191
11 This software may be used and distributed according to the terms of
12 the GNU General Public License (GPL), incorporated herein by reference.
13 Drivers based on or derived from this code fall under the GPL and must
14 retain the authorship, copyright and license notice. This file is not
15 a complete program and may only be used when the entire operating
16 system is licensed under the GPL.
18 See the file COPYING in this distribution for more information.
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/netdevice.h>
25 #include <linux/rtnetlink.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/pci.h>
29 #include <linux/mii.h>
30 #include <linux/delay.h>
31 #include <linux/crc32.h>
32 #include <linux/dma-mapping.h>
35 #define net_drv(p, arg...) if (netif_msg_drv(p)) \
37 #define net_probe(p, arg...) if (netif_msg_probe(p)) \
39 #define net_link(p, arg...) if (netif_msg_link(p)) \
41 #define net_intr(p, arg...) if (netif_msg_intr(p)) \
43 #define net_tx_err(p, arg...) if (netif_msg_tx_err(p)) \
46 #define PHY_MAX_ADDR 32
47 #define PHY_ID_ANY 0x1f
48 #define MII_REG_ANY 0x1f
50 #ifdef CONFIG_SIS190_NAPI
51 #define NAPI_SUFFIX "-NAPI"
53 #define NAPI_SUFFIX ""
56 #define DRV_VERSION "1.2" NAPI_SUFFIX
57 #define DRV_NAME "sis190"
58 #define SIS190_DRIVER_NAME DRV_NAME " Gigabit Ethernet driver " DRV_VERSION
59 #define PFX DRV_NAME ": "
61 #ifdef CONFIG_SIS190_NAPI
62 #define sis190_rx_skb netif_receive_skb
63 #define sis190_rx_quota(count, quota) min(count, quota)
65 #define sis190_rx_skb netif_rx
66 #define sis190_rx_quota(count, quota) count
69 #define MAC_ADDR_LEN 6
71 #define NUM_TX_DESC 64 /* [8..1024] */
72 #define NUM_RX_DESC 64 /* [8..8192] */
73 #define TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
74 #define RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
75 #define RX_BUF_SIZE 1536
76 #define RX_BUF_MASK 0xfff8
78 #define SIS190_REGS_SIZE 0x80
79 #define SIS190_TX_TIMEOUT (6*HZ)
80 #define SIS190_PHY_TIMEOUT (10*HZ)
81 #define SIS190_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
82 NETIF_MSG_LINK | NETIF_MSG_IFUP | \
85 /* Enhanced PHY access register bit definitions */
86 #define EhnMIIread 0x0000
87 #define EhnMIIwrite 0x0020
88 #define EhnMIIdataShift 16
89 #define EhnMIIpmdShift 6 /* 7016 only */
90 #define EhnMIIregShift 11
91 #define EhnMIIreq 0x0010
92 #define EhnMIInotDone 0x0010
94 /* Write/read MMIO register */
95 #define SIS_W8(reg, val) writeb ((val), ioaddr + (reg))
96 #define SIS_W16(reg, val) writew ((val), ioaddr + (reg))
97 #define SIS_W32(reg, val) writel ((val), ioaddr + (reg))
98 #define SIS_R8(reg) readb (ioaddr + (reg))
99 #define SIS_R16(reg) readw (ioaddr + (reg))
100 #define SIS_R32(reg) readl (ioaddr + (reg))
102 #define SIS_PCI_COMMIT() SIS_R32(IntrControl)
104 enum sis190_registers {
106 TxDescStartAddr = 0x04,
107 rsv0 = 0x08, // reserved
108 TxSts = 0x0c, // unused (Control/Status)
110 RxDescStartAddr = 0x14,
111 rsv1 = 0x18, // reserved
112 RxSts = 0x1c, // unused
116 IntrTimer = 0x2c, // unused (Interupt Timer)
117 PMControl = 0x30, // unused (Power Mgmt Control/Status)
118 rsv2 = 0x34, // reserved
121 StationControl = 0x40,
123 GIoCR = 0x48, // unused (GMAC IO Compensation)
124 GIoCtrl = 0x4c, // unused (GMAC IO Control)
126 TxLimit = 0x54, // unused (Tx MAC Timer/TryLimit)
127 RGDelay = 0x58, // unused (RGMII Tx Internal Delay)
128 rsv3 = 0x5c, // reserved
132 // Undocumented = 0x6c,
134 RxWolData = 0x74, // unused (Rx WOL Data Access)
135 RxMPSControl = 0x78, // unused (Rx MPS Control)
136 rsv4 = 0x7c, // reserved
139 enum sis190_register_content {
141 SoftInt = 0x40000000, // unused
142 Timeup = 0x20000000, // unused
143 PauseFrame = 0x00080000, // unused
144 MagicPacket = 0x00040000, // unused
145 WakeupFrame = 0x00020000, // unused
146 LinkChange = 0x00010000,
147 RxQEmpty = 0x00000080,
149 TxQ1Empty = 0x00000020, // unused
150 TxQ1Int = 0x00000010,
151 TxQ0Empty = 0x00000008, // unused
152 TxQ0Int = 0x00000004,
158 CmdRxEnb = 0x08, // unused
160 RxBufEmpty = 0x01, // unused
163 Cfg9346_Lock = 0x00, // unused
164 Cfg9346_Unlock = 0xc0, // unused
167 AcceptErr = 0x20, // unused
168 AcceptRunt = 0x10, // unused
169 AcceptBroadcast = 0x0800,
170 AcceptMulticast = 0x0400,
171 AcceptMyPhys = 0x0200,
172 AcceptAllPhys = 0x0100,
176 RxCfgDMAShift = 8, // 0x1a in RxControl ?
179 TxInterFrameGapShift = 24,
180 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
190 LinkStatus = 0x02, // unused
191 FullDup = 0x01, // unused
194 TBILinkOK = 0x02000000, // unused
211 enum _DescStatusBit {
213 OWNbit = 0x80000000, // RXOWN/TXOWN
214 INTbit = 0x40000000, // RXINT/TXINT
215 CRCbit = 0x00020000, // CRCOFF/CRCEN
216 PADbit = 0x00010000, // PREADD/PADEN
218 RingEnd = 0x80000000,
220 LSEN = 0x08000000, // TSO ? -- FR
247 RxDescCountMask = 0x7f000000, // multi-desc pkt when > 1 ? -- FR
256 RxSizeMask = 0x0000ffff
258 * The asic could apparently do vlan, TSO, jumbo (sis191 only) and
259 * provide two (unused with Linux) Tx queues. No publically
260 * available documentation alas.
264 enum sis190_eeprom_access_register_bits {
265 EECS = 0x00000001, // unused
266 EECLK = 0x00000002, // unused
267 EEDO = 0x00000008, // unused
268 EEDI = 0x00000004, // unused
271 EEWOP = 0x00000100 // unused
274 /* EEPROM Addresses */
275 enum sis190_eeprom_address {
276 EEPROMSignature = 0x00,
277 EEPROMCLK = 0x01, // unused
282 enum sis190_feature {
287 struct sis190_private {
288 void __iomem *mmio_addr;
289 struct pci_dev *pci_dev;
290 struct net_device_stats stats;
299 struct RxDesc *RxDescRing;
300 struct TxDesc *TxDescRing;
301 struct sk_buff *Rx_skbuff[NUM_RX_DESC];
302 struct sk_buff *Tx_skbuff[NUM_TX_DESC];
303 struct work_struct phy_task;
304 struct timer_list timer;
306 struct mii_if_info mii_if;
307 struct list_head first_phy;
312 struct list_head list;
319 enum sis190_phy_type {
326 static struct mii_chip_info {
331 } mii_chip_table[] = {
332 { "Broadcom PHY BCM5461", { 0x0020, 0x60c0 }, LAN, 0 },
333 { "Agere PHY ET1101B", { 0x0282, 0xf010 }, LAN, 0 },
334 { "Marvell PHY 88E1111", { 0x0141, 0x0cc0 }, LAN, F_PHY_88E1111 },
335 { "Realtek PHY RTL8201", { 0x0000, 0x8200 }, LAN, 0 },
339 const static struct {
341 u8 version; /* depend on docs */
342 u32 RxConfigMask; /* clear the bits supported by this chip */
343 } sis_chip_info[] = {
344 { DRV_NAME, 0x00, 0xff7e1880, },
347 static struct pci_device_id sis190_pci_tbl[] __devinitdata = {
348 { PCI_DEVICE(PCI_VENDOR_ID_SI, 0x0190), 0, 0, 0 },
352 MODULE_DEVICE_TABLE(pci, sis190_pci_tbl);
354 static int rx_copybreak = 200;
360 MODULE_DESCRIPTION("SiS sis190 Gigabit Ethernet driver");
361 module_param(rx_copybreak, int, 0);
362 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
363 module_param_named(debug, debug.msg_enable, int, 0);
364 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
365 MODULE_AUTHOR("K.M. Liu <kmliu@sis.com>, Ueimor <romieu@fr.zoreil.com>");
366 MODULE_VERSION(DRV_VERSION);
367 MODULE_LICENSE("GPL");
369 static const u32 sis190_intr_mask =
370 RxQEmpty | RxQInt | TxQ1Int | TxQ0Int | RxHalt | TxHalt | LinkChange;
373 * Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
374 * The chips use a 64 element hash table based on the Ethernet CRC.
376 static int multicast_filter_limit = 32;
378 static void __mdio_cmd(void __iomem *ioaddr, u32 ctl)
382 SIS_W32(GMIIControl, ctl);
386 for (i = 0; i < 100; i++) {
387 if (!(SIS_R32(GMIIControl) & EhnMIInotDone))
393 printk(KERN_ERR PFX "PHY command failed !\n");
396 static void mdio_write(void __iomem *ioaddr, int phy_id, int reg, int val)
398 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIwrite |
399 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift) |
400 (((u32) val) << EhnMIIdataShift));
403 static int mdio_read(void __iomem *ioaddr, int phy_id, int reg)
405 __mdio_cmd(ioaddr, EhnMIIreq | EhnMIIread |
406 (((u32) reg) << EhnMIIregShift) | (phy_id << EhnMIIpmdShift));
408 return (u16) (SIS_R32(GMIIControl) >> EhnMIIdataShift);
411 static void __mdio_write(struct net_device *dev, int phy_id, int reg, int val)
413 struct sis190_private *tp = netdev_priv(dev);
415 mdio_write(tp->mmio_addr, phy_id, reg, val);
418 static int __mdio_read(struct net_device *dev, int phy_id, int reg)
420 struct sis190_private *tp = netdev_priv(dev);
422 return mdio_read(tp->mmio_addr, phy_id, reg);
425 static u16 mdio_read_latched(void __iomem *ioaddr, int phy_id, int reg)
427 mdio_read(ioaddr, phy_id, reg);
428 return mdio_read(ioaddr, phy_id, reg);
431 static u16 __devinit sis190_read_eeprom(void __iomem *ioaddr, u32 reg)
436 if (!(SIS_R32(ROMControl) & 0x0002))
439 SIS_W32(ROMInterface, EEREQ | EEROP | (reg << 10));
441 for (i = 0; i < 200; i++) {
442 if (!(SIS_R32(ROMInterface) & EEREQ)) {
443 data = (SIS_R32(ROMInterface) & 0xffff0000) >> 16;
452 static void sis190_irq_mask_and_ack(void __iomem *ioaddr)
454 SIS_W32(IntrMask, 0x00);
455 SIS_W32(IntrStatus, 0xffffffff);
459 static void sis190_asic_down(void __iomem *ioaddr)
461 /* Stop the chip's Tx and Rx DMA processes. */
463 SIS_W32(TxControl, 0x1a00);
464 SIS_W32(RxControl, 0x1a00);
466 sis190_irq_mask_and_ack(ioaddr);
469 static void sis190_mark_as_last_descriptor(struct RxDesc *desc)
471 desc->size |= cpu_to_le32(RingEnd);
474 static inline void sis190_give_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
476 u32 eor = le32_to_cpu(desc->size) & RingEnd;
479 desc->size = cpu_to_le32((rx_buf_sz & RX_BUF_MASK) | eor);
481 desc->status = cpu_to_le32(OWNbit | INTbit);
484 static inline void sis190_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
487 desc->addr = cpu_to_le32(mapping);
488 sis190_give_to_asic(desc, rx_buf_sz);
491 static inline void sis190_make_unusable_by_asic(struct RxDesc *desc)
494 desc->addr = 0xdeadbeef;
495 desc->size &= cpu_to_le32(RingEnd);
500 static int sis190_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
501 struct RxDesc *desc, u32 rx_buf_sz)
507 skb = dev_alloc_skb(rx_buf_sz);
513 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
516 sis190_map_to_asic(desc, mapping, rx_buf_sz);
522 sis190_make_unusable_by_asic(desc);
526 static u32 sis190_rx_fill(struct sis190_private *tp, struct net_device *dev,
531 for (cur = start; cur < end; cur++) {
532 int ret, i = cur % NUM_RX_DESC;
534 if (tp->Rx_skbuff[i])
537 ret = sis190_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
538 tp->RxDescRing + i, tp->rx_buf_sz);
545 static inline int sis190_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
546 struct RxDesc *desc, int rx_buf_sz)
550 if (pkt_size < rx_copybreak) {
553 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
555 skb_reserve(skb, NET_IP_ALIGN);
556 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
558 sis190_give_to_asic(desc, rx_buf_sz);
565 static inline int sis190_rx_pkt_err(u32 status, struct net_device_stats *stats)
567 #define ErrMask (OVRUN | SHORT | LIMIT | MIIER | NIBON | COLON | ABORT)
569 if ((status & CRCOK) && !(status & ErrMask))
572 if (!(status & CRCOK))
573 stats->rx_crc_errors++;
574 else if (status & OVRUN)
575 stats->rx_over_errors++;
576 else if (status & (SHORT | LIMIT))
577 stats->rx_length_errors++;
578 else if (status & (MIIER | NIBON | COLON))
579 stats->rx_frame_errors++;
585 static int sis190_rx_interrupt(struct net_device *dev,
586 struct sis190_private *tp, void __iomem *ioaddr)
588 struct net_device_stats *stats = &tp->stats;
589 u32 rx_left, cur_rx = tp->cur_rx;
592 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
593 rx_left = sis190_rx_quota(rx_left, (u32) dev->quota);
595 for (; rx_left > 0; rx_left--, cur_rx++) {
596 unsigned int entry = cur_rx % NUM_RX_DESC;
597 struct RxDesc *desc = tp->RxDescRing + entry;
600 if (desc->status & OWNbit)
603 status = le32_to_cpu(desc->PSize);
605 // net_intr(tp, KERN_INFO "%s: Rx PSize = %08x.\n", dev->name,
608 if (sis190_rx_pkt_err(status, stats) < 0)
609 sis190_give_to_asic(desc, tp->rx_buf_sz);
611 struct sk_buff *skb = tp->Rx_skbuff[entry];
612 int pkt_size = (status & RxSizeMask) - 4;
613 void (*pci_action)(struct pci_dev *, dma_addr_t,
614 size_t, int) = pci_dma_sync_single_for_device;
616 if (unlikely(pkt_size > tp->rx_buf_sz)) {
617 net_intr(tp, KERN_INFO
618 "%s: (frag) status = %08x.\n",
621 stats->rx_length_errors++;
622 sis190_give_to_asic(desc, tp->rx_buf_sz);
626 pci_dma_sync_single_for_cpu(tp->pci_dev,
627 le32_to_cpu(desc->addr), tp->rx_buf_sz,
630 if (sis190_try_rx_copy(&skb, pkt_size, desc,
632 pci_action = pci_unmap_single;
633 tp->Rx_skbuff[entry] = NULL;
634 sis190_make_unusable_by_asic(desc);
637 pci_action(tp->pci_dev, le32_to_cpu(desc->addr),
638 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
641 skb_put(skb, pkt_size);
642 skb->protocol = eth_type_trans(skb, dev);
646 dev->last_rx = jiffies;
648 stats->rx_bytes += pkt_size;
649 if ((status & BCAST) == MCAST)
653 count = cur_rx - tp->cur_rx;
656 delta = sis190_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
657 if (!delta && count && netif_msg_intr(tp))
658 printk(KERN_INFO "%s: no Rx buffer allocated.\n", dev->name);
659 tp->dirty_rx += delta;
661 if (((tp->dirty_rx + NUM_RX_DESC) == tp->cur_rx) && netif_msg_intr(tp))
662 printk(KERN_EMERG "%s: Rx buffers exhausted.\n", dev->name);
667 static void sis190_unmap_tx_skb(struct pci_dev *pdev, struct sk_buff *skb,
672 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
674 pci_unmap_single(pdev, le32_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
676 memset(desc, 0x00, sizeof(*desc));
679 static void sis190_tx_interrupt(struct net_device *dev,
680 struct sis190_private *tp, void __iomem *ioaddr)
682 u32 pending, dirty_tx = tp->dirty_tx;
684 * It would not be needed if queueing was allowed to be enabled
685 * again too early (hint: think preempt and unclocked smp systems).
687 unsigned int queue_stopped;
690 pending = tp->cur_tx - dirty_tx;
691 queue_stopped = (pending == NUM_TX_DESC);
693 for (; pending; pending--, dirty_tx++) {
694 unsigned int entry = dirty_tx % NUM_TX_DESC;
695 struct TxDesc *txd = tp->TxDescRing + entry;
698 if (le32_to_cpu(txd->status) & OWNbit)
701 skb = tp->Tx_skbuff[entry];
703 tp->stats.tx_packets++;
704 tp->stats.tx_bytes += skb->len;
706 sis190_unmap_tx_skb(tp->pci_dev, skb, txd);
707 tp->Tx_skbuff[entry] = NULL;
708 dev_kfree_skb_irq(skb);
711 if (tp->dirty_tx != dirty_tx) {
712 tp->dirty_tx = dirty_tx;
715 netif_wake_queue(dev);
720 * The interrupt handler does all of the Rx thread work and cleans up after
723 static irqreturn_t sis190_interrupt(int irq, void *__dev, struct pt_regs *regs)
725 struct net_device *dev = __dev;
726 struct sis190_private *tp = netdev_priv(dev);
727 void __iomem *ioaddr = tp->mmio_addr;
728 unsigned int handled = 0;
731 status = SIS_R32(IntrStatus);
733 if ((status == 0xffffffff) || !status)
738 if (unlikely(!netif_running(dev))) {
739 sis190_asic_down(ioaddr);
743 SIS_W32(IntrStatus, status);
745 // net_intr(tp, KERN_INFO "%s: status = %08x.\n", dev->name, status);
747 if (status & LinkChange) {
748 net_intr(tp, KERN_INFO "%s: link change.\n", dev->name);
749 schedule_work(&tp->phy_task);
753 sis190_rx_interrupt(dev, tp, ioaddr);
755 if (status & TxQ0Int)
756 sis190_tx_interrupt(dev, tp, ioaddr);
758 return IRQ_RETVAL(handled);
761 #ifdef CONFIG_NET_POLL_CONTROLLER
762 static void sis190_netpoll(struct net_device *dev)
764 struct sis190_private *tp = netdev_priv(dev);
765 struct pci_dev *pdev = tp->pci_dev;
767 disable_irq(pdev->irq);
768 sis190_interrupt(pdev->irq, dev, NULL);
769 enable_irq(pdev->irq);
773 static void sis190_free_rx_skb(struct sis190_private *tp,
774 struct sk_buff **sk_buff, struct RxDesc *desc)
776 struct pci_dev *pdev = tp->pci_dev;
778 pci_unmap_single(pdev, le32_to_cpu(desc->addr), tp->rx_buf_sz,
780 dev_kfree_skb(*sk_buff);
782 sis190_make_unusable_by_asic(desc);
785 static void sis190_rx_clear(struct sis190_private *tp)
789 for (i = 0; i < NUM_RX_DESC; i++) {
790 if (!tp->Rx_skbuff[i])
792 sis190_free_rx_skb(tp, tp->Rx_skbuff + i, tp->RxDescRing + i);
796 static void sis190_init_ring_indexes(struct sis190_private *tp)
798 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
801 static int sis190_init_ring(struct net_device *dev)
803 struct sis190_private *tp = netdev_priv(dev);
805 sis190_init_ring_indexes(tp);
807 memset(tp->Tx_skbuff, 0x0, NUM_TX_DESC * sizeof(struct sk_buff *));
808 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
810 if (sis190_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
813 sis190_mark_as_last_descriptor(tp->RxDescRing + NUM_RX_DESC - 1);
822 static void sis190_set_rx_mode(struct net_device *dev)
824 struct sis190_private *tp = netdev_priv(dev);
825 void __iomem *ioaddr = tp->mmio_addr;
827 u32 mc_filter[2]; /* Multicast hash filter */
830 if (dev->flags & IFF_PROMISC) {
831 /* Unconditionally log net taps. */
832 net_drv(tp, KERN_NOTICE "%s: Promiscuous mode enabled.\n",
835 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
837 mc_filter[1] = mc_filter[0] = 0xffffffff;
838 } else if ((dev->mc_count > multicast_filter_limit) ||
839 (dev->flags & IFF_ALLMULTI)) {
840 /* Too many to filter perfectly -- accept all multicasts. */
841 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
842 mc_filter[1] = mc_filter[0] = 0xffffffff;
844 struct dev_mc_list *mclist;
847 rx_mode = AcceptBroadcast | AcceptMyPhys;
848 mc_filter[1] = mc_filter[0] = 0;
849 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
850 i++, mclist = mclist->next) {
852 ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
853 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
854 rx_mode |= AcceptMulticast;
858 spin_lock_irqsave(&tp->lock, flags);
860 SIS_W16(RxMacControl, rx_mode | 0x2);
861 SIS_W32(RxHashTable, mc_filter[0]);
862 SIS_W32(RxHashTable + 4, mc_filter[1]);
864 spin_unlock_irqrestore(&tp->lock, flags);
867 static void sis190_soft_reset(void __iomem *ioaddr)
869 SIS_W32(IntrControl, 0x8000);
872 SIS_W32(IntrControl, 0x0);
873 sis190_asic_down(ioaddr);
877 static void sis190_hw_start(struct net_device *dev)
879 struct sis190_private *tp = netdev_priv(dev);
880 void __iomem *ioaddr = tp->mmio_addr;
882 sis190_soft_reset(ioaddr);
884 SIS_W32(TxDescStartAddr, tp->tx_dma);
885 SIS_W32(RxDescStartAddr, tp->rx_dma);
887 SIS_W32(IntrStatus, 0xffffffff);
888 SIS_W32(IntrMask, 0x0);
890 * Default is 100Mbps.
891 * A bit strange: 100Mbps is 0x1801 elsewhere -- FR 2005/06/09
893 SIS_W16(StationControl, 0x1901);
894 SIS_W32(GMIIControl, 0x0);
895 SIS_W32(TxMacControl, 0x60);
896 SIS_W16(RxMacControl, 0x02);
897 SIS_W32(RxHashTable, 0x0);
899 SIS_W32(RxWolCtrl, 0x0);
900 SIS_W32(RxWolData, 0x0);
904 sis190_set_rx_mode(dev);
906 /* Enable all known interrupts by setting the interrupt mask. */
907 SIS_W32(IntrMask, sis190_intr_mask);
909 SIS_W32(TxControl, 0x1a00 | CmdTxEnb);
910 SIS_W32(RxControl, 0x1a1d);
912 netif_start_queue(dev);
915 static void sis190_phy_task(void * data)
917 struct net_device *dev = data;
918 struct sis190_private *tp = netdev_priv(dev);
919 void __iomem *ioaddr = tp->mmio_addr;
920 int phy_id = tp->mii_if.phy_id;
925 val = mdio_read(ioaddr, phy_id, MII_BMCR);
926 if (val & BMCR_RESET) {
927 // FIXME: needlessly high ? -- FR 02/07/2005
928 mod_timer(&tp->timer, jiffies + HZ/10);
929 } else if (!(mdio_read_latched(ioaddr, phy_id, MII_BMSR) &
930 BMSR_ANEGCOMPLETE)) {
931 net_link(tp, KERN_WARNING "%s: PHY reset until link up.\n",
933 netif_carrier_off(dev);
934 mdio_write(ioaddr, phy_id, MII_BMCR, val | BMCR_RESET);
935 mod_timer(&tp->timer, jiffies + SIS190_PHY_TIMEOUT);
943 { LPA_1000XFULL | LPA_SLCT,
944 "1000 Mbps Full Duplex",
946 { LPA_1000XHALF | LPA_SLCT,
947 "1000 Mbps Half Duplex",
950 "100 Mbps Full Duplex",
953 "100 Mbps Half Duplex",
956 "10 Mbps Full Duplex",
959 "10 Mbps Half Duplex",
961 { 0, "unknown", 0x0000 }
965 val = mdio_read(ioaddr, phy_id, 0x1f);
966 net_link(tp, KERN_INFO "%s: mii ext = %04x.\n", dev->name, val);
968 val = mdio_read(ioaddr, phy_id, MII_LPA);
969 adv = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
970 net_link(tp, KERN_INFO "%s: mii lpa = %04x adv = %04x.\n",
971 dev->name, val, adv);
975 for (p = reg31; p->ctl; p++) {
976 if ((val & p->val) == p->val)
980 SIS_W16(StationControl, p->ctl);
981 net_link(tp, KERN_INFO "%s: link on %s mode.\n", dev->name,
983 netif_carrier_on(dev);
989 static void sis190_phy_timer(unsigned long __opaque)
991 struct net_device *dev = (struct net_device *)__opaque;
992 struct sis190_private *tp = netdev_priv(dev);
994 if (likely(netif_running(dev)))
995 schedule_work(&tp->phy_task);
998 static inline void sis190_delete_timer(struct net_device *dev)
1000 struct sis190_private *tp = netdev_priv(dev);
1002 del_timer_sync(&tp->timer);
1005 static inline void sis190_request_timer(struct net_device *dev)
1007 struct sis190_private *tp = netdev_priv(dev);
1008 struct timer_list *timer = &tp->timer;
1011 timer->expires = jiffies + SIS190_PHY_TIMEOUT;
1012 timer->data = (unsigned long)dev;
1013 timer->function = sis190_phy_timer;
1017 static void sis190_set_rxbufsize(struct sis190_private *tp,
1018 struct net_device *dev)
1020 unsigned int mtu = dev->mtu;
1022 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1023 /* RxDesc->size has a licence to kill the lower bits */
1024 if (tp->rx_buf_sz & 0x07) {
1026 tp->rx_buf_sz &= RX_BUF_MASK;
1030 static int sis190_open(struct net_device *dev)
1032 struct sis190_private *tp = netdev_priv(dev);
1033 struct pci_dev *pdev = tp->pci_dev;
1036 sis190_set_rxbufsize(tp, dev);
1039 * Rx and Tx descriptors need 256 bytes alignment.
1040 * pci_alloc_consistent() guarantees a stronger alignment.
1042 tp->TxDescRing = pci_alloc_consistent(pdev, TX_RING_BYTES, &tp->tx_dma);
1043 if (!tp->TxDescRing)
1046 tp->RxDescRing = pci_alloc_consistent(pdev, RX_RING_BYTES, &tp->rx_dma);
1047 if (!tp->RxDescRing)
1050 rc = sis190_init_ring(dev);
1054 INIT_WORK(&tp->phy_task, sis190_phy_task, dev);
1056 sis190_request_timer(dev);
1058 rc = request_irq(dev->irq, sis190_interrupt, SA_SHIRQ, dev->name, dev);
1060 goto err_release_timer_2;
1062 sis190_hw_start(dev);
1066 err_release_timer_2:
1067 sis190_delete_timer(dev);
1068 sis190_rx_clear(tp);
1070 pci_free_consistent(tp->pci_dev, RX_RING_BYTES, tp->RxDescRing,
1073 pci_free_consistent(tp->pci_dev, TX_RING_BYTES, tp->TxDescRing,
1078 static void sis190_tx_clear(struct sis190_private *tp)
1082 for (i = 0; i < NUM_TX_DESC; i++) {
1083 struct sk_buff *skb = tp->Tx_skbuff[i];
1088 sis190_unmap_tx_skb(tp->pci_dev, skb, tp->TxDescRing + i);
1089 tp->Tx_skbuff[i] = NULL;
1092 tp->stats.tx_dropped++;
1094 tp->cur_tx = tp->dirty_tx = 0;
1097 static void sis190_down(struct net_device *dev)
1099 struct sis190_private *tp = netdev_priv(dev);
1100 void __iomem *ioaddr = tp->mmio_addr;
1101 unsigned int poll_locked = 0;
1103 sis190_delete_timer(dev);
1105 netif_stop_queue(dev);
1107 flush_scheduled_work();
1110 spin_lock_irq(&tp->lock);
1112 sis190_asic_down(ioaddr);
1114 spin_unlock_irq(&tp->lock);
1116 synchronize_irq(dev->irq);
1119 netif_poll_disable(dev);
1123 synchronize_sched();
1125 } while (SIS_R32(IntrMask));
1127 sis190_tx_clear(tp);
1128 sis190_rx_clear(tp);
1131 static int sis190_close(struct net_device *dev)
1133 struct sis190_private *tp = netdev_priv(dev);
1134 struct pci_dev *pdev = tp->pci_dev;
1138 free_irq(dev->irq, dev);
1140 netif_poll_enable(dev);
1142 pci_free_consistent(pdev, TX_RING_BYTES, tp->TxDescRing, tp->tx_dma);
1143 pci_free_consistent(pdev, RX_RING_BYTES, tp->RxDescRing, tp->rx_dma);
1145 tp->TxDescRing = NULL;
1146 tp->RxDescRing = NULL;
1151 static int sis190_start_xmit(struct sk_buff *skb, struct net_device *dev)
1153 struct sis190_private *tp = netdev_priv(dev);
1154 void __iomem *ioaddr = tp->mmio_addr;
1155 u32 len, entry, dirty_tx;
1156 struct TxDesc *desc;
1159 if (unlikely(skb->len < ETH_ZLEN)) {
1160 skb = skb_padto(skb, ETH_ZLEN);
1162 tp->stats.tx_dropped++;
1170 entry = tp->cur_tx % NUM_TX_DESC;
1171 desc = tp->TxDescRing + entry;
1173 if (unlikely(le32_to_cpu(desc->status) & OWNbit)) {
1174 netif_stop_queue(dev);
1175 net_tx_err(tp, KERN_ERR PFX
1176 "%s: BUG! Tx Ring full when queue awake!\n",
1178 return NETDEV_TX_BUSY;
1181 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1183 tp->Tx_skbuff[entry] = skb;
1185 desc->PSize = cpu_to_le32(len);
1186 desc->addr = cpu_to_le32(mapping);
1188 desc->size = cpu_to_le32(len);
1189 if (entry == (NUM_TX_DESC - 1))
1190 desc->size |= cpu_to_le32(RingEnd);
1194 desc->status = cpu_to_le32(OWNbit | INTbit | DEFbit | CRCbit | PADbit);
1200 SIS_W32(TxControl, 0x1a00 | CmdReset | CmdTxEnb);
1202 dev->trans_start = jiffies;
1204 dirty_tx = tp->dirty_tx;
1205 if ((tp->cur_tx - NUM_TX_DESC) == dirty_tx) {
1206 netif_stop_queue(dev);
1208 if (dirty_tx != tp->dirty_tx)
1209 netif_wake_queue(dev);
1212 return NETDEV_TX_OK;
1215 static struct net_device_stats *sis190_get_stats(struct net_device *dev)
1217 struct sis190_private *tp = netdev_priv(dev);
1222 static void sis190_free_phy(struct list_head *first_phy)
1224 struct sis190_phy *cur, *next;
1226 list_for_each_entry_safe(cur, next, first_phy, list) {
1232 * sis190_default_phy - Select default PHY for sis190 mac.
1233 * @dev: the net device to probe for
1235 * Select first detected PHY with link as default.
1236 * If no one is link on, select PHY whose types is HOME as default.
1237 * If HOME doesn't exist, select LAN.
1239 static u16 sis190_default_phy(struct net_device *dev)
1241 struct sis190_phy *phy, *phy_home, *phy_default, *phy_lan;
1242 struct sis190_private *tp = netdev_priv(dev);
1243 struct mii_if_info *mii_if = &tp->mii_if;
1244 void __iomem *ioaddr = tp->mmio_addr;
1247 phy_home = phy_default = phy_lan = NULL;
1249 list_for_each_entry(phy, &tp->first_phy, list) {
1250 status = mdio_read_latched(ioaddr, phy->phy_id, MII_BMSR);
1252 // Link ON & Not select default PHY & not ghost PHY.
1253 if ((status & BMSR_LSTATUS) &&
1255 (phy->type != UNKNOWN)) {
1258 status = mdio_read(ioaddr, phy->phy_id, MII_BMCR);
1259 mdio_write(ioaddr, phy->phy_id, MII_BMCR,
1260 status | BMCR_ANENABLE | BMCR_ISOLATE);
1261 if (phy->type == HOME)
1263 else if (phy->type == LAN)
1270 phy_default = phy_home;
1272 phy_default = phy_lan;
1274 phy_default = list_entry(&tp->first_phy,
1275 struct sis190_phy, list);
1278 if (mii_if->phy_id != phy_default->phy_id) {
1279 mii_if->phy_id = phy_default->phy_id;
1280 net_probe(tp, KERN_INFO
1281 "%s: Using transceiver at address %d as default.\n",
1282 pci_name(tp->pci_dev), mii_if->phy_id);
1285 status = mdio_read(ioaddr, mii_if->phy_id, MII_BMCR);
1286 status &= (~BMCR_ISOLATE);
1288 mdio_write(ioaddr, mii_if->phy_id, MII_BMCR, status);
1289 status = mdio_read_latched(ioaddr, mii_if->phy_id, MII_BMSR);
1294 static void sis190_init_phy(struct net_device *dev, struct sis190_private *tp,
1295 struct sis190_phy *phy, unsigned int phy_id,
1298 void __iomem *ioaddr = tp->mmio_addr;
1299 struct mii_chip_info *p;
1301 INIT_LIST_HEAD(&phy->list);
1302 phy->status = mii_status;
1303 phy->phy_id = phy_id;
1305 phy->id[0] = mdio_read(ioaddr, phy_id, MII_PHYSID1);
1306 phy->id[1] = mdio_read(ioaddr, phy_id, MII_PHYSID2);
1308 for (p = mii_chip_table; p->type; p++) {
1309 if ((p->id[0] == phy->id[0]) &&
1310 (p->id[1] == (phy->id[1] & 0xfff0))) {
1316 phy->type = (p->type == MIX) ?
1317 ((mii_status & (BMSR_100FULL | BMSR_100HALF)) ?
1318 LAN : HOME) : p->type;
1319 tp->features |= p->feature;
1321 phy->type = UNKNOWN;
1323 net_probe(tp, KERN_INFO "%s: %s transceiver at address %d.\n",
1324 pci_name(tp->pci_dev),
1325 (phy->type == UNKNOWN) ? "Unknown PHY" : p->name, phy_id);
1328 static void sis190_mii_probe_88e1111_fixup(struct sis190_private *tp)
1330 if (tp->features & F_PHY_88E1111) {
1331 void __iomem *ioaddr = tp->mmio_addr;
1332 int phy_id = tp->mii_if.phy_id;
1338 p = (tp->features & F_HAS_RGMII) ? reg[0] : reg[1];
1340 mdio_write(ioaddr, phy_id, 0x1b, p[0]);
1342 mdio_write(ioaddr, phy_id, 0x14, p[1]);
1348 * sis190_mii_probe - Probe MII PHY for sis190
1349 * @dev: the net device to probe for
1351 * Search for total of 32 possible mii phy addresses.
1352 * Identify and set current phy if found one,
1353 * return error if it failed to found.
1355 static int __devinit sis190_mii_probe(struct net_device *dev)
1357 struct sis190_private *tp = netdev_priv(dev);
1358 struct mii_if_info *mii_if = &tp->mii_if;
1359 void __iomem *ioaddr = tp->mmio_addr;
1363 INIT_LIST_HEAD(&tp->first_phy);
1365 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1366 struct sis190_phy *phy;
1369 status = mdio_read_latched(ioaddr, phy_id, MII_BMSR);
1371 // Try next mii if the current one is not accessible.
1372 if (status == 0xffff || status == 0x0000)
1375 phy = kmalloc(sizeof(*phy), GFP_KERNEL);
1377 sis190_free_phy(&tp->first_phy);
1382 sis190_init_phy(dev, tp, phy, phy_id, status);
1384 list_add(&tp->first_phy, &phy->list);
1387 if (list_empty(&tp->first_phy)) {
1388 net_probe(tp, KERN_INFO "%s: No MII transceivers found!\n",
1389 pci_name(tp->pci_dev));
1394 /* Select default PHY for mac */
1395 sis190_default_phy(dev);
1397 sis190_mii_probe_88e1111_fixup(tp);
1400 mii_if->mdio_read = __mdio_read;
1401 mii_if->mdio_write = __mdio_write;
1402 mii_if->phy_id_mask = PHY_ID_ANY;
1403 mii_if->reg_num_mask = MII_REG_ANY;
1408 static void __devexit sis190_mii_remove(struct net_device *dev)
1410 struct sis190_private *tp = netdev_priv(dev);
1412 sis190_free_phy(&tp->first_phy);
1415 static void sis190_release_board(struct pci_dev *pdev)
1417 struct net_device *dev = pci_get_drvdata(pdev);
1418 struct sis190_private *tp = netdev_priv(dev);
1420 iounmap(tp->mmio_addr);
1421 pci_release_regions(pdev);
1422 pci_disable_device(pdev);
1426 static struct net_device * __devinit sis190_init_board(struct pci_dev *pdev)
1428 struct sis190_private *tp;
1429 struct net_device *dev;
1430 void __iomem *ioaddr;
1433 dev = alloc_etherdev(sizeof(*tp));
1435 net_drv(&debug, KERN_ERR PFX "unable to alloc new ethernet\n");
1440 SET_MODULE_OWNER(dev);
1441 SET_NETDEV_DEV(dev, &pdev->dev);
1443 tp = netdev_priv(dev);
1444 tp->msg_enable = netif_msg_init(debug.msg_enable, SIS190_MSG_DEFAULT);
1446 rc = pci_enable_device(pdev);
1448 net_probe(tp, KERN_ERR "%s: enable failure\n", pci_name(pdev));
1449 goto err_free_dev_1;
1454 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1455 net_probe(tp, KERN_ERR "%s: region #0 is no MMIO resource.\n",
1457 goto err_pci_disable_2;
1459 if (pci_resource_len(pdev, 0) < SIS190_REGS_SIZE) {
1460 net_probe(tp, KERN_ERR "%s: invalid PCI region size(s).\n",
1462 goto err_pci_disable_2;
1465 rc = pci_request_regions(pdev, DRV_NAME);
1467 net_probe(tp, KERN_ERR PFX "%s: could not request regions.\n",
1469 goto err_pci_disable_2;
1472 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1474 net_probe(tp, KERN_ERR "%s: DMA configuration failed.\n",
1476 goto err_free_res_3;
1479 pci_set_master(pdev);
1481 ioaddr = ioremap(pci_resource_start(pdev, 0), SIS190_REGS_SIZE);
1483 net_probe(tp, KERN_ERR "%s: cannot remap MMIO, aborting\n",
1486 goto err_free_res_3;
1490 tp->mmio_addr = ioaddr;
1492 sis190_irq_mask_and_ack(ioaddr);
1494 sis190_soft_reset(ioaddr);
1499 pci_release_regions(pdev);
1501 pci_disable_device(pdev);
1509 static void sis190_tx_timeout(struct net_device *dev)
1511 struct sis190_private *tp = netdev_priv(dev);
1512 void __iomem *ioaddr = tp->mmio_addr;
1515 /* Disable Tx, if not already */
1516 tmp8 = SIS_R8(TxControl);
1517 if (tmp8 & CmdTxEnb)
1518 SIS_W8(TxControl, tmp8 & ~CmdTxEnb);
1521 net_tx_err(tp, KERN_INFO "%s: Transmit timeout, status %08x %08x.\n",
1522 dev->name, SIS_R32(TxControl), SIS_R32(TxSts));
1524 /* Disable interrupts by clearing the interrupt mask. */
1525 SIS_W32(IntrMask, 0x0000);
1527 /* Stop a shared interrupt from scavenging while we are. */
1528 spin_lock_irq(&tp->lock);
1529 sis190_tx_clear(tp);
1530 spin_unlock_irq(&tp->lock);
1532 /* ...and finally, reset everything. */
1533 sis190_hw_start(dev);
1535 netif_wake_queue(dev);
1538 static void sis190_set_rgmii(struct sis190_private *tp, u8 reg)
1540 tp->features |= (reg & 0x80) ? F_HAS_RGMII : 0;
1543 static int __devinit sis190_get_mac_addr_from_eeprom(struct pci_dev *pdev,
1544 struct net_device *dev)
1546 struct sis190_private *tp = netdev_priv(dev);
1547 void __iomem *ioaddr = tp->mmio_addr;
1551 net_probe(tp, KERN_INFO "%s: Read MAC address from EEPROM\n",
1554 /* Check to see if there is a sane EEPROM */
1555 sig = (u16) sis190_read_eeprom(ioaddr, EEPROMSignature);
1557 if ((sig == 0xffff) || (sig == 0x0000)) {
1558 net_probe(tp, KERN_INFO "%s: Error EEPROM read %x.\n",
1559 pci_name(pdev), sig);
1563 /* Get MAC address from EEPROM */
1564 for (i = 0; i < MAC_ADDR_LEN / 2; i++) {
1565 __le16 w = sis190_read_eeprom(ioaddr, EEPROMMACAddr + i);
1567 ((u16 *)dev->dev_addr)[0] = le16_to_cpu(w);
1570 sis190_set_rgmii(tp, sis190_read_eeprom(ioaddr, EEPROMInfo));
1576 * sis190_get_mac_addr_from_apc - Get MAC address for SiS965 model
1578 * @dev: network device to get address for
1580 * SiS965 model, use APC CMOS RAM to store MAC address.
1581 * APC CMOS RAM is accessed through ISA bridge.
1582 * MAC address is read into @net_dev->dev_addr.
1584 static int __devinit sis190_get_mac_addr_from_apc(struct pci_dev *pdev,
1585 struct net_device *dev)
1587 struct sis190_private *tp = netdev_priv(dev);
1588 struct pci_dev *isa_bridge;
1592 net_probe(tp, KERN_INFO "%s: Read MAC address from APC.\n",
1595 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0965, NULL);
1597 net_probe(tp, KERN_INFO "%s: Can not find ISA bridge.\n",
1602 /* Enable port 78h & 79h to access APC Registers. */
1603 pci_read_config_byte(isa_bridge, 0x48, &tmp8);
1604 reg = (tmp8 & ~0x02);
1605 pci_write_config_byte(isa_bridge, 0x48, reg);
1607 pci_read_config_byte(isa_bridge, 0x48, ®);
1609 for (i = 0; i < MAC_ADDR_LEN; i++) {
1610 outb(0x9 + i, 0x78);
1611 dev->dev_addr[i] = inb(0x79);
1617 sis190_set_rgmii(tp, reg);
1619 /* Restore the value to ISA Bridge */
1620 pci_write_config_byte(isa_bridge, 0x48, tmp8);
1621 pci_dev_put(isa_bridge);
1627 * sis190_init_rxfilter - Initialize the Rx filter
1628 * @dev: network device to initialize
1630 * Set receive filter address to our MAC address
1631 * and enable packet filtering.
1633 static inline void sis190_init_rxfilter(struct net_device *dev)
1635 struct sis190_private *tp = netdev_priv(dev);
1636 void __iomem *ioaddr = tp->mmio_addr;
1640 ctl = SIS_R16(RxMacControl);
1642 * Disable packet filtering before setting filter.
1643 * Note: SiS's driver writes 32 bits but RxMacControl is 16 bits
1644 * only and followed by RxMacAddr (6 bytes). Strange. -- FR
1646 SIS_W16(RxMacControl, ctl & ~0x0f00);
1648 for (i = 0; i < MAC_ADDR_LEN; i++)
1649 SIS_W8(RxMacAddr + i, dev->dev_addr[i]);
1651 SIS_W16(RxMacControl, ctl);
1655 static int sis190_get_mac_addr(struct pci_dev *pdev, struct net_device *dev)
1659 pci_read_config_byte(pdev, 0x73, &from);
1661 return (from & 0x00000001) ?
1662 sis190_get_mac_addr_from_apc(pdev, dev) :
1663 sis190_get_mac_addr_from_eeprom(pdev, dev);
1666 static void sis190_set_speed_auto(struct net_device *dev)
1668 struct sis190_private *tp = netdev_priv(dev);
1669 void __iomem *ioaddr = tp->mmio_addr;
1670 int phy_id = tp->mii_if.phy_id;
1673 net_link(tp, KERN_INFO "%s: Enabling Auto-negotiation.\n", dev->name);
1675 val = mdio_read(ioaddr, phy_id, MII_ADVERTISE);
1677 // Enable 10/100 Full/Half Mode, leave MII_ADVERTISE bit4:0
1679 mdio_write(ioaddr, phy_id, MII_ADVERTISE, (val & ADVERTISE_SLCT) |
1680 ADVERTISE_100FULL | ADVERTISE_10FULL |
1681 ADVERTISE_100HALF | ADVERTISE_10HALF);
1683 // Enable 1000 Full Mode.
1684 mdio_write(ioaddr, phy_id, MII_CTRL1000, ADVERTISE_1000FULL);
1686 // Enable auto-negotiation and restart auto-negotiation.
1687 mdio_write(ioaddr, phy_id, MII_BMCR,
1688 BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET);
1691 static int sis190_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1693 struct sis190_private *tp = netdev_priv(dev);
1695 return mii_ethtool_gset(&tp->mii_if, cmd);
1698 static int sis190_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1700 struct sis190_private *tp = netdev_priv(dev);
1702 return mii_ethtool_sset(&tp->mii_if, cmd);
1705 static void sis190_get_drvinfo(struct net_device *dev,
1706 struct ethtool_drvinfo *info)
1708 struct sis190_private *tp = netdev_priv(dev);
1710 strcpy(info->driver, DRV_NAME);
1711 strcpy(info->version, DRV_VERSION);
1712 strcpy(info->bus_info, pci_name(tp->pci_dev));
1715 static int sis190_get_regs_len(struct net_device *dev)
1717 return SIS190_REGS_SIZE;
1720 static void sis190_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1723 struct sis190_private *tp = netdev_priv(dev);
1724 unsigned long flags;
1726 if (regs->len > SIS190_REGS_SIZE)
1727 regs->len = SIS190_REGS_SIZE;
1729 spin_lock_irqsave(&tp->lock, flags);
1730 memcpy_fromio(p, tp->mmio_addr, regs->len);
1731 spin_unlock_irqrestore(&tp->lock, flags);
1734 static int sis190_nway_reset(struct net_device *dev)
1736 struct sis190_private *tp = netdev_priv(dev);
1738 return mii_nway_restart(&tp->mii_if);
1741 static u32 sis190_get_msglevel(struct net_device *dev)
1743 struct sis190_private *tp = netdev_priv(dev);
1745 return tp->msg_enable;
1748 static void sis190_set_msglevel(struct net_device *dev, u32 value)
1750 struct sis190_private *tp = netdev_priv(dev);
1752 tp->msg_enable = value;
1755 static struct ethtool_ops sis190_ethtool_ops = {
1756 .get_settings = sis190_get_settings,
1757 .set_settings = sis190_set_settings,
1758 .get_drvinfo = sis190_get_drvinfo,
1759 .get_regs_len = sis190_get_regs_len,
1760 .get_regs = sis190_get_regs,
1761 .get_link = ethtool_op_get_link,
1762 .get_msglevel = sis190_get_msglevel,
1763 .set_msglevel = sis190_set_msglevel,
1764 .nway_reset = sis190_nway_reset,
1767 static int sis190_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1769 struct sis190_private *tp = netdev_priv(dev);
1771 return !netif_running(dev) ? -EINVAL :
1772 generic_mii_ioctl(&tp->mii_if, if_mii(ifr), cmd, NULL);
1775 static int __devinit sis190_init_one(struct pci_dev *pdev,
1776 const struct pci_device_id *ent)
1778 static int printed_version = 0;
1779 struct sis190_private *tp;
1780 struct net_device *dev;
1781 void __iomem *ioaddr;
1784 if (!printed_version) {
1785 net_drv(&debug, KERN_INFO SIS190_DRIVER_NAME " loaded.\n");
1786 printed_version = 1;
1789 dev = sis190_init_board(pdev);
1795 tp = netdev_priv(dev);
1796 ioaddr = tp->mmio_addr;
1798 rc = sis190_get_mac_addr(pdev, dev);
1800 goto err_release_board;
1802 sis190_init_rxfilter(dev);
1804 INIT_WORK(&tp->phy_task, sis190_phy_task, dev);
1806 dev->open = sis190_open;
1807 dev->stop = sis190_close;
1808 dev->do_ioctl = sis190_ioctl;
1809 dev->get_stats = sis190_get_stats;
1810 dev->tx_timeout = sis190_tx_timeout;
1811 dev->watchdog_timeo = SIS190_TX_TIMEOUT;
1812 dev->hard_start_xmit = sis190_start_xmit;
1813 #ifdef CONFIG_NET_POLL_CONTROLLER
1814 dev->poll_controller = sis190_netpoll;
1816 dev->set_multicast_list = sis190_set_rx_mode;
1817 SET_ETHTOOL_OPS(dev, &sis190_ethtool_ops);
1818 dev->irq = pdev->irq;
1819 dev->base_addr = (unsigned long) 0xdead;
1821 spin_lock_init(&tp->lock);
1823 rc = sis190_mii_probe(dev);
1825 goto err_release_board;
1827 rc = register_netdev(dev);
1829 goto err_remove_mii;
1831 pci_set_drvdata(pdev, dev);
1833 net_probe(tp, KERN_INFO "%s: %s at %p (IRQ: %d), "
1834 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x\n",
1835 pci_name(pdev), sis_chip_info[ent->driver_data].name,
1837 dev->dev_addr[0], dev->dev_addr[1],
1838 dev->dev_addr[2], dev->dev_addr[3],
1839 dev->dev_addr[4], dev->dev_addr[5]);
1841 net_probe(tp, KERN_INFO "%s: %s mode.\n", dev->name,
1842 (tp->features & F_HAS_RGMII) ? "RGMII" : "GMII");
1844 netif_carrier_off(dev);
1846 sis190_set_speed_auto(dev);
1851 sis190_mii_remove(dev);
1853 sis190_release_board(pdev);
1857 static void __devexit sis190_remove_one(struct pci_dev *pdev)
1859 struct net_device *dev = pci_get_drvdata(pdev);
1861 sis190_mii_remove(dev);
1862 unregister_netdev(dev);
1863 sis190_release_board(pdev);
1864 pci_set_drvdata(pdev, NULL);
1867 static struct pci_driver sis190_pci_driver = {
1869 .id_table = sis190_pci_tbl,
1870 .probe = sis190_init_one,
1871 .remove = __devexit_p(sis190_remove_one),
1874 static int __init sis190_init_module(void)
1876 return pci_module_init(&sis190_pci_driver);
1879 static void __exit sis190_cleanup_module(void)
1881 pci_unregister_driver(&sis190_pci_driver);
1884 module_init(sis190_init_module);
1885 module_exit(sis190_cleanup_module);