1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/delay.h>
12 #include "net_driver.h"
15 #include "falcon_hwdefs.h"
16 #include "falcon_io.h"
22 #include "workarounds.h"
24 /**************************************************************************
28 **************************************************************************/
30 /* Offset of an XMAC register within Falcon */
31 #define FALCON_XMAC_REG(mac_reg) \
32 (FALCON_XMAC_REGBANK + ((mac_reg) * FALCON_XMAC_REG_SIZE))
34 void falcon_xmac_writel(struct efx_nic *efx,
35 efx_dword_t *value, unsigned int mac_reg)
39 EFX_POPULATE_OWORD_1(temp, MAC_DATA, EFX_DWORD_FIELD(*value, MAC_DATA));
40 falcon_write(efx, &temp, FALCON_XMAC_REG(mac_reg));
43 void falcon_xmac_readl(struct efx_nic *efx,
44 efx_dword_t *value, unsigned int mac_reg)
48 falcon_read(efx, &temp, FALCON_XMAC_REG(mac_reg));
49 EFX_POPULATE_DWORD_1(*value, MAC_DATA, EFX_OWORD_FIELD(temp, MAC_DATA));
52 /**************************************************************************
56 *************************************************************************/
57 static int falcon_reset_xmac(struct efx_nic *efx)
62 EFX_POPULATE_DWORD_1(reg, XM_CORE_RST, 1);
63 falcon_xmac_writel(efx, ®, XM_GLB_CFG_REG_MAC);
65 for (count = 0; count < 10000; count++) { /* wait upto 100ms */
66 falcon_xmac_readl(efx, ®, XM_GLB_CFG_REG_MAC);
67 if (EFX_DWORD_FIELD(reg, XM_CORE_RST) == 0)
72 /* This often fails when DSP is disabled, ignore it */
73 if (sfe4001_phy_flash_cfg)
76 EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
80 /* Configure the XAUI driver that is an output from Falcon */
81 static void falcon_setup_xaui(struct efx_nic *efx)
83 efx_dword_t sdctl, txdrv;
85 /* Move the XAUI into low power, unless there is no PHY, in
86 * which case the XAUI will have to drive a cable. */
87 if (efx->phy_type == PHY_TYPE_NONE)
90 falcon_xmac_readl(efx, &sdctl, XX_SD_CTL_REG_MAC);
91 EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT);
92 EFX_SET_DWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT);
93 EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT);
94 EFX_SET_DWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT);
95 EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT);
96 EFX_SET_DWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT);
97 EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT);
98 EFX_SET_DWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT);
99 falcon_xmac_writel(efx, &sdctl, XX_SD_CTL_REG_MAC);
101 EFX_POPULATE_DWORD_8(txdrv,
102 XX_DEQD, XX_TXDRV_DEQ_DEFAULT,
103 XX_DEQC, XX_TXDRV_DEQ_DEFAULT,
104 XX_DEQB, XX_TXDRV_DEQ_DEFAULT,
105 XX_DEQA, XX_TXDRV_DEQ_DEFAULT,
106 XX_DTXD, XX_TXDRV_DTX_DEFAULT,
107 XX_DTXC, XX_TXDRV_DTX_DEFAULT,
108 XX_DTXB, XX_TXDRV_DTX_DEFAULT,
109 XX_DTXA, XX_TXDRV_DTX_DEFAULT);
110 falcon_xmac_writel(efx, &txdrv, XX_TXDRV_CTL_REG_MAC);
113 static void falcon_hold_xaui_in_rst(struct efx_nic *efx)
118 EFX_SET_DWORD_FIELD(reg, XX_PWRDNA_EN, 1);
119 EFX_SET_DWORD_FIELD(reg, XX_PWRDNB_EN, 1);
120 EFX_SET_DWORD_FIELD(reg, XX_PWRDNC_EN, 1);
121 EFX_SET_DWORD_FIELD(reg, XX_PWRDND_EN, 1);
122 EFX_SET_DWORD_FIELD(reg, XX_RSTPLLAB_EN, 1);
123 EFX_SET_DWORD_FIELD(reg, XX_RSTPLLCD_EN, 1);
124 EFX_SET_DWORD_FIELD(reg, XX_RESETA_EN, 1);
125 EFX_SET_DWORD_FIELD(reg, XX_RESETB_EN, 1);
126 EFX_SET_DWORD_FIELD(reg, XX_RESETC_EN, 1);
127 EFX_SET_DWORD_FIELD(reg, XX_RESETD_EN, 1);
128 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSRX_EN, 1);
129 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSTX_EN, 1);
130 falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
134 static int _falcon_reset_xaui_a(struct efx_nic *efx)
138 falcon_hold_xaui_in_rst(efx);
139 falcon_xmac_readl(efx, ®, XX_PWR_RST_REG_MAC);
141 /* Follow the RAMBUS XAUI data reset sequencing
142 * Channels A and B first: power down, reset PLL, reset, clear
144 EFX_SET_DWORD_FIELD(reg, XX_PWRDNA_EN, 0);
145 EFX_SET_DWORD_FIELD(reg, XX_PWRDNB_EN, 0);
146 falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
149 EFX_SET_DWORD_FIELD(reg, XX_RSTPLLAB_EN, 0);
150 falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
153 EFX_SET_DWORD_FIELD(reg, XX_RESETA_EN, 0);
154 EFX_SET_DWORD_FIELD(reg, XX_RESETB_EN, 0);
155 falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
158 /* Channels C and D: power down, reset PLL, reset, clear */
159 EFX_SET_DWORD_FIELD(reg, XX_PWRDNC_EN, 0);
160 EFX_SET_DWORD_FIELD(reg, XX_PWRDND_EN, 0);
161 falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
164 EFX_SET_DWORD_FIELD(reg, XX_RSTPLLCD_EN, 0);
165 falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
168 EFX_SET_DWORD_FIELD(reg, XX_RESETC_EN, 0);
169 EFX_SET_DWORD_FIELD(reg, XX_RESETD_EN, 0);
170 falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
174 falcon_setup_xaui(efx);
177 /* Take XGXS out of reset */
179 falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
185 static int _falcon_reset_xaui_b(struct efx_nic *efx)
190 EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1);
191 falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
193 /* Give some time for the link to establish */
194 for (count = 0; count < 1000; count++) { /* wait upto 10ms */
195 falcon_xmac_readl(efx, ®, XX_PWR_RST_REG_MAC);
196 if (EFX_DWORD_FIELD(reg, XX_RST_XX_EN) == 0) {
197 falcon_setup_xaui(efx);
202 EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n");
206 int falcon_reset_xaui(struct efx_nic *efx)
210 if (EFX_WORKAROUND_9388(efx)) {
211 falcon_hold_xaui_in_rst(efx);
212 efx->phy_op->reset_xaui(efx);
213 rc = _falcon_reset_xaui_a(efx);
215 rc = _falcon_reset_xaui_b(efx);
220 static bool falcon_xgmii_status(struct efx_nic *efx)
224 if (falcon_rev(efx) < FALCON_REV_B0)
227 /* The ISR latches, so clear it and re-read */
228 falcon_xmac_readl(efx, ®, XM_MGT_INT_REG_MAC_B0);
229 falcon_xmac_readl(efx, ®, XM_MGT_INT_REG_MAC_B0);
231 if (EFX_DWORD_FIELD(reg, XM_LCLFLT) ||
232 EFX_DWORD_FIELD(reg, XM_RMTFLT)) {
233 EFX_INFO(efx, "MGT_INT: "EFX_DWORD_FMT"\n", EFX_DWORD_VAL(reg));
240 static void falcon_mask_status_intr(struct efx_nic *efx, bool enable)
244 if ((falcon_rev(efx) < FALCON_REV_B0) || LOOPBACK_INTERNAL(efx))
249 falcon_xmac_readl(efx, ®, XM_MGT_INT_REG_MAC_B0);
251 EFX_POPULATE_DWORD_2(reg,
252 XM_MSK_RMTFLT, !enable,
253 XM_MSK_LCLFLT, !enable);
254 falcon_xmac_writel(efx, ®, XM_MGT_INT_MSK_REG_MAC_B0);
257 int falcon_init_xmac(struct efx_nic *efx)
261 /* Initialize the PHY first so the clock is around */
262 rc = efx->phy_op->init(efx);
266 rc = falcon_reset_xaui(efx);
270 /* Wait again. Give the PHY and MAC time to come back */
271 schedule_timeout_uninterruptible(HZ / 10);
273 rc = falcon_reset_xmac(efx);
277 falcon_mask_status_intr(efx, true);
281 efx->phy_op->fini(efx);
286 bool falcon_xaui_link_ok(struct efx_nic *efx)
289 bool align_done, link_ok = false;
292 if (LOOPBACK_INTERNAL(efx))
295 /* Read link status */
296 falcon_xmac_readl(efx, ®, XX_CORE_STAT_REG_MAC);
298 align_done = EFX_DWORD_FIELD(reg, XX_ALIGN_DONE);
299 sync_status = EFX_DWORD_FIELD(reg, XX_SYNC_STAT);
300 if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED))
303 /* Clear link status ready for next read */
304 EFX_SET_DWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET);
305 EFX_SET_DWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET);
306 EFX_SET_DWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET);
307 falcon_xmac_writel(efx, ®, XX_CORE_STAT_REG_MAC);
309 /* If the link is up, then check the phy side of the xaui link
310 * (error conditions from the wire side propoagate back through
311 * the phy to the xaui side). */
312 if (efx->link_up && link_ok) {
313 if (efx->phy_op->mmds & (1 << MDIO_MMD_PHYXS))
314 link_ok = mdio_clause45_phyxgxs_lane_sync(efx);
317 /* If the PHY and XAUI links are up, then check the mac's xgmii
319 if (efx->link_up && link_ok)
320 link_ok = falcon_xgmii_status(efx);
325 static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
327 unsigned int max_frame_len;
329 bool rx_fc = !!(efx->flow_control & EFX_FC_RX);
331 /* Configure MAC - cut-thru mode is hard wired on */
332 EFX_POPULATE_DWORD_3(reg,
336 falcon_xmac_writel(efx, ®, XM_GLB_CFG_REG_MAC);
339 EFX_POPULATE_DWORD_6(reg,
346 falcon_xmac_writel(efx, ®, XM_TX_CFG_REG_MAC);
349 EFX_POPULATE_DWORD_5(reg,
352 XM_ACPT_ALL_MCAST, 1,
353 XM_ACPT_ALL_UCAST, efx->promiscuous,
355 falcon_xmac_writel(efx, ®, XM_RX_CFG_REG_MAC);
357 /* Set frame length */
358 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
359 EFX_POPULATE_DWORD_1(reg, XM_MAX_RX_FRM_SIZE, max_frame_len);
360 falcon_xmac_writel(efx, ®, XM_RX_PARAM_REG_MAC);
361 EFX_POPULATE_DWORD_2(reg,
362 XM_MAX_TX_FRM_SIZE, max_frame_len,
363 XM_TX_JUMBO_MODE, 1);
364 falcon_xmac_writel(efx, ®, XM_TX_PARAM_REG_MAC);
366 EFX_POPULATE_DWORD_2(reg,
367 XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
368 XM_DIS_FCNTL, !rx_fc);
369 falcon_xmac_writel(efx, ®, XM_FC_REG_MAC);
371 /* Set MAC address */
372 EFX_POPULATE_DWORD_4(reg,
373 XM_ADR_0, efx->net_dev->dev_addr[0],
374 XM_ADR_1, efx->net_dev->dev_addr[1],
375 XM_ADR_2, efx->net_dev->dev_addr[2],
376 XM_ADR_3, efx->net_dev->dev_addr[3]);
377 falcon_xmac_writel(efx, ®, XM_ADR_LO_REG_MAC);
378 EFX_POPULATE_DWORD_2(reg,
379 XM_ADR_4, efx->net_dev->dev_addr[4],
380 XM_ADR_5, efx->net_dev->dev_addr[5]);
381 falcon_xmac_writel(efx, ®, XM_ADR_HI_REG_MAC);
384 static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
387 bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
388 bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
389 bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
391 /* XGXS block is flaky and will need to be reset if moving
392 * into our out of XGMII, XGXS or XAUI loopbacks. */
393 if (EFX_WORKAROUND_5147(efx)) {
394 bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
397 falcon_xmac_readl(efx, ®, XX_CORE_STAT_REG_MAC);
398 old_xgxs_loopback = EFX_DWORD_FIELD(reg, XX_XGXS_LB_EN);
399 old_xgmii_loopback = EFX_DWORD_FIELD(reg, XX_XGMII_LB_EN);
401 falcon_xmac_readl(efx, ®, XX_SD_CTL_REG_MAC);
402 old_xaui_loopback = EFX_DWORD_FIELD(reg, XX_LPBKA);
404 /* The PHY driver may have turned XAUI off */
405 reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
406 (xaui_loopback != old_xaui_loopback) ||
407 (xgmii_loopback != old_xgmii_loopback));
409 falcon_xmac_readl(efx, ®, XX_PWR_RST_REG_MAC);
410 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSTX_EN, 1);
411 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSRX_EN, 1);
412 falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
414 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSTX_EN, 0);
415 EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSRX_EN, 0);
416 falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
421 falcon_xmac_readl(efx, ®, XX_CORE_STAT_REG_MAC);
422 EFX_SET_DWORD_FIELD(reg, XX_FORCE_SIG,
423 (xgxs_loopback || xaui_loopback) ?
424 XX_FORCE_SIG_DECODE_FORCED : 0);
425 EFX_SET_DWORD_FIELD(reg, XX_XGXS_LB_EN, xgxs_loopback);
426 EFX_SET_DWORD_FIELD(reg, XX_XGMII_LB_EN, xgmii_loopback);
427 falcon_xmac_writel(efx, ®, XX_CORE_STAT_REG_MAC);
429 falcon_xmac_readl(efx, ®, XX_SD_CTL_REG_MAC);
430 EFX_SET_DWORD_FIELD(reg, XX_LPBKD, xaui_loopback);
431 EFX_SET_DWORD_FIELD(reg, XX_LPBKC, xaui_loopback);
432 EFX_SET_DWORD_FIELD(reg, XX_LPBKB, xaui_loopback);
433 EFX_SET_DWORD_FIELD(reg, XX_LPBKA, xaui_loopback);
434 falcon_xmac_writel(efx, ®, XX_SD_CTL_REG_MAC);
438 /* Try and bring the Falcon side of the Falcon-Phy XAUI link fails
439 * to come back up. Bash it until it comes back up */
440 static bool falcon_check_xaui_link_up(struct efx_nic *efx)
442 int max_tries, tries;
443 tries = EFX_WORKAROUND_5147(efx) ? 5 : 1;
446 if ((efx->loopback_mode == LOOPBACK_NETWORK) ||
447 (efx->phy_type == PHY_TYPE_NONE))
451 if (falcon_xaui_link_ok(efx))
454 EFX_LOG(efx, "%s Clobbering XAUI (%d tries left).\n",
456 falcon_reset_xaui(efx);
461 EFX_LOG(efx, "Failed to bring XAUI link back up in %d tries!\n",
466 void falcon_reconfigure_xmac(struct efx_nic *efx)
470 falcon_mask_status_intr(efx, false);
472 falcon_deconfigure_mac_wrapper(efx);
474 efx->tx_disabled = LOOPBACK_INTERNAL(efx);
475 efx->phy_op->reconfigure(efx);
477 falcon_reconfigure_xgxs_core(efx);
478 falcon_reconfigure_xmac_core(efx);
480 falcon_reconfigure_mac_wrapper(efx);
482 /* Ensure XAUI link is up */
483 xaui_link_ok = falcon_check_xaui_link_up(efx);
485 if (xaui_link_ok && efx->link_up)
486 falcon_mask_status_intr(efx, true);
489 void falcon_fini_xmac(struct efx_nic *efx)
491 /* Isolate the MAC - PHY */
492 falcon_deconfigure_mac_wrapper(efx);
494 /* Potentially power down the PHY */
495 efx->phy_op->fini(efx);
498 void falcon_update_stats_xmac(struct efx_nic *efx)
500 struct efx_mac_stats *mac_stats = &efx->mac_stats;
503 rc = falcon_dma_stats(efx, XgDmaDone_offset);
507 /* Update MAC stats from DMAed values */
508 FALCON_STAT(efx, XgRxOctets, rx_bytes);
509 FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
510 FALCON_STAT(efx, XgRxPkts, rx_packets);
511 FALCON_STAT(efx, XgRxPktsOK, rx_good);
512 FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
513 FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
514 FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
515 FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
516 FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
517 FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
518 FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
519 FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
520 FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
521 FALCON_STAT(efx, XgRxAlignError, rx_align_error);
522 FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
523 FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
524 FALCON_STAT(efx, XgRxControlPkts, rx_control);
525 FALCON_STAT(efx, XgRxPausePkts, rx_pause);
526 FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
527 FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
528 FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
529 FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
530 FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
531 FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
532 FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
533 FALCON_STAT(efx, XgRxLengthError, rx_length_error);
534 FALCON_STAT(efx, XgTxPkts, tx_packets);
535 FALCON_STAT(efx, XgTxOctets, tx_bytes);
536 FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
537 FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
538 FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
539 FALCON_STAT(efx, XgTxControlPkts, tx_control);
540 FALCON_STAT(efx, XgTxPausePkts, tx_pause);
541 FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
542 FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
543 FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
544 FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
545 FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
546 FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
547 FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
548 FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
549 FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
550 FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
551 FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
552 FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
554 /* Update derived statistics */
555 mac_stats->tx_good_bytes =
556 (mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
557 mac_stats->tx_control * 64);
558 mac_stats->rx_bad_bytes =
559 (mac_stats->rx_bytes - mac_stats->rx_good_bytes -
560 mac_stats->rx_control * 64);
563 int falcon_check_xmac(struct efx_nic *efx)
568 if ((efx->loopback_mode == LOOPBACK_NETWORK) ||
569 (efx->phy_type == PHY_TYPE_NONE))
572 falcon_mask_status_intr(efx, false);
573 xaui_link_ok = falcon_xaui_link_ok(efx);
575 if (EFX_WORKAROUND_5147(efx) && !xaui_link_ok)
576 falcon_reset_xaui(efx);
578 /* Call the PHY check_hw routine */
579 rc = efx->phy_op->check_hw(efx);
581 /* Unmask interrupt if everything was (and still is) ok */
582 if (xaui_link_ok && efx->link_up)
583 falcon_mask_status_intr(efx, true);
588 /* Simulate a PHY event */
589 void falcon_xmac_sim_phy_event(struct efx_nic *efx)
591 efx_qword_t phy_event;
593 EFX_POPULATE_QWORD_2(phy_event,
594 EV_CODE, GLOBAL_EV_DECODE,
596 falcon_generate_event(&efx->channel[0], &phy_event);
599 int falcon_xmac_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
601 mdio_clause45_get_settings(efx, ecmd);
602 ecmd->transceiver = XCVR_INTERNAL;
603 ecmd->phy_address = efx->mii.phy_id;
604 ecmd->autoneg = AUTONEG_DISABLE;
605 ecmd->duplex = DUPLEX_FULL;
609 int falcon_xmac_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
611 if (ecmd->transceiver != XCVR_INTERNAL)
613 if (ecmd->autoneg != AUTONEG_DISABLE)
615 if (ecmd->duplex != DUPLEX_FULL)
618 return mdio_clause45_set_settings(efx, ecmd);
622 int falcon_xmac_set_pause(struct efx_nic *efx, enum efx_fc_type flow_control)
626 if (flow_control & EFX_FC_AUTO) {
627 EFX_LOG(efx, "10G does not support flow control "
628 "autonegotiation\n");
632 if ((flow_control & EFX_FC_TX) && !(flow_control & EFX_FC_RX))
635 /* TX flow control may automatically turn itself off if the
636 * link partner (intermittently) stops responding to pause
637 * frames. There isn't any indication that this has happened,
638 * so the best we do is leave it up to the user to spot this
639 * and fix it be cycling transmit flow control on this end. */
640 reset = ((flow_control & EFX_FC_TX) &&
641 !(efx->flow_control & EFX_FC_TX));
642 if (EFX_WORKAROUND_11482(efx) && reset) {
643 if (falcon_rev(efx) >= FALCON_REV_B0) {
644 /* Recover by resetting the EM block */
646 falcon_drain_tx_fifo(efx);
648 /* Schedule a reset to recover */
649 efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
653 efx->flow_control = flow_control;