1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/i2c-algo-bit.h>
18 #include "net_driver.h"
25 #include "falcon_hwdefs.h"
26 #include "falcon_io.h"
30 #include "workarounds.h"
32 /* Falcon hardware control.
33 * Falcon is the internal codename for the SFC4000 controller that is
34 * present in SFE400X evaluation boards
38 * struct falcon_nic_data - Falcon NIC state
39 * @next_buffer_table: First available buffer table id
40 * @pci_dev2: The secondary PCI device if present
41 * @i2c_data: Operations and state for I2C bit-bashing algorithm
43 struct falcon_nic_data {
44 unsigned next_buffer_table;
45 struct pci_dev *pci_dev2;
46 struct i2c_algo_bit_data i2c_data;
49 /**************************************************************************
53 **************************************************************************
56 static int disable_dma_stats;
58 /* This is set to 16 for a good reason. In summary, if larger than
59 * 16, the descriptor cache holds more than a default socket
60 * buffer's worth of packets (for UDP we can only have at most one
61 * socket buffer's worth outstanding). This combined with the fact
62 * that we only get 1 TX event per descriptor cache means the NIC
65 #define TX_DC_ENTRIES 16
66 #define TX_DC_ENTRIES_ORDER 0
67 #define TX_DC_BASE 0x130000
69 #define RX_DC_ENTRIES 64
70 #define RX_DC_ENTRIES_ORDER 2
71 #define RX_DC_BASE 0x100000
73 /* RX FIFO XOFF watermark
75 * When the amount of the RX FIFO increases used increases past this
76 * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A)
77 * This also has an effect on RX/TX arbitration
79 static int rx_xoff_thresh_bytes = -1;
80 module_param(rx_xoff_thresh_bytes, int, 0644);
81 MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold");
83 /* RX FIFO XON watermark
85 * When the amount of the RX FIFO used decreases below this
86 * watermark send XON. Only used if TX flow control is enabled (ethtool -A)
87 * This also has an effect on RX/TX arbitration
89 static int rx_xon_thresh_bytes = -1;
90 module_param(rx_xon_thresh_bytes, int, 0644);
91 MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
93 /* TX descriptor ring size - min 512 max 4k */
94 #define FALCON_TXD_RING_ORDER TX_DESCQ_SIZE_1K
95 #define FALCON_TXD_RING_SIZE 1024
96 #define FALCON_TXD_RING_MASK (FALCON_TXD_RING_SIZE - 1)
98 /* RX descriptor ring size - min 512 max 4k */
99 #define FALCON_RXD_RING_ORDER RX_DESCQ_SIZE_1K
100 #define FALCON_RXD_RING_SIZE 1024
101 #define FALCON_RXD_RING_MASK (FALCON_RXD_RING_SIZE - 1)
103 /* Event queue size - max 32k */
104 #define FALCON_EVQ_ORDER EVQ_SIZE_4K
105 #define FALCON_EVQ_SIZE 4096
106 #define FALCON_EVQ_MASK (FALCON_EVQ_SIZE - 1)
108 /* Max number of internal errors. After this resets will not be performed */
109 #define FALCON_MAX_INT_ERRORS 4
111 /* Maximum period that we wait for flush events. If the flush event
112 * doesn't arrive in this period of time then we check if the queue
113 * was disabled anyway. */
114 #define FALCON_FLUSH_TIMEOUT 10 /* 10ms */
116 /**************************************************************************
120 **************************************************************************
123 /* DMA address mask */
124 #define FALCON_DMA_MASK DMA_BIT_MASK(46)
126 /* TX DMA length mask (13-bit) */
127 #define FALCON_TX_DMA_MASK (4096 - 1)
129 /* Size and alignment of special buffers (4KB) */
130 #define FALCON_BUF_SIZE 4096
132 /* Dummy SRAM size code */
133 #define SRM_NB_BSZ_ONCHIP_ONLY (-1)
135 /* Be nice if these (or equiv.) were in linux/pci_regs.h, but they're not. */
136 #define PCI_EXP_DEVCAP_PWR_VAL_LBN 18
137 #define PCI_EXP_DEVCAP_PWR_SCL_LBN 26
138 #define PCI_EXP_DEVCTL_PAYLOAD_LBN 5
139 #define PCI_EXP_LNKSTA_LNK_WID 0x3f0
140 #define PCI_EXP_LNKSTA_LNK_WID_LBN 4
142 #define FALCON_IS_DUAL_FUNC(efx) \
143 (falcon_rev(efx) < FALCON_REV_B0)
145 /**************************************************************************
147 * Falcon hardware access
149 **************************************************************************/
151 /* Read the current event from the event queue */
152 static inline efx_qword_t *falcon_event(struct efx_channel *channel,
155 return (((efx_qword_t *) (channel->eventq.addr)) + index);
158 /* See if an event is present
160 * We check both the high and low dword of the event for all ones. We
161 * wrote all ones when we cleared the event, and no valid event can
162 * have all ones in either its high or low dwords. This approach is
163 * robust against reordering.
165 * Note that using a single 64-bit comparison is incorrect; even
166 * though the CPU read will be atomic, the DMA write may not be.
168 static inline int falcon_event_present(efx_qword_t *event)
170 return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) |
171 EFX_DWORD_IS_ALL_ONES(event->dword[1])));
174 /**************************************************************************
176 * I2C bus - this is a bit-bashing interface using GPIO pins
177 * Note that it uses the output enables to tristate the outputs
178 * SDA is the data pin and SCL is the clock
180 **************************************************************************
182 static void falcon_setsda(void *data, int state)
184 struct efx_nic *efx = (struct efx_nic *)data;
187 falcon_read(efx, ®, GPIO_CTL_REG_KER);
188 EFX_SET_OWORD_FIELD(reg, GPIO3_OEN, !state);
189 falcon_write(efx, ®, GPIO_CTL_REG_KER);
192 static void falcon_setscl(void *data, int state)
194 struct efx_nic *efx = (struct efx_nic *)data;
197 falcon_read(efx, ®, GPIO_CTL_REG_KER);
198 EFX_SET_OWORD_FIELD(reg, GPIO0_OEN, !state);
199 falcon_write(efx, ®, GPIO_CTL_REG_KER);
202 static int falcon_getsda(void *data)
204 struct efx_nic *efx = (struct efx_nic *)data;
207 falcon_read(efx, ®, GPIO_CTL_REG_KER);
208 return EFX_OWORD_FIELD(reg, GPIO3_IN);
211 static int falcon_getscl(void *data)
213 struct efx_nic *efx = (struct efx_nic *)data;
216 falcon_read(efx, ®, GPIO_CTL_REG_KER);
217 return EFX_OWORD_FIELD(reg, GPIO0_IN);
220 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
221 .setsda = falcon_setsda,
222 .setscl = falcon_setscl,
223 .getsda = falcon_getsda,
224 .getscl = falcon_getscl,
226 /* Wait up to 50 ms for slave to let us pull SCL high */
227 .timeout = DIV_ROUND_UP(HZ, 20),
230 /**************************************************************************
232 * Falcon special buffer handling
233 * Special buffers are used for event queues and the TX and RX
236 *************************************************************************/
239 * Initialise a Falcon special buffer
241 * This will define a buffer (previously allocated via
242 * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing
243 * it to be used for event queues, descriptor rings etc.
246 falcon_init_special_buffer(struct efx_nic *efx,
247 struct efx_special_buffer *buffer)
249 efx_qword_t buf_desc;
254 EFX_BUG_ON_PARANOID(!buffer->addr);
256 /* Write buffer descriptors to NIC */
257 for (i = 0; i < buffer->entries; i++) {
258 index = buffer->index + i;
259 dma_addr = buffer->dma_addr + (i * 4096);
260 EFX_LOG(efx, "mapping special buffer %d at %llx\n",
261 index, (unsigned long long)dma_addr);
262 EFX_POPULATE_QWORD_4(buf_desc,
263 IP_DAT_BUF_SIZE, IP_DAT_BUF_SIZE_4K,
265 BUF_ADR_FBUF, (dma_addr >> 12),
266 BUF_OWNER_ID_FBUF, 0);
267 falcon_write_sram(efx, &buf_desc, index);
271 /* Unmaps a buffer from Falcon and clears the buffer table entries */
273 falcon_fini_special_buffer(struct efx_nic *efx,
274 struct efx_special_buffer *buffer)
276 efx_oword_t buf_tbl_upd;
277 unsigned int start = buffer->index;
278 unsigned int end = (buffer->index + buffer->entries - 1);
280 if (!buffer->entries)
283 EFX_LOG(efx, "unmapping special buffers %d-%d\n",
284 buffer->index, buffer->index + buffer->entries - 1);
286 EFX_POPULATE_OWORD_4(buf_tbl_upd,
290 BUF_CLR_START_ID, start);
291 falcon_write(efx, &buf_tbl_upd, BUF_TBL_UPD_REG_KER);
295 * Allocate a new Falcon special buffer
297 * This allocates memory for a new buffer, clears it and allocates a
298 * new buffer ID range. It does not write into Falcon's buffer table.
300 * This call will allocate 4KB buffers, since Falcon can't use 8KB
301 * buffers for event queues and descriptor rings.
303 static int falcon_alloc_special_buffer(struct efx_nic *efx,
304 struct efx_special_buffer *buffer,
307 struct falcon_nic_data *nic_data = efx->nic_data;
309 len = ALIGN(len, FALCON_BUF_SIZE);
311 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
316 buffer->entries = len / FALCON_BUF_SIZE;
317 BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1));
319 /* All zeros is a potentially valid event so memset to 0xff */
320 memset(buffer->addr, 0xff, len);
322 /* Select new buffer ID */
323 buffer->index = nic_data->next_buffer_table;
324 nic_data->next_buffer_table += buffer->entries;
326 EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x "
327 "(virt %p phys %lx)\n", buffer->index,
328 buffer->index + buffer->entries - 1,
329 (unsigned long long)buffer->dma_addr, len,
330 buffer->addr, virt_to_phys(buffer->addr));
335 static void falcon_free_special_buffer(struct efx_nic *efx,
336 struct efx_special_buffer *buffer)
341 EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x "
342 "(virt %p phys %lx)\n", buffer->index,
343 buffer->index + buffer->entries - 1,
344 (unsigned long long)buffer->dma_addr, buffer->len,
345 buffer->addr, virt_to_phys(buffer->addr));
347 pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr,
353 /**************************************************************************
355 * Falcon generic buffer handling
356 * These buffers are used for interrupt status and MAC stats
358 **************************************************************************/
360 static int falcon_alloc_buffer(struct efx_nic *efx,
361 struct efx_buffer *buffer, unsigned int len)
363 buffer->addr = pci_alloc_consistent(efx->pci_dev, len,
368 memset(buffer->addr, 0, len);
372 static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
375 pci_free_consistent(efx->pci_dev, buffer->len,
376 buffer->addr, buffer->dma_addr);
381 /**************************************************************************
385 **************************************************************************/
387 /* Returns a pointer to the specified transmit descriptor in the TX
388 * descriptor queue belonging to the specified channel.
390 static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue,
393 return (((efx_qword_t *) (tx_queue->txd.addr)) + index);
396 /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */
397 static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
402 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
403 EFX_POPULATE_DWORD_1(reg, TX_DESC_WPTR_DWORD, write_ptr);
404 falcon_writel_page(tx_queue->efx, ®,
405 TX_DESC_UPD_REG_KER_DWORD, tx_queue->queue);
409 /* For each entry inserted into the software descriptor ring, create a
410 * descriptor in the hardware TX descriptor ring (in host memory), and
413 void falcon_push_buffers(struct efx_tx_queue *tx_queue)
416 struct efx_tx_buffer *buffer;
420 BUG_ON(tx_queue->write_count == tx_queue->insert_count);
423 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
424 buffer = &tx_queue->buffer[write_ptr];
425 txd = falcon_tx_desc(tx_queue, write_ptr);
426 ++tx_queue->write_count;
428 /* Create TX descriptor ring entry */
429 EFX_POPULATE_QWORD_5(*txd,
431 TX_KER_CONT, buffer->continuation,
432 TX_KER_BYTE_CNT, buffer->len,
433 TX_KER_BUF_REGION, 0,
434 TX_KER_BUF_ADR, buffer->dma_addr);
435 } while (tx_queue->write_count != tx_queue->insert_count);
437 wmb(); /* Ensure descriptors are written before they are fetched */
438 falcon_notify_tx_desc(tx_queue);
441 /* Allocate hardware resources for a TX queue */
442 int falcon_probe_tx(struct efx_tx_queue *tx_queue)
444 struct efx_nic *efx = tx_queue->efx;
445 return falcon_alloc_special_buffer(efx, &tx_queue->txd,
446 FALCON_TXD_RING_SIZE *
447 sizeof(efx_qword_t));
450 void falcon_init_tx(struct efx_tx_queue *tx_queue)
452 efx_oword_t tx_desc_ptr;
453 struct efx_nic *efx = tx_queue->efx;
455 /* Pin TX descriptor ring */
456 falcon_init_special_buffer(efx, &tx_queue->txd);
458 /* Push TX descriptor ring to card */
459 EFX_POPULATE_OWORD_10(tx_desc_ptr,
463 TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index,
464 TX_DESCQ_EVQ_ID, tx_queue->channel->channel,
465 TX_DESCQ_OWNER_ID, 0,
466 TX_DESCQ_LABEL, tx_queue->queue,
467 TX_DESCQ_SIZE, FALCON_TXD_RING_ORDER,
469 TX_NON_IP_DROP_DIS_B0, 1);
471 if (falcon_rev(efx) >= FALCON_REV_B0) {
472 int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
473 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_IP_CHKSM_DIS_B0, !csum);
474 EFX_SET_OWORD_FIELD(tx_desc_ptr, TX_TCP_CHKSM_DIS_B0, !csum);
477 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
480 if (falcon_rev(efx) < FALCON_REV_B0) {
483 /* Only 128 bits in this register */
484 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
486 falcon_read(efx, ®, TX_CHKSM_CFG_REG_KER_A1);
487 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
488 clear_bit_le(tx_queue->queue, (void *)®);
490 set_bit_le(tx_queue->queue, (void *)®);
491 falcon_write(efx, ®, TX_CHKSM_CFG_REG_KER_A1);
495 static int falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
497 struct efx_nic *efx = tx_queue->efx;
498 struct efx_channel *channel = &efx->channel[0];
499 efx_oword_t tx_flush_descq;
500 unsigned int read_ptr, i;
502 /* Post a flush command */
503 EFX_POPULATE_OWORD_2(tx_flush_descq,
504 TX_FLUSH_DESCQ_CMD, 1,
505 TX_FLUSH_DESCQ, tx_queue->queue);
506 falcon_write(efx, &tx_flush_descq, TX_FLUSH_DESCQ_REG_KER);
507 msleep(FALCON_FLUSH_TIMEOUT);
509 if (EFX_WORKAROUND_7803(efx))
512 /* Look for a flush completed event */
513 read_ptr = channel->eventq_read_ptr;
514 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
515 efx_qword_t *event = falcon_event(channel, read_ptr);
516 int ev_code, ev_sub_code, ev_queue;
517 if (!falcon_event_present(event))
520 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
521 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
522 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_TX_DESCQ_ID);
523 if ((ev_sub_code == TX_DESCQ_FLS_DONE_EV_DECODE) &&
524 (ev_queue == tx_queue->queue)) {
525 EFX_LOG(efx, "tx queue %d flush command succesful\n",
530 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
533 if (EFX_WORKAROUND_11557(efx)) {
537 falcon_read_table(efx, ®, efx->type->txd_ptr_tbl_base,
539 enabled = EFX_OWORD_FIELD(reg, TX_DESCQ_EN);
541 EFX_LOG(efx, "tx queue %d disabled without a "
542 "flush event seen\n", tx_queue->queue);
547 EFX_ERR(efx, "tx queue %d flush command timed out\n", tx_queue->queue);
551 void falcon_fini_tx(struct efx_tx_queue *tx_queue)
553 struct efx_nic *efx = tx_queue->efx;
554 efx_oword_t tx_desc_ptr;
556 /* Stop the hardware using the queue */
557 if (falcon_flush_tx_queue(tx_queue))
558 EFX_ERR(efx, "failed to flush tx queue %d\n", tx_queue->queue);
560 /* Remove TX descriptor ring from card */
561 EFX_ZERO_OWORD(tx_desc_ptr);
562 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
565 /* Unpin TX descriptor ring */
566 falcon_fini_special_buffer(efx, &tx_queue->txd);
569 /* Free buffers backing TX queue */
570 void falcon_remove_tx(struct efx_tx_queue *tx_queue)
572 falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd);
575 /**************************************************************************
579 **************************************************************************/
581 /* Returns a pointer to the specified descriptor in the RX descriptor queue */
582 static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue,
585 return (((efx_qword_t *) (rx_queue->rxd.addr)) + index);
588 /* This creates an entry in the RX descriptor queue */
589 static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue,
592 struct efx_rx_buffer *rx_buf;
595 rxd = falcon_rx_desc(rx_queue, index);
596 rx_buf = efx_rx_buffer(rx_queue, index);
597 EFX_POPULATE_QWORD_3(*rxd,
600 rx_queue->efx->type->rx_buffer_padding,
601 RX_KER_BUF_REGION, 0,
602 RX_KER_BUF_ADR, rx_buf->dma_addr);
605 /* This writes to the RX_DESC_WPTR register for the specified receive
608 void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
613 while (rx_queue->notified_count != rx_queue->added_count) {
614 falcon_build_rx_desc(rx_queue,
615 rx_queue->notified_count &
616 FALCON_RXD_RING_MASK);
617 ++rx_queue->notified_count;
621 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
622 EFX_POPULATE_DWORD_1(reg, RX_DESC_WPTR_DWORD, write_ptr);
623 falcon_writel_page(rx_queue->efx, ®,
624 RX_DESC_UPD_REG_KER_DWORD, rx_queue->queue);
627 int falcon_probe_rx(struct efx_rx_queue *rx_queue)
629 struct efx_nic *efx = rx_queue->efx;
630 return falcon_alloc_special_buffer(efx, &rx_queue->rxd,
631 FALCON_RXD_RING_SIZE *
632 sizeof(efx_qword_t));
635 void falcon_init_rx(struct efx_rx_queue *rx_queue)
637 efx_oword_t rx_desc_ptr;
638 struct efx_nic *efx = rx_queue->efx;
639 bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
640 bool iscsi_digest_en = is_b0;
642 EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
643 rx_queue->queue, rx_queue->rxd.index,
644 rx_queue->rxd.index + rx_queue->rxd.entries - 1);
646 /* Pin RX descriptor ring */
647 falcon_init_special_buffer(efx, &rx_queue->rxd);
649 /* Push RX descriptor ring to card */
650 EFX_POPULATE_OWORD_10(rx_desc_ptr,
651 RX_ISCSI_DDIG_EN, iscsi_digest_en,
652 RX_ISCSI_HDIG_EN, iscsi_digest_en,
653 RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index,
654 RX_DESCQ_EVQ_ID, rx_queue->channel->channel,
655 RX_DESCQ_OWNER_ID, 0,
656 RX_DESCQ_LABEL, rx_queue->queue,
657 RX_DESCQ_SIZE, FALCON_RXD_RING_ORDER,
658 RX_DESCQ_TYPE, 0 /* kernel queue */ ,
659 /* For >=B0 this is scatter so disable */
660 RX_DESCQ_JUMBO, !is_b0,
662 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
666 static int falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
668 struct efx_nic *efx = rx_queue->efx;
669 struct efx_channel *channel = &efx->channel[0];
670 unsigned int read_ptr, i;
671 efx_oword_t rx_flush_descq;
673 /* Post a flush command */
674 EFX_POPULATE_OWORD_2(rx_flush_descq,
675 RX_FLUSH_DESCQ_CMD, 1,
676 RX_FLUSH_DESCQ, rx_queue->queue);
677 falcon_write(efx, &rx_flush_descq, RX_FLUSH_DESCQ_REG_KER);
678 msleep(FALCON_FLUSH_TIMEOUT);
680 if (EFX_WORKAROUND_7803(efx))
683 /* Look for a flush completed event */
684 read_ptr = channel->eventq_read_ptr;
685 for (i = 0; i < FALCON_EVQ_SIZE; ++i) {
686 efx_qword_t *event = falcon_event(channel, read_ptr);
687 int ev_code, ev_sub_code, ev_queue;
689 if (!falcon_event_present(event))
692 ev_code = EFX_QWORD_FIELD(*event, EV_CODE);
693 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
694 ev_queue = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_DESCQ_ID);
695 ev_failed = EFX_QWORD_FIELD(*event, DRIVER_EV_RX_FLUSH_FAIL);
697 if ((ev_sub_code == RX_DESCQ_FLS_DONE_EV_DECODE) &&
698 (ev_queue == rx_queue->queue)) {
700 EFX_INFO(efx, "rx queue %d flush command "
701 "failed\n", rx_queue->queue);
704 EFX_LOG(efx, "rx queue %d flush command "
705 "succesful\n", rx_queue->queue);
710 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
713 if (EFX_WORKAROUND_11557(efx)) {
717 falcon_read_table(efx, ®, efx->type->rxd_ptr_tbl_base,
719 enabled = EFX_OWORD_FIELD(reg, RX_DESCQ_EN);
721 EFX_LOG(efx, "rx queue %d disabled without a "
722 "flush event seen\n", rx_queue->queue);
727 EFX_ERR(efx, "rx queue %d flush command timed out\n", rx_queue->queue);
731 void falcon_fini_rx(struct efx_rx_queue *rx_queue)
733 efx_oword_t rx_desc_ptr;
734 struct efx_nic *efx = rx_queue->efx;
737 /* Try and flush the rx queue. This may need to be repeated */
738 for (i = 0; i < 5; i++) {
739 rc = falcon_flush_rx_queue(rx_queue);
745 EFX_ERR(efx, "failed to flush rx queue %d\n", rx_queue->queue);
746 efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
749 /* Remove RX descriptor ring from card */
750 EFX_ZERO_OWORD(rx_desc_ptr);
751 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
754 /* Unpin RX descriptor ring */
755 falcon_fini_special_buffer(efx, &rx_queue->rxd);
758 /* Free buffers backing RX queue */
759 void falcon_remove_rx(struct efx_rx_queue *rx_queue)
761 falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd);
764 /**************************************************************************
766 * Falcon event queue processing
767 * Event queues are processed by per-channel tasklets.
769 **************************************************************************/
771 /* Update a channel's event queue's read pointer (RPTR) register
773 * This writes the EVQ_RPTR_REG register for the specified channel's
776 * Note that EVQ_RPTR_REG contains the index of the "last read" event,
777 * whereas channel->eventq_read_ptr contains the index of the "next to
780 void falcon_eventq_read_ack(struct efx_channel *channel)
783 struct efx_nic *efx = channel->efx;
785 EFX_POPULATE_DWORD_1(reg, EVQ_RPTR_DWORD, channel->eventq_read_ptr);
786 falcon_writel_table(efx, ®, efx->type->evq_rptr_tbl_base,
790 /* Use HW to insert a SW defined event */
791 void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
793 efx_oword_t drv_ev_reg;
795 EFX_POPULATE_OWORD_2(drv_ev_reg,
796 DRV_EV_QID, channel->channel,
798 EFX_QWORD_FIELD64(*event, WHOLE_EVENT));
799 falcon_write(channel->efx, &drv_ev_reg, DRV_EV_REG_KER);
802 /* Handle a transmit completion event
804 * Falcon batches TX completion events; the message we receive is of
805 * the form "complete all TX events up to this index".
807 static void falcon_handle_tx_event(struct efx_channel *channel,
810 unsigned int tx_ev_desc_ptr;
811 unsigned int tx_ev_q_label;
812 struct efx_tx_queue *tx_queue;
813 struct efx_nic *efx = channel->efx;
815 if (likely(EFX_QWORD_FIELD(*event, TX_EV_COMP))) {
816 /* Transmit completion */
817 tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, TX_EV_DESC_PTR);
818 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
819 tx_queue = &efx->tx_queue[tx_ev_q_label];
820 efx_xmit_done(tx_queue, tx_ev_desc_ptr);
821 } else if (EFX_QWORD_FIELD(*event, TX_EV_WQ_FF_FULL)) {
822 /* Rewrite the FIFO write pointer */
823 tx_ev_q_label = EFX_QWORD_FIELD(*event, TX_EV_Q_LABEL);
824 tx_queue = &efx->tx_queue[tx_ev_q_label];
826 if (efx_dev_registered(efx))
827 netif_tx_lock(efx->net_dev);
828 falcon_notify_tx_desc(tx_queue);
829 if (efx_dev_registered(efx))
830 netif_tx_unlock(efx->net_dev);
831 } else if (EFX_QWORD_FIELD(*event, TX_EV_PKT_ERR) &&
832 EFX_WORKAROUND_10727(efx)) {
833 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
835 EFX_ERR(efx, "channel %d unexpected TX event "
836 EFX_QWORD_FMT"\n", channel->channel,
837 EFX_QWORD_VAL(*event));
841 /* Detect errors included in the rx_evt_pkt_ok bit. */
842 static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
843 const efx_qword_t *event,
847 struct efx_nic *efx = rx_queue->efx;
848 bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err;
849 bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err;
850 bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc;
851 bool rx_ev_other_err, rx_ev_pause_frm;
852 bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt;
853 unsigned rx_ev_pkt_type;
855 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
856 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
857 rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, RX_EV_TOBE_DISC);
858 rx_ev_pkt_type = EFX_QWORD_FIELD(*event, RX_EV_PKT_TYPE);
859 rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event,
860 RX_EV_BUF_OWNER_ID_ERR);
861 rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, RX_EV_IF_FRAG_ERR);
862 rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event,
863 RX_EV_IP_HDR_CHKSUM_ERR);
864 rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event,
865 RX_EV_TCP_UDP_CHKSUM_ERR);
866 rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, RX_EV_ETH_CRC_ERR);
867 rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, RX_EV_FRM_TRUNC);
868 rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
869 0 : EFX_QWORD_FIELD(*event, RX_EV_DRIB_NIB));
870 rx_ev_pause_frm = EFX_QWORD_FIELD(*event, RX_EV_PAUSE_FRM_ERR);
872 /* Every error apart from tobe_disc and pause_frm */
873 rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err |
874 rx_ev_buf_owner_id_err | rx_ev_eth_crc_err |
875 rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err);
877 /* Count errors that are not in MAC stats. */
879 ++rx_queue->channel->n_rx_frm_trunc;
880 else if (rx_ev_tobe_disc)
881 ++rx_queue->channel->n_rx_tobe_disc;
882 else if (rx_ev_ip_hdr_chksum_err)
883 ++rx_queue->channel->n_rx_ip_hdr_chksum_err;
884 else if (rx_ev_tcp_udp_chksum_err)
885 ++rx_queue->channel->n_rx_tcp_udp_chksum_err;
886 if (rx_ev_ip_frag_err)
887 ++rx_queue->channel->n_rx_ip_frag_err;
889 /* The frame must be discarded if any of these are true. */
890 *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib |
891 rx_ev_tobe_disc | rx_ev_pause_frm);
893 /* TOBE_DISC is expected on unicast mismatches; don't print out an
894 * error message. FRM_TRUNC indicates RXDP dropped the packet due
895 * to a FIFO overflow.
897 #ifdef EFX_ENABLE_DEBUG
898 if (rx_ev_other_err) {
899 EFX_INFO_RL(efx, " RX queue %d unexpected RX event "
900 EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n",
901 rx_queue->queue, EFX_QWORD_VAL(*event),
902 rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "",
903 rx_ev_ip_hdr_chksum_err ?
904 " [IP_HDR_CHKSUM_ERR]" : "",
905 rx_ev_tcp_udp_chksum_err ?
906 " [TCP_UDP_CHKSUM_ERR]" : "",
907 rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "",
908 rx_ev_frm_trunc ? " [FRM_TRUNC]" : "",
909 rx_ev_drib_nib ? " [DRIB_NIB]" : "",
910 rx_ev_tobe_disc ? " [TOBE_DISC]" : "",
911 rx_ev_pause_frm ? " [PAUSE]" : "");
915 if (unlikely(rx_ev_eth_crc_err && EFX_WORKAROUND_10750(efx) &&
916 efx->phy_type == PHY_TYPE_10XPRESS))
917 tenxpress_crc_err(efx);
920 /* Handle receive events that are not in-order. */
921 static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue,
924 struct efx_nic *efx = rx_queue->efx;
925 unsigned expected, dropped;
927 expected = rx_queue->removed_count & FALCON_RXD_RING_MASK;
928 dropped = ((index + FALCON_RXD_RING_SIZE - expected) &
929 FALCON_RXD_RING_MASK);
930 EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n",
931 dropped, index, expected);
933 efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ?
934 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
937 /* Handle a packet received event
939 * Falcon silicon gives a "discard" flag if it's a unicast packet with the
940 * wrong destination address
941 * Also "is multicast" and "matches multicast filter" flags can be used to
942 * discard non-matching multicast packets.
944 static void falcon_handle_rx_event(struct efx_channel *channel,
945 const efx_qword_t *event)
947 unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt;
948 unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt;
949 unsigned expected_ptr;
950 bool rx_ev_pkt_ok, discard = false, checksummed;
951 struct efx_rx_queue *rx_queue;
952 struct efx_nic *efx = channel->efx;
954 /* Basic packet information */
955 rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, RX_EV_BYTE_CNT);
956 rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, RX_EV_PKT_OK);
957 rx_ev_hdr_type = EFX_QWORD_FIELD(*event, RX_EV_HDR_TYPE);
958 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_JUMBO_CONT));
959 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_SOP) != 1);
960 WARN_ON(EFX_QWORD_FIELD(*event, RX_EV_Q_LABEL) != channel->channel);
962 rx_queue = &efx->rx_queue[channel->channel];
964 rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, RX_EV_DESC_PTR);
965 expected_ptr = rx_queue->removed_count & FALCON_RXD_RING_MASK;
966 if (unlikely(rx_ev_desc_ptr != expected_ptr))
967 falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr);
969 if (likely(rx_ev_pkt_ok)) {
970 /* If packet is marked as OK and packet type is TCP/IPv4 or
971 * UDP/IPv4, then we can rely on the hardware checksum.
973 checksummed = RX_EV_HDR_TYPE_HAS_CHECKSUMS(rx_ev_hdr_type);
975 falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok,
980 /* Detect multicast packets that didn't match the filter */
981 rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, RX_EV_MCAST_PKT);
982 if (rx_ev_mcast_pkt) {
983 unsigned int rx_ev_mcast_hash_match =
984 EFX_QWORD_FIELD(*event, RX_EV_MCAST_HASH_MATCH);
986 if (unlikely(!rx_ev_mcast_hash_match))
990 /* Handle received packet */
991 efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt,
992 checksummed, discard);
995 /* Global events are basically PHY events */
996 static void falcon_handle_global_event(struct efx_channel *channel,
999 struct efx_nic *efx = channel->efx;
1000 bool is_phy_event = false, handled = false;
1002 /* Check for interrupt on either port. Some boards have a
1003 * single PHY wired to the interrupt line for port 1. */
1004 if (EFX_QWORD_FIELD(*event, G_PHY0_INTR) ||
1005 EFX_QWORD_FIELD(*event, G_PHY1_INTR) ||
1006 EFX_QWORD_FIELD(*event, XG_PHY_INTR))
1007 is_phy_event = true;
1009 if ((falcon_rev(efx) >= FALCON_REV_B0) &&
1010 EFX_OWORD_FIELD(*event, XG_MNT_INTR_B0))
1011 is_phy_event = true;
1014 efx->phy_op->clear_interrupt(efx);
1015 queue_work(efx->workqueue, &efx->reconfigure_work);
1019 if (EFX_QWORD_FIELD_VER(efx, *event, RX_RECOVERY)) {
1020 EFX_ERR(efx, "channel %d seen global RX_RESET "
1021 "event. Resetting.\n", channel->channel);
1023 atomic_inc(&efx->rx_reset);
1024 efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ?
1025 RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE);
1030 EFX_ERR(efx, "channel %d unknown global event "
1031 EFX_QWORD_FMT "\n", channel->channel,
1032 EFX_QWORD_VAL(*event));
1035 static void falcon_handle_driver_event(struct efx_channel *channel,
1038 struct efx_nic *efx = channel->efx;
1039 unsigned int ev_sub_code;
1040 unsigned int ev_sub_data;
1042 ev_sub_code = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_CODE);
1043 ev_sub_data = EFX_QWORD_FIELD(*event, DRIVER_EV_SUB_DATA);
1045 switch (ev_sub_code) {
1046 case TX_DESCQ_FLS_DONE_EV_DECODE:
1047 EFX_TRACE(efx, "channel %d TXQ %d flushed\n",
1048 channel->channel, ev_sub_data);
1050 case RX_DESCQ_FLS_DONE_EV_DECODE:
1051 EFX_TRACE(efx, "channel %d RXQ %d flushed\n",
1052 channel->channel, ev_sub_data);
1054 case EVQ_INIT_DONE_EV_DECODE:
1055 EFX_LOG(efx, "channel %d EVQ %d initialised\n",
1056 channel->channel, ev_sub_data);
1058 case SRM_UPD_DONE_EV_DECODE:
1059 EFX_TRACE(efx, "channel %d SRAM update done\n",
1062 case WAKE_UP_EV_DECODE:
1063 EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n",
1064 channel->channel, ev_sub_data);
1066 case TIMER_EV_DECODE:
1067 EFX_TRACE(efx, "channel %d RX queue %d timer expired\n",
1068 channel->channel, ev_sub_data);
1070 case RX_RECOVERY_EV_DECODE:
1071 EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. "
1072 "Resetting.\n", channel->channel);
1073 atomic_inc(&efx->rx_reset);
1074 efx_schedule_reset(efx,
1075 EFX_WORKAROUND_6555(efx) ?
1076 RESET_TYPE_RX_RECOVERY :
1077 RESET_TYPE_DISABLE);
1079 case RX_DSC_ERROR_EV_DECODE:
1080 EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error."
1081 " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1082 efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH);
1084 case TX_DSC_ERROR_EV_DECODE:
1085 EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error."
1086 " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data);
1087 efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH);
1090 EFX_TRACE(efx, "channel %d unknown driver event code %d "
1091 "data %04x\n", channel->channel, ev_sub_code,
1097 int falcon_process_eventq(struct efx_channel *channel, int rx_quota)
1099 unsigned int read_ptr;
1100 efx_qword_t event, *p_event;
1104 read_ptr = channel->eventq_read_ptr;
1107 p_event = falcon_event(channel, read_ptr);
1110 if (!falcon_event_present(&event))
1114 EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n",
1115 channel->channel, EFX_QWORD_VAL(event));
1117 /* Clear this event by marking it all ones */
1118 EFX_SET_QWORD(*p_event);
1120 ev_code = EFX_QWORD_FIELD(event, EV_CODE);
1123 case RX_IP_EV_DECODE:
1124 falcon_handle_rx_event(channel, &event);
1127 case TX_IP_EV_DECODE:
1128 falcon_handle_tx_event(channel, &event);
1130 case DRV_GEN_EV_DECODE:
1131 channel->eventq_magic
1132 = EFX_QWORD_FIELD(event, EVQ_MAGIC);
1133 EFX_LOG(channel->efx, "channel %d received generated "
1134 "event "EFX_QWORD_FMT"\n", channel->channel,
1135 EFX_QWORD_VAL(event));
1137 case GLOBAL_EV_DECODE:
1138 falcon_handle_global_event(channel, &event);
1140 case DRIVER_EV_DECODE:
1141 falcon_handle_driver_event(channel, &event);
1144 EFX_ERR(channel->efx, "channel %d unknown event type %d"
1145 " (data " EFX_QWORD_FMT ")\n", channel->channel,
1146 ev_code, EFX_QWORD_VAL(event));
1149 /* Increment read pointer */
1150 read_ptr = (read_ptr + 1) & FALCON_EVQ_MASK;
1152 } while (rx_packets < rx_quota);
1154 channel->eventq_read_ptr = read_ptr;
1158 void falcon_set_int_moderation(struct efx_channel *channel)
1160 efx_dword_t timer_cmd;
1161 struct efx_nic *efx = channel->efx;
1163 /* Set timer register */
1164 if (channel->irq_moderation) {
1165 /* Round to resolution supported by hardware. The value we
1166 * program is based at 0. So actual interrupt moderation
1167 * achieved is ((x + 1) * res).
1169 unsigned int res = 5;
1170 channel->irq_moderation -= (channel->irq_moderation % res);
1171 if (channel->irq_moderation < res)
1172 channel->irq_moderation = res;
1173 EFX_POPULATE_DWORD_2(timer_cmd,
1174 TIMER_MODE, TIMER_MODE_INT_HLDOFF,
1176 (channel->irq_moderation / res) - 1);
1178 EFX_POPULATE_DWORD_2(timer_cmd,
1179 TIMER_MODE, TIMER_MODE_DIS,
1182 falcon_writel_page_locked(efx, &timer_cmd, TIMER_CMD_REG_KER,
1187 /* Allocate buffer table entries for event queue */
1188 int falcon_probe_eventq(struct efx_channel *channel)
1190 struct efx_nic *efx = channel->efx;
1191 unsigned int evq_size;
1193 evq_size = FALCON_EVQ_SIZE * sizeof(efx_qword_t);
1194 return falcon_alloc_special_buffer(efx, &channel->eventq, evq_size);
1197 void falcon_init_eventq(struct efx_channel *channel)
1199 efx_oword_t evq_ptr;
1200 struct efx_nic *efx = channel->efx;
1202 EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n",
1203 channel->channel, channel->eventq.index,
1204 channel->eventq.index + channel->eventq.entries - 1);
1206 /* Pin event queue buffer */
1207 falcon_init_special_buffer(efx, &channel->eventq);
1209 /* Fill event queue with all ones (i.e. empty events) */
1210 memset(channel->eventq.addr, 0xff, channel->eventq.len);
1212 /* Push event queue to card */
1213 EFX_POPULATE_OWORD_3(evq_ptr,
1215 EVQ_SIZE, FALCON_EVQ_ORDER,
1216 EVQ_BUF_BASE_ID, channel->eventq.index);
1217 falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1220 falcon_set_int_moderation(channel);
1223 void falcon_fini_eventq(struct efx_channel *channel)
1225 efx_oword_t eventq_ptr;
1226 struct efx_nic *efx = channel->efx;
1228 /* Remove event queue from card */
1229 EFX_ZERO_OWORD(eventq_ptr);
1230 falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1233 /* Unpin event queue */
1234 falcon_fini_special_buffer(efx, &channel->eventq);
1237 /* Free buffers backing event queue */
1238 void falcon_remove_eventq(struct efx_channel *channel)
1240 falcon_free_special_buffer(channel->efx, &channel->eventq);
1244 /* Generates a test event on the event queue. A subsequent call to
1245 * process_eventq() should pick up the event and place the value of
1246 * "magic" into channel->eventq_magic;
1248 void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic)
1250 efx_qword_t test_event;
1252 EFX_POPULATE_QWORD_2(test_event,
1253 EV_CODE, DRV_GEN_EV_DECODE,
1255 falcon_generate_event(channel, &test_event);
1259 /**************************************************************************
1261 * Falcon hardware interrupts
1262 * The hardware interrupt handler does very little work; all the event
1263 * queue processing is carried out by per-channel tasklets.
1265 **************************************************************************/
1267 /* Enable/disable/generate Falcon interrupts */
1268 static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1271 efx_oword_t int_en_reg_ker;
1273 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1275 DRV_INT_EN_KER, enabled);
1276 falcon_write(efx, &int_en_reg_ker, INT_EN_REG_KER);
1279 void falcon_enable_interrupts(struct efx_nic *efx)
1281 efx_oword_t int_adr_reg_ker;
1282 struct efx_channel *channel;
1284 EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr));
1285 wmb(); /* Ensure interrupt vector is clear before interrupts enabled */
1287 /* Program address */
1288 EFX_POPULATE_OWORD_2(int_adr_reg_ker,
1289 NORM_INT_VEC_DIS_KER, EFX_INT_MODE_USE_MSI(efx),
1290 INT_ADR_KER, efx->irq_status.dma_addr);
1291 falcon_write(efx, &int_adr_reg_ker, INT_ADR_REG_KER);
1293 /* Enable interrupts */
1294 falcon_interrupts(efx, 1, 0);
1296 /* Force processing of all the channels to get the EVQ RPTRs up to
1298 efx_for_each_channel(channel, efx)
1299 efx_schedule_channel(channel);
1302 void falcon_disable_interrupts(struct efx_nic *efx)
1304 /* Disable interrupts */
1305 falcon_interrupts(efx, 0, 0);
1308 /* Generate a Falcon test interrupt
1309 * Interrupt must already have been enabled, otherwise nasty things
1312 void falcon_generate_interrupt(struct efx_nic *efx)
1314 falcon_interrupts(efx, 1, 1);
1317 /* Acknowledge a legacy interrupt from Falcon
1319 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
1321 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
1322 * BIU. Interrupt acknowledge is read sensitive so must write instead
1323 * (then read to ensure the BIU collector is flushed)
1325 * NB most hardware supports MSI interrupts
1327 static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1331 EFX_POPULATE_DWORD_1(reg, INT_ACK_DUMMY_DATA, 0xb7eb7e);
1332 falcon_writel(efx, ®, INT_ACK_REG_KER_A1);
1333 falcon_readl(efx, ®, WORK_AROUND_BROKEN_PCI_READS_REG_KER_A1);
1336 /* Process a fatal interrupt
1337 * Disable bus mastering ASAP and schedule a reset
1339 static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1341 struct falcon_nic_data *nic_data = efx->nic_data;
1342 efx_oword_t *int_ker = efx->irq_status.addr;
1343 efx_oword_t fatal_intr;
1344 int error, mem_perr;
1345 static int n_int_errors;
1347 falcon_read(efx, &fatal_intr, FATAL_INTR_REG_KER);
1348 error = EFX_OWORD_FIELD(fatal_intr, INT_KER_ERROR);
1350 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
1351 EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker),
1352 EFX_OWORD_VAL(fatal_intr),
1353 error ? "disabling bus mastering" : "no recognised error");
1357 /* If this is a memory parity error dump which blocks are offending */
1358 mem_perr = EFX_OWORD_FIELD(fatal_intr, MEM_PERR_INT_KER);
1361 falcon_read(efx, ®, MEM_STAT_REG_KER);
1362 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1363 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1366 /* Disable DMA bus mastering on both devices */
1367 pci_disable_device(efx->pci_dev);
1368 if (FALCON_IS_DUAL_FUNC(efx))
1369 pci_disable_device(nic_data->pci_dev2);
1371 if (++n_int_errors < FALCON_MAX_INT_ERRORS) {
1372 EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n");
1373 efx_schedule_reset(efx, RESET_TYPE_INT_ERROR);
1375 EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen."
1376 "NIC will be disabled\n");
1377 efx_schedule_reset(efx, RESET_TYPE_DISABLE);
1383 /* Handle a legacy interrupt from Falcon
1384 * Acknowledges the interrupt and schedule event queue processing.
1386 static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1388 struct efx_nic *efx = dev_id;
1389 efx_oword_t *int_ker = efx->irq_status.addr;
1390 struct efx_channel *channel;
1395 /* Read the ISR which also ACKs the interrupts */
1396 falcon_readl(efx, ®, INT_ISR0_B0);
1397 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1399 /* Check to see if we have a serious error condition */
1400 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1401 if (unlikely(syserr))
1402 return falcon_fatal_interrupt(efx);
1407 efx->last_irq_cpu = raw_smp_processor_id();
1408 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n",
1409 irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg));
1411 /* Schedule processing of any interrupting queues */
1412 channel = &efx->channel[0];
1415 efx_schedule_channel(channel);
1424 static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
1426 struct efx_nic *efx = dev_id;
1427 efx_oword_t *int_ker = efx->irq_status.addr;
1428 struct efx_channel *channel;
1432 /* Check to see if this is our interrupt. If it isn't, we
1433 * exit without having touched the hardware.
1435 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
1436 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
1437 raw_smp_processor_id());
1440 efx->last_irq_cpu = raw_smp_processor_id();
1441 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1442 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1444 /* Check to see if we have a serious error condition */
1445 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1446 if (unlikely(syserr))
1447 return falcon_fatal_interrupt(efx);
1449 /* Determine interrupting queues, clear interrupt status
1450 * register and acknowledge the device interrupt.
1452 BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS);
1453 queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS);
1454 EFX_ZERO_OWORD(*int_ker);
1455 wmb(); /* Ensure the vector is cleared before interrupt ack */
1456 falcon_irq_ack_a1(efx);
1458 /* Schedule processing of any interrupting queues */
1459 channel = &efx->channel[0];
1462 efx_schedule_channel(channel);
1470 /* Handle an MSI interrupt from Falcon
1472 * Handle an MSI hardware interrupt. This routine schedules event
1473 * queue processing. No interrupt acknowledgement cycle is necessary.
1474 * Also, we never need to check that the interrupt is for us, since
1475 * MSI interrupts cannot be shared.
1477 static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id)
1479 struct efx_channel *channel = dev_id;
1480 struct efx_nic *efx = channel->efx;
1481 efx_oword_t *int_ker = efx->irq_status.addr;
1484 efx->last_irq_cpu = raw_smp_processor_id();
1485 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
1486 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
1488 /* Check to see if we have a serious error condition */
1489 syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT);
1490 if (unlikely(syserr))
1491 return falcon_fatal_interrupt(efx);
1493 /* Schedule processing of the channel */
1494 efx_schedule_channel(channel);
1500 /* Setup RSS indirection table.
1501 * This maps from the hash value of the packet to RXQ
1503 static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1506 unsigned long offset;
1509 if (falcon_rev(efx) < FALCON_REV_B0)
1512 for (offset = RX_RSS_INDIR_TBL_B0;
1513 offset < RX_RSS_INDIR_TBL_B0 + 0x800;
1515 EFX_POPULATE_DWORD_1(dword, RX_RSS_INDIR_ENT_B0,
1516 i % efx->n_rx_queues);
1517 falcon_writel(efx, &dword, offset);
1522 /* Hook interrupt handler(s)
1523 * Try MSI and then legacy interrupts.
1525 int falcon_init_interrupt(struct efx_nic *efx)
1527 struct efx_channel *channel;
1530 if (!EFX_INT_MODE_USE_MSI(efx)) {
1531 irq_handler_t handler;
1532 if (falcon_rev(efx) >= FALCON_REV_B0)
1533 handler = falcon_legacy_interrupt_b0;
1535 handler = falcon_legacy_interrupt_a1;
1537 rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED,
1540 EFX_ERR(efx, "failed to hook legacy IRQ %d\n",
1547 /* Hook MSI or MSI-X interrupt */
1548 efx_for_each_channel(channel, efx) {
1549 rc = request_irq(channel->irq, falcon_msi_interrupt,
1550 IRQF_PROBE_SHARED, /* Not shared */
1551 efx->name, channel);
1553 EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq);
1561 efx_for_each_channel(channel, efx)
1562 free_irq(channel->irq, channel);
1567 void falcon_fini_interrupt(struct efx_nic *efx)
1569 struct efx_channel *channel;
1572 /* Disable MSI/MSI-X interrupts */
1573 efx_for_each_channel(channel, efx) {
1575 free_irq(channel->irq, channel);
1578 /* ACK legacy interrupt */
1579 if (falcon_rev(efx) >= FALCON_REV_B0)
1580 falcon_read(efx, ®, INT_ISR0_B0);
1582 falcon_irq_ack_a1(efx);
1584 /* Disable legacy interrupt */
1585 if (efx->legacy_irq)
1586 free_irq(efx->legacy_irq, efx);
1589 /**************************************************************************
1593 **************************************************************************
1596 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
1598 /* Wait for SPI command completion */
1599 static int falcon_spi_wait(struct efx_nic *efx)
1601 unsigned long timeout = jiffies + DIV_ROUND_UP(HZ, 10);
1603 bool cmd_en, timer_active;
1606 falcon_read(efx, ®, EE_SPI_HCMD_REG_KER);
1607 cmd_en = EFX_OWORD_FIELD(reg, EE_SPI_HCMD_CMD_EN);
1608 timer_active = EFX_OWORD_FIELD(reg, EE_WR_TIMER_ACTIVE);
1609 if (!cmd_en && !timer_active)
1611 if (time_after_eq(jiffies, timeout)) {
1612 EFX_ERR(efx, "timed out waiting for SPI\n");
1619 static int falcon_spi_cmd(const struct efx_spi_device *spi,
1620 unsigned int command, int address,
1621 const void *in, void *out, unsigned int len)
1623 struct efx_nic *efx = spi->efx;
1624 bool addressed = (address >= 0);
1625 bool reading = (out != NULL);
1629 /* Input validation */
1630 if (len > FALCON_SPI_MAX_LEN)
1633 /* Check SPI not currently being accessed */
1634 rc = falcon_spi_wait(efx);
1638 /* Program address register, if we have an address */
1640 EFX_POPULATE_OWORD_1(reg, EE_SPI_HADR_ADR, address);
1641 falcon_write(efx, ®, EE_SPI_HADR_REG_KER);
1644 /* Program data register, if we have data */
1646 memcpy(®, in, len);
1647 falcon_write(efx, ®, EE_SPI_HDATA_REG_KER);
1650 /* Issue read/write command */
1651 EFX_POPULATE_OWORD_7(reg,
1652 EE_SPI_HCMD_CMD_EN, 1,
1653 EE_SPI_HCMD_SF_SEL, spi->device_id,
1654 EE_SPI_HCMD_DABCNT, len,
1655 EE_SPI_HCMD_READ, reading,
1656 EE_SPI_HCMD_DUBCNT, 0,
1658 (addressed ? spi->addr_len : 0),
1659 EE_SPI_HCMD_ENC, command);
1660 falcon_write(efx, ®, EE_SPI_HCMD_REG_KER);
1662 /* Wait for read/write to complete */
1663 rc = falcon_spi_wait(efx);
1669 falcon_read(efx, ®, EE_SPI_HDATA_REG_KER);
1670 memcpy(out, ®, len);
1677 falcon_spi_write_limit(const struct efx_spi_device *spi, unsigned int start)
1679 return min(FALCON_SPI_MAX_LEN,
1680 (spi->block_size - (start & (spi->block_size - 1))));
1684 efx_spi_munge_command(const struct efx_spi_device *spi,
1685 const u8 command, const unsigned int address)
1687 return command | (((address >> 8) & spi->munge_address) << 3);
1691 static int falcon_spi_fast_wait(const struct efx_spi_device *spi)
1696 /* Wait up to 1000us for flash/EEPROM to finish a fast operation. */
1697 for (i = 0; i < 50; i++) {
1700 rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL,
1701 &status, sizeof(status));
1704 if (!(status & SPI_STATUS_NRDY))
1708 "timed out waiting for device %d last status=0x%02x\n",
1709 spi->device_id, status);
1713 int falcon_spi_read(const struct efx_spi_device *spi, loff_t start,
1714 size_t len, size_t *retlen, u8 *buffer)
1716 unsigned int command, block_len, pos = 0;
1720 block_len = min((unsigned int)len - pos,
1721 FALCON_SPI_MAX_LEN);
1723 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1724 rc = falcon_spi_cmd(spi, command, start + pos, NULL,
1725 buffer + pos, block_len);
1730 /* Avoid locking up the system */
1732 if (signal_pending(current)) {
1743 int falcon_spi_write(const struct efx_spi_device *spi, loff_t start,
1744 size_t len, size_t *retlen, const u8 *buffer)
1746 u8 verify_buffer[FALCON_SPI_MAX_LEN];
1747 unsigned int command, block_len, pos = 0;
1751 rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0);
1755 block_len = min((unsigned int)len - pos,
1756 falcon_spi_write_limit(spi, start + pos));
1757 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
1758 rc = falcon_spi_cmd(spi, command, start + pos,
1759 buffer + pos, NULL, block_len);
1763 rc = falcon_spi_fast_wait(spi);
1767 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
1768 rc = falcon_spi_cmd(spi, command, start + pos,
1769 NULL, verify_buffer, block_len);
1770 if (memcmp(verify_buffer, buffer + pos, block_len)) {
1777 /* Avoid locking up the system */
1779 if (signal_pending(current)) {
1790 /**************************************************************************
1794 **************************************************************************
1796 void falcon_drain_tx_fifo(struct efx_nic *efx)
1801 if ((falcon_rev(efx) < FALCON_REV_B0) ||
1802 (efx->loopback_mode != LOOPBACK_NONE))
1805 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1806 /* There is no point in draining more than once */
1807 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1810 /* MAC stats will fail whilst the TX fifo is draining. Serialise
1811 * the drain sequence with the statistics fetch */
1812 spin_lock(&efx->stats_lock);
1814 EFX_SET_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0, 1);
1815 falcon_write(efx, &temp, MAC0_CTRL_REG_KER);
1817 /* Reset the MAC and EM block. */
1818 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1819 EFX_SET_OWORD_FIELD(temp, RST_XGTX, 1);
1820 EFX_SET_OWORD_FIELD(temp, RST_XGRX, 1);
1821 EFX_SET_OWORD_FIELD(temp, RST_EM, 1);
1822 falcon_write(efx, &temp, GLB_CTL_REG_KER);
1826 falcon_read(efx, &temp, GLB_CTL_REG_KER);
1827 if (!EFX_OWORD_FIELD(temp, RST_XGTX) &&
1828 !EFX_OWORD_FIELD(temp, RST_XGRX) &&
1829 !EFX_OWORD_FIELD(temp, RST_EM)) {
1830 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
1835 EFX_ERR(efx, "MAC reset failed\n");
1842 spin_unlock(&efx->stats_lock);
1844 /* If we've reset the EM block and the link is up, then
1845 * we'll have to kick the XAUI link so the PHY can recover */
1846 if (efx->link_up && EFX_WORKAROUND_5147(efx))
1847 falcon_reset_xaui(efx);
1850 void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1854 if (falcon_rev(efx) < FALCON_REV_B0)
1857 /* Isolate the MAC -> RX */
1858 falcon_read(efx, &temp, RX_CFG_REG_KER);
1859 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 0);
1860 falcon_write(efx, &temp, RX_CFG_REG_KER);
1863 falcon_drain_tx_fifo(efx);
1866 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
1872 if (efx->link_options & GM_LPA_10000)
1874 else if (efx->link_options & GM_LPA_1000)
1876 else if (efx->link_options & GM_LPA_100)
1880 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
1881 * as advertised. Disable to ensure packets are not
1882 * indefinitely held and TX queue can be flushed at any point
1883 * while the link is down. */
1884 EFX_POPULATE_OWORD_5(reg,
1885 MAC_XOFF_VAL, 0xffff /* max pause time */,
1887 MAC_UC_PROM, efx->promiscuous,
1888 MAC_LINK_STATUS, 1, /* always set */
1889 MAC_SPEED, link_speed);
1890 /* On B0, MAC backpressure can be disabled and packets get
1892 if (falcon_rev(efx) >= FALCON_REV_B0) {
1893 EFX_SET_OWORD_FIELD(reg, TXFIFO_DRAIN_EN_B0,
1897 falcon_write(efx, ®, MAC0_CTRL_REG_KER);
1899 /* Restore the multicast hash registers. */
1900 falcon_set_multicast_hash(efx);
1902 /* Transmission of pause frames when RX crosses the threshold is
1903 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
1904 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
1905 tx_fc = !!(efx->flow_control & EFX_FC_TX);
1906 falcon_read(efx, ®, RX_CFG_REG_KER);
1907 EFX_SET_OWORD_FIELD_VER(efx, reg, RX_XOFF_MAC_EN, tx_fc);
1909 /* Unisolate the MAC -> RX */
1910 if (falcon_rev(efx) >= FALCON_REV_B0)
1911 EFX_SET_OWORD_FIELD(reg, RX_INGR_EN_B0, 1);
1912 falcon_write(efx, ®, RX_CFG_REG_KER);
1915 int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
1921 if (disable_dma_stats)
1924 /* Statistics fetch will fail if the MAC is in TX drain */
1925 if (falcon_rev(efx) >= FALCON_REV_B0) {
1927 falcon_read(efx, &temp, MAC0_CTRL_REG_KER);
1928 if (EFX_OWORD_FIELD(temp, TXFIFO_DRAIN_EN_B0))
1932 dma_done = (efx->stats_buffer.addr + done_offset);
1933 *dma_done = FALCON_STATS_NOT_DONE;
1934 wmb(); /* ensure done flag is clear */
1936 /* Initiate DMA transfer of stats */
1937 EFX_POPULATE_OWORD_2(reg,
1938 MAC_STAT_DMA_CMD, 1,
1940 efx->stats_buffer.dma_addr);
1941 falcon_write(efx, ®, MAC0_STAT_DMA_REG_KER);
1943 /* Wait for transfer to complete */
1944 for (i = 0; i < 400; i++) {
1945 if (*(volatile u32 *)dma_done == FALCON_STATS_DONE)
1950 EFX_ERR(efx, "timed out waiting for statistics\n");
1954 /**************************************************************************
1956 * PHY access via GMII
1958 **************************************************************************
1961 /* Use the top bit of the MII PHY id to indicate the PHY type
1962 * (1G/10G), with the remaining bits as the actual PHY id.
1964 * This allows us to avoid leaking information from the mii_if_info
1965 * structure into other data structures.
1967 #define FALCON_PHY_ID_ID_WIDTH EFX_WIDTH(MD_PRT_DEV_ADR)
1968 #define FALCON_PHY_ID_ID_MASK ((1 << FALCON_PHY_ID_ID_WIDTH) - 1)
1969 #define FALCON_PHY_ID_WIDTH (FALCON_PHY_ID_ID_WIDTH + 1)
1970 #define FALCON_PHY_ID_MASK ((1 << FALCON_PHY_ID_WIDTH) - 1)
1971 #define FALCON_PHY_ID_10G (1 << (FALCON_PHY_ID_WIDTH - 1))
1974 /* Packing the clause 45 port and device fields into a single value */
1975 #define MD_PRT_ADR_COMP_LBN (MD_PRT_ADR_LBN - MD_DEV_ADR_LBN)
1976 #define MD_PRT_ADR_COMP_WIDTH MD_PRT_ADR_WIDTH
1977 #define MD_DEV_ADR_COMP_LBN 0
1978 #define MD_DEV_ADR_COMP_WIDTH MD_DEV_ADR_WIDTH
1981 /* Wait for GMII access to complete */
1982 static int falcon_gmii_wait(struct efx_nic *efx)
1984 efx_dword_t md_stat;
1987 for (count = 0; count < 1000; count++) { /* wait upto 10ms */
1988 falcon_readl(efx, &md_stat, MD_STAT_REG_KER);
1989 if (EFX_DWORD_FIELD(md_stat, MD_BSY) == 0) {
1990 if (EFX_DWORD_FIELD(md_stat, MD_LNFL) != 0 ||
1991 EFX_DWORD_FIELD(md_stat, MD_BSERR) != 0) {
1992 EFX_ERR(efx, "error from GMII access "
1994 EFX_DWORD_VAL(md_stat));
2001 EFX_ERR(efx, "timed out waiting for GMII\n");
2005 /* Writes a GMII register of a PHY connected to Falcon using MDIO. */
2006 static void falcon_mdio_write(struct net_device *net_dev, int phy_id,
2007 int addr, int value)
2009 struct efx_nic *efx = netdev_priv(net_dev);
2010 unsigned int phy_id2 = phy_id & FALCON_PHY_ID_ID_MASK;
2013 /* The 'generic' prt/dev packing in mdio_10g.h is conveniently
2014 * chosen so that the only current user, Falcon, can take the
2015 * packed value and use them directly.
2016 * Fail to build if this assumption is broken.
2018 BUILD_BUG_ON(FALCON_PHY_ID_10G != MDIO45_XPRT_ID_IS10G);
2019 BUILD_BUG_ON(FALCON_PHY_ID_ID_WIDTH != MDIO45_PRT_DEV_WIDTH);
2020 BUILD_BUG_ON(MD_PRT_ADR_COMP_LBN != MDIO45_PRT_ID_COMP_LBN);
2021 BUILD_BUG_ON(MD_DEV_ADR_COMP_LBN != MDIO45_DEV_ID_COMP_LBN);
2023 if (phy_id2 == PHY_ADDR_INVALID)
2026 /* See falcon_mdio_read for an explanation. */
2027 if (!(phy_id & FALCON_PHY_ID_10G)) {
2028 int mmd = ffs(efx->phy_op->mmds) - 1;
2029 EFX_TRACE(efx, "Fixing erroneous clause22 write\n");
2030 phy_id2 = mdio_clause45_pack(phy_id2, mmd)
2031 & FALCON_PHY_ID_ID_MASK;
2034 EFX_REGDUMP(efx, "writing GMII %d register %02x with %04x\n", phy_id,
2037 spin_lock_bh(&efx->phy_lock);
2039 /* Check MII not currently being accessed */
2040 if (falcon_gmii_wait(efx) != 0)
2043 /* Write the address/ID register */
2044 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2045 falcon_write(efx, ®, MD_PHY_ADR_REG_KER);
2047 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_id2);
2048 falcon_write(efx, ®, MD_ID_REG_KER);
2051 EFX_POPULATE_OWORD_1(reg, MD_TXD, value);
2052 falcon_write(efx, ®, MD_TXD_REG_KER);
2054 EFX_POPULATE_OWORD_2(reg,
2057 falcon_write(efx, ®, MD_CS_REG_KER);
2059 /* Wait for data to be written */
2060 if (falcon_gmii_wait(efx) != 0) {
2061 /* Abort the write operation */
2062 EFX_POPULATE_OWORD_2(reg,
2065 falcon_write(efx, ®, MD_CS_REG_KER);
2070 spin_unlock_bh(&efx->phy_lock);
2073 /* Reads a GMII register from a PHY connected to Falcon. If no value
2074 * could be read, -1 will be returned. */
2075 static int falcon_mdio_read(struct net_device *net_dev, int phy_id, int addr)
2077 struct efx_nic *efx = netdev_priv(net_dev);
2078 unsigned int phy_addr = phy_id & FALCON_PHY_ID_ID_MASK;
2082 if (phy_addr == PHY_ADDR_INVALID)
2085 /* Our PHY code knows whether it needs to talk clause 22(1G) or 45(10G)
2086 * but the generic Linux code does not make any distinction or have
2087 * any state for this.
2088 * We spot the case where someone tried to talk 22 to a 45 PHY and
2089 * redirect the request to the lowest numbered MMD as a clause45
2090 * request. This is enough to allow simple queries like id and link
2091 * state to succeed. TODO: We may need to do more in future.
2093 if (!(phy_id & FALCON_PHY_ID_10G)) {
2094 int mmd = ffs(efx->phy_op->mmds) - 1;
2095 EFX_TRACE(efx, "Fixing erroneous clause22 read\n");
2096 phy_addr = mdio_clause45_pack(phy_addr, mmd)
2097 & FALCON_PHY_ID_ID_MASK;
2100 spin_lock_bh(&efx->phy_lock);
2102 /* Check MII not currently being accessed */
2103 if (falcon_gmii_wait(efx) != 0)
2106 EFX_POPULATE_OWORD_1(reg, MD_PHY_ADR, addr);
2107 falcon_write(efx, ®, MD_PHY_ADR_REG_KER);
2109 EFX_POPULATE_OWORD_1(reg, MD_PRT_DEV_ADR, phy_addr);
2110 falcon_write(efx, ®, MD_ID_REG_KER);
2112 /* Request data to be read */
2113 EFX_POPULATE_OWORD_2(reg, MD_RDC, 1, MD_GC, 0);
2114 falcon_write(efx, ®, MD_CS_REG_KER);
2116 /* Wait for data to become available */
2117 value = falcon_gmii_wait(efx);
2119 falcon_read(efx, ®, MD_RXD_REG_KER);
2120 value = EFX_OWORD_FIELD(reg, MD_RXD);
2121 EFX_REGDUMP(efx, "read from GMII %d register %02x, got %04x\n",
2122 phy_id, addr, value);
2124 /* Abort the read operation */
2125 EFX_POPULATE_OWORD_2(reg,
2128 falcon_write(efx, ®, MD_CS_REG_KER);
2130 EFX_LOG(efx, "read from GMII 0x%x register %02x, got "
2131 "error %d\n", phy_id, addr, value);
2135 spin_unlock_bh(&efx->phy_lock);
2140 static void falcon_init_mdio(struct mii_if_info *gmii)
2142 gmii->mdio_read = falcon_mdio_read;
2143 gmii->mdio_write = falcon_mdio_write;
2144 gmii->phy_id_mask = FALCON_PHY_ID_MASK;
2145 gmii->reg_num_mask = ((1 << EFX_WIDTH(MD_PHY_ADR)) - 1);
2148 static int falcon_probe_phy(struct efx_nic *efx)
2150 switch (efx->phy_type) {
2151 case PHY_TYPE_10XPRESS:
2152 efx->phy_op = &falcon_tenxpress_phy_ops;
2155 efx->phy_op = &falcon_xfp_phy_ops;
2158 EFX_ERR(efx, "Unknown PHY type %d\n",
2163 efx->loopback_modes = LOOPBACKS_10G_INTERNAL | efx->phy_op->loopbacks;
2167 /* This call is responsible for hooking in the MAC and PHY operations */
2168 int falcon_probe_port(struct efx_nic *efx)
2172 /* Hook in PHY operations table */
2173 rc = falcon_probe_phy(efx);
2177 /* Set up GMII structure for PHY */
2178 efx->mii.supports_gmii = true;
2179 falcon_init_mdio(&efx->mii);
2181 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
2182 if (falcon_rev(efx) >= FALCON_REV_B0)
2183 efx->flow_control = EFX_FC_RX | EFX_FC_TX;
2185 efx->flow_control = EFX_FC_RX;
2187 /* Allocate buffer for stats */
2188 rc = falcon_alloc_buffer(efx, &efx->stats_buffer,
2189 FALCON_MAC_STATS_SIZE);
2192 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %lx)\n",
2193 (unsigned long long)efx->stats_buffer.dma_addr,
2194 efx->stats_buffer.addr,
2195 virt_to_phys(efx->stats_buffer.addr));
2200 void falcon_remove_port(struct efx_nic *efx)
2202 falcon_free_buffer(efx, &efx->stats_buffer);
2205 /**************************************************************************
2207 * Multicast filtering
2209 **************************************************************************
2212 void falcon_set_multicast_hash(struct efx_nic *efx)
2214 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
2216 /* Broadcast packets go through the multicast hash filter.
2217 * ether_crc_le() of the broadcast address is 0xbe2612ff
2218 * so we always add bit 0xff to the mask.
2220 set_bit_le(0xff, mc_hash->byte);
2222 falcon_write(efx, &mc_hash->oword[0], MAC_MCAST_HASH_REG0_KER);
2223 falcon_write(efx, &mc_hash->oword[1], MAC_MCAST_HASH_REG1_KER);
2227 /**************************************************************************
2231 **************************************************************************/
2233 int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
2235 struct falcon_nvconfig *nvconfig;
2236 struct efx_spi_device *spi;
2238 int rc, magic_num, struct_ver;
2239 __le16 *word, *limit;
2242 region = kmalloc(NVCONFIG_END, GFP_KERNEL);
2245 nvconfig = region + NVCONFIG_OFFSET;
2247 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
2248 rc = falcon_spi_read(spi, 0, NVCONFIG_END, NULL, region);
2250 EFX_ERR(efx, "Failed to read %s\n",
2251 efx->spi_flash ? "flash" : "EEPROM");
2256 magic_num = le16_to_cpu(nvconfig->board_magic_num);
2257 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
2260 if (magic_num != NVCONFIG_BOARD_MAGIC_NUM) {
2261 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
2264 if (struct_ver < 2) {
2265 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
2267 } else if (struct_ver < 4) {
2268 word = &nvconfig->board_magic_num;
2269 limit = (__le16 *) (nvconfig + 1);
2272 limit = region + NVCONFIG_END;
2274 for (csum = 0; word < limit; ++word)
2275 csum += le16_to_cpu(*word);
2277 if (~csum & 0xffff) {
2278 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
2284 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
2291 /* Registers tested in the falcon register test */
2295 } efx_test_registers[] = {
2296 { ADR_REGION_REG_KER,
2297 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
2299 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
2301 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
2303 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
2304 { MAC0_CTRL_REG_KER,
2305 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
2306 { SRM_TX_DC_CFG_REG_KER,
2307 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
2308 { RX_DC_CFG_REG_KER,
2309 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
2310 { RX_DC_PF_WM_REG_KER,
2311 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
2313 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
2315 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
2317 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
2319 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
2321 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
2323 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
2325 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
2327 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
2330 static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b,
2331 const efx_oword_t *mask)
2333 return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) ||
2334 ((a->u64[1] ^ b->u64[1]) & mask->u64[1]);
2337 int falcon_test_registers(struct efx_nic *efx)
2339 unsigned address = 0, i, j;
2340 efx_oword_t mask, imask, original, reg, buf;
2342 /* Falcon should be in loopback to isolate the XMAC from the PHY */
2343 WARN_ON(!LOOPBACK_INTERNAL(efx));
2345 for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) {
2346 address = efx_test_registers[i].address;
2347 mask = imask = efx_test_registers[i].mask;
2348 EFX_INVERT_OWORD(imask);
2350 falcon_read(efx, &original, address);
2352 /* bit sweep on and off */
2353 for (j = 0; j < 128; j++) {
2354 if (!EFX_EXTRACT_OWORD32(mask, j, j))
2357 /* Test this testable bit can be set in isolation */
2358 EFX_AND_OWORD(reg, original, mask);
2359 EFX_SET_OWORD32(reg, j, j, 1);
2361 falcon_write(efx, ®, address);
2362 falcon_read(efx, &buf, address);
2364 if (efx_masked_compare_oword(®, &buf, &mask))
2367 /* Test this testable bit can be cleared in isolation */
2368 EFX_OR_OWORD(reg, original, mask);
2369 EFX_SET_OWORD32(reg, j, j, 0);
2371 falcon_write(efx, ®, address);
2372 falcon_read(efx, &buf, address);
2374 if (efx_masked_compare_oword(®, &buf, &mask))
2378 falcon_write(efx, &original, address);
2384 EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT
2385 " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg),
2386 EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask));
2390 /**************************************************************************
2394 **************************************************************************
2397 /* Resets NIC to known state. This routine must be called in process
2398 * context and is allowed to sleep. */
2399 int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2401 struct falcon_nic_data *nic_data = efx->nic_data;
2402 efx_oword_t glb_ctl_reg_ker;
2405 EFX_LOG(efx, "performing hardware reset (%d)\n", method);
2407 /* Initiate device reset */
2408 if (method == RESET_TYPE_WORLD) {
2409 rc = pci_save_state(efx->pci_dev);
2411 EFX_ERR(efx, "failed to backup PCI state of primary "
2412 "function prior to hardware reset\n");
2415 if (FALCON_IS_DUAL_FUNC(efx)) {
2416 rc = pci_save_state(nic_data->pci_dev2);
2418 EFX_ERR(efx, "failed to backup PCI state of "
2419 "secondary function prior to "
2420 "hardware reset\n");
2425 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
2426 EXT_PHY_RST_DUR, 0x7,
2429 int reset_phy = (method == RESET_TYPE_INVISIBLE ?
2430 EXCLUDE_FROM_RESET : 0);
2432 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
2433 EXT_PHY_RST_CTL, reset_phy,
2434 PCIE_CORE_RST_CTL, EXCLUDE_FROM_RESET,
2435 PCIE_NSTCK_RST_CTL, EXCLUDE_FROM_RESET,
2436 PCIE_SD_RST_CTL, EXCLUDE_FROM_RESET,
2437 EE_RST_CTL, EXCLUDE_FROM_RESET,
2438 EXT_PHY_RST_DUR, 0x7 /* 10ms */,
2441 falcon_write(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2443 EFX_LOG(efx, "waiting for hardware reset\n");
2444 schedule_timeout_uninterruptible(HZ / 20);
2446 /* Restore PCI configuration if needed */
2447 if (method == RESET_TYPE_WORLD) {
2448 if (FALCON_IS_DUAL_FUNC(efx)) {
2449 rc = pci_restore_state(nic_data->pci_dev2);
2451 EFX_ERR(efx, "failed to restore PCI config for "
2452 "the secondary function\n");
2456 rc = pci_restore_state(efx->pci_dev);
2458 EFX_ERR(efx, "failed to restore PCI config for the "
2459 "primary function\n");
2462 EFX_LOG(efx, "successfully restored PCI config\n");
2465 /* Assert that reset complete */
2466 falcon_read(efx, &glb_ctl_reg_ker, GLB_CTL_REG_KER);
2467 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, SWRST) != 0) {
2469 EFX_ERR(efx, "timed out waiting for hardware reset\n");
2472 EFX_LOG(efx, "hardware reset complete\n");
2476 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
2479 pci_restore_state(efx->pci_dev);
2486 /* Zeroes out the SRAM contents. This routine must be called in
2487 * process context and is allowed to sleep.
2489 static int falcon_reset_sram(struct efx_nic *efx)
2491 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
2494 /* Set the SRAM wake/sleep GPIO appropriately. */
2495 falcon_read(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2496 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OEN, 1);
2497 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, GPIO1_OUT, 1);
2498 falcon_write(efx, &gpio_cfg_reg_ker, GPIO_CTL_REG_KER);
2500 /* Initiate SRAM reset */
2501 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2502 SRAM_OOB_BT_INIT_EN, 1,
2503 SRM_NUM_BANKS_AND_BANK_SIZE, 0);
2504 falcon_write(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2506 /* Wait for SRAM reset to complete */
2509 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
2511 /* SRAM reset is slow; expect around 16ms */
2512 schedule_timeout_uninterruptible(HZ / 50);
2514 /* Check for reset complete */
2515 falcon_read(efx, &srm_cfg_reg_ker, SRM_CFG_REG_KER);
2516 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, SRAM_OOB_BT_INIT_EN)) {
2517 EFX_LOG(efx, "SRAM reset complete\n");
2521 } while (++count < 20); /* wait upto 0.4 sec */
2523 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
2527 static int falcon_spi_device_init(struct efx_nic *efx,
2528 struct efx_spi_device **spi_device_ret,
2529 unsigned int device_id, u32 device_type)
2531 struct efx_spi_device *spi_device;
2533 if (device_type != 0) {
2534 spi_device = kmalloc(sizeof(*spi_device), GFP_KERNEL);
2537 spi_device->device_id = device_id;
2539 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
2540 spi_device->addr_len =
2541 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
2542 spi_device->munge_address = (spi_device->size == 1 << 9 &&
2543 spi_device->addr_len == 1);
2544 spi_device->block_size =
2545 1 << SPI_DEV_TYPE_FIELD(device_type,
2546 SPI_DEV_TYPE_BLOCK_SIZE);
2548 spi_device->efx = efx;
2553 kfree(*spi_device_ret);
2554 *spi_device_ret = spi_device;
2559 static void falcon_remove_spi_devices(struct efx_nic *efx)
2561 kfree(efx->spi_eeprom);
2562 efx->spi_eeprom = NULL;
2563 kfree(efx->spi_flash);
2564 efx->spi_flash = NULL;
2567 /* Extract non-volatile configuration */
2568 static int falcon_probe_nvconfig(struct efx_nic *efx)
2570 struct falcon_nvconfig *nvconfig;
2574 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
2578 rc = falcon_read_nvram(efx, nvconfig);
2579 if (rc == -EINVAL) {
2580 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
2581 efx->phy_type = PHY_TYPE_NONE;
2582 efx->mii.phy_id = PHY_ADDR_INVALID;
2588 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
2589 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
2591 efx->phy_type = v2->port0_phy_type;
2592 efx->mii.phy_id = v2->port0_phy_addr;
2593 board_rev = le16_to_cpu(v2->board_revision);
2595 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
2596 __le32 fl = v3->spi_device_type[EE_SPI_FLASH];
2597 __le32 ee = v3->spi_device_type[EE_SPI_EEPROM];
2598 rc = falcon_spi_device_init(efx, &efx->spi_flash,
2603 rc = falcon_spi_device_init(efx, &efx->spi_eeprom,
2611 /* Read the MAC addresses */
2612 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
2614 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mii.phy_id);
2616 efx_set_board_info(efx, board_rev);
2622 falcon_remove_spi_devices(efx);
2628 /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port
2629 * count, port speed). Set workaround and feature flags accordingly.
2631 static int falcon_probe_nic_variant(struct efx_nic *efx)
2633 efx_oword_t altera_build;
2635 falcon_read(efx, &altera_build, ALTERA_BUILD_REG_KER);
2636 if (EFX_OWORD_FIELD(altera_build, VER_ALL)) {
2637 EFX_ERR(efx, "Falcon FPGA not supported\n");
2641 switch (falcon_rev(efx)) {
2644 EFX_ERR(efx, "Falcon rev A0 not supported\n");
2647 case FALCON_REV_A1:{
2648 efx_oword_t nic_stat;
2650 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2652 if (EFX_OWORD_FIELD(nic_stat, STRAP_PCIE) == 0) {
2653 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
2656 if (!EFX_OWORD_FIELD(nic_stat, STRAP_10G)) {
2657 EFX_ERR(efx, "1G mode not supported\n");
2667 EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
2674 /* Probe all SPI devices on the NIC */
2675 static void falcon_probe_spi_devices(struct efx_nic *efx)
2677 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2678 bool has_flash, has_eeprom, boot_is_external;
2680 falcon_read(efx, &gpio_ctl, GPIO_CTL_REG_KER);
2681 falcon_read(efx, &nic_stat, NIC_STAT_REG);
2682 falcon_read(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2684 has_flash = EFX_OWORD_FIELD(nic_stat, SF_PRST);
2685 has_eeprom = EFX_OWORD_FIELD(nic_stat, EE_PRST);
2686 boot_is_external = EFX_OWORD_FIELD(gpio_ctl, BOOTED_USING_NVDEVICE);
2689 /* Default flash SPI device: Atmel AT25F1024
2690 * 128 KB, 24-bit address, 32 KB erase block,
2693 u32 flash_device_type =
2694 (17 << SPI_DEV_TYPE_SIZE_LBN)
2695 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2696 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
2697 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
2698 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2700 falcon_spi_device_init(efx, &efx->spi_flash,
2701 EE_SPI_FLASH, flash_device_type);
2703 if (!boot_is_external) {
2704 /* Disable VPD and set clock dividers to safe
2705 * values for initial programming.
2707 EFX_LOG(efx, "Booted from internal ASIC settings;"
2708 " setting SPI config\n");
2709 EFX_POPULATE_OWORD_3(ee_vpd_cfg, EE_VPD_EN, 0,
2710 /* 125 MHz / 7 ~= 20 MHz */
2712 /* 125 MHz / 63 ~= 2 MHz */
2713 EE_EE_CLOCK_DIV, 63);
2714 falcon_write(efx, &ee_vpd_cfg, EE_VPD_CFG_REG_KER);
2719 u32 eeprom_device_type;
2721 /* If it has no flash, it must have a large EEPROM
2722 * for chip config; otherwise check whether 9-bit
2723 * addressing is used for VPD configuration
2726 (!boot_is_external ||
2727 EFX_OWORD_FIELD(ee_vpd_cfg, EE_VPD_EN_AD9_MODE))) {
2728 /* Default SPI device: Atmel AT25040 or similar
2729 * 512 B, 9-bit address, 8 B write block
2731 eeprom_device_type =
2732 (9 << SPI_DEV_TYPE_SIZE_LBN)
2733 | (1 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2734 | (3 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2736 /* "Large" SPI device: Atmel AT25640 or similar
2737 * 8 KB, 16-bit address, 32 B write block
2739 eeprom_device_type =
2740 (13 << SPI_DEV_TYPE_SIZE_LBN)
2741 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
2742 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN);
2745 falcon_spi_device_init(efx, &efx->spi_eeprom,
2746 EE_SPI_EEPROM, eeprom_device_type);
2749 EFX_LOG(efx, "flash is %s, EEPROM is %s\n",
2750 (has_flash ? "present" : "absent"),
2751 (has_eeprom ? "present" : "absent"));
2754 int falcon_probe_nic(struct efx_nic *efx)
2756 struct falcon_nic_data *nic_data;
2759 /* Allocate storage for hardware specific data */
2760 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
2761 efx->nic_data = nic_data;
2763 /* Determine number of ports etc. */
2764 rc = falcon_probe_nic_variant(efx);
2768 /* Probe secondary function if expected */
2769 if (FALCON_IS_DUAL_FUNC(efx)) {
2770 struct pci_dev *dev = pci_dev_get(efx->pci_dev);
2772 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
2774 if (dev->bus == efx->pci_dev->bus &&
2775 dev->devfn == efx->pci_dev->devfn + 1) {
2776 nic_data->pci_dev2 = dev;
2780 if (!nic_data->pci_dev2) {
2781 EFX_ERR(efx, "failed to find secondary function\n");
2787 /* Now we can reset the NIC */
2788 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
2790 EFX_ERR(efx, "failed to reset NIC\n");
2794 /* Allocate memory for INT_KER */
2795 rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
2798 BUG_ON(efx->irq_status.dma_addr & 0x0f);
2800 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %lx)\n",
2801 (unsigned long long)efx->irq_status.dma_addr,
2802 efx->irq_status.addr, virt_to_phys(efx->irq_status.addr));
2804 falcon_probe_spi_devices(efx);
2806 /* Read in the non-volatile configuration */
2807 rc = falcon_probe_nvconfig(efx);
2811 /* Initialise I2C adapter */
2812 efx->i2c_adap.owner = THIS_MODULE;
2813 nic_data->i2c_data = falcon_i2c_bit_operations;
2814 nic_data->i2c_data.data = efx;
2815 efx->i2c_adap.algo_data = &nic_data->i2c_data;
2816 efx->i2c_adap.dev.parent = &efx->pci_dev->dev;
2817 strlcpy(efx->i2c_adap.name, "SFC4000 GPIO", sizeof(efx->i2c_adap.name));
2818 rc = i2c_bit_add_bus(&efx->i2c_adap);
2825 falcon_remove_spi_devices(efx);
2826 falcon_free_buffer(efx, &efx->irq_status);
2829 if (nic_data->pci_dev2) {
2830 pci_dev_put(nic_data->pci_dev2);
2831 nic_data->pci_dev2 = NULL;
2835 kfree(efx->nic_data);
2839 /* This call performs hardware-specific global initialisation, such as
2840 * defining the descriptor cache sizes and number of RSS channels.
2841 * It does not set up any buffers, descriptor rings or event queues.
2843 int falcon_init_nic(struct efx_nic *efx)
2849 /* Set up the address region register. This is only needed
2850 * for the B0 FPGA, but since we are just pushing in the
2851 * reset defaults this may as well be unconditional. */
2852 EFX_POPULATE_OWORD_4(temp, ADR_REGION0, 0,
2853 ADR_REGION1, (1 << 16),
2854 ADR_REGION2, (2 << 16),
2855 ADR_REGION3, (3 << 16));
2856 falcon_write(efx, &temp, ADR_REGION_REG_KER);
2858 /* Use on-chip SRAM */
2859 falcon_read(efx, &temp, NIC_STAT_REG);
2860 EFX_SET_OWORD_FIELD(temp, ONCHIP_SRAM, 1);
2861 falcon_write(efx, &temp, NIC_STAT_REG);
2863 /* Set buffer table mode */
2864 EFX_POPULATE_OWORD_1(temp, BUF_TBL_MODE, BUF_TBL_MODE_FULL);
2865 falcon_write(efx, &temp, BUF_TBL_CFG_REG_KER);
2867 rc = falcon_reset_sram(efx);
2871 /* Set positions of descriptor caches in SRAM. */
2872 EFX_POPULATE_OWORD_1(temp, SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
2873 falcon_write(efx, &temp, SRM_TX_DC_CFG_REG_KER);
2874 EFX_POPULATE_OWORD_1(temp, SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
2875 falcon_write(efx, &temp, SRM_RX_DC_CFG_REG_KER);
2877 /* Set TX descriptor cache size. */
2878 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
2879 EFX_POPULATE_OWORD_1(temp, TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
2880 falcon_write(efx, &temp, TX_DC_CFG_REG_KER);
2882 /* Set RX descriptor cache size. Set low watermark to size-8, as
2883 * this allows most efficient prefetching.
2885 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
2886 EFX_POPULATE_OWORD_1(temp, RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
2887 falcon_write(efx, &temp, RX_DC_CFG_REG_KER);
2888 EFX_POPULATE_OWORD_1(temp, RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
2889 falcon_write(efx, &temp, RX_DC_PF_WM_REG_KER);
2891 /* Clear the parity enables on the TX data fifos as
2892 * they produce false parity errors because of timing issues
2894 if (EFX_WORKAROUND_5129(efx)) {
2895 falcon_read(efx, &temp, SPARE_REG_KER);
2896 EFX_SET_OWORD_FIELD(temp, MEM_PERR_EN_TX_DATA, 0);
2897 falcon_write(efx, &temp, SPARE_REG_KER);
2900 /* Enable all the genuinely fatal interrupts. (They are still
2901 * masked by the overall interrupt mask, controlled by
2902 * falcon_interrupts()).
2904 * Note: All other fatal interrupts are enabled
2906 EFX_POPULATE_OWORD_3(temp,
2907 ILL_ADR_INT_KER_EN, 1,
2908 RBUF_OWN_INT_KER_EN, 1,
2909 TBUF_OWN_INT_KER_EN, 1);
2910 EFX_INVERT_OWORD(temp);
2911 falcon_write(efx, &temp, FATAL_INTR_REG_KER);
2913 if (EFX_WORKAROUND_7244(efx)) {
2914 falcon_read(efx, &temp, RX_FILTER_CTL_REG);
2915 EFX_SET_OWORD_FIELD(temp, UDP_FULL_SRCH_LIMIT, 8);
2916 EFX_SET_OWORD_FIELD(temp, UDP_WILD_SRCH_LIMIT, 8);
2917 EFX_SET_OWORD_FIELD(temp, TCP_FULL_SRCH_LIMIT, 8);
2918 EFX_SET_OWORD_FIELD(temp, TCP_WILD_SRCH_LIMIT, 8);
2919 falcon_write(efx, &temp, RX_FILTER_CTL_REG);
2922 falcon_setup_rss_indir_table(efx);
2924 /* Setup RX. Wait for descriptor is broken and must
2925 * be disabled. RXDP recovery shouldn't be needed, but is.
2927 falcon_read(efx, &temp, RX_SELF_RST_REG_KER);
2928 EFX_SET_OWORD_FIELD(temp, RX_NODESC_WAIT_DIS, 1);
2929 EFX_SET_OWORD_FIELD(temp, RX_RECOVERY_EN, 1);
2930 if (EFX_WORKAROUND_5583(efx))
2931 EFX_SET_OWORD_FIELD(temp, RX_ISCSI_DIS, 1);
2932 falcon_write(efx, &temp, RX_SELF_RST_REG_KER);
2934 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
2935 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
2937 falcon_read(efx, &temp, TX_CFG2_REG_KER);
2938 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER, 0xfe);
2939 EFX_SET_OWORD_FIELD(temp, TX_RX_SPACER_EN, 1);
2940 EFX_SET_OWORD_FIELD(temp, TX_ONE_PKT_PER_Q, 1);
2941 EFX_SET_OWORD_FIELD(temp, TX_CSR_PUSH_EN, 0);
2942 EFX_SET_OWORD_FIELD(temp, TX_DIS_NON_IP_EV, 1);
2943 /* Enable SW_EV to inherit in char driver - assume harmless here */
2944 EFX_SET_OWORD_FIELD(temp, TX_SW_EV_EN, 1);
2945 /* Prefetch threshold 2 => fetch when descriptor cache half empty */
2946 EFX_SET_OWORD_FIELD(temp, TX_PREF_THRESHOLD, 2);
2947 /* Squash TX of packets of 16 bytes or less */
2948 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
2949 EFX_SET_OWORD_FIELD(temp, TX_FLUSH_MIN_LEN_EN_B0, 1);
2950 falcon_write(efx, &temp, TX_CFG2_REG_KER);
2952 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
2953 * descriptors (which is bad).
2955 falcon_read(efx, &temp, TX_CFG_REG_KER);
2956 EFX_SET_OWORD_FIELD(temp, TX_NO_EOP_DISC_EN, 0);
2957 falcon_write(efx, &temp, TX_CFG_REG_KER);
2960 falcon_read(efx, &temp, RX_CFG_REG_KER);
2961 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_DESC_PUSH_EN, 0);
2962 if (EFX_WORKAROUND_7575(efx))
2963 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_USR_BUF_SIZE,
2965 if (falcon_rev(efx) >= FALCON_REV_B0)
2966 EFX_SET_OWORD_FIELD(temp, RX_INGR_EN_B0, 1);
2968 /* RX FIFO flow control thresholds */
2969 thresh = ((rx_xon_thresh_bytes >= 0) ?
2970 rx_xon_thresh_bytes : efx->type->rx_xon_thresh);
2971 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_MAC_TH, thresh / 256);
2972 thresh = ((rx_xoff_thresh_bytes >= 0) ?
2973 rx_xoff_thresh_bytes : efx->type->rx_xoff_thresh);
2974 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_MAC_TH, thresh / 256);
2975 /* RX control FIFO thresholds [32 entries] */
2976 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XON_TX_TH, 20);
2977 EFX_SET_OWORD_FIELD_VER(efx, temp, RX_XOFF_TX_TH, 25);
2978 falcon_write(efx, &temp, RX_CFG_REG_KER);
2980 /* Set destination of both TX and RX Flush events */
2981 if (falcon_rev(efx) >= FALCON_REV_B0) {
2982 EFX_POPULATE_OWORD_1(temp, FLS_EVQ_ID, 0);
2983 falcon_write(efx, &temp, DP_CTRL_REG);
2989 void falcon_remove_nic(struct efx_nic *efx)
2991 struct falcon_nic_data *nic_data = efx->nic_data;
2994 rc = i2c_del_adapter(&efx->i2c_adap);
2997 falcon_remove_spi_devices(efx);
2998 falcon_free_buffer(efx, &efx->irq_status);
3000 falcon_reset_hw(efx, RESET_TYPE_ALL);
3002 /* Release the second function after the reset */
3003 if (nic_data->pci_dev2) {
3004 pci_dev_put(nic_data->pci_dev2);
3005 nic_data->pci_dev2 = NULL;
3008 /* Tear down the private nic state */
3009 kfree(efx->nic_data);
3010 efx->nic_data = NULL;
3013 void falcon_update_nic_stats(struct efx_nic *efx)
3017 falcon_read(efx, &cnt, RX_NODESC_DROP_REG_KER);
3018 efx->n_rx_nodesc_drop_cnt += EFX_OWORD_FIELD(cnt, RX_NODESC_DROP_CNT);
3021 /**************************************************************************
3023 * Revision-dependent attributes used by efx.c
3025 **************************************************************************
3028 struct efx_nic_type falcon_a_nic_type = {
3030 .mem_map_size = 0x20000,
3031 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_A1,
3032 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_A1,
3033 .buf_tbl_base = BUF_TBL_KER_A1,
3034 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_A1,
3035 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_A1,
3036 .txd_ring_mask = FALCON_TXD_RING_MASK,
3037 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3038 .evq_size = FALCON_EVQ_SIZE,
3039 .max_dma_mask = FALCON_DMA_MASK,
3040 .tx_dma_mask = FALCON_TX_DMA_MASK,
3041 .bug5391_mask = 0xf,
3042 .rx_xoff_thresh = 2048,
3043 .rx_xon_thresh = 512,
3044 .rx_buffer_padding = 0x24,
3045 .max_interrupt_mode = EFX_INT_MODE_MSI,
3046 .phys_addr_channels = 4,
3049 struct efx_nic_type falcon_b_nic_type = {
3051 /* Map everything up to and including the RSS indirection
3052 * table. Don't map MSI-X table, MSI-X PBA since Linux
3053 * requires that they not be mapped. */
3054 .mem_map_size = RX_RSS_INDIR_TBL_B0 + 0x800,
3055 .txd_ptr_tbl_base = TX_DESC_PTR_TBL_KER_B0,
3056 .rxd_ptr_tbl_base = RX_DESC_PTR_TBL_KER_B0,
3057 .buf_tbl_base = BUF_TBL_KER_B0,
3058 .evq_ptr_tbl_base = EVQ_PTR_TBL_KER_B0,
3059 .evq_rptr_tbl_base = EVQ_RPTR_REG_KER_B0,
3060 .txd_ring_mask = FALCON_TXD_RING_MASK,
3061 .rxd_ring_mask = FALCON_RXD_RING_MASK,
3062 .evq_size = FALCON_EVQ_SIZE,
3063 .max_dma_mask = FALCON_DMA_MASK,
3064 .tx_dma_mask = FALCON_TX_DMA_MASK,
3066 .rx_xoff_thresh = 54272, /* ~80Kb - 3*max MTU */
3067 .rx_xon_thresh = 27648, /* ~3*max MTU */
3068 .rx_buffer_padding = 0,
3069 .max_interrupt_mode = EFX_INT_MODE_MSIX,
3070 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
3071 * interrupt handler only supports 32