2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work = 20;
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit = 32;
61 /* MAC address length */
62 #define MAC_ADDR_LEN 6
64 #define MAX_READ_REQUEST_SHIFT 12
65 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
68 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
69 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
93 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
94 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
95 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
96 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
97 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
98 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
99 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
100 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
101 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
102 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
103 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
104 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
105 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
106 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
107 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
108 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
109 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
110 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
111 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
112 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
113 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
114 RTL_GIGA_MAC_VER_22 = 0x16 // 8168C
117 #define _R(NAME,MAC,MASK) \
118 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
120 static const struct {
123 u32 RxConfigMask; /* Clears the bits supported by this chip */
124 } rtl_chip_info[] = {
125 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
126 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
127 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
128 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
129 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
130 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
131 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
132 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
133 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
134 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
135 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
136 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
137 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
138 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
139 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
140 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
142 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
143 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
144 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
145 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
146 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880) // PCI-E
156 static void rtl_hw_start_8169(struct net_device *);
157 static void rtl_hw_start_8168(struct net_device *);
158 static void rtl_hw_start_8101(struct net_device *);
160 static struct pci_device_id rtl8169_pci_tbl[] = {
161 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
162 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
166 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
167 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
168 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
169 { PCI_VENDOR_ID_LINKSYS, 0x1032,
170 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
172 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
176 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
178 static int rx_copybreak = 200;
185 MAC0 = 0, /* Ethernet hardware address. */
187 MAR0 = 8, /* Multicast filter. */
188 CounterAddrLow = 0x10,
189 CounterAddrHigh = 0x14,
190 TxDescStartAddrLow = 0x20,
191 TxDescStartAddrHigh = 0x24,
192 TxHDescStartAddrLow = 0x28,
193 TxHDescStartAddrHigh = 0x2c,
216 RxDescAddrLow = 0xe4,
217 RxDescAddrHigh = 0xe8,
220 FuncEventMask = 0xf4,
221 FuncPresetState = 0xf8,
222 FuncForceEvent = 0xfc,
225 enum rtl8110_registers {
231 enum rtl8168_8101_registers {
234 #define CSIAR_FLAG 0x80000000
235 #define CSIAR_WRITE_CMD 0x80000000
236 #define CSIAR_BYTE_ENABLE 0x0f
237 #define CSIAR_BYTE_ENABLE_SHIFT 12
238 #define CSIAR_ADDR_MASK 0x0fff
241 #define EPHYAR_FLAG 0x80000000
242 #define EPHYAR_WRITE_CMD 0x80000000
243 #define EPHYAR_REG_MASK 0x1f
244 #define EPHYAR_REG_SHIFT 16
245 #define EPHYAR_DATA_MASK 0xffff
247 #define FIX_NAK_1 (1 << 4)
248 #define FIX_NAK_2 (1 << 3)
251 enum rtl_register_content {
252 /* InterruptStatusBits */
256 TxDescUnavail = 0x0080,
278 /* TXPoll register p.5 */
279 HPQ = 0x80, /* Poll cmd on the high prio queue */
280 NPQ = 0x40, /* Poll cmd on the low prio queue */
281 FSWInt = 0x01, /* Forced software interrupt */
285 Cfg9346_Unlock = 0xc0,
290 AcceptBroadcast = 0x08,
291 AcceptMulticast = 0x04,
293 AcceptAllPhys = 0x01,
300 TxInterFrameGapShift = 24,
301 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
303 /* Config1 register p.24 */
306 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
307 Speed_down = (1 << 4),
311 PMEnable = (1 << 0), /* Power Management Enable */
313 /* Config2 register p. 25 */
314 PCI_Clock_66MHz = 0x01,
315 PCI_Clock_33MHz = 0x00,
317 /* Config3 register p.25 */
318 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
319 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
320 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
322 /* Config5 register p.27 */
323 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
324 MWF = (1 << 5), /* Accept Multicast wakeup frame */
325 UWF = (1 << 4), /* Accept Unicast wakeup frame */
326 LanWake = (1 << 1), /* LanWake enable/disable */
327 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
330 TBIReset = 0x80000000,
331 TBILoopback = 0x40000000,
332 TBINwEnable = 0x20000000,
333 TBINwRestart = 0x10000000,
334 TBILinkOk = 0x02000000,
335 TBINwComplete = 0x01000000,
338 EnableBist = (1 << 15), // 8168 8101
339 Mac_dbgo_oe = (1 << 14), // 8168 8101
340 Normal_mode = (1 << 13), // unused
341 Force_half_dup = (1 << 12), // 8168 8101
342 Force_rxflow_en = (1 << 11), // 8168 8101
343 Force_txflow_en = (1 << 10), // 8168 8101
344 Cxpl_dbg_sel = (1 << 9), // 8168 8101
345 ASF = (1 << 8), // 8168 8101
346 PktCntrDisable = (1 << 7), // 8168 8101
347 Mac_dbgo_sel = 0x001c, // 8168
352 INTT_0 = 0x0000, // 8168
353 INTT_1 = 0x0001, // 8168
354 INTT_2 = 0x0002, // 8168
355 INTT_3 = 0x0003, // 8168
357 /* rtl8169_PHYstatus */
368 TBILinkOK = 0x02000000,
370 /* DumpCounterCommand */
374 enum desc_status_bit {
375 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
376 RingEnd = (1 << 30), /* End of descriptor ring */
377 FirstFrag = (1 << 29), /* First segment of a packet */
378 LastFrag = (1 << 28), /* Final segment of a packet */
381 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
382 MSSShift = 16, /* MSS value position */
383 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
384 IPCS = (1 << 18), /* Calculate IP checksum */
385 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
386 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
387 TxVlanTag = (1 << 17), /* Add VLAN tag */
390 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
391 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
393 #define RxProtoUDP (PID1)
394 #define RxProtoTCP (PID0)
395 #define RxProtoIP (PID1 | PID0)
396 #define RxProtoMask RxProtoIP
398 IPFail = (1 << 16), /* IP checksum failed */
399 UDPFail = (1 << 15), /* UDP/IP checksum failed */
400 TCPFail = (1 << 14), /* TCP/IP checksum failed */
401 RxVlanTag = (1 << 16), /* VLAN tag available */
404 #define RsvdMask 0x3fffc000
421 u8 __pad[sizeof(void *) - sizeof(u32)];
425 RTL_FEATURE_WOL = (1 << 0),
426 RTL_FEATURE_MSI = (1 << 1),
427 RTL_FEATURE_GMII = (1 << 2),
430 struct rtl8169_private {
431 void __iomem *mmio_addr; /* memory map physical address */
432 struct pci_dev *pci_dev; /* Index of PCI device */
433 struct net_device *dev;
434 struct napi_struct napi;
435 spinlock_t lock; /* spin lock flag */
439 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
440 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
443 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
444 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
445 dma_addr_t TxPhyAddr;
446 dma_addr_t RxPhyAddr;
447 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
448 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
451 struct timer_list timer;
456 int phy_auto_nego_reg;
457 int phy_1000_ctrl_reg;
458 #ifdef CONFIG_R8169_VLAN
459 struct vlan_group *vlgrp;
461 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
462 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
463 void (*phy_reset_enable)(void __iomem *);
464 void (*hw_start)(struct net_device *);
465 unsigned int (*phy_reset_pending)(void __iomem *);
466 unsigned int (*link_ok)(void __iomem *);
468 struct delayed_work task;
471 struct mii_if_info mii;
474 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
475 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
476 module_param(rx_copybreak, int, 0);
477 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
478 module_param(use_dac, int, 0);
479 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
480 module_param_named(debug, debug.msg_enable, int, 0);
481 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
482 MODULE_LICENSE("GPL");
483 MODULE_VERSION(RTL8169_VERSION);
485 static int rtl8169_open(struct net_device *dev);
486 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
487 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
488 static int rtl8169_init_ring(struct net_device *dev);
489 static void rtl_hw_start(struct net_device *dev);
490 static int rtl8169_close(struct net_device *dev);
491 static void rtl_set_rx_mode(struct net_device *dev);
492 static void rtl8169_tx_timeout(struct net_device *dev);
493 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
494 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
495 void __iomem *, u32 budget);
496 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
497 static void rtl8169_down(struct net_device *dev);
498 static void rtl8169_rx_clear(struct rtl8169_private *tp);
499 static int rtl8169_poll(struct napi_struct *napi, int budget);
501 static const unsigned int rtl8169_rx_config =
502 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
504 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
508 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
510 for (i = 20; i > 0; i--) {
512 * Check if the RTL8169 has completed writing to the specified
515 if (!(RTL_R32(PHYAR) & 0x80000000))
521 static int mdio_read(void __iomem *ioaddr, int reg_addr)
525 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
527 for (i = 20; i > 0; i--) {
529 * Check if the RTL8169 has completed retrieving data from
530 * the specified MII register.
532 if (RTL_R32(PHYAR) & 0x80000000) {
533 value = RTL_R32(PHYAR) & 0xffff;
541 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
543 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
546 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
549 struct rtl8169_private *tp = netdev_priv(dev);
550 void __iomem *ioaddr = tp->mmio_addr;
552 mdio_write(ioaddr, location, val);
555 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
557 struct rtl8169_private *tp = netdev_priv(dev);
558 void __iomem *ioaddr = tp->mmio_addr;
560 return mdio_read(ioaddr, location);
563 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
567 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
568 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
570 for (i = 0; i < 100; i++) {
571 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
577 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
582 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
584 for (i = 0; i < 100; i++) {
585 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
586 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
595 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
599 RTL_W32(CSIDR, value);
600 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
601 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
603 for (i = 0; i < 100; i++) {
604 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
610 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
615 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
616 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
618 for (i = 0; i < 100; i++) {
619 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
620 value = RTL_R32(CSIDR);
629 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
631 RTL_W16(IntrMask, 0x0000);
633 RTL_W16(IntrStatus, 0xffff);
636 static void rtl8169_asic_down(void __iomem *ioaddr)
638 RTL_W8(ChipCmd, 0x00);
639 rtl8169_irq_mask_and_ack(ioaddr);
643 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
645 return RTL_R32(TBICSR) & TBIReset;
648 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
650 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
653 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
655 return RTL_R32(TBICSR) & TBILinkOk;
658 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
660 return RTL_R8(PHYstatus) & LinkStatus;
663 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
665 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
668 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
672 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
673 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
676 static void rtl8169_check_link_status(struct net_device *dev,
677 struct rtl8169_private *tp,
678 void __iomem *ioaddr)
682 spin_lock_irqsave(&tp->lock, flags);
683 if (tp->link_ok(ioaddr)) {
684 netif_carrier_on(dev);
685 if (netif_msg_ifup(tp))
686 printk(KERN_INFO PFX "%s: link up\n", dev->name);
688 if (netif_msg_ifdown(tp))
689 printk(KERN_INFO PFX "%s: link down\n", dev->name);
690 netif_carrier_off(dev);
692 spin_unlock_irqrestore(&tp->lock, flags);
695 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
697 struct rtl8169_private *tp = netdev_priv(dev);
698 void __iomem *ioaddr = tp->mmio_addr;
703 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
704 wol->supported = WAKE_ANY;
706 spin_lock_irq(&tp->lock);
708 options = RTL_R8(Config1);
709 if (!(options & PMEnable))
712 options = RTL_R8(Config3);
713 if (options & LinkUp)
714 wol->wolopts |= WAKE_PHY;
715 if (options & MagicPacket)
716 wol->wolopts |= WAKE_MAGIC;
718 options = RTL_R8(Config5);
720 wol->wolopts |= WAKE_UCAST;
722 wol->wolopts |= WAKE_BCAST;
724 wol->wolopts |= WAKE_MCAST;
727 spin_unlock_irq(&tp->lock);
730 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
732 struct rtl8169_private *tp = netdev_priv(dev);
733 void __iomem *ioaddr = tp->mmio_addr;
740 { WAKE_ANY, Config1, PMEnable },
741 { WAKE_PHY, Config3, LinkUp },
742 { WAKE_MAGIC, Config3, MagicPacket },
743 { WAKE_UCAST, Config5, UWF },
744 { WAKE_BCAST, Config5, BWF },
745 { WAKE_MCAST, Config5, MWF },
746 { WAKE_ANY, Config5, LanWake }
749 spin_lock_irq(&tp->lock);
751 RTL_W8(Cfg9346, Cfg9346_Unlock);
753 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
754 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
755 if (wol->wolopts & cfg[i].opt)
756 options |= cfg[i].mask;
757 RTL_W8(cfg[i].reg, options);
760 RTL_W8(Cfg9346, Cfg9346_Lock);
763 tp->features |= RTL_FEATURE_WOL;
765 tp->features &= ~RTL_FEATURE_WOL;
766 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
768 spin_unlock_irq(&tp->lock);
773 static void rtl8169_get_drvinfo(struct net_device *dev,
774 struct ethtool_drvinfo *info)
776 struct rtl8169_private *tp = netdev_priv(dev);
778 strcpy(info->driver, MODULENAME);
779 strcpy(info->version, RTL8169_VERSION);
780 strcpy(info->bus_info, pci_name(tp->pci_dev));
783 static int rtl8169_get_regs_len(struct net_device *dev)
785 return R8169_REGS_SIZE;
788 static int rtl8169_set_speed_tbi(struct net_device *dev,
789 u8 autoneg, u16 speed, u8 duplex)
791 struct rtl8169_private *tp = netdev_priv(dev);
792 void __iomem *ioaddr = tp->mmio_addr;
796 reg = RTL_R32(TBICSR);
797 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
798 (duplex == DUPLEX_FULL)) {
799 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
800 } else if (autoneg == AUTONEG_ENABLE)
801 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
803 if (netif_msg_link(tp)) {
804 printk(KERN_WARNING "%s: "
805 "incorrect speed setting refused in TBI mode\n",
814 static int rtl8169_set_speed_xmii(struct net_device *dev,
815 u8 autoneg, u16 speed, u8 duplex)
817 struct rtl8169_private *tp = netdev_priv(dev);
818 void __iomem *ioaddr = tp->mmio_addr;
819 int auto_nego, giga_ctrl;
821 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
822 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
823 ADVERTISE_100HALF | ADVERTISE_100FULL);
824 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
825 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
827 if (autoneg == AUTONEG_ENABLE) {
828 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
829 ADVERTISE_100HALF | ADVERTISE_100FULL);
830 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
832 if (speed == SPEED_10)
833 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
834 else if (speed == SPEED_100)
835 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
836 else if (speed == SPEED_1000)
837 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
839 if (duplex == DUPLEX_HALF)
840 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
842 if (duplex == DUPLEX_FULL)
843 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
845 /* This tweak comes straight from Realtek's driver. */
846 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
847 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
848 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
849 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
853 /* The 8100e/8101e/8102e do Fast Ethernet only. */
854 if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
855 (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
856 (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
857 (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
858 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
859 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
860 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
861 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
862 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
863 netif_msg_link(tp)) {
864 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
867 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
870 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
872 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
873 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
874 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
877 * Vendor specific (0x1f) and reserved (0x0e) MII registers.
879 mdio_write(ioaddr, 0x1f, 0x0000);
880 mdio_write(ioaddr, 0x0e, 0x0000);
883 tp->phy_auto_nego_reg = auto_nego;
884 tp->phy_1000_ctrl_reg = giga_ctrl;
886 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
887 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
888 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
892 static int rtl8169_set_speed(struct net_device *dev,
893 u8 autoneg, u16 speed, u8 duplex)
895 struct rtl8169_private *tp = netdev_priv(dev);
898 ret = tp->set_speed(dev, autoneg, speed, duplex);
900 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
901 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
906 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
908 struct rtl8169_private *tp = netdev_priv(dev);
912 spin_lock_irqsave(&tp->lock, flags);
913 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
914 spin_unlock_irqrestore(&tp->lock, flags);
919 static u32 rtl8169_get_rx_csum(struct net_device *dev)
921 struct rtl8169_private *tp = netdev_priv(dev);
923 return tp->cp_cmd & RxChkSum;
926 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
928 struct rtl8169_private *tp = netdev_priv(dev);
929 void __iomem *ioaddr = tp->mmio_addr;
932 spin_lock_irqsave(&tp->lock, flags);
935 tp->cp_cmd |= RxChkSum;
937 tp->cp_cmd &= ~RxChkSum;
939 RTL_W16(CPlusCmd, tp->cp_cmd);
942 spin_unlock_irqrestore(&tp->lock, flags);
947 #ifdef CONFIG_R8169_VLAN
949 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
952 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
953 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
956 static void rtl8169_vlan_rx_register(struct net_device *dev,
957 struct vlan_group *grp)
959 struct rtl8169_private *tp = netdev_priv(dev);
960 void __iomem *ioaddr = tp->mmio_addr;
963 spin_lock_irqsave(&tp->lock, flags);
966 tp->cp_cmd |= RxVlan;
968 tp->cp_cmd &= ~RxVlan;
969 RTL_W16(CPlusCmd, tp->cp_cmd);
971 spin_unlock_irqrestore(&tp->lock, flags);
974 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
977 u32 opts2 = le32_to_cpu(desc->opts2);
978 struct vlan_group *vlgrp = tp->vlgrp;
981 if (vlgrp && (opts2 & RxVlanTag)) {
982 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
990 #else /* !CONFIG_R8169_VLAN */
992 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
998 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1006 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1008 struct rtl8169_private *tp = netdev_priv(dev);
1009 void __iomem *ioaddr = tp->mmio_addr;
1013 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1014 cmd->port = PORT_FIBRE;
1015 cmd->transceiver = XCVR_INTERNAL;
1017 status = RTL_R32(TBICSR);
1018 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1019 cmd->autoneg = !!(status & TBINwEnable);
1021 cmd->speed = SPEED_1000;
1022 cmd->duplex = DUPLEX_FULL; /* Always set */
1027 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1029 struct rtl8169_private *tp = netdev_priv(dev);
1031 return mii_ethtool_gset(&tp->mii, cmd);
1034 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1036 struct rtl8169_private *tp = netdev_priv(dev);
1037 unsigned long flags;
1040 spin_lock_irqsave(&tp->lock, flags);
1042 rc = tp->get_settings(dev, cmd);
1044 spin_unlock_irqrestore(&tp->lock, flags);
1048 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1051 struct rtl8169_private *tp = netdev_priv(dev);
1052 unsigned long flags;
1054 if (regs->len > R8169_REGS_SIZE)
1055 regs->len = R8169_REGS_SIZE;
1057 spin_lock_irqsave(&tp->lock, flags);
1058 memcpy_fromio(p, tp->mmio_addr, regs->len);
1059 spin_unlock_irqrestore(&tp->lock, flags);
1062 static u32 rtl8169_get_msglevel(struct net_device *dev)
1064 struct rtl8169_private *tp = netdev_priv(dev);
1066 return tp->msg_enable;
1069 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1071 struct rtl8169_private *tp = netdev_priv(dev);
1073 tp->msg_enable = value;
1076 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1083 "tx_single_collisions",
1084 "tx_multi_collisions",
1092 struct rtl8169_counters {
1098 __le16 align_errors;
1099 __le32 tx_one_collision;
1100 __le32 tx_multi_collision;
1102 __le64 rx_broadcast;
1103 __le32 rx_multicast;
1108 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1112 return ARRAY_SIZE(rtl8169_gstrings);
1118 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1119 struct ethtool_stats *stats, u64 *data)
1121 struct rtl8169_private *tp = netdev_priv(dev);
1122 void __iomem *ioaddr = tp->mmio_addr;
1123 struct rtl8169_counters *counters;
1129 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1133 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1134 cmd = (u64)paddr & DMA_32BIT_MASK;
1135 RTL_W32(CounterAddrLow, cmd);
1136 RTL_W32(CounterAddrLow, cmd | CounterDump);
1138 while (RTL_R32(CounterAddrLow) & CounterDump) {
1139 if (msleep_interruptible(1))
1143 RTL_W32(CounterAddrLow, 0);
1144 RTL_W32(CounterAddrHigh, 0);
1146 data[0] = le64_to_cpu(counters->tx_packets);
1147 data[1] = le64_to_cpu(counters->rx_packets);
1148 data[2] = le64_to_cpu(counters->tx_errors);
1149 data[3] = le32_to_cpu(counters->rx_errors);
1150 data[4] = le16_to_cpu(counters->rx_missed);
1151 data[5] = le16_to_cpu(counters->align_errors);
1152 data[6] = le32_to_cpu(counters->tx_one_collision);
1153 data[7] = le32_to_cpu(counters->tx_multi_collision);
1154 data[8] = le64_to_cpu(counters->rx_unicast);
1155 data[9] = le64_to_cpu(counters->rx_broadcast);
1156 data[10] = le32_to_cpu(counters->rx_multicast);
1157 data[11] = le16_to_cpu(counters->tx_aborted);
1158 data[12] = le16_to_cpu(counters->tx_underun);
1160 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1163 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1167 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1172 static const struct ethtool_ops rtl8169_ethtool_ops = {
1173 .get_drvinfo = rtl8169_get_drvinfo,
1174 .get_regs_len = rtl8169_get_regs_len,
1175 .get_link = ethtool_op_get_link,
1176 .get_settings = rtl8169_get_settings,
1177 .set_settings = rtl8169_set_settings,
1178 .get_msglevel = rtl8169_get_msglevel,
1179 .set_msglevel = rtl8169_set_msglevel,
1180 .get_rx_csum = rtl8169_get_rx_csum,
1181 .set_rx_csum = rtl8169_set_rx_csum,
1182 .set_tx_csum = ethtool_op_set_tx_csum,
1183 .set_sg = ethtool_op_set_sg,
1184 .set_tso = ethtool_op_set_tso,
1185 .get_regs = rtl8169_get_regs,
1186 .get_wol = rtl8169_get_wol,
1187 .set_wol = rtl8169_set_wol,
1188 .get_strings = rtl8169_get_strings,
1189 .get_sset_count = rtl8169_get_sset_count,
1190 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1193 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1194 int bitnum, int bitval)
1198 val = mdio_read(ioaddr, reg);
1199 val = (bitval == 1) ?
1200 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1201 mdio_write(ioaddr, reg, val & 0xffff);
1204 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1205 void __iomem *ioaddr)
1208 * The driver currently handles the 8168Bf and the 8168Be identically
1209 * but they can be identified more specifically through the test below
1212 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1214 * Same thing for the 8101Eb and the 8101Ec:
1216 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1224 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1225 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1226 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1227 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1228 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1229 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1232 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1233 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1234 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1235 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1238 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1239 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1240 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1241 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1242 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1243 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1244 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1245 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1246 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1247 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1248 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1249 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1250 /* FIXME: where did these entries come from ? -- FR */
1251 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1252 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1255 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1256 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1257 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1258 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1259 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1260 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1262 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1266 reg = RTL_R32(TxConfig);
1267 while ((reg & p->mask) != p->val)
1269 tp->mac_version = p->mac_version;
1271 if (p->mask == 0x00000000) {
1272 struct pci_dev *pdev = tp->pci_dev;
1274 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1278 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1280 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1288 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1291 mdio_write(ioaddr, regs->reg, regs->val);
1296 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1299 u16 regs[5]; /* Beware of bit-sign propagation */
1300 } phy_magic[5] = { {
1301 { 0x0000, //w 4 15 12 0
1302 0x00a1, //w 3 15 0 00a1
1303 0x0008, //w 2 15 0 0008
1304 0x1020, //w 1 15 0 1020
1305 0x1000 } },{ //w 0 15 0 1000
1306 { 0x7000, //w 4 15 12 7
1307 0xff41, //w 3 15 0 ff41
1308 0xde60, //w 2 15 0 de60
1309 0x0140, //w 1 15 0 0140
1310 0x0077 } },{ //w 0 15 0 0077
1311 { 0xa000, //w 4 15 12 a
1312 0xdf01, //w 3 15 0 df01
1313 0xdf20, //w 2 15 0 df20
1314 0xff95, //w 1 15 0 ff95
1315 0xfa00 } },{ //w 0 15 0 fa00
1316 { 0xb000, //w 4 15 12 b
1317 0xff41, //w 3 15 0 ff41
1318 0xde20, //w 2 15 0 de20
1319 0x0140, //w 1 15 0 0140
1320 0x00bb } },{ //w 0 15 0 00bb
1321 { 0xf000, //w 4 15 12 f
1322 0xdf01, //w 3 15 0 df01
1323 0xdf20, //w 2 15 0 df20
1324 0xff95, //w 1 15 0 ff95
1325 0xbf00 } //w 0 15 0 bf00
1330 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1331 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1332 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1333 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1335 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1338 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1339 mdio_write(ioaddr, pos, val);
1341 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1342 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1343 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1345 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1348 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1350 struct phy_reg phy_reg_init[] = {
1356 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1359 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1361 struct phy_reg phy_reg_init[] = {
1366 mdio_write(ioaddr, 0x1f, 0x0001);
1367 mdio_patch(ioaddr, 0x16, 1 << 0);
1369 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1372 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1374 struct phy_reg phy_reg_init[] = {
1380 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1383 static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1385 struct phy_reg phy_reg_init[] = {
1393 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1396 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1398 struct phy_reg phy_reg_init[] = {
1418 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1420 mdio_patch(ioaddr, 0x14, 1 << 5);
1421 mdio_patch(ioaddr, 0x0d, 1 << 5);
1422 mdio_write(ioaddr, 0x1f, 0x0000);
1425 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1427 struct phy_reg phy_reg_init[] = {
1445 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1447 mdio_patch(ioaddr, 0x16, 1 << 0);
1448 mdio_patch(ioaddr, 0x14, 1 << 5);
1449 mdio_patch(ioaddr, 0x0d, 1 << 5);
1450 mdio_write(ioaddr, 0x1f, 0x0000);
1453 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1455 struct phy_reg phy_reg_init[] = {
1467 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1469 mdio_patch(ioaddr, 0x16, 1 << 0);
1470 mdio_patch(ioaddr, 0x14, 1 << 5);
1471 mdio_patch(ioaddr, 0x0d, 1 << 5);
1472 mdio_write(ioaddr, 0x1f, 0x0000);
1475 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1477 rtl8168c_3_hw_phy_config(ioaddr);
1480 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1482 struct phy_reg phy_reg_init[] = {
1489 mdio_write(ioaddr, 0x1f, 0x0000);
1490 mdio_patch(ioaddr, 0x11, 1 << 12);
1491 mdio_patch(ioaddr, 0x19, 1 << 13);
1493 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1496 static void rtl_hw_phy_config(struct net_device *dev)
1498 struct rtl8169_private *tp = netdev_priv(dev);
1499 void __iomem *ioaddr = tp->mmio_addr;
1501 rtl8169_print_mac_version(tp);
1503 switch (tp->mac_version) {
1504 case RTL_GIGA_MAC_VER_01:
1506 case RTL_GIGA_MAC_VER_02:
1507 case RTL_GIGA_MAC_VER_03:
1508 rtl8169s_hw_phy_config(ioaddr);
1510 case RTL_GIGA_MAC_VER_04:
1511 rtl8169sb_hw_phy_config(ioaddr);
1513 case RTL_GIGA_MAC_VER_07:
1514 case RTL_GIGA_MAC_VER_08:
1515 case RTL_GIGA_MAC_VER_09:
1516 rtl8102e_hw_phy_config(ioaddr);
1518 case RTL_GIGA_MAC_VER_11:
1519 rtl8168bb_hw_phy_config(ioaddr);
1521 case RTL_GIGA_MAC_VER_12:
1522 rtl8168bef_hw_phy_config(ioaddr);
1524 case RTL_GIGA_MAC_VER_17:
1525 rtl8168bef_hw_phy_config(ioaddr);
1527 case RTL_GIGA_MAC_VER_18:
1528 rtl8168cp_hw_phy_config(ioaddr);
1530 case RTL_GIGA_MAC_VER_19:
1531 rtl8168c_1_hw_phy_config(ioaddr);
1533 case RTL_GIGA_MAC_VER_20:
1534 rtl8168c_2_hw_phy_config(ioaddr);
1536 case RTL_GIGA_MAC_VER_21:
1537 rtl8168c_3_hw_phy_config(ioaddr);
1539 case RTL_GIGA_MAC_VER_22:
1540 rtl8168c_4_hw_phy_config(ioaddr);
1547 static void rtl8169_phy_timer(unsigned long __opaque)
1549 struct net_device *dev = (struct net_device *)__opaque;
1550 struct rtl8169_private *tp = netdev_priv(dev);
1551 struct timer_list *timer = &tp->timer;
1552 void __iomem *ioaddr = tp->mmio_addr;
1553 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1555 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1557 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1560 spin_lock_irq(&tp->lock);
1562 if (tp->phy_reset_pending(ioaddr)) {
1564 * A busy loop could burn quite a few cycles on nowadays CPU.
1565 * Let's delay the execution of the timer for a few ticks.
1571 if (tp->link_ok(ioaddr))
1574 if (netif_msg_link(tp))
1575 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1577 tp->phy_reset_enable(ioaddr);
1580 mod_timer(timer, jiffies + timeout);
1582 spin_unlock_irq(&tp->lock);
1585 static inline void rtl8169_delete_timer(struct net_device *dev)
1587 struct rtl8169_private *tp = netdev_priv(dev);
1588 struct timer_list *timer = &tp->timer;
1590 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1593 del_timer_sync(timer);
1596 static inline void rtl8169_request_timer(struct net_device *dev)
1598 struct rtl8169_private *tp = netdev_priv(dev);
1599 struct timer_list *timer = &tp->timer;
1601 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1604 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1607 #ifdef CONFIG_NET_POLL_CONTROLLER
1609 * Polling 'interrupt' - used by things like netconsole to send skbs
1610 * without having to re-enable interrupts. It's not called while
1611 * the interrupt routine is executing.
1613 static void rtl8169_netpoll(struct net_device *dev)
1615 struct rtl8169_private *tp = netdev_priv(dev);
1616 struct pci_dev *pdev = tp->pci_dev;
1618 disable_irq(pdev->irq);
1619 rtl8169_interrupt(pdev->irq, dev);
1620 enable_irq(pdev->irq);
1624 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1625 void __iomem *ioaddr)
1628 pci_release_regions(pdev);
1629 pci_disable_device(pdev);
1633 static void rtl8169_phy_reset(struct net_device *dev,
1634 struct rtl8169_private *tp)
1636 void __iomem *ioaddr = tp->mmio_addr;
1639 tp->phy_reset_enable(ioaddr);
1640 for (i = 0; i < 100; i++) {
1641 if (!tp->phy_reset_pending(ioaddr))
1645 if (netif_msg_link(tp))
1646 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1649 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1651 void __iomem *ioaddr = tp->mmio_addr;
1653 rtl_hw_phy_config(dev);
1655 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1656 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1660 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1662 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1663 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1665 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1666 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1668 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1669 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1672 rtl8169_phy_reset(dev, tp);
1675 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1676 * only 8101. Don't panic.
1678 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1680 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1681 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1684 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1686 void __iomem *ioaddr = tp->mmio_addr;
1690 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1691 high = addr[4] | (addr[5] << 8);
1693 spin_lock_irq(&tp->lock);
1695 RTL_W8(Cfg9346, Cfg9346_Unlock);
1697 RTL_W32(MAC4, high);
1698 RTL_W8(Cfg9346, Cfg9346_Lock);
1700 spin_unlock_irq(&tp->lock);
1703 static int rtl_set_mac_address(struct net_device *dev, void *p)
1705 struct rtl8169_private *tp = netdev_priv(dev);
1706 struct sockaddr *addr = p;
1708 if (!is_valid_ether_addr(addr->sa_data))
1709 return -EADDRNOTAVAIL;
1711 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1713 rtl_rar_set(tp, dev->dev_addr);
1718 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1720 struct rtl8169_private *tp = netdev_priv(dev);
1721 struct mii_ioctl_data *data = if_mii(ifr);
1723 if (!netif_running(dev))
1728 data->phy_id = 32; /* Internal PHY */
1732 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1736 if (!capable(CAP_NET_ADMIN))
1738 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1744 static const struct rtl_cfg_info {
1745 void (*hw_start)(struct net_device *);
1746 unsigned int region;
1751 } rtl_cfg_infos [] = {
1753 .hw_start = rtl_hw_start_8169,
1756 .intr_event = SYSErr | LinkChg | RxOverflow |
1757 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1758 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1759 .features = RTL_FEATURE_GMII
1762 .hw_start = rtl_hw_start_8168,
1765 .intr_event = SYSErr | LinkChg | RxOverflow |
1766 TxErr | TxOK | RxOK | RxErr,
1767 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1768 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1771 .hw_start = rtl_hw_start_8101,
1774 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1775 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1776 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1777 .features = RTL_FEATURE_MSI
1781 /* Cfg9346_Unlock assumed. */
1782 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1783 const struct rtl_cfg_info *cfg)
1788 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1789 if (cfg->features & RTL_FEATURE_MSI) {
1790 if (pci_enable_msi(pdev)) {
1791 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1794 msi = RTL_FEATURE_MSI;
1797 RTL_W8(Config2, cfg2);
1801 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1803 if (tp->features & RTL_FEATURE_MSI) {
1804 pci_disable_msi(pdev);
1805 tp->features &= ~RTL_FEATURE_MSI;
1809 static int rtl_eeprom_read(struct pci_dev *pdev, int cap, int addr, __le32 *val)
1811 int ret, count = 100;
1815 ret = pci_write_config_word(pdev, cap + PCI_VPD_ADDR, addr);
1821 ret = pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &status);
1824 } while (!(status & PCI_VPD_ADDR_F) && --count);
1826 if (!(status & PCI_VPD_ADDR_F))
1829 ret = pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &value);
1833 *val = cpu_to_le32(value);
1838 static void rtl_init_mac_address(struct rtl8169_private *tp,
1839 void __iomem *ioaddr)
1841 struct pci_dev *pdev = tp->pci_dev;
1845 DECLARE_MAC_BUF(buf);
1847 cfg1 = RTL_R8(Config1);
1848 if (!(cfg1 & VPD)) {
1849 dprintk("VPD access not enabled, enabling\n");
1850 RTL_W8(Cfg9346, Cfg9346_Unlock);
1851 RTL_W8(Config1, cfg1 | VPD);
1852 RTL_W8(Cfg9346, Cfg9346_Lock);
1855 vpd_cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
1859 /* MAC address is stored in EEPROM at offset 0x0e
1860 * Realtek says: "The VPD address does not have to be a DWORD-aligned
1861 * address as defined in the PCI 2.2 Specifications, but the VPD data
1862 * is always consecutive 4-byte data starting from the VPD address
1865 if (rtl_eeprom_read(pdev, vpd_cap, 0x000e, (__le32*)&mac[0]) < 0 ||
1866 rtl_eeprom_read(pdev, vpd_cap, 0x0012, (__le32*)&mac[4]) < 0) {
1867 dprintk("Reading MAC address from EEPROM failed\n");
1871 dprintk("MAC address found in EEPROM: %s\n", print_mac(buf, mac));
1873 /* Write MAC address */
1874 rtl_rar_set(tp, mac);
1877 static int __devinit
1878 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1880 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1881 const unsigned int region = cfg->region;
1882 struct rtl8169_private *tp;
1883 struct mii_if_info *mii;
1884 struct net_device *dev;
1885 void __iomem *ioaddr;
1889 if (netif_msg_drv(&debug)) {
1890 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1891 MODULENAME, RTL8169_VERSION);
1894 dev = alloc_etherdev(sizeof (*tp));
1896 if (netif_msg_drv(&debug))
1897 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1902 SET_NETDEV_DEV(dev, &pdev->dev);
1903 tp = netdev_priv(dev);
1906 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1910 mii->mdio_read = rtl_mdio_read;
1911 mii->mdio_write = rtl_mdio_write;
1912 mii->phy_id_mask = 0x1f;
1913 mii->reg_num_mask = 0x1f;
1914 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1916 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1917 rc = pci_enable_device(pdev);
1919 if (netif_msg_probe(tp))
1920 dev_err(&pdev->dev, "enable failure\n");
1921 goto err_out_free_dev_1;
1924 rc = pci_set_mwi(pdev);
1926 goto err_out_disable_2;
1928 /* make sure PCI base addr 1 is MMIO */
1929 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1930 if (netif_msg_probe(tp)) {
1932 "region #%d not an MMIO resource, aborting\n",
1939 /* check for weird/broken PCI region reporting */
1940 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1941 if (netif_msg_probe(tp)) {
1943 "Invalid PCI region size(s), aborting\n");
1949 rc = pci_request_regions(pdev, MODULENAME);
1951 if (netif_msg_probe(tp))
1952 dev_err(&pdev->dev, "could not request regions.\n");
1956 tp->cp_cmd = PCIMulRW | RxChkSum;
1958 if ((sizeof(dma_addr_t) > 4) &&
1959 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1960 tp->cp_cmd |= PCIDAC;
1961 dev->features |= NETIF_F_HIGHDMA;
1963 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1965 if (netif_msg_probe(tp)) {
1967 "DMA configuration failed.\n");
1969 goto err_out_free_res_4;
1973 pci_set_master(pdev);
1975 /* ioremap MMIO region */
1976 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1978 if (netif_msg_probe(tp))
1979 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1981 goto err_out_free_res_4;
1984 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1985 if (!tp->pcie_cap && netif_msg_probe(tp))
1986 dev_info(&pdev->dev, "no PCI Express capability\n");
1988 /* Unneeded ? Don't mess with Mrs. Murphy. */
1989 rtl8169_irq_mask_and_ack(ioaddr);
1991 /* Soft reset the chip. */
1992 RTL_W8(ChipCmd, CmdReset);
1994 /* Check that the chip has finished the reset. */
1995 for (i = 0; i < 100; i++) {
1996 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1998 msleep_interruptible(1);
2001 /* Identify chip attached to board */
2002 rtl8169_get_mac_version(tp, ioaddr);
2004 rtl8169_print_mac_version(tp);
2006 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2007 if (tp->mac_version == rtl_chip_info[i].mac_version)
2010 if (i == ARRAY_SIZE(rtl_chip_info)) {
2011 /* Unknown chip: assume array element #0, original RTL-8169 */
2012 if (netif_msg_probe(tp)) {
2013 dev_printk(KERN_DEBUG, &pdev->dev,
2014 "unknown chip version, assuming %s\n",
2015 rtl_chip_info[0].name);
2021 RTL_W8(Cfg9346, Cfg9346_Unlock);
2022 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2023 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2024 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2025 tp->features |= RTL_FEATURE_WOL;
2026 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2027 tp->features |= RTL_FEATURE_WOL;
2028 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2029 RTL_W8(Cfg9346, Cfg9346_Lock);
2031 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2032 (RTL_R8(PHYstatus) & TBI_Enable)) {
2033 tp->set_speed = rtl8169_set_speed_tbi;
2034 tp->get_settings = rtl8169_gset_tbi;
2035 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2036 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2037 tp->link_ok = rtl8169_tbi_link_ok;
2039 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2041 tp->set_speed = rtl8169_set_speed_xmii;
2042 tp->get_settings = rtl8169_gset_xmii;
2043 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2044 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2045 tp->link_ok = rtl8169_xmii_link_ok;
2047 dev->do_ioctl = rtl8169_ioctl;
2050 spin_lock_init(&tp->lock);
2052 rtl_init_mac_address(tp, ioaddr);
2054 /* Get MAC address */
2055 for (i = 0; i < MAC_ADDR_LEN; i++)
2056 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2057 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2059 dev->open = rtl8169_open;
2060 dev->hard_start_xmit = rtl8169_start_xmit;
2061 dev->get_stats = rtl8169_get_stats;
2062 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2063 dev->stop = rtl8169_close;
2064 dev->tx_timeout = rtl8169_tx_timeout;
2065 dev->set_multicast_list = rtl_set_rx_mode;
2066 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2067 dev->irq = pdev->irq;
2068 dev->base_addr = (unsigned long) ioaddr;
2069 dev->change_mtu = rtl8169_change_mtu;
2070 dev->set_mac_address = rtl_set_mac_address;
2072 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2074 #ifdef CONFIG_R8169_VLAN
2075 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2076 dev->vlan_rx_register = rtl8169_vlan_rx_register;
2079 #ifdef CONFIG_NET_POLL_CONTROLLER
2080 dev->poll_controller = rtl8169_netpoll;
2083 tp->intr_mask = 0xffff;
2084 tp->mmio_addr = ioaddr;
2085 tp->align = cfg->align;
2086 tp->hw_start = cfg->hw_start;
2087 tp->intr_event = cfg->intr_event;
2088 tp->napi_event = cfg->napi_event;
2090 init_timer(&tp->timer);
2091 tp->timer.data = (unsigned long) dev;
2092 tp->timer.function = rtl8169_phy_timer;
2094 rc = register_netdev(dev);
2098 pci_set_drvdata(pdev, dev);
2100 if (netif_msg_probe(tp)) {
2101 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2103 printk(KERN_INFO "%s: %s at 0x%lx, "
2104 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2105 "XID %08x IRQ %d\n",
2107 rtl_chip_info[tp->chipset].name,
2109 dev->dev_addr[0], dev->dev_addr[1],
2110 dev->dev_addr[2], dev->dev_addr[3],
2111 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2114 rtl8169_init_phy(dev, tp);
2115 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2121 rtl_disable_msi(pdev, tp);
2124 pci_release_regions(pdev);
2126 pci_clear_mwi(pdev);
2128 pci_disable_device(pdev);
2134 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2136 struct net_device *dev = pci_get_drvdata(pdev);
2137 struct rtl8169_private *tp = netdev_priv(dev);
2139 flush_scheduled_work();
2141 unregister_netdev(dev);
2142 rtl_disable_msi(pdev, tp);
2143 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2144 pci_set_drvdata(pdev, NULL);
2147 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2148 struct net_device *dev)
2150 unsigned int mtu = dev->mtu;
2152 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2155 static int rtl8169_open(struct net_device *dev)
2157 struct rtl8169_private *tp = netdev_priv(dev);
2158 struct pci_dev *pdev = tp->pci_dev;
2159 int retval = -ENOMEM;
2162 rtl8169_set_rxbufsize(tp, dev);
2165 * Rx and Tx desscriptors needs 256 bytes alignment.
2166 * pci_alloc_consistent provides more.
2168 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2170 if (!tp->TxDescArray)
2173 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2175 if (!tp->RxDescArray)
2178 retval = rtl8169_init_ring(dev);
2182 INIT_DELAYED_WORK(&tp->task, NULL);
2186 retval = request_irq(dev->irq, rtl8169_interrupt,
2187 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2190 goto err_release_ring_2;
2192 napi_enable(&tp->napi);
2196 rtl8169_request_timer(dev);
2198 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2203 rtl8169_rx_clear(tp);
2205 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2208 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2213 static void rtl8169_hw_reset(void __iomem *ioaddr)
2215 /* Disable interrupts */
2216 rtl8169_irq_mask_and_ack(ioaddr);
2218 /* Reset the chipset */
2219 RTL_W8(ChipCmd, CmdReset);
2225 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2227 void __iomem *ioaddr = tp->mmio_addr;
2228 u32 cfg = rtl8169_rx_config;
2230 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2231 RTL_W32(RxConfig, cfg);
2233 /* Set DMA burst size and Interframe Gap Time */
2234 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2235 (InterFrameGap << TxInterFrameGapShift));
2238 static void rtl_hw_start(struct net_device *dev)
2240 struct rtl8169_private *tp = netdev_priv(dev);
2241 void __iomem *ioaddr = tp->mmio_addr;
2244 /* Soft reset the chip. */
2245 RTL_W8(ChipCmd, CmdReset);
2247 /* Check that the chip has finished the reset. */
2248 for (i = 0; i < 100; i++) {
2249 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2251 msleep_interruptible(1);
2256 netif_start_queue(dev);
2260 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2261 void __iomem *ioaddr)
2264 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2265 * register to be written before TxDescAddrLow to work.
2266 * Switching from MMIO to I/O access fixes the issue as well.
2268 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2269 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2270 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2271 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2274 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2278 cmd = RTL_R16(CPlusCmd);
2279 RTL_W16(CPlusCmd, cmd);
2283 static void rtl_set_rx_max_size(void __iomem *ioaddr)
2285 /* Low hurts. Let's disable the filtering. */
2286 RTL_W16(RxMaxSize, 16383);
2289 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2296 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2297 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2298 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2299 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2304 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2305 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2306 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2307 RTL_W32(0x7c, p->val);
2313 static void rtl_hw_start_8169(struct net_device *dev)
2315 struct rtl8169_private *tp = netdev_priv(dev);
2316 void __iomem *ioaddr = tp->mmio_addr;
2317 struct pci_dev *pdev = tp->pci_dev;
2319 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2320 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2321 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2324 RTL_W8(Cfg9346, Cfg9346_Unlock);
2325 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2326 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2327 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2328 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2329 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2331 RTL_W8(EarlyTxThres, EarlyTxThld);
2333 rtl_set_rx_max_size(ioaddr);
2335 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2336 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2337 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2338 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2339 rtl_set_rx_tx_config_registers(tp);
2341 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2343 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2344 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2345 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2346 "Bit-3 and bit-14 MUST be 1\n");
2347 tp->cp_cmd |= (1 << 14);
2350 RTL_W16(CPlusCmd, tp->cp_cmd);
2352 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2355 * Undocumented corner. Supposedly:
2356 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2358 RTL_W16(IntrMitigate, 0x0000);
2360 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2362 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2363 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2364 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2365 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2366 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2367 rtl_set_rx_tx_config_registers(tp);
2370 RTL_W8(Cfg9346, Cfg9346_Lock);
2372 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2375 RTL_W32(RxMissed, 0);
2377 rtl_set_rx_mode(dev);
2379 /* no early-rx interrupts */
2380 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2382 /* Enable all known interrupts by setting the interrupt mask. */
2383 RTL_W16(IntrMask, tp->intr_event);
2386 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2388 struct net_device *dev = pci_get_drvdata(pdev);
2389 struct rtl8169_private *tp = netdev_priv(dev);
2390 int cap = tp->pcie_cap;
2395 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2396 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2397 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2401 static void rtl_csi_access_enable(void __iomem *ioaddr)
2405 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2406 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2410 unsigned int offset;
2415 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2420 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2421 rtl_ephy_write(ioaddr, e->offset, w);
2426 static void rtl_disable_clock_request(struct pci_dev *pdev)
2428 struct net_device *dev = pci_get_drvdata(pdev);
2429 struct rtl8169_private *tp = netdev_priv(dev);
2430 int cap = tp->pcie_cap;
2435 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2436 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2437 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2441 #define R8168_CPCMD_QUIRK_MASK (\
2452 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2454 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2456 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2458 rtl_tx_performance_tweak(pdev,
2459 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
2462 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2464 rtl_hw_start_8168bb(ioaddr, pdev);
2466 RTL_W8(EarlyTxThres, EarlyTxThld);
2468 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
2471 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2473 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2475 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2477 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2479 rtl_disable_clock_request(pdev);
2481 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2484 static void rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2486 static struct ephy_info e_info_8168cp[] = {
2487 { 0x01, 0, 0x0001 },
2488 { 0x02, 0x0800, 0x1000 },
2489 { 0x03, 0, 0x0042 },
2490 { 0x06, 0x0080, 0x0000 },
2494 rtl_csi_access_enable(ioaddr);
2496 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2498 __rtl_hw_start_8168cp(ioaddr, pdev);
2501 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2503 static struct ephy_info e_info_8168c_1[] = {
2504 { 0x02, 0x0800, 0x1000 },
2505 { 0x03, 0, 0x0002 },
2506 { 0x06, 0x0080, 0x0000 }
2509 rtl_csi_access_enable(ioaddr);
2511 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2513 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2515 __rtl_hw_start_8168cp(ioaddr, pdev);
2518 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2520 static struct ephy_info e_info_8168c_2[] = {
2521 { 0x01, 0, 0x0001 },
2522 { 0x03, 0x0400, 0x0220 }
2525 rtl_csi_access_enable(ioaddr);
2527 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2529 __rtl_hw_start_8168cp(ioaddr, pdev);
2532 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2534 rtl_hw_start_8168c_2(ioaddr, pdev);
2537 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2539 rtl_csi_access_enable(ioaddr);
2541 __rtl_hw_start_8168cp(ioaddr, pdev);
2544 static void rtl_hw_start_8168(struct net_device *dev)
2546 struct rtl8169_private *tp = netdev_priv(dev);
2547 void __iomem *ioaddr = tp->mmio_addr;
2548 struct pci_dev *pdev = tp->pci_dev;
2550 RTL_W8(Cfg9346, Cfg9346_Unlock);
2552 RTL_W8(EarlyTxThres, EarlyTxThld);
2554 rtl_set_rx_max_size(ioaddr);
2556 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2558 RTL_W16(CPlusCmd, tp->cp_cmd);
2560 RTL_W16(IntrMitigate, 0x5151);
2562 /* Work around for RxFIFO overflow. */
2563 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2564 tp->intr_event |= RxFIFOOver | PCSTimeout;
2565 tp->intr_event &= ~RxOverflow;
2568 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2570 rtl_set_rx_mode(dev);
2572 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2573 (InterFrameGap << TxInterFrameGapShift));
2577 switch (tp->mac_version) {
2578 case RTL_GIGA_MAC_VER_11:
2579 rtl_hw_start_8168bb(ioaddr, pdev);
2582 case RTL_GIGA_MAC_VER_12:
2583 case RTL_GIGA_MAC_VER_17:
2584 rtl_hw_start_8168bef(ioaddr, pdev);
2587 case RTL_GIGA_MAC_VER_18:
2588 rtl_hw_start_8168cp(ioaddr, pdev);
2591 case RTL_GIGA_MAC_VER_19:
2592 rtl_hw_start_8168c_1(ioaddr, pdev);
2595 case RTL_GIGA_MAC_VER_20:
2596 rtl_hw_start_8168c_2(ioaddr, pdev);
2599 case RTL_GIGA_MAC_VER_21:
2600 rtl_hw_start_8168c_3(ioaddr, pdev);
2603 case RTL_GIGA_MAC_VER_22:
2604 rtl_hw_start_8168c_4(ioaddr, pdev);
2608 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2609 dev->name, tp->mac_version);
2613 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2615 RTL_W8(Cfg9346, Cfg9346_Lock);
2617 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2619 RTL_W16(IntrMask, tp->intr_event);
2622 #define R810X_CPCMD_QUIRK_MASK (\
2634 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2636 static struct ephy_info e_info_8102e_1[] = {
2637 { 0x01, 0, 0x6e65 },
2638 { 0x02, 0, 0x091f },
2639 { 0x03, 0, 0xc2f9 },
2640 { 0x06, 0, 0xafb5 },
2641 { 0x07, 0, 0x0e00 },
2642 { 0x19, 0, 0xec80 },
2643 { 0x01, 0, 0x2e65 },
2648 rtl_csi_access_enable(ioaddr);
2650 RTL_W8(DBG_REG, FIX_NAK_1);
2652 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2655 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2656 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2658 cfg1 = RTL_R8(Config1);
2659 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2660 RTL_W8(Config1, cfg1 & ~LEDS0);
2662 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2664 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2667 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2669 rtl_csi_access_enable(ioaddr);
2671 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2673 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2674 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2676 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2679 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2681 rtl_hw_start_8102e_2(ioaddr, pdev);
2683 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2686 static void rtl_hw_start_8101(struct net_device *dev)
2688 struct rtl8169_private *tp = netdev_priv(dev);
2689 void __iomem *ioaddr = tp->mmio_addr;
2690 struct pci_dev *pdev = tp->pci_dev;
2692 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2693 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2694 int cap = tp->pcie_cap;
2697 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2698 PCI_EXP_DEVCTL_NOSNOOP_EN);
2702 switch (tp->mac_version) {
2703 case RTL_GIGA_MAC_VER_07:
2704 rtl_hw_start_8102e_1(ioaddr, pdev);
2707 case RTL_GIGA_MAC_VER_08:
2708 rtl_hw_start_8102e_3(ioaddr, pdev);
2711 case RTL_GIGA_MAC_VER_09:
2712 rtl_hw_start_8102e_2(ioaddr, pdev);
2716 RTL_W8(Cfg9346, Cfg9346_Unlock);
2718 RTL_W8(EarlyTxThres, EarlyTxThld);
2720 rtl_set_rx_max_size(ioaddr);
2722 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2724 RTL_W16(CPlusCmd, tp->cp_cmd);
2726 RTL_W16(IntrMitigate, 0x0000);
2728 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2730 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2731 rtl_set_rx_tx_config_registers(tp);
2733 RTL_W8(Cfg9346, Cfg9346_Lock);
2737 rtl_set_rx_mode(dev);
2739 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2741 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2743 RTL_W16(IntrMask, tp->intr_event);
2746 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2748 struct rtl8169_private *tp = netdev_priv(dev);
2751 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2756 if (!netif_running(dev))
2761 rtl8169_set_rxbufsize(tp, dev);
2763 ret = rtl8169_init_ring(dev);
2767 napi_enable(&tp->napi);
2771 rtl8169_request_timer(dev);
2777 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2779 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2780 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2783 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2784 struct sk_buff **sk_buff, struct RxDesc *desc)
2786 struct pci_dev *pdev = tp->pci_dev;
2788 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2789 PCI_DMA_FROMDEVICE);
2790 dev_kfree_skb(*sk_buff);
2792 rtl8169_make_unusable_by_asic(desc);
2795 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2797 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2799 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2802 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2805 desc->addr = cpu_to_le64(mapping);
2807 rtl8169_mark_to_asic(desc, rx_buf_sz);
2810 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2811 struct net_device *dev,
2812 struct RxDesc *desc, int rx_buf_sz,
2815 struct sk_buff *skb;
2819 pad = align ? align : NET_IP_ALIGN;
2821 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2825 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2827 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2828 PCI_DMA_FROMDEVICE);
2830 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2835 rtl8169_make_unusable_by_asic(desc);
2839 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2843 for (i = 0; i < NUM_RX_DESC; i++) {
2844 if (tp->Rx_skbuff[i]) {
2845 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2846 tp->RxDescArray + i);
2851 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2856 for (cur = start; end - cur != 0; cur++) {
2857 struct sk_buff *skb;
2858 unsigned int i = cur % NUM_RX_DESC;
2860 WARN_ON((s32)(end - cur) < 0);
2862 if (tp->Rx_skbuff[i])
2865 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2866 tp->RxDescArray + i,
2867 tp->rx_buf_sz, tp->align);
2871 tp->Rx_skbuff[i] = skb;
2876 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2878 desc->opts1 |= cpu_to_le32(RingEnd);
2881 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2883 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2886 static int rtl8169_init_ring(struct net_device *dev)
2888 struct rtl8169_private *tp = netdev_priv(dev);
2890 rtl8169_init_ring_indexes(tp);
2892 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2893 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2895 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2898 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2903 rtl8169_rx_clear(tp);
2907 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2908 struct TxDesc *desc)
2910 unsigned int len = tx_skb->len;
2912 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2919 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2923 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2924 unsigned int entry = i % NUM_TX_DESC;
2925 struct ring_info *tx_skb = tp->tx_skb + entry;
2926 unsigned int len = tx_skb->len;
2929 struct sk_buff *skb = tx_skb->skb;
2931 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2932 tp->TxDescArray + entry);
2937 tp->dev->stats.tx_dropped++;
2940 tp->cur_tx = tp->dirty_tx = 0;
2943 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2945 struct rtl8169_private *tp = netdev_priv(dev);
2947 PREPARE_DELAYED_WORK(&tp->task, task);
2948 schedule_delayed_work(&tp->task, 4);
2951 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2953 struct rtl8169_private *tp = netdev_priv(dev);
2954 void __iomem *ioaddr = tp->mmio_addr;
2956 synchronize_irq(dev->irq);
2958 /* Wait for any pending NAPI task to complete */
2959 napi_disable(&tp->napi);
2961 rtl8169_irq_mask_and_ack(ioaddr);
2963 tp->intr_mask = 0xffff;
2964 RTL_W16(IntrMask, tp->intr_event);
2965 napi_enable(&tp->napi);
2968 static void rtl8169_reinit_task(struct work_struct *work)
2970 struct rtl8169_private *tp =
2971 container_of(work, struct rtl8169_private, task.work);
2972 struct net_device *dev = tp->dev;
2977 if (!netif_running(dev))
2980 rtl8169_wait_for_quiescence(dev);
2983 ret = rtl8169_open(dev);
2984 if (unlikely(ret < 0)) {
2985 if (net_ratelimit() && netif_msg_drv(tp)) {
2986 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
2987 " Rescheduling.\n", dev->name, ret);
2989 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2996 static void rtl8169_reset_task(struct work_struct *work)
2998 struct rtl8169_private *tp =
2999 container_of(work, struct rtl8169_private, task.work);
3000 struct net_device *dev = tp->dev;
3004 if (!netif_running(dev))
3007 rtl8169_wait_for_quiescence(dev);
3009 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
3010 rtl8169_tx_clear(tp);
3012 if (tp->dirty_rx == tp->cur_rx) {
3013 rtl8169_init_ring_indexes(tp);
3015 netif_wake_queue(dev);
3016 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3018 if (net_ratelimit() && netif_msg_intr(tp)) {
3019 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
3022 rtl8169_schedule_work(dev, rtl8169_reset_task);
3029 static void rtl8169_tx_timeout(struct net_device *dev)
3031 struct rtl8169_private *tp = netdev_priv(dev);
3033 rtl8169_hw_reset(tp->mmio_addr);
3035 /* Let's wait a bit while any (async) irq lands on */
3036 rtl8169_schedule_work(dev, rtl8169_reset_task);
3039 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3042 struct skb_shared_info *info = skb_shinfo(skb);
3043 unsigned int cur_frag, entry;
3044 struct TxDesc * uninitialized_var(txd);
3047 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3048 skb_frag_t *frag = info->frags + cur_frag;
3053 entry = (entry + 1) % NUM_TX_DESC;
3055 txd = tp->TxDescArray + entry;
3057 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3058 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3060 /* anti gcc 2.95.3 bugware (sic) */
3061 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3063 txd->opts1 = cpu_to_le32(status);
3064 txd->addr = cpu_to_le64(mapping);
3066 tp->tx_skb[entry].len = len;
3070 tp->tx_skb[entry].skb = skb;
3071 txd->opts1 |= cpu_to_le32(LastFrag);
3077 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3079 if (dev->features & NETIF_F_TSO) {
3080 u32 mss = skb_shinfo(skb)->gso_size;
3083 return LargeSend | ((mss & MSSMask) << MSSShift);
3085 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3086 const struct iphdr *ip = ip_hdr(skb);
3088 if (ip->protocol == IPPROTO_TCP)
3089 return IPCS | TCPCS;
3090 else if (ip->protocol == IPPROTO_UDP)
3091 return IPCS | UDPCS;
3092 WARN_ON(1); /* we need a WARN() */
3097 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3099 struct rtl8169_private *tp = netdev_priv(dev);
3100 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3101 struct TxDesc *txd = tp->TxDescArray + entry;
3102 void __iomem *ioaddr = tp->mmio_addr;
3106 int ret = NETDEV_TX_OK;
3108 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3109 if (netif_msg_drv(tp)) {
3111 "%s: BUG! Tx Ring full when queue awake!\n",
3117 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3120 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3122 frags = rtl8169_xmit_frags(tp, skb, opts1);
3124 len = skb_headlen(skb);
3129 if (unlikely(len < ETH_ZLEN)) {
3130 if (skb_padto(skb, ETH_ZLEN))
3131 goto err_update_stats;
3135 opts1 |= FirstFrag | LastFrag;
3136 tp->tx_skb[entry].skb = skb;
3139 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3141 tp->tx_skb[entry].len = len;
3142 txd->addr = cpu_to_le64(mapping);
3143 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3147 /* anti gcc 2.95.3 bugware (sic) */
3148 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3149 txd->opts1 = cpu_to_le32(status);
3151 dev->trans_start = jiffies;
3153 tp->cur_tx += frags + 1;
3157 RTL_W8(TxPoll, NPQ); /* set polling bit */
3159 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3160 netif_stop_queue(dev);
3162 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3163 netif_wake_queue(dev);
3170 netif_stop_queue(dev);
3171 ret = NETDEV_TX_BUSY;
3173 dev->stats.tx_dropped++;
3177 static void rtl8169_pcierr_interrupt(struct net_device *dev)
3179 struct rtl8169_private *tp = netdev_priv(dev);
3180 struct pci_dev *pdev = tp->pci_dev;
3181 void __iomem *ioaddr = tp->mmio_addr;
3182 u16 pci_status, pci_cmd;
3184 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3185 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3187 if (netif_msg_intr(tp)) {
3189 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3190 dev->name, pci_cmd, pci_status);
3194 * The recovery sequence below admits a very elaborated explanation:
3195 * - it seems to work;
3196 * - I did not see what else could be done;
3197 * - it makes iop3xx happy.
3199 * Feel free to adjust to your needs.
3201 if (pdev->broken_parity_status)
3202 pci_cmd &= ~PCI_COMMAND_PARITY;
3204 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3206 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3208 pci_write_config_word(pdev, PCI_STATUS,
3209 pci_status & (PCI_STATUS_DETECTED_PARITY |
3210 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3211 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3213 /* The infamous DAC f*ckup only happens at boot time */
3214 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3215 if (netif_msg_intr(tp))
3216 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
3217 tp->cp_cmd &= ~PCIDAC;
3218 RTL_W16(CPlusCmd, tp->cp_cmd);
3219 dev->features &= ~NETIF_F_HIGHDMA;
3222 rtl8169_hw_reset(ioaddr);
3224 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3227 static void rtl8169_tx_interrupt(struct net_device *dev,
3228 struct rtl8169_private *tp,
3229 void __iomem *ioaddr)
3231 unsigned int dirty_tx, tx_left;
3233 dirty_tx = tp->dirty_tx;
3235 tx_left = tp->cur_tx - dirty_tx;
3237 while (tx_left > 0) {
3238 unsigned int entry = dirty_tx % NUM_TX_DESC;
3239 struct ring_info *tx_skb = tp->tx_skb + entry;
3240 u32 len = tx_skb->len;
3244 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3245 if (status & DescOwn)
3248 dev->stats.tx_bytes += len;
3249 dev->stats.tx_packets++;
3251 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3253 if (status & LastFrag) {
3254 dev_kfree_skb_irq(tx_skb->skb);
3261 if (tp->dirty_tx != dirty_tx) {
3262 tp->dirty_tx = dirty_tx;
3264 if (netif_queue_stopped(dev) &&
3265 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3266 netif_wake_queue(dev);
3269 * 8168 hack: TxPoll requests are lost when the Tx packets are
3270 * too close. Let's kick an extra TxPoll request when a burst
3271 * of start_xmit activity is detected (if it is not detected,
3272 * it is slow enough). -- FR
3275 if (tp->cur_tx != dirty_tx)
3276 RTL_W8(TxPoll, NPQ);
3280 static inline int rtl8169_fragmented_frame(u32 status)
3282 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3285 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3287 u32 opts1 = le32_to_cpu(desc->opts1);
3288 u32 status = opts1 & RxProtoMask;
3290 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3291 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3292 ((status == RxProtoIP) && !(opts1 & IPFail)))
3293 skb->ip_summed = CHECKSUM_UNNECESSARY;
3295 skb->ip_summed = CHECKSUM_NONE;
3298 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3299 struct rtl8169_private *tp, int pkt_size,
3302 struct sk_buff *skb;
3305 if (pkt_size >= rx_copybreak)
3308 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3312 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3313 PCI_DMA_FROMDEVICE);
3314 skb_reserve(skb, NET_IP_ALIGN);
3315 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3322 static int rtl8169_rx_interrupt(struct net_device *dev,
3323 struct rtl8169_private *tp,
3324 void __iomem *ioaddr, u32 budget)
3326 unsigned int cur_rx, rx_left;
3327 unsigned int delta, count;
3329 cur_rx = tp->cur_rx;
3330 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3331 rx_left = min(rx_left, budget);
3333 for (; rx_left > 0; rx_left--, cur_rx++) {
3334 unsigned int entry = cur_rx % NUM_RX_DESC;
3335 struct RxDesc *desc = tp->RxDescArray + entry;
3339 status = le32_to_cpu(desc->opts1);
3341 if (status & DescOwn)
3343 if (unlikely(status & RxRES)) {
3344 if (netif_msg_rx_err(tp)) {
3346 "%s: Rx ERROR. status = %08x\n",
3349 dev->stats.rx_errors++;
3350 if (status & (RxRWT | RxRUNT))
3351 dev->stats.rx_length_errors++;
3353 dev->stats.rx_crc_errors++;
3354 if (status & RxFOVF) {
3355 rtl8169_schedule_work(dev, rtl8169_reset_task);
3356 dev->stats.rx_fifo_errors++;
3358 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3360 struct sk_buff *skb = tp->Rx_skbuff[entry];
3361 dma_addr_t addr = le64_to_cpu(desc->addr);
3362 int pkt_size = (status & 0x00001FFF) - 4;
3363 struct pci_dev *pdev = tp->pci_dev;
3366 * The driver does not support incoming fragmented
3367 * frames. They are seen as a symptom of over-mtu
3370 if (unlikely(rtl8169_fragmented_frame(status))) {
3371 dev->stats.rx_dropped++;
3372 dev->stats.rx_length_errors++;
3373 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3377 rtl8169_rx_csum(skb, desc);
3379 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3380 pci_dma_sync_single_for_device(pdev, addr,
3381 pkt_size, PCI_DMA_FROMDEVICE);
3382 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3384 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
3385 PCI_DMA_FROMDEVICE);
3386 tp->Rx_skbuff[entry] = NULL;
3389 skb_put(skb, pkt_size);
3390 skb->protocol = eth_type_trans(skb, dev);
3392 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3393 netif_receive_skb(skb);
3395 dev->last_rx = jiffies;
3396 dev->stats.rx_bytes += pkt_size;
3397 dev->stats.rx_packets++;
3400 /* Work around for AMD plateform. */
3401 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3402 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3408 count = cur_rx - tp->cur_rx;
3409 tp->cur_rx = cur_rx;
3411 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3412 if (!delta && count && netif_msg_intr(tp))
3413 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3414 tp->dirty_rx += delta;
3417 * FIXME: until there is periodic timer to try and refill the ring,
3418 * a temporary shortage may definitely kill the Rx process.
3419 * - disable the asic to try and avoid an overflow and kick it again
3421 * - how do others driver handle this condition (Uh oh...).
3423 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3424 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3429 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3431 struct net_device *dev = dev_instance;
3432 struct rtl8169_private *tp = netdev_priv(dev);
3433 void __iomem *ioaddr = tp->mmio_addr;
3437 status = RTL_R16(IntrStatus);
3439 /* hotplug/major error/no more work/shared irq */
3440 if ((status == 0xffff) || !status)
3445 if (unlikely(!netif_running(dev))) {
3446 rtl8169_asic_down(ioaddr);
3450 status &= tp->intr_mask;
3452 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3454 if (!(status & tp->intr_event))
3457 /* Work around for rx fifo overflow */
3458 if (unlikely(status & RxFIFOOver) &&
3459 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3460 netif_stop_queue(dev);
3461 rtl8169_tx_timeout(dev);
3465 if (unlikely(status & SYSErr)) {
3466 rtl8169_pcierr_interrupt(dev);
3470 if (status & LinkChg)
3471 rtl8169_check_link_status(dev, tp, ioaddr);
3473 if (status & tp->napi_event) {
3474 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3475 tp->intr_mask = ~tp->napi_event;
3477 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
3478 __netif_rx_schedule(dev, &tp->napi);
3479 else if (netif_msg_intr(tp)) {
3480 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3485 return IRQ_RETVAL(handled);
3488 static int rtl8169_poll(struct napi_struct *napi, int budget)
3490 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3491 struct net_device *dev = tp->dev;
3492 void __iomem *ioaddr = tp->mmio_addr;
3495 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3496 rtl8169_tx_interrupt(dev, tp, ioaddr);
3498 if (work_done < budget) {
3499 netif_rx_complete(dev, napi);
3500 tp->intr_mask = 0xffff;
3502 * 20040426: the barrier is not strictly required but the
3503 * behavior of the irq handler could be less predictable
3504 * without it. Btw, the lack of flush for the posted pci
3505 * write is safe - FR
3508 RTL_W16(IntrMask, tp->intr_event);
3514 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3516 struct rtl8169_private *tp = netdev_priv(dev);
3518 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3521 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3522 RTL_W32(RxMissed, 0);
3525 static void rtl8169_down(struct net_device *dev)
3527 struct rtl8169_private *tp = netdev_priv(dev);
3528 void __iomem *ioaddr = tp->mmio_addr;
3529 unsigned int intrmask;
3531 rtl8169_delete_timer(dev);
3533 netif_stop_queue(dev);
3535 napi_disable(&tp->napi);
3538 spin_lock_irq(&tp->lock);
3540 rtl8169_asic_down(ioaddr);
3542 rtl8169_rx_missed(dev, ioaddr);
3544 spin_unlock_irq(&tp->lock);
3546 synchronize_irq(dev->irq);
3548 /* Give a racing hard_start_xmit a few cycles to complete. */
3549 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3552 * And now for the 50k$ question: are IRQ disabled or not ?
3554 * Two paths lead here:
3556 * -> netif_running() is available to sync the current code and the
3557 * IRQ handler. See rtl8169_interrupt for details.
3558 * 2) dev->change_mtu
3559 * -> rtl8169_poll can not be issued again and re-enable the
3560 * interruptions. Let's simply issue the IRQ down sequence again.
3562 * No loop if hotpluged or major error (0xffff).
3564 intrmask = RTL_R16(IntrMask);
3565 if (intrmask && (intrmask != 0xffff))
3568 rtl8169_tx_clear(tp);
3570 rtl8169_rx_clear(tp);
3573 static int rtl8169_close(struct net_device *dev)
3575 struct rtl8169_private *tp = netdev_priv(dev);
3576 struct pci_dev *pdev = tp->pci_dev;
3580 free_irq(dev->irq, dev);
3582 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3584 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3586 tp->TxDescArray = NULL;
3587 tp->RxDescArray = NULL;
3592 static void rtl_set_rx_mode(struct net_device *dev)
3594 struct rtl8169_private *tp = netdev_priv(dev);
3595 void __iomem *ioaddr = tp->mmio_addr;
3596 unsigned long flags;
3597 u32 mc_filter[2]; /* Multicast hash filter */
3601 if (dev->flags & IFF_PROMISC) {
3602 /* Unconditionally log net taps. */
3603 if (netif_msg_link(tp)) {
3604 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3608 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3610 mc_filter[1] = mc_filter[0] = 0xffffffff;
3611 } else if ((dev->mc_count > multicast_filter_limit)
3612 || (dev->flags & IFF_ALLMULTI)) {
3613 /* Too many to filter perfectly -- accept all multicasts. */
3614 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3615 mc_filter[1] = mc_filter[0] = 0xffffffff;
3617 struct dev_mc_list *mclist;
3620 rx_mode = AcceptBroadcast | AcceptMyPhys;
3621 mc_filter[1] = mc_filter[0] = 0;
3622 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3623 i++, mclist = mclist->next) {
3624 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3625 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3626 rx_mode |= AcceptMulticast;
3630 spin_lock_irqsave(&tp->lock, flags);
3632 tmp = rtl8169_rx_config | rx_mode |
3633 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3635 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3636 u32 data = mc_filter[0];
3638 mc_filter[0] = swab32(mc_filter[1]);
3639 mc_filter[1] = swab32(data);
3642 RTL_W32(MAR0 + 0, mc_filter[0]);
3643 RTL_W32(MAR0 + 4, mc_filter[1]);
3645 RTL_W32(RxConfig, tmp);
3647 spin_unlock_irqrestore(&tp->lock, flags);
3651 * rtl8169_get_stats - Get rtl8169 read/write statistics
3652 * @dev: The Ethernet Device to get statistics for
3654 * Get TX/RX statistics for rtl8169
3656 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3658 struct rtl8169_private *tp = netdev_priv(dev);
3659 void __iomem *ioaddr = tp->mmio_addr;
3660 unsigned long flags;
3662 if (netif_running(dev)) {
3663 spin_lock_irqsave(&tp->lock, flags);
3664 rtl8169_rx_missed(dev, ioaddr);
3665 spin_unlock_irqrestore(&tp->lock, flags);
3673 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3675 struct net_device *dev = pci_get_drvdata(pdev);
3676 struct rtl8169_private *tp = netdev_priv(dev);
3677 void __iomem *ioaddr = tp->mmio_addr;
3679 if (!netif_running(dev))
3680 goto out_pci_suspend;
3682 netif_device_detach(dev);
3683 netif_stop_queue(dev);
3685 spin_lock_irq(&tp->lock);
3687 rtl8169_asic_down(ioaddr);
3689 rtl8169_rx_missed(dev, ioaddr);
3691 spin_unlock_irq(&tp->lock);
3694 pci_save_state(pdev);
3695 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3696 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3697 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3702 static int rtl8169_resume(struct pci_dev *pdev)
3704 struct net_device *dev = pci_get_drvdata(pdev);
3706 pci_set_power_state(pdev, PCI_D0);
3707 pci_restore_state(pdev);
3708 pci_enable_wake(pdev, PCI_D0, 0);
3710 if (!netif_running(dev))
3713 netif_device_attach(dev);
3715 rtl8169_schedule_work(dev, rtl8169_reset_task);
3720 #endif /* CONFIG_PM */
3722 static struct pci_driver rtl8169_pci_driver = {
3724 .id_table = rtl8169_pci_tbl,
3725 .probe = rtl8169_init_one,
3726 .remove = __devexit_p(rtl8169_remove_one),
3728 .suspend = rtl8169_suspend,
3729 .resume = rtl8169_resume,
3733 static int __init rtl8169_init_module(void)
3735 return pci_register_driver(&rtl8169_pci_driver);
3738 static void __exit rtl8169_cleanup_module(void)
3740 pci_unregister_driver(&rtl8169_pci_driver);
3743 module_init(rtl8169_init_module);
3744 module_exit(rtl8169_cleanup_module);