2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #ifdef CONFIG_R8169_NAPI
32 #define NAPI_SUFFIX "-NAPI"
34 #define NAPI_SUFFIX ""
37 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
38 #define MODULENAME "r8169"
39 #define PFX MODULENAME ": "
42 #define assert(expr) \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
47 #define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
49 #define assert(expr) do {} while (0)
50 #define dprintk(fmt, args...) do {} while (0)
51 #endif /* RTL8169_DEBUG */
53 #define R8169_MSG_DEFAULT \
54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
56 #define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
59 #ifdef CONFIG_R8169_NAPI
60 #define rtl8169_rx_skb netif_receive_skb
61 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
62 #define rtl8169_rx_quota(count, quota) min(count, quota)
64 #define rtl8169_rx_skb netif_rx
65 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
66 #define rtl8169_rx_quota(count, quota) count
69 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
70 static const int max_interrupt_work = 20;
72 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
73 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
74 static const int multicast_filter_limit = 32;
76 /* MAC address length */
77 #define MAC_ADDR_LEN 6
79 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
80 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
81 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
83 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
84 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
85 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
87 #define R8169_REGS_SIZE 256
88 #define R8169_NAPI_WEIGHT 64
89 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
90 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
91 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
92 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
93 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
95 #define RTL8169_TX_TIMEOUT (6*HZ)
96 #define RTL8169_PHY_TIMEOUT (10*HZ)
98 /* write/read MMIO register */
99 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
100 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
101 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
102 #define RTL_R8(reg) readb (ioaddr + (reg))
103 #define RTL_R16(reg) readw (ioaddr + (reg))
104 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
107 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
108 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
109 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
110 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
111 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
112 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
113 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
114 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
115 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
116 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
117 RTL_GIGA_MAC_VER_15 = 0x0f // 8101
121 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
122 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
123 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
124 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
125 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
126 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
129 #define _R(NAME,MAC,MASK) \
130 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
132 static const struct {
135 u32 RxConfigMask; /* Clears the bits supported by this chip */
136 } rtl_chip_info[] = {
137 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
138 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
139 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
140 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
142 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
147 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
157 static void rtl_hw_start_8169(struct net_device *);
158 static void rtl_hw_start_8168(struct net_device *);
159 static void rtl_hw_start_8101(struct net_device *);
161 static struct pci_device_id rtl8169_pci_tbl[] = {
162 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
167 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
168 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
169 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
170 { PCI_VENDOR_ID_LINKSYS, 0x1032,
171 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
175 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
177 static int rx_copybreak = 200;
184 MAC0 = 0, /* Ethernet hardware address. */
185 MAR0 = 8, /* Multicast filter. */
186 CounterAddrLow = 0x10,
187 CounterAddrHigh = 0x14,
188 TxDescStartAddrLow = 0x20,
189 TxDescStartAddrHigh = 0x24,
190 TxHDescStartAddrLow = 0x28,
191 TxHDescStartAddrHigh = 0x2c,
217 RxDescAddrLow = 0xe4,
218 RxDescAddrHigh = 0xe8,
221 FuncEventMask = 0xf4,
222 FuncPresetState = 0xf8,
223 FuncForceEvent = 0xfc,
226 enum rtl_register_content {
227 /* InterruptStatusBits */
231 TxDescUnavail = 0x0080,
253 /* TXPoll register p.5 */
254 HPQ = 0x80, /* Poll cmd on the high prio queue */
255 NPQ = 0x40, /* Poll cmd on the low prio queue */
256 FSWInt = 0x01, /* Forced software interrupt */
260 Cfg9346_Unlock = 0xc0,
265 AcceptBroadcast = 0x08,
266 AcceptMulticast = 0x04,
268 AcceptAllPhys = 0x01,
275 TxInterFrameGapShift = 24,
276 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
278 /* Config1 register p.24 */
279 PMEnable = (1 << 0), /* Power Management Enable */
281 /* Config2 register p. 25 */
282 PCI_Clock_66MHz = 0x01,
283 PCI_Clock_33MHz = 0x00,
285 /* Config3 register p.25 */
286 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
287 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
289 /* Config5 register p.27 */
290 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
291 MWF = (1 << 5), /* Accept Multicast wakeup frame */
292 UWF = (1 << 4), /* Accept Unicast wakeup frame */
293 LanWake = (1 << 1), /* LanWake enable/disable */
294 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
297 TBIReset = 0x80000000,
298 TBILoopback = 0x40000000,
299 TBINwEnable = 0x20000000,
300 TBINwRestart = 0x10000000,
301 TBILinkOk = 0x02000000,
302 TBINwComplete = 0x01000000,
305 PktCntrDisable = (1 << 7), // 8168
310 INTT_0 = 0x0000, // 8168
311 INTT_1 = 0x0001, // 8168
312 INTT_2 = 0x0002, // 8168
313 INTT_3 = 0x0003, // 8168
315 /* rtl8169_PHYstatus */
326 TBILinkOK = 0x02000000,
328 /* DumpCounterCommand */
332 enum desc_status_bit {
333 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
334 RingEnd = (1 << 30), /* End of descriptor ring */
335 FirstFrag = (1 << 29), /* First segment of a packet */
336 LastFrag = (1 << 28), /* Final segment of a packet */
339 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
340 MSSShift = 16, /* MSS value position */
341 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
342 IPCS = (1 << 18), /* Calculate IP checksum */
343 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
344 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
345 TxVlanTag = (1 << 17), /* Add VLAN tag */
348 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
349 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
351 #define RxProtoUDP (PID1)
352 #define RxProtoTCP (PID0)
353 #define RxProtoIP (PID1 | PID0)
354 #define RxProtoMask RxProtoIP
356 IPFail = (1 << 16), /* IP checksum failed */
357 UDPFail = (1 << 15), /* UDP/IP checksum failed */
358 TCPFail = (1 << 14), /* TCP/IP checksum failed */
359 RxVlanTag = (1 << 16), /* VLAN tag available */
362 #define RsvdMask 0x3fffc000
379 u8 __pad[sizeof(void *) - sizeof(u32)];
382 struct rtl8169_private {
383 void __iomem *mmio_addr; /* memory map physical address */
384 struct pci_dev *pci_dev; /* Index of PCI device */
385 struct net_device *dev;
386 struct net_device_stats stats; /* statistics of net device */
387 spinlock_t lock; /* spin lock flag */
392 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
393 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
396 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
397 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
398 dma_addr_t TxPhyAddr;
399 dma_addr_t RxPhyAddr;
400 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
401 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
404 struct timer_list timer;
409 int phy_auto_nego_reg;
410 int phy_1000_ctrl_reg;
411 #ifdef CONFIG_R8169_VLAN
412 struct vlan_group *vlgrp;
414 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
415 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
416 void (*phy_reset_enable)(void __iomem *);
417 void (*hw_start)(struct net_device *);
418 unsigned int (*phy_reset_pending)(void __iomem *);
419 unsigned int (*link_ok)(void __iomem *);
420 struct delayed_work task;
421 unsigned wol_enabled : 1;
424 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
425 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
426 module_param(rx_copybreak, int, 0);
427 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
428 module_param(use_dac, int, 0);
429 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
430 module_param_named(debug, debug.msg_enable, int, 0);
431 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
432 MODULE_LICENSE("GPL");
433 MODULE_VERSION(RTL8169_VERSION);
435 static int rtl8169_open(struct net_device *dev);
436 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
437 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
438 static int rtl8169_init_ring(struct net_device *dev);
439 static void rtl_hw_start(struct net_device *dev);
440 static int rtl8169_close(struct net_device *dev);
441 static void rtl_set_rx_mode(struct net_device *dev);
442 static void rtl8169_tx_timeout(struct net_device *dev);
443 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
444 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
446 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
447 static void rtl8169_down(struct net_device *dev);
448 static void rtl8169_rx_clear(struct rtl8169_private *tp);
450 #ifdef CONFIG_R8169_NAPI
451 static int rtl8169_poll(struct net_device *dev, int *budget);
454 static const unsigned int rtl8169_rx_config =
455 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
457 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
461 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
463 for (i = 20; i > 0; i--) {
465 * Check if the RTL8169 has completed writing to the specified
468 if (!(RTL_R32(PHYAR) & 0x80000000))
474 static int mdio_read(void __iomem *ioaddr, int reg_addr)
478 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
480 for (i = 20; i > 0; i--) {
482 * Check if the RTL8169 has completed retrieving data from
483 * the specified MII register.
485 if (RTL_R32(PHYAR) & 0x80000000) {
486 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
494 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
496 RTL_W16(IntrMask, 0x0000);
498 RTL_W16(IntrStatus, 0xffff);
501 static void rtl8169_asic_down(void __iomem *ioaddr)
503 RTL_W8(ChipCmd, 0x00);
504 rtl8169_irq_mask_and_ack(ioaddr);
508 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
510 return RTL_R32(TBICSR) & TBIReset;
513 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
515 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
518 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
520 return RTL_R32(TBICSR) & TBILinkOk;
523 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
525 return RTL_R8(PHYstatus) & LinkStatus;
528 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
530 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
533 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
537 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
538 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
541 static void rtl8169_check_link_status(struct net_device *dev,
542 struct rtl8169_private *tp,
543 void __iomem *ioaddr)
547 spin_lock_irqsave(&tp->lock, flags);
548 if (tp->link_ok(ioaddr)) {
549 netif_carrier_on(dev);
550 if (netif_msg_ifup(tp))
551 printk(KERN_INFO PFX "%s: link up\n", dev->name);
553 if (netif_msg_ifdown(tp))
554 printk(KERN_INFO PFX "%s: link down\n", dev->name);
555 netif_carrier_off(dev);
557 spin_unlock_irqrestore(&tp->lock, flags);
560 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
562 struct rtl8169_private *tp = netdev_priv(dev);
563 void __iomem *ioaddr = tp->mmio_addr;
568 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
569 wol->supported = WAKE_ANY;
571 spin_lock_irq(&tp->lock);
573 options = RTL_R8(Config1);
574 if (!(options & PMEnable))
577 options = RTL_R8(Config3);
578 if (options & LinkUp)
579 wol->wolopts |= WAKE_PHY;
580 if (options & MagicPacket)
581 wol->wolopts |= WAKE_MAGIC;
583 options = RTL_R8(Config5);
585 wol->wolopts |= WAKE_UCAST;
587 wol->wolopts |= WAKE_BCAST;
589 wol->wolopts |= WAKE_MCAST;
592 spin_unlock_irq(&tp->lock);
595 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
597 struct rtl8169_private *tp = netdev_priv(dev);
598 void __iomem *ioaddr = tp->mmio_addr;
605 { WAKE_ANY, Config1, PMEnable },
606 { WAKE_PHY, Config3, LinkUp },
607 { WAKE_MAGIC, Config3, MagicPacket },
608 { WAKE_UCAST, Config5, UWF },
609 { WAKE_BCAST, Config5, BWF },
610 { WAKE_MCAST, Config5, MWF },
611 { WAKE_ANY, Config5, LanWake }
614 spin_lock_irq(&tp->lock);
616 RTL_W8(Cfg9346, Cfg9346_Unlock);
618 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
619 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
620 if (wol->wolopts & cfg[i].opt)
621 options |= cfg[i].mask;
622 RTL_W8(cfg[i].reg, options);
625 RTL_W8(Cfg9346, Cfg9346_Lock);
627 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
629 spin_unlock_irq(&tp->lock);
634 static void rtl8169_get_drvinfo(struct net_device *dev,
635 struct ethtool_drvinfo *info)
637 struct rtl8169_private *tp = netdev_priv(dev);
639 strcpy(info->driver, MODULENAME);
640 strcpy(info->version, RTL8169_VERSION);
641 strcpy(info->bus_info, pci_name(tp->pci_dev));
644 static int rtl8169_get_regs_len(struct net_device *dev)
646 return R8169_REGS_SIZE;
649 static int rtl8169_set_speed_tbi(struct net_device *dev,
650 u8 autoneg, u16 speed, u8 duplex)
652 struct rtl8169_private *tp = netdev_priv(dev);
653 void __iomem *ioaddr = tp->mmio_addr;
657 reg = RTL_R32(TBICSR);
658 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
659 (duplex == DUPLEX_FULL)) {
660 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
661 } else if (autoneg == AUTONEG_ENABLE)
662 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
664 if (netif_msg_link(tp)) {
665 printk(KERN_WARNING "%s: "
666 "incorrect speed setting refused in TBI mode\n",
675 static int rtl8169_set_speed_xmii(struct net_device *dev,
676 u8 autoneg, u16 speed, u8 duplex)
678 struct rtl8169_private *tp = netdev_priv(dev);
679 void __iomem *ioaddr = tp->mmio_addr;
680 int auto_nego, giga_ctrl;
682 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
683 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
684 ADVERTISE_100HALF | ADVERTISE_100FULL);
685 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
686 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
688 if (autoneg == AUTONEG_ENABLE) {
689 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
690 ADVERTISE_100HALF | ADVERTISE_100FULL);
691 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
693 if (speed == SPEED_10)
694 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
695 else if (speed == SPEED_100)
696 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
697 else if (speed == SPEED_1000)
698 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
700 if (duplex == DUPLEX_HALF)
701 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
703 if (duplex == DUPLEX_FULL)
704 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
706 /* This tweak comes straight from Realtek's driver. */
707 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
708 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
709 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
713 /* The 8100e/8101e do Fast Ethernet only. */
714 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
715 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
716 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
717 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
718 netif_msg_link(tp)) {
719 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
722 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
725 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
727 tp->phy_auto_nego_reg = auto_nego;
728 tp->phy_1000_ctrl_reg = giga_ctrl;
730 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
731 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
732 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
736 static int rtl8169_set_speed(struct net_device *dev,
737 u8 autoneg, u16 speed, u8 duplex)
739 struct rtl8169_private *tp = netdev_priv(dev);
742 ret = tp->set_speed(dev, autoneg, speed, duplex);
744 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
745 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
750 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
752 struct rtl8169_private *tp = netdev_priv(dev);
756 spin_lock_irqsave(&tp->lock, flags);
757 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
758 spin_unlock_irqrestore(&tp->lock, flags);
763 static u32 rtl8169_get_rx_csum(struct net_device *dev)
765 struct rtl8169_private *tp = netdev_priv(dev);
767 return tp->cp_cmd & RxChkSum;
770 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
772 struct rtl8169_private *tp = netdev_priv(dev);
773 void __iomem *ioaddr = tp->mmio_addr;
776 spin_lock_irqsave(&tp->lock, flags);
779 tp->cp_cmd |= RxChkSum;
781 tp->cp_cmd &= ~RxChkSum;
783 RTL_W16(CPlusCmd, tp->cp_cmd);
786 spin_unlock_irqrestore(&tp->lock, flags);
791 #ifdef CONFIG_R8169_VLAN
793 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
796 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
797 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
800 static void rtl8169_vlan_rx_register(struct net_device *dev,
801 struct vlan_group *grp)
803 struct rtl8169_private *tp = netdev_priv(dev);
804 void __iomem *ioaddr = tp->mmio_addr;
807 spin_lock_irqsave(&tp->lock, flags);
810 tp->cp_cmd |= RxVlan;
812 tp->cp_cmd &= ~RxVlan;
813 RTL_W16(CPlusCmd, tp->cp_cmd);
815 spin_unlock_irqrestore(&tp->lock, flags);
818 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
821 u32 opts2 = le32_to_cpu(desc->opts2);
824 if (tp->vlgrp && (opts2 & RxVlanTag)) {
825 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
833 #else /* !CONFIG_R8169_VLAN */
835 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
841 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
849 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
851 struct rtl8169_private *tp = netdev_priv(dev);
852 void __iomem *ioaddr = tp->mmio_addr;
856 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
857 cmd->port = PORT_FIBRE;
858 cmd->transceiver = XCVR_INTERNAL;
860 status = RTL_R32(TBICSR);
861 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
862 cmd->autoneg = !!(status & TBINwEnable);
864 cmd->speed = SPEED_1000;
865 cmd->duplex = DUPLEX_FULL; /* Always set */
868 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
870 struct rtl8169_private *tp = netdev_priv(dev);
871 void __iomem *ioaddr = tp->mmio_addr;
874 cmd->supported = SUPPORTED_10baseT_Half |
875 SUPPORTED_10baseT_Full |
876 SUPPORTED_100baseT_Half |
877 SUPPORTED_100baseT_Full |
878 SUPPORTED_1000baseT_Full |
883 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
885 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
886 cmd->advertising |= ADVERTISED_10baseT_Half;
887 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
888 cmd->advertising |= ADVERTISED_10baseT_Full;
889 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
890 cmd->advertising |= ADVERTISED_100baseT_Half;
891 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
892 cmd->advertising |= ADVERTISED_100baseT_Full;
893 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
894 cmd->advertising |= ADVERTISED_1000baseT_Full;
896 status = RTL_R8(PHYstatus);
898 if (status & _1000bpsF)
899 cmd->speed = SPEED_1000;
900 else if (status & _100bps)
901 cmd->speed = SPEED_100;
902 else if (status & _10bps)
903 cmd->speed = SPEED_10;
905 if (status & TxFlowCtrl)
906 cmd->advertising |= ADVERTISED_Asym_Pause;
907 if (status & RxFlowCtrl)
908 cmd->advertising |= ADVERTISED_Pause;
910 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
911 DUPLEX_FULL : DUPLEX_HALF;
914 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
916 struct rtl8169_private *tp = netdev_priv(dev);
919 spin_lock_irqsave(&tp->lock, flags);
921 tp->get_settings(dev, cmd);
923 spin_unlock_irqrestore(&tp->lock, flags);
927 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
930 struct rtl8169_private *tp = netdev_priv(dev);
933 if (regs->len > R8169_REGS_SIZE)
934 regs->len = R8169_REGS_SIZE;
936 spin_lock_irqsave(&tp->lock, flags);
937 memcpy_fromio(p, tp->mmio_addr, regs->len);
938 spin_unlock_irqrestore(&tp->lock, flags);
941 static u32 rtl8169_get_msglevel(struct net_device *dev)
943 struct rtl8169_private *tp = netdev_priv(dev);
945 return tp->msg_enable;
948 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
950 struct rtl8169_private *tp = netdev_priv(dev);
952 tp->msg_enable = value;
955 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
962 "tx_single_collisions",
963 "tx_multi_collisions",
971 struct rtl8169_counters {
978 u32 tx_one_collision;
979 u32 tx_multi_collision;
987 static int rtl8169_get_stats_count(struct net_device *dev)
989 return ARRAY_SIZE(rtl8169_gstrings);
992 static void rtl8169_get_ethtool_stats(struct net_device *dev,
993 struct ethtool_stats *stats, u64 *data)
995 struct rtl8169_private *tp = netdev_priv(dev);
996 void __iomem *ioaddr = tp->mmio_addr;
997 struct rtl8169_counters *counters;
1003 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1007 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1008 cmd = (u64)paddr & DMA_32BIT_MASK;
1009 RTL_W32(CounterAddrLow, cmd);
1010 RTL_W32(CounterAddrLow, cmd | CounterDump);
1012 while (RTL_R32(CounterAddrLow) & CounterDump) {
1013 if (msleep_interruptible(1))
1017 RTL_W32(CounterAddrLow, 0);
1018 RTL_W32(CounterAddrHigh, 0);
1020 data[0] = le64_to_cpu(counters->tx_packets);
1021 data[1] = le64_to_cpu(counters->rx_packets);
1022 data[2] = le64_to_cpu(counters->tx_errors);
1023 data[3] = le32_to_cpu(counters->rx_errors);
1024 data[4] = le16_to_cpu(counters->rx_missed);
1025 data[5] = le16_to_cpu(counters->align_errors);
1026 data[6] = le32_to_cpu(counters->tx_one_collision);
1027 data[7] = le32_to_cpu(counters->tx_multi_collision);
1028 data[8] = le64_to_cpu(counters->rx_unicast);
1029 data[9] = le64_to_cpu(counters->rx_broadcast);
1030 data[10] = le32_to_cpu(counters->rx_multicast);
1031 data[11] = le16_to_cpu(counters->tx_aborted);
1032 data[12] = le16_to_cpu(counters->tx_underun);
1034 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1037 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1041 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1046 static const struct ethtool_ops rtl8169_ethtool_ops = {
1047 .get_drvinfo = rtl8169_get_drvinfo,
1048 .get_regs_len = rtl8169_get_regs_len,
1049 .get_link = ethtool_op_get_link,
1050 .get_settings = rtl8169_get_settings,
1051 .set_settings = rtl8169_set_settings,
1052 .get_msglevel = rtl8169_get_msglevel,
1053 .set_msglevel = rtl8169_set_msglevel,
1054 .get_rx_csum = rtl8169_get_rx_csum,
1055 .set_rx_csum = rtl8169_set_rx_csum,
1056 .get_tx_csum = ethtool_op_get_tx_csum,
1057 .set_tx_csum = ethtool_op_set_tx_csum,
1058 .get_sg = ethtool_op_get_sg,
1059 .set_sg = ethtool_op_set_sg,
1060 .get_tso = ethtool_op_get_tso,
1061 .set_tso = ethtool_op_set_tso,
1062 .get_regs = rtl8169_get_regs,
1063 .get_wol = rtl8169_get_wol,
1064 .set_wol = rtl8169_set_wol,
1065 .get_strings = rtl8169_get_strings,
1066 .get_stats_count = rtl8169_get_stats_count,
1067 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1068 .get_perm_addr = ethtool_op_get_perm_addr,
1071 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1072 int bitnum, int bitval)
1076 val = mdio_read(ioaddr, reg);
1077 val = (bitval == 1) ?
1078 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1079 mdio_write(ioaddr, reg, val & 0xffff);
1082 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1083 void __iomem *ioaddr)
1086 * The driver currently handles the 8168Bf and the 8168Be identically
1087 * but they can be identified more specifically through the test below
1090 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1092 * Same thing for the 8101Eb and the 8101Ec:
1094 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1100 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1101 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1102 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1103 { 0x30800000, RTL_GIGA_MAC_VER_14 },
1104 { 0x30000000, RTL_GIGA_MAC_VER_11 },
1105 { 0x98000000, RTL_GIGA_MAC_VER_06 },
1106 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1107 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1108 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1109 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1110 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1114 reg = RTL_R32(TxConfig) & 0xfc800000;
1115 while ((reg & p->mask) != p->mask)
1117 tp->mac_version = p->mac_version;
1120 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1122 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1125 static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1126 void __iomem *ioaddr)
1133 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1134 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1135 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1136 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1140 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1141 while ((reg & p->mask) != p->set)
1143 tp->phy_version = p->phy_version;
1146 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1153 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1154 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1155 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1156 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1160 for (p = phy_print; p->msg; p++) {
1161 if (tp->phy_version == p->version) {
1162 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1166 dprintk("phy_version == Unknown\n");
1169 static void rtl8169_hw_phy_config(struct net_device *dev)
1171 struct rtl8169_private *tp = netdev_priv(dev);
1172 void __iomem *ioaddr = tp->mmio_addr;
1174 u16 regs[5]; /* Beware of bit-sign propagation */
1175 } phy_magic[5] = { {
1176 { 0x0000, //w 4 15 12 0
1177 0x00a1, //w 3 15 0 00a1
1178 0x0008, //w 2 15 0 0008
1179 0x1020, //w 1 15 0 1020
1180 0x1000 } },{ //w 0 15 0 1000
1181 { 0x7000, //w 4 15 12 7
1182 0xff41, //w 3 15 0 ff41
1183 0xde60, //w 2 15 0 de60
1184 0x0140, //w 1 15 0 0140
1185 0x0077 } },{ //w 0 15 0 0077
1186 { 0xa000, //w 4 15 12 a
1187 0xdf01, //w 3 15 0 df01
1188 0xdf20, //w 2 15 0 df20
1189 0xff95, //w 1 15 0 ff95
1190 0xfa00 } },{ //w 0 15 0 fa00
1191 { 0xb000, //w 4 15 12 b
1192 0xff41, //w 3 15 0 ff41
1193 0xde20, //w 2 15 0 de20
1194 0x0140, //w 1 15 0 0140
1195 0x00bb } },{ //w 0 15 0 00bb
1196 { 0xf000, //w 4 15 12 f
1197 0xdf01, //w 3 15 0 df01
1198 0xdf20, //w 2 15 0 df20
1199 0xff95, //w 1 15 0 ff95
1200 0xbf00 } //w 0 15 0 bf00
1205 rtl8169_print_mac_version(tp);
1206 rtl8169_print_phy_version(tp);
1208 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1210 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1213 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1214 dprintk("Do final_reg2.cfg\n");
1218 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1219 mdio_write(ioaddr, 31, 0x0002);
1220 mdio_write(ioaddr, 1, 0x90d0);
1221 mdio_write(ioaddr, 31, 0x0000);
1225 /* phy config for RTL8169s mac_version C chip */
1226 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1227 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1228 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1229 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1231 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1234 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1235 mdio_write(ioaddr, pos, val);
1237 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1238 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1239 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1241 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1244 static void rtl8169_phy_timer(unsigned long __opaque)
1246 struct net_device *dev = (struct net_device *)__opaque;
1247 struct rtl8169_private *tp = netdev_priv(dev);
1248 struct timer_list *timer = &tp->timer;
1249 void __iomem *ioaddr = tp->mmio_addr;
1250 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1252 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1253 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1255 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1258 spin_lock_irq(&tp->lock);
1260 if (tp->phy_reset_pending(ioaddr)) {
1262 * A busy loop could burn quite a few cycles on nowadays CPU.
1263 * Let's delay the execution of the timer for a few ticks.
1269 if (tp->link_ok(ioaddr))
1272 if (netif_msg_link(tp))
1273 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1275 tp->phy_reset_enable(ioaddr);
1278 mod_timer(timer, jiffies + timeout);
1280 spin_unlock_irq(&tp->lock);
1283 static inline void rtl8169_delete_timer(struct net_device *dev)
1285 struct rtl8169_private *tp = netdev_priv(dev);
1286 struct timer_list *timer = &tp->timer;
1288 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1289 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1292 del_timer_sync(timer);
1295 static inline void rtl8169_request_timer(struct net_device *dev)
1297 struct rtl8169_private *tp = netdev_priv(dev);
1298 struct timer_list *timer = &tp->timer;
1300 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1301 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1304 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1307 #ifdef CONFIG_NET_POLL_CONTROLLER
1309 * Polling 'interrupt' - used by things like netconsole to send skbs
1310 * without having to re-enable interrupts. It's not called while
1311 * the interrupt routine is executing.
1313 static void rtl8169_netpoll(struct net_device *dev)
1315 struct rtl8169_private *tp = netdev_priv(dev);
1316 struct pci_dev *pdev = tp->pci_dev;
1318 disable_irq(pdev->irq);
1319 rtl8169_interrupt(pdev->irq, dev);
1320 enable_irq(pdev->irq);
1324 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1325 void __iomem *ioaddr)
1328 pci_release_regions(pdev);
1329 pci_disable_device(pdev);
1333 static void rtl8169_phy_reset(struct net_device *dev,
1334 struct rtl8169_private *tp)
1336 void __iomem *ioaddr = tp->mmio_addr;
1339 tp->phy_reset_enable(ioaddr);
1340 for (i = 0; i < 100; i++) {
1341 if (!tp->phy_reset_pending(ioaddr))
1345 if (netif_msg_link(tp))
1346 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1349 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1351 void __iomem *ioaddr = tp->mmio_addr;
1353 rtl8169_hw_phy_config(dev);
1355 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1358 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1360 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1361 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1363 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1364 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1366 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1367 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1370 rtl8169_phy_reset(dev, tp);
1373 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1374 * only 8101. Don't panic.
1376 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1378 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1379 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1382 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1384 struct rtl8169_private *tp = netdev_priv(dev);
1385 struct mii_ioctl_data *data = if_mii(ifr);
1387 if (!netif_running(dev))
1392 data->phy_id = 32; /* Internal PHY */
1396 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1400 if (!capable(CAP_NET_ADMIN))
1402 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1408 static const struct rtl_cfg_info {
1409 void (*hw_start)(struct net_device *);
1410 unsigned int region;
1414 } rtl_cfg_infos [] = {
1416 .hw_start = rtl_hw_start_8169,
1419 .intr_event = SYSErr | LinkChg | RxOverflow |
1420 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1421 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1424 .hw_start = rtl_hw_start_8168,
1427 .intr_event = SYSErr | LinkChg | RxOverflow |
1428 TxErr | TxOK | RxOK | RxErr,
1429 .napi_event = TxErr | TxOK | RxOK | RxOverflow
1432 .hw_start = rtl_hw_start_8101,
1435 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1436 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1437 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1441 static int __devinit
1442 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1444 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1445 const unsigned int region = cfg->region;
1446 struct rtl8169_private *tp;
1447 struct net_device *dev;
1448 void __iomem *ioaddr;
1452 if (netif_msg_drv(&debug)) {
1453 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1454 MODULENAME, RTL8169_VERSION);
1457 dev = alloc_etherdev(sizeof (*tp));
1459 if (netif_msg_drv(&debug))
1460 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1465 SET_MODULE_OWNER(dev);
1466 SET_NETDEV_DEV(dev, &pdev->dev);
1467 tp = netdev_priv(dev);
1469 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1471 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1472 rc = pci_enable_device(pdev);
1474 if (netif_msg_probe(tp))
1475 dev_err(&pdev->dev, "enable failure\n");
1476 goto err_out_free_dev_1;
1479 rc = pci_set_mwi(pdev);
1481 goto err_out_disable_2;
1483 /* make sure PCI base addr 1 is MMIO */
1484 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1485 if (netif_msg_probe(tp)) {
1487 "region #%d not an MMIO resource, aborting\n",
1494 /* check for weird/broken PCI region reporting */
1495 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1496 if (netif_msg_probe(tp)) {
1498 "Invalid PCI region size(s), aborting\n");
1504 rc = pci_request_regions(pdev, MODULENAME);
1506 if (netif_msg_probe(tp))
1507 dev_err(&pdev->dev, "could not request regions.\n");
1511 tp->cp_cmd = PCIMulRW | RxChkSum;
1513 if ((sizeof(dma_addr_t) > 4) &&
1514 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1515 tp->cp_cmd |= PCIDAC;
1516 dev->features |= NETIF_F_HIGHDMA;
1518 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1520 if (netif_msg_probe(tp)) {
1522 "DMA configuration failed.\n");
1524 goto err_out_free_res_4;
1528 pci_set_master(pdev);
1530 /* ioremap MMIO region */
1531 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1533 if (netif_msg_probe(tp))
1534 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1536 goto err_out_free_res_4;
1539 /* Unneeded ? Don't mess with Mrs. Murphy. */
1540 rtl8169_irq_mask_and_ack(ioaddr);
1542 /* Soft reset the chip. */
1543 RTL_W8(ChipCmd, CmdReset);
1545 /* Check that the chip has finished the reset. */
1546 for (i = 0; i < 100; i++) {
1547 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1549 msleep_interruptible(1);
1552 /* Identify chip attached to board */
1553 rtl8169_get_mac_version(tp, ioaddr);
1554 rtl8169_get_phy_version(tp, ioaddr);
1556 rtl8169_print_mac_version(tp);
1557 rtl8169_print_phy_version(tp);
1559 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1560 if (tp->mac_version == rtl_chip_info[i].mac_version)
1564 /* Unknown chip: assume array element #0, original RTL-8169 */
1565 if (netif_msg_probe(tp)) {
1566 dev_printk(KERN_DEBUG, &pdev->dev,
1567 "unknown chip version, assuming %s\n",
1568 rtl_chip_info[0].name);
1574 RTL_W8(Cfg9346, Cfg9346_Unlock);
1575 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1576 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1577 RTL_W8(Cfg9346, Cfg9346_Lock);
1579 if (RTL_R8(PHYstatus) & TBI_Enable) {
1580 tp->set_speed = rtl8169_set_speed_tbi;
1581 tp->get_settings = rtl8169_gset_tbi;
1582 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1583 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1584 tp->link_ok = rtl8169_tbi_link_ok;
1586 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1588 tp->set_speed = rtl8169_set_speed_xmii;
1589 tp->get_settings = rtl8169_gset_xmii;
1590 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1591 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1592 tp->link_ok = rtl8169_xmii_link_ok;
1594 dev->do_ioctl = rtl8169_ioctl;
1597 /* Get MAC address. FIXME: read EEPROM */
1598 for (i = 0; i < MAC_ADDR_LEN; i++)
1599 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1600 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1602 dev->open = rtl8169_open;
1603 dev->hard_start_xmit = rtl8169_start_xmit;
1604 dev->get_stats = rtl8169_get_stats;
1605 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1606 dev->stop = rtl8169_close;
1607 dev->tx_timeout = rtl8169_tx_timeout;
1608 dev->set_multicast_list = rtl_set_rx_mode;
1609 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1610 dev->irq = pdev->irq;
1611 dev->base_addr = (unsigned long) ioaddr;
1612 dev->change_mtu = rtl8169_change_mtu;
1614 #ifdef CONFIG_R8169_NAPI
1615 dev->poll = rtl8169_poll;
1616 dev->weight = R8169_NAPI_WEIGHT;
1619 #ifdef CONFIG_R8169_VLAN
1620 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1621 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1624 #ifdef CONFIG_NET_POLL_CONTROLLER
1625 dev->poll_controller = rtl8169_netpoll;
1628 tp->intr_mask = 0xffff;
1630 tp->mmio_addr = ioaddr;
1631 tp->align = cfg->align;
1632 tp->hw_start = cfg->hw_start;
1633 tp->intr_event = cfg->intr_event;
1634 tp->napi_event = cfg->napi_event;
1636 init_timer(&tp->timer);
1637 tp->timer.data = (unsigned long) dev;
1638 tp->timer.function = rtl8169_phy_timer;
1640 spin_lock_init(&tp->lock);
1642 rc = register_netdev(dev);
1644 goto err_out_unmap_5;
1646 pci_set_drvdata(pdev, dev);
1648 if (netif_msg_probe(tp)) {
1649 printk(KERN_INFO "%s: %s at 0x%lx, "
1650 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1653 rtl_chip_info[tp->chipset].name,
1655 dev->dev_addr[0], dev->dev_addr[1],
1656 dev->dev_addr[2], dev->dev_addr[3],
1657 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1660 rtl8169_init_phy(dev, tp);
1668 pci_release_regions(pdev);
1670 pci_clear_mwi(pdev);
1672 pci_disable_device(pdev);
1678 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1680 struct net_device *dev = pci_get_drvdata(pdev);
1681 struct rtl8169_private *tp = netdev_priv(dev);
1683 flush_scheduled_work();
1685 unregister_netdev(dev);
1686 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1687 pci_set_drvdata(pdev, NULL);
1690 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1691 struct net_device *dev)
1693 unsigned int mtu = dev->mtu;
1695 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1698 static int rtl8169_open(struct net_device *dev)
1700 struct rtl8169_private *tp = netdev_priv(dev);
1701 struct pci_dev *pdev = tp->pci_dev;
1702 int retval = -ENOMEM;
1705 rtl8169_set_rxbufsize(tp, dev);
1708 * Rx and Tx desscriptors needs 256 bytes alignment.
1709 * pci_alloc_consistent provides more.
1711 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1713 if (!tp->TxDescArray)
1716 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1718 if (!tp->RxDescArray)
1721 retval = rtl8169_init_ring(dev);
1725 INIT_DELAYED_WORK(&tp->task, NULL);
1729 retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1732 goto err_release_ring_2;
1736 rtl8169_request_timer(dev);
1738 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1743 rtl8169_rx_clear(tp);
1745 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1748 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1753 static void rtl8169_hw_reset(void __iomem *ioaddr)
1755 /* Disable interrupts */
1756 rtl8169_irq_mask_and_ack(ioaddr);
1758 /* Reset the chipset */
1759 RTL_W8(ChipCmd, CmdReset);
1765 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1767 void __iomem *ioaddr = tp->mmio_addr;
1768 u32 cfg = rtl8169_rx_config;
1770 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1771 RTL_W32(RxConfig, cfg);
1773 /* Set DMA burst size and Interframe Gap Time */
1774 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1775 (InterFrameGap << TxInterFrameGapShift));
1778 static void rtl_hw_start(struct net_device *dev)
1780 struct rtl8169_private *tp = netdev_priv(dev);
1781 void __iomem *ioaddr = tp->mmio_addr;
1784 /* Soft reset the chip. */
1785 RTL_W8(ChipCmd, CmdReset);
1787 /* Check that the chip has finished the reset. */
1788 for (i = 0; i < 100; i++) {
1789 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1791 msleep_interruptible(1);
1796 netif_start_queue(dev);
1800 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1801 void __iomem *ioaddr)
1804 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1805 * register to be written before TxDescAddrLow to work.
1806 * Switching from MMIO to I/O access fixes the issue as well.
1808 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1809 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1810 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1811 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1814 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1818 cmd = RTL_R16(CPlusCmd);
1819 RTL_W16(CPlusCmd, cmd);
1823 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1825 /* Low hurts. Let's disable the filtering. */
1826 RTL_W16(RxMaxSize, 16383);
1829 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1836 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1837 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1838 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1839 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1844 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1845 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1846 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1847 RTL_W32(0x7c, p->val);
1853 static void rtl_hw_start_8169(struct net_device *dev)
1855 struct rtl8169_private *tp = netdev_priv(dev);
1856 void __iomem *ioaddr = tp->mmio_addr;
1857 struct pci_dev *pdev = tp->pci_dev;
1859 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1860 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1861 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1864 RTL_W8(Cfg9346, Cfg9346_Unlock);
1865 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1866 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1867 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1868 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1869 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1871 RTL_W8(EarlyTxThres, EarlyTxThld);
1873 rtl_set_rx_max_size(ioaddr);
1875 rtl_set_rx_tx_config_registers(tp);
1877 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1879 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1880 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1881 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1882 "Bit-3 and bit-14 MUST be 1\n");
1883 tp->cp_cmd |= (1 << 14);
1886 RTL_W16(CPlusCmd, tp->cp_cmd);
1888 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1891 * Undocumented corner. Supposedly:
1892 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1894 RTL_W16(IntrMitigate, 0x0000);
1896 rtl_set_rx_tx_desc_registers(tp, ioaddr);
1898 RTL_W8(Cfg9346, Cfg9346_Lock);
1900 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1903 RTL_W32(RxMissed, 0);
1905 rtl_set_rx_mode(dev);
1907 /* no early-rx interrupts */
1908 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1910 /* Enable all known interrupts by setting the interrupt mask. */
1911 RTL_W16(IntrMask, tp->intr_event);
1913 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1916 static void rtl_hw_start_8168(struct net_device *dev)
1918 struct rtl8169_private *tp = netdev_priv(dev);
1919 void __iomem *ioaddr = tp->mmio_addr;
1920 struct pci_dev *pdev = tp->pci_dev;
1923 RTL_W8(Cfg9346, Cfg9346_Unlock);
1925 RTL_W8(EarlyTxThres, EarlyTxThld);
1927 rtl_set_rx_max_size(ioaddr);
1929 rtl_set_rx_tx_config_registers(tp);
1931 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
1933 RTL_W16(CPlusCmd, tp->cp_cmd);
1935 /* Tx performance tweak. */
1936 pci_read_config_byte(pdev, 0x69, &ctl);
1937 ctl = (ctl & ~0x70) | 0x50;
1938 pci_write_config_byte(pdev, 0x69, ctl);
1940 RTL_W16(IntrMitigate, 0x5151);
1942 /* Work around for RxFIFO overflow. */
1943 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
1944 tp->intr_event |= RxFIFOOver | PCSTimeout;
1945 tp->intr_event &= ~RxOverflow;
1948 rtl_set_rx_tx_desc_registers(tp, ioaddr);
1950 RTL_W8(Cfg9346, Cfg9346_Lock);
1954 RTL_W32(RxMissed, 0);
1956 rtl_set_rx_mode(dev);
1958 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1960 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1962 RTL_W16(IntrMask, tp->intr_event);
1965 static void rtl_hw_start_8101(struct net_device *dev)
1967 struct rtl8169_private *tp = netdev_priv(dev);
1968 void __iomem *ioaddr = tp->mmio_addr;
1969 struct pci_dev *pdev = tp->pci_dev;
1971 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
1972 pci_write_config_word(pdev, 0x68, 0x00);
1973 pci_write_config_word(pdev, 0x69, 0x08);
1976 RTL_W8(Cfg9346, Cfg9346_Unlock);
1978 RTL_W8(EarlyTxThres, EarlyTxThld);
1980 rtl_set_rx_max_size(ioaddr);
1982 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1984 RTL_W16(CPlusCmd, tp->cp_cmd);
1986 RTL_W16(IntrMitigate, 0x0000);
1988 rtl_set_rx_tx_desc_registers(tp, ioaddr);
1990 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1991 rtl_set_rx_tx_config_registers(tp);
1993 RTL_W8(Cfg9346, Cfg9346_Lock);
1997 RTL_W32(RxMissed, 0);
1999 rtl_set_rx_mode(dev);
2001 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2003 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2005 RTL_W16(IntrMask, tp->intr_event);
2008 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2010 struct rtl8169_private *tp = netdev_priv(dev);
2013 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2018 if (!netif_running(dev))
2023 rtl8169_set_rxbufsize(tp, dev);
2025 ret = rtl8169_init_ring(dev);
2029 netif_poll_enable(dev);
2033 rtl8169_request_timer(dev);
2039 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2041 desc->addr = 0x0badbadbadbadbadull;
2042 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2045 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2046 struct sk_buff **sk_buff, struct RxDesc *desc)
2048 struct pci_dev *pdev = tp->pci_dev;
2050 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2051 PCI_DMA_FROMDEVICE);
2052 dev_kfree_skb(*sk_buff);
2054 rtl8169_make_unusable_by_asic(desc);
2057 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2059 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2061 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2064 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2067 desc->addr = cpu_to_le64(mapping);
2069 rtl8169_mark_to_asic(desc, rx_buf_sz);
2072 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2073 struct net_device *dev,
2074 struct RxDesc *desc, int rx_buf_sz,
2077 struct sk_buff *skb;
2080 skb = netdev_alloc_skb(dev, rx_buf_sz + align);
2084 skb_reserve(skb, (align - 1) & (unsigned long)skb->data);
2086 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2087 PCI_DMA_FROMDEVICE);
2089 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2094 rtl8169_make_unusable_by_asic(desc);
2098 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2102 for (i = 0; i < NUM_RX_DESC; i++) {
2103 if (tp->Rx_skbuff[i]) {
2104 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2105 tp->RxDescArray + i);
2110 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2115 for (cur = start; end - cur != 0; cur++) {
2116 struct sk_buff *skb;
2117 unsigned int i = cur % NUM_RX_DESC;
2119 WARN_ON((s32)(end - cur) < 0);
2121 if (tp->Rx_skbuff[i])
2124 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2125 tp->RxDescArray + i,
2126 tp->rx_buf_sz, tp->align);
2130 tp->Rx_skbuff[i] = skb;
2135 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2137 desc->opts1 |= cpu_to_le32(RingEnd);
2140 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2142 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2145 static int rtl8169_init_ring(struct net_device *dev)
2147 struct rtl8169_private *tp = netdev_priv(dev);
2149 rtl8169_init_ring_indexes(tp);
2151 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2152 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2154 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2157 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2162 rtl8169_rx_clear(tp);
2166 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2167 struct TxDesc *desc)
2169 unsigned int len = tx_skb->len;
2171 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2178 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2182 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2183 unsigned int entry = i % NUM_TX_DESC;
2184 struct ring_info *tx_skb = tp->tx_skb + entry;
2185 unsigned int len = tx_skb->len;
2188 struct sk_buff *skb = tx_skb->skb;
2190 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2191 tp->TxDescArray + entry);
2196 tp->stats.tx_dropped++;
2199 tp->cur_tx = tp->dirty_tx = 0;
2202 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2204 struct rtl8169_private *tp = netdev_priv(dev);
2206 PREPARE_DELAYED_WORK(&tp->task, task);
2207 schedule_delayed_work(&tp->task, 4);
2210 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2212 struct rtl8169_private *tp = netdev_priv(dev);
2213 void __iomem *ioaddr = tp->mmio_addr;
2215 synchronize_irq(dev->irq);
2217 /* Wait for any pending NAPI task to complete */
2218 netif_poll_disable(dev);
2220 rtl8169_irq_mask_and_ack(ioaddr);
2222 netif_poll_enable(dev);
2225 static void rtl8169_reinit_task(struct work_struct *work)
2227 struct rtl8169_private *tp =
2228 container_of(work, struct rtl8169_private, task.work);
2229 struct net_device *dev = tp->dev;
2234 if (!netif_running(dev))
2237 rtl8169_wait_for_quiescence(dev);
2240 ret = rtl8169_open(dev);
2241 if (unlikely(ret < 0)) {
2242 if (net_ratelimit() && netif_msg_drv(tp)) {
2243 printk(PFX KERN_ERR "%s: reinit failure (status = %d)."
2244 " Rescheduling.\n", dev->name, ret);
2246 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2253 static void rtl8169_reset_task(struct work_struct *work)
2255 struct rtl8169_private *tp =
2256 container_of(work, struct rtl8169_private, task.work);
2257 struct net_device *dev = tp->dev;
2261 if (!netif_running(dev))
2264 rtl8169_wait_for_quiescence(dev);
2266 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2267 rtl8169_tx_clear(tp);
2269 if (tp->dirty_rx == tp->cur_rx) {
2270 rtl8169_init_ring_indexes(tp);
2272 netif_wake_queue(dev);
2274 if (net_ratelimit() && netif_msg_intr(tp)) {
2275 printk(PFX KERN_EMERG "%s: Rx buffers shortage\n",
2278 rtl8169_schedule_work(dev, rtl8169_reset_task);
2285 static void rtl8169_tx_timeout(struct net_device *dev)
2287 struct rtl8169_private *tp = netdev_priv(dev);
2289 rtl8169_hw_reset(tp->mmio_addr);
2291 /* Let's wait a bit while any (async) irq lands on */
2292 rtl8169_schedule_work(dev, rtl8169_reset_task);
2295 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2298 struct skb_shared_info *info = skb_shinfo(skb);
2299 unsigned int cur_frag, entry;
2303 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2304 skb_frag_t *frag = info->frags + cur_frag;
2309 entry = (entry + 1) % NUM_TX_DESC;
2311 txd = tp->TxDescArray + entry;
2313 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2314 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2316 /* anti gcc 2.95.3 bugware (sic) */
2317 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2319 txd->opts1 = cpu_to_le32(status);
2320 txd->addr = cpu_to_le64(mapping);
2322 tp->tx_skb[entry].len = len;
2326 tp->tx_skb[entry].skb = skb;
2327 txd->opts1 |= cpu_to_le32(LastFrag);
2333 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2335 if (dev->features & NETIF_F_TSO) {
2336 u32 mss = skb_shinfo(skb)->gso_size;
2339 return LargeSend | ((mss & MSSMask) << MSSShift);
2341 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2342 const struct iphdr *ip = ip_hdr(skb);
2344 if (ip->protocol == IPPROTO_TCP)
2345 return IPCS | TCPCS;
2346 else if (ip->protocol == IPPROTO_UDP)
2347 return IPCS | UDPCS;
2348 WARN_ON(1); /* we need a WARN() */
2353 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2355 struct rtl8169_private *tp = netdev_priv(dev);
2356 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2357 struct TxDesc *txd = tp->TxDescArray + entry;
2358 void __iomem *ioaddr = tp->mmio_addr;
2362 int ret = NETDEV_TX_OK;
2364 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2365 if (netif_msg_drv(tp)) {
2367 "%s: BUG! Tx Ring full when queue awake!\n",
2373 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2376 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2378 frags = rtl8169_xmit_frags(tp, skb, opts1);
2380 len = skb_headlen(skb);
2385 if (unlikely(len < ETH_ZLEN)) {
2386 if (skb_padto(skb, ETH_ZLEN))
2387 goto err_update_stats;
2391 opts1 |= FirstFrag | LastFrag;
2392 tp->tx_skb[entry].skb = skb;
2395 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2397 tp->tx_skb[entry].len = len;
2398 txd->addr = cpu_to_le64(mapping);
2399 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2403 /* anti gcc 2.95.3 bugware (sic) */
2404 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2405 txd->opts1 = cpu_to_le32(status);
2407 dev->trans_start = jiffies;
2409 tp->cur_tx += frags + 1;
2413 RTL_W8(TxPoll, NPQ); /* set polling bit */
2415 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2416 netif_stop_queue(dev);
2418 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2419 netif_wake_queue(dev);
2426 netif_stop_queue(dev);
2427 ret = NETDEV_TX_BUSY;
2429 tp->stats.tx_dropped++;
2433 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2435 struct rtl8169_private *tp = netdev_priv(dev);
2436 struct pci_dev *pdev = tp->pci_dev;
2437 void __iomem *ioaddr = tp->mmio_addr;
2438 u16 pci_status, pci_cmd;
2440 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2441 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2443 if (netif_msg_intr(tp)) {
2445 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2446 dev->name, pci_cmd, pci_status);
2450 * The recovery sequence below admits a very elaborated explanation:
2451 * - it seems to work;
2452 * - I did not see what else could be done;
2453 * - it makes iop3xx happy.
2455 * Feel free to adjust to your needs.
2457 if (pdev->broken_parity_status)
2458 pci_cmd &= ~PCI_COMMAND_PARITY;
2460 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2462 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2464 pci_write_config_word(pdev, PCI_STATUS,
2465 pci_status & (PCI_STATUS_DETECTED_PARITY |
2466 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2467 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2469 /* The infamous DAC f*ckup only happens at boot time */
2470 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2471 if (netif_msg_intr(tp))
2472 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2473 tp->cp_cmd &= ~PCIDAC;
2474 RTL_W16(CPlusCmd, tp->cp_cmd);
2475 dev->features &= ~NETIF_F_HIGHDMA;
2478 rtl8169_hw_reset(ioaddr);
2480 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2483 static void rtl8169_tx_interrupt(struct net_device *dev,
2484 struct rtl8169_private *tp,
2485 void __iomem *ioaddr)
2487 unsigned int dirty_tx, tx_left;
2489 dirty_tx = tp->dirty_tx;
2491 tx_left = tp->cur_tx - dirty_tx;
2493 while (tx_left > 0) {
2494 unsigned int entry = dirty_tx % NUM_TX_DESC;
2495 struct ring_info *tx_skb = tp->tx_skb + entry;
2496 u32 len = tx_skb->len;
2500 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2501 if (status & DescOwn)
2504 tp->stats.tx_bytes += len;
2505 tp->stats.tx_packets++;
2507 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2509 if (status & LastFrag) {
2510 dev_kfree_skb_irq(tx_skb->skb);
2517 if (tp->dirty_tx != dirty_tx) {
2518 tp->dirty_tx = dirty_tx;
2520 if (netif_queue_stopped(dev) &&
2521 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2522 netif_wake_queue(dev);
2527 static inline int rtl8169_fragmented_frame(u32 status)
2529 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2532 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2534 u32 opts1 = le32_to_cpu(desc->opts1);
2535 u32 status = opts1 & RxProtoMask;
2537 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2538 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2539 ((status == RxProtoIP) && !(opts1 & IPFail)))
2540 skb->ip_summed = CHECKSUM_UNNECESSARY;
2542 skb->ip_summed = CHECKSUM_NONE;
2545 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2546 struct rtl8169_private *tp, int pkt_size,
2549 struct sk_buff *skb;
2552 if (pkt_size >= rx_copybreak)
2555 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2559 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2560 PCI_DMA_FROMDEVICE);
2561 skb_reserve(skb, NET_IP_ALIGN);
2562 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2569 static int rtl8169_rx_interrupt(struct net_device *dev,
2570 struct rtl8169_private *tp,
2571 void __iomem *ioaddr)
2573 unsigned int cur_rx, rx_left;
2574 unsigned int delta, count;
2576 cur_rx = tp->cur_rx;
2577 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2578 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2580 for (; rx_left > 0; rx_left--, cur_rx++) {
2581 unsigned int entry = cur_rx % NUM_RX_DESC;
2582 struct RxDesc *desc = tp->RxDescArray + entry;
2586 status = le32_to_cpu(desc->opts1);
2588 if (status & DescOwn)
2590 if (unlikely(status & RxRES)) {
2591 if (netif_msg_rx_err(tp)) {
2593 "%s: Rx ERROR. status = %08x\n",
2596 tp->stats.rx_errors++;
2597 if (status & (RxRWT | RxRUNT))
2598 tp->stats.rx_length_errors++;
2600 tp->stats.rx_crc_errors++;
2601 if (status & RxFOVF) {
2602 rtl8169_schedule_work(dev, rtl8169_reset_task);
2603 tp->stats.rx_fifo_errors++;
2605 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2607 struct sk_buff *skb = tp->Rx_skbuff[entry];
2608 dma_addr_t addr = le64_to_cpu(desc->addr);
2609 int pkt_size = (status & 0x00001FFF) - 4;
2610 struct pci_dev *pdev = tp->pci_dev;
2613 * The driver does not support incoming fragmented
2614 * frames. They are seen as a symptom of over-mtu
2617 if (unlikely(rtl8169_fragmented_frame(status))) {
2618 tp->stats.rx_dropped++;
2619 tp->stats.rx_length_errors++;
2620 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2624 rtl8169_rx_csum(skb, desc);
2626 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2627 pci_dma_sync_single_for_device(pdev, addr,
2628 pkt_size, PCI_DMA_FROMDEVICE);
2629 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2631 pci_unmap_single(pdev, addr, pkt_size,
2632 PCI_DMA_FROMDEVICE);
2633 tp->Rx_skbuff[entry] = NULL;
2636 skb_put(skb, pkt_size);
2637 skb->protocol = eth_type_trans(skb, dev);
2639 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2640 rtl8169_rx_skb(skb);
2642 dev->last_rx = jiffies;
2643 tp->stats.rx_bytes += pkt_size;
2644 tp->stats.rx_packets++;
2647 /* Work around for AMD plateform. */
2648 if ((desc->opts2 & 0xfffe000) &&
2649 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2655 count = cur_rx - tp->cur_rx;
2656 tp->cur_rx = cur_rx;
2658 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2659 if (!delta && count && netif_msg_intr(tp))
2660 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2661 tp->dirty_rx += delta;
2664 * FIXME: until there is periodic timer to try and refill the ring,
2665 * a temporary shortage may definitely kill the Rx process.
2666 * - disable the asic to try and avoid an overflow and kick it again
2668 * - how do others driver handle this condition (Uh oh...).
2670 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2671 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2676 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2678 struct net_device *dev = dev_instance;
2679 struct rtl8169_private *tp = netdev_priv(dev);
2680 int boguscnt = max_interrupt_work;
2681 void __iomem *ioaddr = tp->mmio_addr;
2686 status = RTL_R16(IntrStatus);
2688 /* hotplug/major error/no more work/shared irq */
2689 if ((status == 0xFFFF) || !status)
2694 if (unlikely(!netif_running(dev))) {
2695 rtl8169_asic_down(ioaddr);
2699 status &= tp->intr_mask;
2701 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2703 if (!(status & tp->intr_event))
2706 /* Work around for rx fifo overflow */
2707 if (unlikely(status & RxFIFOOver) &&
2708 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2709 netif_stop_queue(dev);
2710 rtl8169_tx_timeout(dev);
2714 if (unlikely(status & SYSErr)) {
2715 rtl8169_pcierr_interrupt(dev);
2719 if (status & LinkChg)
2720 rtl8169_check_link_status(dev, tp, ioaddr);
2722 #ifdef CONFIG_R8169_NAPI
2723 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2724 tp->intr_mask = ~tp->napi_event;
2726 if (likely(netif_rx_schedule_prep(dev)))
2727 __netif_rx_schedule(dev);
2728 else if (netif_msg_intr(tp)) {
2729 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2735 if (status & (RxOK | RxOverflow | RxFIFOOver))
2736 rtl8169_rx_interrupt(dev, tp, ioaddr);
2739 if (status & (TxOK | TxErr))
2740 rtl8169_tx_interrupt(dev, tp, ioaddr);
2744 } while (boguscnt > 0);
2746 if (boguscnt <= 0) {
2747 if (netif_msg_intr(tp) && net_ratelimit() ) {
2749 "%s: Too much work at interrupt!\n", dev->name);
2751 /* Clear all interrupt sources. */
2752 RTL_W16(IntrStatus, 0xffff);
2755 return IRQ_RETVAL(handled);
2758 #ifdef CONFIG_R8169_NAPI
2759 static int rtl8169_poll(struct net_device *dev, int *budget)
2761 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2762 struct rtl8169_private *tp = netdev_priv(dev);
2763 void __iomem *ioaddr = tp->mmio_addr;
2765 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2766 rtl8169_tx_interrupt(dev, tp, ioaddr);
2768 *budget -= work_done;
2769 dev->quota -= work_done;
2771 if (work_done < work_to_do) {
2772 netif_rx_complete(dev);
2773 tp->intr_mask = 0xffff;
2775 * 20040426: the barrier is not strictly required but the
2776 * behavior of the irq handler could be less predictable
2777 * without it. Btw, the lack of flush for the posted pci
2778 * write is safe - FR
2781 RTL_W16(IntrMask, tp->intr_event);
2784 return (work_done >= work_to_do);
2788 static void rtl8169_down(struct net_device *dev)
2790 struct rtl8169_private *tp = netdev_priv(dev);
2791 void __iomem *ioaddr = tp->mmio_addr;
2792 unsigned int poll_locked = 0;
2793 unsigned int intrmask;
2795 rtl8169_delete_timer(dev);
2797 netif_stop_queue(dev);
2800 spin_lock_irq(&tp->lock);
2802 rtl8169_asic_down(ioaddr);
2804 /* Update the error counts. */
2805 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2806 RTL_W32(RxMissed, 0);
2808 spin_unlock_irq(&tp->lock);
2810 synchronize_irq(dev->irq);
2813 netif_poll_disable(dev);
2817 /* Give a racing hard_start_xmit a few cycles to complete. */
2818 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
2821 * And now for the 50k$ question: are IRQ disabled or not ?
2823 * Two paths lead here:
2825 * -> netif_running() is available to sync the current code and the
2826 * IRQ handler. See rtl8169_interrupt for details.
2827 * 2) dev->change_mtu
2828 * -> rtl8169_poll can not be issued again and re-enable the
2829 * interruptions. Let's simply issue the IRQ down sequence again.
2831 * No loop if hotpluged or major error (0xffff).
2833 intrmask = RTL_R16(IntrMask);
2834 if (intrmask && (intrmask != 0xffff))
2837 rtl8169_tx_clear(tp);
2839 rtl8169_rx_clear(tp);
2842 static int rtl8169_close(struct net_device *dev)
2844 struct rtl8169_private *tp = netdev_priv(dev);
2845 struct pci_dev *pdev = tp->pci_dev;
2849 free_irq(dev->irq, dev);
2851 netif_poll_enable(dev);
2853 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2855 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2857 tp->TxDescArray = NULL;
2858 tp->RxDescArray = NULL;
2863 static void rtl_set_rx_mode(struct net_device *dev)
2865 struct rtl8169_private *tp = netdev_priv(dev);
2866 void __iomem *ioaddr = tp->mmio_addr;
2867 unsigned long flags;
2868 u32 mc_filter[2]; /* Multicast hash filter */
2872 if (dev->flags & IFF_PROMISC) {
2873 /* Unconditionally log net taps. */
2874 if (netif_msg_link(tp)) {
2875 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2879 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2881 mc_filter[1] = mc_filter[0] = 0xffffffff;
2882 } else if ((dev->mc_count > multicast_filter_limit)
2883 || (dev->flags & IFF_ALLMULTI)) {
2884 /* Too many to filter perfectly -- accept all multicasts. */
2885 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2886 mc_filter[1] = mc_filter[0] = 0xffffffff;
2888 struct dev_mc_list *mclist;
2891 rx_mode = AcceptBroadcast | AcceptMyPhys;
2892 mc_filter[1] = mc_filter[0] = 0;
2893 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2894 i++, mclist = mclist->next) {
2895 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2896 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2897 rx_mode |= AcceptMulticast;
2901 spin_lock_irqsave(&tp->lock, flags);
2903 tmp = rtl8169_rx_config | rx_mode |
2904 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2906 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2907 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2908 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2909 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2910 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2911 mc_filter[0] = 0xffffffff;
2912 mc_filter[1] = 0xffffffff;
2915 RTL_W32(RxConfig, tmp);
2916 RTL_W32(MAR0 + 0, mc_filter[0]);
2917 RTL_W32(MAR0 + 4, mc_filter[1]);
2919 spin_unlock_irqrestore(&tp->lock, flags);
2923 * rtl8169_get_stats - Get rtl8169 read/write statistics
2924 * @dev: The Ethernet Device to get statistics for
2926 * Get TX/RX statistics for rtl8169
2928 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2930 struct rtl8169_private *tp = netdev_priv(dev);
2931 void __iomem *ioaddr = tp->mmio_addr;
2932 unsigned long flags;
2934 if (netif_running(dev)) {
2935 spin_lock_irqsave(&tp->lock, flags);
2936 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2937 RTL_W32(RxMissed, 0);
2938 spin_unlock_irqrestore(&tp->lock, flags);
2946 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2948 struct net_device *dev = pci_get_drvdata(pdev);
2949 struct rtl8169_private *tp = netdev_priv(dev);
2950 void __iomem *ioaddr = tp->mmio_addr;
2952 if (!netif_running(dev))
2953 goto out_pci_suspend;
2955 netif_device_detach(dev);
2956 netif_stop_queue(dev);
2958 spin_lock_irq(&tp->lock);
2960 rtl8169_asic_down(ioaddr);
2962 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2963 RTL_W32(RxMissed, 0);
2965 spin_unlock_irq(&tp->lock);
2968 pci_save_state(pdev);
2969 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
2970 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2975 static int rtl8169_resume(struct pci_dev *pdev)
2977 struct net_device *dev = pci_get_drvdata(pdev);
2979 pci_set_power_state(pdev, PCI_D0);
2980 pci_restore_state(pdev);
2981 pci_enable_wake(pdev, PCI_D0, 0);
2983 if (!netif_running(dev))
2986 netif_device_attach(dev);
2988 rtl8169_schedule_work(dev, rtl8169_reset_task);
2993 #endif /* CONFIG_PM */
2995 static struct pci_driver rtl8169_pci_driver = {
2997 .id_table = rtl8169_pci_tbl,
2998 .probe = rtl8169_init_one,
2999 .remove = __devexit_p(rtl8169_remove_one),
3001 .suspend = rtl8169_suspend,
3002 .resume = rtl8169_resume,
3006 static int __init rtl8169_init_module(void)
3008 return pci_register_driver(&rtl8169_pci_driver);
3011 static void __exit rtl8169_cleanup_module(void)
3013 pci_unregister_driver(&rtl8169_pci_driver);
3016 module_init(rtl8169_init_module);
3017 module_exit(rtl8169_cleanup_module);