2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #ifdef CONFIG_R8169_NAPI
32 #define NAPI_SUFFIX "-NAPI"
34 #define NAPI_SUFFIX ""
37 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
38 #define MODULENAME "r8169"
39 #define PFX MODULENAME ": "
42 #define assert(expr) \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
47 #define dprintk(fmt, args...) \
48 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
50 #define assert(expr) do {} while (0)
51 #define dprintk(fmt, args...) do {} while (0)
52 #endif /* RTL8169_DEBUG */
54 #define R8169_MSG_DEFAULT \
55 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
57 #define TX_BUFFS_AVAIL(tp) \
58 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
60 #ifdef CONFIG_R8169_NAPI
61 #define rtl8169_rx_skb netif_receive_skb
62 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
63 #define rtl8169_rx_quota(count, quota) min(count, quota)
65 #define rtl8169_rx_skb netif_rx
66 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
67 #define rtl8169_rx_quota(count, quota) count
70 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
71 static const int max_interrupt_work = 20;
73 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
74 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
75 static const int multicast_filter_limit = 32;
77 /* MAC address length */
78 #define MAC_ADDR_LEN 6
80 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
81 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
83 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
84 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
85 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
86 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
88 #define R8169_REGS_SIZE 256
89 #define R8169_NAPI_WEIGHT 64
90 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
91 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
92 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
93 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
94 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
96 #define RTL8169_TX_TIMEOUT (6*HZ)
97 #define RTL8169_PHY_TIMEOUT (10*HZ)
99 /* write/read MMIO register */
100 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
101 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
102 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
103 #define RTL_R8(reg) readb (ioaddr + (reg))
104 #define RTL_R16(reg) readw (ioaddr + (reg))
105 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
108 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
109 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
110 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
111 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
112 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
113 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
114 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
115 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
116 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
117 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
118 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
119 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
120 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
121 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
122 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
123 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
126 #define _R(NAME,MAC,MASK) \
127 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
129 static const struct {
132 u32 RxConfigMask; /* Clears the bits supported by this chip */
133 } rtl_chip_info[] = {
134 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
135 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
136 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
137 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
138 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
139 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
140 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
142 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
143 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
144 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
145 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
146 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
147 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
148 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
159 static void rtl_hw_start_8169(struct net_device *);
160 static void rtl_hw_start_8168(struct net_device *);
161 static void rtl_hw_start_8101(struct net_device *);
163 static struct pci_device_id rtl8169_pci_tbl[] = {
164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
167 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
168 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
169 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
170 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
171 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
172 { PCI_VENDOR_ID_LINKSYS, 0x1032,
173 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
177 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
179 static int rx_copybreak = 200;
186 MAC0 = 0, /* Ethernet hardware address. */
188 MAR0 = 8, /* Multicast filter. */
189 CounterAddrLow = 0x10,
190 CounterAddrHigh = 0x14,
191 TxDescStartAddrLow = 0x20,
192 TxDescStartAddrHigh = 0x24,
193 TxHDescStartAddrLow = 0x28,
194 TxHDescStartAddrHigh = 0x2c,
220 RxDescAddrLow = 0xe4,
221 RxDescAddrHigh = 0xe8,
224 FuncEventMask = 0xf4,
225 FuncPresetState = 0xf8,
226 FuncForceEvent = 0xfc,
229 enum rtl_register_content {
230 /* InterruptStatusBits */
234 TxDescUnavail = 0x0080,
256 /* TXPoll register p.5 */
257 HPQ = 0x80, /* Poll cmd on the high prio queue */
258 NPQ = 0x40, /* Poll cmd on the low prio queue */
259 FSWInt = 0x01, /* Forced software interrupt */
263 Cfg9346_Unlock = 0xc0,
268 AcceptBroadcast = 0x08,
269 AcceptMulticast = 0x04,
271 AcceptAllPhys = 0x01,
278 TxInterFrameGapShift = 24,
279 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
281 /* Config1 register p.24 */
282 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
283 PMEnable = (1 << 0), /* Power Management Enable */
285 /* Config2 register p. 25 */
286 PCI_Clock_66MHz = 0x01,
287 PCI_Clock_33MHz = 0x00,
289 /* Config3 register p.25 */
290 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
291 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
293 /* Config5 register p.27 */
294 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
295 MWF = (1 << 5), /* Accept Multicast wakeup frame */
296 UWF = (1 << 4), /* Accept Unicast wakeup frame */
297 LanWake = (1 << 1), /* LanWake enable/disable */
298 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
301 TBIReset = 0x80000000,
302 TBILoopback = 0x40000000,
303 TBINwEnable = 0x20000000,
304 TBINwRestart = 0x10000000,
305 TBILinkOk = 0x02000000,
306 TBINwComplete = 0x01000000,
309 PktCntrDisable = (1 << 7), // 8168
314 INTT_0 = 0x0000, // 8168
315 INTT_1 = 0x0001, // 8168
316 INTT_2 = 0x0002, // 8168
317 INTT_3 = 0x0003, // 8168
319 /* rtl8169_PHYstatus */
330 TBILinkOK = 0x02000000,
332 /* DumpCounterCommand */
336 enum desc_status_bit {
337 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
338 RingEnd = (1 << 30), /* End of descriptor ring */
339 FirstFrag = (1 << 29), /* First segment of a packet */
340 LastFrag = (1 << 28), /* Final segment of a packet */
343 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
344 MSSShift = 16, /* MSS value position */
345 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
346 IPCS = (1 << 18), /* Calculate IP checksum */
347 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
348 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
349 TxVlanTag = (1 << 17), /* Add VLAN tag */
352 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
353 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
355 #define RxProtoUDP (PID1)
356 #define RxProtoTCP (PID0)
357 #define RxProtoIP (PID1 | PID0)
358 #define RxProtoMask RxProtoIP
360 IPFail = (1 << 16), /* IP checksum failed */
361 UDPFail = (1 << 15), /* UDP/IP checksum failed */
362 TCPFail = (1 << 14), /* TCP/IP checksum failed */
363 RxVlanTag = (1 << 16), /* VLAN tag available */
366 #define RsvdMask 0x3fffc000
383 u8 __pad[sizeof(void *) - sizeof(u32)];
387 RTL_FEATURE_WOL = (1 << 0),
388 RTL_FEATURE_MSI = (1 << 1),
391 struct rtl8169_private {
392 void __iomem *mmio_addr; /* memory map physical address */
393 struct pci_dev *pci_dev; /* Index of PCI device */
394 struct net_device *dev;
395 struct napi_struct napi;
396 spinlock_t lock; /* spin lock flag */
400 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
401 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
404 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
405 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
406 dma_addr_t TxPhyAddr;
407 dma_addr_t RxPhyAddr;
408 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
409 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
412 struct timer_list timer;
417 int phy_auto_nego_reg;
418 int phy_1000_ctrl_reg;
419 #ifdef CONFIG_R8169_VLAN
420 struct vlan_group *vlgrp;
422 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
423 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
424 void (*phy_reset_enable)(void __iomem *);
425 void (*hw_start)(struct net_device *);
426 unsigned int (*phy_reset_pending)(void __iomem *);
427 unsigned int (*link_ok)(void __iomem *);
428 struct delayed_work task;
432 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
433 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
434 module_param(rx_copybreak, int, 0);
435 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
436 module_param(use_dac, int, 0);
437 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
438 module_param_named(debug, debug.msg_enable, int, 0);
439 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
440 MODULE_LICENSE("GPL");
441 MODULE_VERSION(RTL8169_VERSION);
443 static int rtl8169_open(struct net_device *dev);
444 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
445 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
446 static int rtl8169_init_ring(struct net_device *dev);
447 static void rtl_hw_start(struct net_device *dev);
448 static int rtl8169_close(struct net_device *dev);
449 static void rtl_set_rx_mode(struct net_device *dev);
450 static void rtl8169_tx_timeout(struct net_device *dev);
451 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
452 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
453 void __iomem *, u32 budget);
454 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
455 static void rtl8169_down(struct net_device *dev);
456 static void rtl8169_rx_clear(struct rtl8169_private *tp);
458 #ifdef CONFIG_R8169_NAPI
459 static int rtl8169_poll(struct napi_struct *napi, int budget);
462 static const unsigned int rtl8169_rx_config =
463 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
465 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
469 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
471 for (i = 20; i > 0; i--) {
473 * Check if the RTL8169 has completed writing to the specified
476 if (!(RTL_R32(PHYAR) & 0x80000000))
482 static int mdio_read(void __iomem *ioaddr, int reg_addr)
486 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
488 for (i = 20; i > 0; i--) {
490 * Check if the RTL8169 has completed retrieving data from
491 * the specified MII register.
493 if (RTL_R32(PHYAR) & 0x80000000) {
494 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
502 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
504 RTL_W16(IntrMask, 0x0000);
506 RTL_W16(IntrStatus, 0xffff);
509 static void rtl8169_asic_down(void __iomem *ioaddr)
511 RTL_W8(ChipCmd, 0x00);
512 rtl8169_irq_mask_and_ack(ioaddr);
516 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
518 return RTL_R32(TBICSR) & TBIReset;
521 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
523 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
526 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
528 return RTL_R32(TBICSR) & TBILinkOk;
531 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
533 return RTL_R8(PHYstatus) & LinkStatus;
536 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
538 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
541 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
545 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
546 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
549 static void rtl8169_check_link_status(struct net_device *dev,
550 struct rtl8169_private *tp,
551 void __iomem *ioaddr)
555 spin_lock_irqsave(&tp->lock, flags);
556 if (tp->link_ok(ioaddr)) {
557 netif_carrier_on(dev);
558 if (netif_msg_ifup(tp))
559 printk(KERN_INFO PFX "%s: link up\n", dev->name);
561 if (netif_msg_ifdown(tp))
562 printk(KERN_INFO PFX "%s: link down\n", dev->name);
563 netif_carrier_off(dev);
565 spin_unlock_irqrestore(&tp->lock, flags);
568 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
570 struct rtl8169_private *tp = netdev_priv(dev);
571 void __iomem *ioaddr = tp->mmio_addr;
576 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
577 wol->supported = WAKE_ANY;
579 spin_lock_irq(&tp->lock);
581 options = RTL_R8(Config1);
582 if (!(options & PMEnable))
585 options = RTL_R8(Config3);
586 if (options & LinkUp)
587 wol->wolopts |= WAKE_PHY;
588 if (options & MagicPacket)
589 wol->wolopts |= WAKE_MAGIC;
591 options = RTL_R8(Config5);
593 wol->wolopts |= WAKE_UCAST;
595 wol->wolopts |= WAKE_BCAST;
597 wol->wolopts |= WAKE_MCAST;
600 spin_unlock_irq(&tp->lock);
603 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
605 struct rtl8169_private *tp = netdev_priv(dev);
606 void __iomem *ioaddr = tp->mmio_addr;
613 { WAKE_ANY, Config1, PMEnable },
614 { WAKE_PHY, Config3, LinkUp },
615 { WAKE_MAGIC, Config3, MagicPacket },
616 { WAKE_UCAST, Config5, UWF },
617 { WAKE_BCAST, Config5, BWF },
618 { WAKE_MCAST, Config5, MWF },
619 { WAKE_ANY, Config5, LanWake }
622 spin_lock_irq(&tp->lock);
624 RTL_W8(Cfg9346, Cfg9346_Unlock);
626 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
627 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
628 if (wol->wolopts & cfg[i].opt)
629 options |= cfg[i].mask;
630 RTL_W8(cfg[i].reg, options);
633 RTL_W8(Cfg9346, Cfg9346_Lock);
636 tp->features |= RTL_FEATURE_WOL;
638 tp->features &= ~RTL_FEATURE_WOL;
640 spin_unlock_irq(&tp->lock);
645 static void rtl8169_get_drvinfo(struct net_device *dev,
646 struct ethtool_drvinfo *info)
648 struct rtl8169_private *tp = netdev_priv(dev);
650 strcpy(info->driver, MODULENAME);
651 strcpy(info->version, RTL8169_VERSION);
652 strcpy(info->bus_info, pci_name(tp->pci_dev));
655 static int rtl8169_get_regs_len(struct net_device *dev)
657 return R8169_REGS_SIZE;
660 static int rtl8169_set_speed_tbi(struct net_device *dev,
661 u8 autoneg, u16 speed, u8 duplex)
663 struct rtl8169_private *tp = netdev_priv(dev);
664 void __iomem *ioaddr = tp->mmio_addr;
668 reg = RTL_R32(TBICSR);
669 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
670 (duplex == DUPLEX_FULL)) {
671 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
672 } else if (autoneg == AUTONEG_ENABLE)
673 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
675 if (netif_msg_link(tp)) {
676 printk(KERN_WARNING "%s: "
677 "incorrect speed setting refused in TBI mode\n",
686 static int rtl8169_set_speed_xmii(struct net_device *dev,
687 u8 autoneg, u16 speed, u8 duplex)
689 struct rtl8169_private *tp = netdev_priv(dev);
690 void __iomem *ioaddr = tp->mmio_addr;
691 int auto_nego, giga_ctrl;
693 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
694 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
695 ADVERTISE_100HALF | ADVERTISE_100FULL);
696 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
697 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
699 if (autoneg == AUTONEG_ENABLE) {
700 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
701 ADVERTISE_100HALF | ADVERTISE_100FULL);
702 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
704 if (speed == SPEED_10)
705 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
706 else if (speed == SPEED_100)
707 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
708 else if (speed == SPEED_1000)
709 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
711 if (duplex == DUPLEX_HALF)
712 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
714 if (duplex == DUPLEX_FULL)
715 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
717 /* This tweak comes straight from Realtek's driver. */
718 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
719 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
720 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
721 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
725 /* The 8100e/8101e do Fast Ethernet only. */
726 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
727 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
728 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
729 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
730 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
731 netif_msg_link(tp)) {
732 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
735 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
738 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
740 if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
741 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
742 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
743 mdio_write(ioaddr, 0x1f, 0x0000);
744 mdio_write(ioaddr, 0x0e, 0x0000);
747 tp->phy_auto_nego_reg = auto_nego;
748 tp->phy_1000_ctrl_reg = giga_ctrl;
750 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
751 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
752 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
756 static int rtl8169_set_speed(struct net_device *dev,
757 u8 autoneg, u16 speed, u8 duplex)
759 struct rtl8169_private *tp = netdev_priv(dev);
762 ret = tp->set_speed(dev, autoneg, speed, duplex);
764 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
765 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
770 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
772 struct rtl8169_private *tp = netdev_priv(dev);
776 spin_lock_irqsave(&tp->lock, flags);
777 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
778 spin_unlock_irqrestore(&tp->lock, flags);
783 static u32 rtl8169_get_rx_csum(struct net_device *dev)
785 struct rtl8169_private *tp = netdev_priv(dev);
787 return tp->cp_cmd & RxChkSum;
790 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
792 struct rtl8169_private *tp = netdev_priv(dev);
793 void __iomem *ioaddr = tp->mmio_addr;
796 spin_lock_irqsave(&tp->lock, flags);
799 tp->cp_cmd |= RxChkSum;
801 tp->cp_cmd &= ~RxChkSum;
803 RTL_W16(CPlusCmd, tp->cp_cmd);
806 spin_unlock_irqrestore(&tp->lock, flags);
811 #ifdef CONFIG_R8169_VLAN
813 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
816 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
817 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
820 static void rtl8169_vlan_rx_register(struct net_device *dev,
821 struct vlan_group *grp)
823 struct rtl8169_private *tp = netdev_priv(dev);
824 void __iomem *ioaddr = tp->mmio_addr;
827 spin_lock_irqsave(&tp->lock, flags);
830 tp->cp_cmd |= RxVlan;
832 tp->cp_cmd &= ~RxVlan;
833 RTL_W16(CPlusCmd, tp->cp_cmd);
835 spin_unlock_irqrestore(&tp->lock, flags);
838 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
841 u32 opts2 = le32_to_cpu(desc->opts2);
844 if (tp->vlgrp && (opts2 & RxVlanTag)) {
845 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
853 #else /* !CONFIG_R8169_VLAN */
855 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
861 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
869 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
871 struct rtl8169_private *tp = netdev_priv(dev);
872 void __iomem *ioaddr = tp->mmio_addr;
876 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
877 cmd->port = PORT_FIBRE;
878 cmd->transceiver = XCVR_INTERNAL;
880 status = RTL_R32(TBICSR);
881 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
882 cmd->autoneg = !!(status & TBINwEnable);
884 cmd->speed = SPEED_1000;
885 cmd->duplex = DUPLEX_FULL; /* Always set */
888 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
890 struct rtl8169_private *tp = netdev_priv(dev);
891 void __iomem *ioaddr = tp->mmio_addr;
894 cmd->supported = SUPPORTED_10baseT_Half |
895 SUPPORTED_10baseT_Full |
896 SUPPORTED_100baseT_Half |
897 SUPPORTED_100baseT_Full |
898 SUPPORTED_1000baseT_Full |
903 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
905 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
906 cmd->advertising |= ADVERTISED_10baseT_Half;
907 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
908 cmd->advertising |= ADVERTISED_10baseT_Full;
909 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
910 cmd->advertising |= ADVERTISED_100baseT_Half;
911 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
912 cmd->advertising |= ADVERTISED_100baseT_Full;
913 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
914 cmd->advertising |= ADVERTISED_1000baseT_Full;
916 status = RTL_R8(PHYstatus);
918 if (status & _1000bpsF)
919 cmd->speed = SPEED_1000;
920 else if (status & _100bps)
921 cmd->speed = SPEED_100;
922 else if (status & _10bps)
923 cmd->speed = SPEED_10;
925 if (status & TxFlowCtrl)
926 cmd->advertising |= ADVERTISED_Asym_Pause;
927 if (status & RxFlowCtrl)
928 cmd->advertising |= ADVERTISED_Pause;
930 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
931 DUPLEX_FULL : DUPLEX_HALF;
934 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
936 struct rtl8169_private *tp = netdev_priv(dev);
939 spin_lock_irqsave(&tp->lock, flags);
941 tp->get_settings(dev, cmd);
943 spin_unlock_irqrestore(&tp->lock, flags);
947 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
950 struct rtl8169_private *tp = netdev_priv(dev);
953 if (regs->len > R8169_REGS_SIZE)
954 regs->len = R8169_REGS_SIZE;
956 spin_lock_irqsave(&tp->lock, flags);
957 memcpy_fromio(p, tp->mmio_addr, regs->len);
958 spin_unlock_irqrestore(&tp->lock, flags);
961 static u32 rtl8169_get_msglevel(struct net_device *dev)
963 struct rtl8169_private *tp = netdev_priv(dev);
965 return tp->msg_enable;
968 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
970 struct rtl8169_private *tp = netdev_priv(dev);
972 tp->msg_enable = value;
975 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
982 "tx_single_collisions",
983 "tx_multi_collisions",
991 struct rtl8169_counters {
998 __le32 tx_one_collision;
999 __le32 tx_multi_collision;
1001 __le64 rx_broadcast;
1002 __le32 rx_multicast;
1007 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1011 return ARRAY_SIZE(rtl8169_gstrings);
1017 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1018 struct ethtool_stats *stats, u64 *data)
1020 struct rtl8169_private *tp = netdev_priv(dev);
1021 void __iomem *ioaddr = tp->mmio_addr;
1022 struct rtl8169_counters *counters;
1028 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1032 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1033 cmd = (u64)paddr & DMA_32BIT_MASK;
1034 RTL_W32(CounterAddrLow, cmd);
1035 RTL_W32(CounterAddrLow, cmd | CounterDump);
1037 while (RTL_R32(CounterAddrLow) & CounterDump) {
1038 if (msleep_interruptible(1))
1042 RTL_W32(CounterAddrLow, 0);
1043 RTL_W32(CounterAddrHigh, 0);
1045 data[0] = le64_to_cpu(counters->tx_packets);
1046 data[1] = le64_to_cpu(counters->rx_packets);
1047 data[2] = le64_to_cpu(counters->tx_errors);
1048 data[3] = le32_to_cpu(counters->rx_errors);
1049 data[4] = le16_to_cpu(counters->rx_missed);
1050 data[5] = le16_to_cpu(counters->align_errors);
1051 data[6] = le32_to_cpu(counters->tx_one_collision);
1052 data[7] = le32_to_cpu(counters->tx_multi_collision);
1053 data[8] = le64_to_cpu(counters->rx_unicast);
1054 data[9] = le64_to_cpu(counters->rx_broadcast);
1055 data[10] = le32_to_cpu(counters->rx_multicast);
1056 data[11] = le16_to_cpu(counters->tx_aborted);
1057 data[12] = le16_to_cpu(counters->tx_underun);
1059 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1062 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1066 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1071 static const struct ethtool_ops rtl8169_ethtool_ops = {
1072 .get_drvinfo = rtl8169_get_drvinfo,
1073 .get_regs_len = rtl8169_get_regs_len,
1074 .get_link = ethtool_op_get_link,
1075 .get_settings = rtl8169_get_settings,
1076 .set_settings = rtl8169_set_settings,
1077 .get_msglevel = rtl8169_get_msglevel,
1078 .set_msglevel = rtl8169_set_msglevel,
1079 .get_rx_csum = rtl8169_get_rx_csum,
1080 .set_rx_csum = rtl8169_set_rx_csum,
1081 .set_tx_csum = ethtool_op_set_tx_csum,
1082 .set_sg = ethtool_op_set_sg,
1083 .set_tso = ethtool_op_set_tso,
1084 .get_regs = rtl8169_get_regs,
1085 .get_wol = rtl8169_get_wol,
1086 .set_wol = rtl8169_set_wol,
1087 .get_strings = rtl8169_get_strings,
1088 .get_sset_count = rtl8169_get_sset_count,
1089 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1092 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1093 int bitnum, int bitval)
1097 val = mdio_read(ioaddr, reg);
1098 val = (bitval == 1) ?
1099 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1100 mdio_write(ioaddr, reg, val & 0xffff);
1103 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1104 void __iomem *ioaddr)
1107 * The driver currently handles the 8168Bf and the 8168Be identically
1108 * but they can be identified more specifically through the test below
1111 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1113 * Same thing for the 8101Eb and the 8101Ec:
1115 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1123 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1124 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1125 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1126 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1129 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1130 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1131 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1132 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1135 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1136 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1137 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1138 /* FIXME: where did these entries come from ? -- FR */
1139 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1140 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1143 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1144 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1145 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1146 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1147 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1148 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1150 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1154 reg = RTL_R32(TxConfig);
1155 while ((reg & p->mask) != p->val)
1157 tp->mac_version = p->mac_version;
1159 if (p->mask == 0x00000000) {
1160 struct pci_dev *pdev = tp->pci_dev;
1162 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1166 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1168 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1171 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1174 u16 regs[5]; /* Beware of bit-sign propagation */
1175 } phy_magic[5] = { {
1176 { 0x0000, //w 4 15 12 0
1177 0x00a1, //w 3 15 0 00a1
1178 0x0008, //w 2 15 0 0008
1179 0x1020, //w 1 15 0 1020
1180 0x1000 } },{ //w 0 15 0 1000
1181 { 0x7000, //w 4 15 12 7
1182 0xff41, //w 3 15 0 ff41
1183 0xde60, //w 2 15 0 de60
1184 0x0140, //w 1 15 0 0140
1185 0x0077 } },{ //w 0 15 0 0077
1186 { 0xa000, //w 4 15 12 a
1187 0xdf01, //w 3 15 0 df01
1188 0xdf20, //w 2 15 0 df20
1189 0xff95, //w 1 15 0 ff95
1190 0xfa00 } },{ //w 0 15 0 fa00
1191 { 0xb000, //w 4 15 12 b
1192 0xff41, //w 3 15 0 ff41
1193 0xde20, //w 2 15 0 de20
1194 0x0140, //w 1 15 0 0140
1195 0x00bb } },{ //w 0 15 0 00bb
1196 { 0xf000, //w 4 15 12 f
1197 0xdf01, //w 3 15 0 df01
1198 0xdf20, //w 2 15 0 df20
1199 0xff95, //w 1 15 0 ff95
1200 0xbf00 } //w 0 15 0 bf00
1205 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1206 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1207 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1208 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1210 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1213 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1214 mdio_write(ioaddr, pos, val);
1216 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1217 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1218 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1220 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1223 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1225 mdio_write(ioaddr, 31, 0x0002);
1226 mdio_write(ioaddr, 1, 0x90d0);
1227 mdio_write(ioaddr, 31, 0x0000);
1230 static void rtl_hw_phy_config(struct net_device *dev)
1232 struct rtl8169_private *tp = netdev_priv(dev);
1233 void __iomem *ioaddr = tp->mmio_addr;
1235 rtl8169_print_mac_version(tp);
1237 switch (tp->mac_version) {
1238 case RTL_GIGA_MAC_VER_01:
1240 case RTL_GIGA_MAC_VER_02:
1241 case RTL_GIGA_MAC_VER_03:
1242 rtl8169s_hw_phy_config(ioaddr);
1244 case RTL_GIGA_MAC_VER_04:
1245 rtl8169sb_hw_phy_config(ioaddr);
1252 static void rtl8169_phy_timer(unsigned long __opaque)
1254 struct net_device *dev = (struct net_device *)__opaque;
1255 struct rtl8169_private *tp = netdev_priv(dev);
1256 struct timer_list *timer = &tp->timer;
1257 void __iomem *ioaddr = tp->mmio_addr;
1258 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1260 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1262 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1265 spin_lock_irq(&tp->lock);
1267 if (tp->phy_reset_pending(ioaddr)) {
1269 * A busy loop could burn quite a few cycles on nowadays CPU.
1270 * Let's delay the execution of the timer for a few ticks.
1276 if (tp->link_ok(ioaddr))
1279 if (netif_msg_link(tp))
1280 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1282 tp->phy_reset_enable(ioaddr);
1285 mod_timer(timer, jiffies + timeout);
1287 spin_unlock_irq(&tp->lock);
1290 static inline void rtl8169_delete_timer(struct net_device *dev)
1292 struct rtl8169_private *tp = netdev_priv(dev);
1293 struct timer_list *timer = &tp->timer;
1295 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1298 del_timer_sync(timer);
1301 static inline void rtl8169_request_timer(struct net_device *dev)
1303 struct rtl8169_private *tp = netdev_priv(dev);
1304 struct timer_list *timer = &tp->timer;
1306 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1309 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1312 #ifdef CONFIG_NET_POLL_CONTROLLER
1314 * Polling 'interrupt' - used by things like netconsole to send skbs
1315 * without having to re-enable interrupts. It's not called while
1316 * the interrupt routine is executing.
1318 static void rtl8169_netpoll(struct net_device *dev)
1320 struct rtl8169_private *tp = netdev_priv(dev);
1321 struct pci_dev *pdev = tp->pci_dev;
1323 disable_irq(pdev->irq);
1324 rtl8169_interrupt(pdev->irq, dev);
1325 enable_irq(pdev->irq);
1329 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1330 void __iomem *ioaddr)
1333 pci_release_regions(pdev);
1334 pci_disable_device(pdev);
1338 static void rtl8169_phy_reset(struct net_device *dev,
1339 struct rtl8169_private *tp)
1341 void __iomem *ioaddr = tp->mmio_addr;
1344 tp->phy_reset_enable(ioaddr);
1345 for (i = 0; i < 100; i++) {
1346 if (!tp->phy_reset_pending(ioaddr))
1350 if (netif_msg_link(tp))
1351 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1354 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1356 void __iomem *ioaddr = tp->mmio_addr;
1358 rtl_hw_phy_config(dev);
1360 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1363 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1365 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1366 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1368 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1369 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1371 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1372 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1375 rtl8169_phy_reset(dev, tp);
1378 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1379 * only 8101. Don't panic.
1381 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1383 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1384 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1387 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1389 void __iomem *ioaddr = tp->mmio_addr;
1393 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1394 high = addr[4] | (addr[5] << 8);
1396 spin_lock_irq(&tp->lock);
1398 RTL_W8(Cfg9346, Cfg9346_Unlock);
1400 RTL_W32(MAC4, high);
1401 RTL_W8(Cfg9346, Cfg9346_Lock);
1403 spin_unlock_irq(&tp->lock);
1406 static int rtl_set_mac_address(struct net_device *dev, void *p)
1408 struct rtl8169_private *tp = netdev_priv(dev);
1409 struct sockaddr *addr = p;
1411 if (!is_valid_ether_addr(addr->sa_data))
1412 return -EADDRNOTAVAIL;
1414 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1416 rtl_rar_set(tp, dev->dev_addr);
1421 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1423 struct rtl8169_private *tp = netdev_priv(dev);
1424 struct mii_ioctl_data *data = if_mii(ifr);
1426 if (!netif_running(dev))
1431 data->phy_id = 32; /* Internal PHY */
1435 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1439 if (!capable(CAP_NET_ADMIN))
1441 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1447 static const struct rtl_cfg_info {
1448 void (*hw_start)(struct net_device *);
1449 unsigned int region;
1454 } rtl_cfg_infos [] = {
1456 .hw_start = rtl_hw_start_8169,
1459 .intr_event = SYSErr | LinkChg | RxOverflow |
1460 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1461 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1465 .hw_start = rtl_hw_start_8168,
1468 .intr_event = SYSErr | LinkChg | RxOverflow |
1469 TxErr | TxOK | RxOK | RxErr,
1470 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1471 .msi = RTL_FEATURE_MSI
1474 .hw_start = rtl_hw_start_8101,
1477 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1478 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1479 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1480 .msi = RTL_FEATURE_MSI
1484 /* Cfg9346_Unlock assumed. */
1485 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1486 const struct rtl_cfg_info *cfg)
1491 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1493 if (pci_enable_msi(pdev)) {
1494 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1497 msi = RTL_FEATURE_MSI;
1500 RTL_W8(Config2, cfg2);
1504 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1506 if (tp->features & RTL_FEATURE_MSI) {
1507 pci_disable_msi(pdev);
1508 tp->features &= ~RTL_FEATURE_MSI;
1512 static int __devinit
1513 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1515 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1516 const unsigned int region = cfg->region;
1517 struct rtl8169_private *tp;
1518 struct net_device *dev;
1519 void __iomem *ioaddr;
1523 if (netif_msg_drv(&debug)) {
1524 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1525 MODULENAME, RTL8169_VERSION);
1528 dev = alloc_etherdev(sizeof (*tp));
1530 if (netif_msg_drv(&debug))
1531 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1536 SET_NETDEV_DEV(dev, &pdev->dev);
1537 tp = netdev_priv(dev);
1539 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1541 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1542 rc = pci_enable_device(pdev);
1544 if (netif_msg_probe(tp))
1545 dev_err(&pdev->dev, "enable failure\n");
1546 goto err_out_free_dev_1;
1549 rc = pci_set_mwi(pdev);
1551 goto err_out_disable_2;
1553 /* make sure PCI base addr 1 is MMIO */
1554 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1555 if (netif_msg_probe(tp)) {
1557 "region #%d not an MMIO resource, aborting\n",
1564 /* check for weird/broken PCI region reporting */
1565 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1566 if (netif_msg_probe(tp)) {
1568 "Invalid PCI region size(s), aborting\n");
1574 rc = pci_request_regions(pdev, MODULENAME);
1576 if (netif_msg_probe(tp))
1577 dev_err(&pdev->dev, "could not request regions.\n");
1581 tp->cp_cmd = PCIMulRW | RxChkSum;
1583 if ((sizeof(dma_addr_t) > 4) &&
1584 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1585 tp->cp_cmd |= PCIDAC;
1586 dev->features |= NETIF_F_HIGHDMA;
1588 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1590 if (netif_msg_probe(tp)) {
1592 "DMA configuration failed.\n");
1594 goto err_out_free_res_4;
1598 pci_set_master(pdev);
1600 /* ioremap MMIO region */
1601 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1603 if (netif_msg_probe(tp))
1604 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1606 goto err_out_free_res_4;
1609 /* Unneeded ? Don't mess with Mrs. Murphy. */
1610 rtl8169_irq_mask_and_ack(ioaddr);
1612 /* Soft reset the chip. */
1613 RTL_W8(ChipCmd, CmdReset);
1615 /* Check that the chip has finished the reset. */
1616 for (i = 0; i < 100; i++) {
1617 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1619 msleep_interruptible(1);
1622 /* Identify chip attached to board */
1623 rtl8169_get_mac_version(tp, ioaddr);
1625 rtl8169_print_mac_version(tp);
1627 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1628 if (tp->mac_version == rtl_chip_info[i].mac_version)
1632 /* Unknown chip: assume array element #0, original RTL-8169 */
1633 if (netif_msg_probe(tp)) {
1634 dev_printk(KERN_DEBUG, &pdev->dev,
1635 "unknown chip version, assuming %s\n",
1636 rtl_chip_info[0].name);
1642 RTL_W8(Cfg9346, Cfg9346_Unlock);
1643 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1644 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1645 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
1646 RTL_W8(Cfg9346, Cfg9346_Lock);
1648 if (RTL_R8(PHYstatus) & TBI_Enable) {
1649 tp->set_speed = rtl8169_set_speed_tbi;
1650 tp->get_settings = rtl8169_gset_tbi;
1651 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1652 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1653 tp->link_ok = rtl8169_tbi_link_ok;
1655 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1657 tp->set_speed = rtl8169_set_speed_xmii;
1658 tp->get_settings = rtl8169_gset_xmii;
1659 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1660 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1661 tp->link_ok = rtl8169_xmii_link_ok;
1663 dev->do_ioctl = rtl8169_ioctl;
1666 /* Get MAC address. FIXME: read EEPROM */
1667 for (i = 0; i < MAC_ADDR_LEN; i++)
1668 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1669 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1671 dev->open = rtl8169_open;
1672 dev->hard_start_xmit = rtl8169_start_xmit;
1673 dev->get_stats = rtl8169_get_stats;
1674 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1675 dev->stop = rtl8169_close;
1676 dev->tx_timeout = rtl8169_tx_timeout;
1677 dev->set_multicast_list = rtl_set_rx_mode;
1678 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1679 dev->irq = pdev->irq;
1680 dev->base_addr = (unsigned long) ioaddr;
1681 dev->change_mtu = rtl8169_change_mtu;
1682 dev->set_mac_address = rtl_set_mac_address;
1684 #ifdef CONFIG_R8169_NAPI
1685 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1688 #ifdef CONFIG_R8169_VLAN
1689 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1690 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1693 #ifdef CONFIG_NET_POLL_CONTROLLER
1694 dev->poll_controller = rtl8169_netpoll;
1697 tp->intr_mask = 0xffff;
1699 tp->mmio_addr = ioaddr;
1700 tp->align = cfg->align;
1701 tp->hw_start = cfg->hw_start;
1702 tp->intr_event = cfg->intr_event;
1703 tp->napi_event = cfg->napi_event;
1705 init_timer(&tp->timer);
1706 tp->timer.data = (unsigned long) dev;
1707 tp->timer.function = rtl8169_phy_timer;
1709 spin_lock_init(&tp->lock);
1711 rc = register_netdev(dev);
1715 pci_set_drvdata(pdev, dev);
1717 if (netif_msg_probe(tp)) {
1718 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1720 printk(KERN_INFO "%s: %s at 0x%lx, "
1721 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1722 "XID %08x IRQ %d\n",
1724 rtl_chip_info[tp->chipset].name,
1726 dev->dev_addr[0], dev->dev_addr[1],
1727 dev->dev_addr[2], dev->dev_addr[3],
1728 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1731 rtl8169_init_phy(dev, tp);
1737 rtl_disable_msi(pdev, tp);
1740 pci_release_regions(pdev);
1742 pci_clear_mwi(pdev);
1744 pci_disable_device(pdev);
1750 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1752 struct net_device *dev = pci_get_drvdata(pdev);
1753 struct rtl8169_private *tp = netdev_priv(dev);
1755 flush_scheduled_work();
1757 unregister_netdev(dev);
1758 rtl_disable_msi(pdev, tp);
1759 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1760 pci_set_drvdata(pdev, NULL);
1763 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1764 struct net_device *dev)
1766 unsigned int mtu = dev->mtu;
1768 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1771 static int rtl8169_open(struct net_device *dev)
1773 struct rtl8169_private *tp = netdev_priv(dev);
1774 struct pci_dev *pdev = tp->pci_dev;
1775 int retval = -ENOMEM;
1778 rtl8169_set_rxbufsize(tp, dev);
1781 * Rx and Tx desscriptors needs 256 bytes alignment.
1782 * pci_alloc_consistent provides more.
1784 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1786 if (!tp->TxDescArray)
1789 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1791 if (!tp->RxDescArray)
1794 retval = rtl8169_init_ring(dev);
1798 INIT_DELAYED_WORK(&tp->task, NULL);
1802 retval = request_irq(dev->irq, rtl8169_interrupt,
1803 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
1806 goto err_release_ring_2;
1808 #ifdef CONFIG_R8169_NAPI
1809 napi_enable(&tp->napi);
1814 rtl8169_request_timer(dev);
1816 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1821 rtl8169_rx_clear(tp);
1823 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1826 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1831 static void rtl8169_hw_reset(void __iomem *ioaddr)
1833 /* Disable interrupts */
1834 rtl8169_irq_mask_and_ack(ioaddr);
1836 /* Reset the chipset */
1837 RTL_W8(ChipCmd, CmdReset);
1843 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1845 void __iomem *ioaddr = tp->mmio_addr;
1846 u32 cfg = rtl8169_rx_config;
1848 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1849 RTL_W32(RxConfig, cfg);
1851 /* Set DMA burst size and Interframe Gap Time */
1852 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1853 (InterFrameGap << TxInterFrameGapShift));
1856 static void rtl_hw_start(struct net_device *dev)
1858 struct rtl8169_private *tp = netdev_priv(dev);
1859 void __iomem *ioaddr = tp->mmio_addr;
1862 /* Soft reset the chip. */
1863 RTL_W8(ChipCmd, CmdReset);
1865 /* Check that the chip has finished the reset. */
1866 for (i = 0; i < 100; i++) {
1867 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1869 msleep_interruptible(1);
1874 netif_start_queue(dev);
1878 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1879 void __iomem *ioaddr)
1882 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1883 * register to be written before TxDescAddrLow to work.
1884 * Switching from MMIO to I/O access fixes the issue as well.
1886 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1887 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1888 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1889 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1892 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1896 cmd = RTL_R16(CPlusCmd);
1897 RTL_W16(CPlusCmd, cmd);
1901 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1903 /* Low hurts. Let's disable the filtering. */
1904 RTL_W16(RxMaxSize, 16383);
1907 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1914 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1915 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1916 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1917 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1922 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1923 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1924 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1925 RTL_W32(0x7c, p->val);
1931 static void rtl_hw_start_8169(struct net_device *dev)
1933 struct rtl8169_private *tp = netdev_priv(dev);
1934 void __iomem *ioaddr = tp->mmio_addr;
1935 struct pci_dev *pdev = tp->pci_dev;
1937 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1938 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1939 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1942 RTL_W8(Cfg9346, Cfg9346_Unlock);
1943 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1944 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1945 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1946 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1947 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1949 RTL_W8(EarlyTxThres, EarlyTxThld);
1951 rtl_set_rx_max_size(ioaddr);
1953 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1954 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1955 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1956 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1957 rtl_set_rx_tx_config_registers(tp);
1959 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1961 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1962 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1963 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1964 "Bit-3 and bit-14 MUST be 1\n");
1965 tp->cp_cmd |= (1 << 14);
1968 RTL_W16(CPlusCmd, tp->cp_cmd);
1970 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1973 * Undocumented corner. Supposedly:
1974 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1976 RTL_W16(IntrMitigate, 0x0000);
1978 rtl_set_rx_tx_desc_registers(tp, ioaddr);
1980 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
1981 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1982 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
1983 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
1984 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1985 rtl_set_rx_tx_config_registers(tp);
1988 RTL_W8(Cfg9346, Cfg9346_Lock);
1990 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1993 RTL_W32(RxMissed, 0);
1995 rtl_set_rx_mode(dev);
1997 /* no early-rx interrupts */
1998 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2000 /* Enable all known interrupts by setting the interrupt mask. */
2001 RTL_W16(IntrMask, tp->intr_event);
2004 static void rtl_hw_start_8168(struct net_device *dev)
2006 struct rtl8169_private *tp = netdev_priv(dev);
2007 void __iomem *ioaddr = tp->mmio_addr;
2008 struct pci_dev *pdev = tp->pci_dev;
2011 RTL_W8(Cfg9346, Cfg9346_Unlock);
2013 RTL_W8(EarlyTxThres, EarlyTxThld);
2015 rtl_set_rx_max_size(ioaddr);
2017 rtl_set_rx_tx_config_registers(tp);
2019 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2021 RTL_W16(CPlusCmd, tp->cp_cmd);
2023 /* Tx performance tweak. */
2024 pci_read_config_byte(pdev, 0x69, &ctl);
2025 ctl = (ctl & ~0x70) | 0x50;
2026 pci_write_config_byte(pdev, 0x69, ctl);
2028 RTL_W16(IntrMitigate, 0x5151);
2030 /* Work around for RxFIFO overflow. */
2031 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2032 tp->intr_event |= RxFIFOOver | PCSTimeout;
2033 tp->intr_event &= ~RxOverflow;
2036 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2038 RTL_W8(Cfg9346, Cfg9346_Lock);
2042 RTL_W32(RxMissed, 0);
2044 rtl_set_rx_mode(dev);
2046 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2048 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2050 RTL_W16(IntrMask, tp->intr_event);
2053 static void rtl_hw_start_8101(struct net_device *dev)
2055 struct rtl8169_private *tp = netdev_priv(dev);
2056 void __iomem *ioaddr = tp->mmio_addr;
2057 struct pci_dev *pdev = tp->pci_dev;
2059 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2060 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2061 pci_write_config_word(pdev, 0x68, 0x00);
2062 pci_write_config_word(pdev, 0x69, 0x08);
2065 RTL_W8(Cfg9346, Cfg9346_Unlock);
2067 RTL_W8(EarlyTxThres, EarlyTxThld);
2069 rtl_set_rx_max_size(ioaddr);
2071 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2073 RTL_W16(CPlusCmd, tp->cp_cmd);
2075 RTL_W16(IntrMitigate, 0x0000);
2077 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2079 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2080 rtl_set_rx_tx_config_registers(tp);
2082 RTL_W8(Cfg9346, Cfg9346_Lock);
2086 RTL_W32(RxMissed, 0);
2088 rtl_set_rx_mode(dev);
2090 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2092 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2094 RTL_W16(IntrMask, tp->intr_event);
2097 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2099 struct rtl8169_private *tp = netdev_priv(dev);
2102 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2107 if (!netif_running(dev))
2112 rtl8169_set_rxbufsize(tp, dev);
2114 ret = rtl8169_init_ring(dev);
2118 #ifdef CONFIG_R8169_NAPI
2119 napi_enable(&tp->napi);
2124 rtl8169_request_timer(dev);
2130 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2132 desc->addr = 0x0badbadbadbadbadull;
2133 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2136 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2137 struct sk_buff **sk_buff, struct RxDesc *desc)
2139 struct pci_dev *pdev = tp->pci_dev;
2141 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2142 PCI_DMA_FROMDEVICE);
2143 dev_kfree_skb(*sk_buff);
2145 rtl8169_make_unusable_by_asic(desc);
2148 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2150 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2152 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2155 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2158 desc->addr = cpu_to_le64(mapping);
2160 rtl8169_mark_to_asic(desc, rx_buf_sz);
2163 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2164 struct net_device *dev,
2165 struct RxDesc *desc, int rx_buf_sz,
2168 struct sk_buff *skb;
2172 pad = align ? align : NET_IP_ALIGN;
2174 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2178 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2180 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2181 PCI_DMA_FROMDEVICE);
2183 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2188 rtl8169_make_unusable_by_asic(desc);
2192 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2196 for (i = 0; i < NUM_RX_DESC; i++) {
2197 if (tp->Rx_skbuff[i]) {
2198 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2199 tp->RxDescArray + i);
2204 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2209 for (cur = start; end - cur != 0; cur++) {
2210 struct sk_buff *skb;
2211 unsigned int i = cur % NUM_RX_DESC;
2213 WARN_ON((s32)(end - cur) < 0);
2215 if (tp->Rx_skbuff[i])
2218 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2219 tp->RxDescArray + i,
2220 tp->rx_buf_sz, tp->align);
2224 tp->Rx_skbuff[i] = skb;
2229 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2231 desc->opts1 |= cpu_to_le32(RingEnd);
2234 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2236 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2239 static int rtl8169_init_ring(struct net_device *dev)
2241 struct rtl8169_private *tp = netdev_priv(dev);
2243 rtl8169_init_ring_indexes(tp);
2245 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2246 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2248 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2251 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2256 rtl8169_rx_clear(tp);
2260 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2261 struct TxDesc *desc)
2263 unsigned int len = tx_skb->len;
2265 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2272 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2276 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2277 unsigned int entry = i % NUM_TX_DESC;
2278 struct ring_info *tx_skb = tp->tx_skb + entry;
2279 unsigned int len = tx_skb->len;
2282 struct sk_buff *skb = tx_skb->skb;
2284 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2285 tp->TxDescArray + entry);
2290 tp->dev->stats.tx_dropped++;
2293 tp->cur_tx = tp->dirty_tx = 0;
2296 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2298 struct rtl8169_private *tp = netdev_priv(dev);
2300 PREPARE_DELAYED_WORK(&tp->task, task);
2301 schedule_delayed_work(&tp->task, 4);
2304 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2306 struct rtl8169_private *tp = netdev_priv(dev);
2307 void __iomem *ioaddr = tp->mmio_addr;
2309 synchronize_irq(dev->irq);
2311 /* Wait for any pending NAPI task to complete */
2312 #ifdef CONFIG_R8169_NAPI
2313 napi_disable(&tp->napi);
2316 rtl8169_irq_mask_and_ack(ioaddr);
2318 #ifdef CONFIG_R8169_NAPI
2319 napi_enable(&tp->napi);
2323 static void rtl8169_reinit_task(struct work_struct *work)
2325 struct rtl8169_private *tp =
2326 container_of(work, struct rtl8169_private, task.work);
2327 struct net_device *dev = tp->dev;
2332 if (!netif_running(dev))
2335 rtl8169_wait_for_quiescence(dev);
2338 ret = rtl8169_open(dev);
2339 if (unlikely(ret < 0)) {
2340 if (net_ratelimit() && netif_msg_drv(tp)) {
2341 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
2342 " Rescheduling.\n", dev->name, ret);
2344 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2351 static void rtl8169_reset_task(struct work_struct *work)
2353 struct rtl8169_private *tp =
2354 container_of(work, struct rtl8169_private, task.work);
2355 struct net_device *dev = tp->dev;
2359 if (!netif_running(dev))
2362 rtl8169_wait_for_quiescence(dev);
2364 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2365 rtl8169_tx_clear(tp);
2367 if (tp->dirty_rx == tp->cur_rx) {
2368 rtl8169_init_ring_indexes(tp);
2370 netif_wake_queue(dev);
2371 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2373 if (net_ratelimit() && netif_msg_intr(tp)) {
2374 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
2377 rtl8169_schedule_work(dev, rtl8169_reset_task);
2384 static void rtl8169_tx_timeout(struct net_device *dev)
2386 struct rtl8169_private *tp = netdev_priv(dev);
2388 rtl8169_hw_reset(tp->mmio_addr);
2390 /* Let's wait a bit while any (async) irq lands on */
2391 rtl8169_schedule_work(dev, rtl8169_reset_task);
2394 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2397 struct skb_shared_info *info = skb_shinfo(skb);
2398 unsigned int cur_frag, entry;
2399 struct TxDesc * uninitialized_var(txd);
2402 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2403 skb_frag_t *frag = info->frags + cur_frag;
2408 entry = (entry + 1) % NUM_TX_DESC;
2410 txd = tp->TxDescArray + entry;
2412 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2413 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2415 /* anti gcc 2.95.3 bugware (sic) */
2416 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2418 txd->opts1 = cpu_to_le32(status);
2419 txd->addr = cpu_to_le64(mapping);
2421 tp->tx_skb[entry].len = len;
2425 tp->tx_skb[entry].skb = skb;
2426 txd->opts1 |= cpu_to_le32(LastFrag);
2432 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2434 if (dev->features & NETIF_F_TSO) {
2435 u32 mss = skb_shinfo(skb)->gso_size;
2438 return LargeSend | ((mss & MSSMask) << MSSShift);
2440 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2441 const struct iphdr *ip = ip_hdr(skb);
2443 if (ip->protocol == IPPROTO_TCP)
2444 return IPCS | TCPCS;
2445 else if (ip->protocol == IPPROTO_UDP)
2446 return IPCS | UDPCS;
2447 WARN_ON(1); /* we need a WARN() */
2452 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2454 struct rtl8169_private *tp = netdev_priv(dev);
2455 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2456 struct TxDesc *txd = tp->TxDescArray + entry;
2457 void __iomem *ioaddr = tp->mmio_addr;
2461 int ret = NETDEV_TX_OK;
2463 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2464 if (netif_msg_drv(tp)) {
2466 "%s: BUG! Tx Ring full when queue awake!\n",
2472 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2475 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2477 frags = rtl8169_xmit_frags(tp, skb, opts1);
2479 len = skb_headlen(skb);
2484 if (unlikely(len < ETH_ZLEN)) {
2485 if (skb_padto(skb, ETH_ZLEN))
2486 goto err_update_stats;
2490 opts1 |= FirstFrag | LastFrag;
2491 tp->tx_skb[entry].skb = skb;
2494 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2496 tp->tx_skb[entry].len = len;
2497 txd->addr = cpu_to_le64(mapping);
2498 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2502 /* anti gcc 2.95.3 bugware (sic) */
2503 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2504 txd->opts1 = cpu_to_le32(status);
2506 dev->trans_start = jiffies;
2508 tp->cur_tx += frags + 1;
2512 RTL_W8(TxPoll, NPQ); /* set polling bit */
2514 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2515 netif_stop_queue(dev);
2517 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2518 netif_wake_queue(dev);
2525 netif_stop_queue(dev);
2526 ret = NETDEV_TX_BUSY;
2528 dev->stats.tx_dropped++;
2532 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2534 struct rtl8169_private *tp = netdev_priv(dev);
2535 struct pci_dev *pdev = tp->pci_dev;
2536 void __iomem *ioaddr = tp->mmio_addr;
2537 u16 pci_status, pci_cmd;
2539 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2540 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2542 if (netif_msg_intr(tp)) {
2544 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2545 dev->name, pci_cmd, pci_status);
2549 * The recovery sequence below admits a very elaborated explanation:
2550 * - it seems to work;
2551 * - I did not see what else could be done;
2552 * - it makes iop3xx happy.
2554 * Feel free to adjust to your needs.
2556 if (pdev->broken_parity_status)
2557 pci_cmd &= ~PCI_COMMAND_PARITY;
2559 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2561 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2563 pci_write_config_word(pdev, PCI_STATUS,
2564 pci_status & (PCI_STATUS_DETECTED_PARITY |
2565 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2566 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2568 /* The infamous DAC f*ckup only happens at boot time */
2569 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2570 if (netif_msg_intr(tp))
2571 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2572 tp->cp_cmd &= ~PCIDAC;
2573 RTL_W16(CPlusCmd, tp->cp_cmd);
2574 dev->features &= ~NETIF_F_HIGHDMA;
2577 rtl8169_hw_reset(ioaddr);
2579 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2582 static void rtl8169_tx_interrupt(struct net_device *dev,
2583 struct rtl8169_private *tp,
2584 void __iomem *ioaddr)
2586 unsigned int dirty_tx, tx_left;
2588 dirty_tx = tp->dirty_tx;
2590 tx_left = tp->cur_tx - dirty_tx;
2592 while (tx_left > 0) {
2593 unsigned int entry = dirty_tx % NUM_TX_DESC;
2594 struct ring_info *tx_skb = tp->tx_skb + entry;
2595 u32 len = tx_skb->len;
2599 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2600 if (status & DescOwn)
2603 dev->stats.tx_bytes += len;
2604 dev->stats.tx_packets++;
2606 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2608 if (status & LastFrag) {
2609 dev_kfree_skb_irq(tx_skb->skb);
2616 if (tp->dirty_tx != dirty_tx) {
2617 tp->dirty_tx = dirty_tx;
2619 if (netif_queue_stopped(dev) &&
2620 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2621 netif_wake_queue(dev);
2624 * 8168 hack: TxPoll requests are lost when the Tx packets are
2625 * too close. Let's kick an extra TxPoll request when a burst
2626 * of start_xmit activity is detected (if it is not detected,
2627 * it is slow enough). -- FR
2630 if (tp->cur_tx != dirty_tx)
2631 RTL_W8(TxPoll, NPQ);
2635 static inline int rtl8169_fragmented_frame(u32 status)
2637 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2640 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2642 u32 opts1 = le32_to_cpu(desc->opts1);
2643 u32 status = opts1 & RxProtoMask;
2645 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2646 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2647 ((status == RxProtoIP) && !(opts1 & IPFail)))
2648 skb->ip_summed = CHECKSUM_UNNECESSARY;
2650 skb->ip_summed = CHECKSUM_NONE;
2653 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2654 struct rtl8169_private *tp, int pkt_size,
2657 struct sk_buff *skb;
2660 if (pkt_size >= rx_copybreak)
2663 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2667 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2668 PCI_DMA_FROMDEVICE);
2669 skb_reserve(skb, NET_IP_ALIGN);
2670 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2677 static int rtl8169_rx_interrupt(struct net_device *dev,
2678 struct rtl8169_private *tp,
2679 void __iomem *ioaddr, u32 budget)
2681 unsigned int cur_rx, rx_left;
2682 unsigned int delta, count;
2684 cur_rx = tp->cur_rx;
2685 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2686 rx_left = rtl8169_rx_quota(rx_left, budget);
2688 for (; rx_left > 0; rx_left--, cur_rx++) {
2689 unsigned int entry = cur_rx % NUM_RX_DESC;
2690 struct RxDesc *desc = tp->RxDescArray + entry;
2694 status = le32_to_cpu(desc->opts1);
2696 if (status & DescOwn)
2698 if (unlikely(status & RxRES)) {
2699 if (netif_msg_rx_err(tp)) {
2701 "%s: Rx ERROR. status = %08x\n",
2704 dev->stats.rx_errors++;
2705 if (status & (RxRWT | RxRUNT))
2706 dev->stats.rx_length_errors++;
2708 dev->stats.rx_crc_errors++;
2709 if (status & RxFOVF) {
2710 rtl8169_schedule_work(dev, rtl8169_reset_task);
2711 dev->stats.rx_fifo_errors++;
2713 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2715 struct sk_buff *skb = tp->Rx_skbuff[entry];
2716 dma_addr_t addr = le64_to_cpu(desc->addr);
2717 int pkt_size = (status & 0x00001FFF) - 4;
2718 struct pci_dev *pdev = tp->pci_dev;
2721 * The driver does not support incoming fragmented
2722 * frames. They are seen as a symptom of over-mtu
2725 if (unlikely(rtl8169_fragmented_frame(status))) {
2726 dev->stats.rx_dropped++;
2727 dev->stats.rx_length_errors++;
2728 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2732 rtl8169_rx_csum(skb, desc);
2734 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2735 pci_dma_sync_single_for_device(pdev, addr,
2736 pkt_size, PCI_DMA_FROMDEVICE);
2737 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2739 pci_unmap_single(pdev, addr, pkt_size,
2740 PCI_DMA_FROMDEVICE);
2741 tp->Rx_skbuff[entry] = NULL;
2744 skb_put(skb, pkt_size);
2745 skb->protocol = eth_type_trans(skb, dev);
2747 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2748 rtl8169_rx_skb(skb);
2750 dev->last_rx = jiffies;
2751 dev->stats.rx_bytes += pkt_size;
2752 dev->stats.rx_packets++;
2755 /* Work around for AMD plateform. */
2756 if ((desc->opts2 & 0xfffe000) &&
2757 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2763 count = cur_rx - tp->cur_rx;
2764 tp->cur_rx = cur_rx;
2766 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2767 if (!delta && count && netif_msg_intr(tp))
2768 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2769 tp->dirty_rx += delta;
2772 * FIXME: until there is periodic timer to try and refill the ring,
2773 * a temporary shortage may definitely kill the Rx process.
2774 * - disable the asic to try and avoid an overflow and kick it again
2776 * - how do others driver handle this condition (Uh oh...).
2778 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2779 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2784 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2786 struct net_device *dev = dev_instance;
2787 struct rtl8169_private *tp = netdev_priv(dev);
2788 int boguscnt = max_interrupt_work;
2789 void __iomem *ioaddr = tp->mmio_addr;
2794 status = RTL_R16(IntrStatus);
2796 /* hotplug/major error/no more work/shared irq */
2797 if ((status == 0xFFFF) || !status)
2802 if (unlikely(!netif_running(dev))) {
2803 rtl8169_asic_down(ioaddr);
2807 status &= tp->intr_mask;
2809 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2811 if (!(status & tp->intr_event))
2814 /* Work around for rx fifo overflow */
2815 if (unlikely(status & RxFIFOOver) &&
2816 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2817 netif_stop_queue(dev);
2818 rtl8169_tx_timeout(dev);
2822 if (unlikely(status & SYSErr)) {
2823 rtl8169_pcierr_interrupt(dev);
2827 if (status & LinkChg)
2828 rtl8169_check_link_status(dev, tp, ioaddr);
2830 #ifdef CONFIG_R8169_NAPI
2831 if (status & tp->napi_event) {
2832 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2833 tp->intr_mask = ~tp->napi_event;
2835 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2836 __netif_rx_schedule(dev, &tp->napi);
2837 else if (netif_msg_intr(tp)) {
2838 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2845 if (status & (RxOK | RxOverflow | RxFIFOOver))
2846 rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0);
2849 if (status & (TxOK | TxErr))
2850 rtl8169_tx_interrupt(dev, tp, ioaddr);
2854 } while (boguscnt > 0);
2856 if (boguscnt <= 0) {
2857 if (netif_msg_intr(tp) && net_ratelimit() ) {
2859 "%s: Too much work at interrupt!\n", dev->name);
2861 /* Clear all interrupt sources. */
2862 RTL_W16(IntrStatus, 0xffff);
2865 return IRQ_RETVAL(handled);
2868 #ifdef CONFIG_R8169_NAPI
2869 static int rtl8169_poll(struct napi_struct *napi, int budget)
2871 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2872 struct net_device *dev = tp->dev;
2873 void __iomem *ioaddr = tp->mmio_addr;
2876 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
2877 rtl8169_tx_interrupt(dev, tp, ioaddr);
2879 if (work_done < budget) {
2880 netif_rx_complete(dev, napi);
2881 tp->intr_mask = 0xffff;
2883 * 20040426: the barrier is not strictly required but the
2884 * behavior of the irq handler could be less predictable
2885 * without it. Btw, the lack of flush for the posted pci
2886 * write is safe - FR
2889 RTL_W16(IntrMask, tp->intr_event);
2896 static void rtl8169_down(struct net_device *dev)
2898 struct rtl8169_private *tp = netdev_priv(dev);
2899 void __iomem *ioaddr = tp->mmio_addr;
2900 unsigned int poll_locked = 0;
2901 unsigned int intrmask;
2903 rtl8169_delete_timer(dev);
2905 netif_stop_queue(dev);
2908 spin_lock_irq(&tp->lock);
2910 rtl8169_asic_down(ioaddr);
2912 /* Update the error counts. */
2913 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
2914 RTL_W32(RxMissed, 0);
2916 spin_unlock_irq(&tp->lock);
2918 synchronize_irq(dev->irq);
2921 napi_disable(&tp->napi);
2925 /* Give a racing hard_start_xmit a few cycles to complete. */
2926 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
2929 * And now for the 50k$ question: are IRQ disabled or not ?
2931 * Two paths lead here:
2933 * -> netif_running() is available to sync the current code and the
2934 * IRQ handler. See rtl8169_interrupt for details.
2935 * 2) dev->change_mtu
2936 * -> rtl8169_poll can not be issued again and re-enable the
2937 * interruptions. Let's simply issue the IRQ down sequence again.
2939 * No loop if hotpluged or major error (0xffff).
2941 intrmask = RTL_R16(IntrMask);
2942 if (intrmask && (intrmask != 0xffff))
2945 rtl8169_tx_clear(tp);
2947 rtl8169_rx_clear(tp);
2950 static int rtl8169_close(struct net_device *dev)
2952 struct rtl8169_private *tp = netdev_priv(dev);
2953 struct pci_dev *pdev = tp->pci_dev;
2957 free_irq(dev->irq, dev);
2959 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2961 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2963 tp->TxDescArray = NULL;
2964 tp->RxDescArray = NULL;
2969 static void rtl_set_rx_mode(struct net_device *dev)
2971 struct rtl8169_private *tp = netdev_priv(dev);
2972 void __iomem *ioaddr = tp->mmio_addr;
2973 unsigned long flags;
2974 u32 mc_filter[2]; /* Multicast hash filter */
2978 if (dev->flags & IFF_PROMISC) {
2979 /* Unconditionally log net taps. */
2980 if (netif_msg_link(tp)) {
2981 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2985 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2987 mc_filter[1] = mc_filter[0] = 0xffffffff;
2988 } else if ((dev->mc_count > multicast_filter_limit)
2989 || (dev->flags & IFF_ALLMULTI)) {
2990 /* Too many to filter perfectly -- accept all multicasts. */
2991 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2992 mc_filter[1] = mc_filter[0] = 0xffffffff;
2994 struct dev_mc_list *mclist;
2997 rx_mode = AcceptBroadcast | AcceptMyPhys;
2998 mc_filter[1] = mc_filter[0] = 0;
2999 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3000 i++, mclist = mclist->next) {
3001 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3002 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3003 rx_mode |= AcceptMulticast;
3007 spin_lock_irqsave(&tp->lock, flags);
3009 tmp = rtl8169_rx_config | rx_mode |
3010 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3012 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
3013 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
3014 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3015 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
3016 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
3017 (tp->mac_version == RTL_GIGA_MAC_VER_16) ||
3018 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
3019 mc_filter[0] = 0xffffffff;
3020 mc_filter[1] = 0xffffffff;
3023 RTL_W32(MAR0 + 0, mc_filter[0]);
3024 RTL_W32(MAR0 + 4, mc_filter[1]);
3026 RTL_W32(RxConfig, tmp);
3028 spin_unlock_irqrestore(&tp->lock, flags);
3032 * rtl8169_get_stats - Get rtl8169 read/write statistics
3033 * @dev: The Ethernet Device to get statistics for
3035 * Get TX/RX statistics for rtl8169
3037 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3039 struct rtl8169_private *tp = netdev_priv(dev);
3040 void __iomem *ioaddr = tp->mmio_addr;
3041 unsigned long flags;
3043 if (netif_running(dev)) {
3044 spin_lock_irqsave(&tp->lock, flags);
3045 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3046 RTL_W32(RxMissed, 0);
3047 spin_unlock_irqrestore(&tp->lock, flags);
3055 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3057 struct net_device *dev = pci_get_drvdata(pdev);
3058 struct rtl8169_private *tp = netdev_priv(dev);
3059 void __iomem *ioaddr = tp->mmio_addr;
3061 if (!netif_running(dev))
3062 goto out_pci_suspend;
3064 netif_device_detach(dev);
3065 netif_stop_queue(dev);
3067 spin_lock_irq(&tp->lock);
3069 rtl8169_asic_down(ioaddr);
3071 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3072 RTL_W32(RxMissed, 0);
3074 spin_unlock_irq(&tp->lock);
3077 pci_save_state(pdev);
3078 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3079 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3080 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3085 static int rtl8169_resume(struct pci_dev *pdev)
3087 struct net_device *dev = pci_get_drvdata(pdev);
3089 pci_set_power_state(pdev, PCI_D0);
3090 pci_restore_state(pdev);
3091 pci_enable_wake(pdev, PCI_D0, 0);
3093 if (!netif_running(dev))
3096 netif_device_attach(dev);
3098 rtl8169_schedule_work(dev, rtl8169_reset_task);
3103 #endif /* CONFIG_PM */
3105 static struct pci_driver rtl8169_pci_driver = {
3107 .id_table = rtl8169_pci_tbl,
3108 .probe = rtl8169_init_one,
3109 .remove = __devexit_p(rtl8169_remove_one),
3111 .suspend = rtl8169_suspend,
3112 .resume = rtl8169_resume,
3116 static int __init rtl8169_init_module(void)
3118 return pci_register_driver(&rtl8169_pci_driver);
3121 static void __exit rtl8169_cleanup_module(void)
3123 pci_unregister_driver(&rtl8169_pci_driver);
3126 module_init(rtl8169_init_module);
3127 module_exit(rtl8169_cleanup_module);