2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work = 20;
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit = 32;
61 /* MAC address length */
62 #define MAC_ADDR_LEN 6
64 #define MAX_READ_REQUEST_SHIFT 12
65 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
68 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
69 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
93 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
94 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
95 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
96 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
97 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
98 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
99 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
100 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
101 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
102 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
103 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
104 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
105 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
106 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
107 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
108 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
109 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
110 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
111 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
112 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
113 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
114 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
115 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
116 RTL_GIGA_MAC_VER_24 = 0x18 // 8168CP
119 #define _R(NAME,MAC,MASK) \
120 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
122 static const struct {
125 u32 RxConfigMask; /* Clears the bits supported by this chip */
126 } rtl_chip_info[] = {
127 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
128 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
129 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
130 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
131 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
132 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
133 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
134 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
135 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
136 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
137 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
138 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
139 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
140 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
141 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
143 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
144 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
145 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
146 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
147 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
148 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
150 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880) // PCI-E
160 static void rtl_hw_start_8169(struct net_device *);
161 static void rtl_hw_start_8168(struct net_device *);
162 static void rtl_hw_start_8101(struct net_device *);
164 static struct pci_device_id rtl8169_pci_tbl[] = {
165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
167 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
168 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
169 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
170 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
171 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
172 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
173 { PCI_VENDOR_ID_LINKSYS, 0x1032,
174 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
176 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
180 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
182 static int rx_copybreak = 200;
189 MAC0 = 0, /* Ethernet hardware address. */
191 MAR0 = 8, /* Multicast filter. */
192 CounterAddrLow = 0x10,
193 CounterAddrHigh = 0x14,
194 TxDescStartAddrLow = 0x20,
195 TxDescStartAddrHigh = 0x24,
196 TxHDescStartAddrLow = 0x28,
197 TxHDescStartAddrHigh = 0x2c,
220 RxDescAddrLow = 0xe4,
221 RxDescAddrHigh = 0xe8,
224 FuncEventMask = 0xf4,
225 FuncPresetState = 0xf8,
226 FuncForceEvent = 0xfc,
229 enum rtl8110_registers {
235 enum rtl8168_8101_registers {
238 #define CSIAR_FLAG 0x80000000
239 #define CSIAR_WRITE_CMD 0x80000000
240 #define CSIAR_BYTE_ENABLE 0x0f
241 #define CSIAR_BYTE_ENABLE_SHIFT 12
242 #define CSIAR_ADDR_MASK 0x0fff
245 #define EPHYAR_FLAG 0x80000000
246 #define EPHYAR_WRITE_CMD 0x80000000
247 #define EPHYAR_REG_MASK 0x1f
248 #define EPHYAR_REG_SHIFT 16
249 #define EPHYAR_DATA_MASK 0xffff
251 #define FIX_NAK_1 (1 << 4)
252 #define FIX_NAK_2 (1 << 3)
255 enum rtl_register_content {
256 /* InterruptStatusBits */
260 TxDescUnavail = 0x0080,
282 /* TXPoll register p.5 */
283 HPQ = 0x80, /* Poll cmd on the high prio queue */
284 NPQ = 0x40, /* Poll cmd on the low prio queue */
285 FSWInt = 0x01, /* Forced software interrupt */
289 Cfg9346_Unlock = 0xc0,
294 AcceptBroadcast = 0x08,
295 AcceptMulticast = 0x04,
297 AcceptAllPhys = 0x01,
304 TxInterFrameGapShift = 24,
305 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
307 /* Config1 register p.24 */
310 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
311 Speed_down = (1 << 4),
315 PMEnable = (1 << 0), /* Power Management Enable */
317 /* Config2 register p. 25 */
318 PCI_Clock_66MHz = 0x01,
319 PCI_Clock_33MHz = 0x00,
321 /* Config3 register p.25 */
322 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
323 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
324 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
326 /* Config5 register p.27 */
327 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
328 MWF = (1 << 5), /* Accept Multicast wakeup frame */
329 UWF = (1 << 4), /* Accept Unicast wakeup frame */
330 LanWake = (1 << 1), /* LanWake enable/disable */
331 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
334 TBIReset = 0x80000000,
335 TBILoopback = 0x40000000,
336 TBINwEnable = 0x20000000,
337 TBINwRestart = 0x10000000,
338 TBILinkOk = 0x02000000,
339 TBINwComplete = 0x01000000,
342 EnableBist = (1 << 15), // 8168 8101
343 Mac_dbgo_oe = (1 << 14), // 8168 8101
344 Normal_mode = (1 << 13), // unused
345 Force_half_dup = (1 << 12), // 8168 8101
346 Force_rxflow_en = (1 << 11), // 8168 8101
347 Force_txflow_en = (1 << 10), // 8168 8101
348 Cxpl_dbg_sel = (1 << 9), // 8168 8101
349 ASF = (1 << 8), // 8168 8101
350 PktCntrDisable = (1 << 7), // 8168 8101
351 Mac_dbgo_sel = 0x001c, // 8168
356 INTT_0 = 0x0000, // 8168
357 INTT_1 = 0x0001, // 8168
358 INTT_2 = 0x0002, // 8168
359 INTT_3 = 0x0003, // 8168
361 /* rtl8169_PHYstatus */
372 TBILinkOK = 0x02000000,
374 /* DumpCounterCommand */
378 enum desc_status_bit {
379 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
380 RingEnd = (1 << 30), /* End of descriptor ring */
381 FirstFrag = (1 << 29), /* First segment of a packet */
382 LastFrag = (1 << 28), /* Final segment of a packet */
385 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
386 MSSShift = 16, /* MSS value position */
387 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
388 IPCS = (1 << 18), /* Calculate IP checksum */
389 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
390 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
391 TxVlanTag = (1 << 17), /* Add VLAN tag */
394 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
395 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
397 #define RxProtoUDP (PID1)
398 #define RxProtoTCP (PID0)
399 #define RxProtoIP (PID1 | PID0)
400 #define RxProtoMask RxProtoIP
402 IPFail = (1 << 16), /* IP checksum failed */
403 UDPFail = (1 << 15), /* UDP/IP checksum failed */
404 TCPFail = (1 << 14), /* TCP/IP checksum failed */
405 RxVlanTag = (1 << 16), /* VLAN tag available */
408 #define RsvdMask 0x3fffc000
425 u8 __pad[sizeof(void *) - sizeof(u32)];
429 RTL_FEATURE_WOL = (1 << 0),
430 RTL_FEATURE_MSI = (1 << 1),
431 RTL_FEATURE_GMII = (1 << 2),
434 struct rtl8169_private {
435 void __iomem *mmio_addr; /* memory map physical address */
436 struct pci_dev *pci_dev; /* Index of PCI device */
437 struct net_device *dev;
438 struct napi_struct napi;
439 spinlock_t lock; /* spin lock flag */
443 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
444 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
447 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
448 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
449 dma_addr_t TxPhyAddr;
450 dma_addr_t RxPhyAddr;
451 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
452 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
455 struct timer_list timer;
460 int phy_auto_nego_reg;
461 int phy_1000_ctrl_reg;
462 #ifdef CONFIG_R8169_VLAN
463 struct vlan_group *vlgrp;
465 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
466 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
467 void (*phy_reset_enable)(void __iomem *);
468 void (*hw_start)(struct net_device *);
469 unsigned int (*phy_reset_pending)(void __iomem *);
470 unsigned int (*link_ok)(void __iomem *);
472 struct delayed_work task;
475 struct mii_if_info mii;
478 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
479 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
480 module_param(rx_copybreak, int, 0);
481 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
482 module_param(use_dac, int, 0);
483 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
484 module_param_named(debug, debug.msg_enable, int, 0);
485 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
486 MODULE_LICENSE("GPL");
487 MODULE_VERSION(RTL8169_VERSION);
489 static int rtl8169_open(struct net_device *dev);
490 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
491 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
492 static int rtl8169_init_ring(struct net_device *dev);
493 static void rtl_hw_start(struct net_device *dev);
494 static int rtl8169_close(struct net_device *dev);
495 static void rtl_set_rx_mode(struct net_device *dev);
496 static void rtl8169_tx_timeout(struct net_device *dev);
497 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
498 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
499 void __iomem *, u32 budget);
500 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
501 static void rtl8169_down(struct net_device *dev);
502 static void rtl8169_rx_clear(struct rtl8169_private *tp);
503 static int rtl8169_poll(struct napi_struct *napi, int budget);
505 static const unsigned int rtl8169_rx_config =
506 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
508 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
512 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
514 for (i = 20; i > 0; i--) {
516 * Check if the RTL8169 has completed writing to the specified
519 if (!(RTL_R32(PHYAR) & 0x80000000))
525 static int mdio_read(void __iomem *ioaddr, int reg_addr)
529 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
531 for (i = 20; i > 0; i--) {
533 * Check if the RTL8169 has completed retrieving data from
534 * the specified MII register.
536 if (RTL_R32(PHYAR) & 0x80000000) {
537 value = RTL_R32(PHYAR) & 0xffff;
545 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
547 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
550 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
553 struct rtl8169_private *tp = netdev_priv(dev);
554 void __iomem *ioaddr = tp->mmio_addr;
556 mdio_write(ioaddr, location, val);
559 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
561 struct rtl8169_private *tp = netdev_priv(dev);
562 void __iomem *ioaddr = tp->mmio_addr;
564 return mdio_read(ioaddr, location);
567 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
571 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
572 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
574 for (i = 0; i < 100; i++) {
575 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
581 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
586 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
588 for (i = 0; i < 100; i++) {
589 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
590 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
599 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
603 RTL_W32(CSIDR, value);
604 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
605 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
607 for (i = 0; i < 100; i++) {
608 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
614 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
619 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
620 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
622 for (i = 0; i < 100; i++) {
623 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
624 value = RTL_R32(CSIDR);
633 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
635 RTL_W16(IntrMask, 0x0000);
637 RTL_W16(IntrStatus, 0xffff);
640 static void rtl8169_asic_down(void __iomem *ioaddr)
642 RTL_W8(ChipCmd, 0x00);
643 rtl8169_irq_mask_and_ack(ioaddr);
647 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
649 return RTL_R32(TBICSR) & TBIReset;
652 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
654 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
657 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
659 return RTL_R32(TBICSR) & TBILinkOk;
662 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
664 return RTL_R8(PHYstatus) & LinkStatus;
667 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
669 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
672 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
676 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
677 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
680 static void rtl8169_check_link_status(struct net_device *dev,
681 struct rtl8169_private *tp,
682 void __iomem *ioaddr)
686 spin_lock_irqsave(&tp->lock, flags);
687 if (tp->link_ok(ioaddr)) {
688 netif_carrier_on(dev);
689 if (netif_msg_ifup(tp))
690 printk(KERN_INFO PFX "%s: link up\n", dev->name);
692 if (netif_msg_ifdown(tp))
693 printk(KERN_INFO PFX "%s: link down\n", dev->name);
694 netif_carrier_off(dev);
696 spin_unlock_irqrestore(&tp->lock, flags);
699 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
701 struct rtl8169_private *tp = netdev_priv(dev);
702 void __iomem *ioaddr = tp->mmio_addr;
707 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
708 wol->supported = WAKE_ANY;
710 spin_lock_irq(&tp->lock);
712 options = RTL_R8(Config1);
713 if (!(options & PMEnable))
716 options = RTL_R8(Config3);
717 if (options & LinkUp)
718 wol->wolopts |= WAKE_PHY;
719 if (options & MagicPacket)
720 wol->wolopts |= WAKE_MAGIC;
722 options = RTL_R8(Config5);
724 wol->wolopts |= WAKE_UCAST;
726 wol->wolopts |= WAKE_BCAST;
728 wol->wolopts |= WAKE_MCAST;
731 spin_unlock_irq(&tp->lock);
734 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
736 struct rtl8169_private *tp = netdev_priv(dev);
737 void __iomem *ioaddr = tp->mmio_addr;
744 { WAKE_ANY, Config1, PMEnable },
745 { WAKE_PHY, Config3, LinkUp },
746 { WAKE_MAGIC, Config3, MagicPacket },
747 { WAKE_UCAST, Config5, UWF },
748 { WAKE_BCAST, Config5, BWF },
749 { WAKE_MCAST, Config5, MWF },
750 { WAKE_ANY, Config5, LanWake }
753 spin_lock_irq(&tp->lock);
755 RTL_W8(Cfg9346, Cfg9346_Unlock);
757 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
758 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
759 if (wol->wolopts & cfg[i].opt)
760 options |= cfg[i].mask;
761 RTL_W8(cfg[i].reg, options);
764 RTL_W8(Cfg9346, Cfg9346_Lock);
767 tp->features |= RTL_FEATURE_WOL;
769 tp->features &= ~RTL_FEATURE_WOL;
770 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
772 spin_unlock_irq(&tp->lock);
777 static void rtl8169_get_drvinfo(struct net_device *dev,
778 struct ethtool_drvinfo *info)
780 struct rtl8169_private *tp = netdev_priv(dev);
782 strcpy(info->driver, MODULENAME);
783 strcpy(info->version, RTL8169_VERSION);
784 strcpy(info->bus_info, pci_name(tp->pci_dev));
787 static int rtl8169_get_regs_len(struct net_device *dev)
789 return R8169_REGS_SIZE;
792 static int rtl8169_set_speed_tbi(struct net_device *dev,
793 u8 autoneg, u16 speed, u8 duplex)
795 struct rtl8169_private *tp = netdev_priv(dev);
796 void __iomem *ioaddr = tp->mmio_addr;
800 reg = RTL_R32(TBICSR);
801 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
802 (duplex == DUPLEX_FULL)) {
803 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
804 } else if (autoneg == AUTONEG_ENABLE)
805 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
807 if (netif_msg_link(tp)) {
808 printk(KERN_WARNING "%s: "
809 "incorrect speed setting refused in TBI mode\n",
818 static int rtl8169_set_speed_xmii(struct net_device *dev,
819 u8 autoneg, u16 speed, u8 duplex)
821 struct rtl8169_private *tp = netdev_priv(dev);
822 void __iomem *ioaddr = tp->mmio_addr;
823 int auto_nego, giga_ctrl;
825 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
826 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
827 ADVERTISE_100HALF | ADVERTISE_100FULL);
828 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
829 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
831 if (autoneg == AUTONEG_ENABLE) {
832 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
833 ADVERTISE_100HALF | ADVERTISE_100FULL);
834 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
836 if (speed == SPEED_10)
837 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
838 else if (speed == SPEED_100)
839 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
840 else if (speed == SPEED_1000)
841 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
843 if (duplex == DUPLEX_HALF)
844 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
846 if (duplex == DUPLEX_FULL)
847 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
849 /* This tweak comes straight from Realtek's driver. */
850 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
851 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
852 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
853 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
857 /* The 8100e/8101e/8102e do Fast Ethernet only. */
858 if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
859 (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
860 (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
861 (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
862 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
863 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
864 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
865 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
866 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
867 netif_msg_link(tp)) {
868 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
871 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
874 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
876 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
877 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
878 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
881 * Vendor specific (0x1f) and reserved (0x0e) MII registers.
883 mdio_write(ioaddr, 0x1f, 0x0000);
884 mdio_write(ioaddr, 0x0e, 0x0000);
887 tp->phy_auto_nego_reg = auto_nego;
888 tp->phy_1000_ctrl_reg = giga_ctrl;
890 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
891 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
892 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
896 static int rtl8169_set_speed(struct net_device *dev,
897 u8 autoneg, u16 speed, u8 duplex)
899 struct rtl8169_private *tp = netdev_priv(dev);
902 ret = tp->set_speed(dev, autoneg, speed, duplex);
904 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
905 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
910 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
912 struct rtl8169_private *tp = netdev_priv(dev);
916 spin_lock_irqsave(&tp->lock, flags);
917 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
918 spin_unlock_irqrestore(&tp->lock, flags);
923 static u32 rtl8169_get_rx_csum(struct net_device *dev)
925 struct rtl8169_private *tp = netdev_priv(dev);
927 return tp->cp_cmd & RxChkSum;
930 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
932 struct rtl8169_private *tp = netdev_priv(dev);
933 void __iomem *ioaddr = tp->mmio_addr;
936 spin_lock_irqsave(&tp->lock, flags);
939 tp->cp_cmd |= RxChkSum;
941 tp->cp_cmd &= ~RxChkSum;
943 RTL_W16(CPlusCmd, tp->cp_cmd);
946 spin_unlock_irqrestore(&tp->lock, flags);
951 #ifdef CONFIG_R8169_VLAN
953 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
956 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
957 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
960 static void rtl8169_vlan_rx_register(struct net_device *dev,
961 struct vlan_group *grp)
963 struct rtl8169_private *tp = netdev_priv(dev);
964 void __iomem *ioaddr = tp->mmio_addr;
967 spin_lock_irqsave(&tp->lock, flags);
970 tp->cp_cmd |= RxVlan;
972 tp->cp_cmd &= ~RxVlan;
973 RTL_W16(CPlusCmd, tp->cp_cmd);
975 spin_unlock_irqrestore(&tp->lock, flags);
978 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
981 u32 opts2 = le32_to_cpu(desc->opts2);
982 struct vlan_group *vlgrp = tp->vlgrp;
985 if (vlgrp && (opts2 & RxVlanTag)) {
986 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
994 #else /* !CONFIG_R8169_VLAN */
996 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1002 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1003 struct sk_buff *skb)
1010 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1012 struct rtl8169_private *tp = netdev_priv(dev);
1013 void __iomem *ioaddr = tp->mmio_addr;
1017 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1018 cmd->port = PORT_FIBRE;
1019 cmd->transceiver = XCVR_INTERNAL;
1021 status = RTL_R32(TBICSR);
1022 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1023 cmd->autoneg = !!(status & TBINwEnable);
1025 cmd->speed = SPEED_1000;
1026 cmd->duplex = DUPLEX_FULL; /* Always set */
1031 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1033 struct rtl8169_private *tp = netdev_priv(dev);
1035 return mii_ethtool_gset(&tp->mii, cmd);
1038 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1040 struct rtl8169_private *tp = netdev_priv(dev);
1041 unsigned long flags;
1044 spin_lock_irqsave(&tp->lock, flags);
1046 rc = tp->get_settings(dev, cmd);
1048 spin_unlock_irqrestore(&tp->lock, flags);
1052 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1055 struct rtl8169_private *tp = netdev_priv(dev);
1056 unsigned long flags;
1058 if (regs->len > R8169_REGS_SIZE)
1059 regs->len = R8169_REGS_SIZE;
1061 spin_lock_irqsave(&tp->lock, flags);
1062 memcpy_fromio(p, tp->mmio_addr, regs->len);
1063 spin_unlock_irqrestore(&tp->lock, flags);
1066 static u32 rtl8169_get_msglevel(struct net_device *dev)
1068 struct rtl8169_private *tp = netdev_priv(dev);
1070 return tp->msg_enable;
1073 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1075 struct rtl8169_private *tp = netdev_priv(dev);
1077 tp->msg_enable = value;
1080 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1087 "tx_single_collisions",
1088 "tx_multi_collisions",
1096 struct rtl8169_counters {
1102 __le16 align_errors;
1103 __le32 tx_one_collision;
1104 __le32 tx_multi_collision;
1106 __le64 rx_broadcast;
1107 __le32 rx_multicast;
1112 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1116 return ARRAY_SIZE(rtl8169_gstrings);
1122 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1123 struct ethtool_stats *stats, u64 *data)
1125 struct rtl8169_private *tp = netdev_priv(dev);
1126 void __iomem *ioaddr = tp->mmio_addr;
1127 struct rtl8169_counters *counters;
1133 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1137 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1138 cmd = (u64)paddr & DMA_32BIT_MASK;
1139 RTL_W32(CounterAddrLow, cmd);
1140 RTL_W32(CounterAddrLow, cmd | CounterDump);
1142 while (RTL_R32(CounterAddrLow) & CounterDump) {
1143 if (msleep_interruptible(1))
1147 RTL_W32(CounterAddrLow, 0);
1148 RTL_W32(CounterAddrHigh, 0);
1150 data[0] = le64_to_cpu(counters->tx_packets);
1151 data[1] = le64_to_cpu(counters->rx_packets);
1152 data[2] = le64_to_cpu(counters->tx_errors);
1153 data[3] = le32_to_cpu(counters->rx_errors);
1154 data[4] = le16_to_cpu(counters->rx_missed);
1155 data[5] = le16_to_cpu(counters->align_errors);
1156 data[6] = le32_to_cpu(counters->tx_one_collision);
1157 data[7] = le32_to_cpu(counters->tx_multi_collision);
1158 data[8] = le64_to_cpu(counters->rx_unicast);
1159 data[9] = le64_to_cpu(counters->rx_broadcast);
1160 data[10] = le32_to_cpu(counters->rx_multicast);
1161 data[11] = le16_to_cpu(counters->tx_aborted);
1162 data[12] = le16_to_cpu(counters->tx_underun);
1164 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1167 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1171 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1176 static const struct ethtool_ops rtl8169_ethtool_ops = {
1177 .get_drvinfo = rtl8169_get_drvinfo,
1178 .get_regs_len = rtl8169_get_regs_len,
1179 .get_link = ethtool_op_get_link,
1180 .get_settings = rtl8169_get_settings,
1181 .set_settings = rtl8169_set_settings,
1182 .get_msglevel = rtl8169_get_msglevel,
1183 .set_msglevel = rtl8169_set_msglevel,
1184 .get_rx_csum = rtl8169_get_rx_csum,
1185 .set_rx_csum = rtl8169_set_rx_csum,
1186 .set_tx_csum = ethtool_op_set_tx_csum,
1187 .set_sg = ethtool_op_set_sg,
1188 .set_tso = ethtool_op_set_tso,
1189 .get_regs = rtl8169_get_regs,
1190 .get_wol = rtl8169_get_wol,
1191 .set_wol = rtl8169_set_wol,
1192 .get_strings = rtl8169_get_strings,
1193 .get_sset_count = rtl8169_get_sset_count,
1194 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1197 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1198 int bitnum, int bitval)
1202 val = mdio_read(ioaddr, reg);
1203 val = (bitval == 1) ?
1204 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1205 mdio_write(ioaddr, reg, val & 0xffff);
1208 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1209 void __iomem *ioaddr)
1212 * The driver currently handles the 8168Bf and the 8168Be identically
1213 * but they can be identified more specifically through the test below
1216 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1218 * Same thing for the 8101Eb and the 8101Ec:
1220 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1228 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
1229 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1230 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1231 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1232 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1233 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1234 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1235 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1236 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1239 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1240 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1241 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1242 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1245 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1246 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1247 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1248 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1249 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1250 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1251 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1252 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1253 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1254 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1255 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1256 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1257 /* FIXME: where did these entries come from ? -- FR */
1258 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1259 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1262 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1263 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1264 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1265 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1266 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1267 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1269 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1273 reg = RTL_R32(TxConfig);
1274 while ((reg & p->mask) != p->val)
1276 tp->mac_version = p->mac_version;
1278 if (p->mask == 0x00000000) {
1279 struct pci_dev *pdev = tp->pci_dev;
1281 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1285 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1287 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1295 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1298 mdio_write(ioaddr, regs->reg, regs->val);
1303 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1306 u16 regs[5]; /* Beware of bit-sign propagation */
1307 } phy_magic[5] = { {
1308 { 0x0000, //w 4 15 12 0
1309 0x00a1, //w 3 15 0 00a1
1310 0x0008, //w 2 15 0 0008
1311 0x1020, //w 1 15 0 1020
1312 0x1000 } },{ //w 0 15 0 1000
1313 { 0x7000, //w 4 15 12 7
1314 0xff41, //w 3 15 0 ff41
1315 0xde60, //w 2 15 0 de60
1316 0x0140, //w 1 15 0 0140
1317 0x0077 } },{ //w 0 15 0 0077
1318 { 0xa000, //w 4 15 12 a
1319 0xdf01, //w 3 15 0 df01
1320 0xdf20, //w 2 15 0 df20
1321 0xff95, //w 1 15 0 ff95
1322 0xfa00 } },{ //w 0 15 0 fa00
1323 { 0xb000, //w 4 15 12 b
1324 0xff41, //w 3 15 0 ff41
1325 0xde20, //w 2 15 0 de20
1326 0x0140, //w 1 15 0 0140
1327 0x00bb } },{ //w 0 15 0 00bb
1328 { 0xf000, //w 4 15 12 f
1329 0xdf01, //w 3 15 0 df01
1330 0xdf20, //w 2 15 0 df20
1331 0xff95, //w 1 15 0 ff95
1332 0xbf00 } //w 0 15 0 bf00
1337 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1338 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1339 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1340 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1342 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1345 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1346 mdio_write(ioaddr, pos, val);
1348 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1349 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1350 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1352 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1355 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1357 struct phy_reg phy_reg_init[] = {
1363 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1366 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1368 struct phy_reg phy_reg_init[] = {
1373 mdio_write(ioaddr, 0x1f, 0x0001);
1374 mdio_patch(ioaddr, 0x16, 1 << 0);
1376 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1379 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1381 struct phy_reg phy_reg_init[] = {
1387 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1390 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1392 struct phy_reg phy_reg_init[] = {
1400 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1403 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1405 struct phy_reg phy_reg_init[] = {
1411 mdio_write(ioaddr, 0x1f, 0x0000);
1412 mdio_patch(ioaddr, 0x14, 1 << 5);
1413 mdio_patch(ioaddr, 0x0d, 1 << 5);
1415 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1418 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1420 struct phy_reg phy_reg_init[] = {
1440 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1442 mdio_patch(ioaddr, 0x14, 1 << 5);
1443 mdio_patch(ioaddr, 0x0d, 1 << 5);
1444 mdio_write(ioaddr, 0x1f, 0x0000);
1447 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1449 struct phy_reg phy_reg_init[] = {
1467 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1469 mdio_patch(ioaddr, 0x16, 1 << 0);
1470 mdio_patch(ioaddr, 0x14, 1 << 5);
1471 mdio_patch(ioaddr, 0x0d, 1 << 5);
1472 mdio_write(ioaddr, 0x1f, 0x0000);
1475 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1477 struct phy_reg phy_reg_init[] = {
1489 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1491 mdio_patch(ioaddr, 0x16, 1 << 0);
1492 mdio_patch(ioaddr, 0x14, 1 << 5);
1493 mdio_patch(ioaddr, 0x0d, 1 << 5);
1494 mdio_write(ioaddr, 0x1f, 0x0000);
1497 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1499 rtl8168c_3_hw_phy_config(ioaddr);
1502 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1504 struct phy_reg phy_reg_init[] = {
1511 mdio_write(ioaddr, 0x1f, 0x0000);
1512 mdio_patch(ioaddr, 0x11, 1 << 12);
1513 mdio_patch(ioaddr, 0x19, 1 << 13);
1515 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1518 static void rtl_hw_phy_config(struct net_device *dev)
1520 struct rtl8169_private *tp = netdev_priv(dev);
1521 void __iomem *ioaddr = tp->mmio_addr;
1523 rtl8169_print_mac_version(tp);
1525 switch (tp->mac_version) {
1526 case RTL_GIGA_MAC_VER_01:
1528 case RTL_GIGA_MAC_VER_02:
1529 case RTL_GIGA_MAC_VER_03:
1530 rtl8169s_hw_phy_config(ioaddr);
1532 case RTL_GIGA_MAC_VER_04:
1533 rtl8169sb_hw_phy_config(ioaddr);
1535 case RTL_GIGA_MAC_VER_07:
1536 case RTL_GIGA_MAC_VER_08:
1537 case RTL_GIGA_MAC_VER_09:
1538 rtl8102e_hw_phy_config(ioaddr);
1540 case RTL_GIGA_MAC_VER_11:
1541 rtl8168bb_hw_phy_config(ioaddr);
1543 case RTL_GIGA_MAC_VER_12:
1544 rtl8168bef_hw_phy_config(ioaddr);
1546 case RTL_GIGA_MAC_VER_17:
1547 rtl8168bef_hw_phy_config(ioaddr);
1549 case RTL_GIGA_MAC_VER_18:
1550 rtl8168cp_1_hw_phy_config(ioaddr);
1552 case RTL_GIGA_MAC_VER_19:
1553 rtl8168c_1_hw_phy_config(ioaddr);
1555 case RTL_GIGA_MAC_VER_20:
1556 rtl8168c_2_hw_phy_config(ioaddr);
1558 case RTL_GIGA_MAC_VER_21:
1559 rtl8168c_3_hw_phy_config(ioaddr);
1561 case RTL_GIGA_MAC_VER_22:
1562 rtl8168c_4_hw_phy_config(ioaddr);
1564 case RTL_GIGA_MAC_VER_23:
1565 case RTL_GIGA_MAC_VER_24:
1566 rtl8168cp_2_hw_phy_config(ioaddr);
1574 static void rtl8169_phy_timer(unsigned long __opaque)
1576 struct net_device *dev = (struct net_device *)__opaque;
1577 struct rtl8169_private *tp = netdev_priv(dev);
1578 struct timer_list *timer = &tp->timer;
1579 void __iomem *ioaddr = tp->mmio_addr;
1580 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1582 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1584 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1587 spin_lock_irq(&tp->lock);
1589 if (tp->phy_reset_pending(ioaddr)) {
1591 * A busy loop could burn quite a few cycles on nowadays CPU.
1592 * Let's delay the execution of the timer for a few ticks.
1598 if (tp->link_ok(ioaddr))
1601 if (netif_msg_link(tp))
1602 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1604 tp->phy_reset_enable(ioaddr);
1607 mod_timer(timer, jiffies + timeout);
1609 spin_unlock_irq(&tp->lock);
1612 static inline void rtl8169_delete_timer(struct net_device *dev)
1614 struct rtl8169_private *tp = netdev_priv(dev);
1615 struct timer_list *timer = &tp->timer;
1617 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1620 del_timer_sync(timer);
1623 static inline void rtl8169_request_timer(struct net_device *dev)
1625 struct rtl8169_private *tp = netdev_priv(dev);
1626 struct timer_list *timer = &tp->timer;
1628 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1631 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1634 #ifdef CONFIG_NET_POLL_CONTROLLER
1636 * Polling 'interrupt' - used by things like netconsole to send skbs
1637 * without having to re-enable interrupts. It's not called while
1638 * the interrupt routine is executing.
1640 static void rtl8169_netpoll(struct net_device *dev)
1642 struct rtl8169_private *tp = netdev_priv(dev);
1643 struct pci_dev *pdev = tp->pci_dev;
1645 disable_irq(pdev->irq);
1646 rtl8169_interrupt(pdev->irq, dev);
1647 enable_irq(pdev->irq);
1651 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1652 void __iomem *ioaddr)
1655 pci_release_regions(pdev);
1656 pci_disable_device(pdev);
1660 static void rtl8169_phy_reset(struct net_device *dev,
1661 struct rtl8169_private *tp)
1663 void __iomem *ioaddr = tp->mmio_addr;
1666 tp->phy_reset_enable(ioaddr);
1667 for (i = 0; i < 100; i++) {
1668 if (!tp->phy_reset_pending(ioaddr))
1672 if (netif_msg_link(tp))
1673 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1676 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1678 void __iomem *ioaddr = tp->mmio_addr;
1680 rtl_hw_phy_config(dev);
1682 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1683 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1687 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1689 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1690 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1692 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1693 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1695 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1696 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1699 rtl8169_phy_reset(dev, tp);
1702 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1703 * only 8101. Don't panic.
1705 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1707 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1708 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1711 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1713 void __iomem *ioaddr = tp->mmio_addr;
1717 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1718 high = addr[4] | (addr[5] << 8);
1720 spin_lock_irq(&tp->lock);
1722 RTL_W8(Cfg9346, Cfg9346_Unlock);
1724 RTL_W32(MAC4, high);
1725 RTL_W8(Cfg9346, Cfg9346_Lock);
1727 spin_unlock_irq(&tp->lock);
1730 static int rtl_set_mac_address(struct net_device *dev, void *p)
1732 struct rtl8169_private *tp = netdev_priv(dev);
1733 struct sockaddr *addr = p;
1735 if (!is_valid_ether_addr(addr->sa_data))
1736 return -EADDRNOTAVAIL;
1738 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1740 rtl_rar_set(tp, dev->dev_addr);
1745 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1747 struct rtl8169_private *tp = netdev_priv(dev);
1748 struct mii_ioctl_data *data = if_mii(ifr);
1750 if (!netif_running(dev))
1755 data->phy_id = 32; /* Internal PHY */
1759 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1763 if (!capable(CAP_NET_ADMIN))
1765 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1771 static const struct rtl_cfg_info {
1772 void (*hw_start)(struct net_device *);
1773 unsigned int region;
1778 } rtl_cfg_infos [] = {
1780 .hw_start = rtl_hw_start_8169,
1783 .intr_event = SYSErr | LinkChg | RxOverflow |
1784 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1785 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1786 .features = RTL_FEATURE_GMII
1789 .hw_start = rtl_hw_start_8168,
1792 .intr_event = SYSErr | LinkChg | RxOverflow |
1793 TxErr | TxOK | RxOK | RxErr,
1794 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1795 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1798 .hw_start = rtl_hw_start_8101,
1801 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1802 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1803 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1804 .features = RTL_FEATURE_MSI
1808 /* Cfg9346_Unlock assumed. */
1809 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1810 const struct rtl_cfg_info *cfg)
1815 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1816 if (cfg->features & RTL_FEATURE_MSI) {
1817 if (pci_enable_msi(pdev)) {
1818 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1821 msi = RTL_FEATURE_MSI;
1824 RTL_W8(Config2, cfg2);
1828 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1830 if (tp->features & RTL_FEATURE_MSI) {
1831 pci_disable_msi(pdev);
1832 tp->features &= ~RTL_FEATURE_MSI;
1836 static int rtl_eeprom_read(struct pci_dev *pdev, int cap, int addr, __le32 *val)
1838 int ret, count = 100;
1842 ret = pci_write_config_word(pdev, cap + PCI_VPD_ADDR, addr);
1848 ret = pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &status);
1851 } while (!(status & PCI_VPD_ADDR_F) && --count);
1853 if (!(status & PCI_VPD_ADDR_F))
1856 ret = pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &value);
1860 *val = cpu_to_le32(value);
1865 static void rtl_init_mac_address(struct rtl8169_private *tp,
1866 void __iomem *ioaddr)
1868 struct pci_dev *pdev = tp->pci_dev;
1872 DECLARE_MAC_BUF(buf);
1874 cfg1 = RTL_R8(Config1);
1875 if (!(cfg1 & VPD)) {
1876 dprintk("VPD access not enabled, enabling\n");
1877 RTL_W8(Cfg9346, Cfg9346_Unlock);
1878 RTL_W8(Config1, cfg1 | VPD);
1879 RTL_W8(Cfg9346, Cfg9346_Lock);
1882 vpd_cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
1886 /* MAC address is stored in EEPROM at offset 0x0e
1887 * Realtek says: "The VPD address does not have to be a DWORD-aligned
1888 * address as defined in the PCI 2.2 Specifications, but the VPD data
1889 * is always consecutive 4-byte data starting from the VPD address
1892 if (rtl_eeprom_read(pdev, vpd_cap, 0x000e, (__le32*)&mac[0]) < 0 ||
1893 rtl_eeprom_read(pdev, vpd_cap, 0x0012, (__le32*)&mac[4]) < 0) {
1894 dprintk("Reading MAC address from EEPROM failed\n");
1898 dprintk("MAC address found in EEPROM: %s\n", print_mac(buf, mac));
1900 /* Write MAC address */
1901 rtl_rar_set(tp, mac);
1904 static int __devinit
1905 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1907 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1908 const unsigned int region = cfg->region;
1909 struct rtl8169_private *tp;
1910 struct mii_if_info *mii;
1911 struct net_device *dev;
1912 void __iomem *ioaddr;
1916 if (netif_msg_drv(&debug)) {
1917 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1918 MODULENAME, RTL8169_VERSION);
1921 dev = alloc_etherdev(sizeof (*tp));
1923 if (netif_msg_drv(&debug))
1924 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1929 SET_NETDEV_DEV(dev, &pdev->dev);
1930 tp = netdev_priv(dev);
1933 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1937 mii->mdio_read = rtl_mdio_read;
1938 mii->mdio_write = rtl_mdio_write;
1939 mii->phy_id_mask = 0x1f;
1940 mii->reg_num_mask = 0x1f;
1941 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1943 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1944 rc = pci_enable_device(pdev);
1946 if (netif_msg_probe(tp))
1947 dev_err(&pdev->dev, "enable failure\n");
1948 goto err_out_free_dev_1;
1951 rc = pci_set_mwi(pdev);
1953 goto err_out_disable_2;
1955 /* make sure PCI base addr 1 is MMIO */
1956 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1957 if (netif_msg_probe(tp)) {
1959 "region #%d not an MMIO resource, aborting\n",
1966 /* check for weird/broken PCI region reporting */
1967 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1968 if (netif_msg_probe(tp)) {
1970 "Invalid PCI region size(s), aborting\n");
1976 rc = pci_request_regions(pdev, MODULENAME);
1978 if (netif_msg_probe(tp))
1979 dev_err(&pdev->dev, "could not request regions.\n");
1983 tp->cp_cmd = PCIMulRW | RxChkSum;
1985 if ((sizeof(dma_addr_t) > 4) &&
1986 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1987 tp->cp_cmd |= PCIDAC;
1988 dev->features |= NETIF_F_HIGHDMA;
1990 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1992 if (netif_msg_probe(tp)) {
1994 "DMA configuration failed.\n");
1996 goto err_out_free_res_4;
2000 pci_set_master(pdev);
2002 /* ioremap MMIO region */
2003 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2005 if (netif_msg_probe(tp))
2006 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
2008 goto err_out_free_res_4;
2011 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2012 if (!tp->pcie_cap && netif_msg_probe(tp))
2013 dev_info(&pdev->dev, "no PCI Express capability\n");
2015 /* Unneeded ? Don't mess with Mrs. Murphy. */
2016 rtl8169_irq_mask_and_ack(ioaddr);
2018 /* Soft reset the chip. */
2019 RTL_W8(ChipCmd, CmdReset);
2021 /* Check that the chip has finished the reset. */
2022 for (i = 0; i < 100; i++) {
2023 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2025 msleep_interruptible(1);
2028 /* Identify chip attached to board */
2029 rtl8169_get_mac_version(tp, ioaddr);
2031 rtl8169_print_mac_version(tp);
2033 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2034 if (tp->mac_version == rtl_chip_info[i].mac_version)
2037 if (i == ARRAY_SIZE(rtl_chip_info)) {
2038 /* Unknown chip: assume array element #0, original RTL-8169 */
2039 if (netif_msg_probe(tp)) {
2040 dev_printk(KERN_DEBUG, &pdev->dev,
2041 "unknown chip version, assuming %s\n",
2042 rtl_chip_info[0].name);
2048 RTL_W8(Cfg9346, Cfg9346_Unlock);
2049 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2050 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2051 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2052 tp->features |= RTL_FEATURE_WOL;
2053 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2054 tp->features |= RTL_FEATURE_WOL;
2055 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2056 RTL_W8(Cfg9346, Cfg9346_Lock);
2058 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2059 (RTL_R8(PHYstatus) & TBI_Enable)) {
2060 tp->set_speed = rtl8169_set_speed_tbi;
2061 tp->get_settings = rtl8169_gset_tbi;
2062 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2063 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2064 tp->link_ok = rtl8169_tbi_link_ok;
2066 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2068 tp->set_speed = rtl8169_set_speed_xmii;
2069 tp->get_settings = rtl8169_gset_xmii;
2070 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2071 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2072 tp->link_ok = rtl8169_xmii_link_ok;
2074 dev->do_ioctl = rtl8169_ioctl;
2077 spin_lock_init(&tp->lock);
2079 rtl_init_mac_address(tp, ioaddr);
2081 /* Get MAC address */
2082 for (i = 0; i < MAC_ADDR_LEN; i++)
2083 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2084 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2086 dev->open = rtl8169_open;
2087 dev->hard_start_xmit = rtl8169_start_xmit;
2088 dev->get_stats = rtl8169_get_stats;
2089 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2090 dev->stop = rtl8169_close;
2091 dev->tx_timeout = rtl8169_tx_timeout;
2092 dev->set_multicast_list = rtl_set_rx_mode;
2093 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2094 dev->irq = pdev->irq;
2095 dev->base_addr = (unsigned long) ioaddr;
2096 dev->change_mtu = rtl8169_change_mtu;
2097 dev->set_mac_address = rtl_set_mac_address;
2099 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2101 #ifdef CONFIG_R8169_VLAN
2102 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2103 dev->vlan_rx_register = rtl8169_vlan_rx_register;
2106 #ifdef CONFIG_NET_POLL_CONTROLLER
2107 dev->poll_controller = rtl8169_netpoll;
2110 tp->intr_mask = 0xffff;
2111 tp->mmio_addr = ioaddr;
2112 tp->align = cfg->align;
2113 tp->hw_start = cfg->hw_start;
2114 tp->intr_event = cfg->intr_event;
2115 tp->napi_event = cfg->napi_event;
2117 init_timer(&tp->timer);
2118 tp->timer.data = (unsigned long) dev;
2119 tp->timer.function = rtl8169_phy_timer;
2121 rc = register_netdev(dev);
2125 pci_set_drvdata(pdev, dev);
2127 if (netif_msg_probe(tp)) {
2128 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2130 printk(KERN_INFO "%s: %s at 0x%lx, "
2131 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2132 "XID %08x IRQ %d\n",
2134 rtl_chip_info[tp->chipset].name,
2136 dev->dev_addr[0], dev->dev_addr[1],
2137 dev->dev_addr[2], dev->dev_addr[3],
2138 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2141 rtl8169_init_phy(dev, tp);
2142 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2148 rtl_disable_msi(pdev, tp);
2151 pci_release_regions(pdev);
2153 pci_clear_mwi(pdev);
2155 pci_disable_device(pdev);
2161 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2163 struct net_device *dev = pci_get_drvdata(pdev);
2164 struct rtl8169_private *tp = netdev_priv(dev);
2166 flush_scheduled_work();
2168 unregister_netdev(dev);
2169 rtl_disable_msi(pdev, tp);
2170 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2171 pci_set_drvdata(pdev, NULL);
2174 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2175 struct net_device *dev)
2177 unsigned int mtu = dev->mtu;
2179 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2182 static int rtl8169_open(struct net_device *dev)
2184 struct rtl8169_private *tp = netdev_priv(dev);
2185 struct pci_dev *pdev = tp->pci_dev;
2186 int retval = -ENOMEM;
2189 rtl8169_set_rxbufsize(tp, dev);
2192 * Rx and Tx desscriptors needs 256 bytes alignment.
2193 * pci_alloc_consistent provides more.
2195 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2197 if (!tp->TxDescArray)
2200 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2202 if (!tp->RxDescArray)
2205 retval = rtl8169_init_ring(dev);
2209 INIT_DELAYED_WORK(&tp->task, NULL);
2213 retval = request_irq(dev->irq, rtl8169_interrupt,
2214 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2217 goto err_release_ring_2;
2219 napi_enable(&tp->napi);
2223 rtl8169_request_timer(dev);
2225 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2230 rtl8169_rx_clear(tp);
2232 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2235 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2240 static void rtl8169_hw_reset(void __iomem *ioaddr)
2242 /* Disable interrupts */
2243 rtl8169_irq_mask_and_ack(ioaddr);
2245 /* Reset the chipset */
2246 RTL_W8(ChipCmd, CmdReset);
2252 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2254 void __iomem *ioaddr = tp->mmio_addr;
2255 u32 cfg = rtl8169_rx_config;
2257 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2258 RTL_W32(RxConfig, cfg);
2260 /* Set DMA burst size and Interframe Gap Time */
2261 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2262 (InterFrameGap << TxInterFrameGapShift));
2265 static void rtl_hw_start(struct net_device *dev)
2267 struct rtl8169_private *tp = netdev_priv(dev);
2268 void __iomem *ioaddr = tp->mmio_addr;
2271 /* Soft reset the chip. */
2272 RTL_W8(ChipCmd, CmdReset);
2274 /* Check that the chip has finished the reset. */
2275 for (i = 0; i < 100; i++) {
2276 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2278 msleep_interruptible(1);
2283 netif_start_queue(dev);
2287 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2288 void __iomem *ioaddr)
2291 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2292 * register to be written before TxDescAddrLow to work.
2293 * Switching from MMIO to I/O access fixes the issue as well.
2295 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2296 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2297 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2298 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2301 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2305 cmd = RTL_R16(CPlusCmd);
2306 RTL_W16(CPlusCmd, cmd);
2310 static void rtl_set_rx_max_size(void __iomem *ioaddr)
2312 /* Low hurts. Let's disable the filtering. */
2313 RTL_W16(RxMaxSize, 16383);
2316 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2323 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2324 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2325 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2326 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2331 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2332 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2333 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2334 RTL_W32(0x7c, p->val);
2340 static void rtl_hw_start_8169(struct net_device *dev)
2342 struct rtl8169_private *tp = netdev_priv(dev);
2343 void __iomem *ioaddr = tp->mmio_addr;
2344 struct pci_dev *pdev = tp->pci_dev;
2346 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2347 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2348 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2351 RTL_W8(Cfg9346, Cfg9346_Unlock);
2352 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2353 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2354 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2355 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2356 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2358 RTL_W8(EarlyTxThres, EarlyTxThld);
2360 rtl_set_rx_max_size(ioaddr);
2362 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2363 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2364 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2365 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2366 rtl_set_rx_tx_config_registers(tp);
2368 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2370 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2371 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2372 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2373 "Bit-3 and bit-14 MUST be 1\n");
2374 tp->cp_cmd |= (1 << 14);
2377 RTL_W16(CPlusCmd, tp->cp_cmd);
2379 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2382 * Undocumented corner. Supposedly:
2383 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2385 RTL_W16(IntrMitigate, 0x0000);
2387 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2389 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2390 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2391 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2392 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2393 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2394 rtl_set_rx_tx_config_registers(tp);
2397 RTL_W8(Cfg9346, Cfg9346_Lock);
2399 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2402 RTL_W32(RxMissed, 0);
2404 rtl_set_rx_mode(dev);
2406 /* no early-rx interrupts */
2407 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2409 /* Enable all known interrupts by setting the interrupt mask. */
2410 RTL_W16(IntrMask, tp->intr_event);
2413 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2415 struct net_device *dev = pci_get_drvdata(pdev);
2416 struct rtl8169_private *tp = netdev_priv(dev);
2417 int cap = tp->pcie_cap;
2422 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2423 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2424 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2428 static void rtl_csi_access_enable(void __iomem *ioaddr)
2432 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2433 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2437 unsigned int offset;
2442 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2447 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2448 rtl_ephy_write(ioaddr, e->offset, w);
2453 static void rtl_disable_clock_request(struct pci_dev *pdev)
2455 struct net_device *dev = pci_get_drvdata(pdev);
2456 struct rtl8169_private *tp = netdev_priv(dev);
2457 int cap = tp->pcie_cap;
2462 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2463 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2464 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2468 #define R8168_CPCMD_QUIRK_MASK (\
2479 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2481 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2483 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2485 rtl_tx_performance_tweak(pdev,
2486 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
2489 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2491 rtl_hw_start_8168bb(ioaddr, pdev);
2493 RTL_W8(EarlyTxThres, EarlyTxThld);
2495 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
2498 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2500 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2502 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2504 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2506 rtl_disable_clock_request(pdev);
2508 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2511 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
2513 static struct ephy_info e_info_8168cp[] = {
2514 { 0x01, 0, 0x0001 },
2515 { 0x02, 0x0800, 0x1000 },
2516 { 0x03, 0, 0x0042 },
2517 { 0x06, 0x0080, 0x0000 },
2521 rtl_csi_access_enable(ioaddr);
2523 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2525 __rtl_hw_start_8168cp(ioaddr, pdev);
2528 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2530 rtl_csi_access_enable(ioaddr);
2532 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2534 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2536 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2539 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
2541 rtl_csi_access_enable(ioaddr);
2543 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2546 RTL_W8(DBG_REG, 0x20);
2548 RTL_W8(EarlyTxThres, EarlyTxThld);
2550 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2552 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2555 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2557 static struct ephy_info e_info_8168c_1[] = {
2558 { 0x02, 0x0800, 0x1000 },
2559 { 0x03, 0, 0x0002 },
2560 { 0x06, 0x0080, 0x0000 }
2563 rtl_csi_access_enable(ioaddr);
2565 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2567 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2569 __rtl_hw_start_8168cp(ioaddr, pdev);
2572 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2574 static struct ephy_info e_info_8168c_2[] = {
2575 { 0x01, 0, 0x0001 },
2576 { 0x03, 0x0400, 0x0220 }
2579 rtl_csi_access_enable(ioaddr);
2581 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2583 __rtl_hw_start_8168cp(ioaddr, pdev);
2586 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2588 rtl_hw_start_8168c_2(ioaddr, pdev);
2591 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2593 rtl_csi_access_enable(ioaddr);
2595 __rtl_hw_start_8168cp(ioaddr, pdev);
2598 static void rtl_hw_start_8168(struct net_device *dev)
2600 struct rtl8169_private *tp = netdev_priv(dev);
2601 void __iomem *ioaddr = tp->mmio_addr;
2602 struct pci_dev *pdev = tp->pci_dev;
2604 RTL_W8(Cfg9346, Cfg9346_Unlock);
2606 RTL_W8(EarlyTxThres, EarlyTxThld);
2608 rtl_set_rx_max_size(ioaddr);
2610 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2612 RTL_W16(CPlusCmd, tp->cp_cmd);
2614 RTL_W16(IntrMitigate, 0x5151);
2616 /* Work around for RxFIFO overflow. */
2617 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2618 tp->intr_event |= RxFIFOOver | PCSTimeout;
2619 tp->intr_event &= ~RxOverflow;
2622 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2624 rtl_set_rx_mode(dev);
2626 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2627 (InterFrameGap << TxInterFrameGapShift));
2631 switch (tp->mac_version) {
2632 case RTL_GIGA_MAC_VER_11:
2633 rtl_hw_start_8168bb(ioaddr, pdev);
2636 case RTL_GIGA_MAC_VER_12:
2637 case RTL_GIGA_MAC_VER_17:
2638 rtl_hw_start_8168bef(ioaddr, pdev);
2641 case RTL_GIGA_MAC_VER_18:
2642 rtl_hw_start_8168cp_1(ioaddr, pdev);
2645 case RTL_GIGA_MAC_VER_19:
2646 rtl_hw_start_8168c_1(ioaddr, pdev);
2649 case RTL_GIGA_MAC_VER_20:
2650 rtl_hw_start_8168c_2(ioaddr, pdev);
2653 case RTL_GIGA_MAC_VER_21:
2654 rtl_hw_start_8168c_3(ioaddr, pdev);
2657 case RTL_GIGA_MAC_VER_22:
2658 rtl_hw_start_8168c_4(ioaddr, pdev);
2661 case RTL_GIGA_MAC_VER_23:
2662 rtl_hw_start_8168cp_2(ioaddr, pdev);
2665 case RTL_GIGA_MAC_VER_24:
2666 rtl_hw_start_8168cp_3(ioaddr, pdev);
2670 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2671 dev->name, tp->mac_version);
2675 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2677 RTL_W8(Cfg9346, Cfg9346_Lock);
2679 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2681 RTL_W16(IntrMask, tp->intr_event);
2684 #define R810X_CPCMD_QUIRK_MASK (\
2696 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2698 static struct ephy_info e_info_8102e_1[] = {
2699 { 0x01, 0, 0x6e65 },
2700 { 0x02, 0, 0x091f },
2701 { 0x03, 0, 0xc2f9 },
2702 { 0x06, 0, 0xafb5 },
2703 { 0x07, 0, 0x0e00 },
2704 { 0x19, 0, 0xec80 },
2705 { 0x01, 0, 0x2e65 },
2710 rtl_csi_access_enable(ioaddr);
2712 RTL_W8(DBG_REG, FIX_NAK_1);
2714 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2717 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2718 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2720 cfg1 = RTL_R8(Config1);
2721 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2722 RTL_W8(Config1, cfg1 & ~LEDS0);
2724 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2726 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2729 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2731 rtl_csi_access_enable(ioaddr);
2733 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2735 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2736 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2738 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2741 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2743 rtl_hw_start_8102e_2(ioaddr, pdev);
2745 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2748 static void rtl_hw_start_8101(struct net_device *dev)
2750 struct rtl8169_private *tp = netdev_priv(dev);
2751 void __iomem *ioaddr = tp->mmio_addr;
2752 struct pci_dev *pdev = tp->pci_dev;
2754 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2755 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2756 int cap = tp->pcie_cap;
2759 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2760 PCI_EXP_DEVCTL_NOSNOOP_EN);
2764 switch (tp->mac_version) {
2765 case RTL_GIGA_MAC_VER_07:
2766 rtl_hw_start_8102e_1(ioaddr, pdev);
2769 case RTL_GIGA_MAC_VER_08:
2770 rtl_hw_start_8102e_3(ioaddr, pdev);
2773 case RTL_GIGA_MAC_VER_09:
2774 rtl_hw_start_8102e_2(ioaddr, pdev);
2778 RTL_W8(Cfg9346, Cfg9346_Unlock);
2780 RTL_W8(EarlyTxThres, EarlyTxThld);
2782 rtl_set_rx_max_size(ioaddr);
2784 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2786 RTL_W16(CPlusCmd, tp->cp_cmd);
2788 RTL_W16(IntrMitigate, 0x0000);
2790 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2792 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2793 rtl_set_rx_tx_config_registers(tp);
2795 RTL_W8(Cfg9346, Cfg9346_Lock);
2799 rtl_set_rx_mode(dev);
2801 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2803 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2805 RTL_W16(IntrMask, tp->intr_event);
2808 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2810 struct rtl8169_private *tp = netdev_priv(dev);
2813 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2818 if (!netif_running(dev))
2823 rtl8169_set_rxbufsize(tp, dev);
2825 ret = rtl8169_init_ring(dev);
2829 napi_enable(&tp->napi);
2833 rtl8169_request_timer(dev);
2839 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2841 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2842 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2845 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2846 struct sk_buff **sk_buff, struct RxDesc *desc)
2848 struct pci_dev *pdev = tp->pci_dev;
2850 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2851 PCI_DMA_FROMDEVICE);
2852 dev_kfree_skb(*sk_buff);
2854 rtl8169_make_unusable_by_asic(desc);
2857 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2859 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2861 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2864 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2867 desc->addr = cpu_to_le64(mapping);
2869 rtl8169_mark_to_asic(desc, rx_buf_sz);
2872 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2873 struct net_device *dev,
2874 struct RxDesc *desc, int rx_buf_sz,
2877 struct sk_buff *skb;
2881 pad = align ? align : NET_IP_ALIGN;
2883 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2887 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2889 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2890 PCI_DMA_FROMDEVICE);
2892 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2897 rtl8169_make_unusable_by_asic(desc);
2901 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2905 for (i = 0; i < NUM_RX_DESC; i++) {
2906 if (tp->Rx_skbuff[i]) {
2907 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2908 tp->RxDescArray + i);
2913 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2918 for (cur = start; end - cur != 0; cur++) {
2919 struct sk_buff *skb;
2920 unsigned int i = cur % NUM_RX_DESC;
2922 WARN_ON((s32)(end - cur) < 0);
2924 if (tp->Rx_skbuff[i])
2927 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2928 tp->RxDescArray + i,
2929 tp->rx_buf_sz, tp->align);
2933 tp->Rx_skbuff[i] = skb;
2938 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2940 desc->opts1 |= cpu_to_le32(RingEnd);
2943 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2945 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2948 static int rtl8169_init_ring(struct net_device *dev)
2950 struct rtl8169_private *tp = netdev_priv(dev);
2952 rtl8169_init_ring_indexes(tp);
2954 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2955 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2957 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2960 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2965 rtl8169_rx_clear(tp);
2969 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2970 struct TxDesc *desc)
2972 unsigned int len = tx_skb->len;
2974 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2981 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2985 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2986 unsigned int entry = i % NUM_TX_DESC;
2987 struct ring_info *tx_skb = tp->tx_skb + entry;
2988 unsigned int len = tx_skb->len;
2991 struct sk_buff *skb = tx_skb->skb;
2993 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2994 tp->TxDescArray + entry);
2999 tp->dev->stats.tx_dropped++;
3002 tp->cur_tx = tp->dirty_tx = 0;
3005 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
3007 struct rtl8169_private *tp = netdev_priv(dev);
3009 PREPARE_DELAYED_WORK(&tp->task, task);
3010 schedule_delayed_work(&tp->task, 4);
3013 static void rtl8169_wait_for_quiescence(struct net_device *dev)
3015 struct rtl8169_private *tp = netdev_priv(dev);
3016 void __iomem *ioaddr = tp->mmio_addr;
3018 synchronize_irq(dev->irq);
3020 /* Wait for any pending NAPI task to complete */
3021 napi_disable(&tp->napi);
3023 rtl8169_irq_mask_and_ack(ioaddr);
3025 tp->intr_mask = 0xffff;
3026 RTL_W16(IntrMask, tp->intr_event);
3027 napi_enable(&tp->napi);
3030 static void rtl8169_reinit_task(struct work_struct *work)
3032 struct rtl8169_private *tp =
3033 container_of(work, struct rtl8169_private, task.work);
3034 struct net_device *dev = tp->dev;
3039 if (!netif_running(dev))
3042 rtl8169_wait_for_quiescence(dev);
3045 ret = rtl8169_open(dev);
3046 if (unlikely(ret < 0)) {
3047 if (net_ratelimit() && netif_msg_drv(tp)) {
3048 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
3049 " Rescheduling.\n", dev->name, ret);
3051 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3058 static void rtl8169_reset_task(struct work_struct *work)
3060 struct rtl8169_private *tp =
3061 container_of(work, struct rtl8169_private, task.work);
3062 struct net_device *dev = tp->dev;
3066 if (!netif_running(dev))
3069 rtl8169_wait_for_quiescence(dev);
3071 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
3072 rtl8169_tx_clear(tp);
3074 if (tp->dirty_rx == tp->cur_rx) {
3075 rtl8169_init_ring_indexes(tp);
3077 netif_wake_queue(dev);
3078 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3080 if (net_ratelimit() && netif_msg_intr(tp)) {
3081 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
3084 rtl8169_schedule_work(dev, rtl8169_reset_task);
3091 static void rtl8169_tx_timeout(struct net_device *dev)
3093 struct rtl8169_private *tp = netdev_priv(dev);
3095 rtl8169_hw_reset(tp->mmio_addr);
3097 /* Let's wait a bit while any (async) irq lands on */
3098 rtl8169_schedule_work(dev, rtl8169_reset_task);
3101 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3104 struct skb_shared_info *info = skb_shinfo(skb);
3105 unsigned int cur_frag, entry;
3106 struct TxDesc * uninitialized_var(txd);
3109 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3110 skb_frag_t *frag = info->frags + cur_frag;
3115 entry = (entry + 1) % NUM_TX_DESC;
3117 txd = tp->TxDescArray + entry;
3119 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3120 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3122 /* anti gcc 2.95.3 bugware (sic) */
3123 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3125 txd->opts1 = cpu_to_le32(status);
3126 txd->addr = cpu_to_le64(mapping);
3128 tp->tx_skb[entry].len = len;
3132 tp->tx_skb[entry].skb = skb;
3133 txd->opts1 |= cpu_to_le32(LastFrag);
3139 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3141 if (dev->features & NETIF_F_TSO) {
3142 u32 mss = skb_shinfo(skb)->gso_size;
3145 return LargeSend | ((mss & MSSMask) << MSSShift);
3147 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3148 const struct iphdr *ip = ip_hdr(skb);
3150 if (ip->protocol == IPPROTO_TCP)
3151 return IPCS | TCPCS;
3152 else if (ip->protocol == IPPROTO_UDP)
3153 return IPCS | UDPCS;
3154 WARN_ON(1); /* we need a WARN() */
3159 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3161 struct rtl8169_private *tp = netdev_priv(dev);
3162 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3163 struct TxDesc *txd = tp->TxDescArray + entry;
3164 void __iomem *ioaddr = tp->mmio_addr;
3168 int ret = NETDEV_TX_OK;
3170 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3171 if (netif_msg_drv(tp)) {
3173 "%s: BUG! Tx Ring full when queue awake!\n",
3179 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3182 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3184 frags = rtl8169_xmit_frags(tp, skb, opts1);
3186 len = skb_headlen(skb);
3191 if (unlikely(len < ETH_ZLEN)) {
3192 if (skb_padto(skb, ETH_ZLEN))
3193 goto err_update_stats;
3197 opts1 |= FirstFrag | LastFrag;
3198 tp->tx_skb[entry].skb = skb;
3201 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3203 tp->tx_skb[entry].len = len;
3204 txd->addr = cpu_to_le64(mapping);
3205 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3209 /* anti gcc 2.95.3 bugware (sic) */
3210 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3211 txd->opts1 = cpu_to_le32(status);
3213 dev->trans_start = jiffies;
3215 tp->cur_tx += frags + 1;
3219 RTL_W8(TxPoll, NPQ); /* set polling bit */
3221 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3222 netif_stop_queue(dev);
3224 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3225 netif_wake_queue(dev);
3232 netif_stop_queue(dev);
3233 ret = NETDEV_TX_BUSY;
3235 dev->stats.tx_dropped++;
3239 static void rtl8169_pcierr_interrupt(struct net_device *dev)
3241 struct rtl8169_private *tp = netdev_priv(dev);
3242 struct pci_dev *pdev = tp->pci_dev;
3243 void __iomem *ioaddr = tp->mmio_addr;
3244 u16 pci_status, pci_cmd;
3246 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3247 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3249 if (netif_msg_intr(tp)) {
3251 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3252 dev->name, pci_cmd, pci_status);
3256 * The recovery sequence below admits a very elaborated explanation:
3257 * - it seems to work;
3258 * - I did not see what else could be done;
3259 * - it makes iop3xx happy.
3261 * Feel free to adjust to your needs.
3263 if (pdev->broken_parity_status)
3264 pci_cmd &= ~PCI_COMMAND_PARITY;
3266 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3268 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3270 pci_write_config_word(pdev, PCI_STATUS,
3271 pci_status & (PCI_STATUS_DETECTED_PARITY |
3272 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3273 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3275 /* The infamous DAC f*ckup only happens at boot time */
3276 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3277 if (netif_msg_intr(tp))
3278 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
3279 tp->cp_cmd &= ~PCIDAC;
3280 RTL_W16(CPlusCmd, tp->cp_cmd);
3281 dev->features &= ~NETIF_F_HIGHDMA;
3284 rtl8169_hw_reset(ioaddr);
3286 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3289 static void rtl8169_tx_interrupt(struct net_device *dev,
3290 struct rtl8169_private *tp,
3291 void __iomem *ioaddr)
3293 unsigned int dirty_tx, tx_left;
3295 dirty_tx = tp->dirty_tx;
3297 tx_left = tp->cur_tx - dirty_tx;
3299 while (tx_left > 0) {
3300 unsigned int entry = dirty_tx % NUM_TX_DESC;
3301 struct ring_info *tx_skb = tp->tx_skb + entry;
3302 u32 len = tx_skb->len;
3306 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3307 if (status & DescOwn)
3310 dev->stats.tx_bytes += len;
3311 dev->stats.tx_packets++;
3313 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3315 if (status & LastFrag) {
3316 dev_kfree_skb_irq(tx_skb->skb);
3323 if (tp->dirty_tx != dirty_tx) {
3324 tp->dirty_tx = dirty_tx;
3326 if (netif_queue_stopped(dev) &&
3327 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3328 netif_wake_queue(dev);
3331 * 8168 hack: TxPoll requests are lost when the Tx packets are
3332 * too close. Let's kick an extra TxPoll request when a burst
3333 * of start_xmit activity is detected (if it is not detected,
3334 * it is slow enough). -- FR
3337 if (tp->cur_tx != dirty_tx)
3338 RTL_W8(TxPoll, NPQ);
3342 static inline int rtl8169_fragmented_frame(u32 status)
3344 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3347 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3349 u32 opts1 = le32_to_cpu(desc->opts1);
3350 u32 status = opts1 & RxProtoMask;
3352 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3353 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3354 ((status == RxProtoIP) && !(opts1 & IPFail)))
3355 skb->ip_summed = CHECKSUM_UNNECESSARY;
3357 skb->ip_summed = CHECKSUM_NONE;
3360 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3361 struct rtl8169_private *tp, int pkt_size,
3364 struct sk_buff *skb;
3367 if (pkt_size >= rx_copybreak)
3370 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3374 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3375 PCI_DMA_FROMDEVICE);
3376 skb_reserve(skb, NET_IP_ALIGN);
3377 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3384 static int rtl8169_rx_interrupt(struct net_device *dev,
3385 struct rtl8169_private *tp,
3386 void __iomem *ioaddr, u32 budget)
3388 unsigned int cur_rx, rx_left;
3389 unsigned int delta, count;
3391 cur_rx = tp->cur_rx;
3392 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3393 rx_left = min(rx_left, budget);
3395 for (; rx_left > 0; rx_left--, cur_rx++) {
3396 unsigned int entry = cur_rx % NUM_RX_DESC;
3397 struct RxDesc *desc = tp->RxDescArray + entry;
3401 status = le32_to_cpu(desc->opts1);
3403 if (status & DescOwn)
3405 if (unlikely(status & RxRES)) {
3406 if (netif_msg_rx_err(tp)) {
3408 "%s: Rx ERROR. status = %08x\n",
3411 dev->stats.rx_errors++;
3412 if (status & (RxRWT | RxRUNT))
3413 dev->stats.rx_length_errors++;
3415 dev->stats.rx_crc_errors++;
3416 if (status & RxFOVF) {
3417 rtl8169_schedule_work(dev, rtl8169_reset_task);
3418 dev->stats.rx_fifo_errors++;
3420 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3422 struct sk_buff *skb = tp->Rx_skbuff[entry];
3423 dma_addr_t addr = le64_to_cpu(desc->addr);
3424 int pkt_size = (status & 0x00001FFF) - 4;
3425 struct pci_dev *pdev = tp->pci_dev;
3428 * The driver does not support incoming fragmented
3429 * frames. They are seen as a symptom of over-mtu
3432 if (unlikely(rtl8169_fragmented_frame(status))) {
3433 dev->stats.rx_dropped++;
3434 dev->stats.rx_length_errors++;
3435 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3439 rtl8169_rx_csum(skb, desc);
3441 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3442 pci_dma_sync_single_for_device(pdev, addr,
3443 pkt_size, PCI_DMA_FROMDEVICE);
3444 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3446 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
3447 PCI_DMA_FROMDEVICE);
3448 tp->Rx_skbuff[entry] = NULL;
3451 skb_put(skb, pkt_size);
3452 skb->protocol = eth_type_trans(skb, dev);
3454 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3455 netif_receive_skb(skb);
3457 dev->last_rx = jiffies;
3458 dev->stats.rx_bytes += pkt_size;
3459 dev->stats.rx_packets++;
3462 /* Work around for AMD plateform. */
3463 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3464 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3470 count = cur_rx - tp->cur_rx;
3471 tp->cur_rx = cur_rx;
3473 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3474 if (!delta && count && netif_msg_intr(tp))
3475 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3476 tp->dirty_rx += delta;
3479 * FIXME: until there is periodic timer to try and refill the ring,
3480 * a temporary shortage may definitely kill the Rx process.
3481 * - disable the asic to try and avoid an overflow and kick it again
3483 * - how do others driver handle this condition (Uh oh...).
3485 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3486 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3491 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3493 struct net_device *dev = dev_instance;
3494 struct rtl8169_private *tp = netdev_priv(dev);
3495 void __iomem *ioaddr = tp->mmio_addr;
3499 status = RTL_R16(IntrStatus);
3501 /* hotplug/major error/no more work/shared irq */
3502 if ((status == 0xffff) || !status)
3507 if (unlikely(!netif_running(dev))) {
3508 rtl8169_asic_down(ioaddr);
3512 status &= tp->intr_mask;
3514 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3516 if (!(status & tp->intr_event))
3519 /* Work around for rx fifo overflow */
3520 if (unlikely(status & RxFIFOOver) &&
3521 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3522 netif_stop_queue(dev);
3523 rtl8169_tx_timeout(dev);
3527 if (unlikely(status & SYSErr)) {
3528 rtl8169_pcierr_interrupt(dev);
3532 if (status & LinkChg)
3533 rtl8169_check_link_status(dev, tp, ioaddr);
3535 if (status & tp->napi_event) {
3536 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3537 tp->intr_mask = ~tp->napi_event;
3539 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
3540 __netif_rx_schedule(dev, &tp->napi);
3541 else if (netif_msg_intr(tp)) {
3542 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3547 return IRQ_RETVAL(handled);
3550 static int rtl8169_poll(struct napi_struct *napi, int budget)
3552 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3553 struct net_device *dev = tp->dev;
3554 void __iomem *ioaddr = tp->mmio_addr;
3557 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3558 rtl8169_tx_interrupt(dev, tp, ioaddr);
3560 if (work_done < budget) {
3561 netif_rx_complete(dev, napi);
3562 tp->intr_mask = 0xffff;
3564 * 20040426: the barrier is not strictly required but the
3565 * behavior of the irq handler could be less predictable
3566 * without it. Btw, the lack of flush for the posted pci
3567 * write is safe - FR
3570 RTL_W16(IntrMask, tp->intr_event);
3576 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3578 struct rtl8169_private *tp = netdev_priv(dev);
3580 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3583 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3584 RTL_W32(RxMissed, 0);
3587 static void rtl8169_down(struct net_device *dev)
3589 struct rtl8169_private *tp = netdev_priv(dev);
3590 void __iomem *ioaddr = tp->mmio_addr;
3591 unsigned int intrmask;
3593 rtl8169_delete_timer(dev);
3595 netif_stop_queue(dev);
3597 napi_disable(&tp->napi);
3600 spin_lock_irq(&tp->lock);
3602 rtl8169_asic_down(ioaddr);
3604 rtl8169_rx_missed(dev, ioaddr);
3606 spin_unlock_irq(&tp->lock);
3608 synchronize_irq(dev->irq);
3610 /* Give a racing hard_start_xmit a few cycles to complete. */
3611 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3614 * And now for the 50k$ question: are IRQ disabled or not ?
3616 * Two paths lead here:
3618 * -> netif_running() is available to sync the current code and the
3619 * IRQ handler. See rtl8169_interrupt for details.
3620 * 2) dev->change_mtu
3621 * -> rtl8169_poll can not be issued again and re-enable the
3622 * interruptions. Let's simply issue the IRQ down sequence again.
3624 * No loop if hotpluged or major error (0xffff).
3626 intrmask = RTL_R16(IntrMask);
3627 if (intrmask && (intrmask != 0xffff))
3630 rtl8169_tx_clear(tp);
3632 rtl8169_rx_clear(tp);
3635 static int rtl8169_close(struct net_device *dev)
3637 struct rtl8169_private *tp = netdev_priv(dev);
3638 struct pci_dev *pdev = tp->pci_dev;
3642 free_irq(dev->irq, dev);
3644 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3646 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3648 tp->TxDescArray = NULL;
3649 tp->RxDescArray = NULL;
3654 static void rtl_set_rx_mode(struct net_device *dev)
3656 struct rtl8169_private *tp = netdev_priv(dev);
3657 void __iomem *ioaddr = tp->mmio_addr;
3658 unsigned long flags;
3659 u32 mc_filter[2]; /* Multicast hash filter */
3663 if (dev->flags & IFF_PROMISC) {
3664 /* Unconditionally log net taps. */
3665 if (netif_msg_link(tp)) {
3666 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3670 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3672 mc_filter[1] = mc_filter[0] = 0xffffffff;
3673 } else if ((dev->mc_count > multicast_filter_limit)
3674 || (dev->flags & IFF_ALLMULTI)) {
3675 /* Too many to filter perfectly -- accept all multicasts. */
3676 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3677 mc_filter[1] = mc_filter[0] = 0xffffffff;
3679 struct dev_mc_list *mclist;
3682 rx_mode = AcceptBroadcast | AcceptMyPhys;
3683 mc_filter[1] = mc_filter[0] = 0;
3684 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3685 i++, mclist = mclist->next) {
3686 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3687 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3688 rx_mode |= AcceptMulticast;
3692 spin_lock_irqsave(&tp->lock, flags);
3694 tmp = rtl8169_rx_config | rx_mode |
3695 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3697 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3698 u32 data = mc_filter[0];
3700 mc_filter[0] = swab32(mc_filter[1]);
3701 mc_filter[1] = swab32(data);
3704 RTL_W32(MAR0 + 0, mc_filter[0]);
3705 RTL_W32(MAR0 + 4, mc_filter[1]);
3707 RTL_W32(RxConfig, tmp);
3709 spin_unlock_irqrestore(&tp->lock, flags);
3713 * rtl8169_get_stats - Get rtl8169 read/write statistics
3714 * @dev: The Ethernet Device to get statistics for
3716 * Get TX/RX statistics for rtl8169
3718 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3720 struct rtl8169_private *tp = netdev_priv(dev);
3721 void __iomem *ioaddr = tp->mmio_addr;
3722 unsigned long flags;
3724 if (netif_running(dev)) {
3725 spin_lock_irqsave(&tp->lock, flags);
3726 rtl8169_rx_missed(dev, ioaddr);
3727 spin_unlock_irqrestore(&tp->lock, flags);
3735 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3737 struct net_device *dev = pci_get_drvdata(pdev);
3738 struct rtl8169_private *tp = netdev_priv(dev);
3739 void __iomem *ioaddr = tp->mmio_addr;
3741 if (!netif_running(dev))
3742 goto out_pci_suspend;
3744 netif_device_detach(dev);
3745 netif_stop_queue(dev);
3747 spin_lock_irq(&tp->lock);
3749 rtl8169_asic_down(ioaddr);
3751 rtl8169_rx_missed(dev, ioaddr);
3753 spin_unlock_irq(&tp->lock);
3756 pci_save_state(pdev);
3757 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3758 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3759 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3764 static int rtl8169_resume(struct pci_dev *pdev)
3766 struct net_device *dev = pci_get_drvdata(pdev);
3768 pci_set_power_state(pdev, PCI_D0);
3769 pci_restore_state(pdev);
3770 pci_enable_wake(pdev, PCI_D0, 0);
3772 if (!netif_running(dev))
3775 netif_device_attach(dev);
3777 rtl8169_schedule_work(dev, rtl8169_reset_task);
3782 #endif /* CONFIG_PM */
3784 static struct pci_driver rtl8169_pci_driver = {
3786 .id_table = rtl8169_pci_tbl,
3787 .probe = rtl8169_init_one,
3788 .remove = __devexit_p(rtl8169_remove_one),
3790 .suspend = rtl8169_suspend,
3791 .resume = rtl8169_resume,
3795 static int __init rtl8169_init_module(void)
3797 return pci_register_driver(&rtl8169_pci_driver);
3800 static void __exit rtl8169_cleanup_module(void)
3802 pci_unregister_driver(&rtl8169_pci_driver);
3805 module_init(rtl8169_init_module);
3806 module_exit(rtl8169_cleanup_module);