drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30
  31 #ifdef CONFIG_R8169_NAPI
  32 #define NAPI_SUFFIX     "-NAPI"
  33 #else
  34 #define NAPI_SUFFIX     ""
  35 #endif
  36
  37 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
  38 #define MODULENAME "r8169"
  39 #define PFX MODULENAME ": "
  40
  41 #ifdef RTL8169_DEBUG
  42 #define assert(expr) \
  43         if (!(expr)) {                                  \
  44                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  45                 #expr,__FILE__,__FUNCTION__,__LINE__);          \
  46         }
  47 #define dprintk(fmt, args...)   do { printk(PFX fmt, ## args); } while (0)
  48 #else
  49 #define assert(expr) do {} while (0)
  50 #define dprintk(fmt, args...)   do {} while (0)
  51 #endif /* RTL8169_DEBUG */
  52
  53 #define R8169_MSG_DEFAULT \
  54         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  55
  56 #define TX_BUFFS_AVAIL(tp) \
  57         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  58
  59 #ifdef CONFIG_R8169_NAPI
  60 #define rtl8169_rx_skb                  netif_receive_skb
  61 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_receive_skb
  62 #define rtl8169_rx_quota(count, quota)  min(count, quota)
  63 #else
  64 #define rtl8169_rx_skb                  netif_rx
  65 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_rx
  66 #define rtl8169_rx_quota(count, quota)  count
  67 #endif
  68
  69 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  70 static const int max_interrupt_work = 20;
  71
  72 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  73    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  74 static const int multicast_filter_limit = 32;
  75
  76 /* MAC address length */
  77 #define MAC_ADDR_LEN    6
  78
  79 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  80 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  81 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  82 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  83 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
  84 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  85 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  86
  87 #define R8169_REGS_SIZE         256
  88 #define R8169_NAPI_WEIGHT       64
  89 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  90 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  91 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  92 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  93 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  94
  95 #define RTL8169_TX_TIMEOUT      (6*HZ)
  96 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  97
  98 /* write/read MMIO register */
  99 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 100 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 101 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 102 #define RTL_R8(reg)             readb (ioaddr + (reg))
 103 #define RTL_R16(reg)            readw (ioaddr + (reg))
 104 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
 105
 106 enum mac_version {
 107         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
 108         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
 109         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 110         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 111         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 112         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 113         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 114         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
 115         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
 116         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
 117         RTL_GIGA_MAC_VER_15 = 0x0f  // 8101
 118 };
 119
 120 enum phy_version {
 121         RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 122         RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 123         RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 124         RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
 125         RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
 126         RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
 127 };
 128
 129 #define _R(NAME,MAC,MASK) \
 130         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 131
 132 static const struct {
 133         const char *name;
 134         u8 mac_version;
 135         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 136 } rtl_chip_info[] = {
 137         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 138         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 139         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 140         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 141         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 142         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 143         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 144         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 145         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 146         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 147         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880)  // PCI-E 8139
 148 };
 149 #undef _R
 150
 151 enum cfg_version {
 152         RTL_CFG_0 = 0x00,
 153         RTL_CFG_1,
 154         RTL_CFG_2
 155 };
 156
 157 static void rtl_hw_start_8169(struct net_device *);
 158 static void rtl_hw_start_8168(struct net_device *);
 159 static void rtl_hw_start_8101(struct net_device *);
 160
 161 static struct pci_device_id rtl8169_pci_tbl[] = {
 162         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 163         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 164         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 165         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 166         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 167         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 168         { PCI_DEVICE(0x1259,                    0xc107), 0, 0, RTL_CFG_0 },
 169         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 170         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 171                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 172         {0,},
 173 };
 174
 175 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 176
 177 static int rx_copybreak = 200;
 178 static int use_dac;
 179 static struct {
 180         u32 msg_enable;
 181 } debug = { -1 };
 182
 183 enum rtl_registers {
 184         MAC0            = 0,    /* Ethernet hardware address. */
 185         MAR0            = 8,    /* Multicast filter. */
 186         CounterAddrLow          = 0x10,
 187         CounterAddrHigh         = 0x14,
 188         TxDescStartAddrLow      = 0x20,
 189         TxDescStartAddrHigh     = 0x24,
 190         TxHDescStartAddrLow     = 0x28,
 191         TxHDescStartAddrHigh    = 0x2c,
 192         FLASH           = 0x30,
 193         ERSR            = 0x36,
 194         ChipCmd         = 0x37,
 195         TxPoll          = 0x38,
 196         IntrMask        = 0x3c,
 197         IntrStatus      = 0x3e,
 198         TxConfig        = 0x40,
 199         RxConfig        = 0x44,
 200         RxMissed        = 0x4c,
 201         Cfg9346         = 0x50,
 202         Config0         = 0x51,
 203         Config1         = 0x52,
 204         Config2         = 0x53,
 205         Config3         = 0x54,
 206         Config4         = 0x55,
 207         Config5         = 0x56,
 208         MultiIntr       = 0x5c,
 209         PHYAR           = 0x60,
 210         TBICSR          = 0x64,
 211         TBI_ANAR        = 0x68,
 212         TBI_LPAR        = 0x6a,
 213         PHYstatus       = 0x6c,
 214         RxMaxSize       = 0xda,
 215         CPlusCmd        = 0xe0,
 216         IntrMitigate    = 0xe2,
 217         RxDescAddrLow   = 0xe4,
 218         RxDescAddrHigh  = 0xe8,
 219         EarlyTxThres    = 0xec,
 220         FuncEvent       = 0xf0,
 221         FuncEventMask   = 0xf4,
 222         FuncPresetState = 0xf8,
 223         FuncForceEvent  = 0xfc,
 224 };
 225
 226 enum rtl_register_content {
 227         /* InterruptStatusBits */
 228         SYSErr          = 0x8000,
 229         PCSTimeout      = 0x4000,
 230         SWInt           = 0x0100,
 231         TxDescUnavail   = 0x0080,
 232         RxFIFOOver      = 0x0040,
 233         LinkChg         = 0x0020,
 234         RxOverflow      = 0x0010,
 235         TxErr           = 0x0008,
 236         TxOK            = 0x0004,
 237         RxErr           = 0x0002,
 238         RxOK            = 0x0001,
 239
 240         /* RxStatusDesc */
 241         RxFOVF  = (1 << 23),
 242         RxRWT   = (1 << 22),
 243         RxRES   = (1 << 21),
 244         RxRUNT  = (1 << 20),
 245         RxCRC   = (1 << 19),
 246
 247         /* ChipCmdBits */
 248         CmdReset        = 0x10,
 249         CmdRxEnb        = 0x08,
 250         CmdTxEnb        = 0x04,
 251         RxBufEmpty      = 0x01,
 252
 253         /* Cfg9346Bits */
 254         Cfg9346_Lock    = 0x00,
 255         Cfg9346_Unlock  = 0xc0,
 256
 257         /* rx_mode_bits */
 258         AcceptErr       = 0x20,
 259         AcceptRunt      = 0x10,
 260         AcceptBroadcast = 0x08,
 261         AcceptMulticast = 0x04,
 262         AcceptMyPhys    = 0x02,
 263         AcceptAllPhys   = 0x01,
 264
 265         /* RxConfigBits */
 266         RxCfgFIFOShift  = 13,
 267         RxCfgDMAShift   =  8,
 268
 269         /* TxConfigBits */
 270         TxInterFrameGapShift = 24,
 271         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 272
 273         /* Config1 register p.24 */
 274         PMEnable        = (1 << 0),     /* Power Management Enable */
 275
 276         /* Config2 register p. 25 */
 277         PCI_Clock_66MHz = 0x01,
 278         PCI_Clock_33MHz = 0x00,
 279
 280         /* Config3 register p.25 */
 281         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 282         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 283
 284         /* Config5 register p.27 */
 285         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 286         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 287         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 288         LanWake         = (1 << 1),     /* LanWake enable/disable */
 289         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 290
 291         /* TBICSR p.28 */
 292         TBIReset        = 0x80000000,
 293         TBILoopback     = 0x40000000,
 294         TBINwEnable     = 0x20000000,
 295         TBINwRestart    = 0x10000000,
 296         TBILinkOk       = 0x02000000,
 297         TBINwComplete   = 0x01000000,
 298
 299         /* CPlusCmd p.31 */
 300         PktCntrDisable  = (1 << 7),     // 8168
 301         RxVlan          = (1 << 6),
 302         RxChkSum        = (1 << 5),
 303         PCIDAC          = (1 << 4),
 304         PCIMulRW        = (1 << 3),
 305         INTT_0          = 0x0000,       // 8168
 306         INTT_1          = 0x0001,       // 8168
 307         INTT_2          = 0x0002,       // 8168
 308         INTT_3          = 0x0003,       // 8168
 309
 310         /* rtl8169_PHYstatus */
 311         TBI_Enable      = 0x80,
 312         TxFlowCtrl      = 0x40,
 313         RxFlowCtrl      = 0x20,
 314         _1000bpsF       = 0x10,
 315         _100bps         = 0x08,
 316         _10bps          = 0x04,
 317         LinkStatus      = 0x02,
 318         FullDup         = 0x01,
 319
 320         /* _TBICSRBit */
 321         TBILinkOK       = 0x02000000,
 322
 323         /* DumpCounterCommand */
 324         CounterDump     = 0x8,
 325 };
 326
 327 enum desc_status_bit {
 328         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 329         RingEnd         = (1 << 30), /* End of descriptor ring */
 330         FirstFrag       = (1 << 29), /* First segment of a packet */
 331         LastFrag        = (1 << 28), /* Final segment of a packet */
 332
 333         /* Tx private */
 334         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 335         MSSShift        = 16,        /* MSS value position */
 336         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 337         IPCS            = (1 << 18), /* Calculate IP checksum */
 338         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 339         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 340         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 341
 342         /* Rx private */
 343         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 344         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 345
 346 #define RxProtoUDP      (PID1)
 347 #define RxProtoTCP      (PID0)
 348 #define RxProtoIP       (PID1 | PID0)
 349 #define RxProtoMask     RxProtoIP
 350
 351         IPFail          = (1 << 16), /* IP checksum failed */
 352         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 353         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 354         RxVlanTag       = (1 << 16), /* VLAN tag available */
 355 };
 356
 357 #define RsvdMask        0x3fffc000
 358
 359 struct TxDesc {
 360         u32 opts1;
 361         u32 opts2;
 362         u64 addr;
 363 };
 364
 365 struct RxDesc {
 366         u32 opts1;
 367         u32 opts2;
 368         u64 addr;
 369 };
 370
 371 struct ring_info {
 372         struct sk_buff  *skb;
 373         u32             len;
 374         u8              __pad[sizeof(void *) - sizeof(u32)];
 375 };
 376
 377 struct rtl8169_private {
 378         void __iomem *mmio_addr;        /* memory map physical address */
 379         struct pci_dev *pci_dev;        /* Index of PCI device */
 380         struct net_device *dev;
 381         struct net_device_stats stats;  /* statistics of net device */
 382         spinlock_t lock;                /* spin lock flag */
 383         u32 msg_enable;
 384         int chipset;
 385         int mac_version;
 386         int phy_version;
 387         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 388         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 389         u32 dirty_rx;
 390         u32 dirty_tx;
 391         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 392         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 393         dma_addr_t TxPhyAddr;
 394         dma_addr_t RxPhyAddr;
 395         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 396         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 397         unsigned align;
 398         unsigned rx_buf_sz;
 399         struct timer_list timer;
 400         u16 cp_cmd;
 401         u16 intr_event;
 402         u16 napi_event;
 403         u16 intr_mask;
 404         int phy_auto_nego_reg;
 405         int phy_1000_ctrl_reg;
 406 #ifdef CONFIG_R8169_VLAN
 407         struct vlan_group *vlgrp;
 408 #endif
 409         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 410         void (*get_settings)(struct net_device *, struct ethtool_cmd *);
 411         void (*phy_reset_enable)(void __iomem *);
 412         void (*hw_start)(struct net_device *);
 413         unsigned int (*phy_reset_pending)(void __iomem *);
 414         unsigned int (*link_ok)(void __iomem *);
 415         struct delayed_work task;
 416         unsigned wol_enabled : 1;
 417 };
 418
 419 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 420 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 421 module_param(rx_copybreak, int, 0);
 422 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 423 module_param(use_dac, int, 0);
 424 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 425 module_param_named(debug, debug.msg_enable, int, 0);
 426 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 427 MODULE_LICENSE("GPL");
 428 MODULE_VERSION(RTL8169_VERSION);
 429
 430 static int rtl8169_open(struct net_device *dev);
 431 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 432 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 433 static int rtl8169_init_ring(struct net_device *dev);
 434 static void rtl_hw_start(struct net_device *dev);
 435 static int rtl8169_close(struct net_device *dev);
 436 static void rtl_set_rx_mode(struct net_device *dev);
 437 static void rtl8169_tx_timeout(struct net_device *dev);
 438 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 439 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 440                                 void __iomem *);
 441 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 442 static void rtl8169_down(struct net_device *dev);
 443 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 444
 445 #ifdef CONFIG_R8169_NAPI
 446 static int rtl8169_poll(struct net_device *dev, int *budget);
 447 #endif
 448
 449 static const unsigned int rtl8169_rx_config =
 450         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 451
 452 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 453 {
 454         int i;
 455
 456         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
 457
 458         for (i = 20; i > 0; i--) {
 459                 /*
 460                  * Check if the RTL8169 has completed writing to the specified
 461                  * MII register.
 462                  */
 463                 if (!(RTL_R32(PHYAR) & 0x80000000))
 464                         break;
 465                 udelay(25);
 466         }
 467 }
 468
 469 static int mdio_read(void __iomem *ioaddr, int reg_addr)
 470 {
 471         int i, value = -1;
 472
 473         RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
 474
 475         for (i = 20; i > 0; i--) {
 476                 /*
 477                  * Check if the RTL8169 has completed retrieving data from
 478                  * the specified MII register.
 479                  */
 480                 if (RTL_R32(PHYAR) & 0x80000000) {
 481                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
 482                         break;
 483                 }
 484                 udelay(25);
 485         }
 486         return value;
 487 }
 488
 489 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 490 {
 491         RTL_W16(IntrMask, 0x0000);
 492
 493         RTL_W16(IntrStatus, 0xffff);
 494 }
 495
 496 static void rtl8169_asic_down(void __iomem *ioaddr)
 497 {
 498         RTL_W8(ChipCmd, 0x00);
 499         rtl8169_irq_mask_and_ack(ioaddr);
 500         RTL_R16(CPlusCmd);
 501 }
 502
 503 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 504 {
 505         return RTL_R32(TBICSR) & TBIReset;
 506 }
 507
 508 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 509 {
 510         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 511 }
 512
 513 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 514 {
 515         return RTL_R32(TBICSR) & TBILinkOk;
 516 }
 517
 518 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 519 {
 520         return RTL_R8(PHYstatus) & LinkStatus;
 521 }
 522
 523 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 524 {
 525         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 526 }
 527
 528 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 529 {
 530         unsigned int val;
 531
 532         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 533         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 534 }
 535
 536 static void rtl8169_check_link_status(struct net_device *dev,
 537                                       struct rtl8169_private *tp,
 538                                       void __iomem *ioaddr)
 539 {
 540         unsigned long flags;
 541
 542         spin_lock_irqsave(&tp->lock, flags);
 543         if (tp->link_ok(ioaddr)) {
 544                 netif_carrier_on(dev);
 545                 if (netif_msg_ifup(tp))
 546                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
 547         } else {
 548                 if (netif_msg_ifdown(tp))
 549                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
 550                 netif_carrier_off(dev);
 551         }
 552         spin_unlock_irqrestore(&tp->lock, flags);
 553 }
 554
 555 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 556 {
 557         struct rtl8169_private *tp = netdev_priv(dev);
 558         void __iomem *ioaddr = tp->mmio_addr;
 559         u8 options;
 560
 561         wol->wolopts = 0;
 562
 563 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 564         wol->supported = WAKE_ANY;
 565
 566         spin_lock_irq(&tp->lock);
 567
 568         options = RTL_R8(Config1);
 569         if (!(options & PMEnable))
 570                 goto out_unlock;
 571
 572         options = RTL_R8(Config3);
 573         if (options & LinkUp)
 574                 wol->wolopts |= WAKE_PHY;
 575         if (options & MagicPacket)
 576                 wol->wolopts |= WAKE_MAGIC;
 577
 578         options = RTL_R8(Config5);
 579         if (options & UWF)
 580                 wol->wolopts |= WAKE_UCAST;
 581         if (options & BWF)
 582                 wol->wolopts |= WAKE_BCAST;
 583         if (options & MWF)
 584                 wol->wolopts |= WAKE_MCAST;
 585
 586 out_unlock:
 587         spin_unlock_irq(&tp->lock);
 588 }
 589
 590 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 591 {
 592         struct rtl8169_private *tp = netdev_priv(dev);
 593         void __iomem *ioaddr = tp->mmio_addr;
 594         unsigned int i;
 595         static struct {
 596                 u32 opt;
 597                 u16 reg;
 598                 u8  mask;
 599         } cfg[] = {
 600                 { WAKE_ANY,   Config1, PMEnable },
 601                 { WAKE_PHY,   Config3, LinkUp },
 602                 { WAKE_MAGIC, Config3, MagicPacket },
 603                 { WAKE_UCAST, Config5, UWF },
 604                 { WAKE_BCAST, Config5, BWF },
 605                 { WAKE_MCAST, Config5, MWF },
 606                 { WAKE_ANY,   Config5, LanWake }
 607         };
 608
 609         spin_lock_irq(&tp->lock);
 610
 611         RTL_W8(Cfg9346, Cfg9346_Unlock);
 612
 613         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 614                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 615                 if (wol->wolopts & cfg[i].opt)
 616                         options |= cfg[i].mask;
 617                 RTL_W8(cfg[i].reg, options);
 618         }
 619
 620         RTL_W8(Cfg9346, Cfg9346_Lock);
 621
 622         tp->wol_enabled = (wol->wolopts) ? 1 : 0;
 623
 624         spin_unlock_irq(&tp->lock);
 625
 626         return 0;
 627 }
 628
 629 static void rtl8169_get_drvinfo(struct net_device *dev,
 630                                 struct ethtool_drvinfo *info)
 631 {
 632         struct rtl8169_private *tp = netdev_priv(dev);
 633
 634         strcpy(info->driver, MODULENAME);
 635         strcpy(info->version, RTL8169_VERSION);
 636         strcpy(info->bus_info, pci_name(tp->pci_dev));
 637 }
 638
 639 static int rtl8169_get_regs_len(struct net_device *dev)
 640 {
 641         return R8169_REGS_SIZE;
 642 }
 643
 644 static int rtl8169_set_speed_tbi(struct net_device *dev,
 645                                  u8 autoneg, u16 speed, u8 duplex)
 646 {
 647         struct rtl8169_private *tp = netdev_priv(dev);
 648         void __iomem *ioaddr = tp->mmio_addr;
 649         int ret = 0;
 650         u32 reg;
 651
 652         reg = RTL_R32(TBICSR);
 653         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 654             (duplex == DUPLEX_FULL)) {
 655                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 656         } else if (autoneg == AUTONEG_ENABLE)
 657                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 658         else {
 659                 if (netif_msg_link(tp)) {
 660                         printk(KERN_WARNING "%s: "
 661                                "incorrect speed setting refused in TBI mode\n",
 662                                dev->name);
 663                 }
 664                 ret = -EOPNOTSUPP;
 665         }
 666
 667         return ret;
 668 }
 669
 670 static int rtl8169_set_speed_xmii(struct net_device *dev,
 671                                   u8 autoneg, u16 speed, u8 duplex)
 672 {
 673         struct rtl8169_private *tp = netdev_priv(dev);
 674         void __iomem *ioaddr = tp->mmio_addr;
 675         int auto_nego, giga_ctrl;
 676
 677         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 678         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
 679                        ADVERTISE_100HALF | ADVERTISE_100FULL);
 680         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 681         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 682
 683         if (autoneg == AUTONEG_ENABLE) {
 684                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 685                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 686                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 687         } else {
 688                 if (speed == SPEED_10)
 689                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 690                 else if (speed == SPEED_100)
 691                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
 692                 else if (speed == SPEED_1000)
 693                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 694
 695                 if (duplex == DUPLEX_HALF)
 696                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
 697
 698                 if (duplex == DUPLEX_FULL)
 699                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
 700
 701                 /* This tweak comes straight from Realtek's driver. */
 702                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
 703                     (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
 704                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
 705                 }
 706         }
 707
 708         /* The 8100e/8101e do Fast Ethernet only. */
 709         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 710             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
 711             (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
 712                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
 713                     netif_msg_link(tp)) {
 714                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
 715                                dev->name);
 716                 }
 717                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 718         }
 719
 720         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 721
 722         tp->phy_auto_nego_reg = auto_nego;
 723         tp->phy_1000_ctrl_reg = giga_ctrl;
 724
 725         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 726         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 727         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
 728         return 0;
 729 }
 730
 731 static int rtl8169_set_speed(struct net_device *dev,
 732                              u8 autoneg, u16 speed, u8 duplex)
 733 {
 734         struct rtl8169_private *tp = netdev_priv(dev);
 735         int ret;
 736
 737         ret = tp->set_speed(dev, autoneg, speed, duplex);
 738
 739         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 740                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 741
 742         return ret;
 743 }
 744
 745 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 746 {
 747         struct rtl8169_private *tp = netdev_priv(dev);
 748         unsigned long flags;
 749         int ret;
 750
 751         spin_lock_irqsave(&tp->lock, flags);
 752         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 753         spin_unlock_irqrestore(&tp->lock, flags);
 754
 755         return ret;
 756 }
 757
 758 static u32 rtl8169_get_rx_csum(struct net_device *dev)
 759 {
 760         struct rtl8169_private *tp = netdev_priv(dev);
 761
 762         return tp->cp_cmd & RxChkSum;
 763 }
 764
 765 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
 766 {
 767         struct rtl8169_private *tp = netdev_priv(dev);
 768         void __iomem *ioaddr = tp->mmio_addr;
 769         unsigned long flags;
 770
 771         spin_lock_irqsave(&tp->lock, flags);
 772
 773         if (data)
 774                 tp->cp_cmd |= RxChkSum;
 775         else
 776                 tp->cp_cmd &= ~RxChkSum;
 777
 778         RTL_W16(CPlusCmd, tp->cp_cmd);
 779         RTL_R16(CPlusCmd);
 780
 781         spin_unlock_irqrestore(&tp->lock, flags);
 782
 783         return 0;
 784 }
 785
 786 #ifdef CONFIG_R8169_VLAN
 787
 788 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 789                                       struct sk_buff *skb)
 790 {
 791         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
 792                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
 793 }
 794
 795 static void rtl8169_vlan_rx_register(struct net_device *dev,
 796                                      struct vlan_group *grp)
 797 {
 798         struct rtl8169_private *tp = netdev_priv(dev);
 799         void __iomem *ioaddr = tp->mmio_addr;
 800         unsigned long flags;
 801
 802         spin_lock_irqsave(&tp->lock, flags);
 803         tp->vlgrp = grp;
 804         if (tp->vlgrp)
 805                 tp->cp_cmd |= RxVlan;
 806         else
 807                 tp->cp_cmd &= ~RxVlan;
 808         RTL_W16(CPlusCmd, tp->cp_cmd);
 809         RTL_R16(CPlusCmd);
 810         spin_unlock_irqrestore(&tp->lock, flags);
 811 }
 812
 813 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 814                                struct sk_buff *skb)
 815 {
 816         u32 opts2 = le32_to_cpu(desc->opts2);
 817         int ret;
 818
 819         if (tp->vlgrp && (opts2 & RxVlanTag)) {
 820                 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
 821                 ret = 0;
 822         } else
 823                 ret = -1;
 824         desc->opts2 = 0;
 825         return ret;
 826 }
 827
 828 #else /* !CONFIG_R8169_VLAN */
 829
 830 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 831                                       struct sk_buff *skb)
 832 {
 833         return 0;
 834 }
 835
 836 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 837                                struct sk_buff *skb)
 838 {
 839         return -1;
 840 }
 841
 842 #endif
 843
 844 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
 845 {
 846         struct rtl8169_private *tp = netdev_priv(dev);
 847         void __iomem *ioaddr = tp->mmio_addr;
 848         u32 status;
 849
 850         cmd->supported =
 851                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
 852         cmd->port = PORT_FIBRE;
 853         cmd->transceiver = XCVR_INTERNAL;
 854
 855         status = RTL_R32(TBICSR);
 856         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
 857         cmd->autoneg = !!(status & TBINwEnable);
 858
 859         cmd->speed = SPEED_1000;
 860         cmd->duplex = DUPLEX_FULL; /* Always set */
 861 }
 862
 863 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
 864 {
 865         struct rtl8169_private *tp = netdev_priv(dev);
 866         void __iomem *ioaddr = tp->mmio_addr;
 867         u8 status;
 868
 869         cmd->supported = SUPPORTED_10baseT_Half |
 870                          SUPPORTED_10baseT_Full |
 871                          SUPPORTED_100baseT_Half |
 872                          SUPPORTED_100baseT_Full |
 873                          SUPPORTED_1000baseT_Full |
 874                          SUPPORTED_Autoneg |
 875                          SUPPORTED_TP;
 876
 877         cmd->autoneg = 1;
 878         cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
 879
 880         if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
 881                 cmd->advertising |= ADVERTISED_10baseT_Half;
 882         if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
 883                 cmd->advertising |= ADVERTISED_10baseT_Full;
 884         if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
 885                 cmd->advertising |= ADVERTISED_100baseT_Half;
 886         if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
 887                 cmd->advertising |= ADVERTISED_100baseT_Full;
 888         if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
 889                 cmd->advertising |= ADVERTISED_1000baseT_Full;
 890
 891         status = RTL_R8(PHYstatus);
 892
 893         if (status & _1000bpsF)
 894                 cmd->speed = SPEED_1000;
 895         else if (status & _100bps)
 896                 cmd->speed = SPEED_100;
 897         else if (status & _10bps)
 898                 cmd->speed = SPEED_10;
 899
 900         if (status & TxFlowCtrl)
 901                 cmd->advertising |= ADVERTISED_Asym_Pause;
 902         if (status & RxFlowCtrl)
 903                 cmd->advertising |= ADVERTISED_Pause;
 904
 905         cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
 906                       DUPLEX_FULL : DUPLEX_HALF;
 907 }
 908
 909 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 910 {
 911         struct rtl8169_private *tp = netdev_priv(dev);
 912         unsigned long flags;
 913
 914         spin_lock_irqsave(&tp->lock, flags);
 915
 916         tp->get_settings(dev, cmd);
 917
 918         spin_unlock_irqrestore(&tp->lock, flags);
 919         return 0;
 920 }
 921
 922 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 923                              void *p)
 924 {
 925         struct rtl8169_private *tp = netdev_priv(dev);
 926         unsigned long flags;
 927
 928         if (regs->len > R8169_REGS_SIZE)
 929                 regs->len = R8169_REGS_SIZE;
 930
 931         spin_lock_irqsave(&tp->lock, flags);
 932         memcpy_fromio(p, tp->mmio_addr, regs->len);
 933         spin_unlock_irqrestore(&tp->lock, flags);
 934 }
 935
 936 static u32 rtl8169_get_msglevel(struct net_device *dev)
 937 {
 938         struct rtl8169_private *tp = netdev_priv(dev);
 939
 940         return tp->msg_enable;
 941 }
 942
 943 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
 944 {
 945         struct rtl8169_private *tp = netdev_priv(dev);
 946
 947         tp->msg_enable = value;
 948 }
 949
 950 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
 951         "tx_packets",
 952         "rx_packets",
 953         "tx_errors",
 954         "rx_errors",
 955         "rx_missed",
 956         "align_errors",
 957         "tx_single_collisions",
 958         "tx_multi_collisions",
 959         "unicast",
 960         "broadcast",
 961         "multicast",
 962         "tx_aborted",
 963         "tx_underrun",
 964 };
 965
 966 struct rtl8169_counters {
 967         u64     tx_packets;
 968         u64     rx_packets;
 969         u64     tx_errors;
 970         u32     rx_errors;
 971         u16     rx_missed;
 972         u16     align_errors;
 973         u32     tx_one_collision;
 974         u32     tx_multi_collision;
 975         u64     rx_unicast;
 976         u64     rx_broadcast;
 977         u32     rx_multicast;
 978         u16     tx_aborted;
 979         u16     tx_underun;
 980 };
 981
 982 static int rtl8169_get_stats_count(struct net_device *dev)
 983 {
 984         return ARRAY_SIZE(rtl8169_gstrings);
 985 }
 986
 987 static void rtl8169_get_ethtool_stats(struct net_device *dev,
 988                                       struct ethtool_stats *stats, u64 *data)
 989 {
 990         struct rtl8169_private *tp = netdev_priv(dev);
 991         void __iomem *ioaddr = tp->mmio_addr;
 992         struct rtl8169_counters *counters;
 993         dma_addr_t paddr;
 994         u32 cmd;
 995
 996         ASSERT_RTNL();
 997
 998         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
 999         if (!counters)
1000                 return;
1001
1002         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1003         cmd = (u64)paddr & DMA_32BIT_MASK;
1004         RTL_W32(CounterAddrLow, cmd);
1005         RTL_W32(CounterAddrLow, cmd | CounterDump);
1006
1007         while (RTL_R32(CounterAddrLow) & CounterDump) {
1008                 if (msleep_interruptible(1))
1009                         break;
1010         }
1011
1012         RTL_W32(CounterAddrLow, 0);
1013         RTL_W32(CounterAddrHigh, 0);
1014
1015         data[0] = le64_to_cpu(counters->tx_packets);
1016         data[1] = le64_to_cpu(counters->rx_packets);
1017         data[2] = le64_to_cpu(counters->tx_errors);
1018         data[3] = le32_to_cpu(counters->rx_errors);
1019         data[4] = le16_to_cpu(counters->rx_missed);
1020         data[5] = le16_to_cpu(counters->align_errors);
1021         data[6] = le32_to_cpu(counters->tx_one_collision);
1022         data[7] = le32_to_cpu(counters->tx_multi_collision);
1023         data[8] = le64_to_cpu(counters->rx_unicast);
1024         data[9] = le64_to_cpu(counters->rx_broadcast);
1025         data[10] = le32_to_cpu(counters->rx_multicast);
1026         data[11] = le16_to_cpu(counters->tx_aborted);
1027         data[12] = le16_to_cpu(counters->tx_underun);
1028
1029         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1030 }
1031
1032 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1033 {
1034         switch(stringset) {
1035         case ETH_SS_STATS:
1036                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1037                 break;
1038         }
1039 }
1040
1041 static const struct ethtool_ops rtl8169_ethtool_ops = {
1042         .get_drvinfo            = rtl8169_get_drvinfo,
1043         .get_regs_len           = rtl8169_get_regs_len,
1044         .get_link               = ethtool_op_get_link,
1045         .get_settings           = rtl8169_get_settings,
1046         .set_settings           = rtl8169_set_settings,
1047         .get_msglevel           = rtl8169_get_msglevel,
1048         .set_msglevel           = rtl8169_set_msglevel,
1049         .get_rx_csum            = rtl8169_get_rx_csum,
1050         .set_rx_csum            = rtl8169_set_rx_csum,
1051         .get_tx_csum            = ethtool_op_get_tx_csum,
1052         .set_tx_csum            = ethtool_op_set_tx_csum,
1053         .get_sg                 = ethtool_op_get_sg,
1054         .set_sg                 = ethtool_op_set_sg,
1055         .get_tso                = ethtool_op_get_tso,
1056         .set_tso                = ethtool_op_set_tso,
1057         .get_regs               = rtl8169_get_regs,
1058         .get_wol                = rtl8169_get_wol,
1059         .set_wol                = rtl8169_set_wol,
1060         .get_strings            = rtl8169_get_strings,
1061         .get_stats_count        = rtl8169_get_stats_count,
1062         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1063         .get_perm_addr          = ethtool_op_get_perm_addr,
1064 };
1065
1066 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1067                                        int bitnum, int bitval)
1068 {
1069         int val;
1070
1071         val = mdio_read(ioaddr, reg);
1072         val = (bitval == 1) ?
1073                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1074         mdio_write(ioaddr, reg, val & 0xffff);
1075 }
1076
1077 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1078                                     void __iomem *ioaddr)
1079 {
1080         /*
1081          * The driver currently handles the 8168Bf and the 8168Be identically
1082          * but they can be identified more specifically through the test below
1083          * if needed:
1084          *
1085          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1086          *
1087          * Same thing for the 8101Eb and the 8101Ec:
1088          *
1089          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1090          */
1091         const struct {
1092                 u32 mask;
1093                 int mac_version;
1094         } mac_info[] = {
1095                 { 0x38800000,   RTL_GIGA_MAC_VER_15 },
1096                 { 0x38000000,   RTL_GIGA_MAC_VER_12 },
1097                 { 0x34000000,   RTL_GIGA_MAC_VER_13 },
1098                 { 0x30800000,   RTL_GIGA_MAC_VER_14 },
1099                 { 0x30000000,   RTL_GIGA_MAC_VER_11 },
1100                 { 0x98000000,   RTL_GIGA_MAC_VER_06 },
1101                 { 0x18000000,   RTL_GIGA_MAC_VER_05 },
1102                 { 0x10000000,   RTL_GIGA_MAC_VER_04 },
1103                 { 0x04000000,   RTL_GIGA_MAC_VER_03 },
1104                 { 0x00800000,   RTL_GIGA_MAC_VER_02 },
1105                 { 0x00000000,   RTL_GIGA_MAC_VER_01 }   /* Catch-all */
1106         }, *p = mac_info;
1107         u32 reg;
1108
1109         reg = RTL_R32(TxConfig) & 0xfc800000;
1110         while ((reg & p->mask) != p->mask)
1111                 p++;
1112         tp->mac_version = p->mac_version;
1113 }
1114
1115 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1116 {
1117         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1118 }
1119
1120 static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1121                                     void __iomem *ioaddr)
1122 {
1123         const struct {
1124                 u16 mask;
1125                 u16 set;
1126                 int phy_version;
1127         } phy_info[] = {
1128                 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1129                 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1130                 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1131                 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1132         }, *p = phy_info;
1133         u16 reg;
1134
1135         reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1136         while ((reg & p->mask) != p->set)
1137                 p++;
1138         tp->phy_version = p->phy_version;
1139 }
1140
1141 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1142 {
1143         struct {
1144                 int version;
1145                 char *msg;
1146                 u32 reg;
1147         } phy_print[] = {
1148                 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1149                 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1150                 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1151                 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1152                 { 0, NULL, 0x0000 }
1153         }, *p;
1154
1155         for (p = phy_print; p->msg; p++) {
1156                 if (tp->phy_version == p->version) {
1157                         dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1158                         return;
1159                 }
1160         }
1161         dprintk("phy_version == Unknown\n");
1162 }
1163
1164 static void rtl8169_hw_phy_config(struct net_device *dev)
1165 {
1166         struct rtl8169_private *tp = netdev_priv(dev);
1167         void __iomem *ioaddr = tp->mmio_addr;
1168         struct {
1169                 u16 regs[5]; /* Beware of bit-sign propagation */
1170         } phy_magic[5] = { {
1171                 { 0x0000,       //w 4 15 12 0
1172                   0x00a1,       //w 3 15 0 00a1
1173                   0x0008,       //w 2 15 0 0008
1174                   0x1020,       //w 1 15 0 1020
1175                   0x1000 } },{  //w 0 15 0 1000
1176                 { 0x7000,       //w 4 15 12 7
1177                   0xff41,       //w 3 15 0 ff41
1178                   0xde60,       //w 2 15 0 de60
1179                   0x0140,       //w 1 15 0 0140
1180                   0x0077 } },{  //w 0 15 0 0077
1181                 { 0xa000,       //w 4 15 12 a
1182                   0xdf01,       //w 3 15 0 df01
1183                   0xdf20,       //w 2 15 0 df20
1184                   0xff95,       //w 1 15 0 ff95
1185                   0xfa00 } },{  //w 0 15 0 fa00
1186                 { 0xb000,       //w 4 15 12 b
1187                   0xff41,       //w 3 15 0 ff41
1188                   0xde20,       //w 2 15 0 de20
1189                   0x0140,       //w 1 15 0 0140
1190                   0x00bb } },{  //w 0 15 0 00bb
1191                 { 0xf000,       //w 4 15 12 f
1192                   0xdf01,       //w 3 15 0 df01
1193                   0xdf20,       //w 2 15 0 df20
1194                   0xff95,       //w 1 15 0 ff95
1195                   0xbf00 }      //w 0 15 0 bf00
1196                 }
1197         }, *p = phy_magic;
1198         unsigned int i;
1199
1200         rtl8169_print_mac_version(tp);
1201         rtl8169_print_phy_version(tp);
1202
1203         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1204                 return;
1205         if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1206                 return;
1207
1208         dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1209         dprintk("Do final_reg2.cfg\n");
1210
1211         /* Shazam ! */
1212
1213         if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1214                 mdio_write(ioaddr, 31, 0x0002);
1215                 mdio_write(ioaddr,  1, 0x90d0);
1216                 mdio_write(ioaddr, 31, 0x0000);
1217                 return;
1218         }
1219
1220         /* phy config for RTL8169s mac_version C chip */
1221         mdio_write(ioaddr, 31, 0x0001);                 //w 31 2 0 1
1222         mdio_write(ioaddr, 21, 0x1000);                 //w 21 15 0 1000
1223         mdio_write(ioaddr, 24, 0x65c7);                 //w 24 15 0 65c7
1224         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1225
1226         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1227                 int val, pos = 4;
1228
1229                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1230                 mdio_write(ioaddr, pos, val);
1231                 while (--pos >= 0)
1232                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1233                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1234                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1235         }
1236         mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1237 }
1238
1239 static void rtl8169_phy_timer(unsigned long __opaque)
1240 {
1241         struct net_device *dev = (struct net_device *)__opaque;
1242         struct rtl8169_private *tp = netdev_priv(dev);
1243         struct timer_list *timer = &tp->timer;
1244         void __iomem *ioaddr = tp->mmio_addr;
1245         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1246
1247         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1248         assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1249
1250         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1251                 return;
1252
1253         spin_lock_irq(&tp->lock);
1254
1255         if (tp->phy_reset_pending(ioaddr)) {
1256                 /*
1257                  * A busy loop could burn quite a few cycles on nowadays CPU.
1258                  * Let's delay the execution of the timer for a few ticks.
1259                  */
1260                 timeout = HZ/10;
1261                 goto out_mod_timer;
1262         }
1263
1264         if (tp->link_ok(ioaddr))
1265                 goto out_unlock;
1266
1267         if (netif_msg_link(tp))
1268                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1269
1270         tp->phy_reset_enable(ioaddr);
1271
1272 out_mod_timer:
1273         mod_timer(timer, jiffies + timeout);
1274 out_unlock:
1275         spin_unlock_irq(&tp->lock);
1276 }
1277
1278 static inline void rtl8169_delete_timer(struct net_device *dev)
1279 {
1280         struct rtl8169_private *tp = netdev_priv(dev);
1281         struct timer_list *timer = &tp->timer;
1282
1283         if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1284             (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1285                 return;
1286
1287         del_timer_sync(timer);
1288 }
1289
1290 static inline void rtl8169_request_timer(struct net_device *dev)
1291 {
1292         struct rtl8169_private *tp = netdev_priv(dev);
1293         struct timer_list *timer = &tp->timer;
1294
1295         if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1296             (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1297                 return;
1298
1299         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1300 }
1301
1302 #ifdef CONFIG_NET_POLL_CONTROLLER
1303 /*
1304  * Polling 'interrupt' - used by things like netconsole to send skbs
1305  * without having to re-enable interrupts. It's not called while
1306  * the interrupt routine is executing.
1307  */
1308 static void rtl8169_netpoll(struct net_device *dev)
1309 {
1310         struct rtl8169_private *tp = netdev_priv(dev);
1311         struct pci_dev *pdev = tp->pci_dev;
1312
1313         disable_irq(pdev->irq);
1314         rtl8169_interrupt(pdev->irq, dev);
1315         enable_irq(pdev->irq);
1316 }
1317 #endif
1318
1319 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1320                                   void __iomem *ioaddr)
1321 {
1322         iounmap(ioaddr);
1323         pci_release_regions(pdev);
1324         pci_disable_device(pdev);
1325         free_netdev(dev);
1326 }
1327
1328 static void rtl8169_phy_reset(struct net_device *dev,
1329                               struct rtl8169_private *tp)
1330 {
1331         void __iomem *ioaddr = tp->mmio_addr;
1332         unsigned int i;
1333
1334         tp->phy_reset_enable(ioaddr);
1335         for (i = 0; i < 100; i++) {
1336                 if (!tp->phy_reset_pending(ioaddr))
1337                         return;
1338                 msleep(1);
1339         }
1340         if (netif_msg_link(tp))
1341                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1342 }
1343
1344 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1345 {
1346         void __iomem *ioaddr = tp->mmio_addr;
1347
1348         rtl8169_hw_phy_config(dev);
1349
1350         dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1351         RTL_W8(0x82, 0x01);
1352
1353         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1354
1355         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1356                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1357
1358         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1359                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1360                 RTL_W8(0x82, 0x01);
1361                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1362                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1363         }
1364
1365         rtl8169_phy_reset(dev, tp);
1366
1367         /*
1368          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1369          * only 8101. Don't panic.
1370          */
1371         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1372
1373         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1374                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1375 }
1376
1377 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1378 {
1379         struct rtl8169_private *tp = netdev_priv(dev);
1380         struct mii_ioctl_data *data = if_mii(ifr);
1381
1382         if (!netif_running(dev))
1383                 return -ENODEV;
1384
1385         switch (cmd) {
1386         case SIOCGMIIPHY:
1387                 data->phy_id = 32; /* Internal PHY */
1388                 return 0;
1389
1390         case SIOCGMIIREG:
1391                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1392                 return 0;
1393
1394         case SIOCSMIIREG:
1395                 if (!capable(CAP_NET_ADMIN))
1396                         return -EPERM;
1397                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1398                 return 0;
1399         }
1400         return -EOPNOTSUPP;
1401 }
1402
1403 static const struct rtl_cfg_info {
1404         void (*hw_start)(struct net_device *);
1405         unsigned int region;
1406         unsigned int align;
1407         u16 intr_event;
1408         u16 napi_event;
1409 } rtl_cfg_infos [] = {
1410         [RTL_CFG_0] = {
1411                 .hw_start       = rtl_hw_start_8169,
1412                 .region         = 1,
1413                 .align          = 2,
1414                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1415                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1416                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1417         },
1418         [RTL_CFG_1] = {
1419                 .hw_start       = rtl_hw_start_8168,
1420                 .region         = 2,
1421                 .align          = 8,
1422                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1423                                   TxErr | TxOK | RxOK | RxErr,
1424                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow
1425         },
1426         [RTL_CFG_2] = {
1427                 .hw_start       = rtl_hw_start_8101,
1428                 .region         = 2,
1429                 .align          = 8,
1430                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1431                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1432                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1433         }
1434 };
1435
1436 static int __devinit
1437 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1438 {
1439         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1440         const unsigned int region = cfg->region;
1441         struct rtl8169_private *tp;
1442         struct net_device *dev;
1443         void __iomem *ioaddr;
1444         unsigned int i;
1445         int rc;
1446
1447         if (netif_msg_drv(&debug)) {
1448                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1449                        MODULENAME, RTL8169_VERSION);
1450         }
1451
1452         dev = alloc_etherdev(sizeof (*tp));
1453         if (!dev) {
1454                 if (netif_msg_drv(&debug))
1455                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1456                 rc = -ENOMEM;
1457                 goto out;
1458         }
1459
1460         SET_MODULE_OWNER(dev);
1461         SET_NETDEV_DEV(dev, &pdev->dev);
1462         tp = netdev_priv(dev);
1463         tp->dev = dev;
1464         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1465
1466         /* enable device (incl. PCI PM wakeup and hotplug setup) */
1467         rc = pci_enable_device(pdev);
1468         if (rc < 0) {
1469                 if (netif_msg_probe(tp))
1470                         dev_err(&pdev->dev, "enable failure\n");
1471                 goto err_out_free_dev_1;
1472         }
1473
1474         rc = pci_set_mwi(pdev);
1475         if (rc < 0)
1476                 goto err_out_disable_2;
1477
1478         /* make sure PCI base addr 1 is MMIO */
1479         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1480                 if (netif_msg_probe(tp)) {
1481                         dev_err(&pdev->dev,
1482                                 "region #%d not an MMIO resource, aborting\n",
1483                                 region);
1484                 }
1485                 rc = -ENODEV;
1486                 goto err_out_mwi_3;
1487         }
1488
1489         /* check for weird/broken PCI region reporting */
1490         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1491                 if (netif_msg_probe(tp)) {
1492                         dev_err(&pdev->dev,
1493                                 "Invalid PCI region size(s), aborting\n");
1494                 }
1495                 rc = -ENODEV;
1496                 goto err_out_mwi_3;
1497         }
1498
1499         rc = pci_request_regions(pdev, MODULENAME);
1500         if (rc < 0) {
1501                 if (netif_msg_probe(tp))
1502                         dev_err(&pdev->dev, "could not request regions.\n");
1503                 goto err_out_mwi_3;
1504         }
1505
1506         tp->cp_cmd = PCIMulRW | RxChkSum;
1507
1508         if ((sizeof(dma_addr_t) > 4) &&
1509             !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1510                 tp->cp_cmd |= PCIDAC;
1511                 dev->features |= NETIF_F_HIGHDMA;
1512         } else {
1513                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1514                 if (rc < 0) {
1515                         if (netif_msg_probe(tp)) {
1516                                 dev_err(&pdev->dev,
1517                                         "DMA configuration failed.\n");
1518                         }
1519                         goto err_out_free_res_4;
1520                 }
1521         }
1522
1523         pci_set_master(pdev);
1524
1525         /* ioremap MMIO region */
1526         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1527         if (!ioaddr) {
1528                 if (netif_msg_probe(tp))
1529                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1530                 rc = -EIO;
1531                 goto err_out_free_res_4;
1532         }
1533
1534         /* Unneeded ? Don't mess with Mrs. Murphy. */
1535         rtl8169_irq_mask_and_ack(ioaddr);
1536
1537         /* Soft reset the chip. */
1538         RTL_W8(ChipCmd, CmdReset);
1539
1540         /* Check that the chip has finished the reset. */
1541         for (i = 0; i < 100; i++) {
1542                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1543                         break;
1544                 msleep_interruptible(1);
1545         }
1546
1547         /* Identify chip attached to board */
1548         rtl8169_get_mac_version(tp, ioaddr);
1549         rtl8169_get_phy_version(tp, ioaddr);
1550
1551         rtl8169_print_mac_version(tp);
1552         rtl8169_print_phy_version(tp);
1553
1554         for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1555                 if (tp->mac_version == rtl_chip_info[i].mac_version)
1556                         break;
1557         }
1558         if (i < 0) {
1559                 /* Unknown chip: assume array element #0, original RTL-8169 */
1560                 if (netif_msg_probe(tp)) {
1561                         dev_printk(KERN_DEBUG, &pdev->dev,
1562                                 "unknown chip version, assuming %s\n",
1563                                 rtl_chip_info[0].name);
1564                 }
1565                 i++;
1566         }
1567         tp->chipset = i;
1568
1569         RTL_W8(Cfg9346, Cfg9346_Unlock);
1570         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1571         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1572         RTL_W8(Cfg9346, Cfg9346_Lock);
1573
1574         if (RTL_R8(PHYstatus) & TBI_Enable) {
1575                 tp->set_speed = rtl8169_set_speed_tbi;
1576                 tp->get_settings = rtl8169_gset_tbi;
1577                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1578                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1579                 tp->link_ok = rtl8169_tbi_link_ok;
1580
1581                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1582         } else {
1583                 tp->set_speed = rtl8169_set_speed_xmii;
1584                 tp->get_settings = rtl8169_gset_xmii;
1585                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1586                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1587                 tp->link_ok = rtl8169_xmii_link_ok;
1588
1589                 dev->do_ioctl = rtl8169_ioctl;
1590         }
1591
1592         /* Get MAC address.  FIXME: read EEPROM */
1593         for (i = 0; i < MAC_ADDR_LEN; i++)
1594                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1595         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1596
1597         dev->open = rtl8169_open;
1598         dev->hard_start_xmit = rtl8169_start_xmit;
1599         dev->get_stats = rtl8169_get_stats;
1600         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1601         dev->stop = rtl8169_close;
1602         dev->tx_timeout = rtl8169_tx_timeout;
1603         dev->set_multicast_list = rtl_set_rx_mode;
1604         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1605         dev->irq = pdev->irq;
1606         dev->base_addr = (unsigned long) ioaddr;
1607         dev->change_mtu = rtl8169_change_mtu;
1608
1609 #ifdef CONFIG_R8169_NAPI
1610         dev->poll = rtl8169_poll;
1611         dev->weight = R8169_NAPI_WEIGHT;
1612 #endif
1613
1614 #ifdef CONFIG_R8169_VLAN
1615         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1616         dev->vlan_rx_register = rtl8169_vlan_rx_register;
1617 #endif
1618
1619 #ifdef CONFIG_NET_POLL_CONTROLLER
1620         dev->poll_controller = rtl8169_netpoll;
1621 #endif
1622
1623         tp->intr_mask = 0xffff;
1624         tp->pci_dev = pdev;
1625         tp->mmio_addr = ioaddr;
1626         tp->align = cfg->align;
1627         tp->hw_start = cfg->hw_start;
1628         tp->intr_event = cfg->intr_event;
1629         tp->napi_event = cfg->napi_event;
1630
1631         init_timer(&tp->timer);
1632         tp->timer.data = (unsigned long) dev;
1633         tp->timer.function = rtl8169_phy_timer;
1634
1635         spin_lock_init(&tp->lock);
1636
1637         rc = register_netdev(dev);
1638         if (rc < 0)
1639                 goto err_out_unmap_5;
1640
1641         pci_set_drvdata(pdev, dev);
1642
1643         if (netif_msg_probe(tp)) {
1644                 printk(KERN_INFO "%s: %s at 0x%lx, "
1645                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1646                        "IRQ %d\n",
1647                        dev->name,
1648                        rtl_chip_info[tp->chipset].name,
1649                        dev->base_addr,
1650                        dev->dev_addr[0], dev->dev_addr[1],
1651                        dev->dev_addr[2], dev->dev_addr[3],
1652                        dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1653         }
1654
1655         rtl8169_init_phy(dev, tp);
1656
1657 out:
1658         return rc;
1659
1660 err_out_unmap_5:
1661         iounmap(ioaddr);
1662 err_out_free_res_4:
1663         pci_release_regions(pdev);
1664 err_out_mwi_3:
1665         pci_clear_mwi(pdev);
1666 err_out_disable_2:
1667         pci_disable_device(pdev);
1668 err_out_free_dev_1:
1669         free_netdev(dev);
1670         goto out;
1671 }
1672
1673 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1674 {
1675         struct net_device *dev = pci_get_drvdata(pdev);
1676         struct rtl8169_private *tp = netdev_priv(dev);
1677
1678         flush_scheduled_work();
1679
1680         unregister_netdev(dev);
1681         rtl8169_release_board(pdev, dev, tp->mmio_addr);
1682         pci_set_drvdata(pdev, NULL);
1683 }
1684
1685 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1686                                   struct net_device *dev)
1687 {
1688         unsigned int mtu = dev->mtu;
1689
1690         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1691 }
1692
1693 static int rtl8169_open(struct net_device *dev)
1694 {
1695         struct rtl8169_private *tp = netdev_priv(dev);
1696         struct pci_dev *pdev = tp->pci_dev;
1697         int retval = -ENOMEM;
1698
1699
1700         rtl8169_set_rxbufsize(tp, dev);
1701
1702         /*
1703          * Rx and Tx desscriptors needs 256 bytes alignment.
1704          * pci_alloc_consistent provides more.
1705          */
1706         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1707                                                &tp->TxPhyAddr);
1708         if (!tp->TxDescArray)
1709                 goto out;
1710
1711         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1712                                                &tp->RxPhyAddr);
1713         if (!tp->RxDescArray)
1714                 goto err_free_tx_0;
1715
1716         retval = rtl8169_init_ring(dev);
1717         if (retval < 0)
1718                 goto err_free_rx_1;
1719
1720         INIT_DELAYED_WORK(&tp->task, NULL);
1721
1722         smp_mb();
1723
1724         retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1725                              dev->name, dev);
1726         if (retval < 0)
1727                 goto err_release_ring_2;
1728
1729         rtl_hw_start(dev);
1730
1731         rtl8169_request_timer(dev);
1732
1733         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1734 out:
1735         return retval;
1736
1737 err_release_ring_2:
1738         rtl8169_rx_clear(tp);
1739 err_free_rx_1:
1740         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1741                             tp->RxPhyAddr);
1742 err_free_tx_0:
1743         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1744                             tp->TxPhyAddr);
1745         goto out;
1746 }
1747
1748 static void rtl8169_hw_reset(void __iomem *ioaddr)
1749 {
1750         /* Disable interrupts */
1751         rtl8169_irq_mask_and_ack(ioaddr);
1752
1753         /* Reset the chipset */
1754         RTL_W8(ChipCmd, CmdReset);
1755
1756         /* PCI commit */
1757         RTL_R8(ChipCmd);
1758 }
1759
1760 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1761 {
1762         void __iomem *ioaddr = tp->mmio_addr;
1763         u32 cfg = rtl8169_rx_config;
1764
1765         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1766         RTL_W32(RxConfig, cfg);
1767
1768         /* Set DMA burst size and Interframe Gap Time */
1769         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1770                 (InterFrameGap << TxInterFrameGapShift));
1771 }
1772
1773 static void rtl_hw_start(struct net_device *dev)
1774 {
1775         struct rtl8169_private *tp = netdev_priv(dev);
1776         void __iomem *ioaddr = tp->mmio_addr;
1777         unsigned int i;
1778
1779         /* Soft reset the chip. */
1780         RTL_W8(ChipCmd, CmdReset);
1781
1782         /* Check that the chip has finished the reset. */
1783         for (i = 0; i < 100; i++) {
1784                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1785                         break;
1786                 msleep_interruptible(1);
1787         }
1788
1789         tp->hw_start(dev);
1790
1791         netif_start_queue(dev);
1792 }
1793
1794
1795 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1796                                          void __iomem *ioaddr)
1797 {
1798         /*
1799          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1800          * register to be written before TxDescAddrLow to work.
1801          * Switching from MMIO to I/O access fixes the issue as well.
1802          */
1803         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1804         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1805         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1806         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1807 }
1808
1809 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1810 {
1811         u16 cmd;
1812
1813         cmd = RTL_R16(CPlusCmd);
1814         RTL_W16(CPlusCmd, cmd);
1815         return cmd;
1816 }
1817
1818 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1819 {
1820         /* Low hurts. Let's disable the filtering. */
1821         RTL_W16(RxMaxSize, 16383);
1822 }
1823
1824 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1825 {
1826         struct {
1827                 u32 mac_version;
1828                 u32 clk;
1829                 u32 val;
1830         } cfg2_info [] = {
1831                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1832                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1833                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1834                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1835         }, *p = cfg2_info;
1836         unsigned int i;
1837         u32 clk;
1838
1839         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1840         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1841                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1842                         RTL_W32(0x7c, p->val);
1843                         break;
1844                 }
1845         }
1846 }
1847
1848 static void rtl_hw_start_8169(struct net_device *dev)
1849 {
1850         struct rtl8169_private *tp = netdev_priv(dev);
1851         void __iomem *ioaddr = tp->mmio_addr;
1852         struct pci_dev *pdev = tp->pci_dev;
1853
1854         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1855                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1856                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1857         }
1858
1859         RTL_W8(Cfg9346, Cfg9346_Unlock);
1860         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1861             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1862             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1863             (tp->mac_version == RTL_GIGA_MAC_VER_04))
1864                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1865
1866         RTL_W8(EarlyTxThres, EarlyTxThld);
1867
1868         rtl_set_rx_max_size(ioaddr);
1869
1870         rtl_set_rx_tx_config_registers(tp);
1871
1872         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1873
1874         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1875             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1876                 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1877                         "Bit-3 and bit-14 MUST be 1\n");
1878                 tp->cp_cmd |= (1 << 14);
1879         }
1880
1881         RTL_W16(CPlusCmd, tp->cp_cmd);
1882
1883         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1884
1885         /*
1886          * Undocumented corner. Supposedly:
1887          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1888          */
1889         RTL_W16(IntrMitigate, 0x0000);
1890
1891         rtl_set_rx_tx_desc_registers(tp, ioaddr);
1892
1893         RTL_W8(Cfg9346, Cfg9346_Lock);
1894
1895         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1896         RTL_R8(IntrMask);
1897
1898         RTL_W32(RxMissed, 0);
1899
1900         rtl_set_rx_mode(dev);
1901
1902         /* no early-rx interrupts */
1903         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1904
1905         /* Enable all known interrupts by setting the interrupt mask. */
1906         RTL_W16(IntrMask, tp->intr_event);
1907
1908         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1909 }
1910
1911 static void rtl_hw_start_8168(struct net_device *dev)
1912 {
1913         struct rtl8169_private *tp = netdev_priv(dev);
1914         void __iomem *ioaddr = tp->mmio_addr;
1915         struct pci_dev *pdev = tp->pci_dev;
1916         u8 ctl;
1917
1918         RTL_W8(Cfg9346, Cfg9346_Unlock);
1919
1920         RTL_W8(EarlyTxThres, EarlyTxThld);
1921
1922         rtl_set_rx_max_size(ioaddr);
1923
1924         rtl_set_rx_tx_config_registers(tp);
1925
1926         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
1927
1928         RTL_W16(CPlusCmd, tp->cp_cmd);
1929
1930         /* Tx performance tweak. */
1931         pci_read_config_byte(pdev, 0x69, &ctl);
1932         ctl = (ctl & ~0x70) | 0x50;
1933         pci_write_config_byte(pdev, 0x69, ctl);
1934
1935         RTL_W16(IntrMitigate, 0x5151);
1936
1937         /* Work around for RxFIFO overflow. */
1938         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
1939                 tp->intr_event |= RxFIFOOver | PCSTimeout;
1940                 tp->intr_event &= ~RxOverflow;
1941         }
1942
1943         rtl_set_rx_tx_desc_registers(tp, ioaddr);
1944
1945         RTL_W8(Cfg9346, Cfg9346_Lock);
1946
1947         RTL_R8(IntrMask);
1948
1949         RTL_W32(RxMissed, 0);
1950
1951         rtl_set_rx_mode(dev);
1952
1953         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1954
1955         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1956
1957         RTL_W16(IntrMask, tp->intr_event);
1958 }
1959
1960 static void rtl_hw_start_8101(struct net_device *dev)
1961 {
1962         struct rtl8169_private *tp = netdev_priv(dev);
1963         void __iomem *ioaddr = tp->mmio_addr;
1964         struct pci_dev *pdev = tp->pci_dev;
1965
1966         if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
1967                 pci_write_config_word(pdev, 0x68, 0x00);
1968                 pci_write_config_word(pdev, 0x69, 0x08);
1969         }
1970
1971         RTL_W8(Cfg9346, Cfg9346_Unlock);
1972
1973         RTL_W8(EarlyTxThres, EarlyTxThld);
1974
1975         rtl_set_rx_max_size(ioaddr);
1976
1977         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1978
1979         RTL_W16(CPlusCmd, tp->cp_cmd);
1980
1981         RTL_W16(IntrMitigate, 0x0000);
1982
1983         rtl_set_rx_tx_desc_registers(tp, ioaddr);
1984
1985         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1986         rtl_set_rx_tx_config_registers(tp);
1987
1988         RTL_W8(Cfg9346, Cfg9346_Lock);
1989
1990         RTL_R8(IntrMask);
1991
1992         RTL_W32(RxMissed, 0);
1993
1994         rtl_set_rx_mode(dev);
1995
1996         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1997
1998         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
1999
2000         RTL_W16(IntrMask, tp->intr_event);
2001 }
2002
2003 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2004 {
2005         struct rtl8169_private *tp = netdev_priv(dev);
2006         int ret = 0;
2007
2008         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2009                 return -EINVAL;
2010
2011         dev->mtu = new_mtu;
2012
2013         if (!netif_running(dev))
2014                 goto out;
2015
2016         rtl8169_down(dev);
2017
2018         rtl8169_set_rxbufsize(tp, dev);
2019
2020         ret = rtl8169_init_ring(dev);
2021         if (ret < 0)
2022                 goto out;
2023
2024         netif_poll_enable(dev);
2025
2026         rtl_hw_start(dev);
2027
2028         rtl8169_request_timer(dev);
2029
2030 out:
2031         return ret;
2032 }
2033
2034 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2035 {
2036         desc->addr = 0x0badbadbadbadbadull;
2037         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2038 }
2039
2040 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2041                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2042 {
2043         struct pci_dev *pdev = tp->pci_dev;
2044
2045         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2046                          PCI_DMA_FROMDEVICE);
2047         dev_kfree_skb(*sk_buff);
2048         *sk_buff = NULL;
2049         rtl8169_make_unusable_by_asic(desc);
2050 }
2051
2052 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2053 {
2054         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2055
2056         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2057 }
2058
2059 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2060                                        u32 rx_buf_sz)
2061 {
2062         desc->addr = cpu_to_le64(mapping);
2063         wmb();
2064         rtl8169_mark_to_asic(desc, rx_buf_sz);
2065 }
2066
2067 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2068                                             struct net_device *dev,
2069                                             struct RxDesc *desc, int rx_buf_sz,
2070                                             unsigned int align)
2071 {
2072         struct sk_buff *skb;
2073         dma_addr_t mapping;
2074
2075         skb = netdev_alloc_skb(dev, rx_buf_sz + align);
2076         if (!skb)
2077                 goto err_out;
2078
2079         skb_reserve(skb, (align - 1) & (unsigned long)skb->data);
2080
2081         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2082                                  PCI_DMA_FROMDEVICE);
2083
2084         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2085 out:
2086         return skb;
2087
2088 err_out:
2089         rtl8169_make_unusable_by_asic(desc);
2090         goto out;
2091 }
2092
2093 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2094 {
2095         unsigned int i;
2096
2097         for (i = 0; i < NUM_RX_DESC; i++) {
2098                 if (tp->Rx_skbuff[i]) {
2099                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2100                                             tp->RxDescArray + i);
2101                 }
2102         }
2103 }
2104
2105 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2106                            u32 start, u32 end)
2107 {
2108         u32 cur;
2109
2110         for (cur = start; end - cur != 0; cur++) {
2111                 struct sk_buff *skb;
2112                 unsigned int i = cur % NUM_RX_DESC;
2113
2114                 WARN_ON((s32)(end - cur) < 0);
2115
2116                 if (tp->Rx_skbuff[i])
2117                         continue;
2118
2119                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2120                                            tp->RxDescArray + i,
2121                                            tp->rx_buf_sz, tp->align);
2122                 if (!skb)
2123                         break;
2124
2125                 tp->Rx_skbuff[i] = skb;
2126         }
2127         return cur - start;
2128 }
2129
2130 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2131 {
2132         desc->opts1 |= cpu_to_le32(RingEnd);
2133 }
2134
2135 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2136 {
2137         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2138 }
2139
2140 static int rtl8169_init_ring(struct net_device *dev)
2141 {
2142         struct rtl8169_private *tp = netdev_priv(dev);
2143
2144         rtl8169_init_ring_indexes(tp);
2145
2146         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2147         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2148
2149         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2150                 goto err_out;
2151
2152         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2153
2154         return 0;
2155
2156 err_out:
2157         rtl8169_rx_clear(tp);
2158         return -ENOMEM;
2159 }
2160
2161 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2162                                  struct TxDesc *desc)
2163 {
2164         unsigned int len = tx_skb->len;
2165
2166         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2167         desc->opts1 = 0x00;
2168         desc->opts2 = 0x00;
2169         desc->addr = 0x00;
2170         tx_skb->len = 0;
2171 }
2172
2173 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2174 {
2175         unsigned int i;
2176
2177         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2178                 unsigned int entry = i % NUM_TX_DESC;
2179                 struct ring_info *tx_skb = tp->tx_skb + entry;
2180                 unsigned int len = tx_skb->len;
2181
2182                 if (len) {
2183                         struct sk_buff *skb = tx_skb->skb;
2184
2185                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2186                                              tp->TxDescArray + entry);
2187                         if (skb) {
2188                                 dev_kfree_skb(skb);
2189                                 tx_skb->skb = NULL;
2190                         }
2191                         tp->stats.tx_dropped++;
2192                 }
2193         }
2194         tp->cur_tx = tp->dirty_tx = 0;
2195 }
2196
2197 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2198 {
2199         struct rtl8169_private *tp = netdev_priv(dev);
2200
2201         PREPARE_DELAYED_WORK(&tp->task, task);
2202         schedule_delayed_work(&tp->task, 4);
2203 }
2204
2205 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2206 {
2207         struct rtl8169_private *tp = netdev_priv(dev);
2208         void __iomem *ioaddr = tp->mmio_addr;
2209
2210         synchronize_irq(dev->irq);
2211
2212         /* Wait for any pending NAPI task to complete */
2213         netif_poll_disable(dev);
2214
2215         rtl8169_irq_mask_and_ack(ioaddr);
2216
2217         netif_poll_enable(dev);
2218 }
2219
2220 static void rtl8169_reinit_task(struct work_struct *work)
2221 {
2222         struct rtl8169_private *tp =
2223                 container_of(work, struct rtl8169_private, task.work);
2224         struct net_device *dev = tp->dev;
2225         int ret;
2226
2227         rtnl_lock();
2228
2229         if (!netif_running(dev))
2230                 goto out_unlock;
2231
2232         rtl8169_wait_for_quiescence(dev);
2233         rtl8169_close(dev);
2234
2235         ret = rtl8169_open(dev);
2236         if (unlikely(ret < 0)) {
2237                 if (net_ratelimit() && netif_msg_drv(tp)) {
2238                         printk(PFX KERN_ERR "%s: reinit failure (status = %d)."
2239                                " Rescheduling.\n", dev->name, ret);
2240                 }
2241                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2242         }
2243
2244 out_unlock:
2245         rtnl_unlock();
2246 }
2247
2248 static void rtl8169_reset_task(struct work_struct *work)
2249 {
2250         struct rtl8169_private *tp =
2251                 container_of(work, struct rtl8169_private, task.work);
2252         struct net_device *dev = tp->dev;
2253
2254         rtnl_lock();
2255
2256         if (!netif_running(dev))
2257                 goto out_unlock;
2258
2259         rtl8169_wait_for_quiescence(dev);
2260
2261         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2262         rtl8169_tx_clear(tp);
2263
2264         if (tp->dirty_rx == tp->cur_rx) {
2265                 rtl8169_init_ring_indexes(tp);
2266                 rtl_hw_start(dev);
2267                 netif_wake_queue(dev);
2268         } else {
2269                 if (net_ratelimit() && netif_msg_intr(tp)) {
2270                         printk(PFX KERN_EMERG "%s: Rx buffers shortage\n",
2271                                dev->name);
2272                 }
2273                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2274         }
2275
2276 out_unlock:
2277         rtnl_unlock();
2278 }
2279
2280 static void rtl8169_tx_timeout(struct net_device *dev)
2281 {
2282         struct rtl8169_private *tp = netdev_priv(dev);
2283
2284         rtl8169_hw_reset(tp->mmio_addr);
2285
2286         /* Let's wait a bit while any (async) irq lands on */
2287         rtl8169_schedule_work(dev, rtl8169_reset_task);
2288 }
2289
2290 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2291                               u32 opts1)
2292 {
2293         struct skb_shared_info *info = skb_shinfo(skb);
2294         unsigned int cur_frag, entry;
2295         struct TxDesc *txd;
2296
2297         entry = tp->cur_tx;
2298         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2299                 skb_frag_t *frag = info->frags + cur_frag;
2300                 dma_addr_t mapping;
2301                 u32 status, len;
2302                 void *addr;
2303
2304                 entry = (entry + 1) % NUM_TX_DESC;
2305
2306                 txd = tp->TxDescArray + entry;
2307                 len = frag->size;
2308                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2309                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2310
2311                 /* anti gcc 2.95.3 bugware (sic) */
2312                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2313
2314                 txd->opts1 = cpu_to_le32(status);
2315                 txd->addr = cpu_to_le64(mapping);
2316
2317                 tp->tx_skb[entry].len = len;
2318         }
2319
2320         if (cur_frag) {
2321                 tp->tx_skb[entry].skb = skb;
2322                 txd->opts1 |= cpu_to_le32(LastFrag);
2323         }
2324
2325         return cur_frag;
2326 }
2327
2328 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2329 {
2330         if (dev->features & NETIF_F_TSO) {
2331                 u32 mss = skb_shinfo(skb)->gso_size;
2332
2333                 if (mss)
2334                         return LargeSend | ((mss & MSSMask) << MSSShift);
2335         }
2336         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2337                 const struct iphdr *ip = ip_hdr(skb);
2338
2339                 if (ip->protocol == IPPROTO_TCP)
2340                         return IPCS | TCPCS;
2341                 else if (ip->protocol == IPPROTO_UDP)
2342                         return IPCS | UDPCS;
2343                 WARN_ON(1);     /* we need a WARN() */
2344         }
2345         return 0;
2346 }
2347
2348 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2349 {
2350         struct rtl8169_private *tp = netdev_priv(dev);
2351         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2352         struct TxDesc *txd = tp->TxDescArray + entry;
2353         void __iomem *ioaddr = tp->mmio_addr;
2354         dma_addr_t mapping;
2355         u32 status, len;
2356         u32 opts1;
2357         int ret = NETDEV_TX_OK;
2358
2359         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2360                 if (netif_msg_drv(tp)) {
2361                         printk(KERN_ERR
2362                                "%s: BUG! Tx Ring full when queue awake!\n",
2363                                dev->name);
2364                 }
2365                 goto err_stop;
2366         }
2367
2368         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2369                 goto err_stop;
2370
2371         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2372
2373         frags = rtl8169_xmit_frags(tp, skb, opts1);
2374         if (frags) {
2375                 len = skb_headlen(skb);
2376                 opts1 |= FirstFrag;
2377         } else {
2378                 len = skb->len;
2379
2380                 if (unlikely(len < ETH_ZLEN)) {
2381                         if (skb_padto(skb, ETH_ZLEN))
2382                                 goto err_update_stats;
2383                         len = ETH_ZLEN;
2384                 }
2385
2386                 opts1 |= FirstFrag | LastFrag;
2387                 tp->tx_skb[entry].skb = skb;
2388         }
2389
2390         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2391
2392         tp->tx_skb[entry].len = len;
2393         txd->addr = cpu_to_le64(mapping);
2394         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2395
2396         wmb();
2397
2398         /* anti gcc 2.95.3 bugware (sic) */
2399         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2400         txd->opts1 = cpu_to_le32(status);
2401
2402         dev->trans_start = jiffies;
2403
2404         tp->cur_tx += frags + 1;
2405
2406         smp_wmb();
2407
2408         RTL_W8(TxPoll, 0x40);   /* set polling bit */
2409
2410         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2411                 netif_stop_queue(dev);
2412                 smp_rmb();
2413                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2414                         netif_wake_queue(dev);
2415         }
2416
2417 out:
2418         return ret;
2419
2420 err_stop:
2421         netif_stop_queue(dev);
2422         ret = NETDEV_TX_BUSY;
2423 err_update_stats:
2424         tp->stats.tx_dropped++;
2425         goto out;
2426 }
2427
2428 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2429 {
2430         struct rtl8169_private *tp = netdev_priv(dev);
2431         struct pci_dev *pdev = tp->pci_dev;
2432         void __iomem *ioaddr = tp->mmio_addr;
2433         u16 pci_status, pci_cmd;
2434
2435         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2436         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2437
2438         if (netif_msg_intr(tp)) {
2439                 printk(KERN_ERR
2440                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2441                        dev->name, pci_cmd, pci_status);
2442         }
2443
2444         /*
2445          * The recovery sequence below admits a very elaborated explanation:
2446          * - it seems to work;
2447          * - I did not see what else could be done;
2448          * - it makes iop3xx happy.
2449          *
2450          * Feel free to adjust to your needs.
2451          */
2452         if (pdev->broken_parity_status)
2453                 pci_cmd &= ~PCI_COMMAND_PARITY;
2454         else
2455                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2456
2457         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2458
2459         pci_write_config_word(pdev, PCI_STATUS,
2460                 pci_status & (PCI_STATUS_DETECTED_PARITY |
2461                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2462                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2463
2464         /* The infamous DAC f*ckup only happens at boot time */
2465         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2466                 if (netif_msg_intr(tp))
2467                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2468                 tp->cp_cmd &= ~PCIDAC;
2469                 RTL_W16(CPlusCmd, tp->cp_cmd);
2470                 dev->features &= ~NETIF_F_HIGHDMA;
2471         }
2472
2473         rtl8169_hw_reset(ioaddr);
2474
2475         rtl8169_schedule_work(dev, rtl8169_reinit_task);
2476 }
2477
2478 static void rtl8169_tx_interrupt(struct net_device *dev,
2479                                  struct rtl8169_private *tp,
2480                                  void __iomem *ioaddr)
2481 {
2482         unsigned int dirty_tx, tx_left;
2483
2484         dirty_tx = tp->dirty_tx;
2485         smp_rmb();
2486         tx_left = tp->cur_tx - dirty_tx;
2487
2488         while (tx_left > 0) {
2489                 unsigned int entry = dirty_tx % NUM_TX_DESC;
2490                 struct ring_info *tx_skb = tp->tx_skb + entry;
2491                 u32 len = tx_skb->len;
2492                 u32 status;
2493
2494                 rmb();
2495                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2496                 if (status & DescOwn)
2497                         break;
2498
2499                 tp->stats.tx_bytes += len;
2500                 tp->stats.tx_packets++;
2501
2502                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2503
2504                 if (status & LastFrag) {
2505                         dev_kfree_skb_irq(tx_skb->skb);
2506                         tx_skb->skb = NULL;
2507                 }
2508                 dirty_tx++;
2509                 tx_left--;
2510         }
2511
2512         if (tp->dirty_tx != dirty_tx) {
2513                 tp->dirty_tx = dirty_tx;
2514                 smp_wmb();
2515                 if (netif_queue_stopped(dev) &&
2516                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2517                         netif_wake_queue(dev);
2518                 }
2519         }
2520 }
2521
2522 static inline int rtl8169_fragmented_frame(u32 status)
2523 {
2524         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2525 }
2526
2527 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2528 {
2529         u32 opts1 = le32_to_cpu(desc->opts1);
2530         u32 status = opts1 & RxProtoMask;
2531
2532         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2533             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2534             ((status == RxProtoIP) && !(opts1 & IPFail)))
2535                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2536         else
2537                 skb->ip_summed = CHECKSUM_NONE;
2538 }
2539
2540 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2541                                        struct rtl8169_private *tp, int pkt_size,
2542                                        dma_addr_t addr)
2543 {
2544         struct sk_buff *skb;
2545         bool done = false;
2546
2547         if (pkt_size >= rx_copybreak)
2548                 goto out;
2549
2550         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2551         if (!skb)
2552                 goto out;
2553
2554         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2555                                     PCI_DMA_FROMDEVICE);
2556         skb_reserve(skb, NET_IP_ALIGN);
2557         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2558         *sk_buff = skb;
2559         done = true;
2560 out:
2561         return done;
2562 }
2563
2564 static int rtl8169_rx_interrupt(struct net_device *dev,
2565                                 struct rtl8169_private *tp,
2566                                 void __iomem *ioaddr)
2567 {
2568         unsigned int cur_rx, rx_left;
2569         unsigned int delta, count;
2570
2571         cur_rx = tp->cur_rx;
2572         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2573         rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2574
2575         for (; rx_left > 0; rx_left--, cur_rx++) {
2576                 unsigned int entry = cur_rx % NUM_RX_DESC;
2577                 struct RxDesc *desc = tp->RxDescArray + entry;
2578                 u32 status;
2579
2580                 rmb();
2581                 status = le32_to_cpu(desc->opts1);
2582
2583                 if (status & DescOwn)
2584                         break;
2585                 if (unlikely(status & RxRES)) {
2586                         if (netif_msg_rx_err(tp)) {
2587                                 printk(KERN_INFO
2588                                        "%s: Rx ERROR. status = %08x\n",
2589                                        dev->name, status);
2590                         }
2591                         tp->stats.rx_errors++;
2592                         if (status & (RxRWT | RxRUNT))
2593                                 tp->stats.rx_length_errors++;
2594                         if (status & RxCRC)
2595                                 tp->stats.rx_crc_errors++;
2596                         if (status & RxFOVF) {
2597                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2598                                 tp->stats.rx_fifo_errors++;
2599                         }
2600                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2601                 } else {
2602                         struct sk_buff *skb = tp->Rx_skbuff[entry];
2603                         dma_addr_t addr = le64_to_cpu(desc->addr);
2604                         int pkt_size = (status & 0x00001FFF) - 4;
2605                         struct pci_dev *pdev = tp->pci_dev;
2606
2607                         /*
2608                          * The driver does not support incoming fragmented
2609                          * frames. They are seen as a symptom of over-mtu
2610                          * sized frames.
2611                          */
2612                         if (unlikely(rtl8169_fragmented_frame(status))) {
2613                                 tp->stats.rx_dropped++;
2614                                 tp->stats.rx_length_errors++;
2615                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2616                                 continue;
2617                         }
2618
2619                         rtl8169_rx_csum(skb, desc);
2620
2621                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2622                                 pci_dma_sync_single_for_device(pdev, addr,
2623                                         pkt_size, PCI_DMA_FROMDEVICE);
2624                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2625                         } else {
2626                                 pci_unmap_single(pdev, addr, pkt_size,
2627                                                  PCI_DMA_FROMDEVICE);
2628                                 tp->Rx_skbuff[entry] = NULL;
2629                         }
2630
2631                         skb_put(skb, pkt_size);
2632                         skb->protocol = eth_type_trans(skb, dev);
2633
2634                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2635                                 rtl8169_rx_skb(skb);
2636
2637                         dev->last_rx = jiffies;
2638                         tp->stats.rx_bytes += pkt_size;
2639                         tp->stats.rx_packets++;
2640                 }
2641
2642                 /* Work around for AMD plateform. */
2643                 if ((desc->opts2 & 0xfffe000) &&
2644                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2645                         desc->opts2 = 0;
2646                         cur_rx++;
2647                 }
2648         }
2649
2650         count = cur_rx - tp->cur_rx;
2651         tp->cur_rx = cur_rx;
2652
2653         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2654         if (!delta && count && netif_msg_intr(tp))
2655                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2656         tp->dirty_rx += delta;
2657
2658         /*
2659          * FIXME: until there is periodic timer to try and refill the ring,
2660          * a temporary shortage may definitely kill the Rx process.
2661          * - disable the asic to try and avoid an overflow and kick it again
2662          *   after refill ?
2663          * - how do others driver handle this condition (Uh oh...).
2664          */
2665         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2666                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2667
2668         return count;
2669 }
2670
2671 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2672 {
2673         struct net_device *dev = dev_instance;
2674         struct rtl8169_private *tp = netdev_priv(dev);
2675         int boguscnt = max_interrupt_work;
2676         void __iomem *ioaddr = tp->mmio_addr;
2677         int status;
2678         int handled = 0;
2679
2680         do {
2681                 status = RTL_R16(IntrStatus);
2682
2683                 /* hotplug/major error/no more work/shared irq */
2684                 if ((status == 0xFFFF) || !status)
2685                         break;
2686
2687                 handled = 1;
2688
2689                 if (unlikely(!netif_running(dev))) {
2690                         rtl8169_asic_down(ioaddr);
2691                         goto out;
2692                 }
2693
2694                 status &= tp->intr_mask;
2695                 RTL_W16(IntrStatus,
2696                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
2697
2698                 if (!(status & tp->intr_event))
2699                         break;
2700
2701                 /* Work around for rx fifo overflow */
2702                 if (unlikely(status & RxFIFOOver) &&
2703                     (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2704                         netif_stop_queue(dev);
2705                         rtl8169_tx_timeout(dev);
2706                         break;
2707                 }
2708
2709                 if (unlikely(status & SYSErr)) {
2710                         rtl8169_pcierr_interrupt(dev);
2711                         break;
2712                 }
2713
2714                 if (status & LinkChg)
2715                         rtl8169_check_link_status(dev, tp, ioaddr);
2716
2717 #ifdef CONFIG_R8169_NAPI
2718                 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2719                 tp->intr_mask = ~tp->napi_event;
2720
2721                 if (likely(netif_rx_schedule_prep(dev)))
2722                         __netif_rx_schedule(dev);
2723                 else if (netif_msg_intr(tp)) {
2724                         printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2725                                dev->name, status);
2726                 }
2727                 break;
2728 #else
2729                 /* Rx interrupt */
2730                 if (status & (RxOK | RxOverflow | RxFIFOOver))
2731                         rtl8169_rx_interrupt(dev, tp, ioaddr);
2732
2733                 /* Tx interrupt */
2734                 if (status & (TxOK | TxErr))
2735                         rtl8169_tx_interrupt(dev, tp, ioaddr);
2736 #endif
2737
2738                 boguscnt--;
2739         } while (boguscnt > 0);
2740
2741         if (boguscnt <= 0) {
2742                 if (netif_msg_intr(tp) && net_ratelimit() ) {
2743                         printk(KERN_WARNING
2744                                "%s: Too much work at interrupt!\n", dev->name);
2745                 }
2746                 /* Clear all interrupt sources. */
2747                 RTL_W16(IntrStatus, 0xffff);
2748         }
2749 out:
2750         return IRQ_RETVAL(handled);
2751 }
2752
2753 #ifdef CONFIG_R8169_NAPI
2754 static int rtl8169_poll(struct net_device *dev, int *budget)
2755 {
2756         unsigned int work_done, work_to_do = min(*budget, dev->quota);
2757         struct rtl8169_private *tp = netdev_priv(dev);
2758         void __iomem *ioaddr = tp->mmio_addr;
2759
2760         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2761         rtl8169_tx_interrupt(dev, tp, ioaddr);
2762
2763         *budget -= work_done;
2764         dev->quota -= work_done;
2765
2766         if (work_done < work_to_do) {
2767                 netif_rx_complete(dev);
2768                 tp->intr_mask = 0xffff;
2769                 /*
2770                  * 20040426: the barrier is not strictly required but the
2771                  * behavior of the irq handler could be less predictable
2772                  * without it. Btw, the lack of flush for the posted pci
2773                  * write is safe - FR
2774                  */
2775                 smp_wmb();
2776                 RTL_W16(IntrMask, tp->intr_event);
2777         }
2778
2779         return (work_done >= work_to_do);
2780 }
2781 #endif
2782
2783 static void rtl8169_down(struct net_device *dev)
2784 {
2785         struct rtl8169_private *tp = netdev_priv(dev);
2786         void __iomem *ioaddr = tp->mmio_addr;
2787         unsigned int poll_locked = 0;
2788         unsigned int intrmask;
2789
2790         rtl8169_delete_timer(dev);
2791
2792         netif_stop_queue(dev);
2793
2794 core_down:
2795         spin_lock_irq(&tp->lock);
2796
2797         rtl8169_asic_down(ioaddr);
2798
2799         /* Update the error counts. */
2800         tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2801         RTL_W32(RxMissed, 0);
2802
2803         spin_unlock_irq(&tp->lock);
2804
2805         synchronize_irq(dev->irq);
2806
2807         if (!poll_locked) {
2808                 netif_poll_disable(dev);
2809                 poll_locked++;
2810         }
2811
2812         /* Give a racing hard_start_xmit a few cycles to complete. */
2813         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
2814
2815         /*
2816          * And now for the 50k$ question: are IRQ disabled or not ?
2817          *
2818          * Two paths lead here:
2819          * 1) dev->close
2820          *    -> netif_running() is available to sync the current code and the
2821          *       IRQ handler. See rtl8169_interrupt for details.
2822          * 2) dev->change_mtu
2823          *    -> rtl8169_poll can not be issued again and re-enable the
2824          *       interruptions. Let's simply issue the IRQ down sequence again.
2825          *
2826          * No loop if hotpluged or major error (0xffff).
2827          */
2828         intrmask = RTL_R16(IntrMask);
2829         if (intrmask && (intrmask != 0xffff))
2830                 goto core_down;
2831
2832         rtl8169_tx_clear(tp);
2833
2834         rtl8169_rx_clear(tp);
2835 }
2836
2837 static int rtl8169_close(struct net_device *dev)
2838 {
2839         struct rtl8169_private *tp = netdev_priv(dev);
2840         struct pci_dev *pdev = tp->pci_dev;
2841
2842         rtl8169_down(dev);
2843
2844         free_irq(dev->irq, dev);
2845
2846         netif_poll_enable(dev);
2847
2848         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2849                             tp->RxPhyAddr);
2850         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2851                             tp->TxPhyAddr);
2852         tp->TxDescArray = NULL;
2853         tp->RxDescArray = NULL;
2854
2855         return 0;
2856 }
2857
2858 static void rtl_set_rx_mode(struct net_device *dev)
2859 {
2860         struct rtl8169_private *tp = netdev_priv(dev);
2861         void __iomem *ioaddr = tp->mmio_addr;
2862         unsigned long flags;
2863         u32 mc_filter[2];       /* Multicast hash filter */
2864         int rx_mode;
2865         u32 tmp = 0;
2866
2867         if (dev->flags & IFF_PROMISC) {
2868                 /* Unconditionally log net taps. */
2869                 if (netif_msg_link(tp)) {
2870                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2871                                dev->name);
2872                 }
2873                 rx_mode =
2874                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2875                     AcceptAllPhys;
2876                 mc_filter[1] = mc_filter[0] = 0xffffffff;
2877         } else if ((dev->mc_count > multicast_filter_limit)
2878                    || (dev->flags & IFF_ALLMULTI)) {
2879                 /* Too many to filter perfectly -- accept all multicasts. */
2880                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2881                 mc_filter[1] = mc_filter[0] = 0xffffffff;
2882         } else {
2883                 struct dev_mc_list *mclist;
2884                 unsigned int i;
2885
2886                 rx_mode = AcceptBroadcast | AcceptMyPhys;
2887                 mc_filter[1] = mc_filter[0] = 0;
2888                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2889                      i++, mclist = mclist->next) {
2890                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2891                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2892                         rx_mode |= AcceptMulticast;
2893                 }
2894         }
2895
2896         spin_lock_irqsave(&tp->lock, flags);
2897
2898         tmp = rtl8169_rx_config | rx_mode |
2899               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2900
2901         if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2902             (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2903             (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2904             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2905             (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2906                 mc_filter[0] = 0xffffffff;
2907                 mc_filter[1] = 0xffffffff;
2908         }
2909
2910         RTL_W32(RxConfig, tmp);
2911         RTL_W32(MAR0 + 0, mc_filter[0]);
2912         RTL_W32(MAR0 + 4, mc_filter[1]);
2913
2914         spin_unlock_irqrestore(&tp->lock, flags);
2915 }
2916
2917 /**
2918  *  rtl8169_get_stats - Get rtl8169 read/write statistics
2919  *  @dev: The Ethernet Device to get statistics for
2920  *
2921  *  Get TX/RX statistics for rtl8169
2922  */
2923 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2924 {
2925         struct rtl8169_private *tp = netdev_priv(dev);
2926         void __iomem *ioaddr = tp->mmio_addr;
2927         unsigned long flags;
2928
2929         if (netif_running(dev)) {
2930                 spin_lock_irqsave(&tp->lock, flags);
2931                 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2932                 RTL_W32(RxMissed, 0);
2933                 spin_unlock_irqrestore(&tp->lock, flags);
2934         }
2935
2936         return &tp->stats;
2937 }
2938
2939 #ifdef CONFIG_PM
2940
2941 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2942 {
2943         struct net_device *dev = pci_get_drvdata(pdev);
2944         struct rtl8169_private *tp = netdev_priv(dev);
2945         void __iomem *ioaddr = tp->mmio_addr;
2946
2947         if (!netif_running(dev))
2948                 goto out_pci_suspend;
2949
2950         netif_device_detach(dev);
2951         netif_stop_queue(dev);
2952
2953         spin_lock_irq(&tp->lock);
2954
2955         rtl8169_asic_down(ioaddr);
2956
2957         tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2958         RTL_W32(RxMissed, 0);
2959
2960         spin_unlock_irq(&tp->lock);
2961
2962 out_pci_suspend:
2963         pci_save_state(pdev);
2964         pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
2965         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2966
2967         return 0;
2968 }
2969
2970 static int rtl8169_resume(struct pci_dev *pdev)
2971 {
2972         struct net_device *dev = pci_get_drvdata(pdev);
2973
2974         pci_set_power_state(pdev, PCI_D0);
2975         pci_restore_state(pdev);
2976         pci_enable_wake(pdev, PCI_D0, 0);
2977
2978         if (!netif_running(dev))
2979                 goto out;
2980
2981         netif_device_attach(dev);
2982
2983         rtl8169_schedule_work(dev, rtl8169_reset_task);
2984 out:
2985         return 0;
2986 }
2987
2988 #endif /* CONFIG_PM */
2989
2990 static struct pci_driver rtl8169_pci_driver = {
2991         .name           = MODULENAME,
2992         .id_table       = rtl8169_pci_tbl,
2993         .probe          = rtl8169_init_one,
2994         .remove         = __devexit_p(rtl8169_remove_one),
2995 #ifdef CONFIG_PM
2996         .suspend        = rtl8169_suspend,
2997         .resume         = rtl8169_resume,
2998 #endif
2999 };
3000
3001 static int __init rtl8169_init_module(void)
3002 {
3003         return pci_register_driver(&rtl8169_pci_driver);
3004 }
3005
3006 static void __exit rtl8169_cleanup_module(void)
3007 {
3008         pci_unregister_driver(&rtl8169_pci_driver);
3009 }
3010
3011 module_init(rtl8169_init_module);
3012 module_exit(rtl8169_cleanup_module);