2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #ifdef CONFIG_R8169_NAPI
32 #define NAPI_SUFFIX "-NAPI"
34 #define NAPI_SUFFIX ""
37 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
38 #define MODULENAME "r8169"
39 #define PFX MODULENAME ": "
42 #define assert(expr) \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
47 #define dprintk(fmt, args...) \
48 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
50 #define assert(expr) do {} while (0)
51 #define dprintk(fmt, args...) do {} while (0)
52 #endif /* RTL8169_DEBUG */
54 #define R8169_MSG_DEFAULT \
55 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
57 #define TX_BUFFS_AVAIL(tp) \
58 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
60 #ifdef CONFIG_R8169_NAPI
61 #define rtl8169_rx_skb netif_receive_skb
62 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
63 #define rtl8169_rx_quota(count, quota) min(count, quota)
65 #define rtl8169_rx_skb netif_rx
66 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
67 #define rtl8169_rx_quota(count, quota) count
70 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
71 static const int max_interrupt_work = 20;
73 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
74 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
75 static const int multicast_filter_limit = 32;
77 /* MAC address length */
78 #define MAC_ADDR_LEN 6
80 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
81 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
83 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
84 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
85 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
86 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
88 #define R8169_REGS_SIZE 256
89 #define R8169_NAPI_WEIGHT 64
90 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
91 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
92 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
93 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
94 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
96 #define RTL8169_TX_TIMEOUT (6*HZ)
97 #define RTL8169_PHY_TIMEOUT (10*HZ)
99 /* write/read MMIO register */
100 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
101 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
102 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
103 #define RTL_R8(reg) readb (ioaddr + (reg))
104 #define RTL_R16(reg) readw (ioaddr + (reg))
105 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
108 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
109 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
110 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
111 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
112 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
113 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
114 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
115 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
116 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
117 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
118 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
119 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
120 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
121 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
122 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
123 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
126 #define _R(NAME,MAC,MASK) \
127 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
129 static const struct {
132 u32 RxConfigMask; /* Clears the bits supported by this chip */
133 } rtl_chip_info[] = {
134 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
135 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
136 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
137 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
138 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
139 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
140 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
142 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
143 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
144 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
145 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
146 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
147 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
148 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
159 static void rtl_hw_start_8169(struct net_device *);
160 static void rtl_hw_start_8168(struct net_device *);
161 static void rtl_hw_start_8101(struct net_device *);
163 static struct pci_device_id rtl8169_pci_tbl[] = {
164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
167 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
168 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
169 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
170 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
171 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
172 { PCI_VENDOR_ID_LINKSYS, 0x1032,
173 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
177 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
179 static int rx_copybreak = 200;
186 MAC0 = 0, /* Ethernet hardware address. */
188 MAR0 = 8, /* Multicast filter. */
189 CounterAddrLow = 0x10,
190 CounterAddrHigh = 0x14,
191 TxDescStartAddrLow = 0x20,
192 TxDescStartAddrHigh = 0x24,
193 TxHDescStartAddrLow = 0x28,
194 TxHDescStartAddrHigh = 0x2c,
220 RxDescAddrLow = 0xe4,
221 RxDescAddrHigh = 0xe8,
224 FuncEventMask = 0xf4,
225 FuncPresetState = 0xf8,
226 FuncForceEvent = 0xfc,
229 enum rtl_register_content {
230 /* InterruptStatusBits */
234 TxDescUnavail = 0x0080,
256 /* TXPoll register p.5 */
257 HPQ = 0x80, /* Poll cmd on the high prio queue */
258 NPQ = 0x40, /* Poll cmd on the low prio queue */
259 FSWInt = 0x01, /* Forced software interrupt */
263 Cfg9346_Unlock = 0xc0,
268 AcceptBroadcast = 0x08,
269 AcceptMulticast = 0x04,
271 AcceptAllPhys = 0x01,
278 TxInterFrameGapShift = 24,
279 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
281 /* Config1 register p.24 */
282 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
283 PMEnable = (1 << 0), /* Power Management Enable */
285 /* Config2 register p. 25 */
286 PCI_Clock_66MHz = 0x01,
287 PCI_Clock_33MHz = 0x00,
289 /* Config3 register p.25 */
290 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
291 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
293 /* Config5 register p.27 */
294 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
295 MWF = (1 << 5), /* Accept Multicast wakeup frame */
296 UWF = (1 << 4), /* Accept Unicast wakeup frame */
297 LanWake = (1 << 1), /* LanWake enable/disable */
298 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
301 TBIReset = 0x80000000,
302 TBILoopback = 0x40000000,
303 TBINwEnable = 0x20000000,
304 TBINwRestart = 0x10000000,
305 TBILinkOk = 0x02000000,
306 TBINwComplete = 0x01000000,
309 PktCntrDisable = (1 << 7), // 8168
314 INTT_0 = 0x0000, // 8168
315 INTT_1 = 0x0001, // 8168
316 INTT_2 = 0x0002, // 8168
317 INTT_3 = 0x0003, // 8168
319 /* rtl8169_PHYstatus */
330 TBILinkOK = 0x02000000,
332 /* DumpCounterCommand */
336 enum desc_status_bit {
337 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
338 RingEnd = (1 << 30), /* End of descriptor ring */
339 FirstFrag = (1 << 29), /* First segment of a packet */
340 LastFrag = (1 << 28), /* Final segment of a packet */
343 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
344 MSSShift = 16, /* MSS value position */
345 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
346 IPCS = (1 << 18), /* Calculate IP checksum */
347 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
348 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
349 TxVlanTag = (1 << 17), /* Add VLAN tag */
352 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
353 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
355 #define RxProtoUDP (PID1)
356 #define RxProtoTCP (PID0)
357 #define RxProtoIP (PID1 | PID0)
358 #define RxProtoMask RxProtoIP
360 IPFail = (1 << 16), /* IP checksum failed */
361 UDPFail = (1 << 15), /* UDP/IP checksum failed */
362 TCPFail = (1 << 14), /* TCP/IP checksum failed */
363 RxVlanTag = (1 << 16), /* VLAN tag available */
366 #define RsvdMask 0x3fffc000
383 u8 __pad[sizeof(void *) - sizeof(u32)];
387 RTL_FEATURE_WOL = (1 << 0),
388 RTL_FEATURE_MSI = (1 << 1),
391 struct rtl8169_private {
392 void __iomem *mmio_addr; /* memory map physical address */
393 struct pci_dev *pci_dev; /* Index of PCI device */
394 struct net_device *dev;
395 struct napi_struct napi;
396 spinlock_t lock; /* spin lock flag */
400 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
401 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
404 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
405 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
406 dma_addr_t TxPhyAddr;
407 dma_addr_t RxPhyAddr;
408 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
409 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
412 struct timer_list timer;
417 int phy_auto_nego_reg;
418 int phy_1000_ctrl_reg;
419 #ifdef CONFIG_R8169_VLAN
420 struct vlan_group *vlgrp;
422 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
423 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
424 void (*phy_reset_enable)(void __iomem *);
425 void (*hw_start)(struct net_device *);
426 unsigned int (*phy_reset_pending)(void __iomem *);
427 unsigned int (*link_ok)(void __iomem *);
428 struct delayed_work task;
432 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
433 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
434 module_param(rx_copybreak, int, 0);
435 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
436 module_param(use_dac, int, 0);
437 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
438 module_param_named(debug, debug.msg_enable, int, 0);
439 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
440 MODULE_LICENSE("GPL");
441 MODULE_VERSION(RTL8169_VERSION);
443 static int rtl8169_open(struct net_device *dev);
444 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
445 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
446 static int rtl8169_init_ring(struct net_device *dev);
447 static void rtl_hw_start(struct net_device *dev);
448 static int rtl8169_close(struct net_device *dev);
449 static void rtl_set_rx_mode(struct net_device *dev);
450 static void rtl8169_tx_timeout(struct net_device *dev);
451 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
452 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
453 void __iomem *, u32 budget);
454 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
455 static void rtl8169_down(struct net_device *dev);
456 static void rtl8169_rx_clear(struct rtl8169_private *tp);
458 #ifdef CONFIG_R8169_NAPI
459 static int rtl8169_poll(struct napi_struct *napi, int budget);
462 static const unsigned int rtl8169_rx_config =
463 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
465 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
469 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
471 for (i = 20; i > 0; i--) {
473 * Check if the RTL8169 has completed writing to the specified
476 if (!(RTL_R32(PHYAR) & 0x80000000))
482 static int mdio_read(void __iomem *ioaddr, int reg_addr)
486 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
488 for (i = 20; i > 0; i--) {
490 * Check if the RTL8169 has completed retrieving data from
491 * the specified MII register.
493 if (RTL_R32(PHYAR) & 0x80000000) {
494 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
502 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
504 RTL_W16(IntrMask, 0x0000);
506 RTL_W16(IntrStatus, 0xffff);
509 static void rtl8169_asic_down(void __iomem *ioaddr)
511 RTL_W8(ChipCmd, 0x00);
512 rtl8169_irq_mask_and_ack(ioaddr);
516 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
518 return RTL_R32(TBICSR) & TBIReset;
521 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
523 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
526 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
528 return RTL_R32(TBICSR) & TBILinkOk;
531 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
533 return RTL_R8(PHYstatus) & LinkStatus;
536 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
538 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
541 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
545 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
546 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
549 static void rtl8169_check_link_status(struct net_device *dev,
550 struct rtl8169_private *tp,
551 void __iomem *ioaddr)
555 spin_lock_irqsave(&tp->lock, flags);
556 if (tp->link_ok(ioaddr)) {
557 netif_carrier_on(dev);
558 if (netif_msg_ifup(tp))
559 printk(KERN_INFO PFX "%s: link up\n", dev->name);
561 if (netif_msg_ifdown(tp))
562 printk(KERN_INFO PFX "%s: link down\n", dev->name);
563 netif_carrier_off(dev);
565 spin_unlock_irqrestore(&tp->lock, flags);
568 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
570 struct rtl8169_private *tp = netdev_priv(dev);
571 void __iomem *ioaddr = tp->mmio_addr;
576 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
577 wol->supported = WAKE_ANY;
579 spin_lock_irq(&tp->lock);
581 options = RTL_R8(Config1);
582 if (!(options & PMEnable))
585 options = RTL_R8(Config3);
586 if (options & LinkUp)
587 wol->wolopts |= WAKE_PHY;
588 if (options & MagicPacket)
589 wol->wolopts |= WAKE_MAGIC;
591 options = RTL_R8(Config5);
593 wol->wolopts |= WAKE_UCAST;
595 wol->wolopts |= WAKE_BCAST;
597 wol->wolopts |= WAKE_MCAST;
600 spin_unlock_irq(&tp->lock);
603 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
605 struct rtl8169_private *tp = netdev_priv(dev);
606 void __iomem *ioaddr = tp->mmio_addr;
613 { WAKE_ANY, Config1, PMEnable },
614 { WAKE_PHY, Config3, LinkUp },
615 { WAKE_MAGIC, Config3, MagicPacket },
616 { WAKE_UCAST, Config5, UWF },
617 { WAKE_BCAST, Config5, BWF },
618 { WAKE_MCAST, Config5, MWF },
619 { WAKE_ANY, Config5, LanWake }
622 spin_lock_irq(&tp->lock);
624 RTL_W8(Cfg9346, Cfg9346_Unlock);
626 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
627 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
628 if (wol->wolopts & cfg[i].opt)
629 options |= cfg[i].mask;
630 RTL_W8(cfg[i].reg, options);
633 RTL_W8(Cfg9346, Cfg9346_Lock);
636 tp->features |= RTL_FEATURE_WOL;
638 tp->features &= ~RTL_FEATURE_WOL;
640 spin_unlock_irq(&tp->lock);
645 static void rtl8169_get_drvinfo(struct net_device *dev,
646 struct ethtool_drvinfo *info)
648 struct rtl8169_private *tp = netdev_priv(dev);
650 strcpy(info->driver, MODULENAME);
651 strcpy(info->version, RTL8169_VERSION);
652 strcpy(info->bus_info, pci_name(tp->pci_dev));
655 static int rtl8169_get_regs_len(struct net_device *dev)
657 return R8169_REGS_SIZE;
660 static int rtl8169_set_speed_tbi(struct net_device *dev,
661 u8 autoneg, u16 speed, u8 duplex)
663 struct rtl8169_private *tp = netdev_priv(dev);
664 void __iomem *ioaddr = tp->mmio_addr;
668 reg = RTL_R32(TBICSR);
669 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
670 (duplex == DUPLEX_FULL)) {
671 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
672 } else if (autoneg == AUTONEG_ENABLE)
673 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
675 if (netif_msg_link(tp)) {
676 printk(KERN_WARNING "%s: "
677 "incorrect speed setting refused in TBI mode\n",
686 static int rtl8169_set_speed_xmii(struct net_device *dev,
687 u8 autoneg, u16 speed, u8 duplex)
689 struct rtl8169_private *tp = netdev_priv(dev);
690 void __iomem *ioaddr = tp->mmio_addr;
691 int auto_nego, giga_ctrl;
693 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
694 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
695 ADVERTISE_100HALF | ADVERTISE_100FULL);
696 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
697 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
699 if (autoneg == AUTONEG_ENABLE) {
700 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
701 ADVERTISE_100HALF | ADVERTISE_100FULL);
702 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
704 if (speed == SPEED_10)
705 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
706 else if (speed == SPEED_100)
707 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
708 else if (speed == SPEED_1000)
709 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
711 if (duplex == DUPLEX_HALF)
712 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
714 if (duplex == DUPLEX_FULL)
715 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
717 /* This tweak comes straight from Realtek's driver. */
718 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
719 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
720 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
721 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
725 /* The 8100e/8101e do Fast Ethernet only. */
726 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
727 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
728 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
729 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
730 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
731 netif_msg_link(tp)) {
732 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
735 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
738 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
740 if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
741 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
742 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
743 mdio_write(ioaddr, 0x1f, 0x0000);
744 mdio_write(ioaddr, 0x0e, 0x0000);
747 tp->phy_auto_nego_reg = auto_nego;
748 tp->phy_1000_ctrl_reg = giga_ctrl;
750 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
751 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
752 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
756 static int rtl8169_set_speed(struct net_device *dev,
757 u8 autoneg, u16 speed, u8 duplex)
759 struct rtl8169_private *tp = netdev_priv(dev);
762 ret = tp->set_speed(dev, autoneg, speed, duplex);
764 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
765 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
770 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
772 struct rtl8169_private *tp = netdev_priv(dev);
776 spin_lock_irqsave(&tp->lock, flags);
777 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
778 spin_unlock_irqrestore(&tp->lock, flags);
783 static u32 rtl8169_get_rx_csum(struct net_device *dev)
785 struct rtl8169_private *tp = netdev_priv(dev);
787 return tp->cp_cmd & RxChkSum;
790 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
792 struct rtl8169_private *tp = netdev_priv(dev);
793 void __iomem *ioaddr = tp->mmio_addr;
796 spin_lock_irqsave(&tp->lock, flags);
799 tp->cp_cmd |= RxChkSum;
801 tp->cp_cmd &= ~RxChkSum;
803 RTL_W16(CPlusCmd, tp->cp_cmd);
806 spin_unlock_irqrestore(&tp->lock, flags);
811 #ifdef CONFIG_R8169_VLAN
813 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
816 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
817 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
820 static void rtl8169_vlan_rx_register(struct net_device *dev,
821 struct vlan_group *grp)
823 struct rtl8169_private *tp = netdev_priv(dev);
824 void __iomem *ioaddr = tp->mmio_addr;
827 spin_lock_irqsave(&tp->lock, flags);
830 tp->cp_cmd |= RxVlan;
832 tp->cp_cmd &= ~RxVlan;
833 RTL_W16(CPlusCmd, tp->cp_cmd);
835 spin_unlock_irqrestore(&tp->lock, flags);
838 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
841 u32 opts2 = le32_to_cpu(desc->opts2);
844 if (tp->vlgrp && (opts2 & RxVlanTag)) {
845 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
853 #else /* !CONFIG_R8169_VLAN */
855 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
861 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
869 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
871 struct rtl8169_private *tp = netdev_priv(dev);
872 void __iomem *ioaddr = tp->mmio_addr;
876 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
877 cmd->port = PORT_FIBRE;
878 cmd->transceiver = XCVR_INTERNAL;
880 status = RTL_R32(TBICSR);
881 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
882 cmd->autoneg = !!(status & TBINwEnable);
884 cmd->speed = SPEED_1000;
885 cmd->duplex = DUPLEX_FULL; /* Always set */
888 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
890 struct rtl8169_private *tp = netdev_priv(dev);
891 void __iomem *ioaddr = tp->mmio_addr;
894 cmd->supported = SUPPORTED_10baseT_Half |
895 SUPPORTED_10baseT_Full |
896 SUPPORTED_100baseT_Half |
897 SUPPORTED_100baseT_Full |
898 SUPPORTED_1000baseT_Full |
903 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
905 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
906 cmd->advertising |= ADVERTISED_10baseT_Half;
907 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
908 cmd->advertising |= ADVERTISED_10baseT_Full;
909 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
910 cmd->advertising |= ADVERTISED_100baseT_Half;
911 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
912 cmd->advertising |= ADVERTISED_100baseT_Full;
913 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
914 cmd->advertising |= ADVERTISED_1000baseT_Full;
916 status = RTL_R8(PHYstatus);
918 if (status & _1000bpsF)
919 cmd->speed = SPEED_1000;
920 else if (status & _100bps)
921 cmd->speed = SPEED_100;
922 else if (status & _10bps)
923 cmd->speed = SPEED_10;
925 if (status & TxFlowCtrl)
926 cmd->advertising |= ADVERTISED_Asym_Pause;
927 if (status & RxFlowCtrl)
928 cmd->advertising |= ADVERTISED_Pause;
930 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
931 DUPLEX_FULL : DUPLEX_HALF;
934 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
936 struct rtl8169_private *tp = netdev_priv(dev);
939 spin_lock_irqsave(&tp->lock, flags);
941 tp->get_settings(dev, cmd);
943 spin_unlock_irqrestore(&tp->lock, flags);
947 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
950 struct rtl8169_private *tp = netdev_priv(dev);
953 if (regs->len > R8169_REGS_SIZE)
954 regs->len = R8169_REGS_SIZE;
956 spin_lock_irqsave(&tp->lock, flags);
957 memcpy_fromio(p, tp->mmio_addr, regs->len);
958 spin_unlock_irqrestore(&tp->lock, flags);
961 static u32 rtl8169_get_msglevel(struct net_device *dev)
963 struct rtl8169_private *tp = netdev_priv(dev);
965 return tp->msg_enable;
968 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
970 struct rtl8169_private *tp = netdev_priv(dev);
972 tp->msg_enable = value;
975 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
982 "tx_single_collisions",
983 "tx_multi_collisions",
991 struct rtl8169_counters {
998 __le32 tx_one_collision;
999 __le32 tx_multi_collision;
1001 __le64 rx_broadcast;
1002 __le32 rx_multicast;
1007 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1011 return ARRAY_SIZE(rtl8169_gstrings);
1017 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1018 struct ethtool_stats *stats, u64 *data)
1020 struct rtl8169_private *tp = netdev_priv(dev);
1021 void __iomem *ioaddr = tp->mmio_addr;
1022 struct rtl8169_counters *counters;
1028 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1032 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1033 cmd = (u64)paddr & DMA_32BIT_MASK;
1034 RTL_W32(CounterAddrLow, cmd);
1035 RTL_W32(CounterAddrLow, cmd | CounterDump);
1037 while (RTL_R32(CounterAddrLow) & CounterDump) {
1038 if (msleep_interruptible(1))
1042 RTL_W32(CounterAddrLow, 0);
1043 RTL_W32(CounterAddrHigh, 0);
1045 data[0] = le64_to_cpu(counters->tx_packets);
1046 data[1] = le64_to_cpu(counters->rx_packets);
1047 data[2] = le64_to_cpu(counters->tx_errors);
1048 data[3] = le32_to_cpu(counters->rx_errors);
1049 data[4] = le16_to_cpu(counters->rx_missed);
1050 data[5] = le16_to_cpu(counters->align_errors);
1051 data[6] = le32_to_cpu(counters->tx_one_collision);
1052 data[7] = le32_to_cpu(counters->tx_multi_collision);
1053 data[8] = le64_to_cpu(counters->rx_unicast);
1054 data[9] = le64_to_cpu(counters->rx_broadcast);
1055 data[10] = le32_to_cpu(counters->rx_multicast);
1056 data[11] = le16_to_cpu(counters->tx_aborted);
1057 data[12] = le16_to_cpu(counters->tx_underun);
1059 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1062 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1066 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1071 static const struct ethtool_ops rtl8169_ethtool_ops = {
1072 .get_drvinfo = rtl8169_get_drvinfo,
1073 .get_regs_len = rtl8169_get_regs_len,
1074 .get_link = ethtool_op_get_link,
1075 .get_settings = rtl8169_get_settings,
1076 .set_settings = rtl8169_set_settings,
1077 .get_msglevel = rtl8169_get_msglevel,
1078 .set_msglevel = rtl8169_set_msglevel,
1079 .get_rx_csum = rtl8169_get_rx_csum,
1080 .set_rx_csum = rtl8169_set_rx_csum,
1081 .set_tx_csum = ethtool_op_set_tx_csum,
1082 .set_sg = ethtool_op_set_sg,
1083 .set_tso = ethtool_op_set_tso,
1084 .get_regs = rtl8169_get_regs,
1085 .get_wol = rtl8169_get_wol,
1086 .set_wol = rtl8169_set_wol,
1087 .get_strings = rtl8169_get_strings,
1088 .get_sset_count = rtl8169_get_sset_count,
1089 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1092 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1093 int bitnum, int bitval)
1097 val = mdio_read(ioaddr, reg);
1098 val = (bitval == 1) ?
1099 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1100 mdio_write(ioaddr, reg, val & 0xffff);
1103 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1104 void __iomem *ioaddr)
1107 * The driver currently handles the 8168Bf and the 8168Be identically
1108 * but they can be identified more specifically through the test below
1111 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1113 * Same thing for the 8101Eb and the 8101Ec:
1115 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1123 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1124 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1125 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1126 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1129 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1130 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1131 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1132 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1135 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1136 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1137 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1138 /* FIXME: where did these entries come from ? -- FR */
1139 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1140 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1143 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1144 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1145 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1146 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1147 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1148 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1150 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1154 reg = RTL_R32(TxConfig);
1155 while ((reg & p->mask) != p->val)
1157 tp->mac_version = p->mac_version;
1159 if (p->mask == 0x00000000) {
1160 struct pci_dev *pdev = tp->pci_dev;
1162 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1166 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1168 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1171 static void rtl8169_hw_phy_config(struct net_device *dev)
1173 struct rtl8169_private *tp = netdev_priv(dev);
1174 void __iomem *ioaddr = tp->mmio_addr;
1176 u16 regs[5]; /* Beware of bit-sign propagation */
1177 } phy_magic[5] = { {
1178 { 0x0000, //w 4 15 12 0
1179 0x00a1, //w 3 15 0 00a1
1180 0x0008, //w 2 15 0 0008
1181 0x1020, //w 1 15 0 1020
1182 0x1000 } },{ //w 0 15 0 1000
1183 { 0x7000, //w 4 15 12 7
1184 0xff41, //w 3 15 0 ff41
1185 0xde60, //w 2 15 0 de60
1186 0x0140, //w 1 15 0 0140
1187 0x0077 } },{ //w 0 15 0 0077
1188 { 0xa000, //w 4 15 12 a
1189 0xdf01, //w 3 15 0 df01
1190 0xdf20, //w 2 15 0 df20
1191 0xff95, //w 1 15 0 ff95
1192 0xfa00 } },{ //w 0 15 0 fa00
1193 { 0xb000, //w 4 15 12 b
1194 0xff41, //w 3 15 0 ff41
1195 0xde20, //w 2 15 0 de20
1196 0x0140, //w 1 15 0 0140
1197 0x00bb } },{ //w 0 15 0 00bb
1198 { 0xf000, //w 4 15 12 f
1199 0xdf01, //w 3 15 0 df01
1200 0xdf20, //w 2 15 0 df20
1201 0xff95, //w 1 15 0 ff95
1202 0xbf00 } //w 0 15 0 bf00
1207 rtl8169_print_mac_version(tp);
1209 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1212 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1213 dprintk("Do final_reg2.cfg\n");
1217 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1218 mdio_write(ioaddr, 31, 0x0002);
1219 mdio_write(ioaddr, 1, 0x90d0);
1220 mdio_write(ioaddr, 31, 0x0000);
1224 if ((tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1225 (tp->mac_version != RTL_GIGA_MAC_VER_03))
1228 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1229 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1230 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1231 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1233 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1236 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1237 mdio_write(ioaddr, pos, val);
1239 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1240 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1241 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1243 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1246 static void rtl8169_phy_timer(unsigned long __opaque)
1248 struct net_device *dev = (struct net_device *)__opaque;
1249 struct rtl8169_private *tp = netdev_priv(dev);
1250 struct timer_list *timer = &tp->timer;
1251 void __iomem *ioaddr = tp->mmio_addr;
1252 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1254 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1256 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1259 spin_lock_irq(&tp->lock);
1261 if (tp->phy_reset_pending(ioaddr)) {
1263 * A busy loop could burn quite a few cycles on nowadays CPU.
1264 * Let's delay the execution of the timer for a few ticks.
1270 if (tp->link_ok(ioaddr))
1273 if (netif_msg_link(tp))
1274 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1276 tp->phy_reset_enable(ioaddr);
1279 mod_timer(timer, jiffies + timeout);
1281 spin_unlock_irq(&tp->lock);
1284 static inline void rtl8169_delete_timer(struct net_device *dev)
1286 struct rtl8169_private *tp = netdev_priv(dev);
1287 struct timer_list *timer = &tp->timer;
1289 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1292 del_timer_sync(timer);
1295 static inline void rtl8169_request_timer(struct net_device *dev)
1297 struct rtl8169_private *tp = netdev_priv(dev);
1298 struct timer_list *timer = &tp->timer;
1300 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1303 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1306 #ifdef CONFIG_NET_POLL_CONTROLLER
1308 * Polling 'interrupt' - used by things like netconsole to send skbs
1309 * without having to re-enable interrupts. It's not called while
1310 * the interrupt routine is executing.
1312 static void rtl8169_netpoll(struct net_device *dev)
1314 struct rtl8169_private *tp = netdev_priv(dev);
1315 struct pci_dev *pdev = tp->pci_dev;
1317 disable_irq(pdev->irq);
1318 rtl8169_interrupt(pdev->irq, dev);
1319 enable_irq(pdev->irq);
1323 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1324 void __iomem *ioaddr)
1327 pci_release_regions(pdev);
1328 pci_disable_device(pdev);
1332 static void rtl8169_phy_reset(struct net_device *dev,
1333 struct rtl8169_private *tp)
1335 void __iomem *ioaddr = tp->mmio_addr;
1338 tp->phy_reset_enable(ioaddr);
1339 for (i = 0; i < 100; i++) {
1340 if (!tp->phy_reset_pending(ioaddr))
1344 if (netif_msg_link(tp))
1345 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1348 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1350 void __iomem *ioaddr = tp->mmio_addr;
1352 rtl8169_hw_phy_config(dev);
1354 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1357 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1359 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1360 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1362 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1363 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1365 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1366 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1369 rtl8169_phy_reset(dev, tp);
1372 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1373 * only 8101. Don't panic.
1375 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1377 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1378 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1381 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1383 void __iomem *ioaddr = tp->mmio_addr;
1387 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1388 high = addr[4] | (addr[5] << 8);
1390 spin_lock_irq(&tp->lock);
1392 RTL_W8(Cfg9346, Cfg9346_Unlock);
1394 RTL_W32(MAC4, high);
1395 RTL_W8(Cfg9346, Cfg9346_Lock);
1397 spin_unlock_irq(&tp->lock);
1400 static int rtl_set_mac_address(struct net_device *dev, void *p)
1402 struct rtl8169_private *tp = netdev_priv(dev);
1403 struct sockaddr *addr = p;
1405 if (!is_valid_ether_addr(addr->sa_data))
1406 return -EADDRNOTAVAIL;
1408 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1410 rtl_rar_set(tp, dev->dev_addr);
1415 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1417 struct rtl8169_private *tp = netdev_priv(dev);
1418 struct mii_ioctl_data *data = if_mii(ifr);
1420 if (!netif_running(dev))
1425 data->phy_id = 32; /* Internal PHY */
1429 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1433 if (!capable(CAP_NET_ADMIN))
1435 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1441 static const struct rtl_cfg_info {
1442 void (*hw_start)(struct net_device *);
1443 unsigned int region;
1448 } rtl_cfg_infos [] = {
1450 .hw_start = rtl_hw_start_8169,
1453 .intr_event = SYSErr | LinkChg | RxOverflow |
1454 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1455 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1459 .hw_start = rtl_hw_start_8168,
1462 .intr_event = SYSErr | LinkChg | RxOverflow |
1463 TxErr | TxOK | RxOK | RxErr,
1464 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1465 .msi = RTL_FEATURE_MSI
1468 .hw_start = rtl_hw_start_8101,
1471 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1472 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1473 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1474 .msi = RTL_FEATURE_MSI
1478 /* Cfg9346_Unlock assumed. */
1479 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1480 const struct rtl_cfg_info *cfg)
1485 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1487 if (pci_enable_msi(pdev)) {
1488 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1491 msi = RTL_FEATURE_MSI;
1494 RTL_W8(Config2, cfg2);
1498 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1500 if (tp->features & RTL_FEATURE_MSI) {
1501 pci_disable_msi(pdev);
1502 tp->features &= ~RTL_FEATURE_MSI;
1506 static int __devinit
1507 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1509 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1510 const unsigned int region = cfg->region;
1511 struct rtl8169_private *tp;
1512 struct net_device *dev;
1513 void __iomem *ioaddr;
1517 if (netif_msg_drv(&debug)) {
1518 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1519 MODULENAME, RTL8169_VERSION);
1522 dev = alloc_etherdev(sizeof (*tp));
1524 if (netif_msg_drv(&debug))
1525 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1530 SET_NETDEV_DEV(dev, &pdev->dev);
1531 tp = netdev_priv(dev);
1533 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1535 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1536 rc = pci_enable_device(pdev);
1538 if (netif_msg_probe(tp))
1539 dev_err(&pdev->dev, "enable failure\n");
1540 goto err_out_free_dev_1;
1543 rc = pci_set_mwi(pdev);
1545 goto err_out_disable_2;
1547 /* make sure PCI base addr 1 is MMIO */
1548 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1549 if (netif_msg_probe(tp)) {
1551 "region #%d not an MMIO resource, aborting\n",
1558 /* check for weird/broken PCI region reporting */
1559 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1560 if (netif_msg_probe(tp)) {
1562 "Invalid PCI region size(s), aborting\n");
1568 rc = pci_request_regions(pdev, MODULENAME);
1570 if (netif_msg_probe(tp))
1571 dev_err(&pdev->dev, "could not request regions.\n");
1575 tp->cp_cmd = PCIMulRW | RxChkSum;
1577 if ((sizeof(dma_addr_t) > 4) &&
1578 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1579 tp->cp_cmd |= PCIDAC;
1580 dev->features |= NETIF_F_HIGHDMA;
1582 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1584 if (netif_msg_probe(tp)) {
1586 "DMA configuration failed.\n");
1588 goto err_out_free_res_4;
1592 pci_set_master(pdev);
1594 /* ioremap MMIO region */
1595 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1597 if (netif_msg_probe(tp))
1598 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1600 goto err_out_free_res_4;
1603 /* Unneeded ? Don't mess with Mrs. Murphy. */
1604 rtl8169_irq_mask_and_ack(ioaddr);
1606 /* Soft reset the chip. */
1607 RTL_W8(ChipCmd, CmdReset);
1609 /* Check that the chip has finished the reset. */
1610 for (i = 0; i < 100; i++) {
1611 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1613 msleep_interruptible(1);
1616 /* Identify chip attached to board */
1617 rtl8169_get_mac_version(tp, ioaddr);
1619 rtl8169_print_mac_version(tp);
1621 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1622 if (tp->mac_version == rtl_chip_info[i].mac_version)
1626 /* Unknown chip: assume array element #0, original RTL-8169 */
1627 if (netif_msg_probe(tp)) {
1628 dev_printk(KERN_DEBUG, &pdev->dev,
1629 "unknown chip version, assuming %s\n",
1630 rtl_chip_info[0].name);
1636 RTL_W8(Cfg9346, Cfg9346_Unlock);
1637 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1638 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1639 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
1640 RTL_W8(Cfg9346, Cfg9346_Lock);
1642 if (RTL_R8(PHYstatus) & TBI_Enable) {
1643 tp->set_speed = rtl8169_set_speed_tbi;
1644 tp->get_settings = rtl8169_gset_tbi;
1645 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1646 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1647 tp->link_ok = rtl8169_tbi_link_ok;
1649 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1651 tp->set_speed = rtl8169_set_speed_xmii;
1652 tp->get_settings = rtl8169_gset_xmii;
1653 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1654 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1655 tp->link_ok = rtl8169_xmii_link_ok;
1657 dev->do_ioctl = rtl8169_ioctl;
1660 /* Get MAC address. FIXME: read EEPROM */
1661 for (i = 0; i < MAC_ADDR_LEN; i++)
1662 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1663 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1665 dev->open = rtl8169_open;
1666 dev->hard_start_xmit = rtl8169_start_xmit;
1667 dev->get_stats = rtl8169_get_stats;
1668 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1669 dev->stop = rtl8169_close;
1670 dev->tx_timeout = rtl8169_tx_timeout;
1671 dev->set_multicast_list = rtl_set_rx_mode;
1672 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1673 dev->irq = pdev->irq;
1674 dev->base_addr = (unsigned long) ioaddr;
1675 dev->change_mtu = rtl8169_change_mtu;
1676 dev->set_mac_address = rtl_set_mac_address;
1678 #ifdef CONFIG_R8169_NAPI
1679 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1682 #ifdef CONFIG_R8169_VLAN
1683 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1684 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1687 #ifdef CONFIG_NET_POLL_CONTROLLER
1688 dev->poll_controller = rtl8169_netpoll;
1691 tp->intr_mask = 0xffff;
1693 tp->mmio_addr = ioaddr;
1694 tp->align = cfg->align;
1695 tp->hw_start = cfg->hw_start;
1696 tp->intr_event = cfg->intr_event;
1697 tp->napi_event = cfg->napi_event;
1699 init_timer(&tp->timer);
1700 tp->timer.data = (unsigned long) dev;
1701 tp->timer.function = rtl8169_phy_timer;
1703 spin_lock_init(&tp->lock);
1705 rc = register_netdev(dev);
1709 pci_set_drvdata(pdev, dev);
1711 if (netif_msg_probe(tp)) {
1712 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1714 printk(KERN_INFO "%s: %s at 0x%lx, "
1715 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1716 "XID %08x IRQ %d\n",
1718 rtl_chip_info[tp->chipset].name,
1720 dev->dev_addr[0], dev->dev_addr[1],
1721 dev->dev_addr[2], dev->dev_addr[3],
1722 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1725 rtl8169_init_phy(dev, tp);
1731 rtl_disable_msi(pdev, tp);
1734 pci_release_regions(pdev);
1736 pci_clear_mwi(pdev);
1738 pci_disable_device(pdev);
1744 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1746 struct net_device *dev = pci_get_drvdata(pdev);
1747 struct rtl8169_private *tp = netdev_priv(dev);
1749 flush_scheduled_work();
1751 unregister_netdev(dev);
1752 rtl_disable_msi(pdev, tp);
1753 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1754 pci_set_drvdata(pdev, NULL);
1757 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1758 struct net_device *dev)
1760 unsigned int mtu = dev->mtu;
1762 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1765 static int rtl8169_open(struct net_device *dev)
1767 struct rtl8169_private *tp = netdev_priv(dev);
1768 struct pci_dev *pdev = tp->pci_dev;
1769 int retval = -ENOMEM;
1772 rtl8169_set_rxbufsize(tp, dev);
1775 * Rx and Tx desscriptors needs 256 bytes alignment.
1776 * pci_alloc_consistent provides more.
1778 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1780 if (!tp->TxDescArray)
1783 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1785 if (!tp->RxDescArray)
1788 retval = rtl8169_init_ring(dev);
1792 INIT_DELAYED_WORK(&tp->task, NULL);
1796 retval = request_irq(dev->irq, rtl8169_interrupt,
1797 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
1800 goto err_release_ring_2;
1802 #ifdef CONFIG_R8169_NAPI
1803 napi_enable(&tp->napi);
1808 rtl8169_request_timer(dev);
1810 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1815 rtl8169_rx_clear(tp);
1817 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1820 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1825 static void rtl8169_hw_reset(void __iomem *ioaddr)
1827 /* Disable interrupts */
1828 rtl8169_irq_mask_and_ack(ioaddr);
1830 /* Reset the chipset */
1831 RTL_W8(ChipCmd, CmdReset);
1837 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1839 void __iomem *ioaddr = tp->mmio_addr;
1840 u32 cfg = rtl8169_rx_config;
1842 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1843 RTL_W32(RxConfig, cfg);
1845 /* Set DMA burst size and Interframe Gap Time */
1846 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1847 (InterFrameGap << TxInterFrameGapShift));
1850 static void rtl_hw_start(struct net_device *dev)
1852 struct rtl8169_private *tp = netdev_priv(dev);
1853 void __iomem *ioaddr = tp->mmio_addr;
1856 /* Soft reset the chip. */
1857 RTL_W8(ChipCmd, CmdReset);
1859 /* Check that the chip has finished the reset. */
1860 for (i = 0; i < 100; i++) {
1861 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1863 msleep_interruptible(1);
1868 netif_start_queue(dev);
1872 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1873 void __iomem *ioaddr)
1876 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1877 * register to be written before TxDescAddrLow to work.
1878 * Switching from MMIO to I/O access fixes the issue as well.
1880 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1881 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1882 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1883 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1886 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1890 cmd = RTL_R16(CPlusCmd);
1891 RTL_W16(CPlusCmd, cmd);
1895 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1897 /* Low hurts. Let's disable the filtering. */
1898 RTL_W16(RxMaxSize, 16383);
1901 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1908 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1909 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1910 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1911 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1916 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1917 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1918 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1919 RTL_W32(0x7c, p->val);
1925 static void rtl_hw_start_8169(struct net_device *dev)
1927 struct rtl8169_private *tp = netdev_priv(dev);
1928 void __iomem *ioaddr = tp->mmio_addr;
1929 struct pci_dev *pdev = tp->pci_dev;
1931 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1932 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1933 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1936 RTL_W8(Cfg9346, Cfg9346_Unlock);
1937 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1938 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1939 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1940 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1941 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1943 RTL_W8(EarlyTxThres, EarlyTxThld);
1945 rtl_set_rx_max_size(ioaddr);
1947 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1948 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1949 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1950 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1951 rtl_set_rx_tx_config_registers(tp);
1953 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1955 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1956 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1957 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1958 "Bit-3 and bit-14 MUST be 1\n");
1959 tp->cp_cmd |= (1 << 14);
1962 RTL_W16(CPlusCmd, tp->cp_cmd);
1964 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1967 * Undocumented corner. Supposedly:
1968 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1970 RTL_W16(IntrMitigate, 0x0000);
1972 rtl_set_rx_tx_desc_registers(tp, ioaddr);
1974 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
1975 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1976 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
1977 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
1978 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1979 rtl_set_rx_tx_config_registers(tp);
1982 RTL_W8(Cfg9346, Cfg9346_Lock);
1984 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1987 RTL_W32(RxMissed, 0);
1989 rtl_set_rx_mode(dev);
1991 /* no early-rx interrupts */
1992 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1994 /* Enable all known interrupts by setting the interrupt mask. */
1995 RTL_W16(IntrMask, tp->intr_event);
1998 static void rtl_hw_start_8168(struct net_device *dev)
2000 struct rtl8169_private *tp = netdev_priv(dev);
2001 void __iomem *ioaddr = tp->mmio_addr;
2002 struct pci_dev *pdev = tp->pci_dev;
2005 RTL_W8(Cfg9346, Cfg9346_Unlock);
2007 RTL_W8(EarlyTxThres, EarlyTxThld);
2009 rtl_set_rx_max_size(ioaddr);
2011 rtl_set_rx_tx_config_registers(tp);
2013 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2015 RTL_W16(CPlusCmd, tp->cp_cmd);
2017 /* Tx performance tweak. */
2018 pci_read_config_byte(pdev, 0x69, &ctl);
2019 ctl = (ctl & ~0x70) | 0x50;
2020 pci_write_config_byte(pdev, 0x69, ctl);
2022 RTL_W16(IntrMitigate, 0x5151);
2024 /* Work around for RxFIFO overflow. */
2025 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2026 tp->intr_event |= RxFIFOOver | PCSTimeout;
2027 tp->intr_event &= ~RxOverflow;
2030 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2032 RTL_W8(Cfg9346, Cfg9346_Lock);
2036 RTL_W32(RxMissed, 0);
2038 rtl_set_rx_mode(dev);
2040 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2042 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2044 RTL_W16(IntrMask, tp->intr_event);
2047 static void rtl_hw_start_8101(struct net_device *dev)
2049 struct rtl8169_private *tp = netdev_priv(dev);
2050 void __iomem *ioaddr = tp->mmio_addr;
2051 struct pci_dev *pdev = tp->pci_dev;
2053 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2054 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2055 pci_write_config_word(pdev, 0x68, 0x00);
2056 pci_write_config_word(pdev, 0x69, 0x08);
2059 RTL_W8(Cfg9346, Cfg9346_Unlock);
2061 RTL_W8(EarlyTxThres, EarlyTxThld);
2063 rtl_set_rx_max_size(ioaddr);
2065 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2067 RTL_W16(CPlusCmd, tp->cp_cmd);
2069 RTL_W16(IntrMitigate, 0x0000);
2071 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2073 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2074 rtl_set_rx_tx_config_registers(tp);
2076 RTL_W8(Cfg9346, Cfg9346_Lock);
2080 RTL_W32(RxMissed, 0);
2082 rtl_set_rx_mode(dev);
2084 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2086 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2088 RTL_W16(IntrMask, tp->intr_event);
2091 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2093 struct rtl8169_private *tp = netdev_priv(dev);
2096 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2101 if (!netif_running(dev))
2106 rtl8169_set_rxbufsize(tp, dev);
2108 ret = rtl8169_init_ring(dev);
2112 #ifdef CONFIG_R8169_NAPI
2113 napi_enable(&tp->napi);
2118 rtl8169_request_timer(dev);
2124 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2126 desc->addr = 0x0badbadbadbadbadull;
2127 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2130 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2131 struct sk_buff **sk_buff, struct RxDesc *desc)
2133 struct pci_dev *pdev = tp->pci_dev;
2135 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2136 PCI_DMA_FROMDEVICE);
2137 dev_kfree_skb(*sk_buff);
2139 rtl8169_make_unusable_by_asic(desc);
2142 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2144 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2146 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2149 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2152 desc->addr = cpu_to_le64(mapping);
2154 rtl8169_mark_to_asic(desc, rx_buf_sz);
2157 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2158 struct net_device *dev,
2159 struct RxDesc *desc, int rx_buf_sz,
2162 struct sk_buff *skb;
2166 pad = align ? align : NET_IP_ALIGN;
2168 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2172 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2174 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2175 PCI_DMA_FROMDEVICE);
2177 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2182 rtl8169_make_unusable_by_asic(desc);
2186 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2190 for (i = 0; i < NUM_RX_DESC; i++) {
2191 if (tp->Rx_skbuff[i]) {
2192 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2193 tp->RxDescArray + i);
2198 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2203 for (cur = start; end - cur != 0; cur++) {
2204 struct sk_buff *skb;
2205 unsigned int i = cur % NUM_RX_DESC;
2207 WARN_ON((s32)(end - cur) < 0);
2209 if (tp->Rx_skbuff[i])
2212 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2213 tp->RxDescArray + i,
2214 tp->rx_buf_sz, tp->align);
2218 tp->Rx_skbuff[i] = skb;
2223 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2225 desc->opts1 |= cpu_to_le32(RingEnd);
2228 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2230 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2233 static int rtl8169_init_ring(struct net_device *dev)
2235 struct rtl8169_private *tp = netdev_priv(dev);
2237 rtl8169_init_ring_indexes(tp);
2239 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2240 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2242 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2245 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2250 rtl8169_rx_clear(tp);
2254 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2255 struct TxDesc *desc)
2257 unsigned int len = tx_skb->len;
2259 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2266 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2270 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2271 unsigned int entry = i % NUM_TX_DESC;
2272 struct ring_info *tx_skb = tp->tx_skb + entry;
2273 unsigned int len = tx_skb->len;
2276 struct sk_buff *skb = tx_skb->skb;
2278 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2279 tp->TxDescArray + entry);
2284 tp->dev->stats.tx_dropped++;
2287 tp->cur_tx = tp->dirty_tx = 0;
2290 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2292 struct rtl8169_private *tp = netdev_priv(dev);
2294 PREPARE_DELAYED_WORK(&tp->task, task);
2295 schedule_delayed_work(&tp->task, 4);
2298 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2300 struct rtl8169_private *tp = netdev_priv(dev);
2301 void __iomem *ioaddr = tp->mmio_addr;
2303 synchronize_irq(dev->irq);
2305 /* Wait for any pending NAPI task to complete */
2306 #ifdef CONFIG_R8169_NAPI
2307 napi_disable(&tp->napi);
2310 rtl8169_irq_mask_and_ack(ioaddr);
2312 #ifdef CONFIG_R8169_NAPI
2313 napi_enable(&tp->napi);
2317 static void rtl8169_reinit_task(struct work_struct *work)
2319 struct rtl8169_private *tp =
2320 container_of(work, struct rtl8169_private, task.work);
2321 struct net_device *dev = tp->dev;
2326 if (!netif_running(dev))
2329 rtl8169_wait_for_quiescence(dev);
2332 ret = rtl8169_open(dev);
2333 if (unlikely(ret < 0)) {
2334 if (net_ratelimit() && netif_msg_drv(tp)) {
2335 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
2336 " Rescheduling.\n", dev->name, ret);
2338 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2345 static void rtl8169_reset_task(struct work_struct *work)
2347 struct rtl8169_private *tp =
2348 container_of(work, struct rtl8169_private, task.work);
2349 struct net_device *dev = tp->dev;
2353 if (!netif_running(dev))
2356 rtl8169_wait_for_quiescence(dev);
2358 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2359 rtl8169_tx_clear(tp);
2361 if (tp->dirty_rx == tp->cur_rx) {
2362 rtl8169_init_ring_indexes(tp);
2364 netif_wake_queue(dev);
2365 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2367 if (net_ratelimit() && netif_msg_intr(tp)) {
2368 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
2371 rtl8169_schedule_work(dev, rtl8169_reset_task);
2378 static void rtl8169_tx_timeout(struct net_device *dev)
2380 struct rtl8169_private *tp = netdev_priv(dev);
2382 rtl8169_hw_reset(tp->mmio_addr);
2384 /* Let's wait a bit while any (async) irq lands on */
2385 rtl8169_schedule_work(dev, rtl8169_reset_task);
2388 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2391 struct skb_shared_info *info = skb_shinfo(skb);
2392 unsigned int cur_frag, entry;
2393 struct TxDesc * uninitialized_var(txd);
2396 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2397 skb_frag_t *frag = info->frags + cur_frag;
2402 entry = (entry + 1) % NUM_TX_DESC;
2404 txd = tp->TxDescArray + entry;
2406 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2407 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2409 /* anti gcc 2.95.3 bugware (sic) */
2410 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2412 txd->opts1 = cpu_to_le32(status);
2413 txd->addr = cpu_to_le64(mapping);
2415 tp->tx_skb[entry].len = len;
2419 tp->tx_skb[entry].skb = skb;
2420 txd->opts1 |= cpu_to_le32(LastFrag);
2426 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2428 if (dev->features & NETIF_F_TSO) {
2429 u32 mss = skb_shinfo(skb)->gso_size;
2432 return LargeSend | ((mss & MSSMask) << MSSShift);
2434 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2435 const struct iphdr *ip = ip_hdr(skb);
2437 if (ip->protocol == IPPROTO_TCP)
2438 return IPCS | TCPCS;
2439 else if (ip->protocol == IPPROTO_UDP)
2440 return IPCS | UDPCS;
2441 WARN_ON(1); /* we need a WARN() */
2446 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2448 struct rtl8169_private *tp = netdev_priv(dev);
2449 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2450 struct TxDesc *txd = tp->TxDescArray + entry;
2451 void __iomem *ioaddr = tp->mmio_addr;
2455 int ret = NETDEV_TX_OK;
2457 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2458 if (netif_msg_drv(tp)) {
2460 "%s: BUG! Tx Ring full when queue awake!\n",
2466 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2469 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2471 frags = rtl8169_xmit_frags(tp, skb, opts1);
2473 len = skb_headlen(skb);
2478 if (unlikely(len < ETH_ZLEN)) {
2479 if (skb_padto(skb, ETH_ZLEN))
2480 goto err_update_stats;
2484 opts1 |= FirstFrag | LastFrag;
2485 tp->tx_skb[entry].skb = skb;
2488 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2490 tp->tx_skb[entry].len = len;
2491 txd->addr = cpu_to_le64(mapping);
2492 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2496 /* anti gcc 2.95.3 bugware (sic) */
2497 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2498 txd->opts1 = cpu_to_le32(status);
2500 dev->trans_start = jiffies;
2502 tp->cur_tx += frags + 1;
2506 RTL_W8(TxPoll, NPQ); /* set polling bit */
2508 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2509 netif_stop_queue(dev);
2511 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2512 netif_wake_queue(dev);
2519 netif_stop_queue(dev);
2520 ret = NETDEV_TX_BUSY;
2522 dev->stats.tx_dropped++;
2526 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2528 struct rtl8169_private *tp = netdev_priv(dev);
2529 struct pci_dev *pdev = tp->pci_dev;
2530 void __iomem *ioaddr = tp->mmio_addr;
2531 u16 pci_status, pci_cmd;
2533 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2534 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2536 if (netif_msg_intr(tp)) {
2538 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2539 dev->name, pci_cmd, pci_status);
2543 * The recovery sequence below admits a very elaborated explanation:
2544 * - it seems to work;
2545 * - I did not see what else could be done;
2546 * - it makes iop3xx happy.
2548 * Feel free to adjust to your needs.
2550 if (pdev->broken_parity_status)
2551 pci_cmd &= ~PCI_COMMAND_PARITY;
2553 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2555 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2557 pci_write_config_word(pdev, PCI_STATUS,
2558 pci_status & (PCI_STATUS_DETECTED_PARITY |
2559 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2560 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2562 /* The infamous DAC f*ckup only happens at boot time */
2563 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2564 if (netif_msg_intr(tp))
2565 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2566 tp->cp_cmd &= ~PCIDAC;
2567 RTL_W16(CPlusCmd, tp->cp_cmd);
2568 dev->features &= ~NETIF_F_HIGHDMA;
2571 rtl8169_hw_reset(ioaddr);
2573 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2576 static void rtl8169_tx_interrupt(struct net_device *dev,
2577 struct rtl8169_private *tp,
2578 void __iomem *ioaddr)
2580 unsigned int dirty_tx, tx_left;
2582 dirty_tx = tp->dirty_tx;
2584 tx_left = tp->cur_tx - dirty_tx;
2586 while (tx_left > 0) {
2587 unsigned int entry = dirty_tx % NUM_TX_DESC;
2588 struct ring_info *tx_skb = tp->tx_skb + entry;
2589 u32 len = tx_skb->len;
2593 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2594 if (status & DescOwn)
2597 dev->stats.tx_bytes += len;
2598 dev->stats.tx_packets++;
2600 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2602 if (status & LastFrag) {
2603 dev_kfree_skb_irq(tx_skb->skb);
2610 if (tp->dirty_tx != dirty_tx) {
2611 tp->dirty_tx = dirty_tx;
2613 if (netif_queue_stopped(dev) &&
2614 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2615 netif_wake_queue(dev);
2618 * 8168 hack: TxPoll requests are lost when the Tx packets are
2619 * too close. Let's kick an extra TxPoll request when a burst
2620 * of start_xmit activity is detected (if it is not detected,
2621 * it is slow enough). -- FR
2624 if (tp->cur_tx != dirty_tx)
2625 RTL_W8(TxPoll, NPQ);
2629 static inline int rtl8169_fragmented_frame(u32 status)
2631 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2634 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2636 u32 opts1 = le32_to_cpu(desc->opts1);
2637 u32 status = opts1 & RxProtoMask;
2639 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2640 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2641 ((status == RxProtoIP) && !(opts1 & IPFail)))
2642 skb->ip_summed = CHECKSUM_UNNECESSARY;
2644 skb->ip_summed = CHECKSUM_NONE;
2647 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2648 struct rtl8169_private *tp, int pkt_size,
2651 struct sk_buff *skb;
2654 if (pkt_size >= rx_copybreak)
2657 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2661 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2662 PCI_DMA_FROMDEVICE);
2663 skb_reserve(skb, NET_IP_ALIGN);
2664 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2671 static int rtl8169_rx_interrupt(struct net_device *dev,
2672 struct rtl8169_private *tp,
2673 void __iomem *ioaddr, u32 budget)
2675 unsigned int cur_rx, rx_left;
2676 unsigned int delta, count;
2678 cur_rx = tp->cur_rx;
2679 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2680 rx_left = rtl8169_rx_quota(rx_left, budget);
2682 for (; rx_left > 0; rx_left--, cur_rx++) {
2683 unsigned int entry = cur_rx % NUM_RX_DESC;
2684 struct RxDesc *desc = tp->RxDescArray + entry;
2688 status = le32_to_cpu(desc->opts1);
2690 if (status & DescOwn)
2692 if (unlikely(status & RxRES)) {
2693 if (netif_msg_rx_err(tp)) {
2695 "%s: Rx ERROR. status = %08x\n",
2698 dev->stats.rx_errors++;
2699 if (status & (RxRWT | RxRUNT))
2700 dev->stats.rx_length_errors++;
2702 dev->stats.rx_crc_errors++;
2703 if (status & RxFOVF) {
2704 rtl8169_schedule_work(dev, rtl8169_reset_task);
2705 dev->stats.rx_fifo_errors++;
2707 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2709 struct sk_buff *skb = tp->Rx_skbuff[entry];
2710 dma_addr_t addr = le64_to_cpu(desc->addr);
2711 int pkt_size = (status & 0x00001FFF) - 4;
2712 struct pci_dev *pdev = tp->pci_dev;
2715 * The driver does not support incoming fragmented
2716 * frames. They are seen as a symptom of over-mtu
2719 if (unlikely(rtl8169_fragmented_frame(status))) {
2720 dev->stats.rx_dropped++;
2721 dev->stats.rx_length_errors++;
2722 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2726 rtl8169_rx_csum(skb, desc);
2728 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2729 pci_dma_sync_single_for_device(pdev, addr,
2730 pkt_size, PCI_DMA_FROMDEVICE);
2731 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2733 pci_unmap_single(pdev, addr, pkt_size,
2734 PCI_DMA_FROMDEVICE);
2735 tp->Rx_skbuff[entry] = NULL;
2738 skb_put(skb, pkt_size);
2739 skb->protocol = eth_type_trans(skb, dev);
2741 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2742 rtl8169_rx_skb(skb);
2744 dev->last_rx = jiffies;
2745 dev->stats.rx_bytes += pkt_size;
2746 dev->stats.rx_packets++;
2749 /* Work around for AMD plateform. */
2750 if ((desc->opts2 & 0xfffe000) &&
2751 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2757 count = cur_rx - tp->cur_rx;
2758 tp->cur_rx = cur_rx;
2760 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2761 if (!delta && count && netif_msg_intr(tp))
2762 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2763 tp->dirty_rx += delta;
2766 * FIXME: until there is periodic timer to try and refill the ring,
2767 * a temporary shortage may definitely kill the Rx process.
2768 * - disable the asic to try and avoid an overflow and kick it again
2770 * - how do others driver handle this condition (Uh oh...).
2772 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2773 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2778 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2780 struct net_device *dev = dev_instance;
2781 struct rtl8169_private *tp = netdev_priv(dev);
2782 int boguscnt = max_interrupt_work;
2783 void __iomem *ioaddr = tp->mmio_addr;
2788 status = RTL_R16(IntrStatus);
2790 /* hotplug/major error/no more work/shared irq */
2791 if ((status == 0xFFFF) || !status)
2796 if (unlikely(!netif_running(dev))) {
2797 rtl8169_asic_down(ioaddr);
2801 status &= tp->intr_mask;
2803 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2805 if (!(status & tp->intr_event))
2808 /* Work around for rx fifo overflow */
2809 if (unlikely(status & RxFIFOOver) &&
2810 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2811 netif_stop_queue(dev);
2812 rtl8169_tx_timeout(dev);
2816 if (unlikely(status & SYSErr)) {
2817 rtl8169_pcierr_interrupt(dev);
2821 if (status & LinkChg)
2822 rtl8169_check_link_status(dev, tp, ioaddr);
2824 #ifdef CONFIG_R8169_NAPI
2825 if (status & tp->napi_event) {
2826 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2827 tp->intr_mask = ~tp->napi_event;
2829 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2830 __netif_rx_schedule(dev, &tp->napi);
2831 else if (netif_msg_intr(tp)) {
2832 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2839 if (status & (RxOK | RxOverflow | RxFIFOOver))
2840 rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0);
2843 if (status & (TxOK | TxErr))
2844 rtl8169_tx_interrupt(dev, tp, ioaddr);
2848 } while (boguscnt > 0);
2850 if (boguscnt <= 0) {
2851 if (netif_msg_intr(tp) && net_ratelimit() ) {
2853 "%s: Too much work at interrupt!\n", dev->name);
2855 /* Clear all interrupt sources. */
2856 RTL_W16(IntrStatus, 0xffff);
2859 return IRQ_RETVAL(handled);
2862 #ifdef CONFIG_R8169_NAPI
2863 static int rtl8169_poll(struct napi_struct *napi, int budget)
2865 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2866 struct net_device *dev = tp->dev;
2867 void __iomem *ioaddr = tp->mmio_addr;
2870 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
2871 rtl8169_tx_interrupt(dev, tp, ioaddr);
2873 if (work_done < budget) {
2874 netif_rx_complete(dev, napi);
2875 tp->intr_mask = 0xffff;
2877 * 20040426: the barrier is not strictly required but the
2878 * behavior of the irq handler could be less predictable
2879 * without it. Btw, the lack of flush for the posted pci
2880 * write is safe - FR
2883 RTL_W16(IntrMask, tp->intr_event);
2890 static void rtl8169_down(struct net_device *dev)
2892 struct rtl8169_private *tp = netdev_priv(dev);
2893 void __iomem *ioaddr = tp->mmio_addr;
2894 unsigned int poll_locked = 0;
2895 unsigned int intrmask;
2897 rtl8169_delete_timer(dev);
2899 netif_stop_queue(dev);
2902 spin_lock_irq(&tp->lock);
2904 rtl8169_asic_down(ioaddr);
2906 /* Update the error counts. */
2907 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
2908 RTL_W32(RxMissed, 0);
2910 spin_unlock_irq(&tp->lock);
2912 synchronize_irq(dev->irq);
2915 napi_disable(&tp->napi);
2919 /* Give a racing hard_start_xmit a few cycles to complete. */
2920 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
2923 * And now for the 50k$ question: are IRQ disabled or not ?
2925 * Two paths lead here:
2927 * -> netif_running() is available to sync the current code and the
2928 * IRQ handler. See rtl8169_interrupt for details.
2929 * 2) dev->change_mtu
2930 * -> rtl8169_poll can not be issued again and re-enable the
2931 * interruptions. Let's simply issue the IRQ down sequence again.
2933 * No loop if hotpluged or major error (0xffff).
2935 intrmask = RTL_R16(IntrMask);
2936 if (intrmask && (intrmask != 0xffff))
2939 rtl8169_tx_clear(tp);
2941 rtl8169_rx_clear(tp);
2944 static int rtl8169_close(struct net_device *dev)
2946 struct rtl8169_private *tp = netdev_priv(dev);
2947 struct pci_dev *pdev = tp->pci_dev;
2951 free_irq(dev->irq, dev);
2953 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2955 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2957 tp->TxDescArray = NULL;
2958 tp->RxDescArray = NULL;
2963 static void rtl_set_rx_mode(struct net_device *dev)
2965 struct rtl8169_private *tp = netdev_priv(dev);
2966 void __iomem *ioaddr = tp->mmio_addr;
2967 unsigned long flags;
2968 u32 mc_filter[2]; /* Multicast hash filter */
2972 if (dev->flags & IFF_PROMISC) {
2973 /* Unconditionally log net taps. */
2974 if (netif_msg_link(tp)) {
2975 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2979 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2981 mc_filter[1] = mc_filter[0] = 0xffffffff;
2982 } else if ((dev->mc_count > multicast_filter_limit)
2983 || (dev->flags & IFF_ALLMULTI)) {
2984 /* Too many to filter perfectly -- accept all multicasts. */
2985 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2986 mc_filter[1] = mc_filter[0] = 0xffffffff;
2988 struct dev_mc_list *mclist;
2991 rx_mode = AcceptBroadcast | AcceptMyPhys;
2992 mc_filter[1] = mc_filter[0] = 0;
2993 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2994 i++, mclist = mclist->next) {
2995 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2996 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2997 rx_mode |= AcceptMulticast;
3001 spin_lock_irqsave(&tp->lock, flags);
3003 tmp = rtl8169_rx_config | rx_mode |
3004 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3006 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
3007 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
3008 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3009 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
3010 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
3011 (tp->mac_version == RTL_GIGA_MAC_VER_16) ||
3012 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
3013 mc_filter[0] = 0xffffffff;
3014 mc_filter[1] = 0xffffffff;
3017 RTL_W32(MAR0 + 0, mc_filter[0]);
3018 RTL_W32(MAR0 + 4, mc_filter[1]);
3020 RTL_W32(RxConfig, tmp);
3022 spin_unlock_irqrestore(&tp->lock, flags);
3026 * rtl8169_get_stats - Get rtl8169 read/write statistics
3027 * @dev: The Ethernet Device to get statistics for
3029 * Get TX/RX statistics for rtl8169
3031 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3033 struct rtl8169_private *tp = netdev_priv(dev);
3034 void __iomem *ioaddr = tp->mmio_addr;
3035 unsigned long flags;
3037 if (netif_running(dev)) {
3038 spin_lock_irqsave(&tp->lock, flags);
3039 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3040 RTL_W32(RxMissed, 0);
3041 spin_unlock_irqrestore(&tp->lock, flags);
3049 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3051 struct net_device *dev = pci_get_drvdata(pdev);
3052 struct rtl8169_private *tp = netdev_priv(dev);
3053 void __iomem *ioaddr = tp->mmio_addr;
3055 if (!netif_running(dev))
3056 goto out_pci_suspend;
3058 netif_device_detach(dev);
3059 netif_stop_queue(dev);
3061 spin_lock_irq(&tp->lock);
3063 rtl8169_asic_down(ioaddr);
3065 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3066 RTL_W32(RxMissed, 0);
3068 spin_unlock_irq(&tp->lock);
3071 pci_save_state(pdev);
3072 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3073 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3074 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3079 static int rtl8169_resume(struct pci_dev *pdev)
3081 struct net_device *dev = pci_get_drvdata(pdev);
3083 pci_set_power_state(pdev, PCI_D0);
3084 pci_restore_state(pdev);
3085 pci_enable_wake(pdev, PCI_D0, 0);
3087 if (!netif_running(dev))
3090 netif_device_attach(dev);
3092 rtl8169_schedule_work(dev, rtl8169_reset_task);
3097 #endif /* CONFIG_PM */
3099 static struct pci_driver rtl8169_pci_driver = {
3101 .id_table = rtl8169_pci_tbl,
3102 .probe = rtl8169_init_one,
3103 .remove = __devexit_p(rtl8169_remove_one),
3105 .suspend = rtl8169_suspend,
3106 .resume = rtl8169_resume,
3110 static int __init rtl8169_init_module(void)
3112 return pci_register_driver(&rtl8169_pci_driver);
3115 static void __exit rtl8169_cleanup_module(void)
3117 pci_unregister_driver(&rtl8169_pci_driver);
3120 module_init(rtl8169_init_module);
3121 module_exit(rtl8169_cleanup_module);