drivers/net/r8169.c

   1 /*
   2 =========================================================================
   3  r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
   4  --------------------------------------------------------------------
   5
   6  History:
   7  Feb  4 2002    - created initially by ShuChen <shuchen@realtek.com.tw>.
   8  May 20 2002    - Add link status force-mode and TBI mode support.
   9         2004    - Massive updates. See kernel SCM system for details.
  10 =========================================================================
  11 VERSION 1.1     <2002/10/4>
  12
  13         The bit4:0 of MII register 4 is called "selector field", and have to be
  14         00001b to indicate support of IEEE std 802.3 during NWay process of
  15         exchanging Link Code Word (FLP).
  16
  17 VERSION 1.2     <2002/11/30>
  18
  19         - Large style cleanup
  20         - Use ether_crc in stock kernel (linux/crc32.h)
  21         - Copy mc_filter setup code from 8139cp
  22           (includes an optimization, and avoids set_bit use)
  23
  24 VERSION 1.6LK   <2004/04/14>
  25
  26         - Merge of Realtek's version 1.6
  27         - Conversion to DMA API
  28         - Suspend/resume
  29         - Endianness
  30         - Misc Rx/Tx bugs
  31
  32 VERSION 2.2LK   <2005/01/25>
  33
  34         - RX csum, TX csum/SG, TSO
  35         - VLAN
  36         - baby (< 7200) Jumbo frames support
  37         - Merge of Realtek's version 2.2 (new phy)
  38  */
  39
  40 #include <linux/module.h>
  41 #include <linux/moduleparam.h>
  42 #include <linux/pci.h>
  43 #include <linux/netdevice.h>
  44 #include <linux/etherdevice.h>
  45 #include <linux/delay.h>
  46 #include <linux/ethtool.h>
  47 #include <linux/mii.h>
  48 #include <linux/if_vlan.h>
  49 #include <linux/crc32.h>
  50 #include <linux/in.h>
  51 #include <linux/ip.h>
  52 #include <linux/tcp.h>
  53 #include <linux/init.h>
  54 #include <linux/dma-mapping.h>
  55
  56 #include <asm/system.h>
  57 #include <asm/io.h>
  58 #include <asm/irq.h>
  59
  60 #ifdef CONFIG_R8169_NAPI
  61 #define NAPI_SUFFIX     "-NAPI"
  62 #else
  63 #define NAPI_SUFFIX     ""
  64 #endif
  65
  66 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
  67 #define MODULENAME "r8169"
  68 #define PFX MODULENAME ": "
  69
  70 #ifdef RTL8169_DEBUG
  71 #define assert(expr) \
  72         if (!(expr)) {                                  \
  73                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  74                 #expr,__FILE__,__FUNCTION__,__LINE__);          \
  75         }
  76 #define dprintk(fmt, args...)   do { printk(PFX fmt, ## args); } while (0)
  77 #else
  78 #define assert(expr) do {} while (0)
  79 #define dprintk(fmt, args...)   do {} while (0)
  80 #endif /* RTL8169_DEBUG */
  81
  82 #define R8169_MSG_DEFAULT \
  83         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  84
  85 #define TX_BUFFS_AVAIL(tp) \
  86         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  87
  88 #ifdef CONFIG_R8169_NAPI
  89 #define rtl8169_rx_skb                  netif_receive_skb
  90 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_receive_skb
  91 #define rtl8169_rx_quota(count, quota)  min(count, quota)
  92 #else
  93 #define rtl8169_rx_skb                  netif_rx
  94 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_rx
  95 #define rtl8169_rx_quota(count, quota)  count
  96 #endif
  97
  98 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  99 static const int max_interrupt_work = 20;
 100
 101 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
 102    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
 103 static const int multicast_filter_limit = 32;
 104
 105 /* MAC address length */
 106 #define MAC_ADDR_LEN    6
 107
 108 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
 109 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
 110 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
 111 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
 112 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
 113 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
 114 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
 115
 116 #define R8169_REGS_SIZE         256
 117 #define R8169_NAPI_WEIGHT       64
 118 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
 119 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
 120 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
 121 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
 122 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
 123
 124 #define RTL8169_TX_TIMEOUT      (6*HZ)
 125 #define RTL8169_PHY_TIMEOUT     (10*HZ)
 126
 127 /* write/read MMIO register */
 128 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 129 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 130 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 131 #define RTL_R8(reg)             readb (ioaddr + (reg))
 132 #define RTL_R16(reg)            readw (ioaddr + (reg))
 133 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
 134
 135 enum mac_version {
 136         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
 137         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
 138         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 139         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 140         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 141         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 142         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 143         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
 144         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
 145         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
 146         RTL_GIGA_MAC_VER_15 = 0x0f  // 8101
 147 };
 148
 149 enum phy_version {
 150         RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 151         RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 152         RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 153         RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
 154         RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
 155         RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
 156 };
 157
 158 #define _R(NAME,MAC,MASK) \
 159         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 160
 161 static const struct {
 162         const char *name;
 163         u8 mac_version;
 164         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 165 } rtl_chip_info[] = {
 166         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 167         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 168         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 169         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 170         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 171         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 172         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 173         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 174         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 175         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 176         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880)  // PCI-E 8139
 177 };
 178 #undef _R
 179
 180 enum cfg_version {
 181         RTL_CFG_0 = 0x00,
 182         RTL_CFG_1,
 183         RTL_CFG_2
 184 };
 185
 186 static void rtl_hw_start_8169(struct net_device *);
 187 static void rtl_hw_start_8168(struct net_device *);
 188 static void rtl_hw_start_8101(struct net_device *);
 189
 190 static struct pci_device_id rtl8169_pci_tbl[] = {
 191         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 192         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 193         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 194         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 195         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 196         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 197         { PCI_DEVICE(0x1259,                    0xc107), 0, 0, RTL_CFG_0 },
 198         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 199         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 200                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 201         {0,},
 202 };
 203
 204 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 205
 206 static int rx_copybreak = 200;
 207 static int use_dac;
 208 static struct {
 209         u32 msg_enable;
 210 } debug = { -1 };
 211
 212 enum RTL8169_registers {
 213         MAC0 = 0,               /* Ethernet hardware address. */
 214         MAR0 = 8,               /* Multicast filter. */
 215         CounterAddrLow = 0x10,
 216         CounterAddrHigh = 0x14,
 217         TxDescStartAddrLow = 0x20,
 218         TxDescStartAddrHigh = 0x24,
 219         TxHDescStartAddrLow = 0x28,
 220         TxHDescStartAddrHigh = 0x2c,
 221         FLASH = 0x30,
 222         ERSR = 0x36,
 223         ChipCmd = 0x37,
 224         TxPoll = 0x38,
 225         IntrMask = 0x3C,
 226         IntrStatus = 0x3E,
 227         TxConfig = 0x40,
 228         RxConfig = 0x44,
 229         RxMissed = 0x4C,
 230         Cfg9346 = 0x50,
 231         Config0 = 0x51,
 232         Config1 = 0x52,
 233         Config2 = 0x53,
 234         Config3 = 0x54,
 235         Config4 = 0x55,
 236         Config5 = 0x56,
 237         MultiIntr = 0x5C,
 238         PHYAR = 0x60,
 239         TBICSR = 0x64,
 240         TBI_ANAR = 0x68,
 241         TBI_LPAR = 0x6A,
 242         PHYstatus = 0x6C,
 243         RxMaxSize = 0xDA,
 244         CPlusCmd = 0xE0,
 245         IntrMitigate = 0xE2,
 246         RxDescAddrLow = 0xE4,
 247         RxDescAddrHigh = 0xE8,
 248         EarlyTxThres = 0xEC,
 249         FuncEvent = 0xF0,
 250         FuncEventMask = 0xF4,
 251         FuncPresetState = 0xF8,
 252         FuncForceEvent = 0xFC,
 253 };
 254
 255 enum RTL8169_register_content {
 256         /* InterruptStatusBits */
 257         SYSErr = 0x8000,
 258         PCSTimeout = 0x4000,
 259         SWInt = 0x0100,
 260         TxDescUnavail = 0x80,
 261         RxFIFOOver = 0x40,
 262         LinkChg = 0x20,
 263         RxOverflow = 0x10,
 264         TxErr = 0x08,
 265         TxOK = 0x04,
 266         RxErr = 0x02,
 267         RxOK = 0x01,
 268
 269         /* RxStatusDesc */
 270         RxFOVF  = (1 << 23),
 271         RxRWT   = (1 << 22),
 272         RxRES   = (1 << 21),
 273         RxRUNT  = (1 << 20),
 274         RxCRC   = (1 << 19),
 275
 276         /* ChipCmdBits */
 277         CmdReset = 0x10,
 278         CmdRxEnb = 0x08,
 279         CmdTxEnb = 0x04,
 280         RxBufEmpty = 0x01,
 281
 282         /* Cfg9346Bits */
 283         Cfg9346_Lock = 0x00,
 284         Cfg9346_Unlock = 0xC0,
 285
 286         /* rx_mode_bits */
 287         AcceptErr = 0x20,
 288         AcceptRunt = 0x10,
 289         AcceptBroadcast = 0x08,
 290         AcceptMulticast = 0x04,
 291         AcceptMyPhys = 0x02,
 292         AcceptAllPhys = 0x01,
 293
 294         /* RxConfigBits */
 295         RxCfgFIFOShift = 13,
 296         RxCfgDMAShift = 8,
 297
 298         /* TxConfigBits */
 299         TxInterFrameGapShift = 24,
 300         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 301
 302         /* Config1 register p.24 */
 303         PMEnable        = (1 << 0),     /* Power Management Enable */
 304
 305         /* Config2 register p. 25 */
 306         PCI_Clock_66MHz = 0x01,
 307         PCI_Clock_33MHz = 0x00,
 308
 309         /* Config3 register p.25 */
 310         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 311         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 312
 313         /* Config5 register p.27 */
 314         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 315         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 316         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 317         LanWake         = (1 << 1),     /* LanWake enable/disable */
 318         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 319
 320         /* TBICSR p.28 */
 321         TBIReset        = 0x80000000,
 322         TBILoopback     = 0x40000000,
 323         TBINwEnable     = 0x20000000,
 324         TBINwRestart    = 0x10000000,
 325         TBILinkOk       = 0x02000000,
 326         TBINwComplete   = 0x01000000,
 327
 328         /* CPlusCmd p.31 */
 329         PktCntrDisable  = (1 << 7),     // 8168
 330         RxVlan          = (1 << 6),
 331         RxChkSum        = (1 << 5),
 332         PCIDAC          = (1 << 4),
 333         PCIMulRW        = (1 << 3),
 334         INTT_0          = 0x0000,       // 8168
 335         INTT_1          = 0x0001,       // 8168
 336         INTT_2          = 0x0002,       // 8168
 337         INTT_3          = 0x0003,       // 8168
 338
 339         /* rtl8169_PHYstatus */
 340         TBI_Enable = 0x80,
 341         TxFlowCtrl = 0x40,
 342         RxFlowCtrl = 0x20,
 343         _1000bpsF = 0x10,
 344         _100bps = 0x08,
 345         _10bps = 0x04,
 346         LinkStatus = 0x02,
 347         FullDup = 0x01,
 348
 349         /* _TBICSRBit */
 350         TBILinkOK = 0x02000000,
 351
 352         /* DumpCounterCommand */
 353         CounterDump = 0x8,
 354 };
 355
 356 enum _DescStatusBit {
 357         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 358         RingEnd         = (1 << 30), /* End of descriptor ring */
 359         FirstFrag       = (1 << 29), /* First segment of a packet */
 360         LastFrag        = (1 << 28), /* Final segment of a packet */
 361
 362         /* Tx private */
 363         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 364         MSSShift        = 16,        /* MSS value position */
 365         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 366         IPCS            = (1 << 18), /* Calculate IP checksum */
 367         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 368         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 369         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 370
 371         /* Rx private */
 372         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 373         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 374
 375 #define RxProtoUDP      (PID1)
 376 #define RxProtoTCP      (PID0)
 377 #define RxProtoIP       (PID1 | PID0)
 378 #define RxProtoMask     RxProtoIP
 379
 380         IPFail          = (1 << 16), /* IP checksum failed */
 381         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 382         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 383         RxVlanTag       = (1 << 16), /* VLAN tag available */
 384 };
 385
 386 #define RsvdMask        0x3fffc000
 387
 388 struct TxDesc {
 389         u32 opts1;
 390         u32 opts2;
 391         u64 addr;
 392 };
 393
 394 struct RxDesc {
 395         u32 opts1;
 396         u32 opts2;
 397         u64 addr;
 398 };
 399
 400 struct ring_info {
 401         struct sk_buff  *skb;
 402         u32             len;
 403         u8              __pad[sizeof(void *) - sizeof(u32)];
 404 };
 405
 406 struct rtl8169_private {
 407         void __iomem *mmio_addr;        /* memory map physical address */
 408         struct pci_dev *pci_dev;        /* Index of PCI device */
 409         struct net_device *dev;
 410         struct net_device_stats stats;  /* statistics of net device */
 411         spinlock_t lock;                /* spin lock flag */
 412         u32 msg_enable;
 413         int chipset;
 414         int mac_version;
 415         int phy_version;
 416         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 417         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 418         u32 dirty_rx;
 419         u32 dirty_tx;
 420         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 421         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 422         dma_addr_t TxPhyAddr;
 423         dma_addr_t RxPhyAddr;
 424         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 425         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 426         unsigned align;
 427         unsigned rx_buf_sz;
 428         struct timer_list timer;
 429         u16 cp_cmd;
 430         u16 intr_event;
 431         u16 napi_event;
 432         u16 intr_mask;
 433         int phy_auto_nego_reg;
 434         int phy_1000_ctrl_reg;
 435 #ifdef CONFIG_R8169_VLAN
 436         struct vlan_group *vlgrp;
 437 #endif
 438         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 439         void (*get_settings)(struct net_device *, struct ethtool_cmd *);
 440         void (*phy_reset_enable)(void __iomem *);
 441         void (*hw_start)(struct net_device *);
 442         unsigned int (*phy_reset_pending)(void __iomem *);
 443         unsigned int (*link_ok)(void __iomem *);
 444         struct delayed_work task;
 445         unsigned wol_enabled : 1;
 446 };
 447
 448 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 449 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 450 module_param(rx_copybreak, int, 0);
 451 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 452 module_param(use_dac, int, 0);
 453 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 454 module_param_named(debug, debug.msg_enable, int, 0);
 455 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 456 MODULE_LICENSE("GPL");
 457 MODULE_VERSION(RTL8169_VERSION);
 458
 459 static int rtl8169_open(struct net_device *dev);
 460 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 461 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 462 static int rtl8169_init_ring(struct net_device *dev);
 463 static void rtl_hw_start(struct net_device *dev);
 464 static int rtl8169_close(struct net_device *dev);
 465 static void rtl_set_rx_mode(struct net_device *dev);
 466 static void rtl8169_tx_timeout(struct net_device *dev);
 467 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 468 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 469                                 void __iomem *);
 470 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 471 static void rtl8169_down(struct net_device *dev);
 472 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 473
 474 #ifdef CONFIG_R8169_NAPI
 475 static int rtl8169_poll(struct net_device *dev, int *budget);
 476 #endif
 477
 478 static const unsigned int rtl8169_rx_config =
 479         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 480
 481 static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
 482 {
 483         int i;
 484
 485         RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
 486
 487         for (i = 20; i > 0; i--) {
 488                 /* Check if the RTL8169 has completed writing to the specified MII register */
 489                 if (!(RTL_R32(PHYAR) & 0x80000000))
 490                         break;
 491                 udelay(25);
 492         }
 493 }
 494
 495 static int mdio_read(void __iomem *ioaddr, int RegAddr)
 496 {
 497         int i, value = -1;
 498
 499         RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
 500
 501         for (i = 20; i > 0; i--) {
 502                 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
 503                 if (RTL_R32(PHYAR) & 0x80000000) {
 504                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
 505                         break;
 506                 }
 507                 udelay(25);
 508         }
 509         return value;
 510 }
 511
 512 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 513 {
 514         RTL_W16(IntrMask, 0x0000);
 515
 516         RTL_W16(IntrStatus, 0xffff);
 517 }
 518
 519 static void rtl8169_asic_down(void __iomem *ioaddr)
 520 {
 521         RTL_W8(ChipCmd, 0x00);
 522         rtl8169_irq_mask_and_ack(ioaddr);
 523         RTL_R16(CPlusCmd);
 524 }
 525
 526 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 527 {
 528         return RTL_R32(TBICSR) & TBIReset;
 529 }
 530
 531 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 532 {
 533         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 534 }
 535
 536 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 537 {
 538         return RTL_R32(TBICSR) & TBILinkOk;
 539 }
 540
 541 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 542 {
 543         return RTL_R8(PHYstatus) & LinkStatus;
 544 }
 545
 546 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 547 {
 548         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 549 }
 550
 551 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 552 {
 553         unsigned int val;
 554
 555         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 556         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 557 }
 558
 559 static void rtl8169_check_link_status(struct net_device *dev,
 560                                       struct rtl8169_private *tp, void __iomem *ioaddr)
 561 {
 562         unsigned long flags;
 563
 564         spin_lock_irqsave(&tp->lock, flags);
 565         if (tp->link_ok(ioaddr)) {
 566                 netif_carrier_on(dev);
 567                 if (netif_msg_ifup(tp))
 568                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
 569         } else {
 570                 if (netif_msg_ifdown(tp))
 571                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
 572                 netif_carrier_off(dev);
 573         }
 574         spin_unlock_irqrestore(&tp->lock, flags);
 575 }
 576
 577 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 578 {
 579         struct rtl8169_private *tp = netdev_priv(dev);
 580         void __iomem *ioaddr = tp->mmio_addr;
 581         u8 options;
 582
 583         wol->wolopts = 0;
 584
 585 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 586         wol->supported = WAKE_ANY;
 587
 588         spin_lock_irq(&tp->lock);
 589
 590         options = RTL_R8(Config1);
 591         if (!(options & PMEnable))
 592                 goto out_unlock;
 593
 594         options = RTL_R8(Config3);
 595         if (options & LinkUp)
 596                 wol->wolopts |= WAKE_PHY;
 597         if (options & MagicPacket)
 598                 wol->wolopts |= WAKE_MAGIC;
 599
 600         options = RTL_R8(Config5);
 601         if (options & UWF)
 602                 wol->wolopts |= WAKE_UCAST;
 603         if (options & BWF)
 604                 wol->wolopts |= WAKE_BCAST;
 605         if (options & MWF)
 606                 wol->wolopts |= WAKE_MCAST;
 607
 608 out_unlock:
 609         spin_unlock_irq(&tp->lock);
 610 }
 611
 612 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 613 {
 614         struct rtl8169_private *tp = netdev_priv(dev);
 615         void __iomem *ioaddr = tp->mmio_addr;
 616         int i;
 617         static struct {
 618                 u32 opt;
 619                 u16 reg;
 620                 u8  mask;
 621         } cfg[] = {
 622                 { WAKE_ANY,   Config1, PMEnable },
 623                 { WAKE_PHY,   Config3, LinkUp },
 624                 { WAKE_MAGIC, Config3, MagicPacket },
 625                 { WAKE_UCAST, Config5, UWF },
 626                 { WAKE_BCAST, Config5, BWF },
 627                 { WAKE_MCAST, Config5, MWF },
 628                 { WAKE_ANY,   Config5, LanWake }
 629         };
 630
 631         spin_lock_irq(&tp->lock);
 632
 633         RTL_W8(Cfg9346, Cfg9346_Unlock);
 634
 635         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 636                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 637                 if (wol->wolopts & cfg[i].opt)
 638                         options |= cfg[i].mask;
 639                 RTL_W8(cfg[i].reg, options);
 640         }
 641
 642         RTL_W8(Cfg9346, Cfg9346_Lock);
 643
 644         tp->wol_enabled = (wol->wolopts) ? 1 : 0;
 645
 646         spin_unlock_irq(&tp->lock);
 647
 648         return 0;
 649 }
 650
 651 static void rtl8169_get_drvinfo(struct net_device *dev,
 652                                 struct ethtool_drvinfo *info)
 653 {
 654         struct rtl8169_private *tp = netdev_priv(dev);
 655
 656         strcpy(info->driver, MODULENAME);
 657         strcpy(info->version, RTL8169_VERSION);
 658         strcpy(info->bus_info, pci_name(tp->pci_dev));
 659 }
 660
 661 static int rtl8169_get_regs_len(struct net_device *dev)
 662 {
 663         return R8169_REGS_SIZE;
 664 }
 665
 666 static int rtl8169_set_speed_tbi(struct net_device *dev,
 667                                  u8 autoneg, u16 speed, u8 duplex)
 668 {
 669         struct rtl8169_private *tp = netdev_priv(dev);
 670         void __iomem *ioaddr = tp->mmio_addr;
 671         int ret = 0;
 672         u32 reg;
 673
 674         reg = RTL_R32(TBICSR);
 675         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 676             (duplex == DUPLEX_FULL)) {
 677                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 678         } else if (autoneg == AUTONEG_ENABLE)
 679                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 680         else {
 681                 if (netif_msg_link(tp)) {
 682                         printk(KERN_WARNING "%s: "
 683                                "incorrect speed setting refused in TBI mode\n",
 684                                dev->name);
 685                 }
 686                 ret = -EOPNOTSUPP;
 687         }
 688
 689         return ret;
 690 }
 691
 692 static int rtl8169_set_speed_xmii(struct net_device *dev,
 693                                   u8 autoneg, u16 speed, u8 duplex)
 694 {
 695         struct rtl8169_private *tp = netdev_priv(dev);
 696         void __iomem *ioaddr = tp->mmio_addr;
 697         int auto_nego, giga_ctrl;
 698
 699         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 700         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
 701                        ADVERTISE_100HALF | ADVERTISE_100FULL);
 702         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 703         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 704
 705         if (autoneg == AUTONEG_ENABLE) {
 706                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 707                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 708                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 709         } else {
 710                 if (speed == SPEED_10)
 711                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 712                 else if (speed == SPEED_100)
 713                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
 714                 else if (speed == SPEED_1000)
 715                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 716
 717                 if (duplex == DUPLEX_HALF)
 718                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
 719
 720                 if (duplex == DUPLEX_FULL)
 721                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
 722
 723                 /* This tweak comes straight from Realtek's driver. */
 724                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
 725                     (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
 726                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
 727                 }
 728         }
 729
 730         /* The 8100e/8101e do Fast Ethernet only. */
 731         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 732             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
 733             (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
 734                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
 735                     netif_msg_link(tp)) {
 736                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
 737                                dev->name);
 738                 }
 739                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 740         }
 741
 742         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 743
 744         tp->phy_auto_nego_reg = auto_nego;
 745         tp->phy_1000_ctrl_reg = giga_ctrl;
 746
 747         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 748         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 749         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
 750         return 0;
 751 }
 752
 753 static int rtl8169_set_speed(struct net_device *dev,
 754                              u8 autoneg, u16 speed, u8 duplex)
 755 {
 756         struct rtl8169_private *tp = netdev_priv(dev);
 757         int ret;
 758
 759         ret = tp->set_speed(dev, autoneg, speed, duplex);
 760
 761         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 762                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 763
 764         return ret;
 765 }
 766
 767 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 768 {
 769         struct rtl8169_private *tp = netdev_priv(dev);
 770         unsigned long flags;
 771         int ret;
 772
 773         spin_lock_irqsave(&tp->lock, flags);
 774         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 775         spin_unlock_irqrestore(&tp->lock, flags);
 776
 777         return ret;
 778 }
 779
 780 static u32 rtl8169_get_rx_csum(struct net_device *dev)
 781 {
 782         struct rtl8169_private *tp = netdev_priv(dev);
 783
 784         return tp->cp_cmd & RxChkSum;
 785 }
 786
 787 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
 788 {
 789         struct rtl8169_private *tp = netdev_priv(dev);
 790         void __iomem *ioaddr = tp->mmio_addr;
 791         unsigned long flags;
 792
 793         spin_lock_irqsave(&tp->lock, flags);
 794
 795         if (data)
 796                 tp->cp_cmd |= RxChkSum;
 797         else
 798                 tp->cp_cmd &= ~RxChkSum;
 799
 800         RTL_W16(CPlusCmd, tp->cp_cmd);
 801         RTL_R16(CPlusCmd);
 802
 803         spin_unlock_irqrestore(&tp->lock, flags);
 804
 805         return 0;
 806 }
 807
 808 #ifdef CONFIG_R8169_VLAN
 809
 810 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 811                                       struct sk_buff *skb)
 812 {
 813         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
 814                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
 815 }
 816
 817 static void rtl8169_vlan_rx_register(struct net_device *dev,
 818                                      struct vlan_group *grp)
 819 {
 820         struct rtl8169_private *tp = netdev_priv(dev);
 821         void __iomem *ioaddr = tp->mmio_addr;
 822         unsigned long flags;
 823
 824         spin_lock_irqsave(&tp->lock, flags);
 825         tp->vlgrp = grp;
 826         if (tp->vlgrp)
 827                 tp->cp_cmd |= RxVlan;
 828         else
 829                 tp->cp_cmd &= ~RxVlan;
 830         RTL_W16(CPlusCmd, tp->cp_cmd);
 831         RTL_R16(CPlusCmd);
 832         spin_unlock_irqrestore(&tp->lock, flags);
 833 }
 834
 835 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 836                                struct sk_buff *skb)
 837 {
 838         u32 opts2 = le32_to_cpu(desc->opts2);
 839         int ret;
 840
 841         if (tp->vlgrp && (opts2 & RxVlanTag)) {
 842                 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
 843                                        swab16(opts2 & 0xffff));
 844                 ret = 0;
 845         } else
 846                 ret = -1;
 847         desc->opts2 = 0;
 848         return ret;
 849 }
 850
 851 #else /* !CONFIG_R8169_VLAN */
 852
 853 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 854                                       struct sk_buff *skb)
 855 {
 856         return 0;
 857 }
 858
 859 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 860                                struct sk_buff *skb)
 861 {
 862         return -1;
 863 }
 864
 865 #endif
 866
 867 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
 868 {
 869         struct rtl8169_private *tp = netdev_priv(dev);
 870         void __iomem *ioaddr = tp->mmio_addr;
 871         u32 status;
 872
 873         cmd->supported =
 874                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
 875         cmd->port = PORT_FIBRE;
 876         cmd->transceiver = XCVR_INTERNAL;
 877
 878         status = RTL_R32(TBICSR);
 879         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
 880         cmd->autoneg = !!(status & TBINwEnable);
 881
 882         cmd->speed = SPEED_1000;
 883         cmd->duplex = DUPLEX_FULL; /* Always set */
 884 }
 885
 886 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
 887 {
 888         struct rtl8169_private *tp = netdev_priv(dev);
 889         void __iomem *ioaddr = tp->mmio_addr;
 890         u8 status;
 891
 892         cmd->supported = SUPPORTED_10baseT_Half |
 893                          SUPPORTED_10baseT_Full |
 894                          SUPPORTED_100baseT_Half |
 895                          SUPPORTED_100baseT_Full |
 896                          SUPPORTED_1000baseT_Full |
 897                          SUPPORTED_Autoneg |
 898                          SUPPORTED_TP;
 899
 900         cmd->autoneg = 1;
 901         cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
 902
 903         if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
 904                 cmd->advertising |= ADVERTISED_10baseT_Half;
 905         if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
 906                 cmd->advertising |= ADVERTISED_10baseT_Full;
 907         if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
 908                 cmd->advertising |= ADVERTISED_100baseT_Half;
 909         if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
 910                 cmd->advertising |= ADVERTISED_100baseT_Full;
 911         if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
 912                 cmd->advertising |= ADVERTISED_1000baseT_Full;
 913
 914         status = RTL_R8(PHYstatus);
 915
 916         if (status & _1000bpsF)
 917                 cmd->speed = SPEED_1000;
 918         else if (status & _100bps)
 919                 cmd->speed = SPEED_100;
 920         else if (status & _10bps)
 921                 cmd->speed = SPEED_10;
 922
 923         if (status & TxFlowCtrl)
 924                 cmd->advertising |= ADVERTISED_Asym_Pause;
 925         if (status & RxFlowCtrl)
 926                 cmd->advertising |= ADVERTISED_Pause;
 927
 928         cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
 929                       DUPLEX_FULL : DUPLEX_HALF;
 930 }
 931
 932 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 933 {
 934         struct rtl8169_private *tp = netdev_priv(dev);
 935         unsigned long flags;
 936
 937         spin_lock_irqsave(&tp->lock, flags);
 938
 939         tp->get_settings(dev, cmd);
 940
 941         spin_unlock_irqrestore(&tp->lock, flags);
 942         return 0;
 943 }
 944
 945 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 946                              void *p)
 947 {
 948         struct rtl8169_private *tp = netdev_priv(dev);
 949         unsigned long flags;
 950
 951         if (regs->len > R8169_REGS_SIZE)
 952                 regs->len = R8169_REGS_SIZE;
 953
 954         spin_lock_irqsave(&tp->lock, flags);
 955         memcpy_fromio(p, tp->mmio_addr, regs->len);
 956         spin_unlock_irqrestore(&tp->lock, flags);
 957 }
 958
 959 static u32 rtl8169_get_msglevel(struct net_device *dev)
 960 {
 961         struct rtl8169_private *tp = netdev_priv(dev);
 962
 963         return tp->msg_enable;
 964 }
 965
 966 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
 967 {
 968         struct rtl8169_private *tp = netdev_priv(dev);
 969
 970         tp->msg_enable = value;
 971 }
 972
 973 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
 974         "tx_packets",
 975         "rx_packets",
 976         "tx_errors",
 977         "rx_errors",
 978         "rx_missed",
 979         "align_errors",
 980         "tx_single_collisions",
 981         "tx_multi_collisions",
 982         "unicast",
 983         "broadcast",
 984         "multicast",
 985         "tx_aborted",
 986         "tx_underrun",
 987 };
 988
 989 struct rtl8169_counters {
 990         u64     tx_packets;
 991         u64     rx_packets;
 992         u64     tx_errors;
 993         u32     rx_errors;
 994         u16     rx_missed;
 995         u16     align_errors;
 996         u32     tx_one_collision;
 997         u32     tx_multi_collision;
 998         u64     rx_unicast;
 999         u64     rx_broadcast;
1000         u32     rx_multicast;
1001         u16     tx_aborted;
1002         u16     tx_underun;
1003 };
1004
1005 static int rtl8169_get_stats_count(struct net_device *dev)
1006 {
1007         return ARRAY_SIZE(rtl8169_gstrings);
1008 }
1009
1010 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1011                                       struct ethtool_stats *stats, u64 *data)
1012 {
1013         struct rtl8169_private *tp = netdev_priv(dev);
1014         void __iomem *ioaddr = tp->mmio_addr;
1015         struct rtl8169_counters *counters;
1016         dma_addr_t paddr;
1017         u32 cmd;
1018
1019         ASSERT_RTNL();
1020
1021         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1022         if (!counters)
1023                 return;
1024
1025         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1026         cmd = (u64)paddr & DMA_32BIT_MASK;
1027         RTL_W32(CounterAddrLow, cmd);
1028         RTL_W32(CounterAddrLow, cmd | CounterDump);
1029
1030         while (RTL_R32(CounterAddrLow) & CounterDump) {
1031                 if (msleep_interruptible(1))
1032                         break;
1033         }
1034
1035         RTL_W32(CounterAddrLow, 0);
1036         RTL_W32(CounterAddrHigh, 0);
1037
1038         data[0] = le64_to_cpu(counters->tx_packets);
1039         data[1] = le64_to_cpu(counters->rx_packets);
1040         data[2] = le64_to_cpu(counters->tx_errors);
1041         data[3] = le32_to_cpu(counters->rx_errors);
1042         data[4] = le16_to_cpu(counters->rx_missed);
1043         data[5] = le16_to_cpu(counters->align_errors);
1044         data[6] = le32_to_cpu(counters->tx_one_collision);
1045         data[7] = le32_to_cpu(counters->tx_multi_collision);
1046         data[8] = le64_to_cpu(counters->rx_unicast);
1047         data[9] = le64_to_cpu(counters->rx_broadcast);
1048         data[10] = le32_to_cpu(counters->rx_multicast);
1049         data[11] = le16_to_cpu(counters->tx_aborted);
1050         data[12] = le16_to_cpu(counters->tx_underun);
1051
1052         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1053 }
1054
1055 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1056 {
1057         switch(stringset) {
1058         case ETH_SS_STATS:
1059                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1060                 break;
1061         }
1062 }
1063
1064
1065 static const struct ethtool_ops rtl8169_ethtool_ops = {
1066         .get_drvinfo            = rtl8169_get_drvinfo,
1067         .get_regs_len           = rtl8169_get_regs_len,
1068         .get_link               = ethtool_op_get_link,
1069         .get_settings           = rtl8169_get_settings,
1070         .set_settings           = rtl8169_set_settings,
1071         .get_msglevel           = rtl8169_get_msglevel,
1072         .set_msglevel           = rtl8169_set_msglevel,
1073         .get_rx_csum            = rtl8169_get_rx_csum,
1074         .set_rx_csum            = rtl8169_set_rx_csum,
1075         .get_tx_csum            = ethtool_op_get_tx_csum,
1076         .set_tx_csum            = ethtool_op_set_tx_csum,
1077         .get_sg                 = ethtool_op_get_sg,
1078         .set_sg                 = ethtool_op_set_sg,
1079         .get_tso                = ethtool_op_get_tso,
1080         .set_tso                = ethtool_op_set_tso,
1081         .get_regs               = rtl8169_get_regs,
1082         .get_wol                = rtl8169_get_wol,
1083         .set_wol                = rtl8169_set_wol,
1084         .get_strings            = rtl8169_get_strings,
1085         .get_stats_count        = rtl8169_get_stats_count,
1086         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1087         .get_perm_addr          = ethtool_op_get_perm_addr,
1088 };
1089
1090 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
1091                                        int bitval)
1092 {
1093         int val;
1094
1095         val = mdio_read(ioaddr, reg);
1096         val = (bitval == 1) ?
1097                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1098         mdio_write(ioaddr, reg, val & 0xffff);
1099 }
1100
1101 static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1102 {
1103         /*
1104          * The driver currently handles the 8168Bf and the 8168Be identically
1105          * but they can be identified more specifically through the test below
1106          * if needed:
1107          *
1108          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1109          *
1110          * Same thing for the 8101Eb and the 8101Ec:
1111          *
1112          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1113          */
1114         const struct {
1115                 u32 mask;
1116                 int mac_version;
1117         } mac_info[] = {
1118                 { 0x38800000,   RTL_GIGA_MAC_VER_15 },
1119                 { 0x38000000,   RTL_GIGA_MAC_VER_12 },
1120                 { 0x34000000,   RTL_GIGA_MAC_VER_13 },
1121                 { 0x30800000,   RTL_GIGA_MAC_VER_14 },
1122                 { 0x30000000,   RTL_GIGA_MAC_VER_11 },
1123                 { 0x98000000,   RTL_GIGA_MAC_VER_06 },
1124                 { 0x18000000,   RTL_GIGA_MAC_VER_05 },
1125                 { 0x10000000,   RTL_GIGA_MAC_VER_04 },
1126                 { 0x04000000,   RTL_GIGA_MAC_VER_03 },
1127                 { 0x00800000,   RTL_GIGA_MAC_VER_02 },
1128                 { 0x00000000,   RTL_GIGA_MAC_VER_01 }   /* Catch-all */
1129         }, *p = mac_info;
1130         u32 reg;
1131
1132         reg = RTL_R32(TxConfig) & 0xfc800000;
1133         while ((reg & p->mask) != p->mask)
1134                 p++;
1135         tp->mac_version = p->mac_version;
1136 }
1137
1138 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1139 {
1140         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1141 }
1142
1143 static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1144 {
1145         const struct {
1146                 u16 mask;
1147                 u16 set;
1148                 int phy_version;
1149         } phy_info[] = {
1150                 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1151                 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1152                 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1153                 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1154         }, *p = phy_info;
1155         u16 reg;
1156
1157         reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1158         while ((reg & p->mask) != p->set)
1159                 p++;
1160         tp->phy_version = p->phy_version;
1161 }
1162
1163 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1164 {
1165         struct {
1166                 int version;
1167                 char *msg;
1168                 u32 reg;
1169         } phy_print[] = {
1170                 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1171                 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1172                 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1173                 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1174                 { 0, NULL, 0x0000 }
1175         }, *p;
1176
1177         for (p = phy_print; p->msg; p++) {
1178                 if (tp->phy_version == p->version) {
1179                         dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1180                         return;
1181                 }
1182         }
1183         dprintk("phy_version == Unknown\n");
1184 }
1185
1186 static void rtl8169_hw_phy_config(struct net_device *dev)
1187 {
1188         struct rtl8169_private *tp = netdev_priv(dev);
1189         void __iomem *ioaddr = tp->mmio_addr;
1190         struct {
1191                 u16 regs[5]; /* Beware of bit-sign propagation */
1192         } phy_magic[5] = { {
1193                 { 0x0000,       //w 4 15 12 0
1194                   0x00a1,       //w 3 15 0 00a1
1195                   0x0008,       //w 2 15 0 0008
1196                   0x1020,       //w 1 15 0 1020
1197                   0x1000 } },{  //w 0 15 0 1000
1198                 { 0x7000,       //w 4 15 12 7
1199                   0xff41,       //w 3 15 0 ff41
1200                   0xde60,       //w 2 15 0 de60
1201                   0x0140,       //w 1 15 0 0140
1202                   0x0077 } },{  //w 0 15 0 0077
1203                 { 0xa000,       //w 4 15 12 a
1204                   0xdf01,       //w 3 15 0 df01
1205                   0xdf20,       //w 2 15 0 df20
1206                   0xff95,       //w 1 15 0 ff95
1207                   0xfa00 } },{  //w 0 15 0 fa00
1208                 { 0xb000,       //w 4 15 12 b
1209                   0xff41,       //w 3 15 0 ff41
1210                   0xde20,       //w 2 15 0 de20
1211                   0x0140,       //w 1 15 0 0140
1212                   0x00bb } },{  //w 0 15 0 00bb
1213                 { 0xf000,       //w 4 15 12 f
1214                   0xdf01,       //w 3 15 0 df01
1215                   0xdf20,       //w 2 15 0 df20
1216                   0xff95,       //w 1 15 0 ff95
1217                   0xbf00 }      //w 0 15 0 bf00
1218                 }
1219         }, *p = phy_magic;
1220         int i;
1221
1222         rtl8169_print_mac_version(tp);
1223         rtl8169_print_phy_version(tp);
1224
1225         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1226                 return;
1227         if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1228                 return;
1229
1230         dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1231         dprintk("Do final_reg2.cfg\n");
1232
1233         /* Shazam ! */
1234
1235         if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1236                 mdio_write(ioaddr, 31, 0x0002);
1237                 mdio_write(ioaddr,  1, 0x90d0);
1238                 mdio_write(ioaddr, 31, 0x0000);
1239                 return;
1240         }
1241
1242         /* phy config for RTL8169s mac_version C chip */
1243         mdio_write(ioaddr, 31, 0x0001);                 //w 31 2 0 1
1244         mdio_write(ioaddr, 21, 0x1000);                 //w 21 15 0 1000
1245         mdio_write(ioaddr, 24, 0x65c7);                 //w 24 15 0 65c7
1246         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1247
1248         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1249                 int val, pos = 4;
1250
1251                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1252                 mdio_write(ioaddr, pos, val);
1253                 while (--pos >= 0)
1254                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1255                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1256                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1257         }
1258         mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1259 }
1260
1261 static void rtl8169_phy_timer(unsigned long __opaque)
1262 {
1263         struct net_device *dev = (struct net_device *)__opaque;
1264         struct rtl8169_private *tp = netdev_priv(dev);
1265         struct timer_list *timer = &tp->timer;
1266         void __iomem *ioaddr = tp->mmio_addr;
1267         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1268
1269         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1270         assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1271
1272         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1273                 return;
1274
1275         spin_lock_irq(&tp->lock);
1276
1277         if (tp->phy_reset_pending(ioaddr)) {
1278                 /*
1279                  * A busy loop could burn quite a few cycles on nowadays CPU.
1280                  * Let's delay the execution of the timer for a few ticks.
1281                  */
1282                 timeout = HZ/10;
1283                 goto out_mod_timer;
1284         }
1285
1286         if (tp->link_ok(ioaddr))
1287                 goto out_unlock;
1288
1289         if (netif_msg_link(tp))
1290                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1291
1292         tp->phy_reset_enable(ioaddr);
1293
1294 out_mod_timer:
1295         mod_timer(timer, jiffies + timeout);
1296 out_unlock:
1297         spin_unlock_irq(&tp->lock);
1298 }
1299
1300 static inline void rtl8169_delete_timer(struct net_device *dev)
1301 {
1302         struct rtl8169_private *tp = netdev_priv(dev);
1303         struct timer_list *timer = &tp->timer;
1304
1305         if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1306             (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1307                 return;
1308
1309         del_timer_sync(timer);
1310 }
1311
1312 static inline void rtl8169_request_timer(struct net_device *dev)
1313 {
1314         struct rtl8169_private *tp = netdev_priv(dev);
1315         struct timer_list *timer = &tp->timer;
1316
1317         if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1318             (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1319                 return;
1320
1321         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1322 }
1323
1324 #ifdef CONFIG_NET_POLL_CONTROLLER
1325 /*
1326  * Polling 'interrupt' - used by things like netconsole to send skbs
1327  * without having to re-enable interrupts. It's not called while
1328  * the interrupt routine is executing.
1329  */
1330 static void rtl8169_netpoll(struct net_device *dev)
1331 {
1332         struct rtl8169_private *tp = netdev_priv(dev);
1333         struct pci_dev *pdev = tp->pci_dev;
1334
1335         disable_irq(pdev->irq);
1336         rtl8169_interrupt(pdev->irq, dev);
1337         enable_irq(pdev->irq);
1338 }
1339 #endif
1340
1341 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1342                                   void __iomem *ioaddr)
1343 {
1344         iounmap(ioaddr);
1345         pci_release_regions(pdev);
1346         pci_disable_device(pdev);
1347         free_netdev(dev);
1348 }
1349
1350 static void rtl8169_phy_reset(struct net_device *dev,
1351                               struct rtl8169_private *tp)
1352 {
1353         void __iomem *ioaddr = tp->mmio_addr;
1354         int i;
1355
1356         tp->phy_reset_enable(ioaddr);
1357         for (i = 0; i < 100; i++) {
1358                 if (!tp->phy_reset_pending(ioaddr))
1359                         return;
1360                 msleep(1);
1361         }
1362         if (netif_msg_link(tp))
1363                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1364 }
1365
1366 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1367 {
1368         void __iomem *ioaddr = tp->mmio_addr;
1369
1370         rtl8169_hw_phy_config(dev);
1371
1372         dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1373         RTL_W8(0x82, 0x01);
1374
1375         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1376
1377         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1378                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1379
1380         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1381                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1382                 RTL_W8(0x82, 0x01);
1383                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1384                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1385         }
1386
1387         rtl8169_phy_reset(dev, tp);
1388
1389         /*
1390          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1391          * only 8101. Don't panic.
1392          */
1393         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1394
1395         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1396                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1397 }
1398
1399 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1400 {
1401         struct rtl8169_private *tp = netdev_priv(dev);
1402         struct mii_ioctl_data *data = if_mii(ifr);
1403
1404         if (!netif_running(dev))
1405                 return -ENODEV;
1406
1407         switch (cmd) {
1408         case SIOCGMIIPHY:
1409                 data->phy_id = 32; /* Internal PHY */
1410                 return 0;
1411
1412         case SIOCGMIIREG:
1413                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1414                 return 0;
1415
1416         case SIOCSMIIREG:
1417                 if (!capable(CAP_NET_ADMIN))
1418                         return -EPERM;
1419                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1420                 return 0;
1421         }
1422         return -EOPNOTSUPP;
1423 }
1424
1425 static const struct rtl_cfg_info {
1426         void (*hw_start)(struct net_device *);
1427         unsigned int region;
1428         unsigned int align;
1429         u16 intr_event;
1430         u16 napi_event;
1431 } rtl_cfg_infos [] = {
1432         [RTL_CFG_0] = {
1433                 .hw_start       = rtl_hw_start_8169,
1434                 .region         = 1,
1435                 .align          = 2,
1436                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1437                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1438                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1439         },
1440         [RTL_CFG_1] = {
1441                 .hw_start       = rtl_hw_start_8168,
1442                 .region         = 2,
1443                 .align          = 8,
1444                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1445                                   TxErr | TxOK | RxOK | RxErr,
1446                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow
1447         },
1448         [RTL_CFG_2] = {
1449                 .hw_start       = rtl_hw_start_8101,
1450                 .region         = 2,
1451                 .align          = 8,
1452                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1453                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1454                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1455         }
1456 };
1457
1458 static int __devinit
1459 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1460 {
1461         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1462         const unsigned int region = cfg->region;
1463         struct rtl8169_private *tp;
1464         struct net_device *dev;
1465         void __iomem *ioaddr;
1466         unsigned int pm_cap;
1467         int i, rc;
1468
1469         if (netif_msg_drv(&debug)) {
1470                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1471                        MODULENAME, RTL8169_VERSION);
1472         }
1473
1474         dev = alloc_etherdev(sizeof (*tp));
1475         if (!dev) {
1476                 if (netif_msg_drv(&debug))
1477                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1478                 rc = -ENOMEM;
1479                 goto out;
1480         }
1481
1482         SET_MODULE_OWNER(dev);
1483         SET_NETDEV_DEV(dev, &pdev->dev);
1484         tp = netdev_priv(dev);
1485         tp->dev = dev;
1486         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1487
1488         /* enable device (incl. PCI PM wakeup and hotplug setup) */
1489         rc = pci_enable_device(pdev);
1490         if (rc < 0) {
1491                 if (netif_msg_probe(tp))
1492                         dev_err(&pdev->dev, "enable failure\n");
1493                 goto err_out_free_dev_1;
1494         }
1495
1496         rc = pci_set_mwi(pdev);
1497         if (rc < 0)
1498                 goto err_out_disable_2;
1499
1500         /* save power state before pci_enable_device overwrites it */
1501         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1502         if (pm_cap) {
1503                 u16 pwr_command, acpi_idle_state;
1504
1505                 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1506                 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1507         } else {
1508                 if (netif_msg_probe(tp)) {
1509                         dev_err(&pdev->dev,
1510                                 "PowerManagement capability not found.\n");
1511                 }
1512         }
1513
1514         /* make sure PCI base addr 1 is MMIO */
1515         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1516                 if (netif_msg_probe(tp)) {
1517                         dev_err(&pdev->dev,
1518                                 "region #%d not an MMIO resource, aborting\n",
1519                                 region);
1520                 }
1521                 rc = -ENODEV;
1522                 goto err_out_mwi_3;
1523         }
1524
1525         /* check for weird/broken PCI region reporting */
1526         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1527                 if (netif_msg_probe(tp)) {
1528                         dev_err(&pdev->dev,
1529                                 "Invalid PCI region size(s), aborting\n");
1530                 }
1531                 rc = -ENODEV;
1532                 goto err_out_mwi_3;
1533         }
1534
1535         rc = pci_request_regions(pdev, MODULENAME);
1536         if (rc < 0) {
1537                 if (netif_msg_probe(tp))
1538                         dev_err(&pdev->dev, "could not request regions.\n");
1539                 goto err_out_mwi_3;
1540         }
1541
1542         tp->cp_cmd = PCIMulRW | RxChkSum;
1543
1544         if ((sizeof(dma_addr_t) > 4) &&
1545             !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1546                 tp->cp_cmd |= PCIDAC;
1547                 dev->features |= NETIF_F_HIGHDMA;
1548         } else {
1549                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1550                 if (rc < 0) {
1551                         if (netif_msg_probe(tp)) {
1552                                 dev_err(&pdev->dev,
1553                                         "DMA configuration failed.\n");
1554                         }
1555                         goto err_out_free_res_4;
1556                 }
1557         }
1558
1559         pci_set_master(pdev);
1560
1561         /* ioremap MMIO region */
1562         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1563         if (!ioaddr) {
1564                 if (netif_msg_probe(tp))
1565                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1566                 rc = -EIO;
1567                 goto err_out_free_res_4;
1568         }
1569
1570         /* Unneeded ? Don't mess with Mrs. Murphy. */
1571         rtl8169_irq_mask_and_ack(ioaddr);
1572
1573         /* Soft reset the chip. */
1574         RTL_W8(ChipCmd, CmdReset);
1575
1576         /* Check that the chip has finished the reset. */
1577         for (i = 100; i > 0; i--) {
1578                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1579                         break;
1580                 msleep_interruptible(1);
1581         }
1582
1583         /* Identify chip attached to board */
1584         rtl8169_get_mac_version(tp, ioaddr);
1585         rtl8169_get_phy_version(tp, ioaddr);
1586
1587         rtl8169_print_mac_version(tp);
1588         rtl8169_print_phy_version(tp);
1589
1590         for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1591                 if (tp->mac_version == rtl_chip_info[i].mac_version)
1592                         break;
1593         }
1594         if (i < 0) {
1595                 /* Unknown chip: assume array element #0, original RTL-8169 */
1596                 if (netif_msg_probe(tp)) {
1597                         dev_printk(KERN_DEBUG, &pdev->dev,
1598                                 "unknown chip version, assuming %s\n",
1599                                 rtl_chip_info[0].name);
1600                 }
1601                 i++;
1602         }
1603         tp->chipset = i;
1604
1605         RTL_W8(Cfg9346, Cfg9346_Unlock);
1606         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1607         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1608         RTL_W8(Cfg9346, Cfg9346_Lock);
1609
1610         if (RTL_R8(PHYstatus) & TBI_Enable) {
1611                 tp->set_speed = rtl8169_set_speed_tbi;
1612                 tp->get_settings = rtl8169_gset_tbi;
1613                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1614                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1615                 tp->link_ok = rtl8169_tbi_link_ok;
1616
1617                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1618         } else {
1619                 tp->set_speed = rtl8169_set_speed_xmii;
1620                 tp->get_settings = rtl8169_gset_xmii;
1621                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1622                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1623                 tp->link_ok = rtl8169_xmii_link_ok;
1624
1625                 dev->do_ioctl = rtl8169_ioctl;
1626         }
1627
1628         /* Get MAC address.  FIXME: read EEPROM */
1629         for (i = 0; i < MAC_ADDR_LEN; i++)
1630                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1631         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1632
1633         dev->open = rtl8169_open;
1634         dev->hard_start_xmit = rtl8169_start_xmit;
1635         dev->get_stats = rtl8169_get_stats;
1636         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1637         dev->stop = rtl8169_close;
1638         dev->tx_timeout = rtl8169_tx_timeout;
1639         dev->set_multicast_list = rtl_set_rx_mode;
1640         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1641         dev->irq = pdev->irq;
1642         dev->base_addr = (unsigned long) ioaddr;
1643         dev->change_mtu = rtl8169_change_mtu;
1644
1645 #ifdef CONFIG_R8169_NAPI
1646         dev->poll = rtl8169_poll;
1647         dev->weight = R8169_NAPI_WEIGHT;
1648 #endif
1649
1650 #ifdef CONFIG_R8169_VLAN
1651         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1652         dev->vlan_rx_register = rtl8169_vlan_rx_register;
1653 #endif
1654
1655 #ifdef CONFIG_NET_POLL_CONTROLLER
1656         dev->poll_controller = rtl8169_netpoll;
1657 #endif
1658
1659         tp->intr_mask = 0xffff;
1660         tp->pci_dev = pdev;
1661         tp->mmio_addr = ioaddr;
1662         tp->align = cfg->align;
1663         tp->hw_start = cfg->hw_start;
1664         tp->intr_event = cfg->intr_event;
1665         tp->napi_event = cfg->napi_event;
1666
1667         init_timer(&tp->timer);
1668         tp->timer.data = (unsigned long) dev;
1669         tp->timer.function = rtl8169_phy_timer;
1670
1671         spin_lock_init(&tp->lock);
1672
1673         rc = register_netdev(dev);
1674         if (rc < 0)
1675                 goto err_out_unmap_5;
1676
1677         pci_set_drvdata(pdev, dev);
1678
1679         if (netif_msg_probe(tp)) {
1680                 printk(KERN_INFO "%s: %s at 0x%lx, "
1681                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1682                        "IRQ %d\n",
1683                        dev->name,
1684                        rtl_chip_info[tp->chipset].name,
1685                        dev->base_addr,
1686                        dev->dev_addr[0], dev->dev_addr[1],
1687                        dev->dev_addr[2], dev->dev_addr[3],
1688                        dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1689         }
1690
1691         rtl8169_init_phy(dev, tp);
1692
1693 out:
1694         return rc;
1695
1696 err_out_unmap_5:
1697         iounmap(ioaddr);
1698 err_out_free_res_4:
1699         pci_release_regions(pdev);
1700 err_out_mwi_3:
1701         pci_clear_mwi(pdev);
1702 err_out_disable_2:
1703         pci_disable_device(pdev);
1704 err_out_free_dev_1:
1705         free_netdev(dev);
1706         goto out;
1707 }
1708
1709 static void __devexit
1710 rtl8169_remove_one(struct pci_dev *pdev)
1711 {
1712         struct net_device *dev = pci_get_drvdata(pdev);
1713         struct rtl8169_private *tp = netdev_priv(dev);
1714
1715         assert(dev != NULL);
1716         assert(tp != NULL);
1717
1718         flush_scheduled_work();
1719
1720         unregister_netdev(dev);
1721         rtl8169_release_board(pdev, dev, tp->mmio_addr);
1722         pci_set_drvdata(pdev, NULL);
1723 }
1724
1725 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1726                                   struct net_device *dev)
1727 {
1728         unsigned int mtu = dev->mtu;
1729
1730         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1731 }
1732
1733 static int rtl8169_open(struct net_device *dev)
1734 {
1735         struct rtl8169_private *tp = netdev_priv(dev);
1736         struct pci_dev *pdev = tp->pci_dev;
1737         int retval = -ENOMEM;
1738
1739
1740         rtl8169_set_rxbufsize(tp, dev);
1741
1742         /*
1743          * Rx and Tx desscriptors needs 256 bytes alignment.
1744          * pci_alloc_consistent provides more.
1745          */
1746         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1747                                                &tp->TxPhyAddr);
1748         if (!tp->TxDescArray)
1749                 goto out;
1750
1751         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1752                                                &tp->RxPhyAddr);
1753         if (!tp->RxDescArray)
1754                 goto err_free_tx_0;
1755
1756         retval = rtl8169_init_ring(dev);
1757         if (retval < 0)
1758                 goto err_free_rx_1;
1759
1760         INIT_DELAYED_WORK(&tp->task, NULL);
1761
1762         smp_mb();
1763
1764         retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1765                              dev->name, dev);
1766         if (retval < 0)
1767                 goto err_release_ring_2;
1768
1769         rtl_hw_start(dev);
1770
1771         rtl8169_request_timer(dev);
1772
1773         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1774 out:
1775         return retval;
1776
1777 err_release_ring_2:
1778         rtl8169_rx_clear(tp);
1779 err_free_rx_1:
1780         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1781                             tp->RxPhyAddr);
1782 err_free_tx_0:
1783         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1784                             tp->TxPhyAddr);
1785         goto out;
1786 }
1787
1788 static void rtl8169_hw_reset(void __iomem *ioaddr)
1789 {
1790         /* Disable interrupts */
1791         rtl8169_irq_mask_and_ack(ioaddr);
1792
1793         /* Reset the chipset */
1794         RTL_W8(ChipCmd, CmdReset);
1795
1796         /* PCI commit */
1797         RTL_R8(ChipCmd);
1798 }
1799
1800 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1801 {
1802         void __iomem *ioaddr = tp->mmio_addr;
1803         u32 cfg = rtl8169_rx_config;
1804
1805         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1806         RTL_W32(RxConfig, cfg);
1807
1808         /* Set DMA burst size and Interframe Gap Time */
1809         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1810                 (InterFrameGap << TxInterFrameGapShift));
1811 }
1812
1813 static void rtl_hw_start(struct net_device *dev)
1814 {
1815         struct rtl8169_private *tp = netdev_priv(dev);
1816         void __iomem *ioaddr = tp->mmio_addr;
1817         u32 i;
1818
1819         /* Soft reset the chip. */
1820         RTL_W8(ChipCmd, CmdReset);
1821
1822         /* Check that the chip has finished the reset. */
1823         for (i = 100; i > 0; i--) {
1824                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1825                         break;
1826                 msleep_interruptible(1);
1827         }
1828
1829         tp->hw_start(dev);
1830
1831         netif_start_queue(dev);
1832 }
1833
1834
1835 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1836                                          void __iomem *ioaddr)
1837 {
1838         /*
1839          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1840          * register to be written before TxDescAddrLow to work.
1841          * Switching from MMIO to I/O access fixes the issue as well.
1842          */
1843         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1844         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1845         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1846         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1847 }
1848
1849 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1850 {
1851         u16 cmd;
1852
1853         cmd = RTL_R16(CPlusCmd);
1854         RTL_W16(CPlusCmd, cmd);
1855         return cmd;
1856 }
1857
1858 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1859 {
1860         /* Low hurts. Let's disable the filtering. */
1861         RTL_W16(RxMaxSize, 16383);
1862 }
1863
1864 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1865 {
1866         struct {
1867                 u32 mac_version;
1868                 u32 clk;
1869                 u32 val;
1870         } cfg2_info [] = {
1871                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1872                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1873                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1874                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1875         }, *p = cfg2_info;
1876         unsigned int i;
1877         u32 clk;
1878
1879         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1880         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1881                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1882                         RTL_W32(0x7c, p->val);
1883                         break;
1884                 }
1885         }
1886 }
1887
1888 static void rtl_hw_start_8169(struct net_device *dev)
1889 {
1890         struct rtl8169_private *tp = netdev_priv(dev);
1891         void __iomem *ioaddr = tp->mmio_addr;
1892         struct pci_dev *pdev = tp->pci_dev;
1893
1894         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1895                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1896                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1897         }
1898
1899         RTL_W8(Cfg9346, Cfg9346_Unlock);
1900         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1901             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1902             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1903             (tp->mac_version == RTL_GIGA_MAC_VER_04))
1904                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1905
1906         RTL_W8(EarlyTxThres, EarlyTxThld);
1907
1908         rtl_set_rx_max_size(ioaddr);
1909
1910         rtl_set_rx_tx_config_registers(tp);
1911
1912         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1913
1914         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1915             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1916                 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1917                         "Bit-3 and bit-14 MUST be 1\n");
1918                 tp->cp_cmd |= (1 << 14);
1919         }
1920
1921         RTL_W16(CPlusCmd, tp->cp_cmd);
1922
1923         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1924
1925         /*
1926          * Undocumented corner. Supposedly:
1927          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1928          */
1929         RTL_W16(IntrMitigate, 0x0000);
1930
1931         rtl_set_rx_tx_desc_registers(tp, ioaddr);
1932
1933         RTL_W8(Cfg9346, Cfg9346_Lock);
1934
1935         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1936         RTL_R8(IntrMask);
1937
1938         RTL_W32(RxMissed, 0);
1939
1940         rtl_set_rx_mode(dev);
1941
1942         /* no early-rx interrupts */
1943         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1944
1945         /* Enable all known interrupts by setting the interrupt mask. */
1946         RTL_W16(IntrMask, tp->intr_event);
1947
1948         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1949 }
1950
1951 static void rtl_hw_start_8168(struct net_device *dev)
1952 {
1953         struct rtl8169_private *tp = netdev_priv(dev);
1954         void __iomem *ioaddr = tp->mmio_addr;
1955         struct pci_dev *pdev = tp->pci_dev;
1956         u8 ctl;
1957
1958         RTL_W8(Cfg9346, Cfg9346_Unlock);
1959
1960         RTL_W8(EarlyTxThres, EarlyTxThld);
1961
1962         rtl_set_rx_max_size(ioaddr);
1963
1964         rtl_set_rx_tx_config_registers(tp);
1965
1966         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
1967
1968         RTL_W16(CPlusCmd, tp->cp_cmd);
1969
1970         /* Tx performance tweak. */
1971         pci_read_config_byte(pdev, 0x69, &ctl);
1972         ctl = (ctl & ~0x70) | 0x50;
1973         pci_write_config_byte(pdev, 0x69, ctl);
1974
1975         RTL_W16(IntrMitigate, 0x5151);
1976
1977         /* Work around for RxFIFO overflow. */
1978         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
1979                 tp->intr_event |= RxFIFOOver | PCSTimeout;
1980                 tp->intr_event &= ~RxOverflow;
1981         }
1982
1983         rtl_set_rx_tx_desc_registers(tp, ioaddr);
1984
1985         RTL_W8(Cfg9346, Cfg9346_Lock);
1986
1987         RTL_R8(IntrMask);
1988
1989         RTL_W32(RxMissed, 0);
1990
1991         rtl_set_rx_mode(dev);
1992
1993         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1994
1995         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1996
1997         RTL_W16(IntrMask, tp->intr_event);
1998 }
1999
2000 static void rtl_hw_start_8101(struct net_device *dev)
2001 {
2002         struct rtl8169_private *tp = netdev_priv(dev);
2003         void __iomem *ioaddr = tp->mmio_addr;
2004         struct pci_dev *pdev = tp->pci_dev;
2005
2006         if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
2007                 pci_write_config_word(pdev, 0x68, 0x00);
2008                 pci_write_config_word(pdev, 0x69, 0x08);
2009         }
2010
2011         RTL_W8(Cfg9346, Cfg9346_Unlock);
2012
2013         RTL_W8(EarlyTxThres, EarlyTxThld);
2014
2015         rtl_set_rx_max_size(ioaddr);
2016
2017         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2018
2019         RTL_W16(CPlusCmd, tp->cp_cmd);
2020
2021         RTL_W16(IntrMitigate, 0x0000);
2022
2023         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2024
2025         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2026         rtl_set_rx_tx_config_registers(tp);
2027
2028         RTL_W8(Cfg9346, Cfg9346_Lock);
2029
2030         RTL_R8(IntrMask);
2031
2032         RTL_W32(RxMissed, 0);
2033
2034         rtl_set_rx_mode(dev);
2035
2036         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2037
2038         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2039
2040         RTL_W16(IntrMask, tp->intr_event);
2041 }
2042
2043 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2044 {
2045         struct rtl8169_private *tp = netdev_priv(dev);
2046         int ret = 0;
2047
2048         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2049                 return -EINVAL;
2050
2051         dev->mtu = new_mtu;
2052
2053         if (!netif_running(dev))
2054                 goto out;
2055
2056         rtl8169_down(dev);
2057
2058         rtl8169_set_rxbufsize(tp, dev);
2059
2060         ret = rtl8169_init_ring(dev);
2061         if (ret < 0)
2062                 goto out;
2063
2064         netif_poll_enable(dev);
2065
2066         rtl_hw_start(dev);
2067
2068         rtl8169_request_timer(dev);
2069
2070 out:
2071         return ret;
2072 }
2073
2074 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2075 {
2076         desc->addr = 0x0badbadbadbadbadull;
2077         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2078 }
2079
2080 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2081                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2082 {
2083         struct pci_dev *pdev = tp->pci_dev;
2084
2085         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2086                          PCI_DMA_FROMDEVICE);
2087         dev_kfree_skb(*sk_buff);
2088         *sk_buff = NULL;
2089         rtl8169_make_unusable_by_asic(desc);
2090 }
2091
2092 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2093 {
2094         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2095
2096         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2097 }
2098
2099 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2100                                        u32 rx_buf_sz)
2101 {
2102         desc->addr = cpu_to_le64(mapping);
2103         wmb();
2104         rtl8169_mark_to_asic(desc, rx_buf_sz);
2105 }
2106
2107 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2108                                             struct net_device *dev,
2109                                             struct RxDesc *desc, int rx_buf_sz,
2110                                             unsigned int align)
2111 {
2112         struct sk_buff *skb;
2113         dma_addr_t mapping;
2114
2115         skb = netdev_alloc_skb(dev, rx_buf_sz + align);
2116         if (!skb)
2117                 goto err_out;
2118
2119         skb_reserve(skb, (align - 1) & (unsigned long)skb->data);
2120
2121         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2122                                  PCI_DMA_FROMDEVICE);
2123
2124         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2125 out:
2126         return skb;
2127
2128 err_out:
2129         rtl8169_make_unusable_by_asic(desc);
2130         goto out;
2131 }
2132
2133 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2134 {
2135         int i;
2136
2137         for (i = 0; i < NUM_RX_DESC; i++) {
2138                 if (tp->Rx_skbuff[i]) {
2139                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2140                                             tp->RxDescArray + i);
2141                 }
2142         }
2143 }
2144
2145 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2146                            u32 start, u32 end)
2147 {
2148         u32 cur;
2149
2150         for (cur = start; end - cur != 0; cur++) {
2151                 struct sk_buff *skb;
2152                 unsigned int i = cur % NUM_RX_DESC;
2153
2154                 WARN_ON((s32)(end - cur) < 0);
2155
2156                 if (tp->Rx_skbuff[i])
2157                         continue;
2158
2159                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2160                                            tp->RxDescArray + i,
2161                                            tp->rx_buf_sz, tp->align);
2162                 if (!skb)
2163                         break;
2164
2165                 tp->Rx_skbuff[i] = skb;
2166         }
2167         return cur - start;
2168 }
2169
2170 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2171 {
2172         desc->opts1 |= cpu_to_le32(RingEnd);
2173 }
2174
2175 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2176 {
2177         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2178 }
2179
2180 static int rtl8169_init_ring(struct net_device *dev)
2181 {
2182         struct rtl8169_private *tp = netdev_priv(dev);
2183
2184         rtl8169_init_ring_indexes(tp);
2185
2186         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2187         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2188
2189         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2190                 goto err_out;
2191
2192         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2193
2194         return 0;
2195
2196 err_out:
2197         rtl8169_rx_clear(tp);
2198         return -ENOMEM;
2199 }
2200
2201 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2202                                  struct TxDesc *desc)
2203 {
2204         unsigned int len = tx_skb->len;
2205
2206         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2207         desc->opts1 = 0x00;
2208         desc->opts2 = 0x00;
2209         desc->addr = 0x00;
2210         tx_skb->len = 0;
2211 }
2212
2213 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2214 {
2215         unsigned int i;
2216
2217         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2218                 unsigned int entry = i % NUM_TX_DESC;
2219                 struct ring_info *tx_skb = tp->tx_skb + entry;
2220                 unsigned int len = tx_skb->len;
2221
2222                 if (len) {
2223                         struct sk_buff *skb = tx_skb->skb;
2224
2225                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2226                                              tp->TxDescArray + entry);
2227                         if (skb) {
2228                                 dev_kfree_skb(skb);
2229                                 tx_skb->skb = NULL;
2230                         }
2231                         tp->stats.tx_dropped++;
2232                 }
2233         }
2234         tp->cur_tx = tp->dirty_tx = 0;
2235 }
2236
2237 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2238 {
2239         struct rtl8169_private *tp = netdev_priv(dev);
2240
2241         PREPARE_DELAYED_WORK(&tp->task, task);
2242         schedule_delayed_work(&tp->task, 4);
2243 }
2244
2245 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2246 {
2247         struct rtl8169_private *tp = netdev_priv(dev);
2248         void __iomem *ioaddr = tp->mmio_addr;
2249
2250         synchronize_irq(dev->irq);
2251
2252         /* Wait for any pending NAPI task to complete */
2253         netif_poll_disable(dev);
2254
2255         rtl8169_irq_mask_and_ack(ioaddr);
2256
2257         netif_poll_enable(dev);
2258 }
2259
2260 static void rtl8169_reinit_task(struct work_struct *work)
2261 {
2262         struct rtl8169_private *tp =
2263                 container_of(work, struct rtl8169_private, task.work);
2264         struct net_device *dev = tp->dev;
2265         int ret;
2266
2267         rtnl_lock();
2268
2269         if (!netif_running(dev))
2270                 goto out_unlock;
2271
2272         rtl8169_wait_for_quiescence(dev);
2273         rtl8169_close(dev);
2274
2275         ret = rtl8169_open(dev);
2276         if (unlikely(ret < 0)) {
2277                 if (net_ratelimit()) {
2278                         struct rtl8169_private *tp = netdev_priv(dev);
2279
2280                         if (netif_msg_drv(tp)) {
2281                                 printk(PFX KERN_ERR
2282                                        "%s: reinit failure (status = %d)."
2283                                        " Rescheduling.\n", dev->name, ret);
2284                         }
2285                 }
2286                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2287         }
2288
2289 out_unlock:
2290         rtnl_unlock();
2291 }
2292
2293 static void rtl8169_reset_task(struct work_struct *work)
2294 {
2295         struct rtl8169_private *tp =
2296                 container_of(work, struct rtl8169_private, task.work);
2297         struct net_device *dev = tp->dev;
2298
2299         rtnl_lock();
2300
2301         if (!netif_running(dev))
2302                 goto out_unlock;
2303
2304         rtl8169_wait_for_quiescence(dev);
2305
2306         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2307         rtl8169_tx_clear(tp);
2308
2309         if (tp->dirty_rx == tp->cur_rx) {
2310                 rtl8169_init_ring_indexes(tp);
2311                 rtl_hw_start(dev);
2312                 netif_wake_queue(dev);
2313         } else {
2314                 if (net_ratelimit()) {
2315                         struct rtl8169_private *tp = netdev_priv(dev);
2316
2317                         if (netif_msg_intr(tp)) {
2318                                 printk(PFX KERN_EMERG
2319                                        "%s: Rx buffers shortage\n", dev->name);
2320                         }
2321                 }
2322                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2323         }
2324
2325 out_unlock:
2326         rtnl_unlock();
2327 }
2328
2329 static void rtl8169_tx_timeout(struct net_device *dev)
2330 {
2331         struct rtl8169_private *tp = netdev_priv(dev);
2332
2333         rtl8169_hw_reset(tp->mmio_addr);
2334
2335         /* Let's wait a bit while any (async) irq lands on */
2336         rtl8169_schedule_work(dev, rtl8169_reset_task);
2337 }
2338
2339 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2340                               u32 opts1)
2341 {
2342         struct skb_shared_info *info = skb_shinfo(skb);
2343         unsigned int cur_frag, entry;
2344         struct TxDesc *txd;
2345
2346         entry = tp->cur_tx;
2347         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2348                 skb_frag_t *frag = info->frags + cur_frag;
2349                 dma_addr_t mapping;
2350                 u32 status, len;
2351                 void *addr;
2352
2353                 entry = (entry + 1) % NUM_TX_DESC;
2354
2355                 txd = tp->TxDescArray + entry;
2356                 len = frag->size;
2357                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2358                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2359
2360                 /* anti gcc 2.95.3 bugware (sic) */
2361                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2362
2363                 txd->opts1 = cpu_to_le32(status);
2364                 txd->addr = cpu_to_le64(mapping);
2365
2366                 tp->tx_skb[entry].len = len;
2367         }
2368
2369         if (cur_frag) {
2370                 tp->tx_skb[entry].skb = skb;
2371                 txd->opts1 |= cpu_to_le32(LastFrag);
2372         }
2373
2374         return cur_frag;
2375 }
2376
2377 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2378 {
2379         if (dev->features & NETIF_F_TSO) {
2380                 u32 mss = skb_shinfo(skb)->gso_size;
2381
2382                 if (mss)
2383                         return LargeSend | ((mss & MSSMask) << MSSShift);
2384         }
2385         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2386                 const struct iphdr *ip = ip_hdr(skb);
2387
2388                 if (ip->protocol == IPPROTO_TCP)
2389                         return IPCS | TCPCS;
2390                 else if (ip->protocol == IPPROTO_UDP)
2391                         return IPCS | UDPCS;
2392                 WARN_ON(1);     /* we need a WARN() */
2393         }
2394         return 0;
2395 }
2396
2397 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2398 {
2399         struct rtl8169_private *tp = netdev_priv(dev);
2400         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2401         struct TxDesc *txd = tp->TxDescArray + entry;
2402         void __iomem *ioaddr = tp->mmio_addr;
2403         dma_addr_t mapping;
2404         u32 status, len;
2405         u32 opts1;
2406         int ret = NETDEV_TX_OK;
2407
2408         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2409                 if (netif_msg_drv(tp)) {
2410                         printk(KERN_ERR
2411                                "%s: BUG! Tx Ring full when queue awake!\n",
2412                                dev->name);
2413                 }
2414                 goto err_stop;
2415         }
2416
2417         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2418                 goto err_stop;
2419
2420         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2421
2422         frags = rtl8169_xmit_frags(tp, skb, opts1);
2423         if (frags) {
2424                 len = skb_headlen(skb);
2425                 opts1 |= FirstFrag;
2426         } else {
2427                 len = skb->len;
2428
2429                 if (unlikely(len < ETH_ZLEN)) {
2430                         if (skb_padto(skb, ETH_ZLEN))
2431                                 goto err_update_stats;
2432                         len = ETH_ZLEN;
2433                 }
2434
2435                 opts1 |= FirstFrag | LastFrag;
2436                 tp->tx_skb[entry].skb = skb;
2437         }
2438
2439         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2440
2441         tp->tx_skb[entry].len = len;
2442         txd->addr = cpu_to_le64(mapping);
2443         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2444
2445         wmb();
2446
2447         /* anti gcc 2.95.3 bugware (sic) */
2448         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2449         txd->opts1 = cpu_to_le32(status);
2450
2451         dev->trans_start = jiffies;
2452
2453         tp->cur_tx += frags + 1;
2454
2455         smp_wmb();
2456
2457         RTL_W8(TxPoll, 0x40);   /* set polling bit */
2458
2459         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2460                 netif_stop_queue(dev);
2461                 smp_rmb();
2462                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2463                         netif_wake_queue(dev);
2464         }
2465
2466 out:
2467         return ret;
2468
2469 err_stop:
2470         netif_stop_queue(dev);
2471         ret = NETDEV_TX_BUSY;
2472 err_update_stats:
2473         tp->stats.tx_dropped++;
2474         goto out;
2475 }
2476
2477 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2478 {
2479         struct rtl8169_private *tp = netdev_priv(dev);
2480         struct pci_dev *pdev = tp->pci_dev;
2481         void __iomem *ioaddr = tp->mmio_addr;
2482         u16 pci_status, pci_cmd;
2483
2484         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2485         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2486
2487         if (netif_msg_intr(tp)) {
2488                 printk(KERN_ERR
2489                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2490                        dev->name, pci_cmd, pci_status);
2491         }
2492
2493         /*
2494          * The recovery sequence below admits a very elaborated explanation:
2495          * - it seems to work;
2496          * - I did not see what else could be done;
2497          * - it makes iop3xx happy.
2498          *
2499          * Feel free to adjust to your needs.
2500          */
2501         if (pdev->broken_parity_status)
2502                 pci_cmd &= ~PCI_COMMAND_PARITY;
2503         else
2504                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2505
2506         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2507
2508         pci_write_config_word(pdev, PCI_STATUS,
2509                 pci_status & (PCI_STATUS_DETECTED_PARITY |
2510                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2511                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2512
2513         /* The infamous DAC f*ckup only happens at boot time */
2514         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2515                 if (netif_msg_intr(tp))
2516                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2517                 tp->cp_cmd &= ~PCIDAC;
2518                 RTL_W16(CPlusCmd, tp->cp_cmd);
2519                 dev->features &= ~NETIF_F_HIGHDMA;
2520         }
2521
2522         rtl8169_hw_reset(ioaddr);
2523
2524         rtl8169_schedule_work(dev, rtl8169_reinit_task);
2525 }
2526
2527 static void
2528 rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2529                      void __iomem *ioaddr)
2530 {
2531         unsigned int dirty_tx, tx_left;
2532
2533         assert(dev != NULL);
2534         assert(tp != NULL);
2535         assert(ioaddr != NULL);
2536
2537         dirty_tx = tp->dirty_tx;
2538         smp_rmb();
2539         tx_left = tp->cur_tx - dirty_tx;
2540
2541         while (tx_left > 0) {
2542                 unsigned int entry = dirty_tx % NUM_TX_DESC;
2543                 struct ring_info *tx_skb = tp->tx_skb + entry;
2544                 u32 len = tx_skb->len;
2545                 u32 status;
2546
2547                 rmb();
2548                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2549                 if (status & DescOwn)
2550                         break;
2551
2552                 tp->stats.tx_bytes += len;
2553                 tp->stats.tx_packets++;
2554
2555                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2556
2557                 if (status & LastFrag) {
2558                         dev_kfree_skb_irq(tx_skb->skb);
2559                         tx_skb->skb = NULL;
2560                 }
2561                 dirty_tx++;
2562                 tx_left--;
2563         }
2564
2565         if (tp->dirty_tx != dirty_tx) {
2566                 tp->dirty_tx = dirty_tx;
2567                 smp_wmb();
2568                 if (netif_queue_stopped(dev) &&
2569                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2570                         netif_wake_queue(dev);
2571                 }
2572         }
2573 }
2574
2575 static inline int rtl8169_fragmented_frame(u32 status)
2576 {
2577         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2578 }
2579
2580 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2581 {
2582         u32 opts1 = le32_to_cpu(desc->opts1);
2583         u32 status = opts1 & RxProtoMask;
2584
2585         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2586             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2587             ((status == RxProtoIP) && !(opts1 & IPFail)))
2588                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2589         else
2590                 skb->ip_summed = CHECKSUM_NONE;
2591 }
2592
2593 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
2594                                        struct pci_dev *pdev, dma_addr_t addr)
2595 {
2596         struct sk_buff *skb;
2597         bool done = false;
2598
2599         if (pkt_size >= rx_copybreak)
2600                 goto out;
2601
2602         skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
2603         if (!skb)
2604                 goto out;
2605
2606         pci_dma_sync_single_for_cpu(pdev, addr, pkt_size, PCI_DMA_FROMDEVICE);
2607         skb_reserve(skb, NET_IP_ALIGN);
2608         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2609         *sk_buff = skb;
2610         done = true;
2611 out:
2612         return done;
2613 }
2614
2615 static int
2616 rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2617                      void __iomem *ioaddr)
2618 {
2619         unsigned int cur_rx, rx_left;
2620         unsigned int delta, count;
2621
2622         assert(dev != NULL);
2623         assert(tp != NULL);
2624         assert(ioaddr != NULL);
2625
2626         cur_rx = tp->cur_rx;
2627         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2628         rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2629
2630         for (; rx_left > 0; rx_left--, cur_rx++) {
2631                 unsigned int entry = cur_rx % NUM_RX_DESC;
2632                 struct RxDesc *desc = tp->RxDescArray + entry;
2633                 u32 status;
2634
2635                 rmb();
2636                 status = le32_to_cpu(desc->opts1);
2637
2638                 if (status & DescOwn)
2639                         break;
2640                 if (unlikely(status & RxRES)) {
2641                         if (netif_msg_rx_err(tp)) {
2642                                 printk(KERN_INFO
2643                                        "%s: Rx ERROR. status = %08x\n",
2644                                        dev->name, status);
2645                         }
2646                         tp->stats.rx_errors++;
2647                         if (status & (RxRWT | RxRUNT))
2648                                 tp->stats.rx_length_errors++;
2649                         if (status & RxCRC)
2650                                 tp->stats.rx_crc_errors++;
2651                         if (status & RxFOVF) {
2652                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2653                                 tp->stats.rx_fifo_errors++;
2654                         }
2655                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2656                 } else {
2657                         struct sk_buff *skb = tp->Rx_skbuff[entry];
2658                         dma_addr_t addr = le64_to_cpu(desc->addr);
2659                         int pkt_size = (status & 0x00001FFF) - 4;
2660                         struct pci_dev *pdev = tp->pci_dev;
2661
2662                         /*
2663                          * The driver does not support incoming fragmented
2664                          * frames. They are seen as a symptom of over-mtu
2665                          * sized frames.
2666                          */
2667                         if (unlikely(rtl8169_fragmented_frame(status))) {
2668                                 tp->stats.rx_dropped++;
2669                                 tp->stats.rx_length_errors++;
2670                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2671                                 continue;
2672                         }
2673
2674                         rtl8169_rx_csum(skb, desc);
2675
2676                         if (rtl8169_try_rx_copy(&skb, pkt_size, pdev, addr)) {
2677                                 pci_dma_sync_single_for_device(pdev, addr,
2678                                         pkt_size, PCI_DMA_FROMDEVICE);
2679                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2680                         } else {
2681                                 pci_unmap_single(pdev, addr, pkt_size,
2682                                                  PCI_DMA_FROMDEVICE);
2683                                 tp->Rx_skbuff[entry] = NULL;
2684                         }
2685
2686                         skb_put(skb, pkt_size);
2687                         skb->protocol = eth_type_trans(skb, dev);
2688
2689                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2690                                 rtl8169_rx_skb(skb);
2691
2692                         dev->last_rx = jiffies;
2693                         tp->stats.rx_bytes += pkt_size;
2694                         tp->stats.rx_packets++;
2695                 }
2696
2697                 /* Work around for AMD plateform. */
2698                 if ((desc->opts2 & 0xfffe000) &&
2699                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2700                         desc->opts2 = 0;
2701                         cur_rx++;
2702                 }
2703         }
2704
2705         count = cur_rx - tp->cur_rx;
2706         tp->cur_rx = cur_rx;
2707
2708         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2709         if (!delta && count && netif_msg_intr(tp))
2710                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2711         tp->dirty_rx += delta;
2712
2713         /*
2714          * FIXME: until there is periodic timer to try and refill the ring,
2715          * a temporary shortage may definitely kill the Rx process.
2716          * - disable the asic to try and avoid an overflow and kick it again
2717          *   after refill ?
2718          * - how do others driver handle this condition (Uh oh...).
2719          */
2720         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2721                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2722
2723         return count;
2724 }
2725
2726 /* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2727 static irqreturn_t
2728 rtl8169_interrupt(int irq, void *dev_instance)
2729 {
2730         struct net_device *dev = (struct net_device *) dev_instance;
2731         struct rtl8169_private *tp = netdev_priv(dev);
2732         int boguscnt = max_interrupt_work;
2733         void __iomem *ioaddr = tp->mmio_addr;
2734         int status;
2735         int handled = 0;
2736
2737         do {
2738                 status = RTL_R16(IntrStatus);
2739
2740                 /* hotplug/major error/no more work/shared irq */
2741                 if ((status == 0xFFFF) || !status)
2742                         break;
2743
2744                 handled = 1;
2745
2746                 if (unlikely(!netif_running(dev))) {
2747                         rtl8169_asic_down(ioaddr);
2748                         goto out;
2749                 }
2750
2751                 status &= tp->intr_mask;
2752                 RTL_W16(IntrStatus,
2753                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
2754
2755                 if (!(status & tp->intr_event))
2756                         break;
2757
2758                 /* Work around for rx fifo overflow */
2759                 if (unlikely(status & RxFIFOOver) &&
2760                     (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2761                         netif_stop_queue(dev);
2762                         rtl8169_tx_timeout(dev);
2763                         break;
2764                 }
2765
2766                 if (unlikely(status & SYSErr)) {
2767                         rtl8169_pcierr_interrupt(dev);
2768                         break;
2769                 }
2770
2771                 if (status & LinkChg)
2772                         rtl8169_check_link_status(dev, tp, ioaddr);
2773
2774 #ifdef CONFIG_R8169_NAPI
2775                 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2776                 tp->intr_mask = ~tp->napi_event;
2777
2778                 if (likely(netif_rx_schedule_prep(dev)))
2779                         __netif_rx_schedule(dev);
2780                 else if (netif_msg_intr(tp)) {
2781                         printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2782                                dev->name, status);
2783                 }
2784                 break;
2785 #else
2786                 /* Rx interrupt */
2787                 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2788                         rtl8169_rx_interrupt(dev, tp, ioaddr);
2789                 }
2790                 /* Tx interrupt */
2791                 if (status & (TxOK | TxErr))
2792                         rtl8169_tx_interrupt(dev, tp, ioaddr);
2793 #endif
2794
2795                 boguscnt--;
2796         } while (boguscnt > 0);
2797
2798         if (boguscnt <= 0) {
2799                 if (netif_msg_intr(tp) && net_ratelimit() ) {
2800                         printk(KERN_WARNING
2801                                "%s: Too much work at interrupt!\n", dev->name);
2802                 }
2803                 /* Clear all interrupt sources. */
2804                 RTL_W16(IntrStatus, 0xffff);
2805         }
2806 out:
2807         return IRQ_RETVAL(handled);
2808 }
2809
2810 #ifdef CONFIG_R8169_NAPI
2811 static int rtl8169_poll(struct net_device *dev, int *budget)
2812 {
2813         unsigned int work_done, work_to_do = min(*budget, dev->quota);
2814         struct rtl8169_private *tp = netdev_priv(dev);
2815         void __iomem *ioaddr = tp->mmio_addr;
2816
2817         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2818         rtl8169_tx_interrupt(dev, tp, ioaddr);
2819
2820         *budget -= work_done;
2821         dev->quota -= work_done;
2822
2823         if (work_done < work_to_do) {
2824                 netif_rx_complete(dev);
2825                 tp->intr_mask = 0xffff;
2826                 /*
2827                  * 20040426: the barrier is not strictly required but the
2828                  * behavior of the irq handler could be less predictable
2829                  * without it. Btw, the lack of flush for the posted pci
2830                  * write is safe - FR
2831                  */
2832                 smp_wmb();
2833                 RTL_W16(IntrMask, tp->intr_event);
2834         }
2835
2836         return (work_done >= work_to_do);
2837 }
2838 #endif
2839
2840 static void rtl8169_down(struct net_device *dev)
2841 {
2842         struct rtl8169_private *tp = netdev_priv(dev);
2843         void __iomem *ioaddr = tp->mmio_addr;
2844         unsigned int poll_locked = 0;
2845         unsigned int intrmask;
2846
2847         rtl8169_delete_timer(dev);
2848
2849         netif_stop_queue(dev);
2850
2851 core_down:
2852         spin_lock_irq(&tp->lock);
2853
2854         rtl8169_asic_down(ioaddr);
2855
2856         /* Update the error counts. */
2857         tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2858         RTL_W32(RxMissed, 0);
2859
2860         spin_unlock_irq(&tp->lock);
2861
2862         synchronize_irq(dev->irq);
2863
2864         if (!poll_locked) {
2865                 netif_poll_disable(dev);
2866                 poll_locked++;
2867         }
2868
2869         /* Give a racing hard_start_xmit a few cycles to complete. */
2870         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
2871
2872         /*
2873          * And now for the 50k$ question: are IRQ disabled or not ?
2874          *
2875          * Two paths lead here:
2876          * 1) dev->close
2877          *    -> netif_running() is available to sync the current code and the
2878          *       IRQ handler. See rtl8169_interrupt for details.
2879          * 2) dev->change_mtu
2880          *    -> rtl8169_poll can not be issued again and re-enable the
2881          *       interruptions. Let's simply issue the IRQ down sequence again.
2882          *
2883          * No loop if hotpluged or major error (0xffff).
2884          */
2885         intrmask = RTL_R16(IntrMask);
2886         if (intrmask && (intrmask != 0xffff))
2887                 goto core_down;
2888
2889         rtl8169_tx_clear(tp);
2890
2891         rtl8169_rx_clear(tp);
2892 }
2893
2894 static int rtl8169_close(struct net_device *dev)
2895 {
2896         struct rtl8169_private *tp = netdev_priv(dev);
2897         struct pci_dev *pdev = tp->pci_dev;
2898
2899         rtl8169_down(dev);
2900
2901         free_irq(dev->irq, dev);
2902
2903         netif_poll_enable(dev);
2904
2905         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2906                             tp->RxPhyAddr);
2907         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2908                             tp->TxPhyAddr);
2909         tp->TxDescArray = NULL;
2910         tp->RxDescArray = NULL;
2911
2912         return 0;
2913 }
2914
2915 static void rtl_set_rx_mode(struct net_device *dev)
2916 {
2917         struct rtl8169_private *tp = netdev_priv(dev);
2918         void __iomem *ioaddr = tp->mmio_addr;
2919         unsigned long flags;
2920         u32 mc_filter[2];       /* Multicast hash filter */
2921         int i, rx_mode;
2922         u32 tmp = 0;
2923
2924         if (dev->flags & IFF_PROMISC) {
2925                 /* Unconditionally log net taps. */
2926                 if (netif_msg_link(tp)) {
2927                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2928                                dev->name);
2929                 }
2930                 rx_mode =
2931                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2932                     AcceptAllPhys;
2933                 mc_filter[1] = mc_filter[0] = 0xffffffff;
2934         } else if ((dev->mc_count > multicast_filter_limit)
2935                    || (dev->flags & IFF_ALLMULTI)) {
2936                 /* Too many to filter perfectly -- accept all multicasts. */
2937                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2938                 mc_filter[1] = mc_filter[0] = 0xffffffff;
2939         } else {
2940                 struct dev_mc_list *mclist;
2941                 rx_mode = AcceptBroadcast | AcceptMyPhys;
2942                 mc_filter[1] = mc_filter[0] = 0;
2943                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2944                      i++, mclist = mclist->next) {
2945                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2946                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2947                         rx_mode |= AcceptMulticast;
2948                 }
2949         }
2950
2951         spin_lock_irqsave(&tp->lock, flags);
2952
2953         tmp = rtl8169_rx_config | rx_mode |
2954               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2955
2956         if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2957             (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2958             (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2959             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2960             (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2961                 mc_filter[0] = 0xffffffff;
2962                 mc_filter[1] = 0xffffffff;
2963         }
2964
2965         RTL_W32(RxConfig, tmp);
2966         RTL_W32(MAR0 + 0, mc_filter[0]);
2967         RTL_W32(MAR0 + 4, mc_filter[1]);
2968
2969         spin_unlock_irqrestore(&tp->lock, flags);
2970 }
2971
2972 /**
2973  *  rtl8169_get_stats - Get rtl8169 read/write statistics
2974  *  @dev: The Ethernet Device to get statistics for
2975  *
2976  *  Get TX/RX statistics for rtl8169
2977  */
2978 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2979 {
2980         struct rtl8169_private *tp = netdev_priv(dev);
2981         void __iomem *ioaddr = tp->mmio_addr;
2982         unsigned long flags;
2983
2984         if (netif_running(dev)) {
2985                 spin_lock_irqsave(&tp->lock, flags);
2986                 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2987                 RTL_W32(RxMissed, 0);
2988                 spin_unlock_irqrestore(&tp->lock, flags);
2989         }
2990
2991         return &tp->stats;
2992 }
2993
2994 #ifdef CONFIG_PM
2995
2996 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2997 {
2998         struct net_device *dev = pci_get_drvdata(pdev);
2999         struct rtl8169_private *tp = netdev_priv(dev);
3000         void __iomem *ioaddr = tp->mmio_addr;
3001
3002         if (!netif_running(dev))
3003                 goto out_pci_suspend;
3004
3005         netif_device_detach(dev);
3006         netif_stop_queue(dev);
3007
3008         spin_lock_irq(&tp->lock);
3009
3010         rtl8169_asic_down(ioaddr);
3011
3012         tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3013         RTL_W32(RxMissed, 0);
3014
3015         spin_unlock_irq(&tp->lock);
3016
3017 out_pci_suspend:
3018         pci_save_state(pdev);
3019         pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
3020         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3021
3022         return 0;
3023 }
3024
3025 static int rtl8169_resume(struct pci_dev *pdev)
3026 {
3027         struct net_device *dev = pci_get_drvdata(pdev);
3028
3029         pci_set_power_state(pdev, PCI_D0);
3030         pci_restore_state(pdev);
3031         pci_enable_wake(pdev, PCI_D0, 0);
3032
3033         if (!netif_running(dev))
3034                 goto out;
3035
3036         netif_device_attach(dev);
3037
3038         rtl8169_schedule_work(dev, rtl8169_reset_task);
3039 out:
3040         return 0;
3041 }
3042
3043 #endif /* CONFIG_PM */
3044
3045 static struct pci_driver rtl8169_pci_driver = {
3046         .name           = MODULENAME,
3047         .id_table       = rtl8169_pci_tbl,
3048         .probe          = rtl8169_init_one,
3049         .remove         = __devexit_p(rtl8169_remove_one),
3050 #ifdef CONFIG_PM
3051         .suspend        = rtl8169_suspend,
3052         .resume         = rtl8169_resume,
3053 #endif
3054 };
3055
3056 static int __init
3057 rtl8169_init_module(void)
3058 {
3059         return pci_register_driver(&rtl8169_pci_driver);
3060 }
3061
3062 static void __exit
3063 rtl8169_cleanup_module(void)
3064 {
3065         pci_unregister_driver(&rtl8169_pci_driver);
3066 }
3067
3068 module_init(rtl8169_init_module);
3069 module_exit(rtl8169_cleanup_module);