drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30
  31 #ifdef CONFIG_R8169_NAPI
  32 #define NAPI_SUFFIX     "-NAPI"
  33 #else
  34 #define NAPI_SUFFIX     ""
  35 #endif
  36
  37 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
  38 #define MODULENAME "r8169"
  39 #define PFX MODULENAME ": "
  40
  41 #ifdef RTL8169_DEBUG
  42 #define assert(expr) \
  43         if (!(expr)) {                                  \
  44                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  45                 #expr,__FILE__,__FUNCTION__,__LINE__);          \
  46         }
  47 #define dprintk(fmt, args...)   do { printk(PFX fmt, ## args); } while (0)
  48 #else
  49 #define assert(expr) do {} while (0)
  50 #define dprintk(fmt, args...)   do {} while (0)
  51 #endif /* RTL8169_DEBUG */
  52
  53 #define R8169_MSG_DEFAULT \
  54         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  55
  56 #define TX_BUFFS_AVAIL(tp) \
  57         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  58
  59 #ifdef CONFIG_R8169_NAPI
  60 #define rtl8169_rx_skb                  netif_receive_skb
  61 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_receive_skb
  62 #define rtl8169_rx_quota(count, quota)  min(count, quota)
  63 #else
  64 #define rtl8169_rx_skb                  netif_rx
  65 #define rtl8169_rx_hwaccel_skb          vlan_hwaccel_rx
  66 #define rtl8169_rx_quota(count, quota)  count
  67 #endif
  68
  69 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  70 static const int max_interrupt_work = 20;
  71
  72 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  73    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  74 static const int multicast_filter_limit = 32;
  75
  76 /* MAC address length */
  77 #define MAC_ADDR_LEN    6
  78
  79 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  80 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  81 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  82 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  83 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
  84 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  85 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  86
  87 #define R8169_REGS_SIZE         256
  88 #define R8169_NAPI_WEIGHT       64
  89 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  90 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  91 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  92 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  93 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  94
  95 #define RTL8169_TX_TIMEOUT      (6*HZ)
  96 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  97
  98 /* write/read MMIO register */
  99 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
 100 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
 101 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
 102 #define RTL_R8(reg)             readb (ioaddr + (reg))
 103 #define RTL_R16(reg)            readw (ioaddr + (reg))
 104 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
 105
 106 enum mac_version {
 107         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
 108         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
 109         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
 110         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
 111         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
 112         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
 113         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 114         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
 115         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
 116         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
 117         RTL_GIGA_MAC_VER_15 = 0x0f  // 8101
 118 };
 119
 120 enum phy_version {
 121         RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 122         RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 123         RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
 124         RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
 125         RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
 126         RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
 127 };
 128
 129 #define _R(NAME,MAC,MASK) \
 130         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 131
 132 static const struct {
 133         const char *name;
 134         u8 mac_version;
 135         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 136 } rtl_chip_info[] = {
 137         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 138         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 139         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 140         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 141         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 142         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 143         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 144         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 145         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 146         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 147         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880)  // PCI-E 8139
 148 };
 149 #undef _R
 150
 151 enum cfg_version {
 152         RTL_CFG_0 = 0x00,
 153         RTL_CFG_1,
 154         RTL_CFG_2
 155 };
 156
 157 static void rtl_hw_start_8169(struct net_device *);
 158 static void rtl_hw_start_8168(struct net_device *);
 159 static void rtl_hw_start_8101(struct net_device *);
 160
 161 static struct pci_device_id rtl8169_pci_tbl[] = {
 162         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 163         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 164         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 165         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 166         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 167         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 168         { PCI_DEVICE(0x1259,                    0xc107), 0, 0, RTL_CFG_0 },
 169         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 170         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 171                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 172         {0,},
 173 };
 174
 175 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 176
 177 static int rx_copybreak = 200;
 178 static int use_dac;
 179 static struct {
 180         u32 msg_enable;
 181 } debug = { -1 };
 182
 183 enum rtl_registers {
 184         MAC0            = 0,    /* Ethernet hardware address. */
 185         MAR0            = 8,    /* Multicast filter. */
 186         CounterAddrLow          = 0x10,
 187         CounterAddrHigh         = 0x14,
 188         TxDescStartAddrLow      = 0x20,
 189         TxDescStartAddrHigh     = 0x24,
 190         TxHDescStartAddrLow     = 0x28,
 191         TxHDescStartAddrHigh    = 0x2c,
 192         FLASH           = 0x30,
 193         ERSR            = 0x36,
 194         ChipCmd         = 0x37,
 195         TxPoll          = 0x38,
 196         IntrMask        = 0x3c,
 197         IntrStatus      = 0x3e,
 198         TxConfig        = 0x40,
 199         RxConfig        = 0x44,
 200         RxMissed        = 0x4c,
 201         Cfg9346         = 0x50,
 202         Config0         = 0x51,
 203         Config1         = 0x52,
 204         Config2         = 0x53,
 205         Config3         = 0x54,
 206         Config4         = 0x55,
 207         Config5         = 0x56,
 208         MultiIntr       = 0x5c,
 209         PHYAR           = 0x60,
 210         TBICSR          = 0x64,
 211         TBI_ANAR        = 0x68,
 212         TBI_LPAR        = 0x6a,
 213         PHYstatus       = 0x6c,
 214         RxMaxSize       = 0xda,
 215         CPlusCmd        = 0xe0,
 216         IntrMitigate    = 0xe2,
 217         RxDescAddrLow   = 0xe4,
 218         RxDescAddrHigh  = 0xe8,
 219         EarlyTxThres    = 0xec,
 220         FuncEvent       = 0xf0,
 221         FuncEventMask   = 0xf4,
 222         FuncPresetState = 0xf8,
 223         FuncForceEvent  = 0xfc,
 224 };
 225
 226 enum rtl_register_content {
 227         /* InterruptStatusBits */
 228         SYSErr          = 0x8000,
 229         PCSTimeout      = 0x4000,
 230         SWInt           = 0x0100,
 231         TxDescUnavail   = 0x0080,
 232         RxFIFOOver      = 0x0040,
 233         LinkChg         = 0x0020,
 234         RxOverflow      = 0x0010,
 235         TxErr           = 0x0008,
 236         TxOK            = 0x0004,
 237         RxErr           = 0x0002,
 238         RxOK            = 0x0001,
 239
 240         /* RxStatusDesc */
 241         RxFOVF  = (1 << 23),
 242         RxRWT   = (1 << 22),
 243         RxRES   = (1 << 21),
 244         RxRUNT  = (1 << 20),
 245         RxCRC   = (1 << 19),
 246
 247         /* ChipCmdBits */
 248         CmdReset        = 0x10,
 249         CmdRxEnb        = 0x08,
 250         CmdTxEnb        = 0x04,
 251         RxBufEmpty      = 0x01,
 252
 253         /* TXPoll register p.5 */
 254         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 255         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 256         FSWInt          = 0x01,         /* Forced software interrupt */
 257
 258         /* Cfg9346Bits */
 259         Cfg9346_Lock    = 0x00,
 260         Cfg9346_Unlock  = 0xc0,
 261
 262         /* rx_mode_bits */
 263         AcceptErr       = 0x20,
 264         AcceptRunt      = 0x10,
 265         AcceptBroadcast = 0x08,
 266         AcceptMulticast = 0x04,
 267         AcceptMyPhys    = 0x02,
 268         AcceptAllPhys   = 0x01,
 269
 270         /* RxConfigBits */
 271         RxCfgFIFOShift  = 13,
 272         RxCfgDMAShift   =  8,
 273
 274         /* TxConfigBits */
 275         TxInterFrameGapShift = 24,
 276         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 277
 278         /* Config1 register p.24 */
 279         PMEnable        = (1 << 0),     /* Power Management Enable */
 280
 281         /* Config2 register p. 25 */
 282         PCI_Clock_66MHz = 0x01,
 283         PCI_Clock_33MHz = 0x00,
 284
 285         /* Config3 register p.25 */
 286         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 287         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 288
 289         /* Config5 register p.27 */
 290         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 291         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 292         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 293         LanWake         = (1 << 1),     /* LanWake enable/disable */
 294         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 295
 296         /* TBICSR p.28 */
 297         TBIReset        = 0x80000000,
 298         TBILoopback     = 0x40000000,
 299         TBINwEnable     = 0x20000000,
 300         TBINwRestart    = 0x10000000,
 301         TBILinkOk       = 0x02000000,
 302         TBINwComplete   = 0x01000000,
 303
 304         /* CPlusCmd p.31 */
 305         PktCntrDisable  = (1 << 7),     // 8168
 306         RxVlan          = (1 << 6),
 307         RxChkSum        = (1 << 5),
 308         PCIDAC          = (1 << 4),
 309         PCIMulRW        = (1 << 3),
 310         INTT_0          = 0x0000,       // 8168
 311         INTT_1          = 0x0001,       // 8168
 312         INTT_2          = 0x0002,       // 8168
 313         INTT_3          = 0x0003,       // 8168
 314
 315         /* rtl8169_PHYstatus */
 316         TBI_Enable      = 0x80,
 317         TxFlowCtrl      = 0x40,
 318         RxFlowCtrl      = 0x20,
 319         _1000bpsF       = 0x10,
 320         _100bps         = 0x08,
 321         _10bps          = 0x04,
 322         LinkStatus      = 0x02,
 323         FullDup         = 0x01,
 324
 325         /* _TBICSRBit */
 326         TBILinkOK       = 0x02000000,
 327
 328         /* DumpCounterCommand */
 329         CounterDump     = 0x8,
 330 };
 331
 332 enum desc_status_bit {
 333         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 334         RingEnd         = (1 << 30), /* End of descriptor ring */
 335         FirstFrag       = (1 << 29), /* First segment of a packet */
 336         LastFrag        = (1 << 28), /* Final segment of a packet */
 337
 338         /* Tx private */
 339         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 340         MSSShift        = 16,        /* MSS value position */
 341         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 342         IPCS            = (1 << 18), /* Calculate IP checksum */
 343         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 344         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 345         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 346
 347         /* Rx private */
 348         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 349         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 350
 351 #define RxProtoUDP      (PID1)
 352 #define RxProtoTCP      (PID0)
 353 #define RxProtoIP       (PID1 | PID0)
 354 #define RxProtoMask     RxProtoIP
 355
 356         IPFail          = (1 << 16), /* IP checksum failed */
 357         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 358         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 359         RxVlanTag       = (1 << 16), /* VLAN tag available */
 360 };
 361
 362 #define RsvdMask        0x3fffc000
 363
 364 struct TxDesc {
 365         u32 opts1;
 366         u32 opts2;
 367         u64 addr;
 368 };
 369
 370 struct RxDesc {
 371         u32 opts1;
 372         u32 opts2;
 373         u64 addr;
 374 };
 375
 376 struct ring_info {
 377         struct sk_buff  *skb;
 378         u32             len;
 379         u8              __pad[sizeof(void *) - sizeof(u32)];
 380 };
 381
 382 struct rtl8169_private {
 383         void __iomem *mmio_addr;        /* memory map physical address */
 384         struct pci_dev *pci_dev;        /* Index of PCI device */
 385         struct net_device *dev;
 386         struct net_device_stats stats;  /* statistics of net device */
 387         spinlock_t lock;                /* spin lock flag */
 388         u32 msg_enable;
 389         int chipset;
 390         int mac_version;
 391         int phy_version;
 392         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 393         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 394         u32 dirty_rx;
 395         u32 dirty_tx;
 396         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 397         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 398         dma_addr_t TxPhyAddr;
 399         dma_addr_t RxPhyAddr;
 400         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 401         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 402         unsigned align;
 403         unsigned rx_buf_sz;
 404         struct timer_list timer;
 405         u16 cp_cmd;
 406         u16 intr_event;
 407         u16 napi_event;
 408         u16 intr_mask;
 409         int phy_auto_nego_reg;
 410         int phy_1000_ctrl_reg;
 411 #ifdef CONFIG_R8169_VLAN
 412         struct vlan_group *vlgrp;
 413 #endif
 414         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 415         void (*get_settings)(struct net_device *, struct ethtool_cmd *);
 416         void (*phy_reset_enable)(void __iomem *);
 417         void (*hw_start)(struct net_device *);
 418         unsigned int (*phy_reset_pending)(void __iomem *);
 419         unsigned int (*link_ok)(void __iomem *);
 420         struct delayed_work task;
 421         unsigned wol_enabled : 1;
 422 };
 423
 424 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 425 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 426 module_param(rx_copybreak, int, 0);
 427 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 428 module_param(use_dac, int, 0);
 429 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 430 module_param_named(debug, debug.msg_enable, int, 0);
 431 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 432 MODULE_LICENSE("GPL");
 433 MODULE_VERSION(RTL8169_VERSION);
 434
 435 static int rtl8169_open(struct net_device *dev);
 436 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 437 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 438 static int rtl8169_init_ring(struct net_device *dev);
 439 static void rtl_hw_start(struct net_device *dev);
 440 static int rtl8169_close(struct net_device *dev);
 441 static void rtl_set_rx_mode(struct net_device *dev);
 442 static void rtl8169_tx_timeout(struct net_device *dev);
 443 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 444 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 445                                 void __iomem *);
 446 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 447 static void rtl8169_down(struct net_device *dev);
 448 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 449
 450 #ifdef CONFIG_R8169_NAPI
 451 static int rtl8169_poll(struct net_device *dev, int *budget);
 452 #endif
 453
 454 static const unsigned int rtl8169_rx_config =
 455         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 456
 457 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 458 {
 459         int i;
 460
 461         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
 462
 463         for (i = 20; i > 0; i--) {
 464                 /*
 465                  * Check if the RTL8169 has completed writing to the specified
 466                  * MII register.
 467                  */
 468                 if (!(RTL_R32(PHYAR) & 0x80000000))
 469                         break;
 470                 udelay(25);
 471         }
 472 }
 473
 474 static int mdio_read(void __iomem *ioaddr, int reg_addr)
 475 {
 476         int i, value = -1;
 477
 478         RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
 479
 480         for (i = 20; i > 0; i--) {
 481                 /*
 482                  * Check if the RTL8169 has completed retrieving data from
 483                  * the specified MII register.
 484                  */
 485                 if (RTL_R32(PHYAR) & 0x80000000) {
 486                         value = (int) (RTL_R32(PHYAR) & 0xFFFF);
 487                         break;
 488                 }
 489                 udelay(25);
 490         }
 491         return value;
 492 }
 493
 494 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 495 {
 496         RTL_W16(IntrMask, 0x0000);
 497
 498         RTL_W16(IntrStatus, 0xffff);
 499 }
 500
 501 static void rtl8169_asic_down(void __iomem *ioaddr)
 502 {
 503         RTL_W8(ChipCmd, 0x00);
 504         rtl8169_irq_mask_and_ack(ioaddr);
 505         RTL_R16(CPlusCmd);
 506 }
 507
 508 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 509 {
 510         return RTL_R32(TBICSR) & TBIReset;
 511 }
 512
 513 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 514 {
 515         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 516 }
 517
 518 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 519 {
 520         return RTL_R32(TBICSR) & TBILinkOk;
 521 }
 522
 523 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 524 {
 525         return RTL_R8(PHYstatus) & LinkStatus;
 526 }
 527
 528 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 529 {
 530         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 531 }
 532
 533 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 534 {
 535         unsigned int val;
 536
 537         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 538         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 539 }
 540
 541 static void rtl8169_check_link_status(struct net_device *dev,
 542                                       struct rtl8169_private *tp,
 543                                       void __iomem *ioaddr)
 544 {
 545         unsigned long flags;
 546
 547         spin_lock_irqsave(&tp->lock, flags);
 548         if (tp->link_ok(ioaddr)) {
 549                 netif_carrier_on(dev);
 550                 if (netif_msg_ifup(tp))
 551                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
 552         } else {
 553                 if (netif_msg_ifdown(tp))
 554                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
 555                 netif_carrier_off(dev);
 556         }
 557         spin_unlock_irqrestore(&tp->lock, flags);
 558 }
 559
 560 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 561 {
 562         struct rtl8169_private *tp = netdev_priv(dev);
 563         void __iomem *ioaddr = tp->mmio_addr;
 564         u8 options;
 565
 566         wol->wolopts = 0;
 567
 568 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 569         wol->supported = WAKE_ANY;
 570
 571         spin_lock_irq(&tp->lock);
 572
 573         options = RTL_R8(Config1);
 574         if (!(options & PMEnable))
 575                 goto out_unlock;
 576
 577         options = RTL_R8(Config3);
 578         if (options & LinkUp)
 579                 wol->wolopts |= WAKE_PHY;
 580         if (options & MagicPacket)
 581                 wol->wolopts |= WAKE_MAGIC;
 582
 583         options = RTL_R8(Config5);
 584         if (options & UWF)
 585                 wol->wolopts |= WAKE_UCAST;
 586         if (options & BWF)
 587                 wol->wolopts |= WAKE_BCAST;
 588         if (options & MWF)
 589                 wol->wolopts |= WAKE_MCAST;
 590
 591 out_unlock:
 592         spin_unlock_irq(&tp->lock);
 593 }
 594
 595 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 596 {
 597         struct rtl8169_private *tp = netdev_priv(dev);
 598         void __iomem *ioaddr = tp->mmio_addr;
 599         unsigned int i;
 600         static struct {
 601                 u32 opt;
 602                 u16 reg;
 603                 u8  mask;
 604         } cfg[] = {
 605                 { WAKE_ANY,   Config1, PMEnable },
 606                 { WAKE_PHY,   Config3, LinkUp },
 607                 { WAKE_MAGIC, Config3, MagicPacket },
 608                 { WAKE_UCAST, Config5, UWF },
 609                 { WAKE_BCAST, Config5, BWF },
 610                 { WAKE_MCAST, Config5, MWF },
 611                 { WAKE_ANY,   Config5, LanWake }
 612         };
 613
 614         spin_lock_irq(&tp->lock);
 615
 616         RTL_W8(Cfg9346, Cfg9346_Unlock);
 617
 618         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 619                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 620                 if (wol->wolopts & cfg[i].opt)
 621                         options |= cfg[i].mask;
 622                 RTL_W8(cfg[i].reg, options);
 623         }
 624
 625         RTL_W8(Cfg9346, Cfg9346_Lock);
 626
 627         tp->wol_enabled = (wol->wolopts) ? 1 : 0;
 628
 629         spin_unlock_irq(&tp->lock);
 630
 631         return 0;
 632 }
 633
 634 static void rtl8169_get_drvinfo(struct net_device *dev,
 635                                 struct ethtool_drvinfo *info)
 636 {
 637         struct rtl8169_private *tp = netdev_priv(dev);
 638
 639         strcpy(info->driver, MODULENAME);
 640         strcpy(info->version, RTL8169_VERSION);
 641         strcpy(info->bus_info, pci_name(tp->pci_dev));
 642 }
 643
 644 static int rtl8169_get_regs_len(struct net_device *dev)
 645 {
 646         return R8169_REGS_SIZE;
 647 }
 648
 649 static int rtl8169_set_speed_tbi(struct net_device *dev,
 650                                  u8 autoneg, u16 speed, u8 duplex)
 651 {
 652         struct rtl8169_private *tp = netdev_priv(dev);
 653         void __iomem *ioaddr = tp->mmio_addr;
 654         int ret = 0;
 655         u32 reg;
 656
 657         reg = RTL_R32(TBICSR);
 658         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 659             (duplex == DUPLEX_FULL)) {
 660                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 661         } else if (autoneg == AUTONEG_ENABLE)
 662                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 663         else {
 664                 if (netif_msg_link(tp)) {
 665                         printk(KERN_WARNING "%s: "
 666                                "incorrect speed setting refused in TBI mode\n",
 667                                dev->name);
 668                 }
 669                 ret = -EOPNOTSUPP;
 670         }
 671
 672         return ret;
 673 }
 674
 675 static int rtl8169_set_speed_xmii(struct net_device *dev,
 676                                   u8 autoneg, u16 speed, u8 duplex)
 677 {
 678         struct rtl8169_private *tp = netdev_priv(dev);
 679         void __iomem *ioaddr = tp->mmio_addr;
 680         int auto_nego, giga_ctrl;
 681
 682         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 683         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
 684                        ADVERTISE_100HALF | ADVERTISE_100FULL);
 685         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 686         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 687
 688         if (autoneg == AUTONEG_ENABLE) {
 689                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 690                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 691                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 692         } else {
 693                 if (speed == SPEED_10)
 694                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 695                 else if (speed == SPEED_100)
 696                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
 697                 else if (speed == SPEED_1000)
 698                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 699
 700                 if (duplex == DUPLEX_HALF)
 701                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
 702
 703                 if (duplex == DUPLEX_FULL)
 704                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
 705
 706                 /* This tweak comes straight from Realtek's driver. */
 707                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
 708                     (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
 709                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
 710                 }
 711         }
 712
 713         /* The 8100e/8101e do Fast Ethernet only. */
 714         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 715             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
 716             (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
 717                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
 718                     netif_msg_link(tp)) {
 719                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
 720                                dev->name);
 721                 }
 722                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 723         }
 724
 725         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 726
 727         tp->phy_auto_nego_reg = auto_nego;
 728         tp->phy_1000_ctrl_reg = giga_ctrl;
 729
 730         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 731         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 732         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
 733         return 0;
 734 }
 735
 736 static int rtl8169_set_speed(struct net_device *dev,
 737                              u8 autoneg, u16 speed, u8 duplex)
 738 {
 739         struct rtl8169_private *tp = netdev_priv(dev);
 740         int ret;
 741
 742         ret = tp->set_speed(dev, autoneg, speed, duplex);
 743
 744         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 745                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 746
 747         return ret;
 748 }
 749
 750 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 751 {
 752         struct rtl8169_private *tp = netdev_priv(dev);
 753         unsigned long flags;
 754         int ret;
 755
 756         spin_lock_irqsave(&tp->lock, flags);
 757         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 758         spin_unlock_irqrestore(&tp->lock, flags);
 759
 760         return ret;
 761 }
 762
 763 static u32 rtl8169_get_rx_csum(struct net_device *dev)
 764 {
 765         struct rtl8169_private *tp = netdev_priv(dev);
 766
 767         return tp->cp_cmd & RxChkSum;
 768 }
 769
 770 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
 771 {
 772         struct rtl8169_private *tp = netdev_priv(dev);
 773         void __iomem *ioaddr = tp->mmio_addr;
 774         unsigned long flags;
 775
 776         spin_lock_irqsave(&tp->lock, flags);
 777
 778         if (data)
 779                 tp->cp_cmd |= RxChkSum;
 780         else
 781                 tp->cp_cmd &= ~RxChkSum;
 782
 783         RTL_W16(CPlusCmd, tp->cp_cmd);
 784         RTL_R16(CPlusCmd);
 785
 786         spin_unlock_irqrestore(&tp->lock, flags);
 787
 788         return 0;
 789 }
 790
 791 #ifdef CONFIG_R8169_VLAN
 792
 793 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 794                                       struct sk_buff *skb)
 795 {
 796         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
 797                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
 798 }
 799
 800 static void rtl8169_vlan_rx_register(struct net_device *dev,
 801                                      struct vlan_group *grp)
 802 {
 803         struct rtl8169_private *tp = netdev_priv(dev);
 804         void __iomem *ioaddr = tp->mmio_addr;
 805         unsigned long flags;
 806
 807         spin_lock_irqsave(&tp->lock, flags);
 808         tp->vlgrp = grp;
 809         if (tp->vlgrp)
 810                 tp->cp_cmd |= RxVlan;
 811         else
 812                 tp->cp_cmd &= ~RxVlan;
 813         RTL_W16(CPlusCmd, tp->cp_cmd);
 814         RTL_R16(CPlusCmd);
 815         spin_unlock_irqrestore(&tp->lock, flags);
 816 }
 817
 818 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 819                                struct sk_buff *skb)
 820 {
 821         u32 opts2 = le32_to_cpu(desc->opts2);
 822         int ret;
 823
 824         if (tp->vlgrp && (opts2 & RxVlanTag)) {
 825                 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
 826                 ret = 0;
 827         } else
 828                 ret = -1;
 829         desc->opts2 = 0;
 830         return ret;
 831 }
 832
 833 #else /* !CONFIG_R8169_VLAN */
 834
 835 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 836                                       struct sk_buff *skb)
 837 {
 838         return 0;
 839 }
 840
 841 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 842                                struct sk_buff *skb)
 843 {
 844         return -1;
 845 }
 846
 847 #endif
 848
 849 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
 850 {
 851         struct rtl8169_private *tp = netdev_priv(dev);
 852         void __iomem *ioaddr = tp->mmio_addr;
 853         u32 status;
 854
 855         cmd->supported =
 856                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
 857         cmd->port = PORT_FIBRE;
 858         cmd->transceiver = XCVR_INTERNAL;
 859
 860         status = RTL_R32(TBICSR);
 861         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
 862         cmd->autoneg = !!(status & TBINwEnable);
 863
 864         cmd->speed = SPEED_1000;
 865         cmd->duplex = DUPLEX_FULL; /* Always set */
 866 }
 867
 868 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
 869 {
 870         struct rtl8169_private *tp = netdev_priv(dev);
 871         void __iomem *ioaddr = tp->mmio_addr;
 872         u8 status;
 873
 874         cmd->supported = SUPPORTED_10baseT_Half |
 875                          SUPPORTED_10baseT_Full |
 876                          SUPPORTED_100baseT_Half |
 877                          SUPPORTED_100baseT_Full |
 878                          SUPPORTED_1000baseT_Full |
 879                          SUPPORTED_Autoneg |
 880                          SUPPORTED_TP;
 881
 882         cmd->autoneg = 1;
 883         cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
 884
 885         if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
 886                 cmd->advertising |= ADVERTISED_10baseT_Half;
 887         if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
 888                 cmd->advertising |= ADVERTISED_10baseT_Full;
 889         if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
 890                 cmd->advertising |= ADVERTISED_100baseT_Half;
 891         if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
 892                 cmd->advertising |= ADVERTISED_100baseT_Full;
 893         if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
 894                 cmd->advertising |= ADVERTISED_1000baseT_Full;
 895
 896         status = RTL_R8(PHYstatus);
 897
 898         if (status & _1000bpsF)
 899                 cmd->speed = SPEED_1000;
 900         else if (status & _100bps)
 901                 cmd->speed = SPEED_100;
 902         else if (status & _10bps)
 903                 cmd->speed = SPEED_10;
 904
 905         if (status & TxFlowCtrl)
 906                 cmd->advertising |= ADVERTISED_Asym_Pause;
 907         if (status & RxFlowCtrl)
 908                 cmd->advertising |= ADVERTISED_Pause;
 909
 910         cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
 911                       DUPLEX_FULL : DUPLEX_HALF;
 912 }
 913
 914 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 915 {
 916         struct rtl8169_private *tp = netdev_priv(dev);
 917         unsigned long flags;
 918
 919         spin_lock_irqsave(&tp->lock, flags);
 920
 921         tp->get_settings(dev, cmd);
 922
 923         spin_unlock_irqrestore(&tp->lock, flags);
 924         return 0;
 925 }
 926
 927 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 928                              void *p)
 929 {
 930         struct rtl8169_private *tp = netdev_priv(dev);
 931         unsigned long flags;
 932
 933         if (regs->len > R8169_REGS_SIZE)
 934                 regs->len = R8169_REGS_SIZE;
 935
 936         spin_lock_irqsave(&tp->lock, flags);
 937         memcpy_fromio(p, tp->mmio_addr, regs->len);
 938         spin_unlock_irqrestore(&tp->lock, flags);
 939 }
 940
 941 static u32 rtl8169_get_msglevel(struct net_device *dev)
 942 {
 943         struct rtl8169_private *tp = netdev_priv(dev);
 944
 945         return tp->msg_enable;
 946 }
 947
 948 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
 949 {
 950         struct rtl8169_private *tp = netdev_priv(dev);
 951
 952         tp->msg_enable = value;
 953 }
 954
 955 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
 956         "tx_packets",
 957         "rx_packets",
 958         "tx_errors",
 959         "rx_errors",
 960         "rx_missed",
 961         "align_errors",
 962         "tx_single_collisions",
 963         "tx_multi_collisions",
 964         "unicast",
 965         "broadcast",
 966         "multicast",
 967         "tx_aborted",
 968         "tx_underrun",
 969 };
 970
 971 struct rtl8169_counters {
 972         u64     tx_packets;
 973         u64     rx_packets;
 974         u64     tx_errors;
 975         u32     rx_errors;
 976         u16     rx_missed;
 977         u16     align_errors;
 978         u32     tx_one_collision;
 979         u32     tx_multi_collision;
 980         u64     rx_unicast;
 981         u64     rx_broadcast;
 982         u32     rx_multicast;
 983         u16     tx_aborted;
 984         u16     tx_underun;
 985 };
 986
 987 static int rtl8169_get_stats_count(struct net_device *dev)
 988 {
 989         return ARRAY_SIZE(rtl8169_gstrings);
 990 }
 991
 992 static void rtl8169_get_ethtool_stats(struct net_device *dev,
 993                                       struct ethtool_stats *stats, u64 *data)
 994 {
 995         struct rtl8169_private *tp = netdev_priv(dev);
 996         void __iomem *ioaddr = tp->mmio_addr;
 997         struct rtl8169_counters *counters;
 998         dma_addr_t paddr;
 999         u32 cmd;
1000
1001         ASSERT_RTNL();
1002
1003         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1004         if (!counters)
1005                 return;
1006
1007         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1008         cmd = (u64)paddr & DMA_32BIT_MASK;
1009         RTL_W32(CounterAddrLow, cmd);
1010         RTL_W32(CounterAddrLow, cmd | CounterDump);
1011
1012         while (RTL_R32(CounterAddrLow) & CounterDump) {
1013                 if (msleep_interruptible(1))
1014                         break;
1015         }
1016
1017         RTL_W32(CounterAddrLow, 0);
1018         RTL_W32(CounterAddrHigh, 0);
1019
1020         data[0] = le64_to_cpu(counters->tx_packets);
1021         data[1] = le64_to_cpu(counters->rx_packets);
1022         data[2] = le64_to_cpu(counters->tx_errors);
1023         data[3] = le32_to_cpu(counters->rx_errors);
1024         data[4] = le16_to_cpu(counters->rx_missed);
1025         data[5] = le16_to_cpu(counters->align_errors);
1026         data[6] = le32_to_cpu(counters->tx_one_collision);
1027         data[7] = le32_to_cpu(counters->tx_multi_collision);
1028         data[8] = le64_to_cpu(counters->rx_unicast);
1029         data[9] = le64_to_cpu(counters->rx_broadcast);
1030         data[10] = le32_to_cpu(counters->rx_multicast);
1031         data[11] = le16_to_cpu(counters->tx_aborted);
1032         data[12] = le16_to_cpu(counters->tx_underun);
1033
1034         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1035 }
1036
1037 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1038 {
1039         switch(stringset) {
1040         case ETH_SS_STATS:
1041                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1042                 break;
1043         }
1044 }
1045
1046 static const struct ethtool_ops rtl8169_ethtool_ops = {
1047         .get_drvinfo            = rtl8169_get_drvinfo,
1048         .get_regs_len           = rtl8169_get_regs_len,
1049         .get_link               = ethtool_op_get_link,
1050         .get_settings           = rtl8169_get_settings,
1051         .set_settings           = rtl8169_set_settings,
1052         .get_msglevel           = rtl8169_get_msglevel,
1053         .set_msglevel           = rtl8169_set_msglevel,
1054         .get_rx_csum            = rtl8169_get_rx_csum,
1055         .set_rx_csum            = rtl8169_set_rx_csum,
1056         .get_tx_csum            = ethtool_op_get_tx_csum,
1057         .set_tx_csum            = ethtool_op_set_tx_csum,
1058         .get_sg                 = ethtool_op_get_sg,
1059         .set_sg                 = ethtool_op_set_sg,
1060         .get_tso                = ethtool_op_get_tso,
1061         .set_tso                = ethtool_op_set_tso,
1062         .get_regs               = rtl8169_get_regs,
1063         .get_wol                = rtl8169_get_wol,
1064         .set_wol                = rtl8169_set_wol,
1065         .get_strings            = rtl8169_get_strings,
1066         .get_stats_count        = rtl8169_get_stats_count,
1067         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1068         .get_perm_addr          = ethtool_op_get_perm_addr,
1069 };
1070
1071 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1072                                        int bitnum, int bitval)
1073 {
1074         int val;
1075
1076         val = mdio_read(ioaddr, reg);
1077         val = (bitval == 1) ?
1078                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1079         mdio_write(ioaddr, reg, val & 0xffff);
1080 }
1081
1082 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1083                                     void __iomem *ioaddr)
1084 {
1085         /*
1086          * The driver currently handles the 8168Bf and the 8168Be identically
1087          * but they can be identified more specifically through the test below
1088          * if needed:
1089          *
1090          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1091          *
1092          * Same thing for the 8101Eb and the 8101Ec:
1093          *
1094          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1095          */
1096         const struct {
1097                 u32 mask;
1098                 int mac_version;
1099         } mac_info[] = {
1100                 { 0x38800000,   RTL_GIGA_MAC_VER_15 },
1101                 { 0x38000000,   RTL_GIGA_MAC_VER_12 },
1102                 { 0x34000000,   RTL_GIGA_MAC_VER_13 },
1103                 { 0x30800000,   RTL_GIGA_MAC_VER_14 },
1104                 { 0x30000000,   RTL_GIGA_MAC_VER_11 },
1105                 { 0x98000000,   RTL_GIGA_MAC_VER_06 },
1106                 { 0x18000000,   RTL_GIGA_MAC_VER_05 },
1107                 { 0x10000000,   RTL_GIGA_MAC_VER_04 },
1108                 { 0x04000000,   RTL_GIGA_MAC_VER_03 },
1109                 { 0x00800000,   RTL_GIGA_MAC_VER_02 },
1110                 { 0x00000000,   RTL_GIGA_MAC_VER_01 }   /* Catch-all */
1111         }, *p = mac_info;
1112         u32 reg;
1113
1114         reg = RTL_R32(TxConfig) & 0xfc800000;
1115         while ((reg & p->mask) != p->mask)
1116                 p++;
1117         tp->mac_version = p->mac_version;
1118 }
1119
1120 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1121 {
1122         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1123 }
1124
1125 static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1126                                     void __iomem *ioaddr)
1127 {
1128         const struct {
1129                 u16 mask;
1130                 u16 set;
1131                 int phy_version;
1132         } phy_info[] = {
1133                 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1134                 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1135                 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1136                 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1137         }, *p = phy_info;
1138         u16 reg;
1139
1140         reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1141         while ((reg & p->mask) != p->set)
1142                 p++;
1143         tp->phy_version = p->phy_version;
1144 }
1145
1146 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1147 {
1148         struct {
1149                 int version;
1150                 char *msg;
1151                 u32 reg;
1152         } phy_print[] = {
1153                 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1154                 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1155                 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1156                 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1157                 { 0, NULL, 0x0000 }
1158         }, *p;
1159
1160         for (p = phy_print; p->msg; p++) {
1161                 if (tp->phy_version == p->version) {
1162                         dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1163                         return;
1164                 }
1165         }
1166         dprintk("phy_version == Unknown\n");
1167 }
1168
1169 static void rtl8169_hw_phy_config(struct net_device *dev)
1170 {
1171         struct rtl8169_private *tp = netdev_priv(dev);
1172         void __iomem *ioaddr = tp->mmio_addr;
1173         struct {
1174                 u16 regs[5]; /* Beware of bit-sign propagation */
1175         } phy_magic[5] = { {
1176                 { 0x0000,       //w 4 15 12 0
1177                   0x00a1,       //w 3 15 0 00a1
1178                   0x0008,       //w 2 15 0 0008
1179                   0x1020,       //w 1 15 0 1020
1180                   0x1000 } },{  //w 0 15 0 1000
1181                 { 0x7000,       //w 4 15 12 7
1182                   0xff41,       //w 3 15 0 ff41
1183                   0xde60,       //w 2 15 0 de60
1184                   0x0140,       //w 1 15 0 0140
1185                   0x0077 } },{  //w 0 15 0 0077
1186                 { 0xa000,       //w 4 15 12 a
1187                   0xdf01,       //w 3 15 0 df01
1188                   0xdf20,       //w 2 15 0 df20
1189                   0xff95,       //w 1 15 0 ff95
1190                   0xfa00 } },{  //w 0 15 0 fa00
1191                 { 0xb000,       //w 4 15 12 b
1192                   0xff41,       //w 3 15 0 ff41
1193                   0xde20,       //w 2 15 0 de20
1194                   0x0140,       //w 1 15 0 0140
1195                   0x00bb } },{  //w 0 15 0 00bb
1196                 { 0xf000,       //w 4 15 12 f
1197                   0xdf01,       //w 3 15 0 df01
1198                   0xdf20,       //w 2 15 0 df20
1199                   0xff95,       //w 1 15 0 ff95
1200                   0xbf00 }      //w 0 15 0 bf00
1201                 }
1202         }, *p = phy_magic;
1203         unsigned int i;
1204
1205         rtl8169_print_mac_version(tp);
1206         rtl8169_print_phy_version(tp);
1207
1208         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1209                 return;
1210         if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1211                 return;
1212
1213         dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1214         dprintk("Do final_reg2.cfg\n");
1215
1216         /* Shazam ! */
1217
1218         if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1219                 mdio_write(ioaddr, 31, 0x0002);
1220                 mdio_write(ioaddr,  1, 0x90d0);
1221                 mdio_write(ioaddr, 31, 0x0000);
1222                 return;
1223         }
1224
1225         /* phy config for RTL8169s mac_version C chip */
1226         mdio_write(ioaddr, 31, 0x0001);                 //w 31 2 0 1
1227         mdio_write(ioaddr, 21, 0x1000);                 //w 21 15 0 1000
1228         mdio_write(ioaddr, 24, 0x65c7);                 //w 24 15 0 65c7
1229         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1230
1231         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1232                 int val, pos = 4;
1233
1234                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1235                 mdio_write(ioaddr, pos, val);
1236                 while (--pos >= 0)
1237                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1238                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1239                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1240         }
1241         mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1242 }
1243
1244 static void rtl8169_phy_timer(unsigned long __opaque)
1245 {
1246         struct net_device *dev = (struct net_device *)__opaque;
1247         struct rtl8169_private *tp = netdev_priv(dev);
1248         struct timer_list *timer = &tp->timer;
1249         void __iomem *ioaddr = tp->mmio_addr;
1250         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1251
1252         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1253         assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1254
1255         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1256                 return;
1257
1258         spin_lock_irq(&tp->lock);
1259
1260         if (tp->phy_reset_pending(ioaddr)) {
1261                 /*
1262                  * A busy loop could burn quite a few cycles on nowadays CPU.
1263                  * Let's delay the execution of the timer for a few ticks.
1264                  */
1265                 timeout = HZ/10;
1266                 goto out_mod_timer;
1267         }
1268
1269         if (tp->link_ok(ioaddr))
1270                 goto out_unlock;
1271
1272         if (netif_msg_link(tp))
1273                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1274
1275         tp->phy_reset_enable(ioaddr);
1276
1277 out_mod_timer:
1278         mod_timer(timer, jiffies + timeout);
1279 out_unlock:
1280         spin_unlock_irq(&tp->lock);
1281 }
1282
1283 static inline void rtl8169_delete_timer(struct net_device *dev)
1284 {
1285         struct rtl8169_private *tp = netdev_priv(dev);
1286         struct timer_list *timer = &tp->timer;
1287
1288         if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1289             (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1290                 return;
1291
1292         del_timer_sync(timer);
1293 }
1294
1295 static inline void rtl8169_request_timer(struct net_device *dev)
1296 {
1297         struct rtl8169_private *tp = netdev_priv(dev);
1298         struct timer_list *timer = &tp->timer;
1299
1300         if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1301             (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1302                 return;
1303
1304         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1305 }
1306
1307 #ifdef CONFIG_NET_POLL_CONTROLLER
1308 /*
1309  * Polling 'interrupt' - used by things like netconsole to send skbs
1310  * without having to re-enable interrupts. It's not called while
1311  * the interrupt routine is executing.
1312  */
1313 static void rtl8169_netpoll(struct net_device *dev)
1314 {
1315         struct rtl8169_private *tp = netdev_priv(dev);
1316         struct pci_dev *pdev = tp->pci_dev;
1317
1318         disable_irq(pdev->irq);
1319         rtl8169_interrupt(pdev->irq, dev);
1320         enable_irq(pdev->irq);
1321 }
1322 #endif
1323
1324 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1325                                   void __iomem *ioaddr)
1326 {
1327         iounmap(ioaddr);
1328         pci_release_regions(pdev);
1329         pci_disable_device(pdev);
1330         free_netdev(dev);
1331 }
1332
1333 static void rtl8169_phy_reset(struct net_device *dev,
1334                               struct rtl8169_private *tp)
1335 {
1336         void __iomem *ioaddr = tp->mmio_addr;
1337         unsigned int i;
1338
1339         tp->phy_reset_enable(ioaddr);
1340         for (i = 0; i < 100; i++) {
1341                 if (!tp->phy_reset_pending(ioaddr))
1342                         return;
1343                 msleep(1);
1344         }
1345         if (netif_msg_link(tp))
1346                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1347 }
1348
1349 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1350 {
1351         void __iomem *ioaddr = tp->mmio_addr;
1352
1353         rtl8169_hw_phy_config(dev);
1354
1355         dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1356         RTL_W8(0x82, 0x01);
1357
1358         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1359
1360         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1361                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1362
1363         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1364                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1365                 RTL_W8(0x82, 0x01);
1366                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1367                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1368         }
1369
1370         rtl8169_phy_reset(dev, tp);
1371
1372         /*
1373          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1374          * only 8101. Don't panic.
1375          */
1376         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1377
1378         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1379                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1380 }
1381
1382 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1383 {
1384         struct rtl8169_private *tp = netdev_priv(dev);
1385         struct mii_ioctl_data *data = if_mii(ifr);
1386
1387         if (!netif_running(dev))
1388                 return -ENODEV;
1389
1390         switch (cmd) {
1391         case SIOCGMIIPHY:
1392                 data->phy_id = 32; /* Internal PHY */
1393                 return 0;
1394
1395         case SIOCGMIIREG:
1396                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1397                 return 0;
1398
1399         case SIOCSMIIREG:
1400                 if (!capable(CAP_NET_ADMIN))
1401                         return -EPERM;
1402                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1403                 return 0;
1404         }
1405         return -EOPNOTSUPP;
1406 }
1407
1408 static const struct rtl_cfg_info {
1409         void (*hw_start)(struct net_device *);
1410         unsigned int region;
1411         unsigned int align;
1412         u16 intr_event;
1413         u16 napi_event;
1414 } rtl_cfg_infos [] = {
1415         [RTL_CFG_0] = {
1416                 .hw_start       = rtl_hw_start_8169,
1417                 .region         = 1,
1418                 .align          = 0,
1419                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1420                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1421                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1422         },
1423         [RTL_CFG_1] = {
1424                 .hw_start       = rtl_hw_start_8168,
1425                 .region         = 2,
1426                 .align          = 8,
1427                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1428                                   TxErr | TxOK | RxOK | RxErr,
1429                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow
1430         },
1431         [RTL_CFG_2] = {
1432                 .hw_start       = rtl_hw_start_8101,
1433                 .region         = 2,
1434                 .align          = 8,
1435                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1436                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1437                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1438         }
1439 };
1440
1441 static int __devinit
1442 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1443 {
1444         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1445         const unsigned int region = cfg->region;
1446         struct rtl8169_private *tp;
1447         struct net_device *dev;
1448         void __iomem *ioaddr;
1449         unsigned int i;
1450         int rc;
1451
1452         if (netif_msg_drv(&debug)) {
1453                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1454                        MODULENAME, RTL8169_VERSION);
1455         }
1456
1457         dev = alloc_etherdev(sizeof (*tp));
1458         if (!dev) {
1459                 if (netif_msg_drv(&debug))
1460                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1461                 rc = -ENOMEM;
1462                 goto out;
1463         }
1464
1465         SET_MODULE_OWNER(dev);
1466         SET_NETDEV_DEV(dev, &pdev->dev);
1467         tp = netdev_priv(dev);
1468         tp->dev = dev;
1469         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1470
1471         /* enable device (incl. PCI PM wakeup and hotplug setup) */
1472         rc = pci_enable_device(pdev);
1473         if (rc < 0) {
1474                 if (netif_msg_probe(tp))
1475                         dev_err(&pdev->dev, "enable failure\n");
1476                 goto err_out_free_dev_1;
1477         }
1478
1479         rc = pci_set_mwi(pdev);
1480         if (rc < 0)
1481                 goto err_out_disable_2;
1482
1483         /* make sure PCI base addr 1 is MMIO */
1484         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1485                 if (netif_msg_probe(tp)) {
1486                         dev_err(&pdev->dev,
1487                                 "region #%d not an MMIO resource, aborting\n",
1488                                 region);
1489                 }
1490                 rc = -ENODEV;
1491                 goto err_out_mwi_3;
1492         }
1493
1494         /* check for weird/broken PCI region reporting */
1495         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1496                 if (netif_msg_probe(tp)) {
1497                         dev_err(&pdev->dev,
1498                                 "Invalid PCI region size(s), aborting\n");
1499                 }
1500                 rc = -ENODEV;
1501                 goto err_out_mwi_3;
1502         }
1503
1504         rc = pci_request_regions(pdev, MODULENAME);
1505         if (rc < 0) {
1506                 if (netif_msg_probe(tp))
1507                         dev_err(&pdev->dev, "could not request regions.\n");
1508                 goto err_out_mwi_3;
1509         }
1510
1511         tp->cp_cmd = PCIMulRW | RxChkSum;
1512
1513         if ((sizeof(dma_addr_t) > 4) &&
1514             !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1515                 tp->cp_cmd |= PCIDAC;
1516                 dev->features |= NETIF_F_HIGHDMA;
1517         } else {
1518                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1519                 if (rc < 0) {
1520                         if (netif_msg_probe(tp)) {
1521                                 dev_err(&pdev->dev,
1522                                         "DMA configuration failed.\n");
1523                         }
1524                         goto err_out_free_res_4;
1525                 }
1526         }
1527
1528         pci_set_master(pdev);
1529
1530         /* ioremap MMIO region */
1531         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1532         if (!ioaddr) {
1533                 if (netif_msg_probe(tp))
1534                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1535                 rc = -EIO;
1536                 goto err_out_free_res_4;
1537         }
1538
1539         /* Unneeded ? Don't mess with Mrs. Murphy. */
1540         rtl8169_irq_mask_and_ack(ioaddr);
1541
1542         /* Soft reset the chip. */
1543         RTL_W8(ChipCmd, CmdReset);
1544
1545         /* Check that the chip has finished the reset. */
1546         for (i = 0; i < 100; i++) {
1547                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1548                         break;
1549                 msleep_interruptible(1);
1550         }
1551
1552         /* Identify chip attached to board */
1553         rtl8169_get_mac_version(tp, ioaddr);
1554         rtl8169_get_phy_version(tp, ioaddr);
1555
1556         rtl8169_print_mac_version(tp);
1557         rtl8169_print_phy_version(tp);
1558
1559         for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1560                 if (tp->mac_version == rtl_chip_info[i].mac_version)
1561                         break;
1562         }
1563         if (i < 0) {
1564                 /* Unknown chip: assume array element #0, original RTL-8169 */
1565                 if (netif_msg_probe(tp)) {
1566                         dev_printk(KERN_DEBUG, &pdev->dev,
1567                                 "unknown chip version, assuming %s\n",
1568                                 rtl_chip_info[0].name);
1569                 }
1570                 i++;
1571         }
1572         tp->chipset = i;
1573
1574         RTL_W8(Cfg9346, Cfg9346_Unlock);
1575         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1576         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1577         RTL_W8(Cfg9346, Cfg9346_Lock);
1578
1579         if (RTL_R8(PHYstatus) & TBI_Enable) {
1580                 tp->set_speed = rtl8169_set_speed_tbi;
1581                 tp->get_settings = rtl8169_gset_tbi;
1582                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1583                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1584                 tp->link_ok = rtl8169_tbi_link_ok;
1585
1586                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1587         } else {
1588                 tp->set_speed = rtl8169_set_speed_xmii;
1589                 tp->get_settings = rtl8169_gset_xmii;
1590                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1591                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1592                 tp->link_ok = rtl8169_xmii_link_ok;
1593
1594                 dev->do_ioctl = rtl8169_ioctl;
1595         }
1596
1597         /* Get MAC address.  FIXME: read EEPROM */
1598         for (i = 0; i < MAC_ADDR_LEN; i++)
1599                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1600         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1601
1602         dev->open = rtl8169_open;
1603         dev->hard_start_xmit = rtl8169_start_xmit;
1604         dev->get_stats = rtl8169_get_stats;
1605         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1606         dev->stop = rtl8169_close;
1607         dev->tx_timeout = rtl8169_tx_timeout;
1608         dev->set_multicast_list = rtl_set_rx_mode;
1609         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1610         dev->irq = pdev->irq;
1611         dev->base_addr = (unsigned long) ioaddr;
1612         dev->change_mtu = rtl8169_change_mtu;
1613
1614 #ifdef CONFIG_R8169_NAPI
1615         dev->poll = rtl8169_poll;
1616         dev->weight = R8169_NAPI_WEIGHT;
1617 #endif
1618
1619 #ifdef CONFIG_R8169_VLAN
1620         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1621         dev->vlan_rx_register = rtl8169_vlan_rx_register;
1622 #endif
1623
1624 #ifdef CONFIG_NET_POLL_CONTROLLER
1625         dev->poll_controller = rtl8169_netpoll;
1626 #endif
1627
1628         tp->intr_mask = 0xffff;
1629         tp->pci_dev = pdev;
1630         tp->mmio_addr = ioaddr;
1631         tp->align = cfg->align;
1632         tp->hw_start = cfg->hw_start;
1633         tp->intr_event = cfg->intr_event;
1634         tp->napi_event = cfg->napi_event;
1635
1636         init_timer(&tp->timer);
1637         tp->timer.data = (unsigned long) dev;
1638         tp->timer.function = rtl8169_phy_timer;
1639
1640         spin_lock_init(&tp->lock);
1641
1642         rc = register_netdev(dev);
1643         if (rc < 0)
1644                 goto err_out_unmap_5;
1645
1646         pci_set_drvdata(pdev, dev);
1647
1648         if (netif_msg_probe(tp)) {
1649                 printk(KERN_INFO "%s: %s at 0x%lx, "
1650                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1651                        "IRQ %d\n",
1652                        dev->name,
1653                        rtl_chip_info[tp->chipset].name,
1654                        dev->base_addr,
1655                        dev->dev_addr[0], dev->dev_addr[1],
1656                        dev->dev_addr[2], dev->dev_addr[3],
1657                        dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1658         }
1659
1660         rtl8169_init_phy(dev, tp);
1661
1662 out:
1663         return rc;
1664
1665 err_out_unmap_5:
1666         iounmap(ioaddr);
1667 err_out_free_res_4:
1668         pci_release_regions(pdev);
1669 err_out_mwi_3:
1670         pci_clear_mwi(pdev);
1671 err_out_disable_2:
1672         pci_disable_device(pdev);
1673 err_out_free_dev_1:
1674         free_netdev(dev);
1675         goto out;
1676 }
1677
1678 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1679 {
1680         struct net_device *dev = pci_get_drvdata(pdev);
1681         struct rtl8169_private *tp = netdev_priv(dev);
1682
1683         flush_scheduled_work();
1684
1685         unregister_netdev(dev);
1686         rtl8169_release_board(pdev, dev, tp->mmio_addr);
1687         pci_set_drvdata(pdev, NULL);
1688 }
1689
1690 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1691                                   struct net_device *dev)
1692 {
1693         unsigned int mtu = dev->mtu;
1694
1695         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1696 }
1697
1698 static int rtl8169_open(struct net_device *dev)
1699 {
1700         struct rtl8169_private *tp = netdev_priv(dev);
1701         struct pci_dev *pdev = tp->pci_dev;
1702         int retval = -ENOMEM;
1703
1704
1705         rtl8169_set_rxbufsize(tp, dev);
1706
1707         /*
1708          * Rx and Tx desscriptors needs 256 bytes alignment.
1709          * pci_alloc_consistent provides more.
1710          */
1711         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1712                                                &tp->TxPhyAddr);
1713         if (!tp->TxDescArray)
1714                 goto out;
1715
1716         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1717                                                &tp->RxPhyAddr);
1718         if (!tp->RxDescArray)
1719                 goto err_free_tx_0;
1720
1721         retval = rtl8169_init_ring(dev);
1722         if (retval < 0)
1723                 goto err_free_rx_1;
1724
1725         INIT_DELAYED_WORK(&tp->task, NULL);
1726
1727         smp_mb();
1728
1729         retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1730                              dev->name, dev);
1731         if (retval < 0)
1732                 goto err_release_ring_2;
1733
1734         rtl_hw_start(dev);
1735
1736         rtl8169_request_timer(dev);
1737
1738         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1739 out:
1740         return retval;
1741
1742 err_release_ring_2:
1743         rtl8169_rx_clear(tp);
1744 err_free_rx_1:
1745         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1746                             tp->RxPhyAddr);
1747 err_free_tx_0:
1748         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1749                             tp->TxPhyAddr);
1750         goto out;
1751 }
1752
1753 static void rtl8169_hw_reset(void __iomem *ioaddr)
1754 {
1755         /* Disable interrupts */
1756         rtl8169_irq_mask_and_ack(ioaddr);
1757
1758         /* Reset the chipset */
1759         RTL_W8(ChipCmd, CmdReset);
1760
1761         /* PCI commit */
1762         RTL_R8(ChipCmd);
1763 }
1764
1765 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1766 {
1767         void __iomem *ioaddr = tp->mmio_addr;
1768         u32 cfg = rtl8169_rx_config;
1769
1770         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1771         RTL_W32(RxConfig, cfg);
1772
1773         /* Set DMA burst size and Interframe Gap Time */
1774         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1775                 (InterFrameGap << TxInterFrameGapShift));
1776 }
1777
1778 static void rtl_hw_start(struct net_device *dev)
1779 {
1780         struct rtl8169_private *tp = netdev_priv(dev);
1781         void __iomem *ioaddr = tp->mmio_addr;
1782         unsigned int i;
1783
1784         /* Soft reset the chip. */
1785         RTL_W8(ChipCmd, CmdReset);
1786
1787         /* Check that the chip has finished the reset. */
1788         for (i = 0; i < 100; i++) {
1789                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1790                         break;
1791                 msleep_interruptible(1);
1792         }
1793
1794         tp->hw_start(dev);
1795
1796         netif_start_queue(dev);
1797 }
1798
1799
1800 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1801                                          void __iomem *ioaddr)
1802 {
1803         /*
1804          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1805          * register to be written before TxDescAddrLow to work.
1806          * Switching from MMIO to I/O access fixes the issue as well.
1807          */
1808         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1809         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1810         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1811         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1812 }
1813
1814 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1815 {
1816         u16 cmd;
1817
1818         cmd = RTL_R16(CPlusCmd);
1819         RTL_W16(CPlusCmd, cmd);
1820         return cmd;
1821 }
1822
1823 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1824 {
1825         /* Low hurts. Let's disable the filtering. */
1826         RTL_W16(RxMaxSize, 16383);
1827 }
1828
1829 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1830 {
1831         struct {
1832                 u32 mac_version;
1833                 u32 clk;
1834                 u32 val;
1835         } cfg2_info [] = {
1836                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1837                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1838                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1839                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1840         }, *p = cfg2_info;
1841         unsigned int i;
1842         u32 clk;
1843
1844         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1845         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1846                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1847                         RTL_W32(0x7c, p->val);
1848                         break;
1849                 }
1850         }
1851 }
1852
1853 static void rtl_hw_start_8169(struct net_device *dev)
1854 {
1855         struct rtl8169_private *tp = netdev_priv(dev);
1856         void __iomem *ioaddr = tp->mmio_addr;
1857         struct pci_dev *pdev = tp->pci_dev;
1858
1859         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1860                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1861                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1862         }
1863
1864         RTL_W8(Cfg9346, Cfg9346_Unlock);
1865         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1866             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1867             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1868             (tp->mac_version == RTL_GIGA_MAC_VER_04))
1869                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1870
1871         RTL_W8(EarlyTxThres, EarlyTxThld);
1872
1873         rtl_set_rx_max_size(ioaddr);
1874
1875         rtl_set_rx_tx_config_registers(tp);
1876
1877         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1878
1879         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1880             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1881                 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1882                         "Bit-3 and bit-14 MUST be 1\n");
1883                 tp->cp_cmd |= (1 << 14);
1884         }
1885
1886         RTL_W16(CPlusCmd, tp->cp_cmd);
1887
1888         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1889
1890         /*
1891          * Undocumented corner. Supposedly:
1892          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1893          */
1894         RTL_W16(IntrMitigate, 0x0000);
1895
1896         rtl_set_rx_tx_desc_registers(tp, ioaddr);
1897
1898         RTL_W8(Cfg9346, Cfg9346_Lock);
1899
1900         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1901         RTL_R8(IntrMask);
1902
1903         RTL_W32(RxMissed, 0);
1904
1905         rtl_set_rx_mode(dev);
1906
1907         /* no early-rx interrupts */
1908         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1909
1910         /* Enable all known interrupts by setting the interrupt mask. */
1911         RTL_W16(IntrMask, tp->intr_event);
1912
1913         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1914 }
1915
1916 static void rtl_hw_start_8168(struct net_device *dev)
1917 {
1918         struct rtl8169_private *tp = netdev_priv(dev);
1919         void __iomem *ioaddr = tp->mmio_addr;
1920         struct pci_dev *pdev = tp->pci_dev;
1921         u8 ctl;
1922
1923         RTL_W8(Cfg9346, Cfg9346_Unlock);
1924
1925         RTL_W8(EarlyTxThres, EarlyTxThld);
1926
1927         rtl_set_rx_max_size(ioaddr);
1928
1929         rtl_set_rx_tx_config_registers(tp);
1930
1931         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
1932
1933         RTL_W16(CPlusCmd, tp->cp_cmd);
1934
1935         /* Tx performance tweak. */
1936         pci_read_config_byte(pdev, 0x69, &ctl);
1937         ctl = (ctl & ~0x70) | 0x50;
1938         pci_write_config_byte(pdev, 0x69, ctl);
1939
1940         RTL_W16(IntrMitigate, 0x5151);
1941
1942         /* Work around for RxFIFO overflow. */
1943         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
1944                 tp->intr_event |= RxFIFOOver | PCSTimeout;
1945                 tp->intr_event &= ~RxOverflow;
1946         }
1947
1948         rtl_set_rx_tx_desc_registers(tp, ioaddr);
1949
1950         RTL_W8(Cfg9346, Cfg9346_Lock);
1951
1952         RTL_R8(IntrMask);
1953
1954         RTL_W32(RxMissed, 0);
1955
1956         rtl_set_rx_mode(dev);
1957
1958         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1959
1960         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1961
1962         RTL_W16(IntrMask, tp->intr_event);
1963 }
1964
1965 static void rtl_hw_start_8101(struct net_device *dev)
1966 {
1967         struct rtl8169_private *tp = netdev_priv(dev);
1968         void __iomem *ioaddr = tp->mmio_addr;
1969         struct pci_dev *pdev = tp->pci_dev;
1970
1971         if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
1972                 pci_write_config_word(pdev, 0x68, 0x00);
1973                 pci_write_config_word(pdev, 0x69, 0x08);
1974         }
1975
1976         RTL_W8(Cfg9346, Cfg9346_Unlock);
1977
1978         RTL_W8(EarlyTxThres, EarlyTxThld);
1979
1980         rtl_set_rx_max_size(ioaddr);
1981
1982         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1983
1984         RTL_W16(CPlusCmd, tp->cp_cmd);
1985
1986         RTL_W16(IntrMitigate, 0x0000);
1987
1988         rtl_set_rx_tx_desc_registers(tp, ioaddr);
1989
1990         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1991         rtl_set_rx_tx_config_registers(tp);
1992
1993         RTL_W8(Cfg9346, Cfg9346_Lock);
1994
1995         RTL_R8(IntrMask);
1996
1997         RTL_W32(RxMissed, 0);
1998
1999         rtl_set_rx_mode(dev);
2000
2001         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2002
2003         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2004
2005         RTL_W16(IntrMask, tp->intr_event);
2006 }
2007
2008 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2009 {
2010         struct rtl8169_private *tp = netdev_priv(dev);
2011         int ret = 0;
2012
2013         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2014                 return -EINVAL;
2015
2016         dev->mtu = new_mtu;
2017
2018         if (!netif_running(dev))
2019                 goto out;
2020
2021         rtl8169_down(dev);
2022
2023         rtl8169_set_rxbufsize(tp, dev);
2024
2025         ret = rtl8169_init_ring(dev);
2026         if (ret < 0)
2027                 goto out;
2028
2029         netif_poll_enable(dev);
2030
2031         rtl_hw_start(dev);
2032
2033         rtl8169_request_timer(dev);
2034
2035 out:
2036         return ret;
2037 }
2038
2039 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2040 {
2041         desc->addr = 0x0badbadbadbadbadull;
2042         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2043 }
2044
2045 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2046                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2047 {
2048         struct pci_dev *pdev = tp->pci_dev;
2049
2050         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2051                          PCI_DMA_FROMDEVICE);
2052         dev_kfree_skb(*sk_buff);
2053         *sk_buff = NULL;
2054         rtl8169_make_unusable_by_asic(desc);
2055 }
2056
2057 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2058 {
2059         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2060
2061         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2062 }
2063
2064 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2065                                        u32 rx_buf_sz)
2066 {
2067         desc->addr = cpu_to_le64(mapping);
2068         wmb();
2069         rtl8169_mark_to_asic(desc, rx_buf_sz);
2070 }
2071
2072 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2073                                             struct net_device *dev,
2074                                             struct RxDesc *desc, int rx_buf_sz,
2075                                             unsigned int align)
2076 {
2077         struct sk_buff *skb;
2078         dma_addr_t mapping;
2079         unsigned int pad;
2080
2081         pad = align ? align : NET_IP_ALIGN;
2082
2083         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2084         if (!skb)
2085                 goto err_out;
2086
2087         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2088
2089         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2090                                  PCI_DMA_FROMDEVICE);
2091
2092         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2093 out:
2094         return skb;
2095
2096 err_out:
2097         rtl8169_make_unusable_by_asic(desc);
2098         goto out;
2099 }
2100
2101 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2102 {
2103         unsigned int i;
2104
2105         for (i = 0; i < NUM_RX_DESC; i++) {
2106                 if (tp->Rx_skbuff[i]) {
2107                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2108                                             tp->RxDescArray + i);
2109                 }
2110         }
2111 }
2112
2113 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2114                            u32 start, u32 end)
2115 {
2116         u32 cur;
2117
2118         for (cur = start; end - cur != 0; cur++) {
2119                 struct sk_buff *skb;
2120                 unsigned int i = cur % NUM_RX_DESC;
2121
2122                 WARN_ON((s32)(end - cur) < 0);
2123
2124                 if (tp->Rx_skbuff[i])
2125                         continue;
2126
2127                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2128                                            tp->RxDescArray + i,
2129                                            tp->rx_buf_sz, tp->align);
2130                 if (!skb)
2131                         break;
2132
2133                 tp->Rx_skbuff[i] = skb;
2134         }
2135         return cur - start;
2136 }
2137
2138 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2139 {
2140         desc->opts1 |= cpu_to_le32(RingEnd);
2141 }
2142
2143 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2144 {
2145         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2146 }
2147
2148 static int rtl8169_init_ring(struct net_device *dev)
2149 {
2150         struct rtl8169_private *tp = netdev_priv(dev);
2151
2152         rtl8169_init_ring_indexes(tp);
2153
2154         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2155         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2156
2157         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2158                 goto err_out;
2159
2160         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2161
2162         return 0;
2163
2164 err_out:
2165         rtl8169_rx_clear(tp);
2166         return -ENOMEM;
2167 }
2168
2169 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2170                                  struct TxDesc *desc)
2171 {
2172         unsigned int len = tx_skb->len;
2173
2174         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2175         desc->opts1 = 0x00;
2176         desc->opts2 = 0x00;
2177         desc->addr = 0x00;
2178         tx_skb->len = 0;
2179 }
2180
2181 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2182 {
2183         unsigned int i;
2184
2185         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2186                 unsigned int entry = i % NUM_TX_DESC;
2187                 struct ring_info *tx_skb = tp->tx_skb + entry;
2188                 unsigned int len = tx_skb->len;
2189
2190                 if (len) {
2191                         struct sk_buff *skb = tx_skb->skb;
2192
2193                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2194                                              tp->TxDescArray + entry);
2195                         if (skb) {
2196                                 dev_kfree_skb(skb);
2197                                 tx_skb->skb = NULL;
2198                         }
2199                         tp->stats.tx_dropped++;
2200                 }
2201         }
2202         tp->cur_tx = tp->dirty_tx = 0;
2203 }
2204
2205 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2206 {
2207         struct rtl8169_private *tp = netdev_priv(dev);
2208
2209         PREPARE_DELAYED_WORK(&tp->task, task);
2210         schedule_delayed_work(&tp->task, 4);
2211 }
2212
2213 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2214 {
2215         struct rtl8169_private *tp = netdev_priv(dev);
2216         void __iomem *ioaddr = tp->mmio_addr;
2217
2218         synchronize_irq(dev->irq);
2219
2220         /* Wait for any pending NAPI task to complete */
2221         netif_poll_disable(dev);
2222
2223         rtl8169_irq_mask_and_ack(ioaddr);
2224
2225         netif_poll_enable(dev);
2226 }
2227
2228 static void rtl8169_reinit_task(struct work_struct *work)
2229 {
2230         struct rtl8169_private *tp =
2231                 container_of(work, struct rtl8169_private, task.work);
2232         struct net_device *dev = tp->dev;
2233         int ret;
2234
2235         rtnl_lock();
2236
2237         if (!netif_running(dev))
2238                 goto out_unlock;
2239
2240         rtl8169_wait_for_quiescence(dev);
2241         rtl8169_close(dev);
2242
2243         ret = rtl8169_open(dev);
2244         if (unlikely(ret < 0)) {
2245                 if (net_ratelimit() && netif_msg_drv(tp)) {
2246                         printk(PFX KERN_ERR "%s: reinit failure (status = %d)."
2247                                " Rescheduling.\n", dev->name, ret);
2248                 }
2249                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2250         }
2251
2252 out_unlock:
2253         rtnl_unlock();
2254 }
2255
2256 static void rtl8169_reset_task(struct work_struct *work)
2257 {
2258         struct rtl8169_private *tp =
2259                 container_of(work, struct rtl8169_private, task.work);
2260         struct net_device *dev = tp->dev;
2261
2262         rtnl_lock();
2263
2264         if (!netif_running(dev))
2265                 goto out_unlock;
2266
2267         rtl8169_wait_for_quiescence(dev);
2268
2269         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2270         rtl8169_tx_clear(tp);
2271
2272         if (tp->dirty_rx == tp->cur_rx) {
2273                 rtl8169_init_ring_indexes(tp);
2274                 rtl_hw_start(dev);
2275                 netif_wake_queue(dev);
2276         } else {
2277                 if (net_ratelimit() && netif_msg_intr(tp)) {
2278                         printk(PFX KERN_EMERG "%s: Rx buffers shortage\n",
2279                                dev->name);
2280                 }
2281                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2282         }
2283
2284 out_unlock:
2285         rtnl_unlock();
2286 }
2287
2288 static void rtl8169_tx_timeout(struct net_device *dev)
2289 {
2290         struct rtl8169_private *tp = netdev_priv(dev);
2291
2292         rtl8169_hw_reset(tp->mmio_addr);
2293
2294         /* Let's wait a bit while any (async) irq lands on */
2295         rtl8169_schedule_work(dev, rtl8169_reset_task);
2296 }
2297
2298 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2299                               u32 opts1)
2300 {
2301         struct skb_shared_info *info = skb_shinfo(skb);
2302         unsigned int cur_frag, entry;
2303         struct TxDesc *txd;
2304
2305         entry = tp->cur_tx;
2306         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2307                 skb_frag_t *frag = info->frags + cur_frag;
2308                 dma_addr_t mapping;
2309                 u32 status, len;
2310                 void *addr;
2311
2312                 entry = (entry + 1) % NUM_TX_DESC;
2313
2314                 txd = tp->TxDescArray + entry;
2315                 len = frag->size;
2316                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2317                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2318
2319                 /* anti gcc 2.95.3 bugware (sic) */
2320                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2321
2322                 txd->opts1 = cpu_to_le32(status);
2323                 txd->addr = cpu_to_le64(mapping);
2324
2325                 tp->tx_skb[entry].len = len;
2326         }
2327
2328         if (cur_frag) {
2329                 tp->tx_skb[entry].skb = skb;
2330                 txd->opts1 |= cpu_to_le32(LastFrag);
2331         }
2332
2333         return cur_frag;
2334 }
2335
2336 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2337 {
2338         if (dev->features & NETIF_F_TSO) {
2339                 u32 mss = skb_shinfo(skb)->gso_size;
2340
2341                 if (mss)
2342                         return LargeSend | ((mss & MSSMask) << MSSShift);
2343         }
2344         if (skb->ip_summed == CHECKSUM_PARTIAL) {
2345                 const struct iphdr *ip = ip_hdr(skb);
2346
2347                 if (ip->protocol == IPPROTO_TCP)
2348                         return IPCS | TCPCS;
2349                 else if (ip->protocol == IPPROTO_UDP)
2350                         return IPCS | UDPCS;
2351                 WARN_ON(1);     /* we need a WARN() */
2352         }
2353         return 0;
2354 }
2355
2356 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2357 {
2358         struct rtl8169_private *tp = netdev_priv(dev);
2359         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2360         struct TxDesc *txd = tp->TxDescArray + entry;
2361         void __iomem *ioaddr = tp->mmio_addr;
2362         dma_addr_t mapping;
2363         u32 status, len;
2364         u32 opts1;
2365         int ret = NETDEV_TX_OK;
2366
2367         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2368                 if (netif_msg_drv(tp)) {
2369                         printk(KERN_ERR
2370                                "%s: BUG! Tx Ring full when queue awake!\n",
2371                                dev->name);
2372                 }
2373                 goto err_stop;
2374         }
2375
2376         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2377                 goto err_stop;
2378
2379         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2380
2381         frags = rtl8169_xmit_frags(tp, skb, opts1);
2382         if (frags) {
2383                 len = skb_headlen(skb);
2384                 opts1 |= FirstFrag;
2385         } else {
2386                 len = skb->len;
2387
2388                 if (unlikely(len < ETH_ZLEN)) {
2389                         if (skb_padto(skb, ETH_ZLEN))
2390                                 goto err_update_stats;
2391                         len = ETH_ZLEN;
2392                 }
2393
2394                 opts1 |= FirstFrag | LastFrag;
2395                 tp->tx_skb[entry].skb = skb;
2396         }
2397
2398         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2399
2400         tp->tx_skb[entry].len = len;
2401         txd->addr = cpu_to_le64(mapping);
2402         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2403
2404         wmb();
2405
2406         /* anti gcc 2.95.3 bugware (sic) */
2407         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2408         txd->opts1 = cpu_to_le32(status);
2409
2410         dev->trans_start = jiffies;
2411
2412         tp->cur_tx += frags + 1;
2413
2414         smp_wmb();
2415
2416         RTL_W8(TxPoll, NPQ);    /* set polling bit */
2417
2418         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2419                 netif_stop_queue(dev);
2420                 smp_rmb();
2421                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2422                         netif_wake_queue(dev);
2423         }
2424
2425 out:
2426         return ret;
2427
2428 err_stop:
2429         netif_stop_queue(dev);
2430         ret = NETDEV_TX_BUSY;
2431 err_update_stats:
2432         tp->stats.tx_dropped++;
2433         goto out;
2434 }
2435
2436 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2437 {
2438         struct rtl8169_private *tp = netdev_priv(dev);
2439         struct pci_dev *pdev = tp->pci_dev;
2440         void __iomem *ioaddr = tp->mmio_addr;
2441         u16 pci_status, pci_cmd;
2442
2443         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2444         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2445
2446         if (netif_msg_intr(tp)) {
2447                 printk(KERN_ERR
2448                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2449                        dev->name, pci_cmd, pci_status);
2450         }
2451
2452         /*
2453          * The recovery sequence below admits a very elaborated explanation:
2454          * - it seems to work;
2455          * - I did not see what else could be done;
2456          * - it makes iop3xx happy.
2457          *
2458          * Feel free to adjust to your needs.
2459          */
2460         if (pdev->broken_parity_status)
2461                 pci_cmd &= ~PCI_COMMAND_PARITY;
2462         else
2463                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2464
2465         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2466
2467         pci_write_config_word(pdev, PCI_STATUS,
2468                 pci_status & (PCI_STATUS_DETECTED_PARITY |
2469                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2470                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2471
2472         /* The infamous DAC f*ckup only happens at boot time */
2473         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2474                 if (netif_msg_intr(tp))
2475                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2476                 tp->cp_cmd &= ~PCIDAC;
2477                 RTL_W16(CPlusCmd, tp->cp_cmd);
2478                 dev->features &= ~NETIF_F_HIGHDMA;
2479         }
2480
2481         rtl8169_hw_reset(ioaddr);
2482
2483         rtl8169_schedule_work(dev, rtl8169_reinit_task);
2484 }
2485
2486 static void rtl8169_tx_interrupt(struct net_device *dev,
2487                                  struct rtl8169_private *tp,
2488                                  void __iomem *ioaddr)
2489 {
2490         unsigned int dirty_tx, tx_left;
2491
2492         dirty_tx = tp->dirty_tx;
2493         smp_rmb();
2494         tx_left = tp->cur_tx - dirty_tx;
2495
2496         while (tx_left > 0) {
2497                 unsigned int entry = dirty_tx % NUM_TX_DESC;
2498                 struct ring_info *tx_skb = tp->tx_skb + entry;
2499                 u32 len = tx_skb->len;
2500                 u32 status;
2501
2502                 rmb();
2503                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2504                 if (status & DescOwn)
2505                         break;
2506
2507                 tp->stats.tx_bytes += len;
2508                 tp->stats.tx_packets++;
2509
2510                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2511
2512                 if (status & LastFrag) {
2513                         dev_kfree_skb_irq(tx_skb->skb);
2514                         tx_skb->skb = NULL;
2515                 }
2516                 dirty_tx++;
2517                 tx_left--;
2518         }
2519
2520         if (tp->dirty_tx != dirty_tx) {
2521                 tp->dirty_tx = dirty_tx;
2522                 smp_wmb();
2523                 if (netif_queue_stopped(dev) &&
2524                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2525                         netif_wake_queue(dev);
2526                 }
2527         }
2528 }
2529
2530 static inline int rtl8169_fragmented_frame(u32 status)
2531 {
2532         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2533 }
2534
2535 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2536 {
2537         u32 opts1 = le32_to_cpu(desc->opts1);
2538         u32 status = opts1 & RxProtoMask;
2539
2540         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2541             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2542             ((status == RxProtoIP) && !(opts1 & IPFail)))
2543                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2544         else
2545                 skb->ip_summed = CHECKSUM_NONE;
2546 }
2547
2548 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2549                                        struct rtl8169_private *tp, int pkt_size,
2550                                        dma_addr_t addr)
2551 {
2552         struct sk_buff *skb;
2553         bool done = false;
2554
2555         if (pkt_size >= rx_copybreak)
2556                 goto out;
2557
2558         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2559         if (!skb)
2560                 goto out;
2561
2562         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2563                                     PCI_DMA_FROMDEVICE);
2564         skb_reserve(skb, NET_IP_ALIGN);
2565         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2566         *sk_buff = skb;
2567         done = true;
2568 out:
2569         return done;
2570 }
2571
2572 static int rtl8169_rx_interrupt(struct net_device *dev,
2573                                 struct rtl8169_private *tp,
2574                                 void __iomem *ioaddr)
2575 {
2576         unsigned int cur_rx, rx_left;
2577         unsigned int delta, count;
2578
2579         cur_rx = tp->cur_rx;
2580         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2581         rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2582
2583         for (; rx_left > 0; rx_left--, cur_rx++) {
2584                 unsigned int entry = cur_rx % NUM_RX_DESC;
2585                 struct RxDesc *desc = tp->RxDescArray + entry;
2586                 u32 status;
2587
2588                 rmb();
2589                 status = le32_to_cpu(desc->opts1);
2590
2591                 if (status & DescOwn)
2592                         break;
2593                 if (unlikely(status & RxRES)) {
2594                         if (netif_msg_rx_err(tp)) {
2595                                 printk(KERN_INFO
2596                                        "%s: Rx ERROR. status = %08x\n",
2597                                        dev->name, status);
2598                         }
2599                         tp->stats.rx_errors++;
2600                         if (status & (RxRWT | RxRUNT))
2601                                 tp->stats.rx_length_errors++;
2602                         if (status & RxCRC)
2603                                 tp->stats.rx_crc_errors++;
2604                         if (status & RxFOVF) {
2605                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
2606                                 tp->stats.rx_fifo_errors++;
2607                         }
2608                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2609                 } else {
2610                         struct sk_buff *skb = tp->Rx_skbuff[entry];
2611                         dma_addr_t addr = le64_to_cpu(desc->addr);
2612                         int pkt_size = (status & 0x00001FFF) - 4;
2613                         struct pci_dev *pdev = tp->pci_dev;
2614
2615                         /*
2616                          * The driver does not support incoming fragmented
2617                          * frames. They are seen as a symptom of over-mtu
2618                          * sized frames.
2619                          */
2620                         if (unlikely(rtl8169_fragmented_frame(status))) {
2621                                 tp->stats.rx_dropped++;
2622                                 tp->stats.rx_length_errors++;
2623                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2624                                 continue;
2625                         }
2626
2627                         rtl8169_rx_csum(skb, desc);
2628
2629                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2630                                 pci_dma_sync_single_for_device(pdev, addr,
2631                                         pkt_size, PCI_DMA_FROMDEVICE);
2632                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2633                         } else {
2634                                 pci_unmap_single(pdev, addr, pkt_size,
2635                                                  PCI_DMA_FROMDEVICE);
2636                                 tp->Rx_skbuff[entry] = NULL;
2637                         }
2638
2639                         skb_put(skb, pkt_size);
2640                         skb->protocol = eth_type_trans(skb, dev);
2641
2642                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2643                                 rtl8169_rx_skb(skb);
2644
2645                         dev->last_rx = jiffies;
2646                         tp->stats.rx_bytes += pkt_size;
2647                         tp->stats.rx_packets++;
2648                 }
2649
2650                 /* Work around for AMD plateform. */
2651                 if ((desc->opts2 & 0xfffe000) &&
2652                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2653                         desc->opts2 = 0;
2654                         cur_rx++;
2655                 }
2656         }
2657
2658         count = cur_rx - tp->cur_rx;
2659         tp->cur_rx = cur_rx;
2660
2661         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2662         if (!delta && count && netif_msg_intr(tp))
2663                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2664         tp->dirty_rx += delta;
2665
2666         /*
2667          * FIXME: until there is periodic timer to try and refill the ring,
2668          * a temporary shortage may definitely kill the Rx process.
2669          * - disable the asic to try and avoid an overflow and kick it again
2670          *   after refill ?
2671          * - how do others driver handle this condition (Uh oh...).
2672          */
2673         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2674                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2675
2676         return count;
2677 }
2678
2679 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2680 {
2681         struct net_device *dev = dev_instance;
2682         struct rtl8169_private *tp = netdev_priv(dev);
2683         int boguscnt = max_interrupt_work;
2684         void __iomem *ioaddr = tp->mmio_addr;
2685         int status;
2686         int handled = 0;
2687
2688         do {
2689                 status = RTL_R16(IntrStatus);
2690
2691                 /* hotplug/major error/no more work/shared irq */
2692                 if ((status == 0xFFFF) || !status)
2693                         break;
2694
2695                 handled = 1;
2696
2697                 if (unlikely(!netif_running(dev))) {
2698                         rtl8169_asic_down(ioaddr);
2699                         goto out;
2700                 }
2701
2702                 status &= tp->intr_mask;
2703                 RTL_W16(IntrStatus,
2704                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
2705
2706                 if (!(status & tp->intr_event))
2707                         break;
2708
2709                 /* Work around for rx fifo overflow */
2710                 if (unlikely(status & RxFIFOOver) &&
2711                     (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2712                         netif_stop_queue(dev);
2713                         rtl8169_tx_timeout(dev);
2714                         break;
2715                 }
2716
2717                 if (unlikely(status & SYSErr)) {
2718                         rtl8169_pcierr_interrupt(dev);
2719                         break;
2720                 }
2721
2722                 if (status & LinkChg)
2723                         rtl8169_check_link_status(dev, tp, ioaddr);
2724
2725 #ifdef CONFIG_R8169_NAPI
2726                 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2727                 tp->intr_mask = ~tp->napi_event;
2728
2729                 if (likely(netif_rx_schedule_prep(dev)))
2730                         __netif_rx_schedule(dev);
2731                 else if (netif_msg_intr(tp)) {
2732                         printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2733                                dev->name, status);
2734                 }
2735                 break;
2736 #else
2737                 /* Rx interrupt */
2738                 if (status & (RxOK | RxOverflow | RxFIFOOver))
2739                         rtl8169_rx_interrupt(dev, tp, ioaddr);
2740
2741                 /* Tx interrupt */
2742                 if (status & (TxOK | TxErr))
2743                         rtl8169_tx_interrupt(dev, tp, ioaddr);
2744 #endif
2745
2746                 boguscnt--;
2747         } while (boguscnt > 0);
2748
2749         if (boguscnt <= 0) {
2750                 if (netif_msg_intr(tp) && net_ratelimit() ) {
2751                         printk(KERN_WARNING
2752                                "%s: Too much work at interrupt!\n", dev->name);
2753                 }
2754                 /* Clear all interrupt sources. */
2755                 RTL_W16(IntrStatus, 0xffff);
2756         }
2757 out:
2758         return IRQ_RETVAL(handled);
2759 }
2760
2761 #ifdef CONFIG_R8169_NAPI
2762 static int rtl8169_poll(struct net_device *dev, int *budget)
2763 {
2764         unsigned int work_done, work_to_do = min(*budget, dev->quota);
2765         struct rtl8169_private *tp = netdev_priv(dev);
2766         void __iomem *ioaddr = tp->mmio_addr;
2767
2768         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2769         rtl8169_tx_interrupt(dev, tp, ioaddr);
2770
2771         *budget -= work_done;
2772         dev->quota -= work_done;
2773
2774         if (work_done < work_to_do) {
2775                 netif_rx_complete(dev);
2776                 tp->intr_mask = 0xffff;
2777                 /*
2778                  * 20040426: the barrier is not strictly required but the
2779                  * behavior of the irq handler could be less predictable
2780                  * without it. Btw, the lack of flush for the posted pci
2781                  * write is safe - FR
2782                  */
2783                 smp_wmb();
2784                 RTL_W16(IntrMask, tp->intr_event);
2785         }
2786
2787         return (work_done >= work_to_do);
2788 }
2789 #endif
2790
2791 static void rtl8169_down(struct net_device *dev)
2792 {
2793         struct rtl8169_private *tp = netdev_priv(dev);
2794         void __iomem *ioaddr = tp->mmio_addr;
2795         unsigned int poll_locked = 0;
2796         unsigned int intrmask;
2797
2798         rtl8169_delete_timer(dev);
2799
2800         netif_stop_queue(dev);
2801
2802 core_down:
2803         spin_lock_irq(&tp->lock);
2804
2805         rtl8169_asic_down(ioaddr);
2806
2807         /* Update the error counts. */
2808         tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2809         RTL_W32(RxMissed, 0);
2810
2811         spin_unlock_irq(&tp->lock);
2812
2813         synchronize_irq(dev->irq);
2814
2815         if (!poll_locked) {
2816                 netif_poll_disable(dev);
2817                 poll_locked++;
2818         }
2819
2820         /* Give a racing hard_start_xmit a few cycles to complete. */
2821         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
2822
2823         /*
2824          * And now for the 50k$ question: are IRQ disabled or not ?
2825          *
2826          * Two paths lead here:
2827          * 1) dev->close
2828          *    -> netif_running() is available to sync the current code and the
2829          *       IRQ handler. See rtl8169_interrupt for details.
2830          * 2) dev->change_mtu
2831          *    -> rtl8169_poll can not be issued again and re-enable the
2832          *       interruptions. Let's simply issue the IRQ down sequence again.
2833          *
2834          * No loop if hotpluged or major error (0xffff).
2835          */
2836         intrmask = RTL_R16(IntrMask);
2837         if (intrmask && (intrmask != 0xffff))
2838                 goto core_down;
2839
2840         rtl8169_tx_clear(tp);
2841
2842         rtl8169_rx_clear(tp);
2843 }
2844
2845 static int rtl8169_close(struct net_device *dev)
2846 {
2847         struct rtl8169_private *tp = netdev_priv(dev);
2848         struct pci_dev *pdev = tp->pci_dev;
2849
2850         rtl8169_down(dev);
2851
2852         free_irq(dev->irq, dev);
2853
2854         netif_poll_enable(dev);
2855
2856         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2857                             tp->RxPhyAddr);
2858         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2859                             tp->TxPhyAddr);
2860         tp->TxDescArray = NULL;
2861         tp->RxDescArray = NULL;
2862
2863         return 0;
2864 }
2865
2866 static void rtl_set_rx_mode(struct net_device *dev)
2867 {
2868         struct rtl8169_private *tp = netdev_priv(dev);
2869         void __iomem *ioaddr = tp->mmio_addr;
2870         unsigned long flags;
2871         u32 mc_filter[2];       /* Multicast hash filter */
2872         int rx_mode;
2873         u32 tmp = 0;
2874
2875         if (dev->flags & IFF_PROMISC) {
2876                 /* Unconditionally log net taps. */
2877                 if (netif_msg_link(tp)) {
2878                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2879                                dev->name);
2880                 }
2881                 rx_mode =
2882                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2883                     AcceptAllPhys;
2884                 mc_filter[1] = mc_filter[0] = 0xffffffff;
2885         } else if ((dev->mc_count > multicast_filter_limit)
2886                    || (dev->flags & IFF_ALLMULTI)) {
2887                 /* Too many to filter perfectly -- accept all multicasts. */
2888                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2889                 mc_filter[1] = mc_filter[0] = 0xffffffff;
2890         } else {
2891                 struct dev_mc_list *mclist;
2892                 unsigned int i;
2893
2894                 rx_mode = AcceptBroadcast | AcceptMyPhys;
2895                 mc_filter[1] = mc_filter[0] = 0;
2896                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2897                      i++, mclist = mclist->next) {
2898                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2899                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2900                         rx_mode |= AcceptMulticast;
2901                 }
2902         }
2903
2904         spin_lock_irqsave(&tp->lock, flags);
2905
2906         tmp = rtl8169_rx_config | rx_mode |
2907               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2908
2909         if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2910             (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2911             (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2912             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2913             (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2914                 mc_filter[0] = 0xffffffff;
2915                 mc_filter[1] = 0xffffffff;
2916         }
2917
2918         RTL_W32(RxConfig, tmp);
2919         RTL_W32(MAR0 + 0, mc_filter[0]);
2920         RTL_W32(MAR0 + 4, mc_filter[1]);
2921
2922         spin_unlock_irqrestore(&tp->lock, flags);
2923 }
2924
2925 /**
2926  *  rtl8169_get_stats - Get rtl8169 read/write statistics
2927  *  @dev: The Ethernet Device to get statistics for
2928  *
2929  *  Get TX/RX statistics for rtl8169
2930  */
2931 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2932 {
2933         struct rtl8169_private *tp = netdev_priv(dev);
2934         void __iomem *ioaddr = tp->mmio_addr;
2935         unsigned long flags;
2936
2937         if (netif_running(dev)) {
2938                 spin_lock_irqsave(&tp->lock, flags);
2939                 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2940                 RTL_W32(RxMissed, 0);
2941                 spin_unlock_irqrestore(&tp->lock, flags);
2942         }
2943
2944         return &tp->stats;
2945 }
2946
2947 #ifdef CONFIG_PM
2948
2949 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2950 {
2951         struct net_device *dev = pci_get_drvdata(pdev);
2952         struct rtl8169_private *tp = netdev_priv(dev);
2953         void __iomem *ioaddr = tp->mmio_addr;
2954
2955         if (!netif_running(dev))
2956                 goto out_pci_suspend;
2957
2958         netif_device_detach(dev);
2959         netif_stop_queue(dev);
2960
2961         spin_lock_irq(&tp->lock);
2962
2963         rtl8169_asic_down(ioaddr);
2964
2965         tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2966         RTL_W32(RxMissed, 0);
2967
2968         spin_unlock_irq(&tp->lock);
2969
2970 out_pci_suspend:
2971         pci_save_state(pdev);
2972         pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
2973         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2974
2975         return 0;
2976 }
2977
2978 static int rtl8169_resume(struct pci_dev *pdev)
2979 {
2980         struct net_device *dev = pci_get_drvdata(pdev);
2981
2982         pci_set_power_state(pdev, PCI_D0);
2983         pci_restore_state(pdev);
2984         pci_enable_wake(pdev, PCI_D0, 0);
2985
2986         if (!netif_running(dev))
2987                 goto out;
2988
2989         netif_device_attach(dev);
2990
2991         rtl8169_schedule_work(dev, rtl8169_reset_task);
2992 out:
2993         return 0;
2994 }
2995
2996 #endif /* CONFIG_PM */
2997
2998 static struct pci_driver rtl8169_pci_driver = {
2999         .name           = MODULENAME,
3000         .id_table       = rtl8169_pci_tbl,
3001         .probe          = rtl8169_init_one,
3002         .remove         = __devexit_p(rtl8169_remove_one),
3003 #ifdef CONFIG_PM
3004         .suspend        = rtl8169_suspend,
3005         .resume         = rtl8169_resume,
3006 #endif
3007 };
3008
3009 static int __init rtl8169_init_module(void)
3010 {
3011         return pci_register_driver(&rtl8169_pci_driver);
3012 }
3013
3014 static void __exit rtl8169_cleanup_module(void)
3015 {
3016         pci_unregister_driver(&rtl8169_pci_driver);
3017 }
3018
3019 module_init(rtl8169_init_module);
3020 module_exit(rtl8169_cleanup_module);