2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #ifdef CONFIG_R8169_NAPI
32 #define NAPI_SUFFIX "-NAPI"
34 #define NAPI_SUFFIX ""
37 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
38 #define MODULENAME "r8169"
39 #define PFX MODULENAME ": "
42 #define assert(expr) \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
47 #define dprintk(fmt, args...) \
48 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
50 #define assert(expr) do {} while (0)
51 #define dprintk(fmt, args...) do {} while (0)
52 #endif /* RTL8169_DEBUG */
54 #define R8169_MSG_DEFAULT \
55 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
57 #define TX_BUFFS_AVAIL(tp) \
58 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
60 #ifdef CONFIG_R8169_NAPI
61 #define rtl8169_rx_skb netif_receive_skb
62 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
63 #define rtl8169_rx_quota(count, quota) min(count, quota)
65 #define rtl8169_rx_skb netif_rx
66 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
67 #define rtl8169_rx_quota(count, quota) count
70 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
71 static const int max_interrupt_work = 20;
73 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
74 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
75 static const int multicast_filter_limit = 32;
77 /* MAC address length */
78 #define MAC_ADDR_LEN 6
80 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
81 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
83 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
84 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
85 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
86 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
88 #define R8169_REGS_SIZE 256
89 #define R8169_NAPI_WEIGHT 64
90 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
91 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
92 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
93 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
94 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
96 #define RTL8169_TX_TIMEOUT (6*HZ)
97 #define RTL8169_PHY_TIMEOUT (10*HZ)
99 /* write/read MMIO register */
100 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
101 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
102 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
103 #define RTL_R8(reg) readb (ioaddr + (reg))
104 #define RTL_R16(reg) readw (ioaddr + (reg))
105 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
108 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
109 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
110 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
111 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
112 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
113 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
114 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
115 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
116 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
117 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
118 RTL_GIGA_MAC_VER_15 = 0x0f // 8101
122 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
123 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
124 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
125 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
126 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
127 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
130 #define _R(NAME,MAC,MASK) \
131 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
133 static const struct {
136 u32 RxConfigMask; /* Clears the bits supported by this chip */
137 } rtl_chip_info[] = {
138 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
139 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
140 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
141 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
142 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
143 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
145 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
146 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
147 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
148 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
158 static void rtl_hw_start_8169(struct net_device *);
159 static void rtl_hw_start_8168(struct net_device *);
160 static void rtl_hw_start_8101(struct net_device *);
162 static struct pci_device_id rtl8169_pci_tbl[] = {
163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
167 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
168 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
169 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
170 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
171 { PCI_VENDOR_ID_LINKSYS, 0x1032,
172 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
176 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
178 static int rx_copybreak = 200;
185 MAC0 = 0, /* Ethernet hardware address. */
187 MAR0 = 8, /* Multicast filter. */
188 CounterAddrLow = 0x10,
189 CounterAddrHigh = 0x14,
190 TxDescStartAddrLow = 0x20,
191 TxDescStartAddrHigh = 0x24,
192 TxHDescStartAddrLow = 0x28,
193 TxHDescStartAddrHigh = 0x2c,
219 RxDescAddrLow = 0xe4,
220 RxDescAddrHigh = 0xe8,
223 FuncEventMask = 0xf4,
224 FuncPresetState = 0xf8,
225 FuncForceEvent = 0xfc,
228 enum rtl_register_content {
229 /* InterruptStatusBits */
233 TxDescUnavail = 0x0080,
255 /* TXPoll register p.5 */
256 HPQ = 0x80, /* Poll cmd on the high prio queue */
257 NPQ = 0x40, /* Poll cmd on the low prio queue */
258 FSWInt = 0x01, /* Forced software interrupt */
262 Cfg9346_Unlock = 0xc0,
267 AcceptBroadcast = 0x08,
268 AcceptMulticast = 0x04,
270 AcceptAllPhys = 0x01,
277 TxInterFrameGapShift = 24,
278 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
280 /* Config1 register p.24 */
281 PMEnable = (1 << 0), /* Power Management Enable */
283 /* Config2 register p. 25 */
284 PCI_Clock_66MHz = 0x01,
285 PCI_Clock_33MHz = 0x00,
287 /* Config3 register p.25 */
288 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
289 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
291 /* Config5 register p.27 */
292 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
293 MWF = (1 << 5), /* Accept Multicast wakeup frame */
294 UWF = (1 << 4), /* Accept Unicast wakeup frame */
295 LanWake = (1 << 1), /* LanWake enable/disable */
296 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
299 TBIReset = 0x80000000,
300 TBILoopback = 0x40000000,
301 TBINwEnable = 0x20000000,
302 TBINwRestart = 0x10000000,
303 TBILinkOk = 0x02000000,
304 TBINwComplete = 0x01000000,
307 PktCntrDisable = (1 << 7), // 8168
312 INTT_0 = 0x0000, // 8168
313 INTT_1 = 0x0001, // 8168
314 INTT_2 = 0x0002, // 8168
315 INTT_3 = 0x0003, // 8168
317 /* rtl8169_PHYstatus */
328 TBILinkOK = 0x02000000,
330 /* DumpCounterCommand */
334 enum desc_status_bit {
335 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
336 RingEnd = (1 << 30), /* End of descriptor ring */
337 FirstFrag = (1 << 29), /* First segment of a packet */
338 LastFrag = (1 << 28), /* Final segment of a packet */
341 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
342 MSSShift = 16, /* MSS value position */
343 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
344 IPCS = (1 << 18), /* Calculate IP checksum */
345 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
346 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
347 TxVlanTag = (1 << 17), /* Add VLAN tag */
350 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
351 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
353 #define RxProtoUDP (PID1)
354 #define RxProtoTCP (PID0)
355 #define RxProtoIP (PID1 | PID0)
356 #define RxProtoMask RxProtoIP
358 IPFail = (1 << 16), /* IP checksum failed */
359 UDPFail = (1 << 15), /* UDP/IP checksum failed */
360 TCPFail = (1 << 14), /* TCP/IP checksum failed */
361 RxVlanTag = (1 << 16), /* VLAN tag available */
364 #define RsvdMask 0x3fffc000
381 u8 __pad[sizeof(void *) - sizeof(u32)];
385 RTL_FEATURE_WOL = (1 << 0),
388 struct rtl8169_private {
389 void __iomem *mmio_addr; /* memory map physical address */
390 struct pci_dev *pci_dev; /* Index of PCI device */
391 struct net_device *dev;
392 struct napi_struct napi;
393 struct net_device_stats stats; /* statistics of net device */
394 spinlock_t lock; /* spin lock flag */
399 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
400 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
403 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
404 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
405 dma_addr_t TxPhyAddr;
406 dma_addr_t RxPhyAddr;
407 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
408 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
411 struct timer_list timer;
416 int phy_auto_nego_reg;
417 int phy_1000_ctrl_reg;
418 #ifdef CONFIG_R8169_VLAN
419 struct vlan_group *vlgrp;
421 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
422 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
423 void (*phy_reset_enable)(void __iomem *);
424 void (*hw_start)(struct net_device *);
425 unsigned int (*phy_reset_pending)(void __iomem *);
426 unsigned int (*link_ok)(void __iomem *);
427 struct delayed_work task;
431 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
432 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
433 module_param(rx_copybreak, int, 0);
434 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
435 module_param(use_dac, int, 0);
436 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
437 module_param_named(debug, debug.msg_enable, int, 0);
438 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
439 MODULE_LICENSE("GPL");
440 MODULE_VERSION(RTL8169_VERSION);
442 static int rtl8169_open(struct net_device *dev);
443 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
444 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
445 static int rtl8169_init_ring(struct net_device *dev);
446 static void rtl_hw_start(struct net_device *dev);
447 static int rtl8169_close(struct net_device *dev);
448 static void rtl_set_rx_mode(struct net_device *dev);
449 static void rtl8169_tx_timeout(struct net_device *dev);
450 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
451 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
452 void __iomem *, u32 budget);
453 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
454 static void rtl8169_down(struct net_device *dev);
455 static void rtl8169_rx_clear(struct rtl8169_private *tp);
457 #ifdef CONFIG_R8169_NAPI
458 static int rtl8169_poll(struct napi_struct *napi, int budget);
461 static const unsigned int rtl8169_rx_config =
462 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
464 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
468 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
470 for (i = 20; i > 0; i--) {
472 * Check if the RTL8169 has completed writing to the specified
475 if (!(RTL_R32(PHYAR) & 0x80000000))
481 static int mdio_read(void __iomem *ioaddr, int reg_addr)
485 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
487 for (i = 20; i > 0; i--) {
489 * Check if the RTL8169 has completed retrieving data from
490 * the specified MII register.
492 if (RTL_R32(PHYAR) & 0x80000000) {
493 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
501 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
503 RTL_W16(IntrMask, 0x0000);
505 RTL_W16(IntrStatus, 0xffff);
508 static void rtl8169_asic_down(void __iomem *ioaddr)
510 RTL_W8(ChipCmd, 0x00);
511 rtl8169_irq_mask_and_ack(ioaddr);
515 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
517 return RTL_R32(TBICSR) & TBIReset;
520 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
522 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
525 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
527 return RTL_R32(TBICSR) & TBILinkOk;
530 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
532 return RTL_R8(PHYstatus) & LinkStatus;
535 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
537 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
540 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
544 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
545 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
548 static void rtl8169_check_link_status(struct net_device *dev,
549 struct rtl8169_private *tp,
550 void __iomem *ioaddr)
554 spin_lock_irqsave(&tp->lock, flags);
555 if (tp->link_ok(ioaddr)) {
556 netif_carrier_on(dev);
557 if (netif_msg_ifup(tp))
558 printk(KERN_INFO PFX "%s: link up\n", dev->name);
560 if (netif_msg_ifdown(tp))
561 printk(KERN_INFO PFX "%s: link down\n", dev->name);
562 netif_carrier_off(dev);
564 spin_unlock_irqrestore(&tp->lock, flags);
567 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
569 struct rtl8169_private *tp = netdev_priv(dev);
570 void __iomem *ioaddr = tp->mmio_addr;
575 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
576 wol->supported = WAKE_ANY;
578 spin_lock_irq(&tp->lock);
580 options = RTL_R8(Config1);
581 if (!(options & PMEnable))
584 options = RTL_R8(Config3);
585 if (options & LinkUp)
586 wol->wolopts |= WAKE_PHY;
587 if (options & MagicPacket)
588 wol->wolopts |= WAKE_MAGIC;
590 options = RTL_R8(Config5);
592 wol->wolopts |= WAKE_UCAST;
594 wol->wolopts |= WAKE_BCAST;
596 wol->wolopts |= WAKE_MCAST;
599 spin_unlock_irq(&tp->lock);
602 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
604 struct rtl8169_private *tp = netdev_priv(dev);
605 void __iomem *ioaddr = tp->mmio_addr;
612 { WAKE_ANY, Config1, PMEnable },
613 { WAKE_PHY, Config3, LinkUp },
614 { WAKE_MAGIC, Config3, MagicPacket },
615 { WAKE_UCAST, Config5, UWF },
616 { WAKE_BCAST, Config5, BWF },
617 { WAKE_MCAST, Config5, MWF },
618 { WAKE_ANY, Config5, LanWake }
621 spin_lock_irq(&tp->lock);
623 RTL_W8(Cfg9346, Cfg9346_Unlock);
625 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
626 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
627 if (wol->wolopts & cfg[i].opt)
628 options |= cfg[i].mask;
629 RTL_W8(cfg[i].reg, options);
632 RTL_W8(Cfg9346, Cfg9346_Lock);
635 tp->features |= RTL_FEATURE_WOL;
637 tp->features &= ~RTL_FEATURE_WOL;
639 spin_unlock_irq(&tp->lock);
644 static void rtl8169_get_drvinfo(struct net_device *dev,
645 struct ethtool_drvinfo *info)
647 struct rtl8169_private *tp = netdev_priv(dev);
649 strcpy(info->driver, MODULENAME);
650 strcpy(info->version, RTL8169_VERSION);
651 strcpy(info->bus_info, pci_name(tp->pci_dev));
654 static int rtl8169_get_regs_len(struct net_device *dev)
656 return R8169_REGS_SIZE;
659 static int rtl8169_set_speed_tbi(struct net_device *dev,
660 u8 autoneg, u16 speed, u8 duplex)
662 struct rtl8169_private *tp = netdev_priv(dev);
663 void __iomem *ioaddr = tp->mmio_addr;
667 reg = RTL_R32(TBICSR);
668 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
669 (duplex == DUPLEX_FULL)) {
670 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
671 } else if (autoneg == AUTONEG_ENABLE)
672 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
674 if (netif_msg_link(tp)) {
675 printk(KERN_WARNING "%s: "
676 "incorrect speed setting refused in TBI mode\n",
685 static int rtl8169_set_speed_xmii(struct net_device *dev,
686 u8 autoneg, u16 speed, u8 duplex)
688 struct rtl8169_private *tp = netdev_priv(dev);
689 void __iomem *ioaddr = tp->mmio_addr;
690 int auto_nego, giga_ctrl;
692 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
693 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
694 ADVERTISE_100HALF | ADVERTISE_100FULL);
695 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
696 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
698 if (autoneg == AUTONEG_ENABLE) {
699 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
700 ADVERTISE_100HALF | ADVERTISE_100FULL);
701 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
703 if (speed == SPEED_10)
704 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
705 else if (speed == SPEED_100)
706 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
707 else if (speed == SPEED_1000)
708 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
710 if (duplex == DUPLEX_HALF)
711 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
713 if (duplex == DUPLEX_FULL)
714 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
716 /* This tweak comes straight from Realtek's driver. */
717 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
718 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
719 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
723 /* The 8100e/8101e do Fast Ethernet only. */
724 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
725 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
726 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
727 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
728 netif_msg_link(tp)) {
729 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
732 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
735 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
737 if (tp->mac_version == RTL_GIGA_MAC_VER_12) {
738 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
739 mdio_write(ioaddr, 0x1f, 0x0000);
740 mdio_write(ioaddr, 0x0e, 0x0000);
743 tp->phy_auto_nego_reg = auto_nego;
744 tp->phy_1000_ctrl_reg = giga_ctrl;
746 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
747 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
748 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
752 static int rtl8169_set_speed(struct net_device *dev,
753 u8 autoneg, u16 speed, u8 duplex)
755 struct rtl8169_private *tp = netdev_priv(dev);
758 ret = tp->set_speed(dev, autoneg, speed, duplex);
760 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
761 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
766 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
768 struct rtl8169_private *tp = netdev_priv(dev);
772 spin_lock_irqsave(&tp->lock, flags);
773 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
774 spin_unlock_irqrestore(&tp->lock, flags);
779 static u32 rtl8169_get_rx_csum(struct net_device *dev)
781 struct rtl8169_private *tp = netdev_priv(dev);
783 return tp->cp_cmd & RxChkSum;
786 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
788 struct rtl8169_private *tp = netdev_priv(dev);
789 void __iomem *ioaddr = tp->mmio_addr;
792 spin_lock_irqsave(&tp->lock, flags);
795 tp->cp_cmd |= RxChkSum;
797 tp->cp_cmd &= ~RxChkSum;
799 RTL_W16(CPlusCmd, tp->cp_cmd);
802 spin_unlock_irqrestore(&tp->lock, flags);
807 #ifdef CONFIG_R8169_VLAN
809 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
812 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
813 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
816 static void rtl8169_vlan_rx_register(struct net_device *dev,
817 struct vlan_group *grp)
819 struct rtl8169_private *tp = netdev_priv(dev);
820 void __iomem *ioaddr = tp->mmio_addr;
823 spin_lock_irqsave(&tp->lock, flags);
826 tp->cp_cmd |= RxVlan;
828 tp->cp_cmd &= ~RxVlan;
829 RTL_W16(CPlusCmd, tp->cp_cmd);
831 spin_unlock_irqrestore(&tp->lock, flags);
834 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
837 u32 opts2 = le32_to_cpu(desc->opts2);
840 if (tp->vlgrp && (opts2 & RxVlanTag)) {
841 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
849 #else /* !CONFIG_R8169_VLAN */
851 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
857 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
865 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
867 struct rtl8169_private *tp = netdev_priv(dev);
868 void __iomem *ioaddr = tp->mmio_addr;
872 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
873 cmd->port = PORT_FIBRE;
874 cmd->transceiver = XCVR_INTERNAL;
876 status = RTL_R32(TBICSR);
877 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
878 cmd->autoneg = !!(status & TBINwEnable);
880 cmd->speed = SPEED_1000;
881 cmd->duplex = DUPLEX_FULL; /* Always set */
884 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
886 struct rtl8169_private *tp = netdev_priv(dev);
887 void __iomem *ioaddr = tp->mmio_addr;
890 cmd->supported = SUPPORTED_10baseT_Half |
891 SUPPORTED_10baseT_Full |
892 SUPPORTED_100baseT_Half |
893 SUPPORTED_100baseT_Full |
894 SUPPORTED_1000baseT_Full |
899 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
901 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
902 cmd->advertising |= ADVERTISED_10baseT_Half;
903 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
904 cmd->advertising |= ADVERTISED_10baseT_Full;
905 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
906 cmd->advertising |= ADVERTISED_100baseT_Half;
907 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
908 cmd->advertising |= ADVERTISED_100baseT_Full;
909 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
910 cmd->advertising |= ADVERTISED_1000baseT_Full;
912 status = RTL_R8(PHYstatus);
914 if (status & _1000bpsF)
915 cmd->speed = SPEED_1000;
916 else if (status & _100bps)
917 cmd->speed = SPEED_100;
918 else if (status & _10bps)
919 cmd->speed = SPEED_10;
921 if (status & TxFlowCtrl)
922 cmd->advertising |= ADVERTISED_Asym_Pause;
923 if (status & RxFlowCtrl)
924 cmd->advertising |= ADVERTISED_Pause;
926 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
927 DUPLEX_FULL : DUPLEX_HALF;
930 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
932 struct rtl8169_private *tp = netdev_priv(dev);
935 spin_lock_irqsave(&tp->lock, flags);
937 tp->get_settings(dev, cmd);
939 spin_unlock_irqrestore(&tp->lock, flags);
943 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
946 struct rtl8169_private *tp = netdev_priv(dev);
949 if (regs->len > R8169_REGS_SIZE)
950 regs->len = R8169_REGS_SIZE;
952 spin_lock_irqsave(&tp->lock, flags);
953 memcpy_fromio(p, tp->mmio_addr, regs->len);
954 spin_unlock_irqrestore(&tp->lock, flags);
957 static u32 rtl8169_get_msglevel(struct net_device *dev)
959 struct rtl8169_private *tp = netdev_priv(dev);
961 return tp->msg_enable;
964 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
966 struct rtl8169_private *tp = netdev_priv(dev);
968 tp->msg_enable = value;
971 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
978 "tx_single_collisions",
979 "tx_multi_collisions",
987 struct rtl8169_counters {
994 __le32 tx_one_collision;
995 __le32 tx_multi_collision;
1003 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1007 return ARRAY_SIZE(rtl8169_gstrings);
1013 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1014 struct ethtool_stats *stats, u64 *data)
1016 struct rtl8169_private *tp = netdev_priv(dev);
1017 void __iomem *ioaddr = tp->mmio_addr;
1018 struct rtl8169_counters *counters;
1024 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1028 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1029 cmd = (u64)paddr & DMA_32BIT_MASK;
1030 RTL_W32(CounterAddrLow, cmd);
1031 RTL_W32(CounterAddrLow, cmd | CounterDump);
1033 while (RTL_R32(CounterAddrLow) & CounterDump) {
1034 if (msleep_interruptible(1))
1038 RTL_W32(CounterAddrLow, 0);
1039 RTL_W32(CounterAddrHigh, 0);
1041 data[0] = le64_to_cpu(counters->tx_packets);
1042 data[1] = le64_to_cpu(counters->rx_packets);
1043 data[2] = le64_to_cpu(counters->tx_errors);
1044 data[3] = le32_to_cpu(counters->rx_errors);
1045 data[4] = le16_to_cpu(counters->rx_missed);
1046 data[5] = le16_to_cpu(counters->align_errors);
1047 data[6] = le32_to_cpu(counters->tx_one_collision);
1048 data[7] = le32_to_cpu(counters->tx_multi_collision);
1049 data[8] = le64_to_cpu(counters->rx_unicast);
1050 data[9] = le64_to_cpu(counters->rx_broadcast);
1051 data[10] = le32_to_cpu(counters->rx_multicast);
1052 data[11] = le16_to_cpu(counters->tx_aborted);
1053 data[12] = le16_to_cpu(counters->tx_underun);
1055 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1058 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1062 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1067 static const struct ethtool_ops rtl8169_ethtool_ops = {
1068 .get_drvinfo = rtl8169_get_drvinfo,
1069 .get_regs_len = rtl8169_get_regs_len,
1070 .get_link = ethtool_op_get_link,
1071 .get_settings = rtl8169_get_settings,
1072 .set_settings = rtl8169_set_settings,
1073 .get_msglevel = rtl8169_get_msglevel,
1074 .set_msglevel = rtl8169_set_msglevel,
1075 .get_rx_csum = rtl8169_get_rx_csum,
1076 .set_rx_csum = rtl8169_set_rx_csum,
1077 .set_tx_csum = ethtool_op_set_tx_csum,
1078 .set_sg = ethtool_op_set_sg,
1079 .set_tso = ethtool_op_set_tso,
1080 .get_regs = rtl8169_get_regs,
1081 .get_wol = rtl8169_get_wol,
1082 .set_wol = rtl8169_set_wol,
1083 .get_strings = rtl8169_get_strings,
1084 .get_sset_count = rtl8169_get_sset_count,
1085 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1088 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1089 int bitnum, int bitval)
1093 val = mdio_read(ioaddr, reg);
1094 val = (bitval == 1) ?
1095 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1096 mdio_write(ioaddr, reg, val & 0xffff);
1099 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1100 void __iomem *ioaddr)
1103 * The driver currently handles the 8168Bf and the 8168Be identically
1104 * but they can be identified more specifically through the test below
1107 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1109 * Same thing for the 8101Eb and the 8101Ec:
1111 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1117 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1118 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1119 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1120 { 0x30800000, RTL_GIGA_MAC_VER_14 },
1121 { 0x30000000, RTL_GIGA_MAC_VER_11 },
1122 { 0x98000000, RTL_GIGA_MAC_VER_06 },
1123 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1124 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1125 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1126 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1127 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1131 reg = RTL_R32(TxConfig) & 0xfc800000;
1132 while ((reg & p->mask) != p->mask)
1134 tp->mac_version = p->mac_version;
1137 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1139 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1142 static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1143 void __iomem *ioaddr)
1150 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1151 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1152 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1153 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1157 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1158 while ((reg & p->mask) != p->set)
1160 tp->phy_version = p->phy_version;
1163 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1170 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1171 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1172 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1173 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1177 for (p = phy_print; p->msg; p++) {
1178 if (tp->phy_version == p->version) {
1179 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1183 dprintk("phy_version == Unknown\n");
1186 static void rtl8169_hw_phy_config(struct net_device *dev)
1188 struct rtl8169_private *tp = netdev_priv(dev);
1189 void __iomem *ioaddr = tp->mmio_addr;
1191 u16 regs[5]; /* Beware of bit-sign propagation */
1192 } phy_magic[5] = { {
1193 { 0x0000, //w 4 15 12 0
1194 0x00a1, //w 3 15 0 00a1
1195 0x0008, //w 2 15 0 0008
1196 0x1020, //w 1 15 0 1020
1197 0x1000 } },{ //w 0 15 0 1000
1198 { 0x7000, //w 4 15 12 7
1199 0xff41, //w 3 15 0 ff41
1200 0xde60, //w 2 15 0 de60
1201 0x0140, //w 1 15 0 0140
1202 0x0077 } },{ //w 0 15 0 0077
1203 { 0xa000, //w 4 15 12 a
1204 0xdf01, //w 3 15 0 df01
1205 0xdf20, //w 2 15 0 df20
1206 0xff95, //w 1 15 0 ff95
1207 0xfa00 } },{ //w 0 15 0 fa00
1208 { 0xb000, //w 4 15 12 b
1209 0xff41, //w 3 15 0 ff41
1210 0xde20, //w 2 15 0 de20
1211 0x0140, //w 1 15 0 0140
1212 0x00bb } },{ //w 0 15 0 00bb
1213 { 0xf000, //w 4 15 12 f
1214 0xdf01, //w 3 15 0 df01
1215 0xdf20, //w 2 15 0 df20
1216 0xff95, //w 1 15 0 ff95
1217 0xbf00 } //w 0 15 0 bf00
1222 rtl8169_print_mac_version(tp);
1223 rtl8169_print_phy_version(tp);
1225 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1227 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1230 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1231 dprintk("Do final_reg2.cfg\n");
1235 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1236 mdio_write(ioaddr, 31, 0x0002);
1237 mdio_write(ioaddr, 1, 0x90d0);
1238 mdio_write(ioaddr, 31, 0x0000);
1242 if ((tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1243 (tp->mac_version != RTL_GIGA_MAC_VER_03))
1246 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1247 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1248 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1249 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1251 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1254 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1255 mdio_write(ioaddr, pos, val);
1257 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1258 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1259 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1261 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1264 static void rtl8169_phy_timer(unsigned long __opaque)
1266 struct net_device *dev = (struct net_device *)__opaque;
1267 struct rtl8169_private *tp = netdev_priv(dev);
1268 struct timer_list *timer = &tp->timer;
1269 void __iomem *ioaddr = tp->mmio_addr;
1270 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1272 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1273 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1275 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1278 spin_lock_irq(&tp->lock);
1280 if (tp->phy_reset_pending(ioaddr)) {
1282 * A busy loop could burn quite a few cycles on nowadays CPU.
1283 * Let's delay the execution of the timer for a few ticks.
1289 if (tp->link_ok(ioaddr))
1292 if (netif_msg_link(tp))
1293 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1295 tp->phy_reset_enable(ioaddr);
1298 mod_timer(timer, jiffies + timeout);
1300 spin_unlock_irq(&tp->lock);
1303 static inline void rtl8169_delete_timer(struct net_device *dev)
1305 struct rtl8169_private *tp = netdev_priv(dev);
1306 struct timer_list *timer = &tp->timer;
1308 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1309 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1312 del_timer_sync(timer);
1315 static inline void rtl8169_request_timer(struct net_device *dev)
1317 struct rtl8169_private *tp = netdev_priv(dev);
1318 struct timer_list *timer = &tp->timer;
1320 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1321 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1324 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1327 #ifdef CONFIG_NET_POLL_CONTROLLER
1329 * Polling 'interrupt' - used by things like netconsole to send skbs
1330 * without having to re-enable interrupts. It's not called while
1331 * the interrupt routine is executing.
1333 static void rtl8169_netpoll(struct net_device *dev)
1335 struct rtl8169_private *tp = netdev_priv(dev);
1336 struct pci_dev *pdev = tp->pci_dev;
1338 disable_irq(pdev->irq);
1339 rtl8169_interrupt(pdev->irq, dev);
1340 enable_irq(pdev->irq);
1344 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1345 void __iomem *ioaddr)
1348 pci_release_regions(pdev);
1349 pci_disable_device(pdev);
1353 static void rtl8169_phy_reset(struct net_device *dev,
1354 struct rtl8169_private *tp)
1356 void __iomem *ioaddr = tp->mmio_addr;
1359 tp->phy_reset_enable(ioaddr);
1360 for (i = 0; i < 100; i++) {
1361 if (!tp->phy_reset_pending(ioaddr))
1365 if (netif_msg_link(tp))
1366 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1369 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1371 void __iomem *ioaddr = tp->mmio_addr;
1373 rtl8169_hw_phy_config(dev);
1375 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1378 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1380 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1381 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1383 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1384 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1386 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1387 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1390 rtl8169_phy_reset(dev, tp);
1393 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1394 * only 8101. Don't panic.
1396 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1398 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1399 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1402 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1404 void __iomem *ioaddr = tp->mmio_addr;
1408 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1409 high = addr[4] | (addr[5] << 8);
1411 spin_lock_irq(&tp->lock);
1413 RTL_W8(Cfg9346, Cfg9346_Unlock);
1415 RTL_W32(MAC4, high);
1416 RTL_W8(Cfg9346, Cfg9346_Lock);
1418 spin_unlock_irq(&tp->lock);
1421 static int rtl_set_mac_address(struct net_device *dev, void *p)
1423 struct rtl8169_private *tp = netdev_priv(dev);
1424 struct sockaddr *addr = p;
1426 if (!is_valid_ether_addr(addr->sa_data))
1427 return -EADDRNOTAVAIL;
1429 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1431 rtl_rar_set(tp, dev->dev_addr);
1436 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1438 struct rtl8169_private *tp = netdev_priv(dev);
1439 struct mii_ioctl_data *data = if_mii(ifr);
1441 if (!netif_running(dev))
1446 data->phy_id = 32; /* Internal PHY */
1450 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1454 if (!capable(CAP_NET_ADMIN))
1456 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1462 static const struct rtl_cfg_info {
1463 void (*hw_start)(struct net_device *);
1464 unsigned int region;
1468 } rtl_cfg_infos [] = {
1470 .hw_start = rtl_hw_start_8169,
1473 .intr_event = SYSErr | LinkChg | RxOverflow |
1474 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1475 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1478 .hw_start = rtl_hw_start_8168,
1481 .intr_event = SYSErr | LinkChg | RxOverflow |
1482 TxErr | TxOK | RxOK | RxErr,
1483 .napi_event = TxErr | TxOK | RxOK | RxOverflow
1486 .hw_start = rtl_hw_start_8101,
1489 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1490 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1491 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1495 static int __devinit
1496 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1498 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1499 const unsigned int region = cfg->region;
1500 struct rtl8169_private *tp;
1501 struct net_device *dev;
1502 void __iomem *ioaddr;
1506 if (netif_msg_drv(&debug)) {
1507 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1508 MODULENAME, RTL8169_VERSION);
1511 dev = alloc_etherdev(sizeof (*tp));
1513 if (netif_msg_drv(&debug))
1514 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1519 SET_NETDEV_DEV(dev, &pdev->dev);
1520 tp = netdev_priv(dev);
1522 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1524 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1525 rc = pci_enable_device(pdev);
1527 if (netif_msg_probe(tp))
1528 dev_err(&pdev->dev, "enable failure\n");
1529 goto err_out_free_dev_1;
1532 rc = pci_set_mwi(pdev);
1534 goto err_out_disable_2;
1536 /* make sure PCI base addr 1 is MMIO */
1537 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1538 if (netif_msg_probe(tp)) {
1540 "region #%d not an MMIO resource, aborting\n",
1547 /* check for weird/broken PCI region reporting */
1548 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1549 if (netif_msg_probe(tp)) {
1551 "Invalid PCI region size(s), aborting\n");
1557 rc = pci_request_regions(pdev, MODULENAME);
1559 if (netif_msg_probe(tp))
1560 dev_err(&pdev->dev, "could not request regions.\n");
1564 tp->cp_cmd = PCIMulRW | RxChkSum;
1566 if ((sizeof(dma_addr_t) > 4) &&
1567 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1568 tp->cp_cmd |= PCIDAC;
1569 dev->features |= NETIF_F_HIGHDMA;
1571 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1573 if (netif_msg_probe(tp)) {
1575 "DMA configuration failed.\n");
1577 goto err_out_free_res_4;
1581 pci_set_master(pdev);
1583 /* ioremap MMIO region */
1584 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1586 if (netif_msg_probe(tp))
1587 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1589 goto err_out_free_res_4;
1592 /* Unneeded ? Don't mess with Mrs. Murphy. */
1593 rtl8169_irq_mask_and_ack(ioaddr);
1595 /* Soft reset the chip. */
1596 RTL_W8(ChipCmd, CmdReset);
1598 /* Check that the chip has finished the reset. */
1599 for (i = 0; i < 100; i++) {
1600 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1602 msleep_interruptible(1);
1605 /* Identify chip attached to board */
1606 rtl8169_get_mac_version(tp, ioaddr);
1607 rtl8169_get_phy_version(tp, ioaddr);
1609 rtl8169_print_mac_version(tp);
1610 rtl8169_print_phy_version(tp);
1612 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1613 if (tp->mac_version == rtl_chip_info[i].mac_version)
1617 /* Unknown chip: assume array element #0, original RTL-8169 */
1618 if (netif_msg_probe(tp)) {
1619 dev_printk(KERN_DEBUG, &pdev->dev,
1620 "unknown chip version, assuming %s\n",
1621 rtl_chip_info[0].name);
1627 RTL_W8(Cfg9346, Cfg9346_Unlock);
1628 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1629 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1630 RTL_W8(Cfg9346, Cfg9346_Lock);
1632 if (RTL_R8(PHYstatus) & TBI_Enable) {
1633 tp->set_speed = rtl8169_set_speed_tbi;
1634 tp->get_settings = rtl8169_gset_tbi;
1635 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1636 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1637 tp->link_ok = rtl8169_tbi_link_ok;
1639 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1641 tp->set_speed = rtl8169_set_speed_xmii;
1642 tp->get_settings = rtl8169_gset_xmii;
1643 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1644 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1645 tp->link_ok = rtl8169_xmii_link_ok;
1647 dev->do_ioctl = rtl8169_ioctl;
1650 /* Get MAC address. FIXME: read EEPROM */
1651 for (i = 0; i < MAC_ADDR_LEN; i++)
1652 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1653 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1655 dev->open = rtl8169_open;
1656 dev->hard_start_xmit = rtl8169_start_xmit;
1657 dev->get_stats = rtl8169_get_stats;
1658 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1659 dev->stop = rtl8169_close;
1660 dev->tx_timeout = rtl8169_tx_timeout;
1661 dev->set_multicast_list = rtl_set_rx_mode;
1662 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1663 dev->irq = pdev->irq;
1664 dev->base_addr = (unsigned long) ioaddr;
1665 dev->change_mtu = rtl8169_change_mtu;
1666 dev->set_mac_address = rtl_set_mac_address;
1668 #ifdef CONFIG_R8169_NAPI
1669 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1672 #ifdef CONFIG_R8169_VLAN
1673 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1674 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1677 #ifdef CONFIG_NET_POLL_CONTROLLER
1678 dev->poll_controller = rtl8169_netpoll;
1681 tp->intr_mask = 0xffff;
1683 tp->mmio_addr = ioaddr;
1684 tp->align = cfg->align;
1685 tp->hw_start = cfg->hw_start;
1686 tp->intr_event = cfg->intr_event;
1687 tp->napi_event = cfg->napi_event;
1689 init_timer(&tp->timer);
1690 tp->timer.data = (unsigned long) dev;
1691 tp->timer.function = rtl8169_phy_timer;
1693 spin_lock_init(&tp->lock);
1695 rc = register_netdev(dev);
1697 goto err_out_unmap_5;
1699 pci_set_drvdata(pdev, dev);
1701 if (netif_msg_probe(tp)) {
1702 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1704 printk(KERN_INFO "%s: %s at 0x%lx, "
1705 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1706 "XID %08x IRQ %d\n",
1708 rtl_chip_info[tp->chipset].name,
1710 dev->dev_addr[0], dev->dev_addr[1],
1711 dev->dev_addr[2], dev->dev_addr[3],
1712 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1715 rtl8169_init_phy(dev, tp);
1723 pci_release_regions(pdev);
1725 pci_clear_mwi(pdev);
1727 pci_disable_device(pdev);
1733 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1735 struct net_device *dev = pci_get_drvdata(pdev);
1736 struct rtl8169_private *tp = netdev_priv(dev);
1738 flush_scheduled_work();
1740 unregister_netdev(dev);
1741 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1742 pci_set_drvdata(pdev, NULL);
1745 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1746 struct net_device *dev)
1748 unsigned int mtu = dev->mtu;
1750 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1753 static int rtl8169_open(struct net_device *dev)
1755 struct rtl8169_private *tp = netdev_priv(dev);
1756 struct pci_dev *pdev = tp->pci_dev;
1757 int retval = -ENOMEM;
1760 rtl8169_set_rxbufsize(tp, dev);
1763 * Rx and Tx desscriptors needs 256 bytes alignment.
1764 * pci_alloc_consistent provides more.
1766 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1768 if (!tp->TxDescArray)
1771 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1773 if (!tp->RxDescArray)
1776 retval = rtl8169_init_ring(dev);
1780 INIT_DELAYED_WORK(&tp->task, NULL);
1784 retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1787 goto err_release_ring_2;
1789 #ifdef CONFIG_R8169_NAPI
1790 napi_enable(&tp->napi);
1795 rtl8169_request_timer(dev);
1797 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1802 rtl8169_rx_clear(tp);
1804 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1807 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1812 static void rtl8169_hw_reset(void __iomem *ioaddr)
1814 /* Disable interrupts */
1815 rtl8169_irq_mask_and_ack(ioaddr);
1817 /* Reset the chipset */
1818 RTL_W8(ChipCmd, CmdReset);
1824 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1826 void __iomem *ioaddr = tp->mmio_addr;
1827 u32 cfg = rtl8169_rx_config;
1829 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1830 RTL_W32(RxConfig, cfg);
1832 /* Set DMA burst size and Interframe Gap Time */
1833 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1834 (InterFrameGap << TxInterFrameGapShift));
1837 static void rtl_hw_start(struct net_device *dev)
1839 struct rtl8169_private *tp = netdev_priv(dev);
1840 void __iomem *ioaddr = tp->mmio_addr;
1843 /* Soft reset the chip. */
1844 RTL_W8(ChipCmd, CmdReset);
1846 /* Check that the chip has finished the reset. */
1847 for (i = 0; i < 100; i++) {
1848 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1850 msleep_interruptible(1);
1855 netif_start_queue(dev);
1859 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1860 void __iomem *ioaddr)
1863 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1864 * register to be written before TxDescAddrLow to work.
1865 * Switching from MMIO to I/O access fixes the issue as well.
1867 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1868 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1869 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1870 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1873 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1877 cmd = RTL_R16(CPlusCmd);
1878 RTL_W16(CPlusCmd, cmd);
1882 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1884 /* Low hurts. Let's disable the filtering. */
1885 RTL_W16(RxMaxSize, 16383);
1888 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1895 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1896 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1897 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1898 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1903 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1904 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1905 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1906 RTL_W32(0x7c, p->val);
1912 static void rtl_hw_start_8169(struct net_device *dev)
1914 struct rtl8169_private *tp = netdev_priv(dev);
1915 void __iomem *ioaddr = tp->mmio_addr;
1916 struct pci_dev *pdev = tp->pci_dev;
1918 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1919 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1920 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1923 RTL_W8(Cfg9346, Cfg9346_Unlock);
1924 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1925 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1926 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1927 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1928 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1930 RTL_W8(EarlyTxThres, EarlyTxThld);
1932 rtl_set_rx_max_size(ioaddr);
1934 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1935 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1936 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1937 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1938 rtl_set_rx_tx_config_registers(tp);
1940 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1942 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1943 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1944 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1945 "Bit-3 and bit-14 MUST be 1\n");
1946 tp->cp_cmd |= (1 << 14);
1949 RTL_W16(CPlusCmd, tp->cp_cmd);
1951 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1954 * Undocumented corner. Supposedly:
1955 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1957 RTL_W16(IntrMitigate, 0x0000);
1959 rtl_set_rx_tx_desc_registers(tp, ioaddr);
1961 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
1962 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
1963 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
1964 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
1965 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1966 rtl_set_rx_tx_config_registers(tp);
1969 RTL_W8(Cfg9346, Cfg9346_Lock);
1971 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1974 RTL_W32(RxMissed, 0);
1976 rtl_set_rx_mode(dev);
1978 /* no early-rx interrupts */
1979 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1981 /* Enable all known interrupts by setting the interrupt mask. */
1982 RTL_W16(IntrMask, tp->intr_event);
1985 static void rtl_hw_start_8168(struct net_device *dev)
1987 struct rtl8169_private *tp = netdev_priv(dev);
1988 void __iomem *ioaddr = tp->mmio_addr;
1989 struct pci_dev *pdev = tp->pci_dev;
1992 RTL_W8(Cfg9346, Cfg9346_Unlock);
1994 RTL_W8(EarlyTxThres, EarlyTxThld);
1996 rtl_set_rx_max_size(ioaddr);
1998 rtl_set_rx_tx_config_registers(tp);
2000 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2002 RTL_W16(CPlusCmd, tp->cp_cmd);
2004 /* Tx performance tweak. */
2005 pci_read_config_byte(pdev, 0x69, &ctl);
2006 ctl = (ctl & ~0x70) | 0x50;
2007 pci_write_config_byte(pdev, 0x69, ctl);
2009 RTL_W16(IntrMitigate, 0x5151);
2011 /* Work around for RxFIFO overflow. */
2012 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2013 tp->intr_event |= RxFIFOOver | PCSTimeout;
2014 tp->intr_event &= ~RxOverflow;
2017 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2019 RTL_W8(Cfg9346, Cfg9346_Lock);
2023 RTL_W32(RxMissed, 0);
2025 rtl_set_rx_mode(dev);
2027 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2029 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2031 RTL_W16(IntrMask, tp->intr_event);
2034 static void rtl_hw_start_8101(struct net_device *dev)
2036 struct rtl8169_private *tp = netdev_priv(dev);
2037 void __iomem *ioaddr = tp->mmio_addr;
2038 struct pci_dev *pdev = tp->pci_dev;
2040 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
2041 pci_write_config_word(pdev, 0x68, 0x00);
2042 pci_write_config_word(pdev, 0x69, 0x08);
2045 RTL_W8(Cfg9346, Cfg9346_Unlock);
2047 RTL_W8(EarlyTxThres, EarlyTxThld);
2049 rtl_set_rx_max_size(ioaddr);
2051 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2053 RTL_W16(CPlusCmd, tp->cp_cmd);
2055 RTL_W16(IntrMitigate, 0x0000);
2057 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2059 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2060 rtl_set_rx_tx_config_registers(tp);
2062 RTL_W8(Cfg9346, Cfg9346_Lock);
2066 RTL_W32(RxMissed, 0);
2068 rtl_set_rx_mode(dev);
2070 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2072 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2074 RTL_W16(IntrMask, tp->intr_event);
2077 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2079 struct rtl8169_private *tp = netdev_priv(dev);
2082 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2087 if (!netif_running(dev))
2092 rtl8169_set_rxbufsize(tp, dev);
2094 ret = rtl8169_init_ring(dev);
2098 #ifdef CONFIG_R8169_NAPI
2099 napi_enable(&tp->napi);
2104 rtl8169_request_timer(dev);
2110 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2112 desc->addr = 0x0badbadbadbadbadull;
2113 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2116 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2117 struct sk_buff **sk_buff, struct RxDesc *desc)
2119 struct pci_dev *pdev = tp->pci_dev;
2121 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2122 PCI_DMA_FROMDEVICE);
2123 dev_kfree_skb(*sk_buff);
2125 rtl8169_make_unusable_by_asic(desc);
2128 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2130 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2132 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2135 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2138 desc->addr = cpu_to_le64(mapping);
2140 rtl8169_mark_to_asic(desc, rx_buf_sz);
2143 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2144 struct net_device *dev,
2145 struct RxDesc *desc, int rx_buf_sz,
2148 struct sk_buff *skb;
2152 pad = align ? align : NET_IP_ALIGN;
2154 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2158 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2160 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2161 PCI_DMA_FROMDEVICE);
2163 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2168 rtl8169_make_unusable_by_asic(desc);
2172 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2176 for (i = 0; i < NUM_RX_DESC; i++) {
2177 if (tp->Rx_skbuff[i]) {
2178 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2179 tp->RxDescArray + i);
2184 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2189 for (cur = start; end - cur != 0; cur++) {
2190 struct sk_buff *skb;
2191 unsigned int i = cur % NUM_RX_DESC;
2193 WARN_ON((s32)(end - cur) < 0);
2195 if (tp->Rx_skbuff[i])
2198 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2199 tp->RxDescArray + i,
2200 tp->rx_buf_sz, tp->align);
2204 tp->Rx_skbuff[i] = skb;
2209 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2211 desc->opts1 |= cpu_to_le32(RingEnd);
2214 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2216 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2219 static int rtl8169_init_ring(struct net_device *dev)
2221 struct rtl8169_private *tp = netdev_priv(dev);
2223 rtl8169_init_ring_indexes(tp);
2225 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2226 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2228 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2231 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2236 rtl8169_rx_clear(tp);
2240 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2241 struct TxDesc *desc)
2243 unsigned int len = tx_skb->len;
2245 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2252 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2256 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2257 unsigned int entry = i % NUM_TX_DESC;
2258 struct ring_info *tx_skb = tp->tx_skb + entry;
2259 unsigned int len = tx_skb->len;
2262 struct sk_buff *skb = tx_skb->skb;
2264 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2265 tp->TxDescArray + entry);
2270 tp->stats.tx_dropped++;
2273 tp->cur_tx = tp->dirty_tx = 0;
2276 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2278 struct rtl8169_private *tp = netdev_priv(dev);
2280 PREPARE_DELAYED_WORK(&tp->task, task);
2281 schedule_delayed_work(&tp->task, 4);
2284 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2286 struct rtl8169_private *tp = netdev_priv(dev);
2287 void __iomem *ioaddr = tp->mmio_addr;
2289 synchronize_irq(dev->irq);
2291 /* Wait for any pending NAPI task to complete */
2292 #ifdef CONFIG_R8169_NAPI
2293 napi_disable(&tp->napi);
2296 rtl8169_irq_mask_and_ack(ioaddr);
2298 #ifdef CONFIG_R8169_NAPI
2299 napi_enable(&tp->napi);
2303 static void rtl8169_reinit_task(struct work_struct *work)
2305 struct rtl8169_private *tp =
2306 container_of(work, struct rtl8169_private, task.work);
2307 struct net_device *dev = tp->dev;
2312 if (!netif_running(dev))
2315 rtl8169_wait_for_quiescence(dev);
2318 ret = rtl8169_open(dev);
2319 if (unlikely(ret < 0)) {
2320 if (net_ratelimit() && netif_msg_drv(tp)) {
2321 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
2322 " Rescheduling.\n", dev->name, ret);
2324 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2331 static void rtl8169_reset_task(struct work_struct *work)
2333 struct rtl8169_private *tp =
2334 container_of(work, struct rtl8169_private, task.work);
2335 struct net_device *dev = tp->dev;
2339 if (!netif_running(dev))
2342 rtl8169_wait_for_quiescence(dev);
2344 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2345 rtl8169_tx_clear(tp);
2347 if (tp->dirty_rx == tp->cur_rx) {
2348 rtl8169_init_ring_indexes(tp);
2350 netif_wake_queue(dev);
2352 if (net_ratelimit() && netif_msg_intr(tp)) {
2353 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
2356 rtl8169_schedule_work(dev, rtl8169_reset_task);
2363 static void rtl8169_tx_timeout(struct net_device *dev)
2365 struct rtl8169_private *tp = netdev_priv(dev);
2367 rtl8169_hw_reset(tp->mmio_addr);
2369 /* Let's wait a bit while any (async) irq lands on */
2370 rtl8169_schedule_work(dev, rtl8169_reset_task);
2373 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2376 struct skb_shared_info *info = skb_shinfo(skb);
2377 unsigned int cur_frag, entry;
2378 struct TxDesc * uninitialized_var(txd);
2381 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2382 skb_frag_t *frag = info->frags + cur_frag;
2387 entry = (entry + 1) % NUM_TX_DESC;
2389 txd = tp->TxDescArray + entry;
2391 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2392 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2394 /* anti gcc 2.95.3 bugware (sic) */
2395 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2397 txd->opts1 = cpu_to_le32(status);
2398 txd->addr = cpu_to_le64(mapping);
2400 tp->tx_skb[entry].len = len;
2404 tp->tx_skb[entry].skb = skb;
2405 txd->opts1 |= cpu_to_le32(LastFrag);
2411 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2413 if (dev->features & NETIF_F_TSO) {
2414 u32 mss = skb_shinfo(skb)->gso_size;
2417 return LargeSend | ((mss & MSSMask) << MSSShift);
2419 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2420 const struct iphdr *ip = ip_hdr(skb);
2422 if (ip->protocol == IPPROTO_TCP)
2423 return IPCS | TCPCS;
2424 else if (ip->protocol == IPPROTO_UDP)
2425 return IPCS | UDPCS;
2426 WARN_ON(1); /* we need a WARN() */
2431 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2433 struct rtl8169_private *tp = netdev_priv(dev);
2434 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2435 struct TxDesc *txd = tp->TxDescArray + entry;
2436 void __iomem *ioaddr = tp->mmio_addr;
2440 int ret = NETDEV_TX_OK;
2442 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2443 if (netif_msg_drv(tp)) {
2445 "%s: BUG! Tx Ring full when queue awake!\n",
2451 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2454 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2456 frags = rtl8169_xmit_frags(tp, skb, opts1);
2458 len = skb_headlen(skb);
2463 if (unlikely(len < ETH_ZLEN)) {
2464 if (skb_padto(skb, ETH_ZLEN))
2465 goto err_update_stats;
2469 opts1 |= FirstFrag | LastFrag;
2470 tp->tx_skb[entry].skb = skb;
2473 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2475 tp->tx_skb[entry].len = len;
2476 txd->addr = cpu_to_le64(mapping);
2477 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2481 /* anti gcc 2.95.3 bugware (sic) */
2482 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2483 txd->opts1 = cpu_to_le32(status);
2485 dev->trans_start = jiffies;
2487 tp->cur_tx += frags + 1;
2491 RTL_W8(TxPoll, NPQ); /* set polling bit */
2493 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2494 netif_stop_queue(dev);
2496 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2497 netif_wake_queue(dev);
2504 netif_stop_queue(dev);
2505 ret = NETDEV_TX_BUSY;
2507 tp->stats.tx_dropped++;
2511 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2513 struct rtl8169_private *tp = netdev_priv(dev);
2514 struct pci_dev *pdev = tp->pci_dev;
2515 void __iomem *ioaddr = tp->mmio_addr;
2516 u16 pci_status, pci_cmd;
2518 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2519 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2521 if (netif_msg_intr(tp)) {
2523 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2524 dev->name, pci_cmd, pci_status);
2528 * The recovery sequence below admits a very elaborated explanation:
2529 * - it seems to work;
2530 * - I did not see what else could be done;
2531 * - it makes iop3xx happy.
2533 * Feel free to adjust to your needs.
2535 if (pdev->broken_parity_status)
2536 pci_cmd &= ~PCI_COMMAND_PARITY;
2538 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2540 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2542 pci_write_config_word(pdev, PCI_STATUS,
2543 pci_status & (PCI_STATUS_DETECTED_PARITY |
2544 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2545 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2547 /* The infamous DAC f*ckup only happens at boot time */
2548 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2549 if (netif_msg_intr(tp))
2550 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2551 tp->cp_cmd &= ~PCIDAC;
2552 RTL_W16(CPlusCmd, tp->cp_cmd);
2553 dev->features &= ~NETIF_F_HIGHDMA;
2556 rtl8169_hw_reset(ioaddr);
2558 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2561 static void rtl8169_tx_interrupt(struct net_device *dev,
2562 struct rtl8169_private *tp,
2563 void __iomem *ioaddr)
2565 unsigned int dirty_tx, tx_left;
2567 dirty_tx = tp->dirty_tx;
2569 tx_left = tp->cur_tx - dirty_tx;
2571 while (tx_left > 0) {
2572 unsigned int entry = dirty_tx % NUM_TX_DESC;
2573 struct ring_info *tx_skb = tp->tx_skb + entry;
2574 u32 len = tx_skb->len;
2578 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2579 if (status & DescOwn)
2582 tp->stats.tx_bytes += len;
2583 tp->stats.tx_packets++;
2585 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2587 if (status & LastFrag) {
2588 dev_kfree_skb_irq(tx_skb->skb);
2595 if (tp->dirty_tx != dirty_tx) {
2596 tp->dirty_tx = dirty_tx;
2598 if (netif_queue_stopped(dev) &&
2599 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2600 netif_wake_queue(dev);
2603 * 8168 hack: TxPoll requests are lost when the Tx packets are
2604 * too close. Let's kick an extra TxPoll request when a burst
2605 * of start_xmit activity is detected (if it is not detected,
2606 * it is slow enough). -- FR
2609 if (tp->cur_tx != dirty_tx)
2610 RTL_W8(TxPoll, NPQ);
2614 static inline int rtl8169_fragmented_frame(u32 status)
2616 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2619 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2621 u32 opts1 = le32_to_cpu(desc->opts1);
2622 u32 status = opts1 & RxProtoMask;
2624 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2625 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2626 ((status == RxProtoIP) && !(opts1 & IPFail)))
2627 skb->ip_summed = CHECKSUM_UNNECESSARY;
2629 skb->ip_summed = CHECKSUM_NONE;
2632 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2633 struct rtl8169_private *tp, int pkt_size,
2636 struct sk_buff *skb;
2639 if (pkt_size >= rx_copybreak)
2642 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2646 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2647 PCI_DMA_FROMDEVICE);
2648 skb_reserve(skb, NET_IP_ALIGN);
2649 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2656 static int rtl8169_rx_interrupt(struct net_device *dev,
2657 struct rtl8169_private *tp,
2658 void __iomem *ioaddr, u32 budget)
2660 unsigned int cur_rx, rx_left;
2661 unsigned int delta, count;
2663 cur_rx = tp->cur_rx;
2664 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2665 rx_left = rtl8169_rx_quota(rx_left, budget);
2667 for (; rx_left > 0; rx_left--, cur_rx++) {
2668 unsigned int entry = cur_rx % NUM_RX_DESC;
2669 struct RxDesc *desc = tp->RxDescArray + entry;
2673 status = le32_to_cpu(desc->opts1);
2675 if (status & DescOwn)
2677 if (unlikely(status & RxRES)) {
2678 if (netif_msg_rx_err(tp)) {
2680 "%s: Rx ERROR. status = %08x\n",
2683 tp->stats.rx_errors++;
2684 if (status & (RxRWT | RxRUNT))
2685 tp->stats.rx_length_errors++;
2687 tp->stats.rx_crc_errors++;
2688 if (status & RxFOVF) {
2689 rtl8169_schedule_work(dev, rtl8169_reset_task);
2690 tp->stats.rx_fifo_errors++;
2692 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2694 struct sk_buff *skb = tp->Rx_skbuff[entry];
2695 dma_addr_t addr = le64_to_cpu(desc->addr);
2696 int pkt_size = (status & 0x00001FFF) - 4;
2697 struct pci_dev *pdev = tp->pci_dev;
2700 * The driver does not support incoming fragmented
2701 * frames. They are seen as a symptom of over-mtu
2704 if (unlikely(rtl8169_fragmented_frame(status))) {
2705 tp->stats.rx_dropped++;
2706 tp->stats.rx_length_errors++;
2707 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2711 rtl8169_rx_csum(skb, desc);
2713 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2714 pci_dma_sync_single_for_device(pdev, addr,
2715 pkt_size, PCI_DMA_FROMDEVICE);
2716 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2718 pci_unmap_single(pdev, addr, pkt_size,
2719 PCI_DMA_FROMDEVICE);
2720 tp->Rx_skbuff[entry] = NULL;
2723 skb_put(skb, pkt_size);
2724 skb->protocol = eth_type_trans(skb, dev);
2726 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2727 rtl8169_rx_skb(skb);
2729 dev->last_rx = jiffies;
2730 tp->stats.rx_bytes += pkt_size;
2731 tp->stats.rx_packets++;
2734 /* Work around for AMD plateform. */
2735 if ((desc->opts2 & 0xfffe000) &&
2736 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2742 count = cur_rx - tp->cur_rx;
2743 tp->cur_rx = cur_rx;
2745 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2746 if (!delta && count && netif_msg_intr(tp))
2747 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2748 tp->dirty_rx += delta;
2751 * FIXME: until there is periodic timer to try and refill the ring,
2752 * a temporary shortage may definitely kill the Rx process.
2753 * - disable the asic to try and avoid an overflow and kick it again
2755 * - how do others driver handle this condition (Uh oh...).
2757 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2758 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2763 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2765 struct net_device *dev = dev_instance;
2766 struct rtl8169_private *tp = netdev_priv(dev);
2767 int boguscnt = max_interrupt_work;
2768 void __iomem *ioaddr = tp->mmio_addr;
2773 status = RTL_R16(IntrStatus);
2775 /* hotplug/major error/no more work/shared irq */
2776 if ((status == 0xFFFF) || !status)
2781 if (unlikely(!netif_running(dev))) {
2782 rtl8169_asic_down(ioaddr);
2786 status &= tp->intr_mask;
2788 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2790 if (!(status & tp->intr_event))
2793 /* Work around for rx fifo overflow */
2794 if (unlikely(status & RxFIFOOver) &&
2795 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2796 netif_stop_queue(dev);
2797 rtl8169_tx_timeout(dev);
2801 if (unlikely(status & SYSErr)) {
2802 rtl8169_pcierr_interrupt(dev);
2806 if (status & LinkChg)
2807 rtl8169_check_link_status(dev, tp, ioaddr);
2809 #ifdef CONFIG_R8169_NAPI
2810 if (status & tp->napi_event) {
2811 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2812 tp->intr_mask = ~tp->napi_event;
2814 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2815 __netif_rx_schedule(dev, &tp->napi);
2816 else if (netif_msg_intr(tp)) {
2817 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2824 if (status & (RxOK | RxOverflow | RxFIFOOver))
2825 rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0);
2828 if (status & (TxOK | TxErr))
2829 rtl8169_tx_interrupt(dev, tp, ioaddr);
2833 } while (boguscnt > 0);
2835 if (boguscnt <= 0) {
2836 if (netif_msg_intr(tp) && net_ratelimit() ) {
2838 "%s: Too much work at interrupt!\n", dev->name);
2840 /* Clear all interrupt sources. */
2841 RTL_W16(IntrStatus, 0xffff);
2844 return IRQ_RETVAL(handled);
2847 #ifdef CONFIG_R8169_NAPI
2848 static int rtl8169_poll(struct napi_struct *napi, int budget)
2850 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2851 struct net_device *dev = tp->dev;
2852 void __iomem *ioaddr = tp->mmio_addr;
2855 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
2856 rtl8169_tx_interrupt(dev, tp, ioaddr);
2858 if (work_done < budget) {
2859 netif_rx_complete(dev, napi);
2860 tp->intr_mask = 0xffff;
2862 * 20040426: the barrier is not strictly required but the
2863 * behavior of the irq handler could be less predictable
2864 * without it. Btw, the lack of flush for the posted pci
2865 * write is safe - FR
2868 RTL_W16(IntrMask, tp->intr_event);
2875 static void rtl8169_down(struct net_device *dev)
2877 struct rtl8169_private *tp = netdev_priv(dev);
2878 void __iomem *ioaddr = tp->mmio_addr;
2879 unsigned int poll_locked = 0;
2880 unsigned int intrmask;
2882 rtl8169_delete_timer(dev);
2884 netif_stop_queue(dev);
2887 spin_lock_irq(&tp->lock);
2889 rtl8169_asic_down(ioaddr);
2891 /* Update the error counts. */
2892 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2893 RTL_W32(RxMissed, 0);
2895 spin_unlock_irq(&tp->lock);
2897 synchronize_irq(dev->irq);
2900 napi_disable(&tp->napi);
2904 /* Give a racing hard_start_xmit a few cycles to complete. */
2905 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
2908 * And now for the 50k$ question: are IRQ disabled or not ?
2910 * Two paths lead here:
2912 * -> netif_running() is available to sync the current code and the
2913 * IRQ handler. See rtl8169_interrupt for details.
2914 * 2) dev->change_mtu
2915 * -> rtl8169_poll can not be issued again and re-enable the
2916 * interruptions. Let's simply issue the IRQ down sequence again.
2918 * No loop if hotpluged or major error (0xffff).
2920 intrmask = RTL_R16(IntrMask);
2921 if (intrmask && (intrmask != 0xffff))
2924 rtl8169_tx_clear(tp);
2926 rtl8169_rx_clear(tp);
2929 static int rtl8169_close(struct net_device *dev)
2931 struct rtl8169_private *tp = netdev_priv(dev);
2932 struct pci_dev *pdev = tp->pci_dev;
2936 free_irq(dev->irq, dev);
2938 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2940 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2942 tp->TxDescArray = NULL;
2943 tp->RxDescArray = NULL;
2948 static void rtl_set_rx_mode(struct net_device *dev)
2950 struct rtl8169_private *tp = netdev_priv(dev);
2951 void __iomem *ioaddr = tp->mmio_addr;
2952 unsigned long flags;
2953 u32 mc_filter[2]; /* Multicast hash filter */
2957 if (dev->flags & IFF_PROMISC) {
2958 /* Unconditionally log net taps. */
2959 if (netif_msg_link(tp)) {
2960 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2964 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2966 mc_filter[1] = mc_filter[0] = 0xffffffff;
2967 } else if ((dev->mc_count > multicast_filter_limit)
2968 || (dev->flags & IFF_ALLMULTI)) {
2969 /* Too many to filter perfectly -- accept all multicasts. */
2970 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2971 mc_filter[1] = mc_filter[0] = 0xffffffff;
2973 struct dev_mc_list *mclist;
2976 rx_mode = AcceptBroadcast | AcceptMyPhys;
2977 mc_filter[1] = mc_filter[0] = 0;
2978 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2979 i++, mclist = mclist->next) {
2980 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2981 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2982 rx_mode |= AcceptMulticast;
2986 spin_lock_irqsave(&tp->lock, flags);
2988 tmp = rtl8169_rx_config | rx_mode |
2989 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2991 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2992 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2993 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2994 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2995 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2996 mc_filter[0] = 0xffffffff;
2997 mc_filter[1] = 0xffffffff;
3000 RTL_W32(MAR0 + 0, mc_filter[0]);
3001 RTL_W32(MAR0 + 4, mc_filter[1]);
3003 RTL_W32(RxConfig, tmp);
3005 spin_unlock_irqrestore(&tp->lock, flags);
3009 * rtl8169_get_stats - Get rtl8169 read/write statistics
3010 * @dev: The Ethernet Device to get statistics for
3012 * Get TX/RX statistics for rtl8169
3014 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3016 struct rtl8169_private *tp = netdev_priv(dev);
3017 void __iomem *ioaddr = tp->mmio_addr;
3018 unsigned long flags;
3020 if (netif_running(dev)) {
3021 spin_lock_irqsave(&tp->lock, flags);
3022 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3023 RTL_W32(RxMissed, 0);
3024 spin_unlock_irqrestore(&tp->lock, flags);
3032 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3034 struct net_device *dev = pci_get_drvdata(pdev);
3035 struct rtl8169_private *tp = netdev_priv(dev);
3036 void __iomem *ioaddr = tp->mmio_addr;
3038 if (!netif_running(dev))
3039 goto out_pci_suspend;
3041 netif_device_detach(dev);
3042 netif_stop_queue(dev);
3044 spin_lock_irq(&tp->lock);
3046 rtl8169_asic_down(ioaddr);
3048 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3049 RTL_W32(RxMissed, 0);
3051 spin_unlock_irq(&tp->lock);
3054 pci_save_state(pdev);
3055 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3056 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3057 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3062 static int rtl8169_resume(struct pci_dev *pdev)
3064 struct net_device *dev = pci_get_drvdata(pdev);
3066 pci_set_power_state(pdev, PCI_D0);
3067 pci_restore_state(pdev);
3068 pci_enable_wake(pdev, PCI_D0, 0);
3070 if (!netif_running(dev))
3073 netif_device_attach(dev);
3075 rtl8169_schedule_work(dev, rtl8169_reset_task);
3080 #endif /* CONFIG_PM */
3082 static struct pci_driver rtl8169_pci_driver = {
3084 .id_table = rtl8169_pci_tbl,
3085 .probe = rtl8169_init_one,
3086 .remove = __devexit_p(rtl8169_remove_one),
3088 .suspend = rtl8169_suspend,
3089 .resume = rtl8169_resume,
3093 static int __init rtl8169_init_module(void)
3095 return pci_register_driver(&rtl8169_pci_driver);
3098 static void __exit rtl8169_cleanup_module(void)
3100 pci_unregister_driver(&rtl8169_pci_driver);
3103 module_init(rtl8169_init_module);
3104 module_exit(rtl8169_cleanup_module);