drivers/net/qlge/qlge_main.c

   1 /*
   2  * QLogic qlge NIC HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  * See LICENSE.qlge for copyright and licensing details.
   5  * Author:     Linux qlge network device driver by
   6  *                      Ron Mercer <ron.mercer@qlogic.com>
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/sched.h>
  17 #include <linux/slab.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/mempool.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/kthread.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/errno.h>
  24 #include <linux/ioport.h>
  25 #include <linux/in.h>
  26 #include <linux/ip.h>
  27 #include <linux/ipv6.h>
  28 #include <net/ipv6.h>
  29 #include <linux/tcp.h>
  30 #include <linux/udp.h>
  31 #include <linux/if_arp.h>
  32 #include <linux/if_ether.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/rtnetlink.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/delay.h>
  40 #include <linux/mm.h>
  41 #include <linux/vmalloc.h>
  42 #include <net/ip6_checksum.h>
  43
  44 #include "qlge.h"
  45
  46 char qlge_driver_name[] = DRV_NAME;
  47 const char qlge_driver_version[] = DRV_VERSION;
  48
  49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
  50 MODULE_DESCRIPTION(DRV_STRING " ");
  51 MODULE_LICENSE("GPL");
  52 MODULE_VERSION(DRV_VERSION);
  53
  54 static const u32 default_msg =
  55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
  56 /* NETIF_MSG_TIMER |    */
  57     NETIF_MSG_IFDOWN |
  58     NETIF_MSG_IFUP |
  59     NETIF_MSG_RX_ERR |
  60     NETIF_MSG_TX_ERR |
  61     NETIF_MSG_TX_QUEUED |
  62     NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS |
  63 /* NETIF_MSG_PKTDATA | */
  64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
  65
  66 static int debug = 0x00007fff;  /* defaults above */
  67 module_param(debug, int, 0);
  68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  69
  70 #define MSIX_IRQ 0
  71 #define MSI_IRQ 1
  72 #define LEG_IRQ 2
  73 static int irq_type = MSIX_IRQ;
  74 module_param(irq_type, int, MSIX_IRQ);
  75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
  76
  77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
  78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID)},
  79         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID1)},
  80         /* required last entry */
  81         {0,}
  82 };
  83
  84 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
  85
  86 /* This hardware semaphore causes exclusive access to
  87  * resources shared between the NIC driver, MPI firmware,
  88  * FCOE firmware and the FC driver.
  89  */
  90 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
  91 {
  92         u32 sem_bits = 0;
  93
  94         switch (sem_mask) {
  95         case SEM_XGMAC0_MASK:
  96                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
  97                 break;
  98         case SEM_XGMAC1_MASK:
  99                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
 100                 break;
 101         case SEM_ICB_MASK:
 102                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
 103                 break;
 104         case SEM_MAC_ADDR_MASK:
 105                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
 106                 break;
 107         case SEM_FLASH_MASK:
 108                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
 109                 break;
 110         case SEM_PROBE_MASK:
 111                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
 112                 break;
 113         case SEM_RT_IDX_MASK:
 114                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
 115                 break;
 116         case SEM_PROC_REG_MASK:
 117                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
 118                 break;
 119         default:
 120                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
 121                 return -EINVAL;
 122         }
 123
 124         ql_write32(qdev, SEM, sem_bits | sem_mask);
 125         return !(ql_read32(qdev, SEM) & sem_bits);
 126 }
 127
 128 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
 129 {
 130         unsigned int seconds = 3;
 131         do {
 132                 if (!ql_sem_trylock(qdev, sem_mask))
 133                         return 0;
 134                 ssleep(1);
 135         } while (--seconds);
 136         return -ETIMEDOUT;
 137 }
 138
 139 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
 140 {
 141         ql_write32(qdev, SEM, sem_mask);
 142         ql_read32(qdev, SEM);   /* flush */
 143 }
 144
 145 /* This function waits for a specific bit to come ready
 146  * in a given register.  It is used mostly by the initialize
 147  * process, but is also used in kernel thread API such as
 148  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
 149  */
 150 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
 151 {
 152         u32 temp;
 153         int count = UDELAY_COUNT;
 154
 155         while (count) {
 156                 temp = ql_read32(qdev, reg);
 157
 158                 /* check for errors */
 159                 if (temp & err_bit) {
 160                         QPRINTK(qdev, PROBE, ALERT,
 161                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
 162                                 reg, temp);
 163                         return -EIO;
 164                 } else if (temp & bit)
 165                         return 0;
 166                 udelay(UDELAY_DELAY);
 167                 count--;
 168         }
 169         QPRINTK(qdev, PROBE, ALERT,
 170                 "Timed out waiting for reg %x to come ready.\n", reg);
 171         return -ETIMEDOUT;
 172 }
 173
 174 /* The CFG register is used to download TX and RX control blocks
 175  * to the chip. This function waits for an operation to complete.
 176  */
 177 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
 178 {
 179         int count = UDELAY_COUNT;
 180         u32 temp;
 181
 182         while (count) {
 183                 temp = ql_read32(qdev, CFG);
 184                 if (temp & CFG_LE)
 185                         return -EIO;
 186                 if (!(temp & bit))
 187                         return 0;
 188                 udelay(UDELAY_DELAY);
 189                 count--;
 190         }
 191         return -ETIMEDOUT;
 192 }
 193
 194
 195 /* Used to issue init control blocks to hw. Maps control block,
 196  * sets address, triggers download, waits for completion.
 197  */
 198 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
 199                  u16 q_id)
 200 {
 201         u64 map;
 202         int status = 0;
 203         int direction;
 204         u32 mask;
 205         u32 value;
 206
 207         direction =
 208             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
 209             PCI_DMA_FROMDEVICE;
 210
 211         map = pci_map_single(qdev->pdev, ptr, size, direction);
 212         if (pci_dma_mapping_error(qdev->pdev, map)) {
 213                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
 214                 return -ENOMEM;
 215         }
 216
 217         status = ql_wait_cfg(qdev, bit);
 218         if (status) {
 219                 QPRINTK(qdev, IFUP, ERR,
 220                         "Timed out waiting for CFG to come ready.\n");
 221                 goto exit;
 222         }
 223
 224         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
 225         if (status)
 226                 goto exit;
 227         ql_write32(qdev, ICB_L, (u32) map);
 228         ql_write32(qdev, ICB_H, (u32) (map >> 32));
 229         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
 230
 231         mask = CFG_Q_MASK | (bit << 16);
 232         value = bit | (q_id << CFG_Q_SHIFT);
 233         ql_write32(qdev, CFG, (mask | value));
 234
 235         /*
 236          * Wait for the bit to clear after signaling hw.
 237          */
 238         status = ql_wait_cfg(qdev, bit);
 239 exit:
 240         pci_unmap_single(qdev->pdev, map, size, direction);
 241         return status;
 242 }
 243
 244 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
 245 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
 246                         u32 *value)
 247 {
 248         u32 offset = 0;
 249         int status;
 250
 251         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
 252         if (status)
 253                 return status;
 254         switch (type) {
 255         case MAC_ADDR_TYPE_MULTI_MAC:
 256         case MAC_ADDR_TYPE_CAM_MAC:
 257                 {
 258                         status =
 259                             ql_wait_reg_rdy(qdev,
 260                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 261                         if (status)
 262                                 goto exit;
 263                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 264                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 265                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 266                         status =
 267                             ql_wait_reg_rdy(qdev,
 268                                 MAC_ADDR_IDX, MAC_ADDR_MR, MAC_ADDR_E);
 269                         if (status)
 270                                 goto exit;
 271                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 272                         status =
 273                             ql_wait_reg_rdy(qdev,
 274                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 275                         if (status)
 276                                 goto exit;
 277                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 278                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 279                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 280                         status =
 281                             ql_wait_reg_rdy(qdev,
 282                                 MAC_ADDR_IDX, MAC_ADDR_MR, MAC_ADDR_E);
 283                         if (status)
 284                                 goto exit;
 285                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 286                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 287                                 status =
 288                                     ql_wait_reg_rdy(qdev,
 289                                         MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 290                                 if (status)
 291                                         goto exit;
 292                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 293                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
 294                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 295                                 status =
 296                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
 297                                                     MAC_ADDR_MR, MAC_ADDR_E);
 298                                 if (status)
 299                                         goto exit;
 300                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 301                         }
 302                         break;
 303                 }
 304         case MAC_ADDR_TYPE_VLAN:
 305         case MAC_ADDR_TYPE_MULTI_FLTR:
 306         default:
 307                 QPRINTK(qdev, IFUP, CRIT,
 308                         "Address type %d not yet supported.\n", type);
 309                 status = -EPERM;
 310         }
 311 exit:
 312         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 313         return status;
 314 }
 315
 316 /* Set up a MAC, multicast or VLAN address for the
 317  * inbound frame matching.
 318  */
 319 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
 320                                u16 index)
 321 {
 322         u32 offset = 0;
 323         int status = 0;
 324
 325         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
 326         if (status)
 327                 return status;
 328         switch (type) {
 329         case MAC_ADDR_TYPE_MULTI_MAC:
 330         case MAC_ADDR_TYPE_CAM_MAC:
 331                 {
 332                         u32 cam_output;
 333                         u32 upper = (addr[0] << 8) | addr[1];
 334                         u32 lower =
 335                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
 336                             (addr[5]);
 337
 338                         QPRINTK(qdev, IFUP, INFO,
 339                                 "Adding %s address %pM"
 340                                 " at index %d in the CAM.\n",
 341                                 ((type ==
 342                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
 343                                  "UNICAST"), addr, index);
 344
 345                         status =
 346                             ql_wait_reg_rdy(qdev,
 347                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 348                         if (status)
 349                                 goto exit;
 350                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 351                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 352                                    type);       /* type */
 353                         ql_write32(qdev, MAC_ADDR_DATA, lower);
 354                         status =
 355                             ql_wait_reg_rdy(qdev,
 356                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 357                         if (status)
 358                                 goto exit;
 359                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 360                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 361                                    type);       /* type */
 362                         ql_write32(qdev, MAC_ADDR_DATA, upper);
 363                         status =
 364                             ql_wait_reg_rdy(qdev,
 365                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 366                         if (status)
 367                                 goto exit;
 368                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
 369                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 370                                    type);       /* type */
 371                         /* This field should also include the queue id
 372                            and possibly the function id.  Right now we hardcode
 373                            the route field to NIC core.
 374                          */
 375                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 376                                 cam_output = (CAM_OUT_ROUTE_NIC |
 377                                               (qdev->
 378                                                func << CAM_OUT_FUNC_SHIFT) |
 379                                               (qdev->
 380                                                rss_ring_first_cq_id <<
 381                                                CAM_OUT_CQ_ID_SHIFT));
 382                                 if (qdev->vlgrp)
 383                                         cam_output |= CAM_OUT_RV;
 384                                 /* route to NIC core */
 385                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
 386                         }
 387                         break;
 388                 }
 389         case MAC_ADDR_TYPE_VLAN:
 390                 {
 391                         u32 enable_bit = *((u32 *) &addr[0]);
 392                         /* For VLAN, the addr actually holds a bit that
 393                          * either enables or disables the vlan id we are
 394                          * addressing. It's either MAC_ADDR_E on or off.
 395                          * That's bit-27 we're talking about.
 396                          */
 397                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
 398                                 (enable_bit ? "Adding" : "Removing"),
 399                                 index, (enable_bit ? "to" : "from"));
 400
 401                         status =
 402                             ql_wait_reg_rdy(qdev,
 403                                 MAC_ADDR_IDX, MAC_ADDR_MW, MAC_ADDR_E);
 404                         if (status)
 405                                 goto exit;
 406                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
 407                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 408                                    type |       /* type */
 409                                    enable_bit); /* enable/disable */
 410                         break;
 411                 }
 412         case MAC_ADDR_TYPE_MULTI_FLTR:
 413         default:
 414                 QPRINTK(qdev, IFUP, CRIT,
 415                         "Address type %d not yet supported.\n", type);
 416                 status = -EPERM;
 417         }
 418 exit:
 419         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
 420         return status;
 421 }
 422
 423 /* Get a specific frame routing value from the CAM.
 424  * Used for debug and reg dump.
 425  */
 426 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
 427 {
 428         int status = 0;
 429
 430         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
 431         if (status)
 432                 goto exit;
 433
 434         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, RT_IDX_E);
 435         if (status)
 436                 goto exit;
 437
 438         ql_write32(qdev, RT_IDX,
 439                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
 440         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, RT_IDX_E);
 441         if (status)
 442                 goto exit;
 443         *value = ql_read32(qdev, RT_DATA);
 444 exit:
 445         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
 446         return status;
 447 }
 448
 449 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
 450  * to route different frame types to various inbound queues.  We send broadcast/
 451  * multicast/error frames to the default queue for slow handling,
 452  * and CAM hit/RSS frames to the fast handling queues.
 453  */
 454 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
 455                               int enable)
 456 {
 457         int status;
 458         u32 value = 0;
 459
 460         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
 461         if (status)
 462                 return status;
 463
 464         QPRINTK(qdev, IFUP, DEBUG,
 465                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
 466                 (enable ? "Adding" : "Removing"),
 467                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
 468                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
 469                 ((index ==
 470                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
 471                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
 472                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
 473                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
 474                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
 475                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
 476                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
 477                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
 478                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
 479                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
 480                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
 481                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
 482                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
 483                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
 484                 (enable ? "to" : "from"));
 485
 486         switch (mask) {
 487         case RT_IDX_CAM_HIT:
 488                 {
 489                         value = RT_IDX_DST_CAM_Q |      /* dest */
 490                             RT_IDX_TYPE_NICQ |  /* type */
 491                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
 492                         break;
 493                 }
 494         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
 495                 {
 496                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 497                             RT_IDX_TYPE_NICQ |  /* type */
 498                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
 499                         break;
 500                 }
 501         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
 502                 {
 503                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 504                             RT_IDX_TYPE_NICQ |  /* type */
 505                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
 506                         break;
 507                 }
 508         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
 509                 {
 510                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 511                             RT_IDX_TYPE_NICQ |  /* type */
 512                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
 513                         break;
 514                 }
 515         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
 516                 {
 517                         value = RT_IDX_DST_CAM_Q |      /* dest */
 518                             RT_IDX_TYPE_NICQ |  /* type */
 519                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
 520                         break;
 521                 }
 522         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
 523                 {
 524                         value = RT_IDX_DST_CAM_Q |      /* dest */
 525                             RT_IDX_TYPE_NICQ |  /* type */
 526                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 527                         break;
 528                 }
 529         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
 530                 {
 531                         value = RT_IDX_DST_RSS |        /* dest */
 532                             RT_IDX_TYPE_NICQ |  /* type */
 533                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 534                         break;
 535                 }
 536         case 0:         /* Clear the E-bit on an entry. */
 537                 {
 538                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 539                             RT_IDX_TYPE_NICQ |  /* type */
 540                             (index << RT_IDX_IDX_SHIFT);/* index */
 541                         break;
 542                 }
 543         default:
 544                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
 545                         mask);
 546                 status = -EPERM;
 547                 goto exit;
 548         }
 549
 550         if (value) {
 551                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 552                 if (status)
 553                         goto exit;
 554                 value |= (enable ? RT_IDX_E : 0);
 555                 ql_write32(qdev, RT_IDX, value);
 556                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
 557         }
 558 exit:
 559         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
 560         return status;
 561 }
 562
 563 static void ql_enable_interrupts(struct ql_adapter *qdev)
 564 {
 565         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
 566 }
 567
 568 static void ql_disable_interrupts(struct ql_adapter *qdev)
 569 {
 570         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
 571 }
 572
 573 /* If we're running with multiple MSI-X vectors then we enable on the fly.
 574  * Otherwise, we may have multiple outstanding workers and don't want to
 575  * enable until the last one finishes. In this case, the irq_cnt gets
 576  * incremented everytime we queue a worker and decremented everytime
 577  * a worker finishes.  Once it hits zero we enable the interrupt.
 578  */
 579 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 580 {
 581         u32 var = 0;
 582         unsigned long hw_flags = 0;
 583         struct intr_context *ctx = qdev->intr_context + intr;
 584
 585         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
 586                 /* Always enable if we're MSIX multi interrupts and
 587                  * it's not the default (zeroeth) interrupt.
 588                  */
 589                 ql_write32(qdev, INTR_EN,
 590                            ctx->intr_en_mask);
 591                 var = ql_read32(qdev, STS);
 592                 return var;
 593         }
 594
 595         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 596         if (atomic_dec_and_test(&ctx->irq_cnt)) {
 597                 ql_write32(qdev, INTR_EN,
 598                            ctx->intr_en_mask);
 599                 var = ql_read32(qdev, STS);
 600         }
 601         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 602         return var;
 603 }
 604
 605 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 606 {
 607         u32 var = 0;
 608         unsigned long hw_flags;
 609         struct intr_context *ctx;
 610
 611         /* HW disables for us if we're MSIX multi interrupts and
 612          * it's not the default (zeroeth) interrupt.
 613          */
 614         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
 615                 return 0;
 616
 617         ctx = qdev->intr_context + intr;
 618         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 619         if (!atomic_read(&ctx->irq_cnt)) {
 620                 ql_write32(qdev, INTR_EN,
 621                 ctx->intr_dis_mask);
 622                 var = ql_read32(qdev, STS);
 623         }
 624         atomic_inc(&ctx->irq_cnt);
 625         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 626         return var;
 627 }
 628
 629 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
 630 {
 631         int i;
 632         for (i = 0; i < qdev->intr_count; i++) {
 633                 /* The enable call does a atomic_dec_and_test
 634                  * and enables only if the result is zero.
 635                  * So we precharge it here.
 636                  */
 637                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
 638                         i == 0))
 639                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
 640                 ql_enable_completion_interrupt(qdev, i);
 641         }
 642
 643 }
 644
 645 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, u32 *data)
 646 {
 647         int status = 0;
 648         /* wait for reg to come ready */
 649         status = ql_wait_reg_rdy(qdev,
 650                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 651         if (status)
 652                 goto exit;
 653         /* set up for reg read */
 654         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
 655         /* wait for reg to come ready */
 656         status = ql_wait_reg_rdy(qdev,
 657                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 658         if (status)
 659                 goto exit;
 660         /* get the data */
 661         *data = ql_read32(qdev, FLASH_DATA);
 662 exit:
 663         return status;
 664 }
 665
 666 static int ql_get_flash_params(struct ql_adapter *qdev)
 667 {
 668         int i;
 669         int status;
 670         u32 *p = (u32 *)&qdev->flash;
 671
 672         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 673                 return -ETIMEDOUT;
 674
 675         for (i = 0; i < sizeof(qdev->flash) / sizeof(u32); i++, p++) {
 676                 status = ql_read_flash_word(qdev, i, p);
 677                 if (status) {
 678                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 679                         goto exit;
 680                 }
 681
 682         }
 683 exit:
 684         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 685         return status;
 686 }
 687
 688 /* xgmac register are located behind the xgmac_addr and xgmac_data
 689  * register pair.  Each read/write requires us to wait for the ready
 690  * bit before reading/writing the data.
 691  */
 692 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
 693 {
 694         int status;
 695         /* wait for reg to come ready */
 696         status = ql_wait_reg_rdy(qdev,
 697                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 698         if (status)
 699                 return status;
 700         /* write the data to the data reg */
 701         ql_write32(qdev, XGMAC_DATA, data);
 702         /* trigger the write */
 703         ql_write32(qdev, XGMAC_ADDR, reg);
 704         return status;
 705 }
 706
 707 /* xgmac register are located behind the xgmac_addr and xgmac_data
 708  * register pair.  Each read/write requires us to wait for the ready
 709  * bit before reading/writing the data.
 710  */
 711 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
 712 {
 713         int status = 0;
 714         /* wait for reg to come ready */
 715         status = ql_wait_reg_rdy(qdev,
 716                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 717         if (status)
 718                 goto exit;
 719         /* set up for reg read */
 720         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
 721         /* wait for reg to come ready */
 722         status = ql_wait_reg_rdy(qdev,
 723                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 724         if (status)
 725                 goto exit;
 726         /* get the data */
 727         *data = ql_read32(qdev, XGMAC_DATA);
 728 exit:
 729         return status;
 730 }
 731
 732 /* This is used for reading the 64-bit statistics regs. */
 733 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
 734 {
 735         int status = 0;
 736         u32 hi = 0;
 737         u32 lo = 0;
 738
 739         status = ql_read_xgmac_reg(qdev, reg, &lo);
 740         if (status)
 741                 goto exit;
 742
 743         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
 744         if (status)
 745                 goto exit;
 746
 747         *data = (u64) lo | ((u64) hi << 32);
 748
 749 exit:
 750         return status;
 751 }
 752
 753 /* Take the MAC Core out of reset.
 754  * Enable statistics counting.
 755  * Take the transmitter/receiver out of reset.
 756  * This functionality may be done in the MPI firmware at a
 757  * later date.
 758  */
 759 static int ql_port_initialize(struct ql_adapter *qdev)
 760 {
 761         int status = 0;
 762         u32 data;
 763
 764         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
 765                 /* Another function has the semaphore, so
 766                  * wait for the port init bit to come ready.
 767                  */
 768                 QPRINTK(qdev, LINK, INFO,
 769                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
 770                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
 771                 if (status) {
 772                         QPRINTK(qdev, LINK, CRIT,
 773                                 "Port initialize timed out.\n");
 774                 }
 775                 return status;
 776         }
 777
 778         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
 779         /* Set the core reset. */
 780         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
 781         if (status)
 782                 goto end;
 783         data |= GLOBAL_CFG_RESET;
 784         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 785         if (status)
 786                 goto end;
 787
 788         /* Clear the core reset and turn on jumbo for receiver. */
 789         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
 790         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
 791         data |= GLOBAL_CFG_TX_STAT_EN;
 792         data |= GLOBAL_CFG_RX_STAT_EN;
 793         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 794         if (status)
 795                 goto end;
 796
 797         /* Enable transmitter, and clear it's reset. */
 798         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
 799         if (status)
 800                 goto end;
 801         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
 802         data |= TX_CFG_EN;      /* Enable the transmitter. */
 803         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
 804         if (status)
 805                 goto end;
 806
 807         /* Enable receiver and clear it's reset. */
 808         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
 809         if (status)
 810                 goto end;
 811         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
 812         data |= RX_CFG_EN;      /* Enable the receiver. */
 813         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
 814         if (status)
 815                 goto end;
 816
 817         /* Turn on jumbo. */
 818         status =
 819             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
 820         if (status)
 821                 goto end;
 822         status =
 823             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
 824         if (status)
 825                 goto end;
 826
 827         /* Signal to the world that the port is enabled.        */
 828         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
 829 end:
 830         ql_sem_unlock(qdev, qdev->xg_sem_mask);
 831         return status;
 832 }
 833
 834 /* Get the next large buffer. */
 835 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
 836 {
 837         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
 838         rx_ring->lbq_curr_idx++;
 839         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
 840                 rx_ring->lbq_curr_idx = 0;
 841         rx_ring->lbq_free_cnt++;
 842         return lbq_desc;
 843 }
 844
 845 /* Get the next small buffer. */
 846 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
 847 {
 848         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
 849         rx_ring->sbq_curr_idx++;
 850         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
 851                 rx_ring->sbq_curr_idx = 0;
 852         rx_ring->sbq_free_cnt++;
 853         return sbq_desc;
 854 }
 855
 856 /* Update an rx ring index. */
 857 static void ql_update_cq(struct rx_ring *rx_ring)
 858 {
 859         rx_ring->cnsmr_idx++;
 860         rx_ring->curr_entry++;
 861         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
 862                 rx_ring->cnsmr_idx = 0;
 863                 rx_ring->curr_entry = rx_ring->cq_base;
 864         }
 865 }
 866
 867 static void ql_write_cq_idx(struct rx_ring *rx_ring)
 868 {
 869         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
 870 }
 871
 872 /* Process (refill) a large buffer queue. */
 873 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 874 {
 875         int clean_idx = rx_ring->lbq_clean_idx;
 876         struct bq_desc *lbq_desc;
 877         struct bq_element *bq;
 878         u64 map;
 879         int i;
 880
 881         while (rx_ring->lbq_free_cnt > 16) {
 882                 for (i = 0; i < 16; i++) {
 883                         QPRINTK(qdev, RX_STATUS, DEBUG,
 884                                 "lbq: try cleaning clean_idx = %d.\n",
 885                                 clean_idx);
 886                         lbq_desc = &rx_ring->lbq[clean_idx];
 887                         bq = lbq_desc->bq;
 888                         if (lbq_desc->p.lbq_page == NULL) {
 889                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 890                                         "lbq: getting new page for index %d.\n",
 891                                         lbq_desc->index);
 892                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
 893                                 if (lbq_desc->p.lbq_page == NULL) {
 894                                         QPRINTK(qdev, RX_STATUS, ERR,
 895                                                 "Couldn't get a page.\n");
 896                                         return;
 897                                 }
 898                                 map = pci_map_page(qdev->pdev,
 899                                                    lbq_desc->p.lbq_page,
 900                                                    0, PAGE_SIZE,
 901                                                    PCI_DMA_FROMDEVICE);
 902                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
 903                                         QPRINTK(qdev, RX_STATUS, ERR,
 904                                                 "PCI mapping failed.\n");
 905                                         return;
 906                                 }
 907                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
 908                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
 909                                 bq->addr_lo =   /*lbq_desc->addr_lo = */
 910                                     cpu_to_le32(map);
 911                                 bq->addr_hi =   /*lbq_desc->addr_hi = */
 912                                     cpu_to_le32(map >> 32);
 913                         }
 914                         clean_idx++;
 915                         if (clean_idx == rx_ring->lbq_len)
 916                                 clean_idx = 0;
 917                 }
 918
 919                 rx_ring->lbq_clean_idx = clean_idx;
 920                 rx_ring->lbq_prod_idx += 16;
 921                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
 922                         rx_ring->lbq_prod_idx = 0;
 923                 QPRINTK(qdev, RX_STATUS, DEBUG,
 924                         "lbq: updating prod idx = %d.\n",
 925                         rx_ring->lbq_prod_idx);
 926                 ql_write_db_reg(rx_ring->lbq_prod_idx,
 927                                 rx_ring->lbq_prod_idx_db_reg);
 928                 rx_ring->lbq_free_cnt -= 16;
 929         }
 930 }
 931
 932 /* Process (refill) a small buffer queue. */
 933 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 934 {
 935         int clean_idx = rx_ring->sbq_clean_idx;
 936         struct bq_desc *sbq_desc;
 937         struct bq_element *bq;
 938         u64 map;
 939         int i;
 940
 941         while (rx_ring->sbq_free_cnt > 16) {
 942                 for (i = 0; i < 16; i++) {
 943                         sbq_desc = &rx_ring->sbq[clean_idx];
 944                         QPRINTK(qdev, RX_STATUS, DEBUG,
 945                                 "sbq: try cleaning clean_idx = %d.\n",
 946                                 clean_idx);
 947                         bq = sbq_desc->bq;
 948                         if (sbq_desc->p.skb == NULL) {
 949                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 950                                         "sbq: getting new skb for index %d.\n",
 951                                         sbq_desc->index);
 952                                 sbq_desc->p.skb =
 953                                     netdev_alloc_skb(qdev->ndev,
 954                                                      rx_ring->sbq_buf_size);
 955                                 if (sbq_desc->p.skb == NULL) {
 956                                         QPRINTK(qdev, PROBE, ERR,
 957                                                 "Couldn't get an skb.\n");
 958                                         rx_ring->sbq_clean_idx = clean_idx;
 959                                         return;
 960                                 }
 961                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
 962                                 map = pci_map_single(qdev->pdev,
 963                                                      sbq_desc->p.skb->data,
 964                                                      rx_ring->sbq_buf_size /
 965                                                      2, PCI_DMA_FROMDEVICE);
 966                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
 967                                 pci_unmap_len_set(sbq_desc, maplen,
 968                                                   rx_ring->sbq_buf_size / 2);
 969                                 bq->addr_lo = cpu_to_le32(map);
 970                                 bq->addr_hi = cpu_to_le32(map >> 32);
 971                         }
 972
 973                         clean_idx++;
 974                         if (clean_idx == rx_ring->sbq_len)
 975                                 clean_idx = 0;
 976                 }
 977                 rx_ring->sbq_clean_idx = clean_idx;
 978                 rx_ring->sbq_prod_idx += 16;
 979                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
 980                         rx_ring->sbq_prod_idx = 0;
 981                 QPRINTK(qdev, RX_STATUS, DEBUG,
 982                         "sbq: updating prod idx = %d.\n",
 983                         rx_ring->sbq_prod_idx);
 984                 ql_write_db_reg(rx_ring->sbq_prod_idx,
 985                                 rx_ring->sbq_prod_idx_db_reg);
 986
 987                 rx_ring->sbq_free_cnt -= 16;
 988         }
 989 }
 990
 991 static void ql_update_buffer_queues(struct ql_adapter *qdev,
 992                                     struct rx_ring *rx_ring)
 993 {
 994         ql_update_sbq(qdev, rx_ring);
 995         ql_update_lbq(qdev, rx_ring);
 996 }
 997
 998 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
 999  * fails at some stage, or from the interrupt when a tx completes.
1000  */
1001 static void ql_unmap_send(struct ql_adapter *qdev,
1002                           struct tx_ring_desc *tx_ring_desc, int mapped)
1003 {
1004         int i;
1005         for (i = 0; i < mapped; i++) {
1006                 if (i == 0 || (i == 7 && mapped > 7)) {
1007                         /*
1008                          * Unmap the skb->data area, or the
1009                          * external sglist (AKA the Outbound
1010                          * Address List (OAL)).
1011                          * If its the zeroeth element, then it's
1012                          * the skb->data area.  If it's the 7th
1013                          * element and there is more than 6 frags,
1014                          * then its an OAL.
1015                          */
1016                         if (i == 7) {
1017                                 QPRINTK(qdev, TX_DONE, DEBUG,
1018                                         "unmapping OAL area.\n");
1019                         }
1020                         pci_unmap_single(qdev->pdev,
1021                                          pci_unmap_addr(&tx_ring_desc->map[i],
1022                                                         mapaddr),
1023                                          pci_unmap_len(&tx_ring_desc->map[i],
1024                                                        maplen),
1025                                          PCI_DMA_TODEVICE);
1026                 } else {
1027                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1028                                 i);
1029                         pci_unmap_page(qdev->pdev,
1030                                        pci_unmap_addr(&tx_ring_desc->map[i],
1031                                                       mapaddr),
1032                                        pci_unmap_len(&tx_ring_desc->map[i],
1033                                                      maplen), PCI_DMA_TODEVICE);
1034                 }
1035         }
1036
1037 }
1038
1039 /* Map the buffers for this transmit.  This will return
1040  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1041  */
1042 static int ql_map_send(struct ql_adapter *qdev,
1043                        struct ob_mac_iocb_req *mac_iocb_ptr,
1044                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1045 {
1046         int len = skb_headlen(skb);
1047         dma_addr_t map;
1048         int frag_idx, err, map_idx = 0;
1049         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1050         int frag_cnt = skb_shinfo(skb)->nr_frags;
1051
1052         if (frag_cnt) {
1053                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1054         }
1055         /*
1056          * Map the skb buffer first.
1057          */
1058         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1059
1060         err = pci_dma_mapping_error(qdev->pdev, map);
1061         if (err) {
1062                 QPRINTK(qdev, TX_QUEUED, ERR,
1063                         "PCI mapping failed with error: %d\n", err);
1064
1065                 return NETDEV_TX_BUSY;
1066         }
1067
1068         tbd->len = cpu_to_le32(len);
1069         tbd->addr = cpu_to_le64(map);
1070         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1071         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1072         map_idx++;
1073
1074         /*
1075          * This loop fills the remainder of the 8 address descriptors
1076          * in the IOCB.  If there are more than 7 fragments, then the
1077          * eighth address desc will point to an external list (OAL).
1078          * When this happens, the remainder of the frags will be stored
1079          * in this list.
1080          */
1081         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1082                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1083                 tbd++;
1084                 if (frag_idx == 6 && frag_cnt > 7) {
1085                         /* Let's tack on an sglist.
1086                          * Our control block will now
1087                          * look like this:
1088                          * iocb->seg[0] = skb->data
1089                          * iocb->seg[1] = frag[0]
1090                          * iocb->seg[2] = frag[1]
1091                          * iocb->seg[3] = frag[2]
1092                          * iocb->seg[4] = frag[3]
1093                          * iocb->seg[5] = frag[4]
1094                          * iocb->seg[6] = frag[5]
1095                          * iocb->seg[7] = ptr to OAL (external sglist)
1096                          * oal->seg[0] = frag[6]
1097                          * oal->seg[1] = frag[7]
1098                          * oal->seg[2] = frag[8]
1099                          * oal->seg[3] = frag[9]
1100                          * oal->seg[4] = frag[10]
1101                          *      etc...
1102                          */
1103                         /* Tack on the OAL in the eighth segment of IOCB. */
1104                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1105                                              sizeof(struct oal),
1106                                              PCI_DMA_TODEVICE);
1107                         err = pci_dma_mapping_error(qdev->pdev, map);
1108                         if (err) {
1109                                 QPRINTK(qdev, TX_QUEUED, ERR,
1110                                         "PCI mapping outbound address list with error: %d\n",
1111                                         err);
1112                                 goto map_error;
1113                         }
1114
1115                         tbd->addr = cpu_to_le64(map);
1116                         /*
1117                          * The length is the number of fragments
1118                          * that remain to be mapped times the length
1119                          * of our sglist (OAL).
1120                          */
1121                         tbd->len =
1122                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1123                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1124                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1125                                            map);
1126                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1127                                           sizeof(struct oal));
1128                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1129                         map_idx++;
1130                 }
1131
1132                 map =
1133                     pci_map_page(qdev->pdev, frag->page,
1134                                  frag->page_offset, frag->size,
1135                                  PCI_DMA_TODEVICE);
1136
1137                 err = pci_dma_mapping_error(qdev->pdev, map);
1138                 if (err) {
1139                         QPRINTK(qdev, TX_QUEUED, ERR,
1140                                 "PCI mapping frags failed with error: %d.\n",
1141                                 err);
1142                         goto map_error;
1143                 }
1144
1145                 tbd->addr = cpu_to_le64(map);
1146                 tbd->len = cpu_to_le32(frag->size);
1147                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1148                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1149                                   frag->size);
1150
1151         }
1152         /* Save the number of segments we've mapped. */
1153         tx_ring_desc->map_cnt = map_idx;
1154         /* Terminate the last segment. */
1155         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1156         return NETDEV_TX_OK;
1157
1158 map_error:
1159         /*
1160          * If the first frag mapping failed, then i will be zero.
1161          * This causes the unmap of the skb->data area.  Otherwise
1162          * we pass in the number of frags that mapped successfully
1163          * so they can be umapped.
1164          */
1165         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1166         return NETDEV_TX_BUSY;
1167 }
1168
1169 static void ql_realign_skb(struct sk_buff *skb, int len)
1170 {
1171         void *temp_addr = skb->data;
1172
1173         /* Undo the skb_reserve(skb,32) we did before
1174          * giving to hardware, and realign data on
1175          * a 2-byte boundary.
1176          */
1177         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1178         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1179         skb_copy_to_linear_data(skb, temp_addr,
1180                 (unsigned int)len);
1181 }
1182
1183 /*
1184  * This function builds an skb for the given inbound
1185  * completion.  It will be rewritten for readability in the near
1186  * future, but for not it works well.
1187  */
1188 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1189                                        struct rx_ring *rx_ring,
1190                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1191 {
1192         struct bq_desc *lbq_desc;
1193         struct bq_desc *sbq_desc;
1194         struct sk_buff *skb = NULL;
1195         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1196        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1197
1198         /*
1199          * Handle the header buffer if present.
1200          */
1201         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1202             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1203                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1204                 /*
1205                  * Headers fit nicely into a small buffer.
1206                  */
1207                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1208                 pci_unmap_single(qdev->pdev,
1209                                 pci_unmap_addr(sbq_desc, mapaddr),
1210                                 pci_unmap_len(sbq_desc, maplen),
1211                                 PCI_DMA_FROMDEVICE);
1212                 skb = sbq_desc->p.skb;
1213                 ql_realign_skb(skb, hdr_len);
1214                 skb_put(skb, hdr_len);
1215                 sbq_desc->p.skb = NULL;
1216         }
1217
1218         /*
1219          * Handle the data buffer(s).
1220          */
1221         if (unlikely(!length)) {        /* Is there data too? */
1222                 QPRINTK(qdev, RX_STATUS, DEBUG,
1223                         "No Data buffer in this packet.\n");
1224                 return skb;
1225         }
1226
1227         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1228                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1229                         QPRINTK(qdev, RX_STATUS, DEBUG,
1230                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1231                         /*
1232                          * Data is less than small buffer size so it's
1233                          * stuffed in a small buffer.
1234                          * For this case we append the data
1235                          * from the "data" small buffer to the "header" small
1236                          * buffer.
1237                          */
1238                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1239                         pci_dma_sync_single_for_cpu(qdev->pdev,
1240                                                     pci_unmap_addr
1241                                                     (sbq_desc, mapaddr),
1242                                                     pci_unmap_len
1243                                                     (sbq_desc, maplen),
1244                                                     PCI_DMA_FROMDEVICE);
1245                         memcpy(skb_put(skb, length),
1246                                sbq_desc->p.skb->data, length);
1247                         pci_dma_sync_single_for_device(qdev->pdev,
1248                                                        pci_unmap_addr
1249                                                        (sbq_desc,
1250                                                         mapaddr),
1251                                                        pci_unmap_len
1252                                                        (sbq_desc,
1253                                                         maplen),
1254                                                        PCI_DMA_FROMDEVICE);
1255                 } else {
1256                         QPRINTK(qdev, RX_STATUS, DEBUG,
1257                                 "%d bytes in a single small buffer.\n", length);
1258                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1259                         skb = sbq_desc->p.skb;
1260                         ql_realign_skb(skb, length);
1261                         skb_put(skb, length);
1262                         pci_unmap_single(qdev->pdev,
1263                                          pci_unmap_addr(sbq_desc,
1264                                                         mapaddr),
1265                                          pci_unmap_len(sbq_desc,
1266                                                        maplen),
1267                                          PCI_DMA_FROMDEVICE);
1268                         sbq_desc->p.skb = NULL;
1269                 }
1270         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1271                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1272                         QPRINTK(qdev, RX_STATUS, DEBUG,
1273                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1274                         /*
1275                          * The data is in a single large buffer.  We
1276                          * chain it to the header buffer's skb and let
1277                          * it rip.
1278                          */
1279                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1280                         pci_unmap_page(qdev->pdev,
1281                                        pci_unmap_addr(lbq_desc,
1282                                                       mapaddr),
1283                                        pci_unmap_len(lbq_desc, maplen),
1284                                        PCI_DMA_FROMDEVICE);
1285                         QPRINTK(qdev, RX_STATUS, DEBUG,
1286                                 "Chaining page to skb.\n");
1287                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1288                                            0, length);
1289                         skb->len += length;
1290                         skb->data_len += length;
1291                         skb->truesize += length;
1292                         lbq_desc->p.lbq_page = NULL;
1293                 } else {
1294                         /*
1295                          * The headers and data are in a single large buffer. We
1296                          * copy it to a new skb and let it go. This can happen with
1297                          * jumbo mtu on a non-TCP/UDP frame.
1298                          */
1299                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1300                         skb = netdev_alloc_skb(qdev->ndev, length);
1301                         if (skb == NULL) {
1302                                 QPRINTK(qdev, PROBE, DEBUG,
1303                                         "No skb available, drop the packet.\n");
1304                                 return NULL;
1305                         }
1306                         skb_reserve(skb, NET_IP_ALIGN);
1307                         QPRINTK(qdev, RX_STATUS, DEBUG,
1308                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1309                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1310                                            0, length);
1311                         skb->len += length;
1312                         skb->data_len += length;
1313                         skb->truesize += length;
1314                         length -= length;
1315                         lbq_desc->p.lbq_page = NULL;
1316                         __pskb_pull_tail(skb,
1317                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1318                                 VLAN_ETH_HLEN : ETH_HLEN);
1319                 }
1320         } else {
1321                 /*
1322                  * The data is in a chain of large buffers
1323                  * pointed to by a small buffer.  We loop
1324                  * thru and chain them to the our small header
1325                  * buffer's skb.
1326                  * frags:  There are 18 max frags and our small
1327                  *         buffer will hold 32 of them. The thing is,
1328                  *         we'll use 3 max for our 9000 byte jumbo
1329                  *         frames.  If the MTU goes up we could
1330                  *          eventually be in trouble.
1331                  */
1332                 int size, offset, i = 0;
1333                 struct bq_element *bq, bq_array[8];
1334                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1335                 pci_unmap_single(qdev->pdev,
1336                                  pci_unmap_addr(sbq_desc, mapaddr),
1337                                  pci_unmap_len(sbq_desc, maplen),
1338                                  PCI_DMA_FROMDEVICE);
1339                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1340                         /*
1341                          * This is an non TCP/UDP IP frame, so
1342                          * the headers aren't split into a small
1343                          * buffer.  We have to use the small buffer
1344                          * that contains our sg list as our skb to
1345                          * send upstairs. Copy the sg list here to
1346                          * a local buffer and use it to find the
1347                          * pages to chain.
1348                          */
1349                         QPRINTK(qdev, RX_STATUS, DEBUG,
1350                                 "%d bytes of headers & data in chain of large.\n", length);
1351                         skb = sbq_desc->p.skb;
1352                         bq = &bq_array[0];
1353                         memcpy(bq, skb->data, sizeof(bq_array));
1354                         sbq_desc->p.skb = NULL;
1355                         skb_reserve(skb, NET_IP_ALIGN);
1356                 } else {
1357                         QPRINTK(qdev, RX_STATUS, DEBUG,
1358                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1359                         bq = (struct bq_element *)sbq_desc->p.skb->data;
1360                 }
1361                 while (length > 0) {
1362                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1363                         if ((bq->addr_lo & ~BQ_MASK) != lbq_desc->bq->addr_lo) {
1364                                 QPRINTK(qdev, RX_STATUS, ERR,
1365                                         "Panic!!! bad large buffer address, expected 0x%.08x, got 0x%.08x.\n",
1366                                         lbq_desc->bq->addr_lo, bq->addr_lo);
1367                                 return NULL;
1368                         }
1369                         pci_unmap_page(qdev->pdev,
1370                                        pci_unmap_addr(lbq_desc,
1371                                                       mapaddr),
1372                                        pci_unmap_len(lbq_desc,
1373                                                      maplen),
1374                                        PCI_DMA_FROMDEVICE);
1375                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1376                         offset = 0;
1377
1378                         QPRINTK(qdev, RX_STATUS, DEBUG,
1379                                 "Adding page %d to skb for %d bytes.\n",
1380                                 i, size);
1381                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1382                                            offset, size);
1383                         skb->len += size;
1384                         skb->data_len += size;
1385                         skb->truesize += size;
1386                         length -= size;
1387                         lbq_desc->p.lbq_page = NULL;
1388                         bq++;
1389                         i++;
1390                 }
1391                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1392                                 VLAN_ETH_HLEN : ETH_HLEN);
1393         }
1394         return skb;
1395 }
1396
1397 /* Process an inbound completion from an rx ring. */
1398 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1399                                    struct rx_ring *rx_ring,
1400                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1401 {
1402         struct net_device *ndev = qdev->ndev;
1403         struct sk_buff *skb = NULL;
1404
1405         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1406
1407         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1408         if (unlikely(!skb)) {
1409                 QPRINTK(qdev, RX_STATUS, DEBUG,
1410                         "No skb available, drop packet.\n");
1411                 return;
1412         }
1413
1414         prefetch(skb->data);
1415         skb->dev = ndev;
1416         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1417                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1418                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1419                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1420                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1421                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1422                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1423                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1424         }
1425         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1426                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1427         }
1428         if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) {
1429                 QPRINTK(qdev, RX_STATUS, ERR,
1430                         "Bad checksum for this %s packet.\n",
1431                         ((ib_mac_rsp->
1432                           flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP"));
1433                 skb->ip_summed = CHECKSUM_NONE;
1434         } else if (qdev->rx_csum &&
1435                    ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ||
1436                     ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1437                      !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) {
1438                 QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n");
1439                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1440         }
1441         qdev->stats.rx_packets++;
1442         qdev->stats.rx_bytes += skb->len;
1443         skb->protocol = eth_type_trans(skb, ndev);
1444         if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1445                 QPRINTK(qdev, RX_STATUS, DEBUG,
1446                         "Passing a VLAN packet upstream.\n");
1447                 vlan_hwaccel_rx(skb, qdev->vlgrp,
1448                                 le16_to_cpu(ib_mac_rsp->vlan_id));
1449         } else {
1450                 QPRINTK(qdev, RX_STATUS, DEBUG,
1451                         "Passing a normal packet upstream.\n");
1452                 netif_rx(skb);
1453         }
1454 }
1455
1456 /* Process an outbound completion from an rx ring. */
1457 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1458                                    struct ob_mac_iocb_rsp *mac_rsp)
1459 {
1460         struct tx_ring *tx_ring;
1461         struct tx_ring_desc *tx_ring_desc;
1462
1463         QL_DUMP_OB_MAC_RSP(mac_rsp);
1464         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1465         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1466         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1467         qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1468         qdev->stats.tx_packets++;
1469         dev_kfree_skb(tx_ring_desc->skb);
1470         tx_ring_desc->skb = NULL;
1471
1472         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1473                                         OB_MAC_IOCB_RSP_S |
1474                                         OB_MAC_IOCB_RSP_L |
1475                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1476                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1477                         QPRINTK(qdev, TX_DONE, WARNING,
1478                                 "Total descriptor length did not match transfer length.\n");
1479                 }
1480                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1481                         QPRINTK(qdev, TX_DONE, WARNING,
1482                                 "Frame too short to be legal, not sent.\n");
1483                 }
1484                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1485                         QPRINTK(qdev, TX_DONE, WARNING,
1486                                 "Frame too long, but sent anyway.\n");
1487                 }
1488                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1489                         QPRINTK(qdev, TX_DONE, WARNING,
1490                                 "PCI backplane error. Frame not sent.\n");
1491                 }
1492         }
1493         atomic_inc(&tx_ring->tx_count);
1494 }
1495
1496 /* Fire up a handler to reset the MPI processor. */
1497 void ql_queue_fw_error(struct ql_adapter *qdev)
1498 {
1499         netif_stop_queue(qdev->ndev);
1500         netif_carrier_off(qdev->ndev);
1501         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1502 }
1503
1504 void ql_queue_asic_error(struct ql_adapter *qdev)
1505 {
1506         netif_stop_queue(qdev->ndev);
1507         netif_carrier_off(qdev->ndev);
1508         ql_disable_interrupts(qdev);
1509         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1510 }
1511
1512 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1513                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1514 {
1515         switch (ib_ae_rsp->event) {
1516         case MGMT_ERR_EVENT:
1517                 QPRINTK(qdev, RX_ERR, ERR,
1518                         "Management Processor Fatal Error.\n");
1519                 ql_queue_fw_error(qdev);
1520                 return;
1521
1522         case CAM_LOOKUP_ERR_EVENT:
1523                 QPRINTK(qdev, LINK, ERR,
1524                         "Multiple CAM hits lookup occurred.\n");
1525                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1526                 ql_queue_asic_error(qdev);
1527                 return;
1528
1529         case SOFT_ECC_ERROR_EVENT:
1530                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1531                 ql_queue_asic_error(qdev);
1532                 break;
1533
1534         case PCI_ERR_ANON_BUF_RD:
1535                 QPRINTK(qdev, RX_ERR, ERR,
1536                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1537                         ib_ae_rsp->q_id);
1538                 ql_queue_asic_error(qdev);
1539                 break;
1540
1541         default:
1542                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1543                         ib_ae_rsp->event);
1544                 ql_queue_asic_error(qdev);
1545                 break;
1546         }
1547 }
1548
1549 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1550 {
1551         struct ql_adapter *qdev = rx_ring->qdev;
1552         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1553         struct ob_mac_iocb_rsp *net_rsp = NULL;
1554         int count = 0;
1555
1556         /* While there are entries in the completion queue. */
1557         while (prod != rx_ring->cnsmr_idx) {
1558
1559                 QPRINTK(qdev, RX_STATUS, DEBUG,
1560                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1561                         prod, rx_ring->cnsmr_idx);
1562
1563                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1564                 rmb();
1565                 switch (net_rsp->opcode) {
1566
1567                 case OPCODE_OB_MAC_TSO_IOCB:
1568                 case OPCODE_OB_MAC_IOCB:
1569                         ql_process_mac_tx_intr(qdev, net_rsp);
1570                         break;
1571                 default:
1572                         QPRINTK(qdev, RX_STATUS, DEBUG,
1573                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1574                                 net_rsp->opcode);
1575                 }
1576                 count++;
1577                 ql_update_cq(rx_ring);
1578                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1579         }
1580         ql_write_cq_idx(rx_ring);
1581         if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1582                 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1583                 if (atomic_read(&tx_ring->queue_stopped) &&
1584                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1585                         /*
1586                          * The queue got stopped because the tx_ring was full.
1587                          * Wake it up, because it's now at least 25% empty.
1588                          */
1589                         netif_wake_queue(qdev->ndev);
1590         }
1591
1592         return count;
1593 }
1594
1595 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1596 {
1597         struct ql_adapter *qdev = rx_ring->qdev;
1598         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1599         struct ql_net_rsp_iocb *net_rsp;
1600         int count = 0;
1601
1602         /* While there are entries in the completion queue. */
1603         while (prod != rx_ring->cnsmr_idx) {
1604
1605                 QPRINTK(qdev, RX_STATUS, DEBUG,
1606                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1607                         prod, rx_ring->cnsmr_idx);
1608
1609                 net_rsp = rx_ring->curr_entry;
1610                 rmb();
1611                 switch (net_rsp->opcode) {
1612                 case OPCODE_IB_MAC_IOCB:
1613                         ql_process_mac_rx_intr(qdev, rx_ring,
1614                                                (struct ib_mac_iocb_rsp *)
1615                                                net_rsp);
1616                         break;
1617
1618                 case OPCODE_IB_AE_IOCB:
1619                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1620                                                 net_rsp);
1621                         break;
1622                 default:
1623                         {
1624                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1625                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1626                                         net_rsp->opcode);
1627                         }
1628                 }
1629                 count++;
1630                 ql_update_cq(rx_ring);
1631                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1632                 if (count == budget)
1633                         break;
1634         }
1635         ql_update_buffer_queues(qdev, rx_ring);
1636         ql_write_cq_idx(rx_ring);
1637         return count;
1638 }
1639
1640 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1641 {
1642         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1643         struct ql_adapter *qdev = rx_ring->qdev;
1644         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1645
1646         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1647                 rx_ring->cq_id);
1648
1649         if (work_done < budget) {
1650                 __netif_rx_complete(napi);
1651                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1652         }
1653         return work_done;
1654 }
1655
1656 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1657 {
1658         struct ql_adapter *qdev = netdev_priv(ndev);
1659
1660         qdev->vlgrp = grp;
1661         if (grp) {
1662                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1663                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1664                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1665         } else {
1666                 QPRINTK(qdev, IFUP, DEBUG,
1667                         "Turning off VLAN in NIC_RCV_CFG.\n");
1668                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1669         }
1670 }
1671
1672 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1673 {
1674         struct ql_adapter *qdev = netdev_priv(ndev);
1675         u32 enable_bit = MAC_ADDR_E;
1676
1677         spin_lock(&qdev->hw_lock);
1678         if (ql_set_mac_addr_reg
1679             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1680                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1681         }
1682         spin_unlock(&qdev->hw_lock);
1683 }
1684
1685 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1686 {
1687         struct ql_adapter *qdev = netdev_priv(ndev);
1688         u32 enable_bit = 0;
1689
1690         spin_lock(&qdev->hw_lock);
1691         if (ql_set_mac_addr_reg
1692             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1693                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1694         }
1695         spin_unlock(&qdev->hw_lock);
1696
1697 }
1698
1699 /* Worker thread to process a given rx_ring that is dedicated
1700  * to outbound completions.
1701  */
1702 static void ql_tx_clean(struct work_struct *work)
1703 {
1704         struct rx_ring *rx_ring =
1705             container_of(work, struct rx_ring, rx_work.work);
1706         ql_clean_outbound_rx_ring(rx_ring);
1707         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1708
1709 }
1710
1711 /* Worker thread to process a given rx_ring that is dedicated
1712  * to inbound completions.
1713  */
1714 static void ql_rx_clean(struct work_struct *work)
1715 {
1716         struct rx_ring *rx_ring =
1717             container_of(work, struct rx_ring, rx_work.work);
1718         ql_clean_inbound_rx_ring(rx_ring, 64);
1719         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1720 }
1721
1722 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1723 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1724 {
1725         struct rx_ring *rx_ring = dev_id;
1726         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1727                               &rx_ring->rx_work, 0);
1728         return IRQ_HANDLED;
1729 }
1730
1731 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1732 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1733 {
1734         struct rx_ring *rx_ring = dev_id;
1735         netif_rx_schedule(&rx_ring->napi);
1736         return IRQ_HANDLED;
1737 }
1738
1739 /* This handles a fatal error, MPI activity, and the default
1740  * rx_ring in an MSI-X multiple vector environment.
1741  * In MSI/Legacy environment it also process the rest of
1742  * the rx_rings.
1743  */
1744 static irqreturn_t qlge_isr(int irq, void *dev_id)
1745 {
1746         struct rx_ring *rx_ring = dev_id;
1747         struct ql_adapter *qdev = rx_ring->qdev;
1748         struct intr_context *intr_context = &qdev->intr_context[0];
1749         u32 var;
1750         int i;
1751         int work_done = 0;
1752
1753         spin_lock(&qdev->hw_lock);
1754         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1755                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1756                 spin_unlock(&qdev->hw_lock);
1757                 return IRQ_NONE;
1758         }
1759         spin_unlock(&qdev->hw_lock);
1760
1761         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1762
1763         /*
1764          * Check for fatal error.
1765          */
1766         if (var & STS_FE) {
1767                 ql_queue_asic_error(qdev);
1768                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1769                 var = ql_read32(qdev, ERR_STS);
1770                 QPRINTK(qdev, INTR, ERR,
1771                         "Resetting chip. Error Status Register = 0x%x\n", var);
1772                 return IRQ_HANDLED;
1773         }
1774
1775         /*
1776          * Check MPI processor activity.
1777          */
1778         if (var & STS_PI) {
1779                 /*
1780                  * We've got an async event or mailbox completion.
1781                  * Handle it and clear the source of the interrupt.
1782                  */
1783                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1784                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1785                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1786                                       &qdev->mpi_work, 0);
1787                 work_done++;
1788         }
1789
1790         /*
1791          * Check the default queue and wake handler if active.
1792          */
1793         rx_ring = &qdev->rx_ring[0];
1794         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1795                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1796                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1797                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1798                                       &rx_ring->rx_work, 0);
1799                 work_done++;
1800         }
1801
1802         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1803                 /*
1804                  * Start the DPC for each active queue.
1805                  */
1806                 for (i = 1; i < qdev->rx_ring_count; i++) {
1807                         rx_ring = &qdev->rx_ring[i];
1808                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1809                             rx_ring->cnsmr_idx) {
1810                                 QPRINTK(qdev, INTR, INFO,
1811                                         "Waking handler for rx_ring[%d].\n", i);
1812                                 ql_disable_completion_interrupt(qdev,
1813                                                                 intr_context->
1814                                                                 intr);
1815                                 if (i < qdev->rss_ring_first_cq_id)
1816                                         queue_delayed_work_on(rx_ring->cpu,
1817                                                               qdev->q_workqueue,
1818                                                               &rx_ring->rx_work,
1819                                                               0);
1820                                 else
1821                                         netif_rx_schedule(&rx_ring->napi);
1822                                 work_done++;
1823                         }
1824                 }
1825         }
1826         ql_enable_completion_interrupt(qdev, intr_context->intr);
1827         return work_done ? IRQ_HANDLED : IRQ_NONE;
1828 }
1829
1830 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1831 {
1832
1833         if (skb_is_gso(skb)) {
1834                 int err;
1835                 if (skb_header_cloned(skb)) {
1836                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1837                         if (err)
1838                                 return err;
1839                 }
1840
1841                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1842                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1843                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1844                 mac_iocb_ptr->total_hdrs_len =
1845                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1846                 mac_iocb_ptr->net_trans_offset =
1847                     cpu_to_le16(skb_network_offset(skb) |
1848                                 skb_transport_offset(skb)
1849                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
1850                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1851                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1852                 if (likely(skb->protocol == htons(ETH_P_IP))) {
1853                         struct iphdr *iph = ip_hdr(skb);
1854                         iph->check = 0;
1855                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1856                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1857                                                                  iph->daddr, 0,
1858                                                                  IPPROTO_TCP,
1859                                                                  0);
1860                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1861                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
1862                         tcp_hdr(skb)->check =
1863                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
1864                                              &ipv6_hdr(skb)->daddr,
1865                                              0, IPPROTO_TCP, 0);
1866                 }
1867                 return 1;
1868         }
1869         return 0;
1870 }
1871
1872 static void ql_hw_csum_setup(struct sk_buff *skb,
1873                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1874 {
1875         int len;
1876         struct iphdr *iph = ip_hdr(skb);
1877         u16 *check;
1878         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1879         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1880         mac_iocb_ptr->net_trans_offset =
1881                 cpu_to_le16(skb_network_offset(skb) |
1882                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
1883
1884         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1885         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
1886         if (likely(iph->protocol == IPPROTO_TCP)) {
1887                 check = &(tcp_hdr(skb)->check);
1888                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
1889                 mac_iocb_ptr->total_hdrs_len =
1890                     cpu_to_le16(skb_transport_offset(skb) +
1891                                 (tcp_hdr(skb)->doff << 2));
1892         } else {
1893                 check = &(udp_hdr(skb)->check);
1894                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
1895                 mac_iocb_ptr->total_hdrs_len =
1896                     cpu_to_le16(skb_transport_offset(skb) +
1897                                 sizeof(struct udphdr));
1898         }
1899         *check = ~csum_tcpudp_magic(iph->saddr,
1900                                     iph->daddr, len, iph->protocol, 0);
1901 }
1902
1903 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
1904 {
1905         struct tx_ring_desc *tx_ring_desc;
1906         struct ob_mac_iocb_req *mac_iocb_ptr;
1907         struct ql_adapter *qdev = netdev_priv(ndev);
1908         int tso;
1909         struct tx_ring *tx_ring;
1910         u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
1911
1912         tx_ring = &qdev->tx_ring[tx_ring_idx];
1913
1914         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
1915                 QPRINTK(qdev, TX_QUEUED, INFO,
1916                         "%s: shutting down tx queue %d du to lack of resources.\n",
1917                         __func__, tx_ring_idx);
1918                 netif_stop_queue(ndev);
1919                 atomic_inc(&tx_ring->queue_stopped);
1920                 return NETDEV_TX_BUSY;
1921         }
1922         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
1923         mac_iocb_ptr = tx_ring_desc->queue_entry;
1924         memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
1925         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) != NETDEV_TX_OK) {
1926                 QPRINTK(qdev, TX_QUEUED, ERR, "Could not map the segments.\n");
1927                 return NETDEV_TX_BUSY;
1928         }
1929
1930         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
1931         mac_iocb_ptr->tid = tx_ring_desc->index;
1932         /* We use the upper 32-bits to store the tx queue for this IO.
1933          * When we get the completion we can use it to establish the context.
1934          */
1935         mac_iocb_ptr->txq_idx = tx_ring_idx;
1936         tx_ring_desc->skb = skb;
1937
1938         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
1939
1940         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
1941                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
1942                         vlan_tx_tag_get(skb));
1943                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
1944                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
1945         }
1946         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1947         if (tso < 0) {
1948                 dev_kfree_skb_any(skb);
1949                 return NETDEV_TX_OK;
1950         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
1951                 ql_hw_csum_setup(skb,
1952                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
1953         }
1954         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
1955         tx_ring->prod_idx++;
1956         if (tx_ring->prod_idx == tx_ring->wq_len)
1957                 tx_ring->prod_idx = 0;
1958         wmb();
1959
1960         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
1961         ndev->trans_start = jiffies;
1962         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
1963                 tx_ring->prod_idx, skb->len);
1964
1965         atomic_dec(&tx_ring->tx_count);
1966         return NETDEV_TX_OK;
1967 }
1968
1969 static void ql_free_shadow_space(struct ql_adapter *qdev)
1970 {
1971         if (qdev->rx_ring_shadow_reg_area) {
1972                 pci_free_consistent(qdev->pdev,
1973                                     PAGE_SIZE,
1974                                     qdev->rx_ring_shadow_reg_area,
1975                                     qdev->rx_ring_shadow_reg_dma);
1976                 qdev->rx_ring_shadow_reg_area = NULL;
1977         }
1978         if (qdev->tx_ring_shadow_reg_area) {
1979                 pci_free_consistent(qdev->pdev,
1980                                     PAGE_SIZE,
1981                                     qdev->tx_ring_shadow_reg_area,
1982                                     qdev->tx_ring_shadow_reg_dma);
1983                 qdev->tx_ring_shadow_reg_area = NULL;
1984         }
1985 }
1986
1987 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
1988 {
1989         qdev->rx_ring_shadow_reg_area =
1990             pci_alloc_consistent(qdev->pdev,
1991                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
1992         if (qdev->rx_ring_shadow_reg_area == NULL) {
1993                 QPRINTK(qdev, IFUP, ERR,
1994                         "Allocation of RX shadow space failed.\n");
1995                 return -ENOMEM;
1996         }
1997         qdev->tx_ring_shadow_reg_area =
1998             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
1999                                  &qdev->tx_ring_shadow_reg_dma);
2000         if (qdev->tx_ring_shadow_reg_area == NULL) {
2001                 QPRINTK(qdev, IFUP, ERR,
2002                         "Allocation of TX shadow space failed.\n");
2003                 goto err_wqp_sh_area;
2004         }
2005         return 0;
2006
2007 err_wqp_sh_area:
2008         pci_free_consistent(qdev->pdev,
2009                             PAGE_SIZE,
2010                             qdev->rx_ring_shadow_reg_area,
2011                             qdev->rx_ring_shadow_reg_dma);
2012         return -ENOMEM;
2013 }
2014
2015 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2016 {
2017         struct tx_ring_desc *tx_ring_desc;
2018         int i;
2019         struct ob_mac_iocb_req *mac_iocb_ptr;
2020
2021         mac_iocb_ptr = tx_ring->wq_base;
2022         tx_ring_desc = tx_ring->q;
2023         for (i = 0; i < tx_ring->wq_len; i++) {
2024                 tx_ring_desc->index = i;
2025                 tx_ring_desc->skb = NULL;
2026                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2027                 mac_iocb_ptr++;
2028                 tx_ring_desc++;
2029         }
2030         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2031         atomic_set(&tx_ring->queue_stopped, 0);
2032 }
2033
2034 static void ql_free_tx_resources(struct ql_adapter *qdev,
2035                                  struct tx_ring *tx_ring)
2036 {
2037         if (tx_ring->wq_base) {
2038                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2039                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2040                 tx_ring->wq_base = NULL;
2041         }
2042         kfree(tx_ring->q);
2043         tx_ring->q = NULL;
2044 }
2045
2046 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2047                                  struct tx_ring *tx_ring)
2048 {
2049         tx_ring->wq_base =
2050             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2051                                  &tx_ring->wq_base_dma);
2052
2053         if ((tx_ring->wq_base == NULL)
2054             || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2055                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2056                 return -ENOMEM;
2057         }
2058         tx_ring->q =
2059             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2060         if (tx_ring->q == NULL)
2061                 goto err;
2062
2063         return 0;
2064 err:
2065         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2066                             tx_ring->wq_base, tx_ring->wq_base_dma);
2067         return -ENOMEM;
2068 }
2069
2070 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2071 {
2072         int i;
2073         struct bq_desc *lbq_desc;
2074
2075         for (i = 0; i < rx_ring->lbq_len; i++) {
2076                 lbq_desc = &rx_ring->lbq[i];
2077                 if (lbq_desc->p.lbq_page) {
2078                         pci_unmap_page(qdev->pdev,
2079                                        pci_unmap_addr(lbq_desc, mapaddr),
2080                                        pci_unmap_len(lbq_desc, maplen),
2081                                        PCI_DMA_FROMDEVICE);
2082
2083                         put_page(lbq_desc->p.lbq_page);
2084                         lbq_desc->p.lbq_page = NULL;
2085                 }
2086                 lbq_desc->bq->addr_lo = 0;
2087                 lbq_desc->bq->addr_hi = 0;
2088         }
2089 }
2090
2091 /*
2092  * Allocate and map a page for each element of the lbq.
2093  */
2094 static int ql_alloc_lbq_buffers(struct ql_adapter *qdev,
2095                                 struct rx_ring *rx_ring)
2096 {
2097         int i;
2098         struct bq_desc *lbq_desc;
2099         u64 map;
2100         struct bq_element *bq = rx_ring->lbq_base;
2101
2102         for (i = 0; i < rx_ring->lbq_len; i++) {
2103                 lbq_desc = &rx_ring->lbq[i];
2104                 memset(lbq_desc, 0, sizeof(lbq_desc));
2105                 lbq_desc->bq = bq;
2106                 lbq_desc->index = i;
2107                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
2108                 if (unlikely(!lbq_desc->p.lbq_page)) {
2109                         QPRINTK(qdev, IFUP, ERR, "failed alloc_page().\n");
2110                         goto mem_error;
2111                 } else {
2112                         map = pci_map_page(qdev->pdev,
2113                                            lbq_desc->p.lbq_page,
2114                                            0, PAGE_SIZE, PCI_DMA_FROMDEVICE);
2115                         if (pci_dma_mapping_error(qdev->pdev, map)) {
2116                                 QPRINTK(qdev, IFUP, ERR,
2117                                         "PCI mapping failed.\n");
2118                                 goto mem_error;
2119                         }
2120                         pci_unmap_addr_set(lbq_desc, mapaddr, map);
2121                         pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
2122                         bq->addr_lo = cpu_to_le32(map);
2123                         bq->addr_hi = cpu_to_le32(map >> 32);
2124                 }
2125                 bq++;
2126         }
2127         return 0;
2128 mem_error:
2129         ql_free_lbq_buffers(qdev, rx_ring);
2130         return -ENOMEM;
2131 }
2132
2133 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2134 {
2135         int i;
2136         struct bq_desc *sbq_desc;
2137
2138         for (i = 0; i < rx_ring->sbq_len; i++) {
2139                 sbq_desc = &rx_ring->sbq[i];
2140                 if (sbq_desc == NULL) {
2141                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2142                         return;
2143                 }
2144                 if (sbq_desc->p.skb) {
2145                         pci_unmap_single(qdev->pdev,
2146                                          pci_unmap_addr(sbq_desc, mapaddr),
2147                                          pci_unmap_len(sbq_desc, maplen),
2148                                          PCI_DMA_FROMDEVICE);
2149                         dev_kfree_skb(sbq_desc->p.skb);
2150                         sbq_desc->p.skb = NULL;
2151                 }
2152                 if (sbq_desc->bq == NULL) {
2153                         QPRINTK(qdev, IFUP, ERR, "sbq_desc->bq %d is NULL.\n",
2154                                 i);
2155                         return;
2156                 }
2157                 sbq_desc->bq->addr_lo = 0;
2158                 sbq_desc->bq->addr_hi = 0;
2159         }
2160 }
2161
2162 /* Allocate and map an skb for each element of the sbq. */
2163 static int ql_alloc_sbq_buffers(struct ql_adapter *qdev,
2164                                 struct rx_ring *rx_ring)
2165 {
2166         int i;
2167         struct bq_desc *sbq_desc;
2168         struct sk_buff *skb;
2169         u64 map;
2170         struct bq_element *bq = rx_ring->sbq_base;
2171
2172         for (i = 0; i < rx_ring->sbq_len; i++) {
2173                 sbq_desc = &rx_ring->sbq[i];
2174                 memset(sbq_desc, 0, sizeof(sbq_desc));
2175                 sbq_desc->index = i;
2176                 sbq_desc->bq = bq;
2177                 skb = netdev_alloc_skb(qdev->ndev, rx_ring->sbq_buf_size);
2178                 if (unlikely(!skb)) {
2179                         /* Better luck next round */
2180                         QPRINTK(qdev, IFUP, ERR,
2181                                 "small buff alloc failed for %d bytes at index %d.\n",
2182                                 rx_ring->sbq_buf_size, i);
2183                         goto mem_err;
2184                 }
2185                 skb_reserve(skb, QLGE_SB_PAD);
2186                 sbq_desc->p.skb = skb;
2187                 /*
2188                  * Map only half the buffer. Because the
2189                  * other half may get some data copied to it
2190                  * when the completion arrives.
2191                  */
2192                 map = pci_map_single(qdev->pdev,
2193                                      skb->data,
2194                                      rx_ring->sbq_buf_size / 2,
2195                                      PCI_DMA_FROMDEVICE);
2196                 if (pci_dma_mapping_error(qdev->pdev, map)) {
2197                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
2198                         goto mem_err;
2199                 }
2200                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
2201                 pci_unmap_len_set(sbq_desc, maplen, rx_ring->sbq_buf_size / 2);
2202                 bq->addr_lo =   /*sbq_desc->addr_lo = */
2203                     cpu_to_le32(map);
2204                 bq->addr_hi =   /*sbq_desc->addr_hi = */
2205                     cpu_to_le32(map >> 32);
2206                 bq++;
2207         }
2208         return 0;
2209 mem_err:
2210         ql_free_sbq_buffers(qdev, rx_ring);
2211         return -ENOMEM;
2212 }
2213
2214 static void ql_free_rx_resources(struct ql_adapter *qdev,
2215                                  struct rx_ring *rx_ring)
2216 {
2217         if (rx_ring->sbq_len)
2218                 ql_free_sbq_buffers(qdev, rx_ring);
2219         if (rx_ring->lbq_len)
2220                 ql_free_lbq_buffers(qdev, rx_ring);
2221
2222         /* Free the small buffer queue. */
2223         if (rx_ring->sbq_base) {
2224                 pci_free_consistent(qdev->pdev,
2225                                     rx_ring->sbq_size,
2226                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2227                 rx_ring->sbq_base = NULL;
2228         }
2229
2230         /* Free the small buffer queue control blocks. */
2231         kfree(rx_ring->sbq);
2232         rx_ring->sbq = NULL;
2233
2234         /* Free the large buffer queue. */
2235         if (rx_ring->lbq_base) {
2236                 pci_free_consistent(qdev->pdev,
2237                                     rx_ring->lbq_size,
2238                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2239                 rx_ring->lbq_base = NULL;
2240         }
2241
2242         /* Free the large buffer queue control blocks. */
2243         kfree(rx_ring->lbq);
2244         rx_ring->lbq = NULL;
2245
2246         /* Free the rx queue. */
2247         if (rx_ring->cq_base) {
2248                 pci_free_consistent(qdev->pdev,
2249                                     rx_ring->cq_size,
2250                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2251                 rx_ring->cq_base = NULL;
2252         }
2253 }
2254
2255 /* Allocate queues and buffers for this completions queue based
2256  * on the values in the parameter structure. */
2257 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2258                                  struct rx_ring *rx_ring)
2259 {
2260
2261         /*
2262          * Allocate the completion queue for this rx_ring.
2263          */
2264         rx_ring->cq_base =
2265             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2266                                  &rx_ring->cq_base_dma);
2267
2268         if (rx_ring->cq_base == NULL) {
2269                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2270                 return -ENOMEM;
2271         }
2272
2273         if (rx_ring->sbq_len) {
2274                 /*
2275                  * Allocate small buffer queue.
2276                  */
2277                 rx_ring->sbq_base =
2278                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2279                                          &rx_ring->sbq_base_dma);
2280
2281                 if (rx_ring->sbq_base == NULL) {
2282                         QPRINTK(qdev, IFUP, ERR,
2283                                 "Small buffer queue allocation failed.\n");
2284                         goto err_mem;
2285                 }
2286
2287                 /*
2288                  * Allocate small buffer queue control blocks.
2289                  */
2290                 rx_ring->sbq =
2291                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2292                             GFP_KERNEL);
2293                 if (rx_ring->sbq == NULL) {
2294                         QPRINTK(qdev, IFUP, ERR,
2295                                 "Small buffer queue control block allocation failed.\n");
2296                         goto err_mem;
2297                 }
2298
2299                 if (ql_alloc_sbq_buffers(qdev, rx_ring)) {
2300                         QPRINTK(qdev, IFUP, ERR,
2301                                 "Small buffer allocation failed.\n");
2302                         goto err_mem;
2303                 }
2304         }
2305
2306         if (rx_ring->lbq_len) {
2307                 /*
2308                  * Allocate large buffer queue.
2309                  */
2310                 rx_ring->lbq_base =
2311                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2312                                          &rx_ring->lbq_base_dma);
2313
2314                 if (rx_ring->lbq_base == NULL) {
2315                         QPRINTK(qdev, IFUP, ERR,
2316                                 "Large buffer queue allocation failed.\n");
2317                         goto err_mem;
2318                 }
2319                 /*
2320                  * Allocate large buffer queue control blocks.
2321                  */
2322                 rx_ring->lbq =
2323                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2324                             GFP_KERNEL);
2325                 if (rx_ring->lbq == NULL) {
2326                         QPRINTK(qdev, IFUP, ERR,
2327                                 "Large buffer queue control block allocation failed.\n");
2328                         goto err_mem;
2329                 }
2330
2331                 /*
2332                  * Allocate the buffers.
2333                  */
2334                 if (ql_alloc_lbq_buffers(qdev, rx_ring)) {
2335                         QPRINTK(qdev, IFUP, ERR,
2336                                 "Large buffer allocation failed.\n");
2337                         goto err_mem;
2338                 }
2339         }
2340
2341         return 0;
2342
2343 err_mem:
2344         ql_free_rx_resources(qdev, rx_ring);
2345         return -ENOMEM;
2346 }
2347
2348 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2349 {
2350         struct tx_ring *tx_ring;
2351         struct tx_ring_desc *tx_ring_desc;
2352         int i, j;
2353
2354         /*
2355          * Loop through all queues and free
2356          * any resources.
2357          */
2358         for (j = 0; j < qdev->tx_ring_count; j++) {
2359                 tx_ring = &qdev->tx_ring[j];
2360                 for (i = 0; i < tx_ring->wq_len; i++) {
2361                         tx_ring_desc = &tx_ring->q[i];
2362                         if (tx_ring_desc && tx_ring_desc->skb) {
2363                                 QPRINTK(qdev, IFDOWN, ERR,
2364                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2365                                         tx_ring_desc->skb, j,
2366                                         tx_ring_desc->index);
2367                                 ql_unmap_send(qdev, tx_ring_desc,
2368                                               tx_ring_desc->map_cnt);
2369                                 dev_kfree_skb(tx_ring_desc->skb);
2370                                 tx_ring_desc->skb = NULL;
2371                         }
2372                 }
2373         }
2374 }
2375
2376 static void ql_free_ring_cb(struct ql_adapter *qdev)
2377 {
2378         kfree(qdev->ring_mem);
2379 }
2380
2381 static int ql_alloc_ring_cb(struct ql_adapter *qdev)
2382 {
2383         /* Allocate space for tx/rx ring control blocks. */
2384         qdev->ring_mem_size =
2385             (qdev->tx_ring_count * sizeof(struct tx_ring)) +
2386             (qdev->rx_ring_count * sizeof(struct rx_ring));
2387         qdev->ring_mem = kmalloc(qdev->ring_mem_size, GFP_KERNEL);
2388         if (qdev->ring_mem == NULL) {
2389                 return -ENOMEM;
2390         } else {
2391                 qdev->rx_ring = qdev->ring_mem;
2392                 qdev->tx_ring = qdev->ring_mem +
2393                     (qdev->rx_ring_count * sizeof(struct rx_ring));
2394         }
2395         return 0;
2396 }
2397
2398 static void ql_free_mem_resources(struct ql_adapter *qdev)
2399 {
2400         int i;
2401
2402         for (i = 0; i < qdev->tx_ring_count; i++)
2403                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2404         for (i = 0; i < qdev->rx_ring_count; i++)
2405                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2406         ql_free_shadow_space(qdev);
2407 }
2408
2409 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2410 {
2411         int i;
2412
2413         /* Allocate space for our shadow registers and such. */
2414         if (ql_alloc_shadow_space(qdev))
2415                 return -ENOMEM;
2416
2417         for (i = 0; i < qdev->rx_ring_count; i++) {
2418                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2419                         QPRINTK(qdev, IFUP, ERR,
2420                                 "RX resource allocation failed.\n");
2421                         goto err_mem;
2422                 }
2423         }
2424         /* Allocate tx queue resources */
2425         for (i = 0; i < qdev->tx_ring_count; i++) {
2426                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2427                         QPRINTK(qdev, IFUP, ERR,
2428                                 "TX resource allocation failed.\n");
2429                         goto err_mem;
2430                 }
2431         }
2432         return 0;
2433
2434 err_mem:
2435         ql_free_mem_resources(qdev);
2436         return -ENOMEM;
2437 }
2438
2439 /* Set up the rx ring control block and pass it to the chip.
2440  * The control block is defined as
2441  * "Completion Queue Initialization Control Block", or cqicb.
2442  */
2443 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2444 {
2445         struct cqicb *cqicb = &rx_ring->cqicb;
2446         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2447             (rx_ring->cq_id * sizeof(u64) * 4);
2448         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2449             (rx_ring->cq_id * sizeof(u64) * 4);
2450         void __iomem *doorbell_area =
2451             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2452         int err = 0;
2453         u16 bq_len;
2454
2455         /* Set up the shadow registers for this ring. */
2456         rx_ring->prod_idx_sh_reg = shadow_reg;
2457         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2458         shadow_reg += sizeof(u64);
2459         shadow_reg_dma += sizeof(u64);
2460         rx_ring->lbq_base_indirect = shadow_reg;
2461         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2462         shadow_reg += sizeof(u64);
2463         shadow_reg_dma += sizeof(u64);
2464         rx_ring->sbq_base_indirect = shadow_reg;
2465         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2466
2467         /* PCI doorbell mem area + 0x00 for consumer index register */
2468         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2469         rx_ring->cnsmr_idx = 0;
2470         rx_ring->curr_entry = rx_ring->cq_base;
2471
2472         /* PCI doorbell mem area + 0x04 for valid register */
2473         rx_ring->valid_db_reg = doorbell_area + 0x04;
2474
2475         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2476         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2477
2478         /* PCI doorbell mem area + 0x1c */
2479         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2480
2481         memset((void *)cqicb, 0, sizeof(struct cqicb));
2482         cqicb->msix_vect = rx_ring->irq;
2483
2484         cqicb->len = cpu_to_le16(rx_ring->cq_len | LEN_V | LEN_CPP_CONT);
2485
2486         cqicb->addr_lo = cpu_to_le32(rx_ring->cq_base_dma);
2487         cqicb->addr_hi = cpu_to_le32((u64) rx_ring->cq_base_dma >> 32);
2488
2489         cqicb->prod_idx_addr_lo = cpu_to_le32(rx_ring->prod_idx_sh_reg_dma);
2490         cqicb->prod_idx_addr_hi =
2491             cpu_to_le32((u64) rx_ring->prod_idx_sh_reg_dma >> 32);
2492
2493         /*
2494          * Set up the control block load flags.
2495          */
2496         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2497             FLAGS_LV |          /* Load MSI-X vector */
2498             FLAGS_LI;           /* Load irq delay values */
2499         if (rx_ring->lbq_len) {
2500                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2501                 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2502                 cqicb->lbq_addr_lo =
2503                     cpu_to_le32(rx_ring->lbq_base_indirect_dma);
2504                 cqicb->lbq_addr_hi =
2505                     cpu_to_le32((u64) rx_ring->lbq_base_indirect_dma >> 32);
2506                 cqicb->lbq_buf_size = cpu_to_le32(rx_ring->lbq_buf_size);
2507                 bq_len = (u16) rx_ring->lbq_len;
2508                 cqicb->lbq_len = cpu_to_le16(bq_len);
2509                 rx_ring->lbq_prod_idx = rx_ring->lbq_len - 16;
2510                 rx_ring->lbq_curr_idx = 0;
2511                 rx_ring->lbq_clean_idx = rx_ring->lbq_prod_idx;
2512                 rx_ring->lbq_free_cnt = 16;
2513         }
2514         if (rx_ring->sbq_len) {
2515                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2516                 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2517                 cqicb->sbq_addr_lo =
2518                     cpu_to_le32(rx_ring->sbq_base_indirect_dma);
2519                 cqicb->sbq_addr_hi =
2520                     cpu_to_le32((u64) rx_ring->sbq_base_indirect_dma >> 32);
2521                 cqicb->sbq_buf_size =
2522                     cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
2523                 bq_len = (u16) rx_ring->sbq_len;
2524                 cqicb->sbq_len = cpu_to_le16(bq_len);
2525                 rx_ring->sbq_prod_idx = rx_ring->sbq_len - 16;
2526                 rx_ring->sbq_curr_idx = 0;
2527                 rx_ring->sbq_clean_idx = rx_ring->sbq_prod_idx;
2528                 rx_ring->sbq_free_cnt = 16;
2529         }
2530         switch (rx_ring->type) {
2531         case TX_Q:
2532                 /* If there's only one interrupt, then we use
2533                  * worker threads to process the outbound
2534                  * completion handling rx_rings. We do this so
2535                  * they can be run on multiple CPUs. There is
2536                  * room to play with this more where we would only
2537                  * run in a worker if there are more than x number
2538                  * of outbound completions on the queue and more
2539                  * than one queue active.  Some threshold that
2540                  * would indicate a benefit in spite of the cost
2541                  * of a context switch.
2542                  * If there's more than one interrupt, then the
2543                  * outbound completions are processed in the ISR.
2544                  */
2545                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2546                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2547                 else {
2548                         /* With all debug warnings on we see a WARN_ON message
2549                          * when we free the skb in the interrupt context.
2550                          */
2551                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2552                 }
2553                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2554                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2555                 break;
2556         case DEFAULT_Q:
2557                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2558                 cqicb->irq_delay = 0;
2559                 cqicb->pkt_delay = 0;
2560                 break;
2561         case RX_Q:
2562                 /* Inbound completion handling rx_rings run in
2563                  * separate NAPI contexts.
2564                  */
2565                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2566                                64);
2567                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2568                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2569                 break;
2570         default:
2571                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2572                         rx_ring->type);
2573         }
2574         QPRINTK(qdev, IFUP, INFO, "Initializing rx work queue.\n");
2575         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2576                            CFG_LCQ, rx_ring->cq_id);
2577         if (err) {
2578                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2579                 return err;
2580         }
2581         QPRINTK(qdev, IFUP, INFO, "Successfully loaded CQICB.\n");
2582         /*
2583          * Advance the producer index for the buffer queues.
2584          */
2585         wmb();
2586         if (rx_ring->lbq_len)
2587                 ql_write_db_reg(rx_ring->lbq_prod_idx,
2588                                 rx_ring->lbq_prod_idx_db_reg);
2589         if (rx_ring->sbq_len)
2590                 ql_write_db_reg(rx_ring->sbq_prod_idx,
2591                                 rx_ring->sbq_prod_idx_db_reg);
2592         return err;
2593 }
2594
2595 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2596 {
2597         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2598         void __iomem *doorbell_area =
2599             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2600         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2601             (tx_ring->wq_id * sizeof(u64));
2602         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2603             (tx_ring->wq_id * sizeof(u64));
2604         int err = 0;
2605
2606         /*
2607          * Assign doorbell registers for this tx_ring.
2608          */
2609         /* TX PCI doorbell mem area for tx producer index */
2610         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2611         tx_ring->prod_idx = 0;
2612         /* TX PCI doorbell mem area + 0x04 */
2613         tx_ring->valid_db_reg = doorbell_area + 0x04;
2614
2615         /*
2616          * Assign shadow registers for this tx_ring.
2617          */
2618         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2619         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2620
2621         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2622         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2623                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2624         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2625         wqicb->rid = 0;
2626         wqicb->addr_lo = cpu_to_le32(tx_ring->wq_base_dma);
2627         wqicb->addr_hi = cpu_to_le32((u64) tx_ring->wq_base_dma >> 32);
2628
2629         wqicb->cnsmr_idx_addr_lo = cpu_to_le32(tx_ring->cnsmr_idx_sh_reg_dma);
2630         wqicb->cnsmr_idx_addr_hi =
2631             cpu_to_le32((u64) tx_ring->cnsmr_idx_sh_reg_dma >> 32);
2632
2633         ql_init_tx_ring(qdev, tx_ring);
2634
2635         err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2636                            (u16) tx_ring->wq_id);
2637         if (err) {
2638                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2639                 return err;
2640         }
2641         QPRINTK(qdev, IFUP, INFO, "Successfully loaded WQICB.\n");
2642         return err;
2643 }
2644
2645 static void ql_disable_msix(struct ql_adapter *qdev)
2646 {
2647         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2648                 pci_disable_msix(qdev->pdev);
2649                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2650                 kfree(qdev->msi_x_entry);
2651                 qdev->msi_x_entry = NULL;
2652         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2653                 pci_disable_msi(qdev->pdev);
2654                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2655         }
2656 }
2657
2658 static void ql_enable_msix(struct ql_adapter *qdev)
2659 {
2660         int i;
2661
2662         qdev->intr_count = 1;
2663         /* Get the MSIX vectors. */
2664         if (irq_type == MSIX_IRQ) {
2665                 /* Try to alloc space for the msix struct,
2666                  * if it fails then go to MSI/legacy.
2667                  */
2668                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2669                                             sizeof(struct msix_entry),
2670                                             GFP_KERNEL);
2671                 if (!qdev->msi_x_entry) {
2672                         irq_type = MSI_IRQ;
2673                         goto msi;
2674                 }
2675
2676                 for (i = 0; i < qdev->rx_ring_count; i++)
2677                         qdev->msi_x_entry[i].entry = i;
2678
2679                 if (!pci_enable_msix
2680                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2681                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2682                         qdev->intr_count = qdev->rx_ring_count;
2683                         QPRINTK(qdev, IFUP, INFO,
2684                                 "MSI-X Enabled, got %d vectors.\n",
2685                                 qdev->intr_count);
2686                         return;
2687                 } else {
2688                         kfree(qdev->msi_x_entry);
2689                         qdev->msi_x_entry = NULL;
2690                         QPRINTK(qdev, IFUP, WARNING,
2691                                 "MSI-X Enable failed, trying MSI.\n");
2692                         irq_type = MSI_IRQ;
2693                 }
2694         }
2695 msi:
2696         if (irq_type == MSI_IRQ) {
2697                 if (!pci_enable_msi(qdev->pdev)) {
2698                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2699                         QPRINTK(qdev, IFUP, INFO,
2700                                 "Running with MSI interrupts.\n");
2701                         return;
2702                 }
2703         }
2704         irq_type = LEG_IRQ;
2705         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2706 }
2707
2708 /*
2709  * Here we build the intr_context structures based on
2710  * our rx_ring count and intr vector count.
2711  * The intr_context structure is used to hook each vector
2712  * to possibly different handlers.
2713  */
2714 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2715 {
2716         int i = 0;
2717         struct intr_context *intr_context = &qdev->intr_context[0];
2718
2719         ql_enable_msix(qdev);
2720
2721         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2722                 /* Each rx_ring has it's
2723                  * own intr_context since we have separate
2724                  * vectors for each queue.
2725                  * This only true when MSI-X is enabled.
2726                  */
2727                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2728                         qdev->rx_ring[i].irq = i;
2729                         intr_context->intr = i;
2730                         intr_context->qdev = qdev;
2731                         /*
2732                          * We set up each vectors enable/disable/read bits so
2733                          * there's no bit/mask calculations in the critical path.
2734                          */
2735                         intr_context->intr_en_mask =
2736                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2737                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2738                             | i;
2739                         intr_context->intr_dis_mask =
2740                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2741                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2742                             INTR_EN_IHD | i;
2743                         intr_context->intr_read_mask =
2744                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2745                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2746                             i;
2747
2748                         if (i == 0) {
2749                                 /*
2750                                  * Default queue handles bcast/mcast plus
2751                                  * async events.  Needs buffers.
2752                                  */
2753                                 intr_context->handler = qlge_isr;
2754                                 sprintf(intr_context->name, "%s-default-queue",
2755                                         qdev->ndev->name);
2756                         } else if (i < qdev->rss_ring_first_cq_id) {
2757                                 /*
2758                                  * Outbound queue is for outbound completions only.
2759                                  */
2760                                 intr_context->handler = qlge_msix_tx_isr;
2761                                 sprintf(intr_context->name, "%s-txq-%d",
2762                                         qdev->ndev->name, i);
2763                         } else {
2764                                 /*
2765                                  * Inbound queues handle unicast frames only.
2766                                  */
2767                                 intr_context->handler = qlge_msix_rx_isr;
2768                                 sprintf(intr_context->name, "%s-rxq-%d",
2769                                         qdev->ndev->name, i);
2770                         }
2771                 }
2772         } else {
2773                 /*
2774                  * All rx_rings use the same intr_context since
2775                  * there is only one vector.
2776                  */
2777                 intr_context->intr = 0;
2778                 intr_context->qdev = qdev;
2779                 /*
2780                  * We set up each vectors enable/disable/read bits so
2781                  * there's no bit/mask calculations in the critical path.
2782                  */
2783                 intr_context->intr_en_mask =
2784                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2785                 intr_context->intr_dis_mask =
2786                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2787                     INTR_EN_TYPE_DISABLE;
2788                 intr_context->intr_read_mask =
2789                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2790                 /*
2791                  * Single interrupt means one handler for all rings.
2792                  */
2793                 intr_context->handler = qlge_isr;
2794                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2795                 for (i = 0; i < qdev->rx_ring_count; i++)
2796                         qdev->rx_ring[i].irq = 0;
2797         }
2798 }
2799
2800 static void ql_free_irq(struct ql_adapter *qdev)
2801 {
2802         int i;
2803         struct intr_context *intr_context = &qdev->intr_context[0];
2804
2805         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2806                 if (intr_context->hooked) {
2807                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2808                                 free_irq(qdev->msi_x_entry[i].vector,
2809                                          &qdev->rx_ring[i]);
2810                                 QPRINTK(qdev, IFDOWN, ERR,
2811                                         "freeing msix interrupt %d.\n", i);
2812                         } else {
2813                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2814                                 QPRINTK(qdev, IFDOWN, ERR,
2815                                         "freeing msi interrupt %d.\n", i);
2816                         }
2817                 }
2818         }
2819         ql_disable_msix(qdev);
2820 }
2821
2822 static int ql_request_irq(struct ql_adapter *qdev)
2823 {
2824         int i;
2825         int status = 0;
2826         struct pci_dev *pdev = qdev->pdev;
2827         struct intr_context *intr_context = &qdev->intr_context[0];
2828
2829         ql_resolve_queues_to_irqs(qdev);
2830
2831         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2832                 atomic_set(&intr_context->irq_cnt, 0);
2833                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2834                         status = request_irq(qdev->msi_x_entry[i].vector,
2835                                              intr_context->handler,
2836                                              0,
2837                                              intr_context->name,
2838                                              &qdev->rx_ring[i]);
2839                         if (status) {
2840                                 QPRINTK(qdev, IFUP, ERR,
2841                                         "Failed request for MSIX interrupt %d.\n",
2842                                         i);
2843                                 goto err_irq;
2844                         } else {
2845                                 QPRINTK(qdev, IFUP, INFO,
2846                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2847                                         i,
2848                                         qdev->rx_ring[i].type ==
2849                                         DEFAULT_Q ? "DEFAULT_Q" : "",
2850                                         qdev->rx_ring[i].type ==
2851                                         TX_Q ? "TX_Q" : "",
2852                                         qdev->rx_ring[i].type ==
2853                                         RX_Q ? "RX_Q" : "", intr_context->name);
2854                         }
2855                 } else {
2856                         QPRINTK(qdev, IFUP, DEBUG,
2857                                 "trying msi or legacy interrupts.\n");
2858                         QPRINTK(qdev, IFUP, DEBUG,
2859                                 "%s: irq = %d.\n", __func__, pdev->irq);
2860                         QPRINTK(qdev, IFUP, DEBUG,
2861                                 "%s: context->name = %s.\n", __func__,
2862                                intr_context->name);
2863                         QPRINTK(qdev, IFUP, DEBUG,
2864                                 "%s: dev_id = 0x%p.\n", __func__,
2865                                &qdev->rx_ring[0]);
2866                         status =
2867                             request_irq(pdev->irq, qlge_isr,
2868                                         test_bit(QL_MSI_ENABLED,
2869                                                  &qdev->
2870                                                  flags) ? 0 : IRQF_SHARED,
2871                                         intr_context->name, &qdev->rx_ring[0]);
2872                         if (status)
2873                                 goto err_irq;
2874
2875                         QPRINTK(qdev, IFUP, ERR,
2876                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2877                                 i,
2878                                 qdev->rx_ring[0].type ==
2879                                 DEFAULT_Q ? "DEFAULT_Q" : "",
2880                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2881                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2882                                 intr_context->name);
2883                 }
2884                 intr_context->hooked = 1;
2885         }
2886         return status;
2887 err_irq:
2888         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2889         ql_free_irq(qdev);
2890         return status;
2891 }
2892
2893 static int ql_start_rss(struct ql_adapter *qdev)
2894 {
2895         struct ricb *ricb = &qdev->ricb;
2896         int status = 0;
2897         int i;
2898         u8 *hash_id = (u8 *) ricb->hash_cq_id;
2899
2900         memset((void *)ricb, 0, sizeof(ricb));
2901
2902         ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2903         ricb->flags =
2904             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2905              RSS_RT6);
2906         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2907
2908         /*
2909          * Fill out the Indirection Table.
2910          */
2911         for (i = 0; i < 32; i++)
2912                 hash_id[i] = i & 1;
2913
2914         /*
2915          * Random values for the IPv6 and IPv4 Hash Keys.
2916          */
2917         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2918         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2919
2920         QPRINTK(qdev, IFUP, INFO, "Initializing RSS.\n");
2921
2922         status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2923         if (status) {
2924                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2925                 return status;
2926         }
2927         QPRINTK(qdev, IFUP, INFO, "Successfully loaded RICB.\n");
2928         return status;
2929 }
2930
2931 /* Initialize the frame-to-queue routing. */
2932 static int ql_route_initialize(struct ql_adapter *qdev)
2933 {
2934         int status = 0;
2935         int i;
2936
2937         /* Clear all the entries in the routing table. */
2938         for (i = 0; i < 16; i++) {
2939                 status = ql_set_routing_reg(qdev, i, 0, 0);
2940                 if (status) {
2941                         QPRINTK(qdev, IFUP, ERR,
2942                                 "Failed to init routing register for CAM packets.\n");
2943                         return status;
2944                 }
2945         }
2946
2947         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2948         if (status) {
2949                 QPRINTK(qdev, IFUP, ERR,
2950                         "Failed to init routing register for error packets.\n");
2951                 return status;
2952         }
2953         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
2954         if (status) {
2955                 QPRINTK(qdev, IFUP, ERR,
2956                         "Failed to init routing register for broadcast packets.\n");
2957                 return status;
2958         }
2959         /* If we have more than one inbound queue, then turn on RSS in the
2960          * routing block.
2961          */
2962         if (qdev->rss_ring_count > 1) {
2963                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
2964                                         RT_IDX_RSS_MATCH, 1);
2965                 if (status) {
2966                         QPRINTK(qdev, IFUP, ERR,
2967                                 "Failed to init routing register for MATCH RSS packets.\n");
2968                         return status;
2969                 }
2970         }
2971
2972         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
2973                                     RT_IDX_CAM_HIT, 1);
2974         if (status) {
2975                 QPRINTK(qdev, IFUP, ERR,
2976                         "Failed to init routing register for CAM packets.\n");
2977                 return status;
2978         }
2979         return status;
2980 }
2981
2982 static int ql_adapter_initialize(struct ql_adapter *qdev)
2983 {
2984         u32 value, mask;
2985         int i;
2986         int status = 0;
2987
2988         /*
2989          * Set up the System register to halt on errors.
2990          */
2991         value = SYS_EFE | SYS_FAE;
2992         mask = value << 16;
2993         ql_write32(qdev, SYS, mask | value);
2994
2995         /* Set the default queue. */
2996         value = NIC_RCV_CFG_DFQ;
2997         mask = NIC_RCV_CFG_DFQ_MASK;
2998         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
2999
3000         /* Set the MPI interrupt to enabled. */
3001         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3002
3003         /* Enable the function, set pagesize, enable error checking. */
3004         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3005             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3006
3007         /* Set/clear header splitting. */
3008         mask = FSC_VM_PAGESIZE_MASK |
3009             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3010         ql_write32(qdev, FSC, mask | value);
3011
3012         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3013                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3014
3015         /* Start up the rx queues. */
3016         for (i = 0; i < qdev->rx_ring_count; i++) {
3017                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3018                 if (status) {
3019                         QPRINTK(qdev, IFUP, ERR,
3020                                 "Failed to start rx ring[%d].\n", i);
3021                         return status;
3022                 }
3023         }
3024
3025         /* If there is more than one inbound completion queue
3026          * then download a RICB to configure RSS.
3027          */
3028         if (qdev->rss_ring_count > 1) {
3029                 status = ql_start_rss(qdev);
3030                 if (status) {
3031                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3032                         return status;
3033                 }
3034         }
3035
3036         /* Start up the tx queues. */
3037         for (i = 0; i < qdev->tx_ring_count; i++) {
3038                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3039                 if (status) {
3040                         QPRINTK(qdev, IFUP, ERR,
3041                                 "Failed to start tx ring[%d].\n", i);
3042                         return status;
3043                 }
3044         }
3045
3046         status = ql_port_initialize(qdev);
3047         if (status) {
3048                 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3049                 return status;
3050         }
3051
3052         status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3053                                      MAC_ADDR_TYPE_CAM_MAC, qdev->func);
3054         if (status) {
3055                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3056                 return status;
3057         }
3058
3059         status = ql_route_initialize(qdev);
3060         if (status) {
3061                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3062                 return status;
3063         }
3064
3065         /* Start NAPI for the RSS queues. */
3066         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3067                 QPRINTK(qdev, IFUP, INFO, "Enabling NAPI for rx_ring[%d].\n",
3068                         i);
3069                 napi_enable(&qdev->rx_ring[i].napi);
3070         }
3071
3072         return status;
3073 }
3074
3075 /* Issue soft reset to chip. */
3076 static int ql_adapter_reset(struct ql_adapter *qdev)
3077 {
3078         u32 value;
3079         int max_wait_time;
3080         int status = 0;
3081         int resetCnt = 0;
3082
3083 #define MAX_RESET_CNT   1
3084 issueReset:
3085         resetCnt++;
3086         QPRINTK(qdev, IFDOWN, DEBUG, "Issue soft reset to chip.\n");
3087         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3088         /* Wait for reset to complete. */
3089         max_wait_time = 3;
3090         QPRINTK(qdev, IFDOWN, DEBUG, "Wait %d seconds for reset to complete.\n",
3091                 max_wait_time);
3092         do {
3093                 value = ql_read32(qdev, RST_FO);
3094                 if ((value & RST_FO_FR) == 0)
3095                         break;
3096
3097                 ssleep(1);
3098         } while ((--max_wait_time));
3099         if (value & RST_FO_FR) {
3100                 QPRINTK(qdev, IFDOWN, ERR,
3101                         "Stuck in SoftReset:  FSC_SR:0x%08x\n", value);
3102                 if (resetCnt < MAX_RESET_CNT)
3103                         goto issueReset;
3104         }
3105         if (max_wait_time == 0) {
3106                 status = -ETIMEDOUT;
3107                 QPRINTK(qdev, IFDOWN, ERR,
3108                         "ETIMEOUT!!! errored out of resetting the chip!\n");
3109         }
3110
3111         return status;
3112 }
3113
3114 static void ql_display_dev_info(struct net_device *ndev)
3115 {
3116         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3117
3118         QPRINTK(qdev, PROBE, INFO,
3119                 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3120                 "XG Roll = %d, XG Rev = %d.\n",
3121                 qdev->func,
3122                 qdev->chip_rev_id & 0x0000000f,
3123                 qdev->chip_rev_id >> 4 & 0x0000000f,
3124                 qdev->chip_rev_id >> 8 & 0x0000000f,
3125                 qdev->chip_rev_id >> 12 & 0x0000000f);
3126         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3127 }
3128
3129 static int ql_adapter_down(struct ql_adapter *qdev)
3130 {
3131         struct net_device *ndev = qdev->ndev;
3132         int i, status = 0;
3133         struct rx_ring *rx_ring;
3134
3135         netif_stop_queue(ndev);
3136         netif_carrier_off(ndev);
3137
3138         cancel_delayed_work_sync(&qdev->asic_reset_work);
3139         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3140         cancel_delayed_work_sync(&qdev->mpi_work);
3141
3142         /* The default queue at index 0 is always processed in
3143          * a workqueue.
3144          */
3145         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3146
3147         /* The rest of the rx_rings are processed in
3148          * a workqueue only if it's a single interrupt
3149          * environment (MSI/Legacy).
3150          */
3151         for (i = 1; i < qdev->rx_ring_count; i++) {
3152                 rx_ring = &qdev->rx_ring[i];
3153                 /* Only the RSS rings use NAPI on multi irq
3154                  * environment.  Outbound completion processing
3155                  * is done in interrupt context.
3156                  */
3157                 if (i >= qdev->rss_ring_first_cq_id) {
3158                         napi_disable(&rx_ring->napi);
3159                 } else {
3160                         cancel_delayed_work_sync(&rx_ring->rx_work);
3161                 }
3162         }
3163
3164         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3165
3166         ql_disable_interrupts(qdev);
3167
3168         ql_tx_ring_clean(qdev);
3169
3170         spin_lock(&qdev->hw_lock);
3171         status = ql_adapter_reset(qdev);
3172         if (status)
3173                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3174                         qdev->func);
3175         spin_unlock(&qdev->hw_lock);
3176         return status;
3177 }
3178
3179 static int ql_adapter_up(struct ql_adapter *qdev)
3180 {
3181         int err = 0;
3182
3183         spin_lock(&qdev->hw_lock);
3184         err = ql_adapter_initialize(qdev);
3185         if (err) {
3186                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3187                 spin_unlock(&qdev->hw_lock);
3188                 goto err_init;
3189         }
3190         spin_unlock(&qdev->hw_lock);
3191         set_bit(QL_ADAPTER_UP, &qdev->flags);
3192         ql_enable_interrupts(qdev);
3193         ql_enable_all_completion_interrupts(qdev);
3194         if ((ql_read32(qdev, STS) & qdev->port_init)) {
3195                 netif_carrier_on(qdev->ndev);
3196                 netif_start_queue(qdev->ndev);
3197         }
3198
3199         return 0;
3200 err_init:
3201         ql_adapter_reset(qdev);
3202         return err;
3203 }
3204
3205 static int ql_cycle_adapter(struct ql_adapter *qdev)
3206 {
3207         int status;
3208
3209         status = ql_adapter_down(qdev);
3210         if (status)
3211                 goto error;
3212
3213         status = ql_adapter_up(qdev);
3214         if (status)
3215                 goto error;
3216
3217         return status;
3218 error:
3219         QPRINTK(qdev, IFUP, ALERT,
3220                 "Driver up/down cycle failed, closing device\n");
3221         rtnl_lock();
3222         dev_close(qdev->ndev);
3223         rtnl_unlock();
3224         return status;
3225 }
3226
3227 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3228 {
3229         ql_free_mem_resources(qdev);
3230         ql_free_irq(qdev);
3231 }
3232
3233 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3234 {
3235         int status = 0;
3236
3237         if (ql_alloc_mem_resources(qdev)) {
3238                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3239                 return -ENOMEM;
3240         }
3241         status = ql_request_irq(qdev);
3242         if (status)
3243                 goto err_irq;
3244         return status;
3245 err_irq:
3246         ql_free_mem_resources(qdev);
3247         return status;
3248 }
3249
3250 static int qlge_close(struct net_device *ndev)
3251 {
3252         struct ql_adapter *qdev = netdev_priv(ndev);
3253
3254         /*
3255          * Wait for device to recover from a reset.
3256          * (Rarely happens, but possible.)
3257          */
3258         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3259                 msleep(1);
3260         ql_adapter_down(qdev);
3261         ql_release_adapter_resources(qdev);
3262         ql_free_ring_cb(qdev);
3263         return 0;
3264 }
3265
3266 static int ql_configure_rings(struct ql_adapter *qdev)
3267 {
3268         int i;
3269         struct rx_ring *rx_ring;
3270         struct tx_ring *tx_ring;
3271         int cpu_cnt = num_online_cpus();
3272
3273         /*
3274          * For each processor present we allocate one
3275          * rx_ring for outbound completions, and one
3276          * rx_ring for inbound completions.  Plus there is
3277          * always the one default queue.  For the CPU
3278          * counts we end up with the following rx_rings:
3279          * rx_ring count =
3280          *  one default queue +
3281          *  (CPU count * outbound completion rx_ring) +
3282          *  (CPU count * inbound (RSS) completion rx_ring)
3283          * To keep it simple we limit the total number of
3284          * queues to < 32, so we truncate CPU to 8.
3285          * This limitation can be removed when requested.
3286          */
3287
3288         if (cpu_cnt > 8)
3289                 cpu_cnt = 8;
3290
3291         /*
3292          * rx_ring[0] is always the default queue.
3293          */
3294         /* Allocate outbound completion ring for each CPU. */
3295         qdev->tx_ring_count = cpu_cnt;
3296         /* Allocate inbound completion (RSS) ring for each CPU. */
3297         qdev->rss_ring_count = cpu_cnt;
3298         /* cq_id for the first inbound ring handler. */
3299         qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3300         /*
3301          * qdev->rx_ring_count:
3302          * Total number of rx_rings.  This includes the one
3303          * default queue, a number of outbound completion
3304          * handler rx_rings, and the number of inbound
3305          * completion handler rx_rings.
3306          */
3307         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3308
3309         if (ql_alloc_ring_cb(qdev))
3310                 return -ENOMEM;
3311
3312         for (i = 0; i < qdev->tx_ring_count; i++) {
3313                 tx_ring = &qdev->tx_ring[i];
3314                 memset((void *)tx_ring, 0, sizeof(tx_ring));
3315                 tx_ring->qdev = qdev;
3316                 tx_ring->wq_id = i;
3317                 tx_ring->wq_len = qdev->tx_ring_size;
3318                 tx_ring->wq_size =
3319                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3320
3321                 /*
3322                  * The completion queue ID for the tx rings start
3323                  * immediately after the default Q ID, which is zero.
3324                  */
3325                 tx_ring->cq_id = i + 1;
3326         }
3327
3328         for (i = 0; i < qdev->rx_ring_count; i++) {
3329                 rx_ring = &qdev->rx_ring[i];
3330                 memset((void *)rx_ring, 0, sizeof(rx_ring));
3331                 rx_ring->qdev = qdev;
3332                 rx_ring->cq_id = i;
3333                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3334                 if (i == 0) {   /* Default queue at index 0. */
3335                         /*
3336                          * Default queue handles bcast/mcast plus
3337                          * async events.  Needs buffers.
3338                          */
3339                         rx_ring->cq_len = qdev->rx_ring_size;
3340                         rx_ring->cq_size =
3341                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3342                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3343                         rx_ring->lbq_size =
3344                             rx_ring->lbq_len * sizeof(struct bq_element);
3345                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3346                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3347                         rx_ring->sbq_size =
3348                             rx_ring->sbq_len * sizeof(struct bq_element);
3349                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3350                         rx_ring->type = DEFAULT_Q;
3351                 } else if (i < qdev->rss_ring_first_cq_id) {
3352                         /*
3353                          * Outbound queue handles outbound completions only.
3354                          */
3355                         /* outbound cq is same size as tx_ring it services. */
3356                         rx_ring->cq_len = qdev->tx_ring_size;
3357                         rx_ring->cq_size =
3358                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3359                         rx_ring->lbq_len = 0;
3360                         rx_ring->lbq_size = 0;
3361                         rx_ring->lbq_buf_size = 0;
3362                         rx_ring->sbq_len = 0;
3363                         rx_ring->sbq_size = 0;
3364                         rx_ring->sbq_buf_size = 0;
3365                         rx_ring->type = TX_Q;
3366                 } else {        /* Inbound completions (RSS) queues */
3367                         /*
3368                          * Inbound queues handle unicast frames only.
3369                          */
3370                         rx_ring->cq_len = qdev->rx_ring_size;
3371                         rx_ring->cq_size =
3372                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3373                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3374                         rx_ring->lbq_size =
3375                             rx_ring->lbq_len * sizeof(struct bq_element);
3376                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3377                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3378                         rx_ring->sbq_size =
3379                             rx_ring->sbq_len * sizeof(struct bq_element);
3380                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3381                         rx_ring->type = RX_Q;
3382                 }
3383         }
3384         return 0;
3385 }
3386
3387 static int qlge_open(struct net_device *ndev)
3388 {
3389         int err = 0;
3390         struct ql_adapter *qdev = netdev_priv(ndev);
3391
3392         err = ql_configure_rings(qdev);
3393         if (err)
3394                 return err;
3395
3396         err = ql_get_adapter_resources(qdev);
3397         if (err)
3398                 goto error_up;
3399
3400         err = ql_adapter_up(qdev);
3401         if (err)
3402                 goto error_up;
3403
3404         return err;
3405
3406 error_up:
3407         ql_release_adapter_resources(qdev);
3408         ql_free_ring_cb(qdev);
3409         return err;
3410 }
3411
3412 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3413 {
3414         struct ql_adapter *qdev = netdev_priv(ndev);
3415
3416         if (ndev->mtu == 1500 && new_mtu == 9000) {
3417                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3418         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3419                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3420         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3421                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3422                 return 0;
3423         } else
3424                 return -EINVAL;
3425         ndev->mtu = new_mtu;
3426         return 0;
3427 }
3428
3429 static struct net_device_stats *qlge_get_stats(struct net_device
3430                                                *ndev)
3431 {
3432         struct ql_adapter *qdev = netdev_priv(ndev);
3433         return &qdev->stats;
3434 }
3435
3436 static void qlge_set_multicast_list(struct net_device *ndev)
3437 {
3438         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3439         struct dev_mc_list *mc_ptr;
3440         int i;
3441
3442         spin_lock(&qdev->hw_lock);
3443         /*
3444          * Set or clear promiscuous mode if a
3445          * transition is taking place.
3446          */
3447         if (ndev->flags & IFF_PROMISC) {
3448                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3449                         if (ql_set_routing_reg
3450                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3451                                 QPRINTK(qdev, HW, ERR,
3452                                         "Failed to set promiscous mode.\n");
3453                         } else {
3454                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3455                         }
3456                 }
3457         } else {
3458                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3459                         if (ql_set_routing_reg
3460                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3461                                 QPRINTK(qdev, HW, ERR,
3462                                         "Failed to clear promiscous mode.\n");
3463                         } else {
3464                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3465                         }
3466                 }
3467         }
3468
3469         /*
3470          * Set or clear all multicast mode if a
3471          * transition is taking place.
3472          */
3473         if ((ndev->flags & IFF_ALLMULTI) ||
3474             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3475                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3476                         if (ql_set_routing_reg
3477                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3478                                 QPRINTK(qdev, HW, ERR,
3479                                         "Failed to set all-multi mode.\n");
3480                         } else {
3481                                 set_bit(QL_ALLMULTI, &qdev->flags);
3482                         }
3483                 }
3484         } else {
3485                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3486                         if (ql_set_routing_reg
3487                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3488                                 QPRINTK(qdev, HW, ERR,
3489                                         "Failed to clear all-multi mode.\n");
3490                         } else {
3491                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3492                         }
3493                 }
3494         }
3495
3496         if (ndev->mc_count) {
3497                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3498                      i++, mc_ptr = mc_ptr->next)
3499                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3500                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3501                                 QPRINTK(qdev, HW, ERR,
3502                                         "Failed to loadmulticast address.\n");
3503                                 goto exit;
3504                         }
3505                 if (ql_set_routing_reg
3506                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3507                         QPRINTK(qdev, HW, ERR,
3508                                 "Failed to set multicast match mode.\n");
3509                 } else {
3510                         set_bit(QL_ALLMULTI, &qdev->flags);
3511                 }
3512         }
3513 exit:
3514         spin_unlock(&qdev->hw_lock);
3515 }
3516
3517 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3518 {
3519         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3520         struct sockaddr *addr = p;
3521         int ret = 0;
3522
3523         if (netif_running(ndev))
3524                 return -EBUSY;
3525
3526         if (!is_valid_ether_addr(addr->sa_data))
3527                 return -EADDRNOTAVAIL;
3528         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3529
3530         spin_lock(&qdev->hw_lock);
3531         if (ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3532                         MAC_ADDR_TYPE_CAM_MAC, qdev->func)) {/* Unicast */
3533                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3534                 ret = -1;
3535         }
3536         spin_unlock(&qdev->hw_lock);
3537
3538         return ret;
3539 }
3540
3541 static void qlge_tx_timeout(struct net_device *ndev)
3542 {
3543         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3544         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
3545 }
3546
3547 static void ql_asic_reset_work(struct work_struct *work)
3548 {
3549         struct ql_adapter *qdev =
3550             container_of(work, struct ql_adapter, asic_reset_work.work);
3551         ql_cycle_adapter(qdev);
3552 }
3553
3554 static void ql_get_board_info(struct ql_adapter *qdev)
3555 {
3556         qdev->func =
3557             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3558         if (qdev->func) {
3559                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3560                 qdev->port_link_up = STS_PL1;
3561                 qdev->port_init = STS_PI1;
3562                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3563                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3564         } else {
3565                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3566                 qdev->port_link_up = STS_PL0;
3567                 qdev->port_init = STS_PI0;
3568                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3569                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3570         }
3571         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3572 }
3573
3574 static void ql_release_all(struct pci_dev *pdev)
3575 {
3576         struct net_device *ndev = pci_get_drvdata(pdev);
3577         struct ql_adapter *qdev = netdev_priv(ndev);
3578
3579         if (qdev->workqueue) {
3580                 destroy_workqueue(qdev->workqueue);
3581                 qdev->workqueue = NULL;
3582         }
3583         if (qdev->q_workqueue) {
3584                 destroy_workqueue(qdev->q_workqueue);
3585                 qdev->q_workqueue = NULL;
3586         }
3587         if (qdev->reg_base)
3588                 iounmap(qdev->reg_base);
3589         if (qdev->doorbell_area)
3590                 iounmap(qdev->doorbell_area);
3591         pci_release_regions(pdev);
3592         pci_set_drvdata(pdev, NULL);
3593 }
3594
3595 static int __devinit ql_init_device(struct pci_dev *pdev,
3596                                     struct net_device *ndev, int cards_found)
3597 {
3598         struct ql_adapter *qdev = netdev_priv(ndev);
3599         int pos, err = 0;
3600         u16 val16;
3601
3602         memset((void *)qdev, 0, sizeof(qdev));
3603         err = pci_enable_device(pdev);
3604         if (err) {
3605                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3606                 return err;
3607         }
3608
3609         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3610         if (pos <= 0) {
3611                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3612                         "aborting.\n");
3613                 goto err_out;
3614         } else {
3615                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3616                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3617                 val16 |= (PCI_EXP_DEVCTL_CERE |
3618                           PCI_EXP_DEVCTL_NFERE |
3619                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3620                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3621         }
3622
3623         err = pci_request_regions(pdev, DRV_NAME);
3624         if (err) {
3625                 dev_err(&pdev->dev, "PCI region request failed.\n");
3626                 goto err_out;
3627         }
3628
3629         pci_set_master(pdev);
3630         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3631                 set_bit(QL_DMA64, &qdev->flags);
3632                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3633         } else {
3634                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3635                 if (!err)
3636                        err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3637         }
3638
3639         if (err) {
3640                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3641                 goto err_out;
3642         }
3643
3644         pci_set_drvdata(pdev, ndev);
3645         qdev->reg_base =
3646             ioremap_nocache(pci_resource_start(pdev, 1),
3647                             pci_resource_len(pdev, 1));
3648         if (!qdev->reg_base) {
3649                 dev_err(&pdev->dev, "Register mapping failed.\n");
3650                 err = -ENOMEM;
3651                 goto err_out;
3652         }
3653
3654         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3655         qdev->doorbell_area =
3656             ioremap_nocache(pci_resource_start(pdev, 3),
3657                             pci_resource_len(pdev, 3));
3658         if (!qdev->doorbell_area) {
3659                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3660                 err = -ENOMEM;
3661                 goto err_out;
3662         }
3663
3664         ql_get_board_info(qdev);
3665         qdev->ndev = ndev;
3666         qdev->pdev = pdev;
3667         qdev->msg_enable = netif_msg_init(debug, default_msg);
3668         spin_lock_init(&qdev->hw_lock);
3669         spin_lock_init(&qdev->stats_lock);
3670
3671         /* make sure the EEPROM is good */
3672         err = ql_get_flash_params(qdev);
3673         if (err) {
3674                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3675                 goto err_out;
3676         }
3677
3678         if (!is_valid_ether_addr(qdev->flash.mac_addr))
3679                 goto err_out;
3680
3681         memcpy(ndev->dev_addr, qdev->flash.mac_addr, ndev->addr_len);
3682         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3683
3684         /* Set up the default ring sizes. */
3685         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3686         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3687
3688         /* Set up the coalescing parameters. */
3689         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3690         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3691         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3692         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3693
3694         /*
3695          * Set up the operating parameters.
3696          */
3697         qdev->rx_csum = 1;
3698
3699         qdev->q_workqueue = create_workqueue(ndev->name);
3700         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3701         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3702         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3703         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3704
3705         if (!cards_found) {
3706                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3707                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3708                          DRV_NAME, DRV_VERSION);
3709         }
3710         return 0;
3711 err_out:
3712         ql_release_all(pdev);
3713         pci_disable_device(pdev);
3714         return err;
3715 }
3716
3717
3718 static const struct net_device_ops qlge_netdev_ops = {
3719         .ndo_open               = qlge_open,
3720         .ndo_stop               = qlge_close,
3721         .ndo_start_xmit         = qlge_send,
3722         .ndo_change_mtu         = qlge_change_mtu,
3723         .ndo_get_stats          = qlge_get_stats,
3724         .ndo_set_multicast_list = qlge_set_multicast_list,
3725         .ndo_set_mac_address    = qlge_set_mac_address,
3726         .ndo_validate_addr      = eth_validate_addr,
3727         .ndo_tx_timeout         = qlge_tx_timeout,
3728         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3729         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3730         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3731 };
3732
3733 static int __devinit qlge_probe(struct pci_dev *pdev,
3734                                 const struct pci_device_id *pci_entry)
3735 {
3736         struct net_device *ndev = NULL;
3737         struct ql_adapter *qdev = NULL;
3738         static int cards_found = 0;
3739         int err = 0;
3740
3741         ndev = alloc_etherdev(sizeof(struct ql_adapter));
3742         if (!ndev)
3743                 return -ENOMEM;
3744
3745         err = ql_init_device(pdev, ndev, cards_found);
3746         if (err < 0) {
3747                 free_netdev(ndev);
3748                 return err;
3749         }
3750
3751         qdev = netdev_priv(ndev);
3752         SET_NETDEV_DEV(ndev, &pdev->dev);
3753         ndev->features = (0
3754                           | NETIF_F_IP_CSUM
3755                           | NETIF_F_SG
3756                           | NETIF_F_TSO
3757                           | NETIF_F_TSO6
3758                           | NETIF_F_TSO_ECN
3759                           | NETIF_F_HW_VLAN_TX
3760                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3761
3762         if (test_bit(QL_DMA64, &qdev->flags))
3763                 ndev->features |= NETIF_F_HIGHDMA;
3764
3765         /*
3766          * Set up net_device structure.
3767          */
3768         ndev->tx_queue_len = qdev->tx_ring_size;
3769         ndev->irq = pdev->irq;
3770
3771         ndev->netdev_ops = &qlge_netdev_ops;
3772         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3773         ndev->watchdog_timeo = 10 * HZ;
3774
3775         err = register_netdev(ndev);
3776         if (err) {
3777                 dev_err(&pdev->dev, "net device registration failed.\n");
3778                 ql_release_all(pdev);
3779                 pci_disable_device(pdev);
3780                 return err;
3781         }
3782         netif_carrier_off(ndev);
3783         netif_stop_queue(ndev);
3784         ql_display_dev_info(ndev);
3785         cards_found++;
3786         return 0;
3787 }
3788
3789 static void __devexit qlge_remove(struct pci_dev *pdev)
3790 {
3791         struct net_device *ndev = pci_get_drvdata(pdev);
3792         unregister_netdev(ndev);
3793         ql_release_all(pdev);
3794         pci_disable_device(pdev);
3795         free_netdev(ndev);
3796 }
3797
3798 /*
3799  * This callback is called by the PCI subsystem whenever
3800  * a PCI bus error is detected.
3801  */
3802 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3803                                                enum pci_channel_state state)
3804 {
3805         struct net_device *ndev = pci_get_drvdata(pdev);
3806         struct ql_adapter *qdev = netdev_priv(ndev);
3807
3808         if (netif_running(ndev))
3809                 ql_adapter_down(qdev);
3810
3811         pci_disable_device(pdev);
3812
3813         /* Request a slot reset. */
3814         return PCI_ERS_RESULT_NEED_RESET;
3815 }
3816
3817 /*
3818  * This callback is called after the PCI buss has been reset.
3819  * Basically, this tries to restart the card from scratch.
3820  * This is a shortened version of the device probe/discovery code,
3821  * it resembles the first-half of the () routine.
3822  */
3823 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3824 {
3825         struct net_device *ndev = pci_get_drvdata(pdev);
3826         struct ql_adapter *qdev = netdev_priv(ndev);
3827
3828         if (pci_enable_device(pdev)) {
3829                 QPRINTK(qdev, IFUP, ERR,
3830                         "Cannot re-enable PCI device after reset.\n");
3831                 return PCI_ERS_RESULT_DISCONNECT;
3832         }
3833
3834         pci_set_master(pdev);
3835
3836         netif_carrier_off(ndev);
3837         netif_stop_queue(ndev);
3838         ql_adapter_reset(qdev);
3839
3840         /* Make sure the EEPROM is good */
3841         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3842
3843         if (!is_valid_ether_addr(ndev->perm_addr)) {
3844                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3845                 return PCI_ERS_RESULT_DISCONNECT;
3846         }
3847
3848         return PCI_ERS_RESULT_RECOVERED;
3849 }
3850
3851 static void qlge_io_resume(struct pci_dev *pdev)
3852 {
3853         struct net_device *ndev = pci_get_drvdata(pdev);
3854         struct ql_adapter *qdev = netdev_priv(ndev);
3855
3856         pci_set_master(pdev);
3857
3858         if (netif_running(ndev)) {
3859                 if (ql_adapter_up(qdev)) {
3860                         QPRINTK(qdev, IFUP, ERR,
3861                                 "Device initialization failed after reset.\n");
3862                         return;
3863                 }
3864         }
3865
3866         netif_device_attach(ndev);
3867 }
3868
3869 static struct pci_error_handlers qlge_err_handler = {
3870         .error_detected = qlge_io_error_detected,
3871         .slot_reset = qlge_io_slot_reset,
3872         .resume = qlge_io_resume,
3873 };
3874
3875 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3876 {
3877         struct net_device *ndev = pci_get_drvdata(pdev);
3878         struct ql_adapter *qdev = netdev_priv(ndev);
3879         int err;
3880
3881         netif_device_detach(ndev);
3882
3883         if (netif_running(ndev)) {
3884                 err = ql_adapter_down(qdev);
3885                 if (!err)
3886                         return err;
3887         }
3888
3889         err = pci_save_state(pdev);
3890         if (err)
3891                 return err;
3892
3893         pci_disable_device(pdev);
3894
3895         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3896
3897         return 0;
3898 }
3899
3900 #ifdef CONFIG_PM
3901 static int qlge_resume(struct pci_dev *pdev)
3902 {
3903         struct net_device *ndev = pci_get_drvdata(pdev);
3904         struct ql_adapter *qdev = netdev_priv(ndev);
3905         int err;
3906
3907         pci_set_power_state(pdev, PCI_D0);
3908         pci_restore_state(pdev);
3909         err = pci_enable_device(pdev);
3910         if (err) {
3911                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3912                 return err;
3913         }
3914         pci_set_master(pdev);
3915
3916         pci_enable_wake(pdev, PCI_D3hot, 0);
3917         pci_enable_wake(pdev, PCI_D3cold, 0);
3918
3919         if (netif_running(ndev)) {
3920                 err = ql_adapter_up(qdev);
3921                 if (err)
3922                         return err;
3923         }
3924
3925         netif_device_attach(ndev);
3926
3927         return 0;
3928 }
3929 #endif /* CONFIG_PM */
3930
3931 static void qlge_shutdown(struct pci_dev *pdev)
3932 {
3933         qlge_suspend(pdev, PMSG_SUSPEND);
3934 }
3935
3936 static struct pci_driver qlge_driver = {
3937         .name = DRV_NAME,
3938         .id_table = qlge_pci_tbl,
3939         .probe = qlge_probe,
3940         .remove = __devexit_p(qlge_remove),
3941 #ifdef CONFIG_PM
3942         .suspend = qlge_suspend,
3943         .resume = qlge_resume,
3944 #endif
3945         .shutdown = qlge_shutdown,
3946         .err_handler = &qlge_err_handler
3947 };
3948
3949 static int __init qlge_init_module(void)
3950 {
3951         return pci_register_driver(&qlge_driver);
3952 }
3953
3954 static void __exit qlge_exit(void)
3955 {
3956         pci_unregister_driver(&qlge_driver);
3957 }
3958
3959 module_init(qlge_init_module);
3960 module_exit(qlge_exit);