drivers/net/qla3xxx.c

   1 /*
   2  * QLogic QLA3xxx NIC HBA Driver
   3  * Copyright (c)  2003-2006 QLogic Corporation
   4  *
   5  * See LICENSE.qla3xxx for copyright and licensing details.
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/sched.h>
  16 #include <linux/slab.h>
  17 #include <linux/dmapool.h>
  18 #include <linux/mempool.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/kthread.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/errno.h>
  23 #include <linux/ioport.h>
  24 #include <linux/ip.h>
  25 #include <linux/in.h>
  26 #include <linux/if_arp.h>
  27 #include <linux/if_ether.h>
  28 #include <linux/netdevice.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/ethtool.h>
  31 #include <linux/skbuff.h>
  32 #include <linux/rtnetlink.h>
  33 #include <linux/if_vlan.h>
  34 #include <linux/init.h>
  35 #include <linux/delay.h>
  36 #include <linux/mm.h>
  37
  38 #include "qla3xxx.h"
  39
  40 #define DRV_NAME        "qla3xxx"
  41 #define DRV_STRING      "QLogic ISP3XXX Network Driver"
  42 #define DRV_VERSION     "v2.02.00-k36"
  43 #define PFX             DRV_NAME " "
  44
  45 static const char ql3xxx_driver_name[] = DRV_NAME;
  46 static const char ql3xxx_driver_version[] = DRV_VERSION;
  47
  48 MODULE_AUTHOR("QLogic Corporation");
  49 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
  50 MODULE_LICENSE("GPL");
  51 MODULE_VERSION(DRV_VERSION);
  52
  53 static const u32 default_msg
  54     = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
  55     | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
  56
  57 static int debug = -1;          /* defaults above */
  58 module_param(debug, int, 0);
  59 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  60
  61 static int msi;
  62 module_param(msi, int, 0);
  63 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
  64
  65 static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
  66         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
  67         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
  68         /* required last entry */
  69         {0,}
  70 };
  71
  72 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
  73
  74 /*
  75  * Caller must take hw_lock.
  76  */
  77 static int ql_sem_spinlock(struct ql3_adapter *qdev,
  78                             u32 sem_mask, u32 sem_bits)
  79 {
  80         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  81         u32 value;
  82         unsigned int seconds = 3;
  83
  84         do {
  85                 writel((sem_mask | sem_bits),
  86                        &port_regs->CommonRegs.semaphoreReg);
  87                 value = readl(&port_regs->CommonRegs.semaphoreReg);
  88                 if ((value & (sem_mask >> 16)) == sem_bits)
  89                         return 0;
  90                 ssleep(1);
  91         } while(--seconds);
  92         return -1;
  93 }
  94
  95 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
  96 {
  97         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
  98         writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
  99         readl(&port_regs->CommonRegs.semaphoreReg);
 100 }
 101
 102 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
 103 {
 104         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 105         u32 value;
 106
 107         writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
 108         value = readl(&port_regs->CommonRegs.semaphoreReg);
 109         return ((value & (sem_mask >> 16)) == sem_bits);
 110 }
 111
 112 /*
 113  * Caller holds hw_lock.
 114  */
 115 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
 116 {
 117         int i = 0;
 118
 119         while (1) {
 120                 if (!ql_sem_lock(qdev,
 121                                  QL_DRVR_SEM_MASK,
 122                                  (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
 123                                   * 2) << 1)) {
 124                         if (i < 10) {
 125                                 ssleep(1);
 126                                 i++;
 127                         } else {
 128                                 printk(KERN_ERR PFX "%s: Timed out waiting for "
 129                                        "driver lock...\n",
 130                                        qdev->ndev->name);
 131                                 return 0;
 132                         }
 133                 } else {
 134                         printk(KERN_DEBUG PFX
 135                                "%s: driver lock acquired.\n",
 136                                qdev->ndev->name);
 137                         return 1;
 138                 }
 139         }
 140 }
 141
 142 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
 143 {
 144         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 145
 146         writel(((ISP_CONTROL_NP_MASK << 16) | page),
 147                         &port_regs->CommonRegs.ispControlStatus);
 148         readl(&port_regs->CommonRegs.ispControlStatus);
 149         qdev->current_page = page;
 150 }
 151
 152 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
 153                               u32 __iomem * reg)
 154 {
 155         u32 value;
 156         unsigned long hw_flags;
 157
 158         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 159         value = readl(reg);
 160         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 161
 162         return value;
 163 }
 164
 165 static u32 ql_read_common_reg(struct ql3_adapter *qdev,
 166                               u32 __iomem * reg)
 167 {
 168         return readl(reg);
 169 }
 170
 171 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
 172 {
 173         u32 value;
 174         unsigned long hw_flags;
 175
 176         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 177
 178         if (qdev->current_page != 0)
 179                 ql_set_register_page(qdev,0);
 180         value = readl(reg);
 181
 182         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 183         return value;
 184 }
 185
 186 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
 187 {
 188         if (qdev->current_page != 0)
 189                 ql_set_register_page(qdev,0);
 190         return readl(reg);
 191 }
 192
 193 static void ql_write_common_reg_l(struct ql3_adapter *qdev,
 194                                 u32 __iomem *reg, u32 value)
 195 {
 196         unsigned long hw_flags;
 197
 198         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 199         writel(value, reg);
 200         readl(reg);
 201         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 202         return;
 203 }
 204
 205 static void ql_write_common_reg(struct ql3_adapter *qdev,
 206                                 u32 __iomem *reg, u32 value)
 207 {
 208         writel(value, reg);
 209         readl(reg);
 210         return;
 211 }
 212
 213 static void ql_write_nvram_reg(struct ql3_adapter *qdev,
 214                                 u32 __iomem *reg, u32 value)
 215 {
 216         writel(value, reg);
 217         readl(reg);
 218         udelay(1);
 219         return;
 220 }
 221
 222 static void ql_write_page0_reg(struct ql3_adapter *qdev,
 223                                u32 __iomem *reg, u32 value)
 224 {
 225         if (qdev->current_page != 0)
 226                 ql_set_register_page(qdev,0);
 227         writel(value, reg);
 228         readl(reg);
 229         return;
 230 }
 231
 232 /*
 233  * Caller holds hw_lock. Only called during init.
 234  */
 235 static void ql_write_page1_reg(struct ql3_adapter *qdev,
 236                                u32 __iomem *reg, u32 value)
 237 {
 238         if (qdev->current_page != 1)
 239                 ql_set_register_page(qdev,1);
 240         writel(value, reg);
 241         readl(reg);
 242         return;
 243 }
 244
 245 /*
 246  * Caller holds hw_lock. Only called during init.
 247  */
 248 static void ql_write_page2_reg(struct ql3_adapter *qdev,
 249                                u32 __iomem *reg, u32 value)
 250 {
 251         if (qdev->current_page != 2)
 252                 ql_set_register_page(qdev,2);
 253         writel(value, reg);
 254         readl(reg);
 255         return;
 256 }
 257
 258 static void ql_disable_interrupts(struct ql3_adapter *qdev)
 259 {
 260         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 261
 262         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
 263                             (ISP_IMR_ENABLE_INT << 16));
 264
 265 }
 266
 267 static void ql_enable_interrupts(struct ql3_adapter *qdev)
 268 {
 269         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
 270
 271         ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
 272                             ((0xff << 16) | ISP_IMR_ENABLE_INT));
 273
 274 }
 275
 276 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
 277                                             struct ql_rcv_buf_cb *lrg_buf_cb)
 278 {
 279         u64 map;
 280         lrg_buf_cb->next = NULL;
 281
 282         if (qdev->lrg_buf_free_tail == NULL) {  /* The list is empty  */
 283                 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
 284         } else {
 285                 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
 286                 qdev->lrg_buf_free_tail = lrg_buf_cb;
 287         }
 288
 289         if (!lrg_buf_cb->skb) {
 290                 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
 291                                                    qdev->lrg_buffer_len);
 292                 if (unlikely(!lrg_buf_cb->skb)) {
 293                         printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
 294                                qdev->ndev->name);
 295                         qdev->lrg_buf_skb_check++;
 296                 } else {
 297                         /*
 298                          * We save some space to copy the ethhdr from first
 299                          * buffer
 300                          */
 301                         skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
 302                         map = pci_map_single(qdev->pdev,
 303                                              lrg_buf_cb->skb->data,
 304                                              qdev->lrg_buffer_len -
 305                                              QL_HEADER_SPACE,
 306                                              PCI_DMA_FROMDEVICE);
 307                         lrg_buf_cb->buf_phy_addr_low =
 308                             cpu_to_le32(LS_64BITS(map));
 309                         lrg_buf_cb->buf_phy_addr_high =
 310                             cpu_to_le32(MS_64BITS(map));
 311                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
 312                         pci_unmap_len_set(lrg_buf_cb, maplen,
 313                                           qdev->lrg_buffer_len -
 314                                           QL_HEADER_SPACE);
 315                 }
 316         }
 317
 318         qdev->lrg_buf_free_count++;
 319 }
 320
 321 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
 322                                                            *qdev)
 323 {
 324         struct ql_rcv_buf_cb *lrg_buf_cb;
 325
 326         if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
 327                 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
 328                         qdev->lrg_buf_free_tail = NULL;
 329                 qdev->lrg_buf_free_count--;
 330         }
 331
 332         return lrg_buf_cb;
 333 }
 334
 335 static u32 addrBits = EEPROM_NO_ADDR_BITS;
 336 static u32 dataBits = EEPROM_NO_DATA_BITS;
 337
 338 static void fm93c56a_deselect(struct ql3_adapter *qdev);
 339 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
 340                             unsigned short *value);
 341
 342 /*
 343  * Caller holds hw_lock.
 344  */
 345 static void fm93c56a_select(struct ql3_adapter *qdev)
 346 {
 347         struct ql3xxx_port_registers __iomem *port_regs =
 348                         qdev->mem_map_registers;
 349
 350         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
 351         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 352                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
 353         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 354                             ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
 355 }
 356
 357 /*
 358  * Caller holds hw_lock.
 359  */
 360 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
 361 {
 362         int i;
 363         u32 mask;
 364         u32 dataBit;
 365         u32 previousBit;
 366         struct ql3xxx_port_registers __iomem *port_regs =
 367                         qdev->mem_map_registers;
 368
 369         /* Clock in a zero, then do the start bit */
 370         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 371                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 372                             AUBURN_EEPROM_DO_1);
 373         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 374                             ISP_NVRAM_MASK | qdev->
 375                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
 376                             AUBURN_EEPROM_CLK_RISE);
 377         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 378                             ISP_NVRAM_MASK | qdev->
 379                             eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
 380                             AUBURN_EEPROM_CLK_FALL);
 381
 382         mask = 1 << (FM93C56A_CMD_BITS - 1);
 383         /* Force the previous data bit to be different */
 384         previousBit = 0xffff;
 385         for (i = 0; i < FM93C56A_CMD_BITS; i++) {
 386                 dataBit =
 387                     (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
 388                 if (previousBit != dataBit) {
 389                         /*
 390                          * If the bit changed, then change the DO state to
 391                          * match
 392                          */
 393                         ql_write_nvram_reg(qdev,
 394                                             &port_regs->CommonRegs.
 395                                             serialPortInterfaceReg,
 396                                             ISP_NVRAM_MASK | qdev->
 397                                             eeprom_cmd_data | dataBit);
 398                         previousBit = dataBit;
 399                 }
 400                 ql_write_nvram_reg(qdev,
 401                                     &port_regs->CommonRegs.
 402                                     serialPortInterfaceReg,
 403                                     ISP_NVRAM_MASK | qdev->
 404                                     eeprom_cmd_data | dataBit |
 405                                     AUBURN_EEPROM_CLK_RISE);
 406                 ql_write_nvram_reg(qdev,
 407                                     &port_regs->CommonRegs.
 408                                     serialPortInterfaceReg,
 409                                     ISP_NVRAM_MASK | qdev->
 410                                     eeprom_cmd_data | dataBit |
 411                                     AUBURN_EEPROM_CLK_FALL);
 412                 cmd = cmd << 1;
 413         }
 414
 415         mask = 1 << (addrBits - 1);
 416         /* Force the previous data bit to be different */
 417         previousBit = 0xffff;
 418         for (i = 0; i < addrBits; i++) {
 419                 dataBit =
 420                     (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
 421                     AUBURN_EEPROM_DO_0;
 422                 if (previousBit != dataBit) {
 423                         /*
 424                          * If the bit changed, then change the DO state to
 425                          * match
 426                          */
 427                         ql_write_nvram_reg(qdev,
 428                                             &port_regs->CommonRegs.
 429                                             serialPortInterfaceReg,
 430                                             ISP_NVRAM_MASK | qdev->
 431                                             eeprom_cmd_data | dataBit);
 432                         previousBit = dataBit;
 433                 }
 434                 ql_write_nvram_reg(qdev,
 435                                     &port_regs->CommonRegs.
 436                                     serialPortInterfaceReg,
 437                                     ISP_NVRAM_MASK | qdev->
 438                                     eeprom_cmd_data | dataBit |
 439                                     AUBURN_EEPROM_CLK_RISE);
 440                 ql_write_nvram_reg(qdev,
 441                                     &port_regs->CommonRegs.
 442                                     serialPortInterfaceReg,
 443                                     ISP_NVRAM_MASK | qdev->
 444                                     eeprom_cmd_data | dataBit |
 445                                     AUBURN_EEPROM_CLK_FALL);
 446                 eepromAddr = eepromAddr << 1;
 447         }
 448 }
 449
 450 /*
 451  * Caller holds hw_lock.
 452  */
 453 static void fm93c56a_deselect(struct ql3_adapter *qdev)
 454 {
 455         struct ql3xxx_port_registers __iomem *port_regs =
 456                         qdev->mem_map_registers;
 457         qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
 458         ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
 459                             ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
 460 }
 461
 462 /*
 463  * Caller holds hw_lock.
 464  */
 465 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
 466 {
 467         int i;
 468         u32 data = 0;
 469         u32 dataBit;
 470         struct ql3xxx_port_registers __iomem *port_regs =
 471                         qdev->mem_map_registers;
 472
 473         /* Read the data bits */
 474         /* The first bit is a dummy.  Clock right over it. */
 475         for (i = 0; i < dataBits; i++) {
 476                 ql_write_nvram_reg(qdev,
 477                                     &port_regs->CommonRegs.
 478                                     serialPortInterfaceReg,
 479                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 480                                     AUBURN_EEPROM_CLK_RISE);
 481                 ql_write_nvram_reg(qdev,
 482                                     &port_regs->CommonRegs.
 483                                     serialPortInterfaceReg,
 484                                     ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
 485                                     AUBURN_EEPROM_CLK_FALL);
 486                 dataBit =
 487                     (ql_read_common_reg
 488                      (qdev,
 489                       &port_regs->CommonRegs.
 490                       serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
 491                 data = (data << 1) | dataBit;
 492         }
 493         *value = (u16) data;
 494 }
 495
 496 /*
 497  * Caller holds hw_lock.
 498  */
 499 static void eeprom_readword(struct ql3_adapter *qdev,
 500                             u32 eepromAddr, unsigned short *value)
 501 {
 502         fm93c56a_select(qdev);
 503         fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
 504         fm93c56a_datain(qdev, value);
 505         fm93c56a_deselect(qdev);
 506 }
 507
 508 static void ql_swap_mac_addr(u8 * macAddress)
 509 {
 510 #ifdef __BIG_ENDIAN
 511         u8 temp;
 512         temp = macAddress[0];
 513         macAddress[0] = macAddress[1];
 514         macAddress[1] = temp;
 515         temp = macAddress[2];
 516         macAddress[2] = macAddress[3];
 517         macAddress[3] = temp;
 518         temp = macAddress[4];
 519         macAddress[4] = macAddress[5];
 520         macAddress[5] = temp;
 521 #endif
 522 }
 523
 524 static int ql_get_nvram_params(struct ql3_adapter *qdev)
 525 {
 526         u16 *pEEPROMData;
 527         u16 checksum = 0;
 528         u32 index;
 529         unsigned long hw_flags;
 530
 531         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 532
 533         pEEPROMData = (u16 *) & qdev->nvram_data;
 534         qdev->eeprom_cmd_data = 0;
 535         if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
 536                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
 537                          2) << 10)) {
 538                 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
 539                         __func__);
 540                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 541                 return -1;
 542         }
 543
 544         for (index = 0; index < EEPROM_SIZE; index++) {
 545                 eeprom_readword(qdev, index, pEEPROMData);
 546                 checksum += *pEEPROMData;
 547                 pEEPROMData++;
 548         }
 549         ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
 550
 551         if (checksum != 0) {
 552                 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
 553                        qdev->ndev->name, checksum);
 554                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 555                 return -1;
 556         }
 557
 558         /*
 559          * We have a problem with endianness for the MAC addresses
 560          * and the two 8-bit values version, and numPorts.  We
 561          * have to swap them on big endian systems.
 562          */
 563         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
 564         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
 565         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
 566         ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
 567         pEEPROMData = (u16 *) & qdev->nvram_data.version;
 568         *pEEPROMData = le16_to_cpu(*pEEPROMData);
 569
 570         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 571         return checksum;
 572 }
 573
 574 static const u32 PHYAddr[2] = {
 575         PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
 576 };
 577
 578 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
 579 {
 580         struct ql3xxx_port_registers __iomem *port_regs =
 581                         qdev->mem_map_registers;
 582         u32 temp;
 583         int count = 1000;
 584
 585         while (count) {
 586                 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
 587                 if (!(temp & MAC_MII_STATUS_BSY))
 588                         return 0;
 589                 udelay(10);
 590                 count--;
 591         }
 592         return -1;
 593 }
 594
 595 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
 596 {
 597         struct ql3xxx_port_registers __iomem *port_regs =
 598                         qdev->mem_map_registers;
 599         u32 scanControl;
 600
 601         if (qdev->numPorts > 1) {
 602                 /* Auto scan will cycle through multiple ports */
 603                 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
 604         } else {
 605                 scanControl = MAC_MII_CONTROL_SC;
 606         }
 607
 608         /*
 609          * Scan register 1 of PHY/PETBI,
 610          * Set up to scan both devices
 611          * The autoscan starts from the first register, completes
 612          * the last one before rolling over to the first
 613          */
 614         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 615                            PHYAddr[0] | MII_SCAN_REGISTER);
 616
 617         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 618                            (scanControl) |
 619                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
 620 }
 621
 622 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
 623 {
 624         u8 ret;
 625         struct ql3xxx_port_registers __iomem *port_regs =
 626                                         qdev->mem_map_registers;
 627
 628         /* See if scan mode is enabled before we turn it off */
 629         if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
 630             (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
 631                 /* Scan is enabled */
 632                 ret = 1;
 633         } else {
 634                 /* Scan is disabled */
 635                 ret = 0;
 636         }
 637
 638         /*
 639          * When disabling scan mode you must first change the MII register
 640          * address
 641          */
 642         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 643                            PHYAddr[0] | MII_SCAN_REGISTER);
 644
 645         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 646                            ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
 647                              MAC_MII_CONTROL_RC) << 16));
 648
 649         return ret;
 650 }
 651
 652 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
 653                                u16 regAddr, u16 value, u32 mac_index)
 654 {
 655         struct ql3xxx_port_registers __iomem *port_regs =
 656                         qdev->mem_map_registers;
 657         u8 scanWasEnabled;
 658
 659         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
 660
 661         if (ql_wait_for_mii_ready(qdev)) {
 662                 if (netif_msg_link(qdev))
 663                         printk(KERN_WARNING PFX
 664                                "%s Timed out waiting for management port to "
 665                                "get free before issuing command.\n",
 666                                qdev->ndev->name);
 667                 return -1;
 668         }
 669
 670         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 671                            PHYAddr[mac_index] | regAddr);
 672
 673         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
 674
 675         /* Wait for write to complete 9/10/04 SJP */
 676         if (ql_wait_for_mii_ready(qdev)) {
 677                 if (netif_msg_link(qdev))
 678                         printk(KERN_WARNING PFX
 679                                "%s: Timed out waiting for management port to"
 680                                "get free before issuing command.\n",
 681                                qdev->ndev->name);
 682                 return -1;
 683         }
 684
 685         if (scanWasEnabled)
 686                 ql_mii_enable_scan_mode(qdev);
 687
 688         return 0;
 689 }
 690
 691 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
 692                               u16 * value, u32 mac_index)
 693 {
 694         struct ql3xxx_port_registers __iomem *port_regs =
 695                         qdev->mem_map_registers;
 696         u8 scanWasEnabled;
 697         u32 temp;
 698
 699         scanWasEnabled = ql_mii_disable_scan_mode(qdev);
 700
 701         if (ql_wait_for_mii_ready(qdev)) {
 702                 if (netif_msg_link(qdev))
 703                         printk(KERN_WARNING PFX
 704                                "%s: Timed out waiting for management port to "
 705                                "get free before issuing command.\n",
 706                                qdev->ndev->name);
 707                 return -1;
 708         }
 709
 710         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 711                            PHYAddr[mac_index] | regAddr);
 712
 713         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 714                            (MAC_MII_CONTROL_RC << 16));
 715
 716         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 717                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
 718
 719         /* Wait for the read to complete */
 720         if (ql_wait_for_mii_ready(qdev)) {
 721                 if (netif_msg_link(qdev))
 722                         printk(KERN_WARNING PFX
 723                                "%s: Timed out waiting for management port to "
 724                                "get free after issuing command.\n",
 725                                qdev->ndev->name);
 726                 return -1;
 727         }
 728
 729         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
 730         *value = (u16) temp;
 731
 732         if (scanWasEnabled)
 733                 ql_mii_enable_scan_mode(qdev);
 734
 735         return 0;
 736 }
 737
 738 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
 739 {
 740         struct ql3xxx_port_registers __iomem *port_regs =
 741                         qdev->mem_map_registers;
 742
 743         ql_mii_disable_scan_mode(qdev);
 744
 745         if (ql_wait_for_mii_ready(qdev)) {
 746                 if (netif_msg_link(qdev))
 747                         printk(KERN_WARNING PFX
 748                                "%s: Timed out waiting for management port to "
 749                                "get free before issuing command.\n",
 750                                qdev->ndev->name);
 751                 return -1;
 752         }
 753
 754         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 755                            qdev->PHYAddr | regAddr);
 756
 757         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
 758
 759         /* Wait for write to complete. */
 760         if (ql_wait_for_mii_ready(qdev)) {
 761                 if (netif_msg_link(qdev))
 762                         printk(KERN_WARNING PFX
 763                                "%s: Timed out waiting for management port to "
 764                                "get free before issuing command.\n",
 765                                qdev->ndev->name);
 766                 return -1;
 767         }
 768
 769         ql_mii_enable_scan_mode(qdev);
 770
 771         return 0;
 772 }
 773
 774 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
 775 {
 776         u32 temp;
 777         struct ql3xxx_port_registers __iomem *port_regs =
 778                         qdev->mem_map_registers;
 779
 780         ql_mii_disable_scan_mode(qdev);
 781
 782         if (ql_wait_for_mii_ready(qdev)) {
 783                 if (netif_msg_link(qdev))
 784                         printk(KERN_WARNING PFX
 785                                "%s: Timed out waiting for management port to "
 786                                "get free before issuing command.\n",
 787                                qdev->ndev->name);
 788                 return -1;
 789         }
 790
 791         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
 792                            qdev->PHYAddr | regAddr);
 793
 794         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 795                            (MAC_MII_CONTROL_RC << 16));
 796
 797         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
 798                            (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
 799
 800         /* Wait for the read to complete */
 801         if (ql_wait_for_mii_ready(qdev)) {
 802                 if (netif_msg_link(qdev))
 803                         printk(KERN_WARNING PFX
 804                                "%s: Timed out waiting for management port to "
 805                                "get free before issuing command.\n",
 806                                qdev->ndev->name);
 807                 return -1;
 808         }
 809
 810         temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
 811         *value = (u16) temp;
 812
 813         ql_mii_enable_scan_mode(qdev);
 814
 815         return 0;
 816 }
 817
 818 static void ql_petbi_reset(struct ql3_adapter *qdev)
 819 {
 820         ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
 821 }
 822
 823 static void ql_petbi_start_neg(struct ql3_adapter *qdev)
 824 {
 825         u16 reg;
 826
 827         /* Enable Auto-negotiation sense */
 828         ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
 829         reg |= PETBI_TBI_AUTO_SENSE;
 830         ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
 831
 832         ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
 833                          PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
 834
 835         ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
 836                          PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
 837                          PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
 838
 839 }
 840
 841 static void ql_petbi_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
 842 {
 843         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
 844                             mac_index);
 845 }
 846
 847 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
 848 {
 849         u16 reg;
 850
 851         /* Enable Auto-negotiation sense */
 852         ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg, mac_index);
 853         reg |= PETBI_TBI_AUTO_SENSE;
 854         ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, mac_index);
 855
 856         ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
 857                             PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX, mac_index);
 858
 859         ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
 860                             PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
 861                             PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
 862                             mac_index);
 863 }
 864
 865 static void ql_petbi_init(struct ql3_adapter *qdev)
 866 {
 867         ql_petbi_reset(qdev);
 868         ql_petbi_start_neg(qdev);
 869 }
 870
 871 static void ql_petbi_init_ex(struct ql3_adapter *qdev, u32 mac_index)
 872 {
 873         ql_petbi_reset_ex(qdev, mac_index);
 874         ql_petbi_start_neg_ex(qdev, mac_index);
 875 }
 876
 877 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
 878 {
 879         u16 reg;
 880
 881         if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
 882                 return 0;
 883
 884         return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
 885 }
 886
 887 static int ql_phy_get_speed(struct ql3_adapter *qdev)
 888 {
 889         u16 reg;
 890
 891         if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
 892                 return 0;
 893
 894         reg = (((reg & 0x18) >> 3) & 3);
 895
 896         if (reg == 2)
 897                 return SPEED_1000;
 898         else if (reg == 1)
 899                 return SPEED_100;
 900         else if (reg == 0)
 901                 return SPEED_10;
 902         else
 903                 return -1;
 904 }
 905
 906 static int ql_is_full_dup(struct ql3_adapter *qdev)
 907 {
 908         u16 reg;
 909
 910         if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
 911                 return 0;
 912
 913         return (reg & PHY_AUX_DUPLEX_STAT) != 0;
 914 }
 915
 916 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
 917 {
 918         u16 reg;
 919
 920         if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
 921                 return 0;
 922
 923         return (reg & PHY_NEG_PAUSE) != 0;
 924 }
 925
 926 /*
 927  * Caller holds hw_lock.
 928  */
 929 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
 930 {
 931         struct ql3xxx_port_registers __iomem *port_regs =
 932                         qdev->mem_map_registers;
 933         u32 value;
 934
 935         if (enable)
 936                 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
 937         else
 938                 value = (MAC_CONFIG_REG_PE << 16);
 939
 940         if (qdev->mac_index)
 941                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
 942         else
 943                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
 944 }
 945
 946 /*
 947  * Caller holds hw_lock.
 948  */
 949 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
 950 {
 951         struct ql3xxx_port_registers __iomem *port_regs =
 952                         qdev->mem_map_registers;
 953         u32 value;
 954
 955         if (enable)
 956                 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
 957         else
 958                 value = (MAC_CONFIG_REG_SR << 16);
 959
 960         if (qdev->mac_index)
 961                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
 962         else
 963                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
 964 }
 965
 966 /*
 967  * Caller holds hw_lock.
 968  */
 969 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
 970 {
 971         struct ql3xxx_port_registers __iomem *port_regs =
 972                         qdev->mem_map_registers;
 973         u32 value;
 974
 975         if (enable)
 976                 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
 977         else
 978                 value = (MAC_CONFIG_REG_GM << 16);
 979
 980         if (qdev->mac_index)
 981                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
 982         else
 983                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
 984 }
 985
 986 /*
 987  * Caller holds hw_lock.
 988  */
 989 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
 990 {
 991         struct ql3xxx_port_registers __iomem *port_regs =
 992                         qdev->mem_map_registers;
 993         u32 value;
 994
 995         if (enable)
 996                 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
 997         else
 998                 value = (MAC_CONFIG_REG_FD << 16);
 999
1000         if (qdev->mac_index)
1001                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1002         else
1003                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1004 }
1005
1006 /*
1007  * Caller holds hw_lock.
1008  */
1009 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1010 {
1011         struct ql3xxx_port_registers __iomem *port_regs =
1012                         qdev->mem_map_registers;
1013         u32 value;
1014
1015         if (enable)
1016                 value =
1017                     ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1018                      ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1019         else
1020                 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1021
1022         if (qdev->mac_index)
1023                 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1024         else
1025                 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1026 }
1027
1028 /*
1029  * Caller holds hw_lock.
1030  */
1031 static int ql_is_fiber(struct ql3_adapter *qdev)
1032 {
1033         struct ql3xxx_port_registers __iomem *port_regs =
1034                         qdev->mem_map_registers;
1035         u32 bitToCheck = 0;
1036         u32 temp;
1037
1038         switch (qdev->mac_index) {
1039         case 0:
1040                 bitToCheck = PORT_STATUS_SM0;
1041                 break;
1042         case 1:
1043                 bitToCheck = PORT_STATUS_SM1;
1044                 break;
1045         }
1046
1047         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1048         return (temp & bitToCheck) != 0;
1049 }
1050
1051 static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1052 {
1053         u16 reg;
1054         ql_mii_read_reg(qdev, 0x00, &reg);
1055         return (reg & 0x1000) != 0;
1056 }
1057
1058 /*
1059  * Caller holds hw_lock.
1060  */
1061 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1062 {
1063         struct ql3xxx_port_registers __iomem *port_regs =
1064                         qdev->mem_map_registers;
1065         u32 bitToCheck = 0;
1066         u32 temp;
1067
1068         switch (qdev->mac_index) {
1069         case 0:
1070                 bitToCheck = PORT_STATUS_AC0;
1071                 break;
1072         case 1:
1073                 bitToCheck = PORT_STATUS_AC1;
1074                 break;
1075         }
1076
1077         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1078         if (temp & bitToCheck) {
1079                 if (netif_msg_link(qdev))
1080                         printk(KERN_INFO PFX
1081                                "%s: Auto-Negotiate complete.\n",
1082                                qdev->ndev->name);
1083                 return 1;
1084         } else {
1085                 if (netif_msg_link(qdev))
1086                         printk(KERN_WARNING PFX
1087                                "%s: Auto-Negotiate incomplete.\n",
1088                                qdev->ndev->name);
1089                 return 0;
1090         }
1091 }
1092
1093 /*
1094  *  ql_is_neg_pause() returns 1 if pause was negotiated to be on
1095  */
1096 static int ql_is_neg_pause(struct ql3_adapter *qdev)
1097 {
1098         if (ql_is_fiber(qdev))
1099                 return ql_is_petbi_neg_pause(qdev);
1100         else
1101                 return ql_is_phy_neg_pause(qdev);
1102 }
1103
1104 static int ql_auto_neg_error(struct ql3_adapter *qdev)
1105 {
1106         struct ql3xxx_port_registers __iomem *port_regs =
1107                         qdev->mem_map_registers;
1108         u32 bitToCheck = 0;
1109         u32 temp;
1110
1111         switch (qdev->mac_index) {
1112         case 0:
1113                 bitToCheck = PORT_STATUS_AE0;
1114                 break;
1115         case 1:
1116                 bitToCheck = PORT_STATUS_AE1;
1117                 break;
1118         }
1119         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1120         return (temp & bitToCheck) != 0;
1121 }
1122
1123 static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1124 {
1125         if (ql_is_fiber(qdev))
1126                 return SPEED_1000;
1127         else
1128                 return ql_phy_get_speed(qdev);
1129 }
1130
1131 static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1132 {
1133         if (ql_is_fiber(qdev))
1134                 return 1;
1135         else
1136                 return ql_is_full_dup(qdev);
1137 }
1138
1139 /*
1140  * Caller holds hw_lock.
1141  */
1142 static int ql_link_down_detect(struct ql3_adapter *qdev)
1143 {
1144         struct ql3xxx_port_registers __iomem *port_regs =
1145                         qdev->mem_map_registers;
1146         u32 bitToCheck = 0;
1147         u32 temp;
1148
1149         switch (qdev->mac_index) {
1150         case 0:
1151                 bitToCheck = ISP_CONTROL_LINK_DN_0;
1152                 break;
1153         case 1:
1154                 bitToCheck = ISP_CONTROL_LINK_DN_1;
1155                 break;
1156         }
1157
1158         temp =
1159             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1160         return (temp & bitToCheck) != 0;
1161 }
1162
1163 /*
1164  * Caller holds hw_lock.
1165  */
1166 static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1167 {
1168         struct ql3xxx_port_registers __iomem *port_regs =
1169                         qdev->mem_map_registers;
1170
1171         switch (qdev->mac_index) {
1172         case 0:
1173                 ql_write_common_reg(qdev,
1174                                     &port_regs->CommonRegs.ispControlStatus,
1175                                     (ISP_CONTROL_LINK_DN_0) |
1176                                     (ISP_CONTROL_LINK_DN_0 << 16));
1177                 break;
1178
1179         case 1:
1180                 ql_write_common_reg(qdev,
1181                                     &port_regs->CommonRegs.ispControlStatus,
1182                                     (ISP_CONTROL_LINK_DN_1) |
1183                                     (ISP_CONTROL_LINK_DN_1 << 16));
1184                 break;
1185
1186         default:
1187                 return 1;
1188         }
1189
1190         return 0;
1191 }
1192
1193 /*
1194  * Caller holds hw_lock.
1195  */
1196 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev,
1197                                          u32 mac_index)
1198 {
1199         struct ql3xxx_port_registers __iomem *port_regs =
1200                         qdev->mem_map_registers;
1201         u32 bitToCheck = 0;
1202         u32 temp;
1203
1204         switch (mac_index) {
1205         case 0:
1206                 bitToCheck = PORT_STATUS_F1_ENABLED;
1207                 break;
1208         case 1:
1209                 bitToCheck = PORT_STATUS_F3_ENABLED;
1210                 break;
1211         default:
1212                 break;
1213         }
1214
1215         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1216         if (temp & bitToCheck) {
1217                 if (netif_msg_link(qdev))
1218                         printk(KERN_DEBUG PFX
1219                                "%s: is not link master.\n", qdev->ndev->name);
1220                 return 0;
1221         } else {
1222                 if (netif_msg_link(qdev))
1223                         printk(KERN_DEBUG PFX
1224                                "%s: is link master.\n", qdev->ndev->name);
1225                 return 1;
1226         }
1227 }
1228
1229 static void ql_phy_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
1230 {
1231         ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, mac_index);
1232 }
1233
1234 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
1235 {
1236         u16 reg;
1237
1238         ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER,
1239                             PHY_NEG_PAUSE | PHY_NEG_ADV_SPEED | 1, mac_index);
1240
1241         ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, mac_index);
1242         ql_mii_write_reg_ex(qdev, CONTROL_REG, reg | PHY_CTRL_RESTART_NEG,
1243                             mac_index);
1244 }
1245
1246 static void ql_phy_init_ex(struct ql3_adapter *qdev, u32 mac_index)
1247 {
1248         ql_phy_reset_ex(qdev, mac_index);
1249         ql_phy_start_neg_ex(qdev, mac_index);
1250 }
1251
1252 /*
1253  * Caller holds hw_lock.
1254  */
1255 static u32 ql_get_link_state(struct ql3_adapter *qdev)
1256 {
1257         struct ql3xxx_port_registers __iomem *port_regs =
1258                         qdev->mem_map_registers;
1259         u32 bitToCheck = 0;
1260         u32 temp, linkState;
1261
1262         switch (qdev->mac_index) {
1263         case 0:
1264                 bitToCheck = PORT_STATUS_UP0;
1265                 break;
1266         case 1:
1267                 bitToCheck = PORT_STATUS_UP1;
1268                 break;
1269         }
1270         temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1271         if (temp & bitToCheck) {
1272                 linkState = LS_UP;
1273         } else {
1274                 linkState = LS_DOWN;
1275                 if (netif_msg_link(qdev))
1276                         printk(KERN_WARNING PFX
1277                                "%s: Link is down.\n", qdev->ndev->name);
1278         }
1279         return linkState;
1280 }
1281
1282 static int ql_port_start(struct ql3_adapter *qdev)
1283 {
1284         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1285                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1286                          2) << 7))
1287                 return -1;
1288
1289         if (ql_is_fiber(qdev)) {
1290                 ql_petbi_init(qdev);
1291         } else {
1292                 /* Copper port */
1293                 ql_phy_init_ex(qdev, qdev->mac_index);
1294         }
1295
1296         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1297         return 0;
1298 }
1299
1300 static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1301 {
1302
1303         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1304                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1305                          2) << 7))
1306                 return -1;
1307
1308         if (!ql_auto_neg_error(qdev)) {
1309                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1310                         /* configure the MAC */
1311                         if (netif_msg_link(qdev))
1312                                 printk(KERN_DEBUG PFX
1313                                        "%s: Configuring link.\n",
1314                                        qdev->ndev->
1315                                        name);
1316                         ql_mac_cfg_soft_reset(qdev, 1);
1317                         ql_mac_cfg_gig(qdev,
1318                                        (ql_get_link_speed
1319                                         (qdev) ==
1320                                         SPEED_1000));
1321                         ql_mac_cfg_full_dup(qdev,
1322                                             ql_is_link_full_dup
1323                                             (qdev));
1324                         ql_mac_cfg_pause(qdev,
1325                                          ql_is_neg_pause
1326                                          (qdev));
1327                         ql_mac_cfg_soft_reset(qdev, 0);
1328
1329                         /* enable the MAC */
1330                         if (netif_msg_link(qdev))
1331                                 printk(KERN_DEBUG PFX
1332                                        "%s: Enabling mac.\n",
1333                                        qdev->ndev->
1334                                                name);
1335                         ql_mac_enable(qdev, 1);
1336                 }
1337
1338                 if (netif_msg_link(qdev))
1339                         printk(KERN_DEBUG PFX
1340                                "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1341                                qdev->ndev->name);
1342                 qdev->port_link_state = LS_UP;
1343                 netif_start_queue(qdev->ndev);
1344                 netif_carrier_on(qdev->ndev);
1345                 if (netif_msg_link(qdev))
1346                         printk(KERN_INFO PFX
1347                                "%s: Link is up at %d Mbps, %s duplex.\n",
1348                                qdev->ndev->name,
1349                                ql_get_link_speed(qdev),
1350                                ql_is_link_full_dup(qdev)
1351                                ? "full" : "half");
1352
1353         } else {        /* Remote error detected */
1354
1355                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1356                         if (netif_msg_link(qdev))
1357                                 printk(KERN_DEBUG PFX
1358                                        "%s: Remote error detected. "
1359                                        "Calling ql_port_start().\n",
1360                                        qdev->ndev->
1361                                        name);
1362                         /*
1363                          * ql_port_start() is shared code and needs
1364                          * to lock the PHY on it's own.
1365                          */
1366                         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1367                         if(ql_port_start(qdev)) {/* Restart port */
1368                                 return -1;
1369                         } else
1370                                 return 0;
1371                 }
1372         }
1373         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1374         return 0;
1375 }
1376
1377 static void ql_link_state_machine(struct ql3_adapter *qdev)
1378 {
1379         u32 curr_link_state;
1380         unsigned long hw_flags;
1381
1382         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1383
1384         curr_link_state = ql_get_link_state(qdev);
1385
1386         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1387                 if (netif_msg_link(qdev))
1388                         printk(KERN_INFO PFX
1389                                "%s: Reset in progress, skip processing link "
1390                                "state.\n", qdev->ndev->name);
1391
1392                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1393                 return;
1394         }
1395
1396         switch (qdev->port_link_state) {
1397         default:
1398                 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1399                         ql_port_start(qdev);
1400                 }
1401                 qdev->port_link_state = LS_DOWN;
1402                 /* Fall Through */
1403
1404         case LS_DOWN:
1405                 if (netif_msg_link(qdev))
1406                         printk(KERN_DEBUG PFX
1407                                "%s: port_link_state = LS_DOWN.\n",
1408                                qdev->ndev->name);
1409                 if (curr_link_state == LS_UP) {
1410                         if (netif_msg_link(qdev))
1411                                 printk(KERN_DEBUG PFX
1412                                        "%s: curr_link_state = LS_UP.\n",
1413                                        qdev->ndev->name);
1414                         if (ql_is_auto_neg_complete(qdev))
1415                                 ql_finish_auto_neg(qdev);
1416
1417                         if (qdev->port_link_state == LS_UP)
1418                                 ql_link_down_detect_clear(qdev);
1419
1420                 }
1421                 break;
1422
1423         case LS_UP:
1424                 /*
1425                  * See if the link is currently down or went down and came
1426                  * back up
1427                  */
1428                 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1429                         if (netif_msg_link(qdev))
1430                                 printk(KERN_INFO PFX "%s: Link is down.\n",
1431                                        qdev->ndev->name);
1432                         qdev->port_link_state = LS_DOWN;
1433                 }
1434                 break;
1435         }
1436         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1437 }
1438
1439 /*
1440  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1441  */
1442 static void ql_get_phy_owner(struct ql3_adapter *qdev)
1443 {
1444         if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1445                 set_bit(QL_LINK_MASTER,&qdev->flags);
1446         else
1447                 clear_bit(QL_LINK_MASTER,&qdev->flags);
1448 }
1449
1450 /*
1451  * Caller must take hw_lock and QL_PHY_GIO_SEM.
1452  */
1453 static void ql_init_scan_mode(struct ql3_adapter *qdev)
1454 {
1455         ql_mii_enable_scan_mode(qdev);
1456
1457         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1458                 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1459                         ql_petbi_init_ex(qdev, qdev->mac_index);
1460         } else {
1461                 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1462                         ql_phy_init_ex(qdev, qdev->mac_index);
1463         }
1464 }
1465
1466 /*
1467  * MII_Setup needs to be called before taking the PHY out of reset so that the
1468  * management interface clock speed can be set properly.  It would be better if
1469  * we had a way to disable MDC until after the PHY is out of reset, but we
1470  * don't have that capability.
1471  */
1472 static int ql_mii_setup(struct ql3_adapter *qdev)
1473 {
1474         u32 reg;
1475         struct ql3xxx_port_registers __iomem *port_regs =
1476                         qdev->mem_map_registers;
1477
1478         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1479                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1480                          2) << 7))
1481                 return -1;
1482
1483         if (qdev->device_id == QL3032_DEVICE_ID)
1484                 ql_write_page0_reg(qdev,
1485                         &port_regs->macMIIMgmtControlReg, 0x0f00000);
1486
1487         /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1488         reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1489
1490         ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1491                            reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1492
1493         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1494         return 0;
1495 }
1496
1497 static u32 ql_supported_modes(struct ql3_adapter *qdev)
1498 {
1499         u32 supported;
1500
1501         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1502                 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1503                     | SUPPORTED_Autoneg;
1504         } else {
1505                 supported = SUPPORTED_10baseT_Half
1506                     | SUPPORTED_10baseT_Full
1507                     | SUPPORTED_100baseT_Half
1508                     | SUPPORTED_100baseT_Full
1509                     | SUPPORTED_1000baseT_Half
1510                     | SUPPORTED_1000baseT_Full
1511                     | SUPPORTED_Autoneg | SUPPORTED_TP;
1512         }
1513
1514         return supported;
1515 }
1516
1517 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1518 {
1519         int status;
1520         unsigned long hw_flags;
1521         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1522         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1523                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1524                          2) << 7)) {
1525                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1526                 return 0;
1527         }
1528         status = ql_is_auto_cfg(qdev);
1529         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1530         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1531         return status;
1532 }
1533
1534 static u32 ql_get_speed(struct ql3_adapter *qdev)
1535 {
1536         u32 status;
1537         unsigned long hw_flags;
1538         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1539         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1540                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1541                          2) << 7)) {
1542                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1543                 return 0;
1544         }
1545         status = ql_get_link_speed(qdev);
1546         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1547         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1548         return status;
1549 }
1550
1551 static int ql_get_full_dup(struct ql3_adapter *qdev)
1552 {
1553         int status;
1554         unsigned long hw_flags;
1555         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1556         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1557                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1558                          2) << 7)) {
1559                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1560                 return 0;
1561         }
1562         status = ql_is_link_full_dup(qdev);
1563         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1564         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1565         return status;
1566 }
1567
1568
1569 static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1570 {
1571         struct ql3_adapter *qdev = netdev_priv(ndev);
1572
1573         ecmd->transceiver = XCVR_INTERNAL;
1574         ecmd->supported = ql_supported_modes(qdev);
1575
1576         if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1577                 ecmd->port = PORT_FIBRE;
1578         } else {
1579                 ecmd->port = PORT_TP;
1580                 ecmd->phy_address = qdev->PHYAddr;
1581         }
1582         ecmd->advertising = ql_supported_modes(qdev);
1583         ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1584         ecmd->speed = ql_get_speed(qdev);
1585         ecmd->duplex = ql_get_full_dup(qdev);
1586         return 0;
1587 }
1588
1589 static void ql_get_drvinfo(struct net_device *ndev,
1590                            struct ethtool_drvinfo *drvinfo)
1591 {
1592         struct ql3_adapter *qdev = netdev_priv(ndev);
1593         strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1594         strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1595         strncpy(drvinfo->fw_version, "N/A", 32);
1596         strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1597         drvinfo->n_stats = 0;
1598         drvinfo->testinfo_len = 0;
1599         drvinfo->regdump_len = 0;
1600         drvinfo->eedump_len = 0;
1601 }
1602
1603 static u32 ql_get_msglevel(struct net_device *ndev)
1604 {
1605         struct ql3_adapter *qdev = netdev_priv(ndev);
1606         return qdev->msg_enable;
1607 }
1608
1609 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1610 {
1611         struct ql3_adapter *qdev = netdev_priv(ndev);
1612         qdev->msg_enable = value;
1613 }
1614
1615 static const struct ethtool_ops ql3xxx_ethtool_ops = {
1616         .get_settings = ql_get_settings,
1617         .get_drvinfo = ql_get_drvinfo,
1618         .get_perm_addr = ethtool_op_get_perm_addr,
1619         .get_link = ethtool_op_get_link,
1620         .get_msglevel = ql_get_msglevel,
1621         .set_msglevel = ql_set_msglevel,
1622 };
1623
1624 static int ql_populate_free_queue(struct ql3_adapter *qdev)
1625 {
1626         struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1627         u64 map;
1628
1629         while (lrg_buf_cb) {
1630                 if (!lrg_buf_cb->skb) {
1631                         lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1632                                                            qdev->lrg_buffer_len);
1633                         if (unlikely(!lrg_buf_cb->skb)) {
1634                                 printk(KERN_DEBUG PFX
1635                                        "%s: Failed netdev_alloc_skb().\n",
1636                                        qdev->ndev->name);
1637                                 break;
1638                         } else {
1639                                 /*
1640                                  * We save some space to copy the ethhdr from
1641                                  * first buffer
1642                                  */
1643                                 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1644                                 map = pci_map_single(qdev->pdev,
1645                                                      lrg_buf_cb->skb->data,
1646                                                      qdev->lrg_buffer_len -
1647                                                      QL_HEADER_SPACE,
1648                                                      PCI_DMA_FROMDEVICE);
1649                                 lrg_buf_cb->buf_phy_addr_low =
1650                                     cpu_to_le32(LS_64BITS(map));
1651                                 lrg_buf_cb->buf_phy_addr_high =
1652                                     cpu_to_le32(MS_64BITS(map));
1653                                 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1654                                 pci_unmap_len_set(lrg_buf_cb, maplen,
1655                                                   qdev->lrg_buffer_len -
1656                                                   QL_HEADER_SPACE);
1657                                 --qdev->lrg_buf_skb_check;
1658                                 if (!qdev->lrg_buf_skb_check)
1659                                         return 1;
1660                         }
1661                 }
1662                 lrg_buf_cb = lrg_buf_cb->next;
1663         }
1664         return 0;
1665 }
1666
1667 /*
1668  * Caller holds hw_lock.
1669  */
1670 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1671 {
1672         struct bufq_addr_element *lrg_buf_q_ele;
1673         int i;
1674         struct ql_rcv_buf_cb *lrg_buf_cb;
1675         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1676
1677         if ((qdev->lrg_buf_free_count >= 8)
1678             && (qdev->lrg_buf_release_cnt >= 16)) {
1679
1680                 if (qdev->lrg_buf_skb_check)
1681                         if (!ql_populate_free_queue(qdev))
1682                                 return;
1683
1684                 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1685
1686                 while ((qdev->lrg_buf_release_cnt >= 16)
1687                        && (qdev->lrg_buf_free_count >= 8)) {
1688
1689                         for (i = 0; i < 8; i++) {
1690                                 lrg_buf_cb =
1691                                     ql_get_from_lrg_buf_free_list(qdev);
1692                                 lrg_buf_q_ele->addr_high =
1693                                     lrg_buf_cb->buf_phy_addr_high;
1694                                 lrg_buf_q_ele->addr_low =
1695                                     lrg_buf_cb->buf_phy_addr_low;
1696                                 lrg_buf_q_ele++;
1697
1698                                 qdev->lrg_buf_release_cnt--;
1699                         }
1700
1701                         qdev->lrg_buf_q_producer_index++;
1702
1703                         if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
1704                                 qdev->lrg_buf_q_producer_index = 0;
1705
1706                         if (qdev->lrg_buf_q_producer_index ==
1707                             (qdev->num_lbufq_entries - 1)) {
1708                                 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1709                         }
1710                 }
1711
1712                 qdev->lrg_buf_next_free = lrg_buf_q_ele;
1713
1714                 ql_write_common_reg(qdev,
1715                                     &port_regs->CommonRegs.
1716                                     rxLargeQProducerIndex,
1717                                     qdev->lrg_buf_q_producer_index);
1718         }
1719 }
1720
1721 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1722                                    struct ob_mac_iocb_rsp *mac_rsp)
1723 {
1724         struct ql_tx_buf_cb *tx_cb;
1725         int i;
1726
1727         tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1728         pci_unmap_single(qdev->pdev,
1729                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
1730                          pci_unmap_len(&tx_cb->map[0], maplen),
1731                          PCI_DMA_TODEVICE);
1732         tx_cb->seg_count--;
1733         if (tx_cb->seg_count) {
1734                 for (i = 1; i < tx_cb->seg_count; i++) {
1735                         pci_unmap_page(qdev->pdev,
1736                                        pci_unmap_addr(&tx_cb->map[i],
1737                                                       mapaddr),
1738                                        pci_unmap_len(&tx_cb->map[i], maplen),
1739                                        PCI_DMA_TODEVICE);
1740                 }
1741         }
1742         qdev->stats.tx_packets++;
1743         qdev->stats.tx_bytes += tx_cb->skb->len;
1744         dev_kfree_skb_irq(tx_cb->skb);
1745         tx_cb->skb = NULL;
1746         atomic_inc(&qdev->tx_count);
1747 }
1748
1749 void ql_get_sbuf(struct ql3_adapter *qdev)
1750 {
1751         if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1752                 qdev->small_buf_index = 0;
1753         qdev->small_buf_release_cnt++;
1754 }
1755
1756 struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
1757 {
1758         struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
1759         lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
1760         qdev->lrg_buf_release_cnt++;
1761         if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1762                 qdev->lrg_buf_index = 0;
1763         return(lrg_buf_cb);
1764 }
1765
1766 /*
1767  * The difference between 3022 and 3032 for inbound completions:
1768  * 3022 uses two buffers per completion.  The first buffer contains
1769  * (some) header info, the second the remainder of the headers plus
1770  * the data.  For this chip we reserve some space at the top of the
1771  * receive buffer so that the header info in buffer one can be
1772  * prepended to the buffer two.  Buffer two is the sent up while
1773  * buffer one is returned to the hardware to be reused.
1774  * 3032 receives all of it's data and headers in one buffer for a
1775  * simpler process.  3032 also supports checksum verification as
1776  * can be seen in ql_process_macip_rx_intr().
1777  */
1778 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
1779                                    struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
1780 {
1781         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1782         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1783         struct sk_buff *skb;
1784         u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
1785
1786         /*
1787          * Get the inbound address list (small buffer).
1788          */
1789         ql_get_sbuf(qdev);
1790
1791         if (qdev->device_id == QL3022_DEVICE_ID)
1792                 lrg_buf_cb1 = ql_get_lbuf(qdev);
1793
1794         /* start of second buffer */
1795         lrg_buf_cb2 = ql_get_lbuf(qdev);
1796         skb = lrg_buf_cb2->skb;
1797
1798         qdev->stats.rx_packets++;
1799         qdev->stats.rx_bytes += length;
1800
1801         skb_put(skb, length);
1802         pci_unmap_single(qdev->pdev,
1803                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
1804                          pci_unmap_len(lrg_buf_cb2, maplen),
1805                          PCI_DMA_FROMDEVICE);
1806         prefetch(skb->data);
1807         skb->dev = qdev->ndev;
1808         skb->ip_summed = CHECKSUM_NONE;
1809         skb->protocol = eth_type_trans(skb, qdev->ndev);
1810
1811         netif_receive_skb(skb);
1812         qdev->ndev->last_rx = jiffies;
1813         lrg_buf_cb2->skb = NULL;
1814
1815         if (qdev->device_id == QL3022_DEVICE_ID)
1816                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1817         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1818 }
1819
1820 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
1821                                      struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
1822 {
1823         struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1824         struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1825         struct sk_buff *skb1 = NULL, *skb2;
1826         struct net_device *ndev = qdev->ndev;
1827         u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
1828         u16 size = 0;
1829
1830         /*
1831          * Get the inbound address list (small buffer).
1832          */
1833
1834         ql_get_sbuf(qdev);
1835
1836         if (qdev->device_id == QL3022_DEVICE_ID) {
1837                 /* start of first buffer on 3022 */
1838                 lrg_buf_cb1 = ql_get_lbuf(qdev);
1839                 skb1 = lrg_buf_cb1->skb;
1840                 size = ETH_HLEN;
1841                 if (*((u16 *) skb1->data) != 0xFFFF)
1842                         size += VLAN_ETH_HLEN - ETH_HLEN;
1843         }
1844
1845         /* start of second buffer */
1846         lrg_buf_cb2 = ql_get_lbuf(qdev);
1847         skb2 = lrg_buf_cb2->skb;
1848
1849         skb_put(skb2, length);  /* Just the second buffer length here. */
1850         pci_unmap_single(qdev->pdev,
1851                          pci_unmap_addr(lrg_buf_cb2, mapaddr),
1852                          pci_unmap_len(lrg_buf_cb2, maplen),
1853                          PCI_DMA_FROMDEVICE);
1854         prefetch(skb2->data);
1855
1856         skb2->ip_summed = CHECKSUM_NONE;
1857         if (qdev->device_id == QL3022_DEVICE_ID) {
1858                 /*
1859                  * Copy the ethhdr from first buffer to second. This
1860                  * is necessary for 3022 IP completions.
1861                  */
1862                 memcpy(skb_push(skb2, size), skb1->data + VLAN_ID_LEN, size);
1863         } else {
1864                 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
1865                 if (checksum &
1866                         (IB_IP_IOCB_RSP_3032_ICE |
1867                          IB_IP_IOCB_RSP_3032_CE |
1868                          IB_IP_IOCB_RSP_3032_NUC)) {
1869                         printk(KERN_ERR
1870                                "%s: Bad checksum for this %s packet, checksum = %x.\n",
1871                                __func__,
1872                                ((checksum &
1873                                 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
1874                                 "UDP"),checksum);
1875                 } else if (checksum & IB_IP_IOCB_RSP_3032_TCP) {
1876                         skb2->ip_summed = CHECKSUM_UNNECESSARY;
1877                 }
1878         }
1879         skb2->dev = qdev->ndev;
1880         skb2->protocol = eth_type_trans(skb2, qdev->ndev);
1881
1882         netif_receive_skb(skb2);
1883         qdev->stats.rx_packets++;
1884         qdev->stats.rx_bytes += length;
1885         ndev->last_rx = jiffies;
1886         lrg_buf_cb2->skb = NULL;
1887
1888         if (qdev->device_id == QL3022_DEVICE_ID)
1889                 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1890         ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1891 }
1892
1893 static int ql_tx_rx_clean(struct ql3_adapter *qdev,
1894                           int *tx_cleaned, int *rx_cleaned, int work_to_do)
1895 {
1896         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1897         struct net_rsp_iocb *net_rsp;
1898         struct net_device *ndev = qdev->ndev;
1899         unsigned long hw_flags;
1900
1901         /* While there are entries in the completion queue. */
1902         while ((cpu_to_le32(*(qdev->prsp_producer_index)) !=
1903                 qdev->rsp_consumer_index) && (*rx_cleaned < work_to_do)) {
1904
1905                 net_rsp = qdev->rsp_current;
1906                 switch (net_rsp->opcode) {
1907
1908                 case OPCODE_OB_MAC_IOCB_FN0:
1909                 case OPCODE_OB_MAC_IOCB_FN2:
1910                         ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
1911                                                net_rsp);
1912                         (*tx_cleaned)++;
1913                         break;
1914
1915                 case OPCODE_IB_MAC_IOCB:
1916                 case OPCODE_IB_3032_MAC_IOCB:
1917                         ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
1918                                                net_rsp);
1919                         (*rx_cleaned)++;
1920                         break;
1921
1922                 case OPCODE_IB_IP_IOCB:
1923                 case OPCODE_IB_3032_IP_IOCB:
1924                         ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
1925                                                  net_rsp);
1926                         (*rx_cleaned)++;
1927                         break;
1928                 default:
1929                         {
1930                                 u32 *tmp = (u32 *) net_rsp;
1931                                 printk(KERN_ERR PFX
1932                                        "%s: Hit default case, not "
1933                                        "handled!\n"
1934                                        "        dropping the packet, opcode = "
1935                                        "%x.\n",
1936                                        ndev->name, net_rsp->opcode);
1937                                 printk(KERN_ERR PFX
1938                                        "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
1939                                        (unsigned long int)tmp[0],
1940                                        (unsigned long int)tmp[1],
1941                                        (unsigned long int)tmp[2],
1942                                        (unsigned long int)tmp[3]);
1943                         }
1944                 }
1945
1946                 qdev->rsp_consumer_index++;
1947
1948                 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
1949                         qdev->rsp_consumer_index = 0;
1950                         qdev->rsp_current = qdev->rsp_q_virt_addr;
1951                 } else {
1952                         qdev->rsp_current++;
1953                 }
1954         }
1955
1956         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1957
1958         ql_update_lrg_bufq_prod_index(qdev);
1959
1960         if (qdev->small_buf_release_cnt >= 16) {
1961                 while (qdev->small_buf_release_cnt >= 16) {
1962                         qdev->small_buf_q_producer_index++;
1963
1964                         if (qdev->small_buf_q_producer_index ==
1965                             NUM_SBUFQ_ENTRIES)
1966                                 qdev->small_buf_q_producer_index = 0;
1967                         qdev->small_buf_release_cnt -= 8;
1968                 }
1969
1970                 ql_write_common_reg(qdev,
1971                                     &port_regs->CommonRegs.
1972                                     rxSmallQProducerIndex,
1973                                     qdev->small_buf_q_producer_index);
1974         }
1975
1976         ql_write_common_reg(qdev,
1977                             &port_regs->CommonRegs.rspQConsumerIndex,
1978                             qdev->rsp_consumer_index);
1979         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1980
1981         if (unlikely(netif_queue_stopped(qdev->ndev))) {
1982                 if (netif_queue_stopped(qdev->ndev) &&
1983                     (atomic_read(&qdev->tx_count) > (NUM_REQ_Q_ENTRIES / 4)))
1984                         netif_wake_queue(qdev->ndev);
1985         }
1986
1987         return *tx_cleaned + *rx_cleaned;
1988 }
1989
1990 static int ql_poll(struct net_device *ndev, int *budget)
1991 {
1992         struct ql3_adapter *qdev = netdev_priv(ndev);
1993         int work_to_do = min(*budget, ndev->quota);
1994         int rx_cleaned = 0, tx_cleaned = 0;
1995
1996         if (!netif_carrier_ok(ndev))
1997                 goto quit_polling;
1998
1999         ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, work_to_do);
2000         *budget -= rx_cleaned;
2001         ndev->quota -= rx_cleaned;
2002
2003         if ((!tx_cleaned && !rx_cleaned) || !netif_running(ndev)) {
2004 quit_polling:
2005                 netif_rx_complete(ndev);
2006                 ql_enable_interrupts(qdev);
2007                 return 0;
2008         }
2009         return 1;
2010 }
2011
2012 static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2013 {
2014
2015         struct net_device *ndev = dev_id;
2016         struct ql3_adapter *qdev = netdev_priv(ndev);
2017         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2018         u32 value;
2019         int handled = 1;
2020         u32 var;
2021
2022         port_regs = qdev->mem_map_registers;
2023
2024         value =
2025             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2026
2027         if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2028                 spin_lock(&qdev->adapter_lock);
2029                 netif_stop_queue(qdev->ndev);
2030                 netif_carrier_off(qdev->ndev);
2031                 ql_disable_interrupts(qdev);
2032                 qdev->port_link_state = LS_DOWN;
2033                 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2034
2035                 if (value & ISP_CONTROL_FE) {
2036                         /*
2037                          * Chip Fatal Error.
2038                          */
2039                         var =
2040                             ql_read_page0_reg_l(qdev,
2041                                               &port_regs->PortFatalErrStatus);
2042                         printk(KERN_WARNING PFX
2043                                "%s: Resetting chip. PortFatalErrStatus "
2044                                "register = 0x%x\n", ndev->name, var);
2045                         set_bit(QL_RESET_START,&qdev->flags) ;
2046                 } else {
2047                         /*
2048                          * Soft Reset Requested.
2049                          */
2050                         set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2051                         printk(KERN_ERR PFX
2052                                "%s: Another function issued a reset to the "
2053                                "chip. ISR value = %x.\n", ndev->name, value);
2054                 }
2055                 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2056                 spin_unlock(&qdev->adapter_lock);
2057         } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2058                 ql_disable_interrupts(qdev);
2059                 if (likely(netif_rx_schedule_prep(ndev)))
2060                         __netif_rx_schedule(ndev);
2061                 else
2062                         ql_enable_interrupts(qdev);
2063         } else {
2064                 return IRQ_NONE;
2065         }
2066
2067         return IRQ_RETVAL(handled);
2068 }
2069
2070 /*
2071  * Get the total number of segments needed for the
2072  * given number of fragments.  This is necessary because
2073  * outbound address lists (OAL) will be used when more than
2074  * two frags are given.  Each address list has 5 addr/len
2075  * pairs.  The 5th pair in each AOL is used to  point to
2076  * the next AOL if more frags are coming.
2077  * That is why the frags:segment count  ratio is not linear.
2078  */
2079 static int ql_get_seg_count(unsigned short frags)
2080 {
2081         switch(frags) {
2082         case 0: return 1;       /* just the skb->data seg */
2083         case 1: return 2;       /* skb->data + 1 frag */
2084         case 2: return 3;       /* skb->data + 2 frags */
2085         case 3: return 5;       /* skb->data + 1 frag + 1 AOL containting 2 frags */
2086         case 4: return 6;
2087         case 5: return 7;
2088         case 6: return 8;
2089         case 7: return 10;
2090         case 8: return 11;
2091         case 9: return 12;
2092         case 10: return 13;
2093         case 11: return 15;
2094         case 12: return 16;
2095         case 13: return 17;
2096         case 14: return 18;
2097         case 15: return 20;
2098         case 16: return 21;
2099         case 17: return 22;
2100         case 18: return 23;
2101         }
2102         return -1;
2103 }
2104
2105 static void ql_hw_csum_setup(struct sk_buff *skb,
2106                              struct ob_mac_iocb_req *mac_iocb_ptr)
2107 {
2108         struct ethhdr *eth;
2109         struct iphdr *ip = NULL;
2110         u8 offset = ETH_HLEN;
2111
2112         eth = (struct ethhdr *)(skb->data);
2113
2114         if (eth->h_proto == __constant_htons(ETH_P_IP)) {
2115                 ip = (struct iphdr *)&skb->data[ETH_HLEN];
2116         } else if (eth->h_proto == htons(ETH_P_8021Q) &&
2117                    ((struct vlan_ethhdr *)skb->data)->
2118                    h_vlan_encapsulated_proto == __constant_htons(ETH_P_IP)) {
2119                 ip = (struct iphdr *)&skb->data[VLAN_ETH_HLEN];
2120                 offset = VLAN_ETH_HLEN;
2121         }
2122
2123         if (ip) {
2124                 if (ip->protocol == IPPROTO_TCP) {
2125                         mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC;
2126                         mac_iocb_ptr->ip_hdr_off = offset;
2127                         mac_iocb_ptr->ip_hdr_len = ip->ihl;
2128                 } else if (ip->protocol == IPPROTO_UDP) {
2129                         mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC;
2130                         mac_iocb_ptr->ip_hdr_off = offset;
2131                         mac_iocb_ptr->ip_hdr_len = ip->ihl;
2132                 }
2133         }
2134 }
2135
2136 /*
2137  * The difference between 3022 and 3032 sends:
2138  * 3022 only supports a simple single segment transmission.
2139  * 3032 supports checksumming and scatter/gather lists (fragments).
2140  * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2141  * in the IOCB plus a chain of outbound address lists (OAL) that
2142  * each contain 5 ALPs.  The last ALP of the IOCB (3rd) or OAL (5th)
2143  * will used to point to an OAL when more ALP entries are required.
2144  * The IOCB is always the top of the chain followed by one or more
2145  * OALs (when necessary).
2146  */
2147 static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2148 {
2149         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2150         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2151         struct ql_tx_buf_cb *tx_cb;
2152         u32 tot_len = skb->len;
2153         struct oal *oal;
2154         struct oal_entry *oal_entry;
2155         int len;
2156         struct ob_mac_iocb_req *mac_iocb_ptr;
2157         u64 map;
2158         int seg_cnt, seg = 0;
2159         int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2160
2161         if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
2162                 if (!netif_queue_stopped(ndev))
2163                         netif_stop_queue(ndev);
2164                 return NETDEV_TX_BUSY;
2165         }
2166         tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
2167         seg_cnt = tx_cb->seg_count = ql_get_seg_count((skb_shinfo(skb)->nr_frags));
2168         if(seg_cnt == -1) {
2169                 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2170                 return NETDEV_TX_OK;
2171
2172         }
2173         mac_iocb_ptr = tx_cb->queue_entry;
2174         mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2175         mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2176         mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2177         mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2178         tx_cb->skb = skb;
2179         if (skb->ip_summed == CHECKSUM_PARTIAL)
2180                 ql_hw_csum_setup(skb, mac_iocb_ptr);
2181         len = skb_headlen(skb);
2182         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2183         oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2184         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2185         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2186         oal_entry->len = cpu_to_le32(len);
2187         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2188         pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2189         seg++;
2190
2191         if (!skb_shinfo(skb)->nr_frags) {
2192                 /* Terminate the last segment. */
2193                 oal_entry->len =
2194                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2195         } else {
2196                 int i;
2197                 oal = tx_cb->oal;
2198                 for (i=0; i<frag_cnt; i++,seg++) {
2199                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2200                         oal_entry++;
2201                         if ((seg == 2 && seg_cnt > 3) ||        /* Check for continuation */
2202                             (seg == 7 && seg_cnt > 8) ||        /* requirements. It's strange */
2203                             (seg == 12 && seg_cnt > 13) ||      /* but necessary. */
2204                             (seg == 17 && seg_cnt > 18)) {
2205                                 /* Continuation entry points to outbound address list. */
2206                                 map = pci_map_single(qdev->pdev, oal,
2207                                                      sizeof(struct oal),
2208                                                      PCI_DMA_TODEVICE);
2209                                 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2210                                 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2211                                 oal_entry->len =
2212                                     cpu_to_le32(sizeof(struct oal) |
2213                                                 OAL_CONT_ENTRY);
2214                                 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2215                                                    map);
2216                                 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2217                                                   len);
2218                                 oal_entry = (struct oal_entry *)oal;
2219                                 oal++;
2220                                 seg++;
2221                         }
2222
2223                         map =
2224                             pci_map_page(qdev->pdev, frag->page,
2225                                          frag->page_offset, frag->size,
2226                                          PCI_DMA_TODEVICE);
2227                         oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2228                         oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2229                         oal_entry->len = cpu_to_le32(frag->size);
2230                         pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2231                         pci_unmap_len_set(&tx_cb->map[seg], maplen,
2232                                           frag->size);
2233                 }
2234                 /* Terminate the last segment. */
2235                 oal_entry->len =
2236                     cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2237         }
2238         wmb();
2239         qdev->req_producer_index++;
2240         if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2241                 qdev->req_producer_index = 0;
2242         wmb();
2243         ql_write_common_reg_l(qdev,
2244                             &port_regs->CommonRegs.reqQProducerIndex,
2245                             qdev->req_producer_index);
2246
2247         ndev->trans_start = jiffies;
2248         if (netif_msg_tx_queued(qdev))
2249                 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2250                        ndev->name, qdev->req_producer_index, skb->len);
2251
2252         atomic_dec(&qdev->tx_count);
2253         return NETDEV_TX_OK;
2254 }
2255
2256 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2257 {
2258         qdev->req_q_size =
2259             (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2260
2261         qdev->req_q_virt_addr =
2262             pci_alloc_consistent(qdev->pdev,
2263                                  (size_t) qdev->req_q_size,
2264                                  &qdev->req_q_phy_addr);
2265
2266         if ((qdev->req_q_virt_addr == NULL) ||
2267             LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2268                 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2269                        qdev->ndev->name);
2270                 return -ENOMEM;
2271         }
2272
2273         qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2274
2275         qdev->rsp_q_virt_addr =
2276             pci_alloc_consistent(qdev->pdev,
2277                                  (size_t) qdev->rsp_q_size,
2278                                  &qdev->rsp_q_phy_addr);
2279
2280         if ((qdev->rsp_q_virt_addr == NULL) ||
2281             LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2282                 printk(KERN_ERR PFX
2283                        "%s: rspQ allocation failed\n",
2284                        qdev->ndev->name);
2285                 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2286                                     qdev->req_q_virt_addr,
2287                                     qdev->req_q_phy_addr);
2288                 return -ENOMEM;
2289         }
2290
2291         set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2292
2293         return 0;
2294 }
2295
2296 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2297 {
2298         if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2299                 printk(KERN_INFO PFX
2300                        "%s: Already done.\n", qdev->ndev->name);
2301                 return;
2302         }
2303
2304         pci_free_consistent(qdev->pdev,
2305                             qdev->req_q_size,
2306                             qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2307
2308         qdev->req_q_virt_addr = NULL;
2309
2310         pci_free_consistent(qdev->pdev,
2311                             qdev->rsp_q_size,
2312                             qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2313
2314         qdev->rsp_q_virt_addr = NULL;
2315
2316         clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2317 }
2318
2319 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2320 {
2321         /* Create Large Buffer Queue */
2322         qdev->lrg_buf_q_size =
2323             qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2324         if (qdev->lrg_buf_q_size < PAGE_SIZE)
2325                 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2326         else
2327                 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2328
2329         qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2330         if (qdev->lrg_buf == NULL) {
2331                 printk(KERN_ERR PFX
2332                        "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2333                 return -ENOMEM;
2334         }
2335
2336         qdev->lrg_buf_q_alloc_virt_addr =
2337             pci_alloc_consistent(qdev->pdev,
2338                                  qdev->lrg_buf_q_alloc_size,
2339                                  &qdev->lrg_buf_q_alloc_phy_addr);
2340
2341         if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2342                 printk(KERN_ERR PFX
2343                        "%s: lBufQ failed\n", qdev->ndev->name);
2344                 return -ENOMEM;
2345         }
2346         qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2347         qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2348
2349         /* Create Small Buffer Queue */
2350         qdev->small_buf_q_size =
2351             NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2352         if (qdev->small_buf_q_size < PAGE_SIZE)
2353                 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2354         else
2355                 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2356
2357         qdev->small_buf_q_alloc_virt_addr =
2358             pci_alloc_consistent(qdev->pdev,
2359                                  qdev->small_buf_q_alloc_size,
2360                                  &qdev->small_buf_q_alloc_phy_addr);
2361
2362         if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2363                 printk(KERN_ERR PFX
2364                        "%s: Small Buffer Queue allocation failed.\n",
2365                        qdev->ndev->name);
2366                 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2367                                     qdev->lrg_buf_q_alloc_virt_addr,
2368                                     qdev->lrg_buf_q_alloc_phy_addr);
2369                 return -ENOMEM;
2370         }
2371
2372         qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2373         qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2374         set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2375         return 0;
2376 }
2377
2378 static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2379 {
2380         if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2381                 printk(KERN_INFO PFX
2382                        "%s: Already done.\n", qdev->ndev->name);
2383                 return;
2384         }
2385         if(qdev->lrg_buf) kfree(qdev->lrg_buf);
2386         pci_free_consistent(qdev->pdev,
2387                             qdev->lrg_buf_q_alloc_size,
2388                             qdev->lrg_buf_q_alloc_virt_addr,
2389                             qdev->lrg_buf_q_alloc_phy_addr);
2390
2391         qdev->lrg_buf_q_virt_addr = NULL;
2392
2393         pci_free_consistent(qdev->pdev,
2394                             qdev->small_buf_q_alloc_size,
2395                             qdev->small_buf_q_alloc_virt_addr,
2396                             qdev->small_buf_q_alloc_phy_addr);
2397
2398         qdev->small_buf_q_virt_addr = NULL;
2399
2400         clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2401 }
2402
2403 static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2404 {
2405         int i;
2406         struct bufq_addr_element *small_buf_q_entry;
2407
2408         /* Currently we allocate on one of memory and use it for smallbuffers */
2409         qdev->small_buf_total_size =
2410             (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2411              QL_SMALL_BUFFER_SIZE);
2412
2413         qdev->small_buf_virt_addr =
2414             pci_alloc_consistent(qdev->pdev,
2415                                  qdev->small_buf_total_size,
2416                                  &qdev->small_buf_phy_addr);
2417
2418         if (qdev->small_buf_virt_addr == NULL) {
2419                 printk(KERN_ERR PFX
2420                        "%s: Failed to get small buffer memory.\n",
2421                        qdev->ndev->name);
2422                 return -ENOMEM;
2423         }
2424
2425         qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2426         qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2427
2428         small_buf_q_entry = qdev->small_buf_q_virt_addr;
2429
2430         /* Initialize the small buffer queue. */
2431         for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2432                 small_buf_q_entry->addr_high =
2433                     cpu_to_le32(qdev->small_buf_phy_addr_high);
2434                 small_buf_q_entry->addr_low =
2435                     cpu_to_le32(qdev->small_buf_phy_addr_low +
2436                                 (i * QL_SMALL_BUFFER_SIZE));
2437                 small_buf_q_entry++;
2438         }
2439         qdev->small_buf_index = 0;
2440         set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2441         return 0;
2442 }
2443
2444 static void ql_free_small_buffers(struct ql3_adapter *qdev)
2445 {
2446         if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2447                 printk(KERN_INFO PFX
2448                        "%s: Already done.\n", qdev->ndev->name);
2449                 return;
2450         }
2451         if (qdev->small_buf_virt_addr != NULL) {
2452                 pci_free_consistent(qdev->pdev,
2453                                     qdev->small_buf_total_size,
2454                                     qdev->small_buf_virt_addr,
2455                                     qdev->small_buf_phy_addr);
2456
2457                 qdev->small_buf_virt_addr = NULL;
2458         }
2459 }
2460
2461 static void ql_free_large_buffers(struct ql3_adapter *qdev)
2462 {
2463         int i = 0;
2464         struct ql_rcv_buf_cb *lrg_buf_cb;
2465
2466         for (i = 0; i < qdev->num_large_buffers; i++) {
2467                 lrg_buf_cb = &qdev->lrg_buf[i];
2468                 if (lrg_buf_cb->skb) {
2469                         dev_kfree_skb(lrg_buf_cb->skb);
2470                         pci_unmap_single(qdev->pdev,
2471                                          pci_unmap_addr(lrg_buf_cb, mapaddr),
2472                                          pci_unmap_len(lrg_buf_cb, maplen),
2473                                          PCI_DMA_FROMDEVICE);
2474                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2475                 } else {
2476                         break;
2477                 }
2478         }
2479 }
2480
2481 static void ql_init_large_buffers(struct ql3_adapter *qdev)
2482 {
2483         int i;
2484         struct ql_rcv_buf_cb *lrg_buf_cb;
2485         struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2486
2487         for (i = 0; i < qdev->num_large_buffers; i++) {
2488                 lrg_buf_cb = &qdev->lrg_buf[i];
2489                 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2490                 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2491                 buf_addr_ele++;
2492         }
2493         qdev->lrg_buf_index = 0;
2494         qdev->lrg_buf_skb_check = 0;
2495 }
2496
2497 static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2498 {
2499         int i;
2500         struct ql_rcv_buf_cb *lrg_buf_cb;
2501         struct sk_buff *skb;
2502         u64 map;
2503
2504         for (i = 0; i < qdev->num_large_buffers; i++) {
2505                 skb = netdev_alloc_skb(qdev->ndev,
2506                                        qdev->lrg_buffer_len);
2507                 if (unlikely(!skb)) {
2508                         /* Better luck next round */
2509                         printk(KERN_ERR PFX
2510                                "%s: large buff alloc failed, "
2511                                "for %d bytes at index %d.\n",
2512                                qdev->ndev->name,
2513                                qdev->lrg_buffer_len * 2, i);
2514                         ql_free_large_buffers(qdev);
2515                         return -ENOMEM;
2516                 } else {
2517
2518                         lrg_buf_cb = &qdev->lrg_buf[i];
2519                         memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2520                         lrg_buf_cb->index = i;
2521                         lrg_buf_cb->skb = skb;
2522                         /*
2523                          * We save some space to copy the ethhdr from first
2524                          * buffer
2525                          */
2526                         skb_reserve(skb, QL_HEADER_SPACE);
2527                         map = pci_map_single(qdev->pdev,
2528                                              skb->data,
2529                                              qdev->lrg_buffer_len -
2530                                              QL_HEADER_SPACE,
2531                                              PCI_DMA_FROMDEVICE);
2532                         pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2533                         pci_unmap_len_set(lrg_buf_cb, maplen,
2534                                           qdev->lrg_buffer_len -
2535                                           QL_HEADER_SPACE);
2536                         lrg_buf_cb->buf_phy_addr_low =
2537                             cpu_to_le32(LS_64BITS(map));
2538                         lrg_buf_cb->buf_phy_addr_high =
2539                             cpu_to_le32(MS_64BITS(map));
2540                 }
2541         }
2542         return 0;
2543 }
2544
2545 static void ql_free_send_free_list(struct ql3_adapter *qdev)
2546 {
2547         struct ql_tx_buf_cb *tx_cb;
2548         int i;
2549
2550         tx_cb = &qdev->tx_buf[0];
2551         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2552                 if (tx_cb->oal) {
2553                         kfree(tx_cb->oal);
2554                         tx_cb->oal = NULL;
2555                 }
2556                 tx_cb++;
2557         }
2558 }
2559
2560 static int ql_create_send_free_list(struct ql3_adapter *qdev)
2561 {
2562         struct ql_tx_buf_cb *tx_cb;
2563         int i;
2564         struct ob_mac_iocb_req *req_q_curr =
2565                                         qdev->req_q_virt_addr;
2566
2567         /* Create free list of transmit buffers */
2568         for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2569
2570                 tx_cb = &qdev->tx_buf[i];
2571                 tx_cb->skb = NULL;
2572                 tx_cb->queue_entry = req_q_curr;
2573                 req_q_curr++;
2574                 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2575                 if (tx_cb->oal == NULL)
2576                         return -1;
2577         }
2578         return 0;
2579 }
2580
2581 static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2582 {
2583         if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2584                 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2585                 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2586         }
2587         else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2588                 /*
2589                  * Bigger buffers, so less of them.
2590                  */
2591                 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2592                 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2593         } else {
2594                 printk(KERN_ERR PFX
2595                        "%s: Invalid mtu size.  Only 1500 and 9000 are accepted.\n",
2596                        qdev->ndev->name);
2597                 return -ENOMEM;
2598         }
2599         qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2600         qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2601         qdev->max_frame_size =
2602             (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2603
2604         /*
2605          * First allocate a page of shared memory and use it for shadow
2606          * locations of Network Request Queue Consumer Address Register and
2607          * Network Completion Queue Producer Index Register
2608          */
2609         qdev->shadow_reg_virt_addr =
2610             pci_alloc_consistent(qdev->pdev,
2611                                  PAGE_SIZE, &qdev->shadow_reg_phy_addr);
2612
2613         if (qdev->shadow_reg_virt_addr != NULL) {
2614                 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
2615                 qdev->req_consumer_index_phy_addr_high =
2616                     MS_64BITS(qdev->shadow_reg_phy_addr);
2617                 qdev->req_consumer_index_phy_addr_low =
2618                     LS_64BITS(qdev->shadow_reg_phy_addr);
2619
2620                 qdev->prsp_producer_index =
2621                     (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2622                 qdev->rsp_producer_index_phy_addr_high =
2623                     qdev->req_consumer_index_phy_addr_high;
2624                 qdev->rsp_producer_index_phy_addr_low =
2625                     qdev->req_consumer_index_phy_addr_low + 8;
2626         } else {
2627                 printk(KERN_ERR PFX
2628                        "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
2629                 return -ENOMEM;
2630         }
2631
2632         if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2633                 printk(KERN_ERR PFX
2634                        "%s: ql_alloc_net_req_rsp_queues failed.\n",
2635                        qdev->ndev->name);
2636                 goto err_req_rsp;
2637         }
2638
2639         if (ql_alloc_buffer_queues(qdev) != 0) {
2640                 printk(KERN_ERR PFX
2641                        "%s: ql_alloc_buffer_queues failed.\n",
2642                        qdev->ndev->name);
2643                 goto err_buffer_queues;
2644         }
2645
2646         if (ql_alloc_small_buffers(qdev) != 0) {
2647                 printk(KERN_ERR PFX
2648                        "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
2649                 goto err_small_buffers;
2650         }
2651
2652         if (ql_alloc_large_buffers(qdev) != 0) {
2653                 printk(KERN_ERR PFX
2654                        "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
2655                 goto err_small_buffers;
2656         }
2657
2658         /* Initialize the large buffer queue. */
2659         ql_init_large_buffers(qdev);
2660         if (ql_create_send_free_list(qdev))
2661                 goto err_free_list;
2662
2663         qdev->rsp_current = qdev->rsp_q_virt_addr;
2664
2665         return 0;
2666 err_free_list:
2667         ql_free_send_free_list(qdev);
2668 err_small_buffers:
2669         ql_free_buffer_queues(qdev);
2670 err_buffer_queues:
2671         ql_free_net_req_rsp_queues(qdev);
2672 err_req_rsp:
2673         pci_free_consistent(qdev->pdev,
2674                             PAGE_SIZE,
2675                             qdev->shadow_reg_virt_addr,
2676                             qdev->shadow_reg_phy_addr);
2677
2678         return -ENOMEM;
2679 }
2680
2681 static void ql_free_mem_resources(struct ql3_adapter *qdev)
2682 {
2683         ql_free_send_free_list(qdev);
2684         ql_free_large_buffers(qdev);
2685         ql_free_small_buffers(qdev);
2686         ql_free_buffer_queues(qdev);
2687         ql_free_net_req_rsp_queues(qdev);
2688         if (qdev->shadow_reg_virt_addr != NULL) {
2689                 pci_free_consistent(qdev->pdev,
2690                                     PAGE_SIZE,
2691                                     qdev->shadow_reg_virt_addr,
2692                                     qdev->shadow_reg_phy_addr);
2693                 qdev->shadow_reg_virt_addr = NULL;
2694         }
2695 }
2696
2697 static int ql_init_misc_registers(struct ql3_adapter *qdev)
2698 {
2699         struct ql3xxx_local_ram_registers __iomem *local_ram =
2700             (void __iomem *)qdev->mem_map_registers;
2701
2702         if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2703                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2704                          2) << 4))
2705                 return -1;
2706
2707         ql_write_page2_reg(qdev,
2708                            &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2709
2710         ql_write_page2_reg(qdev,
2711                            &local_ram->maxBufletCount,
2712                            qdev->nvram_data.bufletCount);
2713
2714         ql_write_page2_reg(qdev,
2715                            &local_ram->freeBufletThresholdLow,
2716                            (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2717                            (qdev->nvram_data.tcpWindowThreshold0));
2718
2719         ql_write_page2_reg(qdev,
2720                            &local_ram->freeBufletThresholdHigh,
2721                            qdev->nvram_data.tcpWindowThreshold50);
2722
2723         ql_write_page2_reg(qdev,
2724                            &local_ram->ipHashTableBase,
2725                            (qdev->nvram_data.ipHashTableBaseHi << 16) |
2726                            qdev->nvram_data.ipHashTableBaseLo);
2727         ql_write_page2_reg(qdev,
2728                            &local_ram->ipHashTableCount,
2729                            qdev->nvram_data.ipHashTableSize);
2730         ql_write_page2_reg(qdev,
2731                            &local_ram->tcpHashTableBase,
2732                            (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2733                            qdev->nvram_data.tcpHashTableBaseLo);
2734         ql_write_page2_reg(qdev,
2735                            &local_ram->tcpHashTableCount,
2736                            qdev->nvram_data.tcpHashTableSize);
2737         ql_write_page2_reg(qdev,
2738                            &local_ram->ncbBase,
2739                            (qdev->nvram_data.ncbTableBaseHi << 16) |
2740                            qdev->nvram_data.ncbTableBaseLo);
2741         ql_write_page2_reg(qdev,
2742                            &local_ram->maxNcbCount,
2743                            qdev->nvram_data.ncbTableSize);
2744         ql_write_page2_reg(qdev,
2745                            &local_ram->drbBase,
2746                            (qdev->nvram_data.drbTableBaseHi << 16) |
2747                            qdev->nvram_data.drbTableBaseLo);
2748         ql_write_page2_reg(qdev,
2749                            &local_ram->maxDrbCount,
2750                            qdev->nvram_data.drbTableSize);
2751         ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
2752         return 0;
2753 }
2754
2755 static int ql_adapter_initialize(struct ql3_adapter *qdev)
2756 {
2757         u32 value;
2758         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2759         struct ql3xxx_host_memory_registers __iomem *hmem_regs =
2760                                                 (void __iomem *)port_regs;
2761         u32 delay = 10;
2762         int status = 0;
2763
2764         if(ql_mii_setup(qdev))
2765                 return -1;
2766
2767         /* Bring out PHY out of reset */
2768         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2769                             (ISP_SERIAL_PORT_IF_WE |
2770                              (ISP_SERIAL_PORT_IF_WE << 16)));
2771
2772         qdev->port_link_state = LS_DOWN;
2773         netif_carrier_off(qdev->ndev);
2774
2775         /* V2 chip fix for ARS-39168. */
2776         ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2777                             (ISP_SERIAL_PORT_IF_SDE |
2778                              (ISP_SERIAL_PORT_IF_SDE << 16)));
2779
2780         /* Request Queue Registers */
2781         *((u32 *) (qdev->preq_consumer_index)) = 0;
2782         atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
2783         qdev->req_producer_index = 0;
2784
2785         ql_write_page1_reg(qdev,
2786                            &hmem_regs->reqConsumerIndexAddrHigh,
2787                            qdev->req_consumer_index_phy_addr_high);
2788         ql_write_page1_reg(qdev,
2789                            &hmem_regs->reqConsumerIndexAddrLow,
2790                            qdev->req_consumer_index_phy_addr_low);
2791
2792         ql_write_page1_reg(qdev,
2793                            &hmem_regs->reqBaseAddrHigh,
2794                            MS_64BITS(qdev->req_q_phy_addr));
2795         ql_write_page1_reg(qdev,
2796                            &hmem_regs->reqBaseAddrLow,
2797                            LS_64BITS(qdev->req_q_phy_addr));
2798         ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
2799
2800         /* Response Queue Registers */
2801         *((u16 *) (qdev->prsp_producer_index)) = 0;
2802         qdev->rsp_consumer_index = 0;
2803         qdev->rsp_current = qdev->rsp_q_virt_addr;
2804
2805         ql_write_page1_reg(qdev,
2806                            &hmem_regs->rspProducerIndexAddrHigh,
2807                            qdev->rsp_producer_index_phy_addr_high);
2808
2809         ql_write_page1_reg(qdev,
2810                            &hmem_regs->rspProducerIndexAddrLow,
2811                            qdev->rsp_producer_index_phy_addr_low);
2812
2813         ql_write_page1_reg(qdev,
2814                            &hmem_regs->rspBaseAddrHigh,
2815                            MS_64BITS(qdev->rsp_q_phy_addr));
2816
2817         ql_write_page1_reg(qdev,
2818                            &hmem_regs->rspBaseAddrLow,
2819                            LS_64BITS(qdev->rsp_q_phy_addr));
2820
2821         ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
2822
2823         /* Large Buffer Queue */
2824         ql_write_page1_reg(qdev,
2825                            &hmem_regs->rxLargeQBaseAddrHigh,
2826                            MS_64BITS(qdev->lrg_buf_q_phy_addr));
2827
2828         ql_write_page1_reg(qdev,
2829                            &hmem_regs->rxLargeQBaseAddrLow,
2830                            LS_64BITS(qdev->lrg_buf_q_phy_addr));
2831
2832         ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
2833
2834         ql_write_page1_reg(qdev,
2835                            &hmem_regs->rxLargeBufferLength,
2836                            qdev->lrg_buffer_len);
2837
2838         /* Small Buffer Queue */
2839         ql_write_page1_reg(qdev,
2840                            &hmem_regs->rxSmallQBaseAddrHigh,
2841                            MS_64BITS(qdev->small_buf_q_phy_addr));
2842
2843         ql_write_page1_reg(qdev,
2844                            &hmem_regs->rxSmallQBaseAddrLow,
2845                            LS_64BITS(qdev->small_buf_q_phy_addr));
2846
2847         ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
2848         ql_write_page1_reg(qdev,
2849                            &hmem_regs->rxSmallBufferLength,
2850                            QL_SMALL_BUFFER_SIZE);
2851
2852         qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
2853         qdev->small_buf_release_cnt = 8;
2854         qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
2855         qdev->lrg_buf_release_cnt = 8;
2856         qdev->lrg_buf_next_free =
2857             (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
2858         qdev->small_buf_index = 0;
2859         qdev->lrg_buf_index = 0;
2860         qdev->lrg_buf_free_count = 0;
2861         qdev->lrg_buf_free_head = NULL;
2862         qdev->lrg_buf_free_tail = NULL;
2863
2864         ql_write_common_reg(qdev,
2865                             &port_regs->CommonRegs.
2866                             rxSmallQProducerIndex,
2867                             qdev->small_buf_q_producer_index);
2868         ql_write_common_reg(qdev,
2869                             &port_regs->CommonRegs.
2870                             rxLargeQProducerIndex,
2871                             qdev->lrg_buf_q_producer_index);
2872
2873         /*
2874          * Find out if the chip has already been initialized.  If it has, then
2875          * we skip some of the initialization.
2876          */
2877         clear_bit(QL_LINK_MASTER, &qdev->flags);
2878         value = ql_read_page0_reg(qdev, &port_regs->portStatus);
2879         if ((value & PORT_STATUS_IC) == 0) {
2880
2881                 /* Chip has not been configured yet, so let it rip. */
2882                 if(ql_init_misc_registers(qdev)) {
2883                         status = -1;
2884                         goto out;
2885                 }
2886
2887                 if (qdev->mac_index)
2888                         ql_write_page0_reg(qdev,
2889                                            &port_regs->mac1MaxFrameLengthReg,
2890                                            qdev->max_frame_size);
2891                 else
2892                         ql_write_page0_reg(qdev,
2893                                            &port_regs->mac0MaxFrameLengthReg,
2894                                            qdev->max_frame_size);
2895
2896                 value = qdev->nvram_data.tcpMaxWindowSize;
2897                 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
2898
2899                 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
2900
2901                 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
2902                                 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
2903                                  * 2) << 13)) {
2904                         status = -1;
2905                         goto out;
2906                 }
2907                 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
2908                 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
2909                                    (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
2910                                      16) | (INTERNAL_CHIP_SD |
2911                                             INTERNAL_CHIP_WE)));
2912                 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
2913         }
2914
2915
2916         if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
2917                         (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2918                          2) << 7)) {
2919                 status = -1;
2920                 goto out;
2921         }
2922
2923         ql_init_scan_mode(qdev);
2924         ql_get_phy_owner(qdev);
2925
2926         /* Load the MAC Configuration */
2927
2928         /* Program lower 32 bits of the MAC address */
2929         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
2930                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
2931         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
2932                            ((qdev->ndev->dev_addr[2] << 24)
2933                             | (qdev->ndev->dev_addr[3] << 16)
2934                             | (qdev->ndev->dev_addr[4] << 8)
2935                             | qdev->ndev->dev_addr[5]));
2936
2937         /* Program top 16 bits of the MAC address */
2938         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
2939                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
2940         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
2941                            ((qdev->ndev->dev_addr[0] << 8)
2942                             | qdev->ndev->dev_addr[1]));
2943
2944         /* Enable Primary MAC */
2945         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
2946                            ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
2947                             MAC_ADDR_INDIRECT_PTR_REG_PE));
2948
2949         /* Clear Primary and Secondary IP addresses */
2950         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
2951                            ((IP_ADDR_INDEX_REG_MASK << 16) |
2952                             (qdev->mac_index << 2)));
2953         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
2954
2955         ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
2956                            ((IP_ADDR_INDEX_REG_MASK << 16) |
2957                             ((qdev->mac_index << 2) + 1)));
2958         ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
2959
2960         ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
2961
2962         /* Indicate Configuration Complete */
2963         ql_write_page0_reg(qdev,
2964                            &port_regs->portControl,
2965                            ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
2966
2967         do {
2968                 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
2969                 if (value & PORT_STATUS_IC)
2970                         break;
2971                 msleep(500);
2972         } while (--delay);
2973
2974         if (delay == 0) {
2975                 printk(KERN_ERR PFX
2976                        "%s: Hw Initialization timeout.\n", qdev->ndev->name);
2977                 status = -1;
2978                 goto out;
2979         }
2980
2981         /* Enable Ethernet Function */
2982         if (qdev->device_id == QL3032_DEVICE_ID) {
2983                 value =
2984                     (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
2985                      QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4);
2986                 ql_write_page0_reg(qdev, &port_regs->functionControl,
2987                                    ((value << 16) | value));
2988         } else {
2989                 value =
2990                     (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
2991                      PORT_CONTROL_HH);
2992                 ql_write_page0_reg(qdev, &port_regs->portControl,
2993                                    ((value << 16) | value));
2994         }
2995
2996
2997 out:
2998         return status;
2999 }
3000
3001 /*
3002  * Caller holds hw_lock.
3003  */
3004 static int ql_adapter_reset(struct ql3_adapter *qdev)
3005 {
3006         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3007         int status = 0;
3008         u16 value;
3009         int max_wait_time;
3010
3011         set_bit(QL_RESET_ACTIVE, &qdev->flags);
3012         clear_bit(QL_RESET_DONE, &qdev->flags);
3013
3014         /*
3015          * Issue soft reset to chip.
3016          */
3017         printk(KERN_DEBUG PFX
3018                "%s: Issue soft reset to chip.\n",
3019                qdev->ndev->name);
3020         ql_write_common_reg(qdev,
3021                             &port_regs->CommonRegs.ispControlStatus,
3022                             ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3023
3024         /* Wait 3 seconds for reset to complete. */
3025         printk(KERN_DEBUG PFX
3026                "%s: Wait 10 milliseconds for reset to complete.\n",
3027                qdev->ndev->name);
3028
3029         /* Wait until the firmware tells us the Soft Reset is done */
3030         max_wait_time = 5;
3031         do {
3032                 value =
3033                     ql_read_common_reg(qdev,
3034                                        &port_regs->CommonRegs.ispControlStatus);
3035                 if ((value & ISP_CONTROL_SR) == 0)
3036                         break;
3037
3038                 ssleep(1);
3039         } while ((--max_wait_time));
3040
3041         /*
3042          * Also, make sure that the Network Reset Interrupt bit has been
3043          * cleared after the soft reset has taken place.
3044          */
3045         value =
3046             ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3047         if (value & ISP_CONTROL_RI) {
3048                 printk(KERN_DEBUG PFX
3049                        "ql_adapter_reset: clearing RI after reset.\n");
3050                 ql_write_common_reg(qdev,
3051                                     &port_regs->CommonRegs.
3052                                     ispControlStatus,
3053                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3054         }
3055
3056         if (max_wait_time == 0) {
3057                 /* Issue Force Soft Reset */
3058                 ql_write_common_reg(qdev,
3059                                     &port_regs->CommonRegs.
3060                                     ispControlStatus,
3061                                     ((ISP_CONTROL_FSR << 16) |
3062                                      ISP_CONTROL_FSR));
3063                 /*
3064                  * Wait until the firmware tells us the Force Soft Reset is
3065                  * done
3066                  */
3067                 max_wait_time = 5;
3068                 do {
3069                         value =
3070                             ql_read_common_reg(qdev,
3071                                                &port_regs->CommonRegs.
3072                                                ispControlStatus);
3073                         if ((value & ISP_CONTROL_FSR) == 0) {
3074                                 break;
3075                         }
3076                         ssleep(1);
3077                 } while ((--max_wait_time));
3078         }
3079         if (max_wait_time == 0)
3080                 status = 1;
3081
3082         clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3083         set_bit(QL_RESET_DONE, &qdev->flags);
3084         return status;
3085 }
3086
3087 static void ql_set_mac_info(struct ql3_adapter *qdev)
3088 {
3089         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3090         u32 value, port_status;
3091         u8 func_number;
3092
3093         /* Get the function number */
3094         value =
3095             ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3096         func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3097         port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3098         switch (value & ISP_CONTROL_FN_MASK) {
3099         case ISP_CONTROL_FN0_NET:
3100                 qdev->mac_index = 0;
3101                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3102                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3103                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3104                 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3105                 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3106                 if (port_status & PORT_STATUS_SM0)
3107                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3108                 else
3109                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3110                 break;
3111
3112         case ISP_CONTROL_FN1_NET:
3113                 qdev->mac_index = 1;
3114                 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3115                 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3116                 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3117                 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3118                 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3119                 if (port_status & PORT_STATUS_SM1)
3120                         set_bit(QL_LINK_OPTICAL,&qdev->flags);
3121                 else
3122                         clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3123                 break;
3124
3125         case ISP_CONTROL_FN0_SCSI:
3126         case ISP_CONTROL_FN1_SCSI:
3127         default:
3128                 printk(KERN_DEBUG PFX
3129                        "%s: Invalid function number, ispControlStatus = 0x%x\n",
3130                        qdev->ndev->name,value);
3131                 break;
3132         }
3133         qdev->numPorts = qdev->nvram_data.numPorts;
3134 }
3135
3136 static void ql_display_dev_info(struct net_device *ndev)
3137 {
3138         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3139         struct pci_dev *pdev = qdev->pdev;
3140
3141         printk(KERN_INFO PFX
3142                "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3143                DRV_NAME, qdev->index, qdev->chip_rev_id,
3144                (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3145                qdev->pci_slot);
3146         printk(KERN_INFO PFX
3147                "%s Interface.\n",
3148                test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3149
3150         /*
3151          * Print PCI bus width/type.
3152          */
3153         printk(KERN_INFO PFX
3154                "Bus interface is %s %s.\n",
3155                ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3156                ((qdev->pci_x) ? "PCI-X" : "PCI"));
3157
3158         printk(KERN_INFO PFX
3159                "mem  IO base address adjusted = 0x%p\n",
3160                qdev->mem_map_registers);
3161         printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3162
3163         if (netif_msg_probe(qdev))
3164                 printk(KERN_INFO PFX
3165                        "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
3166                        ndev->name, ndev->dev_addr[0], ndev->dev_addr[1],
3167                        ndev->dev_addr[2], ndev->dev_addr[3], ndev->dev_addr[4],
3168                        ndev->dev_addr[5]);
3169 }
3170
3171 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3172 {
3173         struct net_device *ndev = qdev->ndev;
3174         int retval = 0;
3175
3176         netif_stop_queue(ndev);
3177         netif_carrier_off(ndev);
3178
3179         clear_bit(QL_ADAPTER_UP,&qdev->flags);
3180         clear_bit(QL_LINK_MASTER,&qdev->flags);
3181
3182         ql_disable_interrupts(qdev);
3183
3184         free_irq(qdev->pdev->irq, ndev);
3185
3186         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3187                 printk(KERN_INFO PFX
3188                        "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3189                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3190                 pci_disable_msi(qdev->pdev);
3191         }
3192
3193         del_timer_sync(&qdev->adapter_timer);
3194
3195         netif_poll_disable(ndev);
3196
3197         if (do_reset) {
3198                 int soft_reset;
3199                 unsigned long hw_flags;
3200
3201                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3202                 if (ql_wait_for_drvr_lock(qdev)) {
3203                         if ((soft_reset = ql_adapter_reset(qdev))) {
3204                                 printk(KERN_ERR PFX
3205                                        "%s: ql_adapter_reset(%d) FAILED!\n",
3206                                        ndev->name, qdev->index);
3207                         }
3208                         printk(KERN_ERR PFX
3209                                 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3210                 } else {
3211                         printk(KERN_ERR PFX
3212                                "%s: Could not acquire driver lock to do "
3213                                "reset!\n", ndev->name);
3214                         retval = -1;
3215                 }
3216                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3217         }
3218         ql_free_mem_resources(qdev);
3219         return retval;
3220 }
3221
3222 static int ql_adapter_up(struct ql3_adapter *qdev)
3223 {
3224         struct net_device *ndev = qdev->ndev;
3225         int err;
3226         unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
3227         unsigned long hw_flags;
3228
3229         if (ql_alloc_mem_resources(qdev)) {
3230                 printk(KERN_ERR PFX
3231                        "%s Unable to  allocate buffers.\n", ndev->name);
3232                 return -ENOMEM;
3233         }
3234
3235         if (qdev->msi) {
3236                 if (pci_enable_msi(qdev->pdev)) {
3237                         printk(KERN_ERR PFX
3238                                "%s: User requested MSI, but MSI failed to "
3239                                "initialize.  Continuing without MSI.\n",
3240                                qdev->ndev->name);
3241                         qdev->msi = 0;
3242                 } else {
3243                         printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3244                         set_bit(QL_MSI_ENABLED,&qdev->flags);
3245                         irq_flags &= ~IRQF_SHARED;
3246                 }
3247         }
3248
3249         if ((err = request_irq(qdev->pdev->irq,
3250                                ql3xxx_isr,
3251                                irq_flags, ndev->name, ndev))) {
3252                 printk(KERN_ERR PFX
3253                        "%s: Failed to reserve interrupt %d already in use.\n",
3254                        ndev->name, qdev->pdev->irq);
3255                 goto err_irq;
3256         }
3257
3258         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3259
3260         if ((err = ql_wait_for_drvr_lock(qdev))) {
3261                 if ((err = ql_adapter_initialize(qdev))) {
3262                         printk(KERN_ERR PFX
3263                                "%s: Unable to initialize adapter.\n",
3264                                ndev->name);
3265                         goto err_init;
3266                 }
3267                 printk(KERN_ERR PFX
3268                                 "%s: Releaseing driver lock.\n",ndev->name);
3269                 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3270         } else {
3271                 printk(KERN_ERR PFX
3272                        "%s: Could not aquire driver lock.\n",
3273                        ndev->name);
3274                 goto err_lock;
3275         }
3276
3277         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3278
3279         set_bit(QL_ADAPTER_UP,&qdev->flags);
3280
3281         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3282
3283         netif_poll_enable(ndev);
3284         ql_enable_interrupts(qdev);
3285         return 0;
3286
3287 err_init:
3288         ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3289 err_lock:
3290         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3291         free_irq(qdev->pdev->irq, ndev);
3292 err_irq:
3293         if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3294                 printk(KERN_INFO PFX
3295                        "%s: calling pci_disable_msi().\n",
3296                        qdev->ndev->name);
3297                 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3298                 pci_disable_msi(qdev->pdev);
3299         }
3300         return err;
3301 }
3302
3303 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3304 {
3305         if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3306                 printk(KERN_ERR PFX
3307                                 "%s: Driver up/down cycle failed, "
3308                                 "closing device\n",qdev->ndev->name);
3309                 dev_close(qdev->ndev);
3310                 return -1;
3311         }
3312         return 0;
3313 }
3314
3315 static int ql3xxx_close(struct net_device *ndev)
3316 {
3317         struct ql3_adapter *qdev = netdev_priv(ndev);
3318
3319         /*
3320          * Wait for device to recover from a reset.
3321          * (Rarely happens, but possible.)
3322          */
3323         while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3324                 msleep(50);
3325
3326         ql_adapter_down(qdev,QL_DO_RESET);
3327         return 0;
3328 }
3329
3330 static int ql3xxx_open(struct net_device *ndev)
3331 {
3332         struct ql3_adapter *qdev = netdev_priv(ndev);
3333         return (ql_adapter_up(qdev));
3334 }
3335
3336 static struct net_device_stats *ql3xxx_get_stats(struct net_device *dev)
3337 {
3338         struct ql3_adapter *qdev = (struct ql3_adapter *)dev->priv;
3339         return &qdev->stats;
3340 }
3341
3342 static void ql3xxx_set_multicast_list(struct net_device *ndev)
3343 {
3344         /*
3345          * We are manually parsing the list in the net_device structure.
3346          */
3347         return;
3348 }
3349
3350 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3351 {
3352         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3353         struct ql3xxx_port_registers __iomem *port_regs =
3354                         qdev->mem_map_registers;
3355         struct sockaddr *addr = p;
3356         unsigned long hw_flags;
3357
3358         if (netif_running(ndev))
3359                 return -EBUSY;
3360
3361         if (!is_valid_ether_addr(addr->sa_data))
3362                 return -EADDRNOTAVAIL;
3363
3364         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3365
3366         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3367         /* Program lower 32 bits of the MAC address */
3368         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3369                            (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3370         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3371                            ((ndev->dev_addr[2] << 24) | (ndev->
3372                                                          dev_addr[3] << 16) |
3373                             (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3374
3375         /* Program top 16 bits of the MAC address */
3376         ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3377                            ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3378         ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3379                            ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3380         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3381
3382         return 0;
3383 }
3384
3385 static void ql3xxx_tx_timeout(struct net_device *ndev)
3386 {
3387         struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3388
3389         printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3390         /*
3391          * Stop the queues, we've got a problem.
3392          */
3393         netif_stop_queue(ndev);
3394
3395         /*
3396          * Wake up the worker to process this event.
3397          */
3398         queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3399 }
3400
3401 static void ql_reset_work(struct work_struct *work)
3402 {
3403         struct ql3_adapter *qdev =
3404                 container_of(work, struct ql3_adapter, reset_work.work);
3405         struct net_device *ndev = qdev->ndev;
3406         u32 value;
3407         struct ql_tx_buf_cb *tx_cb;
3408         int max_wait_time, i;
3409         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3410         unsigned long hw_flags;
3411
3412         if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3413                 clear_bit(QL_LINK_MASTER,&qdev->flags);
3414
3415                 /*
3416                  * Loop through the active list and return the skb.
3417                  */
3418                 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3419                         int j;
3420                         tx_cb = &qdev->tx_buf[i];
3421                         if (tx_cb->skb) {
3422                                 printk(KERN_DEBUG PFX
3423                                        "%s: Freeing lost SKB.\n",
3424                                        qdev->ndev->name);
3425                                 pci_unmap_single(qdev->pdev,
3426                                          pci_unmap_addr(&tx_cb->map[0], mapaddr),
3427                                          pci_unmap_len(&tx_cb->map[0], maplen),
3428                                          PCI_DMA_TODEVICE);
3429                                 for(j=1;j<tx_cb->seg_count;j++) {
3430                                         pci_unmap_page(qdev->pdev,
3431                                                pci_unmap_addr(&tx_cb->map[j],mapaddr),
3432                                                pci_unmap_len(&tx_cb->map[j],maplen),
3433                                                PCI_DMA_TODEVICE);
3434                                 }
3435                                 dev_kfree_skb(tx_cb->skb);
3436                                 tx_cb->skb = NULL;
3437                         }
3438                 }
3439
3440                 printk(KERN_ERR PFX
3441                        "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3442                 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3443                 ql_write_common_reg(qdev,
3444                                     &port_regs->CommonRegs.
3445                                     ispControlStatus,
3446                                     ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3447                 /*
3448                  * Wait the for Soft Reset to Complete.
3449                  */
3450                 max_wait_time = 10;
3451                 do {
3452                         value = ql_read_common_reg(qdev,
3453                                                    &port_regs->CommonRegs.
3454
3455                                                    ispControlStatus);
3456                         if ((value & ISP_CONTROL_SR) == 0) {
3457                                 printk(KERN_DEBUG PFX
3458                                        "%s: reset completed.\n",
3459                                        qdev->ndev->name);
3460                                 break;
3461                         }
3462
3463                         if (value & ISP_CONTROL_RI) {
3464                                 printk(KERN_DEBUG PFX
3465                                        "%s: clearing NRI after reset.\n",
3466                                        qdev->ndev->name);
3467                                 ql_write_common_reg(qdev,
3468                                                     &port_regs->
3469                                                     CommonRegs.
3470                                                     ispControlStatus,
3471                                                     ((ISP_CONTROL_RI <<
3472                                                       16) | ISP_CONTROL_RI));
3473                         }
3474
3475                         ssleep(1);
3476                 } while (--max_wait_time);
3477                 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3478
3479                 if (value & ISP_CONTROL_SR) {
3480
3481                         /*
3482                          * Set the reset flags and clear the board again.
3483                          * Nothing else to do...
3484                          */
3485                         printk(KERN_ERR PFX
3486                                "%s: Timed out waiting for reset to "
3487                                "complete.\n", ndev->name);
3488                         printk(KERN_ERR PFX
3489                                "%s: Do a reset.\n", ndev->name);
3490                         clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3491                         clear_bit(QL_RESET_START,&qdev->flags);
3492                         ql_cycle_adapter(qdev,QL_DO_RESET);
3493                         return;
3494                 }
3495
3496                 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3497                 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3498                 clear_bit(QL_RESET_START,&qdev->flags);
3499                 ql_cycle_adapter(qdev,QL_NO_RESET);
3500         }
3501 }
3502
3503 static void ql_tx_timeout_work(struct work_struct *work)
3504 {
3505         struct ql3_adapter *qdev =
3506                 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3507
3508         ql_cycle_adapter(qdev, QL_DO_RESET);
3509 }
3510
3511 static void ql_get_board_info(struct ql3_adapter *qdev)
3512 {
3513         struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3514         u32 value;
3515
3516         value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3517
3518         qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3519         if (value & PORT_STATUS_64)
3520                 qdev->pci_width = 64;
3521         else
3522                 qdev->pci_width = 32;
3523         if (value & PORT_STATUS_X)
3524                 qdev->pci_x = 1;
3525         else
3526                 qdev->pci_x = 0;
3527         qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3528 }
3529
3530 static void ql3xxx_timer(unsigned long ptr)
3531 {
3532         struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3533
3534         if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
3535                 printk(KERN_DEBUG PFX
3536                        "%s: Reset in progress.\n",
3537                        qdev->ndev->name);
3538                 goto end;
3539         }
3540
3541         ql_link_state_machine(qdev);
3542
3543         /* Restart timer on 2 second interval. */
3544 end:
3545         mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3546 }
3547
3548 static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3549                                   const struct pci_device_id *pci_entry)
3550 {
3551         struct net_device *ndev = NULL;
3552         struct ql3_adapter *qdev = NULL;
3553         static int cards_found = 0;
3554         int pci_using_dac, err;
3555
3556         err = pci_enable_device(pdev);
3557         if (err) {
3558                 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3559                        pci_name(pdev));
3560                 goto err_out;
3561         }
3562
3563         err = pci_request_regions(pdev, DRV_NAME);
3564         if (err) {
3565                 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3566                        pci_name(pdev));
3567                 goto err_out_disable_pdev;
3568         }
3569
3570         pci_set_master(pdev);
3571
3572         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3573                 pci_using_dac = 1;
3574                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3575         } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3576                 pci_using_dac = 0;
3577                 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3578         }
3579
3580         if (err) {
3581                 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3582                        pci_name(pdev));
3583                 goto err_out_free_regions;
3584         }
3585
3586         ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3587         if (!ndev) {
3588                 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
3589                        pci_name(pdev));
3590                 err = -ENOMEM;
3591                 goto err_out_free_regions;
3592         }
3593
3594         SET_MODULE_OWNER(ndev);
3595         SET_NETDEV_DEV(ndev, &pdev->dev);
3596
3597         pci_set_drvdata(pdev, ndev);
3598
3599         qdev = netdev_priv(ndev);
3600         qdev->index = cards_found;
3601         qdev->ndev = ndev;
3602         qdev->pdev = pdev;
3603         qdev->device_id = pci_entry->device;
3604         qdev->port_link_state = LS_DOWN;
3605         if (msi)
3606                 qdev->msi = 1;
3607
3608         qdev->msg_enable = netif_msg_init(debug, default_msg);
3609
3610         if (pci_using_dac)
3611                 ndev->features |= NETIF_F_HIGHDMA;
3612         if (qdev->device_id == QL3032_DEVICE_ID)
3613                 ndev->features |= (NETIF_F_HW_CSUM | NETIF_F_SG);
3614
3615         qdev->mem_map_registers =
3616             ioremap_nocache(pci_resource_start(pdev, 1),
3617                             pci_resource_len(qdev->pdev, 1));
3618         if (!qdev->mem_map_registers) {
3619                 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3620                        pci_name(pdev));
3621                 err = -EIO;
3622                 goto err_out_free_ndev;
3623         }
3624
3625         spin_lock_init(&qdev->adapter_lock);
3626         spin_lock_init(&qdev->hw_lock);
3627
3628         /* Set driver entry points */
3629         ndev->open = ql3xxx_open;
3630         ndev->hard_start_xmit = ql3xxx_send;
3631         ndev->stop = ql3xxx_close;
3632         ndev->get_stats = ql3xxx_get_stats;
3633         ndev->set_multicast_list = ql3xxx_set_multicast_list;
3634         SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
3635         ndev->set_mac_address = ql3xxx_set_mac_address;
3636         ndev->tx_timeout = ql3xxx_tx_timeout;
3637         ndev->watchdog_timeo = 5 * HZ;
3638
3639         ndev->poll = &ql_poll;
3640         ndev->weight = 64;
3641
3642         ndev->irq = pdev->irq;
3643
3644         /* make sure the EEPROM is good */
3645         if (ql_get_nvram_params(qdev)) {
3646                 printk(KERN_ALERT PFX
3647                        "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
3648                        qdev->index);
3649                 err = -EIO;
3650                 goto err_out_iounmap;
3651         }
3652
3653         ql_set_mac_info(qdev);
3654
3655         /* Validate and set parameters */
3656         if (qdev->mac_index) {
3657                 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
3658                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
3659                        ETH_ALEN);
3660         } else {
3661                 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
3662                 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
3663                        ETH_ALEN);
3664         }
3665         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3666
3667         ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3668
3669         /* Turn off support for multicasting */
3670         ndev->flags &= ~IFF_MULTICAST;
3671
3672         /* Record PCI bus information. */
3673         ql_get_board_info(qdev);
3674
3675         /*
3676          * Set the Maximum Memory Read Byte Count value. We do this to handle
3677          * jumbo frames.
3678          */
3679         if (qdev->pci_x) {
3680                 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3681         }
3682
3683         err = register_netdev(ndev);
3684         if (err) {
3685                 printk(KERN_ERR PFX "%s: cannot register net device\n",
3686                        pci_name(pdev));
3687                 goto err_out_iounmap;
3688         }
3689
3690         /* we're going to reset, so assume we have no link for now */
3691
3692         netif_carrier_off(ndev);
3693         netif_stop_queue(ndev);
3694
3695         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3696         INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3697         INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3698
3699         init_timer(&qdev->adapter_timer);
3700         qdev->adapter_timer.function = ql3xxx_timer;
3701         qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3702         qdev->adapter_timer.data = (unsigned long)qdev;
3703
3704         if(!cards_found) {
3705                 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
3706                 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
3707                    DRV_NAME, DRV_VERSION);
3708         }
3709         ql_display_dev_info(ndev);
3710
3711         cards_found++;
3712         return 0;
3713
3714 err_out_iounmap:
3715         iounmap(qdev->mem_map_registers);
3716 err_out_free_ndev:
3717         free_netdev(ndev);
3718 err_out_free_regions:
3719         pci_release_regions(pdev);
3720 err_out_disable_pdev:
3721         pci_disable_device(pdev);
3722         pci_set_drvdata(pdev, NULL);
3723 err_out:
3724         return err;
3725 }
3726
3727 static void __devexit ql3xxx_remove(struct pci_dev *pdev)
3728 {
3729         struct net_device *ndev = pci_get_drvdata(pdev);
3730         struct ql3_adapter *qdev = netdev_priv(ndev);
3731
3732         unregister_netdev(ndev);
3733         qdev = netdev_priv(ndev);
3734
3735         ql_disable_interrupts(qdev);
3736
3737         if (qdev->workqueue) {
3738                 cancel_delayed_work(&qdev->reset_work);
3739                 cancel_delayed_work(&qdev->tx_timeout_work);
3740                 destroy_workqueue(qdev->workqueue);
3741                 qdev->workqueue = NULL;
3742         }
3743
3744         iounmap(qdev->mem_map_registers);
3745         pci_release_regions(pdev);
3746         pci_set_drvdata(pdev, NULL);
3747         free_netdev(ndev);
3748 }
3749
3750 static struct pci_driver ql3xxx_driver = {
3751
3752         .name = DRV_NAME,
3753         .id_table = ql3xxx_pci_tbl,
3754         .probe = ql3xxx_probe,
3755         .remove = __devexit_p(ql3xxx_remove),
3756 };
3757
3758 static int __init ql3xxx_init_module(void)
3759 {
3760         return pci_register_driver(&ql3xxx_driver);
3761 }
3762
3763 static void __exit ql3xxx_exit(void)
3764 {
3765         pci_unregister_driver(&ql3xxx_driver);
3766 }
3767
3768 module_init(ql3xxx_init_module);
3769 module_exit(ql3xxx_exit);