drivers/net/pcnet32.c

   1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
   2 /*
   3  *      Copyright 1996-1999 Thomas Bogendoerfer
   4  *
   5  *      Derived from the lance driver written 1993,1994,1995 by Donald Becker.
   6  *
   7  *      Copyright 1993 United States Government as represented by the
   8  *      Director, National Security Agency.
   9  *
  10  *      This software may be used and distributed according to the terms
  11  *      of the GNU General Public License, incorporated herein by reference.
  12  *
  13  *      This driver is for PCnet32 and PCnetPCI based ethercards
  14  */
  15 /**************************************************************************
  16  *  23 Oct, 2000.
  17  *  Fixed a few bugs, related to running the controller in 32bit mode.
  18  *
  19  *  Carsten Langgaard, carstenl@mips.com
  20  *  Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  21  *
  22  *************************************************************************/
  23
  24 #define DRV_NAME        "pcnet32"
  25 #ifdef CONFIG_PCNET32_NAPI
  26 #define DRV_VERSION     "1.34-NAPI"
  27 #else
  28 #define DRV_VERSION     "1.34"
  29 #endif
  30 #define DRV_RELDATE     "14.Aug.2007"
  31 #define PFX             DRV_NAME ": "
  32
  33 static const char *const version =
  34     DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
  35
  36 #include <linux/module.h>
  37 #include <linux/kernel.h>
  38 #include <linux/string.h>
  39 #include <linux/errno.h>
  40 #include <linux/ioport.h>
  41 #include <linux/slab.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/pci.h>
  44 #include <linux/delay.h>
  45 #include <linux/init.h>
  46 #include <linux/ethtool.h>
  47 #include <linux/mii.h>
  48 #include <linux/crc32.h>
  49 #include <linux/netdevice.h>
  50 #include <linux/etherdevice.h>
  51 #include <linux/skbuff.h>
  52 #include <linux/spinlock.h>
  53 #include <linux/moduleparam.h>
  54 #include <linux/bitops.h>
  55
  56 #include <asm/dma.h>
  57 #include <asm/io.h>
  58 #include <asm/uaccess.h>
  59 #include <asm/irq.h>
  60
  61 /*
  62  * PCI device identifiers for "new style" Linux PCI Device Drivers
  63  */
  64 static struct pci_device_id pcnet32_pci_tbl[] = {
  65         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
  66         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
  67
  68         /*
  69          * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
  70          * the incorrect vendor id.
  71          */
  72         { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
  73           .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
  74
  75         { }     /* terminate list */
  76 };
  77
  78 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
  79
  80 static int cards_found;
  81
  82 /*
  83  * VLB I/O addresses
  84  */
  85 static unsigned int pcnet32_portlist[] __initdata =
  86     { 0x300, 0x320, 0x340, 0x360, 0 };
  87
  88 static int pcnet32_debug = 0;
  89 static int tx_start = 1;        /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
  90 static int pcnet32vlb;          /* check for VLB cards ? */
  91
  92 static struct net_device *pcnet32_dev;
  93
  94 static int max_interrupt_work = 2;
  95 static int rx_copybreak = 200;
  96
  97 #define PCNET32_PORT_AUI      0x00
  98 #define PCNET32_PORT_10BT     0x01
  99 #define PCNET32_PORT_GPSI     0x02
 100 #define PCNET32_PORT_MII      0x03
 101
 102 #define PCNET32_PORT_PORTSEL  0x03
 103 #define PCNET32_PORT_ASEL     0x04
 104 #define PCNET32_PORT_100      0x40
 105 #define PCNET32_PORT_FD       0x80
 106
 107 #define PCNET32_DMA_MASK 0xffffffff
 108
 109 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
 110 #define PCNET32_BLINK_TIMEOUT   (jiffies + (HZ/4))
 111
 112 /*
 113  * table to translate option values from tulip
 114  * to internal options
 115  */
 116 static const unsigned char options_mapping[] = {
 117         PCNET32_PORT_ASEL,                      /*  0 Auto-select      */
 118         PCNET32_PORT_AUI,                       /*  1 BNC/AUI          */
 119         PCNET32_PORT_AUI,                       /*  2 AUI/BNC          */
 120         PCNET32_PORT_ASEL,                      /*  3 not supported    */
 121         PCNET32_PORT_10BT | PCNET32_PORT_FD,    /*  4 10baseT-FD       */
 122         PCNET32_PORT_ASEL,                      /*  5 not supported    */
 123         PCNET32_PORT_ASEL,                      /*  6 not supported    */
 124         PCNET32_PORT_ASEL,                      /*  7 not supported    */
 125         PCNET32_PORT_ASEL,                      /*  8 not supported    */
 126         PCNET32_PORT_MII,                       /*  9 MII 10baseT      */
 127         PCNET32_PORT_MII | PCNET32_PORT_FD,     /* 10 MII 10baseT-FD   */
 128         PCNET32_PORT_MII,                       /* 11 MII (autosel)    */
 129         PCNET32_PORT_10BT,                      /* 12 10BaseT          */
 130         PCNET32_PORT_MII | PCNET32_PORT_100,    /* 13 MII 100BaseTx    */
 131                                                 /* 14 MII 100BaseTx-FD */
 132         PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
 133         PCNET32_PORT_ASEL                       /* 15 not supported    */
 134 };
 135
 136 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
 137         "Loopback test  (offline)"
 138 };
 139
 140 #define PCNET32_TEST_LEN        ARRAY_SIZE(pcnet32_gstrings_test)
 141
 142 #define PCNET32_NUM_REGS 136
 143
 144 #define MAX_UNITS 8             /* More are supported, limit only on options */
 145 static int options[MAX_UNITS];
 146 static int full_duplex[MAX_UNITS];
 147 static int homepna[MAX_UNITS];
 148
 149 /*
 150  *                              Theory of Operation
 151  *
 152  * This driver uses the same software structure as the normal lance
 153  * driver. So look for a verbose description in lance.c. The differences
 154  * to the normal lance driver is the use of the 32bit mode of PCnet32
 155  * and PCnetPCI chips. Because these chips are 32bit chips, there is no
 156  * 16MB limitation and we don't need bounce buffers.
 157  */
 158
 159 /*
 160  * Set the number of Tx and Rx buffers, using Log_2(# buffers).
 161  * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
 162  * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
 163  */
 164 #ifndef PCNET32_LOG_TX_BUFFERS
 165 #define PCNET32_LOG_TX_BUFFERS          4
 166 #define PCNET32_LOG_RX_BUFFERS          5
 167 #define PCNET32_LOG_MAX_TX_BUFFERS      9       /* 2^9 == 512 */
 168 #define PCNET32_LOG_MAX_RX_BUFFERS      9
 169 #endif
 170
 171 #define TX_RING_SIZE            (1 << (PCNET32_LOG_TX_BUFFERS))
 172 #define TX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
 173
 174 #define RX_RING_SIZE            (1 << (PCNET32_LOG_RX_BUFFERS))
 175 #define RX_MAX_RING_SIZE        (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
 176
 177 #define PKT_BUF_SKB             1544
 178 /* actual buffer length after being aligned */
 179 #define PKT_BUF_SIZE            (PKT_BUF_SKB - NET_IP_ALIGN)
 180 /* chip wants twos complement of the (aligned) buffer length */
 181 #define NEG_BUF_SIZE            (NET_IP_ALIGN - PKT_BUF_SKB)
 182
 183 /* Offsets from base I/O address. */
 184 #define PCNET32_WIO_RDP         0x10
 185 #define PCNET32_WIO_RAP         0x12
 186 #define PCNET32_WIO_RESET       0x14
 187 #define PCNET32_WIO_BDP         0x16
 188
 189 #define PCNET32_DWIO_RDP        0x10
 190 #define PCNET32_DWIO_RAP        0x14
 191 #define PCNET32_DWIO_RESET      0x18
 192 #define PCNET32_DWIO_BDP        0x1C
 193
 194 #define PCNET32_TOTAL_SIZE      0x20
 195
 196 #define CSR0            0
 197 #define CSR0_INIT       0x1
 198 #define CSR0_START      0x2
 199 #define CSR0_STOP       0x4
 200 #define CSR0_TXPOLL     0x8
 201 #define CSR0_INTEN      0x40
 202 #define CSR0_IDON       0x0100
 203 #define CSR0_NORMAL     (CSR0_START | CSR0_INTEN)
 204 #define PCNET32_INIT_LOW        1
 205 #define PCNET32_INIT_HIGH       2
 206 #define CSR3            3
 207 #define CSR4            4
 208 #define CSR5            5
 209 #define CSR5_SUSPEND    0x0001
 210 #define CSR15           15
 211 #define PCNET32_MC_FILTER       8
 212
 213 #define PCNET32_79C970A 0x2621
 214
 215 /* The PCNET32 Rx and Tx ring descriptors. */
 216 struct pcnet32_rx_head {
 217         __le32  base;
 218         __le16  buf_length;     /* two`s complement of length */
 219         __le16  status;
 220         __le32  msg_length;
 221         __le32  reserved;
 222 };
 223
 224 struct pcnet32_tx_head {
 225         __le32  base;
 226         __le16  length;         /* two`s complement of length */
 227         __le16  status;
 228         __le32  misc;
 229         __le32  reserved;
 230 };
 231
 232 /* The PCNET32 32-Bit initialization block, described in databook. */
 233 struct pcnet32_init_block {
 234         __le16  mode;
 235         __le16  tlen_rlen;
 236         u8      phys_addr[6];
 237         __le16  reserved;
 238         __le32  filter[2];
 239         /* Receive and transmit ring base, along with extra bits. */
 240         __le32  rx_ring;
 241         __le32  tx_ring;
 242 };
 243
 244 /* PCnet32 access functions */
 245 struct pcnet32_access {
 246         u16     (*read_csr) (unsigned long, int);
 247         void    (*write_csr) (unsigned long, int, u16);
 248         u16     (*read_bcr) (unsigned long, int);
 249         void    (*write_bcr) (unsigned long, int, u16);
 250         u16     (*read_rap) (unsigned long);
 251         void    (*write_rap) (unsigned long, u16);
 252         void    (*reset) (unsigned long);
 253 };
 254
 255 /*
 256  * The first field of pcnet32_private is read by the ethernet device
 257  * so the structure should be allocated using pci_alloc_consistent().
 258  */
 259 struct pcnet32_private {
 260         struct pcnet32_init_block *init_block;
 261         /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
 262         struct pcnet32_rx_head  *rx_ring;
 263         struct pcnet32_tx_head  *tx_ring;
 264         dma_addr_t              init_dma_addr;/* DMA address of beginning of the init block,
 265                                    returned by pci_alloc_consistent */
 266         struct pci_dev          *pci_dev;
 267         const char              *name;
 268         /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 269         struct sk_buff          **tx_skbuff;
 270         struct sk_buff          **rx_skbuff;
 271         dma_addr_t              *tx_dma_addr;
 272         dma_addr_t              *rx_dma_addr;
 273         struct pcnet32_access   a;
 274         spinlock_t              lock;           /* Guard lock */
 275         unsigned int            cur_rx, cur_tx; /* The next free ring entry */
 276         unsigned int            rx_ring_size;   /* current rx ring size */
 277         unsigned int            tx_ring_size;   /* current tx ring size */
 278         unsigned int            rx_mod_mask;    /* rx ring modular mask */
 279         unsigned int            tx_mod_mask;    /* tx ring modular mask */
 280         unsigned short          rx_len_bits;
 281         unsigned short          tx_len_bits;
 282         dma_addr_t              rx_ring_dma_addr;
 283         dma_addr_t              tx_ring_dma_addr;
 284         unsigned int            dirty_rx,       /* ring entries to be freed. */
 285                                 dirty_tx;
 286
 287         struct net_device       *dev;
 288         struct napi_struct      napi;
 289         char                    tx_full;
 290         char                    phycount;       /* number of phys found */
 291         int                     options;
 292         unsigned int            shared_irq:1,   /* shared irq possible */
 293                                 dxsuflo:1,   /* disable transmit stop on uflo */
 294                                 mii:1;          /* mii port available */
 295         struct net_device       *next;
 296         struct mii_if_info      mii_if;
 297         struct timer_list       watchdog_timer;
 298         struct timer_list       blink_timer;
 299         u32                     msg_enable;     /* debug message level */
 300
 301         /* each bit indicates an available PHY */
 302         u32                     phymask;
 303         unsigned short          chip_version;   /* which variant this is */
 304 };
 305
 306 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
 307 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
 308 static int pcnet32_open(struct net_device *);
 309 static int pcnet32_init_ring(struct net_device *);
 310 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
 311 static void pcnet32_tx_timeout(struct net_device *dev);
 312 static irqreturn_t pcnet32_interrupt(int, void *);
 313 static int pcnet32_close(struct net_device *);
 314 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
 315 static void pcnet32_load_multicast(struct net_device *dev);
 316 static void pcnet32_set_multicast_list(struct net_device *);
 317 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
 318 static void pcnet32_watchdog(struct net_device *);
 319 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
 320 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
 321                        int val);
 322 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
 323 static void pcnet32_ethtool_test(struct net_device *dev,
 324                                  struct ethtool_test *eth_test, u64 * data);
 325 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
 326 static int pcnet32_phys_id(struct net_device *dev, u32 data);
 327 static void pcnet32_led_blink_callback(struct net_device *dev);
 328 static int pcnet32_get_regs_len(struct net_device *dev);
 329 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 330                              void *ptr);
 331 static void pcnet32_purge_tx_ring(struct net_device *dev);
 332 static int pcnet32_alloc_ring(struct net_device *dev, char *name);
 333 static void pcnet32_free_ring(struct net_device *dev);
 334 static void pcnet32_check_media(struct net_device *dev, int verbose);
 335
 336 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
 337 {
 338         outw(index, addr + PCNET32_WIO_RAP);
 339         return inw(addr + PCNET32_WIO_RDP);
 340 }
 341
 342 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
 343 {
 344         outw(index, addr + PCNET32_WIO_RAP);
 345         outw(val, addr + PCNET32_WIO_RDP);
 346 }
 347
 348 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
 349 {
 350         outw(index, addr + PCNET32_WIO_RAP);
 351         return inw(addr + PCNET32_WIO_BDP);
 352 }
 353
 354 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
 355 {
 356         outw(index, addr + PCNET32_WIO_RAP);
 357         outw(val, addr + PCNET32_WIO_BDP);
 358 }
 359
 360 static u16 pcnet32_wio_read_rap(unsigned long addr)
 361 {
 362         return inw(addr + PCNET32_WIO_RAP);
 363 }
 364
 365 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
 366 {
 367         outw(val, addr + PCNET32_WIO_RAP);
 368 }
 369
 370 static void pcnet32_wio_reset(unsigned long addr)
 371 {
 372         inw(addr + PCNET32_WIO_RESET);
 373 }
 374
 375 static int pcnet32_wio_check(unsigned long addr)
 376 {
 377         outw(88, addr + PCNET32_WIO_RAP);
 378         return (inw(addr + PCNET32_WIO_RAP) == 88);
 379 }
 380
 381 static struct pcnet32_access pcnet32_wio = {
 382         .read_csr = pcnet32_wio_read_csr,
 383         .write_csr = pcnet32_wio_write_csr,
 384         .read_bcr = pcnet32_wio_read_bcr,
 385         .write_bcr = pcnet32_wio_write_bcr,
 386         .read_rap = pcnet32_wio_read_rap,
 387         .write_rap = pcnet32_wio_write_rap,
 388         .reset = pcnet32_wio_reset
 389 };
 390
 391 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
 392 {
 393         outl(index, addr + PCNET32_DWIO_RAP);
 394         return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
 395 }
 396
 397 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
 398 {
 399         outl(index, addr + PCNET32_DWIO_RAP);
 400         outl(val, addr + PCNET32_DWIO_RDP);
 401 }
 402
 403 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
 404 {
 405         outl(index, addr + PCNET32_DWIO_RAP);
 406         return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
 407 }
 408
 409 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
 410 {
 411         outl(index, addr + PCNET32_DWIO_RAP);
 412         outl(val, addr + PCNET32_DWIO_BDP);
 413 }
 414
 415 static u16 pcnet32_dwio_read_rap(unsigned long addr)
 416 {
 417         return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
 418 }
 419
 420 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
 421 {
 422         outl(val, addr + PCNET32_DWIO_RAP);
 423 }
 424
 425 static void pcnet32_dwio_reset(unsigned long addr)
 426 {
 427         inl(addr + PCNET32_DWIO_RESET);
 428 }
 429
 430 static int pcnet32_dwio_check(unsigned long addr)
 431 {
 432         outl(88, addr + PCNET32_DWIO_RAP);
 433         return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
 434 }
 435
 436 static struct pcnet32_access pcnet32_dwio = {
 437         .read_csr = pcnet32_dwio_read_csr,
 438         .write_csr = pcnet32_dwio_write_csr,
 439         .read_bcr = pcnet32_dwio_read_bcr,
 440         .write_bcr = pcnet32_dwio_write_bcr,
 441         .read_rap = pcnet32_dwio_read_rap,
 442         .write_rap = pcnet32_dwio_write_rap,
 443         .reset = pcnet32_dwio_reset
 444 };
 445
 446 static void pcnet32_netif_stop(struct net_device *dev)
 447 {
 448 #ifdef CONFIG_PCNET32_NAPI
 449         struct pcnet32_private *lp = netdev_priv(dev);
 450 #endif
 451         dev->trans_start = jiffies;
 452 #ifdef CONFIG_PCNET32_NAPI
 453         napi_disable(&lp->napi);
 454 #endif
 455         netif_tx_disable(dev);
 456 }
 457
 458 static void pcnet32_netif_start(struct net_device *dev)
 459 {
 460 #ifdef CONFIG_PCNET32_NAPI
 461         struct pcnet32_private *lp = netdev_priv(dev);
 462         ulong ioaddr = dev->base_addr;
 463         u16 val;
 464 #endif
 465         netif_wake_queue(dev);
 466 #ifdef CONFIG_PCNET32_NAPI
 467         val = lp->a.read_csr(ioaddr, CSR3);
 468         val &= 0x00ff;
 469         lp->a.write_csr(ioaddr, CSR3, val);
 470         napi_enable(&lp->napi);
 471 #endif
 472 }
 473
 474 /*
 475  * Allocate space for the new sized tx ring.
 476  * Free old resources
 477  * Save new resources.
 478  * Any failure keeps old resources.
 479  * Must be called with lp->lock held.
 480  */
 481 static void pcnet32_realloc_tx_ring(struct net_device *dev,
 482                                     struct pcnet32_private *lp,
 483                                     unsigned int size)
 484 {
 485         dma_addr_t new_ring_dma_addr;
 486         dma_addr_t *new_dma_addr_list;
 487         struct pcnet32_tx_head *new_tx_ring;
 488         struct sk_buff **new_skb_list;
 489
 490         pcnet32_purge_tx_ring(dev);
 491
 492         new_tx_ring = pci_alloc_consistent(lp->pci_dev,
 493                                            sizeof(struct pcnet32_tx_head) *
 494                                            (1 << size),
 495                                            &new_ring_dma_addr);
 496         if (new_tx_ring == NULL) {
 497                 if (netif_msg_drv(lp))
 498                         printk("\n" KERN_ERR
 499                                "%s: Consistent memory allocation failed.\n",
 500                                dev->name);
 501                 return;
 502         }
 503         memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
 504
 505         new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
 506                                 GFP_ATOMIC);
 507         if (!new_dma_addr_list) {
 508                 if (netif_msg_drv(lp))
 509                         printk("\n" KERN_ERR
 510                                "%s: Memory allocation failed.\n", dev->name);
 511                 goto free_new_tx_ring;
 512         }
 513
 514         new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
 515                                 GFP_ATOMIC);
 516         if (!new_skb_list) {
 517                 if (netif_msg_drv(lp))
 518                         printk("\n" KERN_ERR
 519                                "%s: Memory allocation failed.\n", dev->name);
 520                 goto free_new_lists;
 521         }
 522
 523         kfree(lp->tx_skbuff);
 524         kfree(lp->tx_dma_addr);
 525         pci_free_consistent(lp->pci_dev,
 526                             sizeof(struct pcnet32_tx_head) *
 527                             lp->tx_ring_size, lp->tx_ring,
 528                             lp->tx_ring_dma_addr);
 529
 530         lp->tx_ring_size = (1 << size);
 531         lp->tx_mod_mask = lp->tx_ring_size - 1;
 532         lp->tx_len_bits = (size << 12);
 533         lp->tx_ring = new_tx_ring;
 534         lp->tx_ring_dma_addr = new_ring_dma_addr;
 535         lp->tx_dma_addr = new_dma_addr_list;
 536         lp->tx_skbuff = new_skb_list;
 537         return;
 538
 539     free_new_lists:
 540         kfree(new_dma_addr_list);
 541     free_new_tx_ring:
 542         pci_free_consistent(lp->pci_dev,
 543                             sizeof(struct pcnet32_tx_head) *
 544                             (1 << size),
 545                             new_tx_ring,
 546                             new_ring_dma_addr);
 547         return;
 548 }
 549
 550 /*
 551  * Allocate space for the new sized rx ring.
 552  * Re-use old receive buffers.
 553  *   alloc extra buffers
 554  *   free unneeded buffers
 555  *   free unneeded buffers
 556  * Save new resources.
 557  * Any failure keeps old resources.
 558  * Must be called with lp->lock held.
 559  */
 560 static void pcnet32_realloc_rx_ring(struct net_device *dev,
 561                                     struct pcnet32_private *lp,
 562                                     unsigned int size)
 563 {
 564         dma_addr_t new_ring_dma_addr;
 565         dma_addr_t *new_dma_addr_list;
 566         struct pcnet32_rx_head *new_rx_ring;
 567         struct sk_buff **new_skb_list;
 568         int new, overlap;
 569
 570         new_rx_ring = pci_alloc_consistent(lp->pci_dev,
 571                                            sizeof(struct pcnet32_rx_head) *
 572                                            (1 << size),
 573                                            &new_ring_dma_addr);
 574         if (new_rx_ring == NULL) {
 575                 if (netif_msg_drv(lp))
 576                         printk("\n" KERN_ERR
 577                                "%s: Consistent memory allocation failed.\n",
 578                                dev->name);
 579                 return;
 580         }
 581         memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
 582
 583         new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
 584                                 GFP_ATOMIC);
 585         if (!new_dma_addr_list) {
 586                 if (netif_msg_drv(lp))
 587                         printk("\n" KERN_ERR
 588                                "%s: Memory allocation failed.\n", dev->name);
 589                 goto free_new_rx_ring;
 590         }
 591
 592         new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
 593                                 GFP_ATOMIC);
 594         if (!new_skb_list) {
 595                 if (netif_msg_drv(lp))
 596                         printk("\n" KERN_ERR
 597                                "%s: Memory allocation failed.\n", dev->name);
 598                 goto free_new_lists;
 599         }
 600
 601         /* first copy the current receive buffers */
 602         overlap = min(size, lp->rx_ring_size);
 603         for (new = 0; new < overlap; new++) {
 604                 new_rx_ring[new] = lp->rx_ring[new];
 605                 new_dma_addr_list[new] = lp->rx_dma_addr[new];
 606                 new_skb_list[new] = lp->rx_skbuff[new];
 607         }
 608         /* now allocate any new buffers needed */
 609         for (; new < size; new++ ) {
 610                 struct sk_buff *rx_skbuff;
 611                 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SKB);
 612                 if (!(rx_skbuff = new_skb_list[new])) {
 613                         /* keep the original lists and buffers */
 614                         if (netif_msg_drv(lp))
 615                                 printk(KERN_ERR
 616                                        "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
 617                                        dev->name);
 618                         goto free_all_new;
 619                 }
 620                 skb_reserve(rx_skbuff, NET_IP_ALIGN);
 621
 622                 new_dma_addr_list[new] =
 623                             pci_map_single(lp->pci_dev, rx_skbuff->data,
 624                                            PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 625                 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
 626                 new_rx_ring[new].buf_length = cpu_to_le16(NEG_BUF_SIZE);
 627                 new_rx_ring[new].status = cpu_to_le16(0x8000);
 628         }
 629         /* and free any unneeded buffers */
 630         for (; new < lp->rx_ring_size; new++) {
 631                 if (lp->rx_skbuff[new]) {
 632                         pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
 633                                          PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 634                         dev_kfree_skb(lp->rx_skbuff[new]);
 635                 }
 636         }
 637
 638         kfree(lp->rx_skbuff);
 639         kfree(lp->rx_dma_addr);
 640         pci_free_consistent(lp->pci_dev,
 641                             sizeof(struct pcnet32_rx_head) *
 642                             lp->rx_ring_size, lp->rx_ring,
 643                             lp->rx_ring_dma_addr);
 644
 645         lp->rx_ring_size = (1 << size);
 646         lp->rx_mod_mask = lp->rx_ring_size - 1;
 647         lp->rx_len_bits = (size << 4);
 648         lp->rx_ring = new_rx_ring;
 649         lp->rx_ring_dma_addr = new_ring_dma_addr;
 650         lp->rx_dma_addr = new_dma_addr_list;
 651         lp->rx_skbuff = new_skb_list;
 652         return;
 653
 654     free_all_new:
 655         for (; --new >= lp->rx_ring_size; ) {
 656                 if (new_skb_list[new]) {
 657                         pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
 658                                          PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 659                         dev_kfree_skb(new_skb_list[new]);
 660                 }
 661         }
 662         kfree(new_skb_list);
 663     free_new_lists:
 664         kfree(new_dma_addr_list);
 665     free_new_rx_ring:
 666         pci_free_consistent(lp->pci_dev,
 667                             sizeof(struct pcnet32_rx_head) *
 668                             (1 << size),
 669                             new_rx_ring,
 670                             new_ring_dma_addr);
 671         return;
 672 }
 673
 674 static void pcnet32_purge_rx_ring(struct net_device *dev)
 675 {
 676         struct pcnet32_private *lp = netdev_priv(dev);
 677         int i;
 678
 679         /* free all allocated skbuffs */
 680         for (i = 0; i < lp->rx_ring_size; i++) {
 681                 lp->rx_ring[i].status = 0;      /* CPU owns buffer */
 682                 wmb();          /* Make sure adapter sees owner change */
 683                 if (lp->rx_skbuff[i]) {
 684                         pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
 685                                          PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
 686                         dev_kfree_skb_any(lp->rx_skbuff[i]);
 687                 }
 688                 lp->rx_skbuff[i] = NULL;
 689                 lp->rx_dma_addr[i] = 0;
 690         }
 691 }
 692
 693 #ifdef CONFIG_NET_POLL_CONTROLLER
 694 static void pcnet32_poll_controller(struct net_device *dev)
 695 {
 696         disable_irq(dev->irq);
 697         pcnet32_interrupt(0, dev);
 698         enable_irq(dev->irq);
 699 }
 700 #endif
 701
 702 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 703 {
 704         struct pcnet32_private *lp = netdev_priv(dev);
 705         unsigned long flags;
 706         int r = -EOPNOTSUPP;
 707
 708         if (lp->mii) {
 709                 spin_lock_irqsave(&lp->lock, flags);
 710                 mii_ethtool_gset(&lp->mii_if, cmd);
 711                 spin_unlock_irqrestore(&lp->lock, flags);
 712                 r = 0;
 713         }
 714         return r;
 715 }
 716
 717 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 718 {
 719         struct pcnet32_private *lp = netdev_priv(dev);
 720         unsigned long flags;
 721         int r = -EOPNOTSUPP;
 722
 723         if (lp->mii) {
 724                 spin_lock_irqsave(&lp->lock, flags);
 725                 r = mii_ethtool_sset(&lp->mii_if, cmd);
 726                 spin_unlock_irqrestore(&lp->lock, flags);
 727         }
 728         return r;
 729 }
 730
 731 static void pcnet32_get_drvinfo(struct net_device *dev,
 732                                 struct ethtool_drvinfo *info)
 733 {
 734         struct pcnet32_private *lp = netdev_priv(dev);
 735
 736         strcpy(info->driver, DRV_NAME);
 737         strcpy(info->version, DRV_VERSION);
 738         if (lp->pci_dev)
 739                 strcpy(info->bus_info, pci_name(lp->pci_dev));
 740         else
 741                 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
 742 }
 743
 744 static u32 pcnet32_get_link(struct net_device *dev)
 745 {
 746         struct pcnet32_private *lp = netdev_priv(dev);
 747         unsigned long flags;
 748         int r;
 749
 750         spin_lock_irqsave(&lp->lock, flags);
 751         if (lp->mii) {
 752                 r = mii_link_ok(&lp->mii_if);
 753         } else if (lp->chip_version >= PCNET32_79C970A) {
 754                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
 755                 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
 756         } else {        /* can not detect link on really old chips */
 757                 r = 1;
 758         }
 759         spin_unlock_irqrestore(&lp->lock, flags);
 760
 761         return r;
 762 }
 763
 764 static u32 pcnet32_get_msglevel(struct net_device *dev)
 765 {
 766         struct pcnet32_private *lp = netdev_priv(dev);
 767         return lp->msg_enable;
 768 }
 769
 770 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
 771 {
 772         struct pcnet32_private *lp = netdev_priv(dev);
 773         lp->msg_enable = value;
 774 }
 775
 776 static int pcnet32_nway_reset(struct net_device *dev)
 777 {
 778         struct pcnet32_private *lp = netdev_priv(dev);
 779         unsigned long flags;
 780         int r = -EOPNOTSUPP;
 781
 782         if (lp->mii) {
 783                 spin_lock_irqsave(&lp->lock, flags);
 784                 r = mii_nway_restart(&lp->mii_if);
 785                 spin_unlock_irqrestore(&lp->lock, flags);
 786         }
 787         return r;
 788 }
 789
 790 static void pcnet32_get_ringparam(struct net_device *dev,
 791                                   struct ethtool_ringparam *ering)
 792 {
 793         struct pcnet32_private *lp = netdev_priv(dev);
 794
 795         ering->tx_max_pending = TX_MAX_RING_SIZE;
 796         ering->tx_pending = lp->tx_ring_size;
 797         ering->rx_max_pending = RX_MAX_RING_SIZE;
 798         ering->rx_pending = lp->rx_ring_size;
 799 }
 800
 801 static int pcnet32_set_ringparam(struct net_device *dev,
 802                                  struct ethtool_ringparam *ering)
 803 {
 804         struct pcnet32_private *lp = netdev_priv(dev);
 805         unsigned long flags;
 806         unsigned int size;
 807         ulong ioaddr = dev->base_addr;
 808         int i;
 809
 810         if (ering->rx_mini_pending || ering->rx_jumbo_pending)
 811                 return -EINVAL;
 812
 813         if (netif_running(dev))
 814                 pcnet32_netif_stop(dev);
 815
 816         spin_lock_irqsave(&lp->lock, flags);
 817         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* stop the chip */
 818
 819         size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
 820
 821         /* set the minimum ring size to 4, to allow the loopback test to work
 822          * unchanged.
 823          */
 824         for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
 825                 if (size <= (1 << i))
 826                         break;
 827         }
 828         if ((1 << i) != lp->tx_ring_size)
 829                 pcnet32_realloc_tx_ring(dev, lp, i);
 830
 831         size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
 832         for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
 833                 if (size <= (1 << i))
 834                         break;
 835         }
 836         if ((1 << i) != lp->rx_ring_size)
 837                 pcnet32_realloc_rx_ring(dev, lp, i);
 838
 839         lp->napi.weight = lp->rx_ring_size / 2;
 840
 841         if (netif_running(dev)) {
 842                 pcnet32_netif_start(dev);
 843                 pcnet32_restart(dev, CSR0_NORMAL);
 844         }
 845
 846         spin_unlock_irqrestore(&lp->lock, flags);
 847
 848         if (netif_msg_drv(lp))
 849                 printk(KERN_INFO
 850                        "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
 851                        lp->rx_ring_size, lp->tx_ring_size);
 852
 853         return 0;
 854 }
 855
 856 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
 857                                 u8 * data)
 858 {
 859         memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
 860 }
 861
 862 static int pcnet32_get_sset_count(struct net_device *dev, int sset)
 863 {
 864         switch (sset) {
 865         case ETH_SS_TEST:
 866                 return PCNET32_TEST_LEN;
 867         default:
 868                 return -EOPNOTSUPP;
 869         }
 870 }
 871
 872 static void pcnet32_ethtool_test(struct net_device *dev,
 873                                  struct ethtool_test *test, u64 * data)
 874 {
 875         struct pcnet32_private *lp = netdev_priv(dev);
 876         int rc;
 877
 878         if (test->flags == ETH_TEST_FL_OFFLINE) {
 879                 rc = pcnet32_loopback_test(dev, data);
 880                 if (rc) {
 881                         if (netif_msg_hw(lp))
 882                                 printk(KERN_DEBUG "%s: Loopback test failed.\n",
 883                                        dev->name);
 884                         test->flags |= ETH_TEST_FL_FAILED;
 885                 } else if (netif_msg_hw(lp))
 886                         printk(KERN_DEBUG "%s: Loopback test passed.\n",
 887                                dev->name);
 888         } else if (netif_msg_hw(lp))
 889                 printk(KERN_DEBUG
 890                        "%s: No tests to run (specify 'Offline' on ethtool).",
 891                        dev->name);
 892 }                               /* end pcnet32_ethtool_test */
 893
 894 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
 895 {
 896         struct pcnet32_private *lp = netdev_priv(dev);
 897         struct pcnet32_access *a = &lp->a;      /* access to registers */
 898         ulong ioaddr = dev->base_addr;  /* card base I/O address */
 899         struct sk_buff *skb;    /* sk buff */
 900         int x, i;               /* counters */
 901         int numbuffs = 4;       /* number of TX/RX buffers and descs */
 902         u16 status = 0x8300;    /* TX ring status */
 903         __le16 teststatus;      /* test of ring status */
 904         int rc;                 /* return code */
 905         int size;               /* size of packets */
 906         unsigned char *packet;  /* source packet data */
 907         static const int data_len = 60; /* length of source packets */
 908         unsigned long flags;
 909         unsigned long ticks;
 910
 911         rc = 1;                 /* default to fail */
 912
 913         if (netif_running(dev))
 914 #ifdef CONFIG_PCNET32_NAPI
 915                 pcnet32_netif_stop(dev);
 916 #else
 917                 pcnet32_close(dev);
 918 #endif
 919
 920         spin_lock_irqsave(&lp->lock, flags);
 921         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* stop the chip */
 922
 923         numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
 924
 925         /* Reset the PCNET32 */
 926         lp->a.reset(ioaddr);
 927         lp->a.write_csr(ioaddr, CSR4, 0x0915);  /* auto tx pad */
 928
 929         /* switch pcnet32 to 32bit mode */
 930         lp->a.write_bcr(ioaddr, 20, 2);
 931
 932         /* purge & init rings but don't actually restart */
 933         pcnet32_restart(dev, 0x0000);
 934
 935         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* Set STOP bit */
 936
 937         /* Initialize Transmit buffers. */
 938         size = data_len + 15;
 939         for (x = 0; x < numbuffs; x++) {
 940                 if (!(skb = dev_alloc_skb(size))) {
 941                         if (netif_msg_hw(lp))
 942                                 printk(KERN_DEBUG
 943                                        "%s: Cannot allocate skb at line: %d!\n",
 944                                        dev->name, __LINE__);
 945                         goto clean_up;
 946                 } else {
 947                         packet = skb->data;
 948                         skb_put(skb, size);     /* create space for data */
 949                         lp->tx_skbuff[x] = skb;
 950                         lp->tx_ring[x].length = cpu_to_le16(-skb->len);
 951                         lp->tx_ring[x].misc = 0;
 952
 953                         /* put DA and SA into the skb */
 954                         for (i = 0; i < 6; i++)
 955                                 *packet++ = dev->dev_addr[i];
 956                         for (i = 0; i < 6; i++)
 957                                 *packet++ = dev->dev_addr[i];
 958                         /* type */
 959                         *packet++ = 0x08;
 960                         *packet++ = 0x06;
 961                         /* packet number */
 962                         *packet++ = x;
 963                         /* fill packet with data */
 964                         for (i = 0; i < data_len; i++)
 965                                 *packet++ = i;
 966
 967                         lp->tx_dma_addr[x] =
 968                             pci_map_single(lp->pci_dev, skb->data, skb->len,
 969                                            PCI_DMA_TODEVICE);
 970                         lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
 971                         wmb();  /* Make sure owner changes after all others are visible */
 972                         lp->tx_ring[x].status = cpu_to_le16(status);
 973                 }
 974         }
 975
 976         x = a->read_bcr(ioaddr, 32);    /* set internal loopback in BCR32 */
 977         a->write_bcr(ioaddr, 32, x | 0x0002);
 978
 979         /* set int loopback in CSR15 */
 980         x = a->read_csr(ioaddr, CSR15) & 0xfffc;
 981         lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
 982
 983         teststatus = cpu_to_le16(0x8000);
 984         lp->a.write_csr(ioaddr, CSR0, CSR0_START);      /* Set STRT bit */
 985
 986         /* Check status of descriptors */
 987         for (x = 0; x < numbuffs; x++) {
 988                 ticks = 0;
 989                 rmb();
 990                 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
 991                         spin_unlock_irqrestore(&lp->lock, flags);
 992                         msleep(1);
 993                         spin_lock_irqsave(&lp->lock, flags);
 994                         rmb();
 995                         ticks++;
 996                 }
 997                 if (ticks == 200) {
 998                         if (netif_msg_hw(lp))
 999                                 printk("%s: Desc %d failed to reset!\n",
1000                                        dev->name, x);
1001                         break;
1002                 }
1003         }
1004
1005         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);       /* Set STOP bit */
1006         wmb();
1007         if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
1008                 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
1009
1010                 for (x = 0; x < numbuffs; x++) {
1011                         printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
1012                         skb = lp->rx_skbuff[x];
1013                         for (i = 0; i < size; i++) {
1014                                 printk("%02x ", *(skb->data + i));
1015                         }
1016                         printk("\n");
1017                 }
1018         }
1019
1020         x = 0;
1021         rc = 0;
1022         while (x < numbuffs && !rc) {
1023                 skb = lp->rx_skbuff[x];
1024                 packet = lp->tx_skbuff[x]->data;
1025                 for (i = 0; i < size; i++) {
1026                         if (*(skb->data + i) != packet[i]) {
1027                                 if (netif_msg_hw(lp))
1028                                         printk(KERN_DEBUG
1029                                                "%s: Error in compare! %2x - %02x %02x\n",
1030                                                dev->name, i, *(skb->data + i),
1031                                                packet[i]);
1032                                 rc = 1;
1033                                 break;
1034                         }
1035                 }
1036                 x++;
1037         }
1038
1039       clean_up:
1040         *data1 = rc;
1041         pcnet32_purge_tx_ring(dev);
1042
1043         x = a->read_csr(ioaddr, CSR15);
1044         a->write_csr(ioaddr, CSR15, (x & ~0x0044));     /* reset bits 6 and 2 */
1045
1046         x = a->read_bcr(ioaddr, 32);    /* reset internal loopback */
1047         a->write_bcr(ioaddr, 32, (x & ~0x0002));
1048
1049 #ifdef CONFIG_PCNET32_NAPI
1050         if (netif_running(dev)) {
1051                 pcnet32_netif_start(dev);
1052                 pcnet32_restart(dev, CSR0_NORMAL);
1053         } else {
1054                 pcnet32_purge_rx_ring(dev);
1055                 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1056         }
1057         spin_unlock_irqrestore(&lp->lock, flags);
1058 #else
1059         if (netif_running(dev)) {
1060                 spin_unlock_irqrestore(&lp->lock, flags);
1061                 pcnet32_open(dev);
1062         } else {
1063                 pcnet32_purge_rx_ring(dev);
1064                 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1065                 spin_unlock_irqrestore(&lp->lock, flags);
1066         }
1067 #endif
1068
1069         return (rc);
1070 }                               /* end pcnet32_loopback_test  */
1071
1072 static void pcnet32_led_blink_callback(struct net_device *dev)
1073 {
1074         struct pcnet32_private *lp = netdev_priv(dev);
1075         struct pcnet32_access *a = &lp->a;
1076         ulong ioaddr = dev->base_addr;
1077         unsigned long flags;
1078         int i;
1079
1080         spin_lock_irqsave(&lp->lock, flags);
1081         for (i = 4; i < 8; i++) {
1082                 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1083         }
1084         spin_unlock_irqrestore(&lp->lock, flags);
1085
1086         mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1087 }
1088
1089 static int pcnet32_phys_id(struct net_device *dev, u32 data)
1090 {
1091         struct pcnet32_private *lp = netdev_priv(dev);
1092         struct pcnet32_access *a = &lp->a;
1093         ulong ioaddr = dev->base_addr;
1094         unsigned long flags;
1095         int i, regs[4];
1096
1097         if (!lp->blink_timer.function) {
1098                 init_timer(&lp->blink_timer);
1099                 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1100                 lp->blink_timer.data = (unsigned long)dev;
1101         }
1102
1103         /* Save the current value of the bcrs */
1104         spin_lock_irqsave(&lp->lock, flags);
1105         for (i = 4; i < 8; i++) {
1106                 regs[i - 4] = a->read_bcr(ioaddr, i);
1107         }
1108         spin_unlock_irqrestore(&lp->lock, flags);
1109
1110         mod_timer(&lp->blink_timer, jiffies);
1111         set_current_state(TASK_INTERRUPTIBLE);
1112
1113         /* AV: the limit here makes no sense whatsoever */
1114         if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1115                 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1116
1117         msleep_interruptible(data * 1000);
1118         del_timer_sync(&lp->blink_timer);
1119
1120         /* Restore the original value of the bcrs */
1121         spin_lock_irqsave(&lp->lock, flags);
1122         for (i = 4; i < 8; i++) {
1123                 a->write_bcr(ioaddr, i, regs[i - 4]);
1124         }
1125         spin_unlock_irqrestore(&lp->lock, flags);
1126
1127         return 0;
1128 }
1129
1130 /*
1131  * lp->lock must be held.
1132  */
1133 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1134                 int can_sleep)
1135 {
1136         int csr5;
1137         struct pcnet32_private *lp = netdev_priv(dev);
1138         struct pcnet32_access *a = &lp->a;
1139         ulong ioaddr = dev->base_addr;
1140         int ticks;
1141
1142         /* really old chips have to be stopped. */
1143         if (lp->chip_version < PCNET32_79C970A)
1144                 return 0;
1145
1146         /* set SUSPEND (SPND) - CSR5 bit 0 */
1147         csr5 = a->read_csr(ioaddr, CSR5);
1148         a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1149
1150         /* poll waiting for bit to be set */
1151         ticks = 0;
1152         while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1153                 spin_unlock_irqrestore(&lp->lock, *flags);
1154                 if (can_sleep)
1155                         msleep(1);
1156                 else
1157                         mdelay(1);
1158                 spin_lock_irqsave(&lp->lock, *flags);
1159                 ticks++;
1160                 if (ticks > 200) {
1161                         if (netif_msg_hw(lp))
1162                                 printk(KERN_DEBUG
1163                                        "%s: Error getting into suspend!\n",
1164                                        dev->name);
1165                         return 0;
1166                 }
1167         }
1168         return 1;
1169 }
1170
1171 /*
1172  * process one receive descriptor entry
1173  */
1174
1175 static void pcnet32_rx_entry(struct net_device *dev,
1176                              struct pcnet32_private *lp,
1177                              struct pcnet32_rx_head *rxp,
1178                              int entry)
1179 {
1180         int status = (short)le16_to_cpu(rxp->status) >> 8;
1181         int rx_in_place = 0;
1182         struct sk_buff *skb;
1183         short pkt_len;
1184
1185         if (status != 0x03) {   /* There was an error. */
1186                 /*
1187                  * There is a tricky error noted by John Murphy,
1188                  * <murf@perftech.com> to Russ Nelson: Even with full-sized
1189                  * buffers it's possible for a jabber packet to use two
1190                  * buffers, with only the last correctly noting the error.
1191                  */
1192                 if (status & 0x01)      /* Only count a general error at the */
1193                         dev->stats.rx_errors++; /* end of a packet. */
1194                 if (status & 0x20)
1195                         dev->stats.rx_frame_errors++;
1196                 if (status & 0x10)
1197                         dev->stats.rx_over_errors++;
1198                 if (status & 0x08)
1199                         dev->stats.rx_crc_errors++;
1200                 if (status & 0x04)
1201                         dev->stats.rx_fifo_errors++;
1202                 return;
1203         }
1204
1205         pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1206
1207         /* Discard oversize frames. */
1208         if (unlikely(pkt_len > PKT_BUF_SIZE)) {
1209                 if (netif_msg_drv(lp))
1210                         printk(KERN_ERR "%s: Impossible packet size %d!\n",
1211                                dev->name, pkt_len);
1212                 dev->stats.rx_errors++;
1213                 return;
1214         }
1215         if (pkt_len < 60) {
1216                 if (netif_msg_rx_err(lp))
1217                         printk(KERN_ERR "%s: Runt packet!\n", dev->name);
1218                 dev->stats.rx_errors++;
1219                 return;
1220         }
1221
1222         if (pkt_len > rx_copybreak) {
1223                 struct sk_buff *newskb;
1224
1225                 if ((newskb = dev_alloc_skb(PKT_BUF_SKB))) {
1226                         skb_reserve(newskb, NET_IP_ALIGN);
1227                         skb = lp->rx_skbuff[entry];
1228                         pci_unmap_single(lp->pci_dev,
1229                                          lp->rx_dma_addr[entry],
1230                                          PKT_BUF_SIZE,
1231                                          PCI_DMA_FROMDEVICE);
1232                         skb_put(skb, pkt_len);
1233                         lp->rx_skbuff[entry] = newskb;
1234                         lp->rx_dma_addr[entry] =
1235                                             pci_map_single(lp->pci_dev,
1236                                                            newskb->data,
1237                                                            PKT_BUF_SIZE,
1238                                                            PCI_DMA_FROMDEVICE);
1239                         rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
1240                         rx_in_place = 1;
1241                 } else
1242                         skb = NULL;
1243         } else {
1244                 skb = dev_alloc_skb(pkt_len + NET_IP_ALIGN);
1245         }
1246
1247         if (skb == NULL) {
1248                 if (netif_msg_drv(lp))
1249                         printk(KERN_ERR
1250                                "%s: Memory squeeze, dropping packet.\n",
1251                                dev->name);
1252                 dev->stats.rx_dropped++;
1253                 return;
1254         }
1255         skb->dev = dev;
1256         if (!rx_in_place) {
1257                 skb_reserve(skb, NET_IP_ALIGN);
1258                 skb_put(skb, pkt_len);  /* Make room */
1259                 pci_dma_sync_single_for_cpu(lp->pci_dev,
1260                                             lp->rx_dma_addr[entry],
1261                                             pkt_len,
1262                                             PCI_DMA_FROMDEVICE);
1263                 skb_copy_to_linear_data(skb,
1264                                  (unsigned char *)(lp->rx_skbuff[entry]->data),
1265                                  pkt_len);
1266                 pci_dma_sync_single_for_device(lp->pci_dev,
1267                                                lp->rx_dma_addr[entry],
1268                                                pkt_len,
1269                                                PCI_DMA_FROMDEVICE);
1270         }
1271         dev->stats.rx_bytes += skb->len;
1272         skb->protocol = eth_type_trans(skb, dev);
1273 #ifdef CONFIG_PCNET32_NAPI
1274         netif_receive_skb(skb);
1275 #else
1276         netif_rx(skb);
1277 #endif
1278         dev->last_rx = jiffies;
1279         dev->stats.rx_packets++;
1280         return;
1281 }
1282
1283 static int pcnet32_rx(struct net_device *dev, int budget)
1284 {
1285         struct pcnet32_private *lp = netdev_priv(dev);
1286         int entry = lp->cur_rx & lp->rx_mod_mask;
1287         struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1288         int npackets = 0;
1289
1290         /* If we own the next entry, it's a new packet. Send it up. */
1291         while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
1292                 pcnet32_rx_entry(dev, lp, rxp, entry);
1293                 npackets += 1;
1294                 /*
1295                  * The docs say that the buffer length isn't touched, but Andrew
1296                  * Boyd of QNX reports that some revs of the 79C965 clear it.
1297                  */
1298                 rxp->buf_length = cpu_to_le16(NEG_BUF_SIZE);
1299                 wmb();  /* Make sure owner changes after others are visible */
1300                 rxp->status = cpu_to_le16(0x8000);
1301                 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1302                 rxp = &lp->rx_ring[entry];
1303         }
1304
1305         return npackets;
1306 }
1307
1308 static int pcnet32_tx(struct net_device *dev)
1309 {
1310         struct pcnet32_private *lp = netdev_priv(dev);
1311         unsigned int dirty_tx = lp->dirty_tx;
1312         int delta;
1313         int must_restart = 0;
1314
1315         while (dirty_tx != lp->cur_tx) {
1316                 int entry = dirty_tx & lp->tx_mod_mask;
1317                 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1318
1319                 if (status < 0)
1320                         break;  /* It still hasn't been Txed */
1321
1322                 lp->tx_ring[entry].base = 0;
1323
1324                 if (status & 0x4000) {
1325                         /* There was a major error, log it. */
1326                         int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1327                         dev->stats.tx_errors++;
1328                         if (netif_msg_tx_err(lp))
1329                                 printk(KERN_ERR
1330                                        "%s: Tx error status=%04x err_status=%08x\n",
1331                                        dev->name, status,
1332                                        err_status);
1333                         if (err_status & 0x04000000)
1334                                 dev->stats.tx_aborted_errors++;
1335                         if (err_status & 0x08000000)
1336                                 dev->stats.tx_carrier_errors++;
1337                         if (err_status & 0x10000000)
1338                                 dev->stats.tx_window_errors++;
1339 #ifndef DO_DXSUFLO
1340                         if (err_status & 0x40000000) {
1341                                 dev->stats.tx_fifo_errors++;
1342                                 /* Ackk!  On FIFO errors the Tx unit is turned off! */
1343                                 /* Remove this verbosity later! */
1344                                 if (netif_msg_tx_err(lp))
1345                                         printk(KERN_ERR
1346                                                "%s: Tx FIFO error!\n",
1347                                                dev->name);
1348                                 must_restart = 1;
1349                         }
1350 #else
1351                         if (err_status & 0x40000000) {
1352                                 dev->stats.tx_fifo_errors++;
1353                                 if (!lp->dxsuflo) {     /* If controller doesn't recover ... */
1354                                         /* Ackk!  On FIFO errors the Tx unit is turned off! */
1355                                         /* Remove this verbosity later! */
1356                                         if (netif_msg_tx_err(lp))
1357                                                 printk(KERN_ERR
1358                                                        "%s: Tx FIFO error!\n",
1359                                                        dev->name);
1360                                         must_restart = 1;
1361                                 }
1362                         }
1363 #endif
1364                 } else {
1365                         if (status & 0x1800)
1366                                 dev->stats.collisions++;
1367                         dev->stats.tx_packets++;
1368                 }
1369
1370                 /* We must free the original skb */
1371                 if (lp->tx_skbuff[entry]) {
1372                         pci_unmap_single(lp->pci_dev,
1373                                          lp->tx_dma_addr[entry],
1374                                          lp->tx_skbuff[entry]->
1375                                          len, PCI_DMA_TODEVICE);
1376                         dev_kfree_skb_any(lp->tx_skbuff[entry]);
1377                         lp->tx_skbuff[entry] = NULL;
1378                         lp->tx_dma_addr[entry] = 0;
1379                 }
1380                 dirty_tx++;
1381         }
1382
1383         delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1384         if (delta > lp->tx_ring_size) {
1385                 if (netif_msg_drv(lp))
1386                         printk(KERN_ERR
1387                                "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1388                                dev->name, dirty_tx, lp->cur_tx,
1389                                lp->tx_full);
1390                 dirty_tx += lp->tx_ring_size;
1391                 delta -= lp->tx_ring_size;
1392         }
1393
1394         if (lp->tx_full &&
1395             netif_queue_stopped(dev) &&
1396             delta < lp->tx_ring_size - 2) {
1397                 /* The ring is no longer full, clear tbusy. */
1398                 lp->tx_full = 0;
1399                 netif_wake_queue(dev);
1400         }
1401         lp->dirty_tx = dirty_tx;
1402
1403         return must_restart;
1404 }
1405
1406 #ifdef CONFIG_PCNET32_NAPI
1407 static int pcnet32_poll(struct napi_struct *napi, int budget)
1408 {
1409         struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1410         struct net_device *dev = lp->dev;
1411         unsigned long ioaddr = dev->base_addr;
1412         unsigned long flags;
1413         int work_done;
1414         u16 val;
1415
1416         work_done = pcnet32_rx(dev, budget);
1417
1418         spin_lock_irqsave(&lp->lock, flags);
1419         if (pcnet32_tx(dev)) {
1420                 /* reset the chip to clear the error condition, then restart */
1421                 lp->a.reset(ioaddr);
1422                 lp->a.write_csr(ioaddr, CSR4, 0x0915);  /* auto tx pad */
1423                 pcnet32_restart(dev, CSR0_START);
1424                 netif_wake_queue(dev);
1425         }
1426         spin_unlock_irqrestore(&lp->lock, flags);
1427
1428         if (work_done < budget) {
1429                 spin_lock_irqsave(&lp->lock, flags);
1430
1431                 __netif_rx_complete(dev, napi);
1432
1433                 /* clear interrupt masks */
1434                 val = lp->a.read_csr(ioaddr, CSR3);
1435                 val &= 0x00ff;
1436                 lp->a.write_csr(ioaddr, CSR3, val);
1437
1438                 /* Set interrupt enable. */
1439                 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
1440                 mmiowb();
1441                 spin_unlock_irqrestore(&lp->lock, flags);
1442         }
1443         return work_done;
1444 }
1445 #endif
1446
1447 #define PCNET32_REGS_PER_PHY    32
1448 #define PCNET32_MAX_PHYS        32
1449 static int pcnet32_get_regs_len(struct net_device *dev)
1450 {
1451         struct pcnet32_private *lp = netdev_priv(dev);
1452         int j = lp->phycount * PCNET32_REGS_PER_PHY;
1453
1454         return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1455 }
1456
1457 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1458                              void *ptr)
1459 {
1460         int i, csr0;
1461         u16 *buff = ptr;
1462         struct pcnet32_private *lp = netdev_priv(dev);
1463         struct pcnet32_access *a = &lp->a;
1464         ulong ioaddr = dev->base_addr;
1465         unsigned long flags;
1466
1467         spin_lock_irqsave(&lp->lock, flags);
1468
1469         csr0 = a->read_csr(ioaddr, CSR0);
1470         if (!(csr0 & CSR0_STOP))        /* If not stopped */
1471                 pcnet32_suspend(dev, &flags, 1);
1472
1473         /* read address PROM */
1474         for (i = 0; i < 16; i += 2)
1475                 *buff++ = inw(ioaddr + i);
1476
1477         /* read control and status registers */
1478         for (i = 0; i < 90; i++) {
1479                 *buff++ = a->read_csr(ioaddr, i);
1480         }
1481
1482         *buff++ = a->read_csr(ioaddr, 112);
1483         *buff++ = a->read_csr(ioaddr, 114);
1484
1485         /* read bus configuration registers */
1486         for (i = 0; i < 30; i++) {
1487                 *buff++ = a->read_bcr(ioaddr, i);
1488         }
1489         *buff++ = 0;            /* skip bcr30 so as not to hang 79C976 */
1490         for (i = 31; i < 36; i++) {
1491                 *buff++ = a->read_bcr(ioaddr, i);
1492         }
1493
1494         /* read mii phy registers */
1495         if (lp->mii) {
1496                 int j;
1497                 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1498                         if (lp->phymask & (1 << j)) {
1499                                 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1500                                         lp->a.write_bcr(ioaddr, 33,
1501                                                         (j << 5) | i);
1502                                         *buff++ = lp->a.read_bcr(ioaddr, 34);
1503                                 }
1504                         }
1505                 }
1506         }
1507
1508         if (!(csr0 & CSR0_STOP)) {      /* If not stopped */
1509                 int csr5;
1510
1511                 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1512                 csr5 = a->read_csr(ioaddr, CSR5);
1513                 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
1514         }
1515
1516         spin_unlock_irqrestore(&lp->lock, flags);
1517 }
1518
1519 static const struct ethtool_ops pcnet32_ethtool_ops = {
1520         .get_settings           = pcnet32_get_settings,
1521         .set_settings           = pcnet32_set_settings,
1522         .get_drvinfo            = pcnet32_get_drvinfo,
1523         .get_msglevel           = pcnet32_get_msglevel,
1524         .set_msglevel           = pcnet32_set_msglevel,
1525         .nway_reset             = pcnet32_nway_reset,
1526         .get_link               = pcnet32_get_link,
1527         .get_ringparam          = pcnet32_get_ringparam,
1528         .set_ringparam          = pcnet32_set_ringparam,
1529         .get_strings            = pcnet32_get_strings,
1530         .self_test              = pcnet32_ethtool_test,
1531         .phys_id                = pcnet32_phys_id,
1532         .get_regs_len           = pcnet32_get_regs_len,
1533         .get_regs               = pcnet32_get_regs,
1534         .get_sset_count         = pcnet32_get_sset_count,
1535 };
1536
1537 /* only probes for non-PCI devices, the rest are handled by
1538  * pci_register_driver via pcnet32_probe_pci */
1539
1540 static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1541 {
1542         unsigned int *port, ioaddr;
1543
1544         /* search for PCnet32 VLB cards at known addresses */
1545         for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1546                 if (request_region
1547                     (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1548                         /* check if there is really a pcnet chip on that ioaddr */
1549                         if ((inb(ioaddr + 14) == 0x57)
1550                             && (inb(ioaddr + 15) == 0x57)) {
1551                                 pcnet32_probe1(ioaddr, 0, NULL);
1552                         } else {
1553                                 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1554                         }
1555                 }
1556         }
1557 }
1558
1559 static int __devinit
1560 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1561 {
1562         unsigned long ioaddr;
1563         int err;
1564
1565         err = pci_enable_device(pdev);
1566         if (err < 0) {
1567                 if (pcnet32_debug & NETIF_MSG_PROBE)
1568                         printk(KERN_ERR PFX
1569                                "failed to enable device -- err=%d\n", err);
1570                 return err;
1571         }
1572         pci_set_master(pdev);
1573
1574         ioaddr = pci_resource_start(pdev, 0);
1575         if (!ioaddr) {
1576                 if (pcnet32_debug & NETIF_MSG_PROBE)
1577                         printk(KERN_ERR PFX
1578                                "card has no PCI IO resources, aborting\n");
1579                 return -ENODEV;
1580         }
1581
1582         if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1583                 if (pcnet32_debug & NETIF_MSG_PROBE)
1584                         printk(KERN_ERR PFX
1585                                "architecture does not support 32bit PCI busmaster DMA\n");
1586                 return -ENODEV;
1587         }
1588         if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1589             NULL) {
1590                 if (pcnet32_debug & NETIF_MSG_PROBE)
1591                         printk(KERN_ERR PFX
1592                                "io address range already allocated\n");
1593                 return -EBUSY;
1594         }
1595
1596         err = pcnet32_probe1(ioaddr, 1, pdev);
1597         if (err < 0) {
1598                 pci_disable_device(pdev);
1599         }
1600         return err;
1601 }
1602
1603 /* pcnet32_probe1
1604  *  Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1605  *  pdev will be NULL when called from pcnet32_probe_vlbus.
1606  */
1607 static int __devinit
1608 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1609 {
1610         struct pcnet32_private *lp;
1611         int i, media;
1612         int fdx, mii, fset, dxsuflo;
1613         int chip_version;
1614         char *chipname;
1615         struct net_device *dev;
1616         struct pcnet32_access *a = NULL;
1617         u8 promaddr[6];
1618         int ret = -ENODEV;
1619
1620         /* reset the chip */
1621         pcnet32_wio_reset(ioaddr);
1622
1623         /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1624         if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1625                 a = &pcnet32_wio;
1626         } else {
1627                 pcnet32_dwio_reset(ioaddr);
1628                 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1629                     && pcnet32_dwio_check(ioaddr)) {
1630                         a = &pcnet32_dwio;
1631                 } else
1632                         goto err_release_region;
1633         }
1634
1635         chip_version =
1636             a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1637         if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1638                 printk(KERN_INFO "  PCnet chip version is %#x.\n",
1639                        chip_version);
1640         if ((chip_version & 0xfff) != 0x003) {
1641                 if (pcnet32_debug & NETIF_MSG_PROBE)
1642                         printk(KERN_INFO PFX "Unsupported chip version.\n");
1643                 goto err_release_region;
1644         }
1645
1646         /* initialize variables */
1647         fdx = mii = fset = dxsuflo = 0;
1648         chip_version = (chip_version >> 12) & 0xffff;
1649
1650         switch (chip_version) {
1651         case 0x2420:
1652                 chipname = "PCnet/PCI 79C970";  /* PCI */
1653                 break;
1654         case 0x2430:
1655                 if (shared)
1656                         chipname = "PCnet/PCI 79C970";  /* 970 gives the wrong chip id back */
1657                 else
1658                         chipname = "PCnet/32 79C965";   /* 486/VL bus */
1659                 break;
1660         case 0x2621:
1661                 chipname = "PCnet/PCI II 79C970A";      /* PCI */
1662                 fdx = 1;
1663                 break;
1664         case 0x2623:
1665                 chipname = "PCnet/FAST 79C971"; /* PCI */
1666                 fdx = 1;
1667                 mii = 1;
1668                 fset = 1;
1669                 break;
1670         case 0x2624:
1671                 chipname = "PCnet/FAST+ 79C972";        /* PCI */
1672                 fdx = 1;
1673                 mii = 1;
1674                 fset = 1;
1675                 break;
1676         case 0x2625:
1677                 chipname = "PCnet/FAST III 79C973";     /* PCI */
1678                 fdx = 1;
1679                 mii = 1;
1680                 break;
1681         case 0x2626:
1682                 chipname = "PCnet/Home 79C978"; /* PCI */
1683                 fdx = 1;
1684                 /*
1685                  * This is based on specs published at www.amd.com.  This section
1686                  * assumes that a card with a 79C978 wants to go into standard
1687                  * ethernet mode.  The 79C978 can also go into 1Mb HomePNA mode,
1688                  * and the module option homepna=1 can select this instead.
1689                  */
1690                 media = a->read_bcr(ioaddr, 49);
1691                 media &= ~3;    /* default to 10Mb ethernet */
1692                 if (cards_found < MAX_UNITS && homepna[cards_found])
1693                         media |= 1;     /* switch to home wiring mode */
1694                 if (pcnet32_debug & NETIF_MSG_PROBE)
1695                         printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1696                                (media & 1) ? "1" : "10");
1697                 a->write_bcr(ioaddr, 49, media);
1698                 break;
1699         case 0x2627:
1700                 chipname = "PCnet/FAST III 79C975";     /* PCI */
1701                 fdx = 1;
1702                 mii = 1;
1703                 break;
1704         case 0x2628:
1705                 chipname = "PCnet/PRO 79C976";
1706                 fdx = 1;
1707                 mii = 1;
1708                 break;
1709         default:
1710                 if (pcnet32_debug & NETIF_MSG_PROBE)
1711                         printk(KERN_INFO PFX
1712                                "PCnet version %#x, no PCnet32 chip.\n",
1713                                chip_version);
1714                 goto err_release_region;
1715         }
1716
1717         /*
1718          *  On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1719          *  starting until the packet is loaded. Strike one for reliability, lose
1720          *  one for latency - although on PCI this isnt a big loss. Older chips
1721          *  have FIFO's smaller than a packet, so you can't do this.
1722          *  Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1723          */
1724
1725         if (fset) {
1726                 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1727                 a->write_csr(ioaddr, 80,
1728                              (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1729                 dxsuflo = 1;
1730         }
1731
1732         dev = alloc_etherdev(sizeof(*lp));
1733         if (!dev) {
1734                 if (pcnet32_debug & NETIF_MSG_PROBE)
1735                         printk(KERN_ERR PFX "Memory allocation failed.\n");
1736                 ret = -ENOMEM;
1737                 goto err_release_region;
1738         }
1739         SET_NETDEV_DEV(dev, &pdev->dev);
1740
1741         if (pcnet32_debug & NETIF_MSG_PROBE)
1742                 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1743
1744         /* In most chips, after a chip reset, the ethernet address is read from the
1745          * station address PROM at the base address and programmed into the
1746          * "Physical Address Registers" CSR12-14.
1747          * As a precautionary measure, we read the PROM values and complain if
1748          * they disagree with the CSRs.  If they miscompare, and the PROM addr
1749          * is valid, then the PROM addr is used.
1750          */
1751         for (i = 0; i < 3; i++) {
1752                 unsigned int val;
1753                 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1754                 /* There may be endianness issues here. */
1755                 dev->dev_addr[2 * i] = val & 0x0ff;
1756                 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1757         }
1758
1759         /* read PROM address and compare with CSR address */
1760         for (i = 0; i < 6; i++)
1761                 promaddr[i] = inb(ioaddr + i);
1762
1763         if (memcmp(promaddr, dev->dev_addr, 6)
1764             || !is_valid_ether_addr(dev->dev_addr)) {
1765                 if (is_valid_ether_addr(promaddr)) {
1766                         if (pcnet32_debug & NETIF_MSG_PROBE) {
1767                                 printk(" warning: CSR address invalid,\n");
1768                                 printk(KERN_INFO
1769                                        "    using instead PROM address of");
1770                         }
1771                         memcpy(dev->dev_addr, promaddr, 6);
1772                 }
1773         }
1774         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1775
1776         /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1777         if (!is_valid_ether_addr(dev->perm_addr))
1778                 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1779
1780         if (pcnet32_debug & NETIF_MSG_PROBE) {
1781                 DECLARE_MAC_BUF(mac);
1782                 printk(" %s", print_mac(mac, dev->dev_addr));
1783
1784                 /* Version 0x2623 and 0x2624 */
1785                 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1786                         i = a->read_csr(ioaddr, 80) & 0x0C00;   /* Check tx_start_pt */
1787                         printk("\n" KERN_INFO "    tx_start_pt(0x%04x):", i);
1788                         switch (i >> 10) {
1789                         case 0:
1790                                 printk("  20 bytes,");
1791                                 break;
1792                         case 1:
1793                                 printk("  64 bytes,");
1794                                 break;
1795                         case 2:
1796                                 printk(" 128 bytes,");
1797                                 break;
1798                         case 3:
1799                                 printk("~220 bytes,");
1800                                 break;
1801                         }
1802                         i = a->read_bcr(ioaddr, 18);    /* Check Burst/Bus control */
1803                         printk(" BCR18(%x):", i & 0xffff);
1804                         if (i & (1 << 5))
1805                                 printk("BurstWrEn ");
1806                         if (i & (1 << 6))
1807                                 printk("BurstRdEn ");
1808                         if (i & (1 << 7))
1809                                 printk("DWordIO ");
1810                         if (i & (1 << 11))
1811                                 printk("NoUFlow ");
1812                         i = a->read_bcr(ioaddr, 25);
1813                         printk("\n" KERN_INFO "    SRAMSIZE=0x%04x,", i << 8);
1814                         i = a->read_bcr(ioaddr, 26);
1815                         printk(" SRAM_BND=0x%04x,", i << 8);
1816                         i = a->read_bcr(ioaddr, 27);
1817                         if (i & (1 << 14))
1818                                 printk("LowLatRx");
1819                 }
1820         }
1821
1822         dev->base_addr = ioaddr;
1823         lp = netdev_priv(dev);
1824         /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1825         if ((lp->init_block =
1826              pci_alloc_consistent(pdev, sizeof(*lp->init_block), &lp->init_dma_addr)) == NULL) {
1827                 if (pcnet32_debug & NETIF_MSG_PROBE)
1828                         printk(KERN_ERR PFX
1829                                "Consistent memory allocation failed.\n");
1830                 ret = -ENOMEM;
1831                 goto err_free_netdev;
1832         }
1833         lp->pci_dev = pdev;
1834
1835         lp->dev = dev;
1836
1837         spin_lock_init(&lp->lock);
1838
1839         SET_NETDEV_DEV(dev, &pdev->dev);
1840         lp->name = chipname;
1841         lp->shared_irq = shared;
1842         lp->tx_ring_size = TX_RING_SIZE;        /* default tx ring size */
1843         lp->rx_ring_size = RX_RING_SIZE;        /* default rx ring size */
1844         lp->tx_mod_mask = lp->tx_ring_size - 1;
1845         lp->rx_mod_mask = lp->rx_ring_size - 1;
1846         lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1847         lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1848         lp->mii_if.full_duplex = fdx;
1849         lp->mii_if.phy_id_mask = 0x1f;
1850         lp->mii_if.reg_num_mask = 0x1f;
1851         lp->dxsuflo = dxsuflo;
1852         lp->mii = mii;
1853         lp->chip_version = chip_version;
1854         lp->msg_enable = pcnet32_debug;
1855         if ((cards_found >= MAX_UNITS)
1856             || (options[cards_found] > sizeof(options_mapping)))
1857                 lp->options = PCNET32_PORT_ASEL;
1858         else
1859                 lp->options = options_mapping[options[cards_found]];
1860         lp->mii_if.dev = dev;
1861         lp->mii_if.mdio_read = mdio_read;
1862         lp->mii_if.mdio_write = mdio_write;
1863
1864         /* napi.weight is used in both the napi and non-napi cases */
1865         lp->napi.weight = lp->rx_ring_size / 2;
1866
1867 #ifdef CONFIG_PCNET32_NAPI
1868         netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1869 #endif
1870
1871         if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1872             ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1873                 lp->options |= PCNET32_PORT_FD;
1874
1875         if (!a) {
1876                 if (pcnet32_debug & NETIF_MSG_PROBE)
1877                         printk(KERN_ERR PFX "No access methods\n");
1878                 ret = -ENODEV;
1879                 goto err_free_consistent;
1880         }
1881         lp->a = *a;
1882
1883         /* prior to register_netdev, dev->name is not yet correct */
1884         if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1885                 ret = -ENOMEM;
1886                 goto err_free_ring;
1887         }
1888         /* detect special T1/E1 WAN card by checking for MAC address */
1889         if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1890             && dev->dev_addr[2] == 0x75)
1891                 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1892
1893         lp->init_block->mode = cpu_to_le16(0x0003);     /* Disable Rx and Tx. */
1894         lp->init_block->tlen_rlen =
1895             cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
1896         for (i = 0; i < 6; i++)
1897                 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1898         lp->init_block->filter[0] = 0x00000000;
1899         lp->init_block->filter[1] = 0x00000000;
1900         lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1901         lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
1902
1903         /* switch pcnet32 to 32bit mode */
1904         a->write_bcr(ioaddr, 20, 2);
1905
1906         a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1907         a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
1908
1909         if (pdev) {             /* use the IRQ provided by PCI */
1910                 dev->irq = pdev->irq;
1911                 if (pcnet32_debug & NETIF_MSG_PROBE)
1912                         printk(" assigned IRQ %d.\n", dev->irq);
1913         } else {
1914                 unsigned long irq_mask = probe_irq_on();
1915
1916                 /*
1917                  * To auto-IRQ we enable the initialization-done and DMA error
1918                  * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1919                  * boards will work.
1920                  */
1921                 /* Trigger an initialization just for the interrupt. */
1922                 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1923                 mdelay(1);
1924
1925                 dev->irq = probe_irq_off(irq_mask);
1926                 if (!dev->irq) {
1927                         if (pcnet32_debug & NETIF_MSG_PROBE)
1928                                 printk(", failed to detect IRQ line.\n");
1929                         ret = -ENODEV;
1930                         goto err_free_ring;
1931                 }
1932                 if (pcnet32_debug & NETIF_MSG_PROBE)
1933                         printk(", probed IRQ %d.\n", dev->irq);
1934         }
1935
1936         /* Set the mii phy_id so that we can query the link state */
1937         if (lp->mii) {
1938                 /* lp->phycount and lp->phymask are set to 0 by memset above */
1939
1940                 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1941                 /* scan for PHYs */
1942                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1943                         unsigned short id1, id2;
1944
1945                         id1 = mdio_read(dev, i, MII_PHYSID1);
1946                         if (id1 == 0xffff)
1947                                 continue;
1948                         id2 = mdio_read(dev, i, MII_PHYSID2);
1949                         if (id2 == 0xffff)
1950                                 continue;
1951                         if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1952                                 continue;       /* 79C971 & 79C972 have phantom phy at id 31 */
1953                         lp->phycount++;
1954                         lp->phymask |= (1 << i);
1955                         lp->mii_if.phy_id = i;
1956                         if (pcnet32_debug & NETIF_MSG_PROBE)
1957                                 printk(KERN_INFO PFX
1958                                        "Found PHY %04x:%04x at address %d.\n",
1959                                        id1, id2, i);
1960                 }
1961                 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1962                 if (lp->phycount > 1) {
1963                         lp->options |= PCNET32_PORT_MII;
1964                 }
1965         }
1966
1967         init_timer(&lp->watchdog_timer);
1968         lp->watchdog_timer.data = (unsigned long)dev;
1969         lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1970
1971         /* The PCNET32-specific entries in the device structure. */
1972         dev->open = &pcnet32_open;
1973         dev->hard_start_xmit = &pcnet32_start_xmit;
1974         dev->stop = &pcnet32_close;
1975         dev->get_stats = &pcnet32_get_stats;
1976         dev->set_multicast_list = &pcnet32_set_multicast_list;
1977         dev->do_ioctl = &pcnet32_ioctl;
1978         dev->ethtool_ops = &pcnet32_ethtool_ops;
1979         dev->tx_timeout = pcnet32_tx_timeout;
1980         dev->watchdog_timeo = (5 * HZ);
1981
1982 #ifdef CONFIG_NET_POLL_CONTROLLER
1983         dev->poll_controller = pcnet32_poll_controller;
1984 #endif
1985
1986         /* Fill in the generic fields of the device structure. */
1987         if (register_netdev(dev))
1988                 goto err_free_ring;
1989
1990         if (pdev) {
1991                 pci_set_drvdata(pdev, dev);
1992         } else {
1993                 lp->next = pcnet32_dev;
1994                 pcnet32_dev = dev;
1995         }
1996
1997         if (pcnet32_debug & NETIF_MSG_PROBE)
1998                 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1999         cards_found++;
2000
2001         /* enable LED writes */
2002         a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
2003
2004         return 0;
2005
2006       err_free_ring:
2007         pcnet32_free_ring(dev);
2008       err_free_consistent:
2009         pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2010                             lp->init_block, lp->init_dma_addr);
2011       err_free_netdev:
2012         free_netdev(dev);
2013       err_release_region:
2014         release_region(ioaddr, PCNET32_TOTAL_SIZE);
2015         return ret;
2016 }
2017
2018 /* if any allocation fails, caller must also call pcnet32_free_ring */
2019 static int pcnet32_alloc_ring(struct net_device *dev, char *name)
2020 {
2021         struct pcnet32_private *lp = netdev_priv(dev);
2022
2023         lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
2024                                            sizeof(struct pcnet32_tx_head) *
2025                                            lp->tx_ring_size,
2026                                            &lp->tx_ring_dma_addr);
2027         if (lp->tx_ring == NULL) {
2028                 if (netif_msg_drv(lp))
2029                         printk("\n" KERN_ERR PFX
2030                                "%s: Consistent memory allocation failed.\n",
2031                                name);
2032                 return -ENOMEM;
2033         }
2034
2035         lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
2036                                            sizeof(struct pcnet32_rx_head) *
2037                                            lp->rx_ring_size,
2038                                            &lp->rx_ring_dma_addr);
2039         if (lp->rx_ring == NULL) {
2040                 if (netif_msg_drv(lp))
2041                         printk("\n" KERN_ERR PFX
2042                                "%s: Consistent memory allocation failed.\n",
2043                                name);
2044                 return -ENOMEM;
2045         }
2046
2047         lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
2048                                   GFP_ATOMIC);
2049         if (!lp->tx_dma_addr) {
2050                 if (netif_msg_drv(lp))
2051                         printk("\n" KERN_ERR PFX
2052                                "%s: Memory allocation failed.\n", name);
2053                 return -ENOMEM;
2054         }
2055
2056         lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
2057                                   GFP_ATOMIC);
2058         if (!lp->rx_dma_addr) {
2059                 if (netif_msg_drv(lp))
2060                         printk("\n" KERN_ERR PFX
2061                                "%s: Memory allocation failed.\n", name);
2062                 return -ENOMEM;
2063         }
2064
2065         lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
2066                                 GFP_ATOMIC);
2067         if (!lp->tx_skbuff) {
2068                 if (netif_msg_drv(lp))
2069                         printk("\n" KERN_ERR PFX
2070                                "%s: Memory allocation failed.\n", name);
2071                 return -ENOMEM;
2072         }
2073
2074         lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
2075                                 GFP_ATOMIC);
2076         if (!lp->rx_skbuff) {
2077                 if (netif_msg_drv(lp))
2078                         printk("\n" KERN_ERR PFX
2079                                "%s: Memory allocation failed.\n", name);
2080                 return -ENOMEM;
2081         }
2082
2083         return 0;
2084 }
2085
2086 static void pcnet32_free_ring(struct net_device *dev)
2087 {
2088         struct pcnet32_private *lp = netdev_priv(dev);
2089
2090         kfree(lp->tx_skbuff);
2091         lp->tx_skbuff = NULL;
2092
2093         kfree(lp->rx_skbuff);
2094         lp->rx_skbuff = NULL;
2095
2096         kfree(lp->tx_dma_addr);
2097         lp->tx_dma_addr = NULL;
2098
2099         kfree(lp->rx_dma_addr);
2100         lp->rx_dma_addr = NULL;
2101
2102         if (lp->tx_ring) {
2103                 pci_free_consistent(lp->pci_dev,
2104                                     sizeof(struct pcnet32_tx_head) *
2105                                     lp->tx_ring_size, lp->tx_ring,
2106                                     lp->tx_ring_dma_addr);
2107                 lp->tx_ring = NULL;
2108         }
2109
2110         if (lp->rx_ring) {
2111                 pci_free_consistent(lp->pci_dev,
2112                                     sizeof(struct pcnet32_rx_head) *
2113                                     lp->rx_ring_size, lp->rx_ring,
2114                                     lp->rx_ring_dma_addr);
2115                 lp->rx_ring = NULL;
2116         }
2117 }
2118
2119 static int pcnet32_open(struct net_device *dev)
2120 {
2121         struct pcnet32_private *lp = netdev_priv(dev);
2122         unsigned long ioaddr = dev->base_addr;
2123         u16 val;
2124         int i;
2125         int rc;
2126         unsigned long flags;
2127
2128         if (request_irq(dev->irq, &pcnet32_interrupt,
2129                         lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2130                         (void *)dev)) {
2131                 return -EAGAIN;
2132         }
2133
2134         spin_lock_irqsave(&lp->lock, flags);
2135         /* Check for a valid station address */
2136         if (!is_valid_ether_addr(dev->dev_addr)) {
2137                 rc = -EINVAL;
2138                 goto err_free_irq;
2139         }
2140
2141         /* Reset the PCNET32 */
2142         lp->a.reset(ioaddr);
2143
2144         /* switch pcnet32 to 32bit mode */
2145         lp->a.write_bcr(ioaddr, 20, 2);
2146
2147         if (netif_msg_ifup(lp))
2148                 printk(KERN_DEBUG
2149                        "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2150                        dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
2151                        (u32) (lp->rx_ring_dma_addr),
2152                        (u32) (lp->init_dma_addr));
2153
2154         /* set/reset autoselect bit */
2155         val = lp->a.read_bcr(ioaddr, 2) & ~2;
2156         if (lp->options & PCNET32_PORT_ASEL)
2157                 val |= 2;
2158         lp->a.write_bcr(ioaddr, 2, val);
2159
2160         /* handle full duplex setting */
2161         if (lp->mii_if.full_duplex) {
2162                 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2163                 if (lp->options & PCNET32_PORT_FD) {
2164                         val |= 1;
2165                         if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2166                                 val |= 2;
2167                 } else if (lp->options & PCNET32_PORT_ASEL) {
2168                         /* workaround of xSeries250, turn on for 79C975 only */
2169                         if (lp->chip_version == 0x2627)
2170                                 val |= 3;
2171                 }
2172                 lp->a.write_bcr(ioaddr, 9, val);
2173         }
2174
2175         /* set/reset GPSI bit in test register */
2176         val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2177         if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2178                 val |= 0x10;
2179         lp->a.write_csr(ioaddr, 124, val);
2180
2181         /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2182         if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2183             (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2184              lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2185                 if (lp->options & PCNET32_PORT_ASEL) {
2186                         lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2187                         if (netif_msg_link(lp))
2188                                 printk(KERN_DEBUG
2189                                        "%s: Setting 100Mb-Full Duplex.\n",
2190                                        dev->name);
2191                 }
2192         }
2193         if (lp->phycount < 2) {
2194                 /*
2195                  * 24 Jun 2004 according AMD, in order to change the PHY,
2196                  * DANAS (or DISPM for 79C976) must be set; then select the speed,
2197                  * duplex, and/or enable auto negotiation, and clear DANAS
2198                  */
2199                 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2200                         lp->a.write_bcr(ioaddr, 32,
2201                                         lp->a.read_bcr(ioaddr, 32) | 0x0080);
2202                         /* disable Auto Negotiation, set 10Mpbs, HD */
2203                         val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2204                         if (lp->options & PCNET32_PORT_FD)
2205                                 val |= 0x10;
2206                         if (lp->options & PCNET32_PORT_100)
2207                                 val |= 0x08;
2208                         lp->a.write_bcr(ioaddr, 32, val);
2209                 } else {
2210                         if (lp->options & PCNET32_PORT_ASEL) {
2211                                 lp->a.write_bcr(ioaddr, 32,
2212                                                 lp->a.read_bcr(ioaddr,
2213                                                                32) | 0x0080);
2214                                 /* enable auto negotiate, setup, disable fd */
2215                                 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2216                                 val |= 0x20;
2217                                 lp->a.write_bcr(ioaddr, 32, val);
2218                         }
2219                 }
2220         } else {
2221                 int first_phy = -1;
2222                 u16 bmcr;
2223                 u32 bcr9;
2224                 struct ethtool_cmd ecmd;
2225
2226                 /*
2227                  * There is really no good other way to handle multiple PHYs
2228                  * other than turning off all automatics
2229                  */
2230                 val = lp->a.read_bcr(ioaddr, 2);
2231                 lp->a.write_bcr(ioaddr, 2, val & ~2);
2232                 val = lp->a.read_bcr(ioaddr, 32);
2233                 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7));   /* stop MII manager */
2234
2235                 if (!(lp->options & PCNET32_PORT_ASEL)) {
2236                         /* setup ecmd */
2237                         ecmd.port = PORT_MII;
2238                         ecmd.transceiver = XCVR_INTERNAL;
2239                         ecmd.autoneg = AUTONEG_DISABLE;
2240                         ecmd.speed =
2241                             lp->
2242                             options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2243                         bcr9 = lp->a.read_bcr(ioaddr, 9);
2244
2245                         if (lp->options & PCNET32_PORT_FD) {
2246                                 ecmd.duplex = DUPLEX_FULL;
2247                                 bcr9 |= (1 << 0);
2248                         } else {
2249                                 ecmd.duplex = DUPLEX_HALF;
2250                                 bcr9 |= ~(1 << 0);
2251                         }
2252                         lp->a.write_bcr(ioaddr, 9, bcr9);
2253                 }
2254
2255                 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2256                         if (lp->phymask & (1 << i)) {
2257                                 /* isolate all but the first PHY */
2258                                 bmcr = mdio_read(dev, i, MII_BMCR);
2259                                 if (first_phy == -1) {
2260                                         first_phy = i;
2261                                         mdio_write(dev, i, MII_BMCR,
2262                                                    bmcr & ~BMCR_ISOLATE);
2263                                 } else {
2264                                         mdio_write(dev, i, MII_BMCR,
2265                                                    bmcr | BMCR_ISOLATE);
2266                                 }
2267                                 /* use mii_ethtool_sset to setup PHY */
2268                                 lp->mii_if.phy_id = i;
2269                                 ecmd.phy_address = i;
2270                                 if (lp->options & PCNET32_PORT_ASEL) {
2271                                         mii_ethtool_gset(&lp->mii_if, &ecmd);
2272                                         ecmd.autoneg = AUTONEG_ENABLE;
2273                                 }
2274                                 mii_ethtool_sset(&lp->mii_if, &ecmd);
2275                         }
2276                 }
2277                 lp->mii_if.phy_id = first_phy;
2278                 if (netif_msg_link(lp))
2279                         printk(KERN_INFO "%s: Using PHY number %d.\n",
2280                                dev->name, first_phy);
2281         }
2282
2283 #ifdef DO_DXSUFLO
2284         if (lp->dxsuflo) {      /* Disable transmit stop on underflow */
2285                 val = lp->a.read_csr(ioaddr, CSR3);
2286                 val |= 0x40;
2287                 lp->a.write_csr(ioaddr, CSR3, val);
2288         }
2289 #endif
2290
2291         lp->init_block->mode =
2292             cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2293         pcnet32_load_multicast(dev);
2294
2295         if (pcnet32_init_ring(dev)) {
2296                 rc = -ENOMEM;
2297                 goto err_free_ring;
2298         }
2299
2300 #ifdef CONFIG_PCNET32_NAPI
2301         napi_enable(&lp->napi);
2302 #endif
2303
2304         /* Re-initialize the PCNET32, and start it when done. */
2305         lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2306         lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
2307
2308         lp->a.write_csr(ioaddr, CSR4, 0x0915);  /* auto tx pad */
2309         lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2310
2311         netif_start_queue(dev);
2312
2313         if (lp->chip_version >= PCNET32_79C970A) {
2314                 /* Print the link status and start the watchdog */
2315                 pcnet32_check_media(dev, 1);
2316                 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2317         }
2318
2319         i = 0;
2320         while (i++ < 100)
2321                 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2322                         break;
2323         /*
2324          * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2325          * reports that doing so triggers a bug in the '974.
2326          */
2327         lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
2328
2329         if (netif_msg_ifup(lp))
2330                 printk(KERN_DEBUG
2331                        "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2332                        dev->name, i,
2333                        (u32) (lp->init_dma_addr),
2334                        lp->a.read_csr(ioaddr, CSR0));
2335
2336         spin_unlock_irqrestore(&lp->lock, flags);
2337
2338         return 0;               /* Always succeed */
2339
2340       err_free_ring:
2341         /* free any allocated skbuffs */
2342         pcnet32_purge_rx_ring(dev);
2343
2344         /*
2345          * Switch back to 16bit mode to avoid problems with dumb
2346          * DOS packet driver after a warm reboot
2347          */
2348         lp->a.write_bcr(ioaddr, 20, 4);
2349
2350       err_free_irq:
2351         spin_unlock_irqrestore(&lp->lock, flags);
2352         free_irq(dev->irq, dev);
2353         return rc;
2354 }
2355
2356 /*
2357  * The LANCE has been halted for one reason or another (busmaster memory
2358  * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2359  * etc.).  Modern LANCE variants always reload their ring-buffer
2360  * configuration when restarted, so we must reinitialize our ring
2361  * context before restarting.  As part of this reinitialization,
2362  * find all packets still on the Tx ring and pretend that they had been
2363  * sent (in effect, drop the packets on the floor) - the higher-level
2364  * protocols will time out and retransmit.  It'd be better to shuffle
2365  * these skbs to a temp list and then actually re-Tx them after
2366  * restarting the chip, but I'm too lazy to do so right now.  dplatt@3do.com
2367  */
2368
2369 static void pcnet32_purge_tx_ring(struct net_device *dev)
2370 {
2371         struct pcnet32_private *lp = netdev_priv(dev);
2372         int i;
2373
2374         for (i = 0; i < lp->tx_ring_size; i++) {
2375                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2376                 wmb();          /* Make sure adapter sees owner change */
2377                 if (lp->tx_skbuff[i]) {
2378                         pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2379                                          lp->tx_skbuff[i]->len,
2380                                          PCI_DMA_TODEVICE);
2381                         dev_kfree_skb_any(lp->tx_skbuff[i]);
2382                 }
2383                 lp->tx_skbuff[i] = NULL;
2384                 lp->tx_dma_addr[i] = 0;
2385         }
2386 }
2387
2388 /* Initialize the PCNET32 Rx and Tx rings. */
2389 static int pcnet32_init_ring(struct net_device *dev)
2390 {
2391         struct pcnet32_private *lp = netdev_priv(dev);
2392         int i;
2393
2394         lp->tx_full = 0;
2395         lp->cur_rx = lp->cur_tx = 0;
2396         lp->dirty_rx = lp->dirty_tx = 0;
2397
2398         for (i = 0; i < lp->rx_ring_size; i++) {
2399                 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2400                 if (rx_skbuff == NULL) {
2401                         if (!
2402                             (rx_skbuff = lp->rx_skbuff[i] =
2403                              dev_alloc_skb(PKT_BUF_SKB))) {
2404                                 /* there is not much, we can do at this point */
2405                                 if (netif_msg_drv(lp))
2406                                         printk(KERN_ERR
2407                                                "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2408                                                dev->name);
2409                                 return -1;
2410                         }
2411                         skb_reserve(rx_skbuff, NET_IP_ALIGN);
2412                 }
2413
2414                 rmb();
2415                 if (lp->rx_dma_addr[i] == 0)
2416                         lp->rx_dma_addr[i] =
2417                             pci_map_single(lp->pci_dev, rx_skbuff->data,
2418                                            PKT_BUF_SIZE, PCI_DMA_FROMDEVICE);
2419                 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2420                 lp->rx_ring[i].buf_length = cpu_to_le16(NEG_BUF_SIZE);
2421                 wmb();          /* Make sure owner changes after all others are visible */
2422                 lp->rx_ring[i].status = cpu_to_le16(0x8000);
2423         }
2424         /* The Tx buffer address is filled in as needed, but we do need to clear
2425          * the upper ownership bit. */
2426         for (i = 0; i < lp->tx_ring_size; i++) {
2427                 lp->tx_ring[i].status = 0;      /* CPU owns buffer */
2428                 wmb();          /* Make sure adapter sees owner change */
2429                 lp->tx_ring[i].base = 0;
2430                 lp->tx_dma_addr[i] = 0;
2431         }
2432
2433         lp->init_block->tlen_rlen =
2434             cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
2435         for (i = 0; i < 6; i++)
2436                 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2437         lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2438         lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
2439         wmb();                  /* Make sure all changes are visible */
2440         return 0;
2441 }
2442
2443 /* the pcnet32 has been issued a stop or reset.  Wait for the stop bit
2444  * then flush the pending transmit operations, re-initialize the ring,
2445  * and tell the chip to initialize.
2446  */
2447 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2448 {
2449         struct pcnet32_private *lp = netdev_priv(dev);
2450         unsigned long ioaddr = dev->base_addr;
2451         int i;
2452
2453         /* wait for stop */
2454         for (i = 0; i < 100; i++)
2455                 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
2456                         break;
2457
2458         if (i >= 100 && netif_msg_drv(lp))
2459                 printk(KERN_ERR
2460                        "%s: pcnet32_restart timed out waiting for stop.\n",
2461                        dev->name);
2462
2463         pcnet32_purge_tx_ring(dev);
2464         if (pcnet32_init_ring(dev))
2465                 return;
2466
2467         /* ReInit Ring */
2468         lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2469         i = 0;
2470         while (i++ < 1000)
2471                 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2472                         break;
2473
2474         lp->a.write_csr(ioaddr, CSR0, csr0_bits);
2475 }
2476
2477 static void pcnet32_tx_timeout(struct net_device *dev)
2478 {
2479         struct pcnet32_private *lp = netdev_priv(dev);
2480         unsigned long ioaddr = dev->base_addr, flags;
2481
2482         spin_lock_irqsave(&lp->lock, flags);
2483         /* Transmitter timeout, serious problems. */
2484         if (pcnet32_debug & NETIF_MSG_DRV)
2485                 printk(KERN_ERR
2486                        "%s: transmit timed out, status %4.4x, resetting.\n",
2487                        dev->name, lp->a.read_csr(ioaddr, CSR0));
2488         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2489         dev->stats.tx_errors++;
2490         if (netif_msg_tx_err(lp)) {
2491                 int i;
2492                 printk(KERN_DEBUG
2493                        " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2494                        lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2495                        lp->cur_rx);
2496                 for (i = 0; i < lp->rx_ring_size; i++)
2497                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2498                                le32_to_cpu(lp->rx_ring[i].base),
2499                                (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2500                                0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2501                                le16_to_cpu(lp->rx_ring[i].status));
2502                 for (i = 0; i < lp->tx_ring_size; i++)
2503                         printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2504                                le32_to_cpu(lp->tx_ring[i].base),
2505                                (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2506                                le32_to_cpu(lp->tx_ring[i].misc),
2507                                le16_to_cpu(lp->tx_ring[i].status));
2508                 printk("\n");
2509         }
2510         pcnet32_restart(dev, CSR0_NORMAL);
2511
2512         dev->trans_start = jiffies;
2513         netif_wake_queue(dev);
2514
2515         spin_unlock_irqrestore(&lp->lock, flags);
2516 }
2517
2518 static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
2519 {
2520         struct pcnet32_private *lp = netdev_priv(dev);
2521         unsigned long ioaddr = dev->base_addr;
2522         u16 status;
2523         int entry;
2524         unsigned long flags;
2525
2526         spin_lock_irqsave(&lp->lock, flags);
2527
2528         if (netif_msg_tx_queued(lp)) {
2529                 printk(KERN_DEBUG
2530                        "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2531                        dev->name, lp->a.read_csr(ioaddr, CSR0));
2532         }
2533
2534         /* Default status -- will not enable Successful-TxDone
2535          * interrupt when that option is available to us.
2536          */
2537         status = 0x8300;
2538
2539         /* Fill in a Tx ring entry */
2540
2541         /* Mask to ring buffer boundary. */
2542         entry = lp->cur_tx & lp->tx_mod_mask;
2543
2544         /* Caution: the write order is important here, set the status
2545          * with the "ownership" bits last. */
2546
2547         lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
2548
2549         lp->tx_ring[entry].misc = 0x00000000;
2550
2551         lp->tx_skbuff[entry] = skb;
2552         lp->tx_dma_addr[entry] =
2553             pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2554         lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
2555         wmb();                  /* Make sure owner changes after all others are visible */
2556         lp->tx_ring[entry].status = cpu_to_le16(status);
2557
2558         lp->cur_tx++;
2559         dev->stats.tx_bytes += skb->len;
2560
2561         /* Trigger an immediate send poll. */
2562         lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2563
2564         dev->trans_start = jiffies;
2565
2566         if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2567                 lp->tx_full = 1;
2568                 netif_stop_queue(dev);
2569         }
2570         spin_unlock_irqrestore(&lp->lock, flags);
2571         return 0;
2572 }
2573
2574 /* The PCNET32 interrupt handler. */
2575 static irqreturn_t
2576 pcnet32_interrupt(int irq, void *dev_id)
2577 {
2578         struct net_device *dev = dev_id;
2579         struct pcnet32_private *lp;
2580         unsigned long ioaddr;
2581         u16 csr0;
2582         int boguscnt = max_interrupt_work;
2583
2584         ioaddr = dev->base_addr;
2585         lp = netdev_priv(dev);
2586
2587         spin_lock(&lp->lock);
2588
2589         csr0 = lp->a.read_csr(ioaddr, CSR0);
2590         while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2591                 if (csr0 == 0xffff) {
2592                         break;  /* PCMCIA remove happened */
2593                 }
2594                 /* Acknowledge all of the current interrupt sources ASAP. */
2595                 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2596
2597                 if (netif_msg_intr(lp))
2598                         printk(KERN_DEBUG
2599                                "%s: interrupt  csr0=%#2.2x new csr=%#2.2x.\n",
2600                                dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
2601
2602                 /* Log misc errors. */
2603                 if (csr0 & 0x4000)
2604                         dev->stats.tx_errors++; /* Tx babble. */
2605                 if (csr0 & 0x1000) {
2606                         /*
2607                          * This happens when our receive ring is full. This
2608                          * shouldn't be a problem as we will see normal rx
2609                          * interrupts for the frames in the receive ring.  But
2610                          * there are some PCI chipsets (I can reproduce this
2611                          * on SP3G with Intel saturn chipset) which have
2612                          * sometimes problems and will fill up the receive
2613                          * ring with error descriptors.  In this situation we
2614                          * don't get a rx interrupt, but a missed frame
2615                          * interrupt sooner or later.
2616                          */
2617                         dev->stats.rx_errors++; /* Missed a Rx frame. */
2618                 }
2619                 if (csr0 & 0x0800) {
2620                         if (netif_msg_drv(lp))
2621                                 printk(KERN_ERR
2622                                        "%s: Bus master arbitration failure, status %4.4x.\n",
2623                                        dev->name, csr0);
2624                         /* unlike for the lance, there is no restart needed */
2625                 }
2626 #ifdef CONFIG_PCNET32_NAPI
2627                 if (netif_rx_schedule_prep(dev, &lp->napi)) {
2628                         u16 val;
2629                         /* set interrupt masks */
2630                         val = lp->a.read_csr(ioaddr, CSR3);
2631                         val |= 0x5f00;
2632                         lp->a.write_csr(ioaddr, CSR3, val);
2633                         mmiowb();
2634                         __netif_rx_schedule(dev, &lp->napi);
2635                         break;
2636                 }
2637 #else
2638                 pcnet32_rx(dev, lp->napi.weight);
2639                 if (pcnet32_tx(dev)) {
2640                         /* reset the chip to clear the error condition, then restart */
2641                         lp->a.reset(ioaddr);
2642                         lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2643                         pcnet32_restart(dev, CSR0_START);
2644                         netif_wake_queue(dev);
2645                 }
2646 #endif
2647                 csr0 = lp->a.read_csr(ioaddr, CSR0);
2648         }
2649
2650 #ifndef CONFIG_PCNET32_NAPI
2651         /* Set interrupt enable. */
2652         lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
2653 #endif
2654
2655         if (netif_msg_intr(lp))
2656                 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
2657                        dev->name, lp->a.read_csr(ioaddr, CSR0));
2658
2659         spin_unlock(&lp->lock);
2660
2661         return IRQ_HANDLED;
2662 }
2663
2664 static int pcnet32_close(struct net_device *dev)
2665 {
2666         unsigned long ioaddr = dev->base_addr;
2667         struct pcnet32_private *lp = netdev_priv(dev);
2668         unsigned long flags;
2669
2670         del_timer_sync(&lp->watchdog_timer);
2671
2672         netif_stop_queue(dev);
2673 #ifdef CONFIG_PCNET32_NAPI
2674         napi_disable(&lp->napi);
2675 #endif
2676
2677         spin_lock_irqsave(&lp->lock, flags);
2678
2679         dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2680
2681         if (netif_msg_ifdown(lp))
2682                 printk(KERN_DEBUG
2683                        "%s: Shutting down ethercard, status was %2.2x.\n",
2684                        dev->name, lp->a.read_csr(ioaddr, CSR0));
2685
2686         /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2687         lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2688
2689         /*
2690          * Switch back to 16bit mode to avoid problems with dumb
2691          * DOS packet driver after a warm reboot
2692          */
2693         lp->a.write_bcr(ioaddr, 20, 4);
2694
2695         spin_unlock_irqrestore(&lp->lock, flags);
2696
2697         free_irq(dev->irq, dev);
2698
2699         spin_lock_irqsave(&lp->lock, flags);
2700
2701         pcnet32_purge_rx_ring(dev);
2702         pcnet32_purge_tx_ring(dev);
2703
2704         spin_unlock_irqrestore(&lp->lock, flags);
2705
2706         return 0;
2707 }
2708
2709 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2710 {
2711         struct pcnet32_private *lp = netdev_priv(dev);
2712         unsigned long ioaddr = dev->base_addr;
2713         unsigned long flags;
2714
2715         spin_lock_irqsave(&lp->lock, flags);
2716         dev->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2717         spin_unlock_irqrestore(&lp->lock, flags);
2718
2719         return &dev->stats;
2720 }
2721
2722 /* taken from the sunlance driver, which it took from the depca driver */
2723 static void pcnet32_load_multicast(struct net_device *dev)
2724 {
2725         struct pcnet32_private *lp = netdev_priv(dev);
2726         volatile struct pcnet32_init_block *ib = lp->init_block;
2727         volatile __le16 *mcast_table = (__le16 *)ib->filter;
2728         struct dev_mc_list *dmi = dev->mc_list;
2729         unsigned long ioaddr = dev->base_addr;
2730         char *addrs;
2731         int i;
2732         u32 crc;
2733
2734         /* set all multicast bits */
2735         if (dev->flags & IFF_ALLMULTI) {
2736                 ib->filter[0] = cpu_to_le32(~0U);
2737                 ib->filter[1] = cpu_to_le32(~0U);
2738                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2739                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2740                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2741                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2742                 return;
2743         }
2744         /* clear the multicast filter */
2745         ib->filter[0] = 0;
2746         ib->filter[1] = 0;
2747
2748         /* Add addresses */
2749         for (i = 0; i < dev->mc_count; i++) {
2750                 addrs = dmi->dmi_addr;
2751                 dmi = dmi->next;
2752
2753                 /* multicast address? */
2754                 if (!(*addrs & 1))
2755                         continue;
2756
2757                 crc = ether_crc_le(6, addrs);
2758                 crc = crc >> 26;
2759                 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
2760         }
2761         for (i = 0; i < 4; i++)
2762                 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2763                                 le16_to_cpu(mcast_table[i]));
2764         return;
2765 }
2766
2767 /*
2768  * Set or clear the multicast filter for this adaptor.
2769  */
2770 static void pcnet32_set_multicast_list(struct net_device *dev)
2771 {
2772         unsigned long ioaddr = dev->base_addr, flags;
2773         struct pcnet32_private *lp = netdev_priv(dev);
2774         int csr15, suspended;
2775
2776         spin_lock_irqsave(&lp->lock, flags);
2777         suspended = pcnet32_suspend(dev, &flags, 0);
2778         csr15 = lp->a.read_csr(ioaddr, CSR15);
2779         if (dev->flags & IFF_PROMISC) {
2780                 /* Log any net taps. */
2781                 if (netif_msg_hw(lp))
2782                         printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2783                                dev->name);
2784                 lp->init_block->mode =
2785                     cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2786                                 7);
2787                 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
2788         } else {
2789                 lp->init_block->mode =
2790                     cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2791                 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2792                 pcnet32_load_multicast(dev);
2793         }
2794
2795         if (suspended) {
2796                 int csr5;
2797                 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2798                 csr5 = lp->a.read_csr(ioaddr, CSR5);
2799                 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2800         } else {
2801                 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2802                 pcnet32_restart(dev, CSR0_NORMAL);
2803                 netif_wake_queue(dev);
2804         }
2805
2806         spin_unlock_irqrestore(&lp->lock, flags);
2807 }
2808
2809 /* This routine assumes that the lp->lock is held */
2810 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2811 {
2812         struct pcnet32_private *lp = netdev_priv(dev);
2813         unsigned long ioaddr = dev->base_addr;
2814         u16 val_out;
2815
2816         if (!lp->mii)
2817                 return 0;
2818
2819         lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2820         val_out = lp->a.read_bcr(ioaddr, 34);
2821
2822         return val_out;
2823 }
2824
2825 /* This routine assumes that the lp->lock is held */
2826 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2827 {
2828         struct pcnet32_private *lp = netdev_priv(dev);
2829         unsigned long ioaddr = dev->base_addr;
2830
2831         if (!lp->mii)
2832                 return;
2833
2834         lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2835         lp->a.write_bcr(ioaddr, 34, val);
2836 }
2837
2838 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2839 {
2840         struct pcnet32_private *lp = netdev_priv(dev);
2841         int rc;
2842         unsigned long flags;
2843
2844         /* SIOC[GS]MIIxxx ioctls */
2845         if (lp->mii) {
2846                 spin_lock_irqsave(&lp->lock, flags);
2847                 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2848                 spin_unlock_irqrestore(&lp->lock, flags);
2849         } else {
2850                 rc = -EOPNOTSUPP;
2851         }
2852
2853         return rc;
2854 }
2855
2856 static int pcnet32_check_otherphy(struct net_device *dev)
2857 {
2858         struct pcnet32_private *lp = netdev_priv(dev);
2859         struct mii_if_info mii = lp->mii_if;
2860         u16 bmcr;
2861         int i;
2862
2863         for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2864                 if (i == lp->mii_if.phy_id)
2865                         continue;       /* skip active phy */
2866                 if (lp->phymask & (1 << i)) {
2867                         mii.phy_id = i;
2868                         if (mii_link_ok(&mii)) {
2869                                 /* found PHY with active link */
2870                                 if (netif_msg_link(lp))
2871                                         printk(KERN_INFO
2872                                                "%s: Using PHY number %d.\n",
2873                                                dev->name, i);
2874
2875                                 /* isolate inactive phy */
2876                                 bmcr =
2877                                     mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2878                                 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2879                                            bmcr | BMCR_ISOLATE);
2880
2881                                 /* de-isolate new phy */
2882                                 bmcr = mdio_read(dev, i, MII_BMCR);
2883                                 mdio_write(dev, i, MII_BMCR,
2884                                            bmcr & ~BMCR_ISOLATE);
2885
2886                                 /* set new phy address */
2887                                 lp->mii_if.phy_id = i;
2888                                 return 1;
2889                         }
2890                 }
2891         }
2892         return 0;
2893 }
2894
2895 /*
2896  * Show the status of the media.  Similar to mii_check_media however it
2897  * correctly shows the link speed for all (tested) pcnet32 variants.
2898  * Devices with no mii just report link state without speed.
2899  *
2900  * Caller is assumed to hold and release the lp->lock.
2901  */
2902
2903 static void pcnet32_check_media(struct net_device *dev, int verbose)
2904 {
2905         struct pcnet32_private *lp = netdev_priv(dev);
2906         int curr_link;
2907         int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2908         u32 bcr9;
2909
2910         if (lp->mii) {
2911                 curr_link = mii_link_ok(&lp->mii_if);
2912         } else {
2913                 ulong ioaddr = dev->base_addr;  /* card base I/O address */
2914                 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2915         }
2916         if (!curr_link) {
2917                 if (prev_link || verbose) {
2918                         netif_carrier_off(dev);
2919                         if (netif_msg_link(lp))
2920                                 printk(KERN_INFO "%s: link down\n", dev->name);
2921                 }
2922                 if (lp->phycount > 1) {
2923                         curr_link = pcnet32_check_otherphy(dev);
2924                         prev_link = 0;
2925                 }
2926         } else if (verbose || !prev_link) {
2927                 netif_carrier_on(dev);
2928                 if (lp->mii) {
2929                         if (netif_msg_link(lp)) {
2930                                 struct ethtool_cmd ecmd;
2931                                 mii_ethtool_gset(&lp->mii_if, &ecmd);
2932                                 printk(KERN_INFO
2933                                        "%s: link up, %sMbps, %s-duplex\n",
2934                                        dev->name,
2935                                        (ecmd.speed == SPEED_100) ? "100" : "10",
2936                                        (ecmd.duplex ==
2937                                         DUPLEX_FULL) ? "full" : "half");
2938                         }
2939                         bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2940                         if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2941                                 if (lp->mii_if.full_duplex)
2942                                         bcr9 |= (1 << 0);
2943                                 else
2944                                         bcr9 &= ~(1 << 0);
2945                                 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2946                         }
2947                 } else {
2948                         if (netif_msg_link(lp))
2949                                 printk(KERN_INFO "%s: link up\n", dev->name);
2950                 }
2951         }
2952 }
2953
2954 /*
2955  * Check for loss of link and link establishment.
2956  * Can not use mii_check_media because it does nothing if mode is forced.
2957  */
2958
2959 static void pcnet32_watchdog(struct net_device *dev)
2960 {
2961         struct pcnet32_private *lp = netdev_priv(dev);
2962         unsigned long flags;
2963
2964         /* Print the link status if it has changed */
2965         spin_lock_irqsave(&lp->lock, flags);
2966         pcnet32_check_media(dev, 0);
2967         spin_unlock_irqrestore(&lp->lock, flags);
2968
2969         mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2970 }
2971
2972 static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2973 {
2974         struct net_device *dev = pci_get_drvdata(pdev);
2975
2976         if (netif_running(dev)) {
2977                 netif_device_detach(dev);
2978                 pcnet32_close(dev);
2979         }
2980         pci_save_state(pdev);
2981         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2982         return 0;
2983 }
2984
2985 static int pcnet32_pm_resume(struct pci_dev *pdev)
2986 {
2987         struct net_device *dev = pci_get_drvdata(pdev);
2988
2989         pci_set_power_state(pdev, PCI_D0);
2990         pci_restore_state(pdev);
2991
2992         if (netif_running(dev)) {
2993                 pcnet32_open(dev);
2994                 netif_device_attach(dev);
2995         }
2996         return 0;
2997 }
2998
2999 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
3000 {
3001         struct net_device *dev = pci_get_drvdata(pdev);
3002
3003         if (dev) {
3004                 struct pcnet32_private *lp = netdev_priv(dev);
3005
3006                 unregister_netdev(dev);
3007                 pcnet32_free_ring(dev);
3008                 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
3009                 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
3010                                     lp->init_block, lp->init_dma_addr);
3011                 free_netdev(dev);
3012                 pci_disable_device(pdev);
3013                 pci_set_drvdata(pdev, NULL);
3014         }
3015 }
3016
3017 static struct pci_driver pcnet32_driver = {
3018         .name = DRV_NAME,
3019         .probe = pcnet32_probe_pci,
3020         .remove = __devexit_p(pcnet32_remove_one),
3021         .id_table = pcnet32_pci_tbl,
3022         .suspend = pcnet32_pm_suspend,
3023         .resume = pcnet32_pm_resume,
3024 };
3025
3026 /* An additional parameter that may be passed in... */
3027 static int debug = -1;
3028 static int tx_start_pt = -1;
3029 static int pcnet32_have_pci;
3030
3031 module_param(debug, int, 0);
3032 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
3033 module_param(max_interrupt_work, int, 0);
3034 MODULE_PARM_DESC(max_interrupt_work,
3035                  DRV_NAME " maximum events handled per interrupt");
3036 module_param(rx_copybreak, int, 0);
3037 MODULE_PARM_DESC(rx_copybreak,
3038                  DRV_NAME " copy breakpoint for copy-only-tiny-frames");
3039 module_param(tx_start_pt, int, 0);
3040 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
3041 module_param(pcnet32vlb, int, 0);
3042 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
3043 module_param_array(options, int, NULL, 0);
3044 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
3045 module_param_array(full_duplex, int, NULL, 0);
3046 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
3047 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
3048 module_param_array(homepna, int, NULL, 0);
3049 MODULE_PARM_DESC(homepna,
3050                  DRV_NAME
3051                  " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
3052
3053 MODULE_AUTHOR("Thomas Bogendoerfer");
3054 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3055 MODULE_LICENSE("GPL");
3056
3057 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3058
3059 static int __init pcnet32_init_module(void)
3060 {
3061         printk(KERN_INFO "%s", version);
3062
3063         pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
3064
3065         if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3066                 tx_start = tx_start_pt;
3067
3068         /* find the PCI devices */
3069         if (!pci_register_driver(&pcnet32_driver))
3070                 pcnet32_have_pci = 1;
3071
3072         /* should we find any remaining VLbus devices ? */
3073         if (pcnet32vlb)
3074                 pcnet32_probe_vlbus(pcnet32_portlist);
3075
3076         if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3077                 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
3078
3079         return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
3080 }
3081
3082 static void __exit pcnet32_cleanup_module(void)
3083 {
3084         struct net_device *next_dev;
3085
3086         while (pcnet32_dev) {
3087                 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
3088                 next_dev = lp->next;
3089                 unregister_netdev(pcnet32_dev);
3090                 pcnet32_free_ring(pcnet32_dev);
3091                 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
3092                 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
3093                                     lp->init_block, lp->init_dma_addr);
3094                 free_netdev(pcnet32_dev);
3095                 pcnet32_dev = next_dev;
3096         }
3097
3098         if (pcnet32_have_pci)
3099                 pci_unregister_driver(&pcnet32_driver);
3100 }
3101
3102 module_init(pcnet32_init_module);
3103 module_exit(pcnet32_cleanup_module);
3104
3105 /*
3106  * Local variables:
3107  *  c-indent-level: 4
3108  *  tab-width: 8
3109  * End:
3110  */