2 * Copyright (C) 2003 - 2006 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
30 * Source file for NIC routines to access the Phantom hardware
34 #include "netxen_nic.h"
35 #include "netxen_nic_hw.h"
36 #include "netxen_nic_phan_reg.h"
41 #define MASK(n) ((1ULL<<(n))-1)
42 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
43 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
44 #define MS_WIN(addr) (addr & 0x0ffc0000)
46 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
48 #define CRB_BLK(off) ((off >> 20) & 0x3f)
49 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
50 #define CRB_WINDOW_2M (0x130060)
51 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
52 #define CRB_INDIRECT_2M (0x1e0000UL)
54 #define CRB_WIN_LOCK_TIMEOUT 100000000
55 static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
56 {{{0, 0, 0, 0} } }, /* 0: PCI */
57 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
58 {1, 0x0110000, 0x0120000, 0x130000},
59 {1, 0x0120000, 0x0122000, 0x124000},
60 {1, 0x0130000, 0x0132000, 0x126000},
61 {1, 0x0140000, 0x0142000, 0x128000},
62 {1, 0x0150000, 0x0152000, 0x12a000},
63 {1, 0x0160000, 0x0170000, 0x110000},
64 {1, 0x0170000, 0x0172000, 0x12e000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {1, 0x01e0000, 0x01e0800, 0x122000},
72 {0, 0x0000000, 0x0000000, 0x000000} } },
73 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
74 {{{0, 0, 0, 0} } }, /* 3: */
75 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
76 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
77 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
78 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
79 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {1, 0x08f0000, 0x08f2000, 0x172000} } },
95 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {1, 0x09f0000, 0x09f2000, 0x176000} } },
111 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
127 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
143 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
144 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
145 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
146 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
147 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
148 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
149 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
150 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
151 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
152 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
153 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
154 {{{0, 0, 0, 0} } }, /* 23: */
155 {{{0, 0, 0, 0} } }, /* 24: */
156 {{{0, 0, 0, 0} } }, /* 25: */
157 {{{0, 0, 0, 0} } }, /* 26: */
158 {{{0, 0, 0, 0} } }, /* 27: */
159 {{{0, 0, 0, 0} } }, /* 28: */
160 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
161 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
162 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
163 {{{0} } }, /* 32: PCI */
164 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
165 {1, 0x2110000, 0x2120000, 0x130000},
166 {1, 0x2120000, 0x2122000, 0x124000},
167 {1, 0x2130000, 0x2132000, 0x126000},
168 {1, 0x2140000, 0x2142000, 0x128000},
169 {1, 0x2150000, 0x2152000, 0x12a000},
170 {1, 0x2160000, 0x2170000, 0x110000},
171 {1, 0x2170000, 0x2172000, 0x12e000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000} } },
180 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
186 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
187 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
188 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
189 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
190 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
191 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
192 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
193 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
194 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
195 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
196 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
197 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
199 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
200 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
201 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
202 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
203 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
204 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
205 {{{0} } }, /* 59: I2C0 */
206 {{{0} } }, /* 60: I2C1 */
207 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
208 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
209 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
213 * top 12 bits of crb internal address (hub, agent)
215 static unsigned crb_hub_agt[64] =
218 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
219 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
220 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
222 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
223 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
224 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
225 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
226 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
227 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
228 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
229 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
230 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
231 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
232 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
233 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
234 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
235 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
236 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
237 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
238 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
239 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
240 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
241 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
242 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
243 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
245 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
246 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
248 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
250 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
251 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
257 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
259 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
260 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
261 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
262 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
263 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
264 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
265 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
266 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
267 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
268 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
270 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
272 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
273 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
275 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
276 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
277 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
283 struct netxen_recv_crb recv_crb_registers[] = {
288 /* crb_rcv_producer: */
290 NETXEN_NIC_REG(0x100),
292 NETXEN_NIC_REG(0x110),
294 NETXEN_NIC_REG(0x120)
296 /* crb_sts_consumer: */
297 NETXEN_NIC_REG(0x138),
303 /* crb_rcv_producer: */
305 NETXEN_NIC_REG(0x144),
307 NETXEN_NIC_REG(0x154),
309 NETXEN_NIC_REG(0x164)
311 /* crb_sts_consumer: */
312 NETXEN_NIC_REG(0x17c),
318 /* crb_rcv_producer: */
320 NETXEN_NIC_REG(0x1d8),
322 NETXEN_NIC_REG(0x1f8),
324 NETXEN_NIC_REG(0x208)
326 /* crb_sts_consumer: */
327 NETXEN_NIC_REG(0x220),
333 /* crb_rcv_producer: */
335 NETXEN_NIC_REG(0x22c),
337 NETXEN_NIC_REG(0x23c),
339 NETXEN_NIC_REG(0x24c)
341 /* crb_sts_consumer: */
342 NETXEN_NIC_REG(0x264),
346 static u64 ctx_addr_sig_regs[][3] = {
347 {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
348 {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
349 {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
350 {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
352 #define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0])
353 #define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2])
354 #define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1])
357 /* PCI Windowing for DDR regions. */
359 #define ADDR_IN_RANGE(addr, low, high) \
360 (((addr) <= (high)) && ((addr) >= (low)))
362 #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
363 #define NETXEN_MIN_MTU 64
364 #define NETXEN_ETH_FCS_SIZE 4
365 #define NETXEN_ENET_HEADER_SIZE 14
366 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
367 #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
368 #define NETXEN_NIU_HDRSIZE (0x1 << 6)
369 #define NETXEN_NIU_TLRSIZE (0x1 << 5)
371 #define lower32(x) ((u32)((x) & 0xffffffff))
373 ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff))
375 #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
376 #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
377 #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
378 #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
380 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
382 int netxen_nic_set_mac(struct net_device *netdev, void *p)
384 struct netxen_adapter *adapter = netdev_priv(netdev);
385 struct sockaddr *addr = p;
387 if (netif_running(netdev))
390 if (!is_valid_ether_addr(addr->sa_data))
391 return -EADDRNOTAVAIL;
393 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
395 if (adapter->macaddr_set)
396 adapter->macaddr_set(adapter, addr->sa_data);
401 #define NETXEN_UNICAST_ADDR(port, index) \
402 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
403 #define NETXEN_MCAST_ADDR(port, index) \
404 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
405 #define MAC_HI(addr) \
406 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
407 #define MAC_LO(addr) \
408 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
411 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
414 u16 port = adapter->physical_port;
415 u8 *addr = adapter->netdev->dev_addr;
417 if (adapter->mc_enabled)
420 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
421 val |= (1UL << (28+port));
422 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
424 /* add broadcast addr to filter */
426 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
427 netxen_crb_writelit_adapter(adapter,
428 NETXEN_UNICAST_ADDR(port, 0)+4, val);
430 /* add station addr to filter */
432 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
434 netxen_crb_writelit_adapter(adapter,
435 NETXEN_UNICAST_ADDR(port, 1)+4, val);
437 adapter->mc_enabled = 1;
442 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
445 u16 port = adapter->physical_port;
446 u8 *addr = adapter->netdev->dev_addr;
448 if (!adapter->mc_enabled)
451 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
452 val &= ~(1UL << (28+port));
453 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
456 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
458 netxen_crb_writelit_adapter(adapter,
459 NETXEN_UNICAST_ADDR(port, 0)+4, val);
461 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
462 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
464 adapter->mc_enabled = 0;
469 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
473 u16 port = adapter->physical_port;
478 netxen_crb_writelit_adapter(adapter,
479 NETXEN_MCAST_ADDR(port, index), hi);
480 netxen_crb_writelit_adapter(adapter,
481 NETXEN_MCAST_ADDR(port, index)+4, lo);
487 * netxen_nic_set_multi - Multicast
489 void netxen_nic_set_multi(struct net_device *netdev)
491 struct netxen_adapter *adapter = netdev_priv(netdev);
492 struct dev_mc_list *mc_ptr;
496 memset(null_addr, 0, 6);
498 if (netdev->flags & IFF_PROMISC) {
500 adapter->set_promisc(adapter,
501 NETXEN_NIU_PROMISC_MODE);
503 /* Full promiscuous mode */
504 netxen_nic_disable_mcast_filter(adapter);
509 if (netdev->mc_count == 0) {
510 adapter->set_promisc(adapter,
511 NETXEN_NIU_NON_PROMISC_MODE);
512 netxen_nic_disable_mcast_filter(adapter);
516 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
517 if (netdev->flags & IFF_ALLMULTI ||
518 netdev->mc_count > adapter->max_mc_count) {
519 netxen_nic_disable_mcast_filter(adapter);
523 netxen_nic_enable_mcast_filter(adapter);
525 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
526 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
528 if (index != netdev->mc_count)
529 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
530 netxen_nic_driver_name, netdev->name);
532 /* Clear out remaining addresses */
533 for (; index < adapter->max_mc_count; index++)
534 netxen_nic_set_mcast_addr(adapter, index, null_addr);
538 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
539 * @returns 0 on success, negative on failure
541 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
543 struct netxen_adapter *adapter = netdev_priv(netdev);
544 int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
546 if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
547 printk(KERN_ERR "%s: %s %d is not supported.\n",
548 netxen_nic_driver_name, netdev->name, mtu);
552 if (adapter->set_mtu)
553 adapter->set_mtu(adapter, mtu);
560 * check if the firmware has been downloaded and ready to run and
561 * setup the address for the descriptors in the adapter
563 int netxen_alloc_hw_resources(struct netxen_adapter *adapter)
565 struct netxen_hardware_context *hw = &adapter->ahw;
570 struct netxen_recv_context *recv_ctx;
571 struct netxen_rcv_desc_ctx *rcv_desc;
572 int func_id = adapter->portnum;
574 err = netxen_receive_peg_ready(adapter);
576 printk(KERN_ERR "Rcv Peg initialization not complete:%x.\n",
580 adapter->intr_scheme = adapter->pci_read_normalize(adapter,
581 CRB_NIC_CAPABILITIES_FW);
582 adapter->msi_mode = adapter->pci_read_normalize(adapter,
583 CRB_NIC_MSI_MODE_FW);
585 addr = pci_alloc_consistent(adapter->pdev,
586 sizeof(struct netxen_ring_ctx) + sizeof(uint32_t),
587 &adapter->ctx_desc_phys_addr);
590 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
594 memset(addr, 0, sizeof(struct netxen_ring_ctx));
595 adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
596 adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum);
597 adapter->ctx_desc->cmd_consumer_offset =
598 cpu_to_le64(adapter->ctx_desc_phys_addr +
599 sizeof(struct netxen_ring_ctx));
600 adapter->cmd_consumer = (__le32 *) (((char *)addr) +
601 sizeof(struct netxen_ring_ctx));
603 addr = pci_alloc_consistent(adapter->pdev,
604 sizeof(struct cmd_desc_type0) *
605 adapter->max_tx_desc_count,
606 &hw->cmd_desc_phys_addr);
609 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
610 netxen_free_hw_resources(adapter);
614 adapter->ctx_desc->cmd_ring_addr =
615 cpu_to_le64(hw->cmd_desc_phys_addr);
616 adapter->ctx_desc->cmd_ring_size =
617 cpu_to_le32(adapter->max_tx_desc_count);
619 hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
621 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
622 recv_ctx = &adapter->recv_ctx[ctx];
624 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
625 rcv_desc = &recv_ctx->rcv_desc[ring];
626 addr = pci_alloc_consistent(adapter->pdev,
628 &rcv_desc->phys_addr);
630 DPRINTK(ERR, "bad return from "
631 "pci_alloc_consistent\n");
632 netxen_free_hw_resources(adapter);
636 rcv_desc->desc_head = (struct rcv_desc *)addr;
637 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr =
638 cpu_to_le64(rcv_desc->phys_addr);
639 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
640 cpu_to_le32(rcv_desc->max_rx_desc_count);
641 rcv_desc->crb_rcv_producer =
642 recv_crb_registers[adapter->portnum].
643 crb_rcv_producer[ring];
646 addr = pci_alloc_consistent(adapter->pdev, STATUS_DESC_RINGSIZE,
647 &recv_ctx->rcv_status_desc_phys_addr);
649 DPRINTK(ERR, "bad return from"
650 " pci_alloc_consistent\n");
651 netxen_free_hw_resources(adapter);
655 recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
656 adapter->ctx_desc->sts_ring_addr =
657 cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
658 adapter->ctx_desc->sts_ring_size =
659 cpu_to_le32(adapter->max_rx_desc_count);
660 recv_ctx->crb_sts_consumer =
661 recv_crb_registers[adapter->portnum].crb_sts_consumer;
666 adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_LO(func_id),
667 lower32(adapter->ctx_desc_phys_addr));
668 adapter->pci_write_normalize(adapter, CRB_CTX_ADDR_REG_HI(func_id),
669 upper32(adapter->ctx_desc_phys_addr));
670 adapter->pci_write_normalize(adapter, CRB_CTX_SIGNATURE_REG(func_id),
671 NETXEN_CTX_SIGNATURE | func_id);
675 void netxen_free_hw_resources(struct netxen_adapter *adapter)
677 struct netxen_recv_context *recv_ctx;
678 struct netxen_rcv_desc_ctx *rcv_desc;
681 if (adapter->ctx_desc != NULL) {
682 pci_free_consistent(adapter->pdev,
683 sizeof(struct netxen_ring_ctx) +
686 adapter->ctx_desc_phys_addr);
687 adapter->ctx_desc = NULL;
690 if (adapter->ahw.cmd_desc_head != NULL) {
691 pci_free_consistent(adapter->pdev,
692 sizeof(struct cmd_desc_type0) *
693 adapter->max_tx_desc_count,
694 adapter->ahw.cmd_desc_head,
695 adapter->ahw.cmd_desc_phys_addr);
696 adapter->ahw.cmd_desc_head = NULL;
699 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
700 recv_ctx = &adapter->recv_ctx[ctx];
701 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
702 rcv_desc = &recv_ctx->rcv_desc[ring];
704 if (rcv_desc->desc_head != NULL) {
705 pci_free_consistent(adapter->pdev,
708 rcv_desc->phys_addr);
709 rcv_desc->desc_head = NULL;
713 if (recv_ctx->rcv_status_desc_head != NULL) {
714 pci_free_consistent(adapter->pdev,
715 STATUS_DESC_RINGSIZE,
716 recv_ctx->rcv_status_desc_head,
718 rcv_status_desc_phys_addr);
719 recv_ctx->rcv_status_desc_head = NULL;
724 void netxen_tso_check(struct netxen_adapter *adapter,
725 struct cmd_desc_type0 *desc, struct sk_buff *skb)
728 desc->total_hdr_length = (sizeof(struct ethhdr) +
729 ip_hdrlen(skb) + tcp_hdrlen(skb));
730 netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO);
731 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
732 if (ip_hdr(skb)->protocol == IPPROTO_TCP) {
733 netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT);
734 } else if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
735 netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT);
740 desc->tcp_hdr_offset = skb_transport_offset(skb);
741 desc->ip_hdr_offset = skb_network_offset(skb);
744 int netxen_is_flash_supported(struct netxen_adapter *adapter)
746 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
747 int addr, val01, val02, i, j;
749 /* if the flash size less than 4Mb, make huge war cry and die */
750 for (j = 1; j < 4; j++) {
751 addr = j * NETXEN_NIC_WINDOW_MARGIN;
752 for (i = 0; i < ARRAY_SIZE(locs); i++) {
753 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
754 && netxen_rom_fast_read(adapter, (addr + locs[i]),
766 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
767 int size, __le32 * buf)
775 for (i = 0; i < size / sizeof(u32); i++) {
776 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
778 *ptr32 = cpu_to_le32(v);
782 if ((char *)buf + size > (char *)ptr32) {
784 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
786 local = cpu_to_le32(v);
787 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
793 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[])
795 __le32 *pmac = (__le32 *) & mac[0];
797 if (netxen_get_flash_block(adapter,
799 offsetof(struct netxen_new_user_info,
801 FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
804 if (*mac == cpu_to_le64(~0ULL)) {
805 if (netxen_get_flash_block(adapter,
806 NETXEN_USER_START_OLD +
807 offsetof(struct netxen_user_old_info,
809 FLASH_NUM_PORTS * sizeof(u64),
812 if (*mac == cpu_to_le64(~0ULL))
818 #define CRB_WIN_LOCK_TIMEOUT 100000000
820 static int crb_win_lock(struct netxen_adapter *adapter)
822 int done = 0, timeout = 0;
825 /* acquire semaphore3 from PCI HW block */
826 adapter->hw_read_wx(adapter,
827 NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4);
830 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
835 netxen_crb_writelit_adapter(adapter,
836 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
840 static void crb_win_unlock(struct netxen_adapter *adapter)
844 adapter->hw_read_wx(adapter,
845 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4);
849 * Changes the CRB window to the specified window.
852 netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
854 void __iomem *offset;
857 uint8_t func = adapter->ahw.pci_func;
859 if (adapter->curr_window == wndw)
862 * Move the CRB window.
863 * We need to write to the "direct access" region of PCI
864 * to avoid a race condition where the window register has
865 * not been successfully written across CRB before the target
866 * register address is received by PCI. The direct region bypasses
869 offset = PCI_OFFSET_SECOND_RANGE(adapter,
870 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
873 wndw = NETXEN_WINDOW_ONE;
875 writel(wndw, offset);
877 /* MUST make sure window is set before we forge on... */
878 while ((tmp = readl(offset)) != wndw) {
879 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
880 "registered properly: 0x%08x.\n",
881 netxen_nic_driver_name, __func__, tmp);
888 if (wndw == NETXEN_WINDOW_ONE)
889 adapter->curr_window = 1;
891 adapter->curr_window = 0;
895 * Return -1 if off is not valid,
896 * 1 if window access is needed. 'off' is set to offset from
897 * CRB space in 128M pci map
898 * 0 if no window access is needed. 'off' is set to 2M addr
899 * In: 'off' is offset from base in 128M pci map
902 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
905 unsigned long end = *off + len;
906 crb_128M_2M_sub_block_map_t *m;
909 if (*off >= NETXEN_CRB_MAX)
912 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
913 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
914 (ulong)adapter->ahw.pci_base0;
918 if (*off < NETXEN_PCI_CRBSPACE)
921 *off -= NETXEN_PCI_CRBSPACE;
927 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
929 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
930 *off = *off + m->start_2M - m->start_128M +
931 (ulong)adapter->ahw.pci_base0;
936 * Not in direct map, use crb window
942 * In: 'off' is offset from CRB space in 128M pci map
943 * Out: 'off' is 2M pci map addr
944 * side effect: lock crb window
947 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
951 adapter->crb_win = CRB_HI(*off);
952 writel(adapter->crb_win, (void *)(CRB_WINDOW_2M +
953 adapter->ahw.pci_base0));
955 * Read back value to make sure write has gone through before trying
958 win_read = readl((void *)(CRB_WINDOW_2M + adapter->ahw.pci_base0));
959 if (win_read != adapter->crb_win) {
960 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
961 "Read crbwin (0x%x), off=0x%lx\n",
962 __func__, adapter->crb_win, win_read, *off);
964 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
965 (ulong)adapter->ahw.pci_base0;
968 int netxen_load_firmware(struct netxen_adapter *adapter)
972 u32 flashaddr = NETXEN_BOOTLD_START, memaddr = NETXEN_BOOTLD_START;
974 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START)/4;
976 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
977 adapter->pci_write_normalize(adapter,
978 NETXEN_ROMUSB_GLB_CAS_RST, 1);
980 for (i = 0; i < size; i++) {
981 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0)
984 adapter->pci_mem_write(adapter, memaddr, &data, 4);
991 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
992 adapter->pci_write_normalize(adapter,
993 NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
995 adapter->pci_write_normalize(adapter,
996 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
997 adapter->pci_write_normalize(adapter,
998 NETXEN_ROMUSB_GLB_CAS_RST, 0);
1005 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1006 ulong off, void *data, int len)
1010 if (ADDR_IN_WINDOW1(off)) {
1011 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1012 } else { /* Window 0 */
1013 addr = pci_base_offset(adapter, off);
1014 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1017 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
1018 " data %llx len %d\n",
1019 pci_base(adapter, off), off, addr,
1020 *(unsigned long long *)data, len);
1022 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1028 writeb(*(u8 *) data, addr);
1031 writew(*(u16 *) data, addr);
1034 writel(*(u32 *) data, addr);
1037 writeq(*(u64 *) data, addr);
1041 "writing data %lx to offset %llx, num words=%d\n",
1042 *(unsigned long *)data, off, (len >> 3));
1044 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
1048 if (!ADDR_IN_WINDOW1(off))
1049 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1055 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1056 ulong off, void *data, int len)
1060 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1061 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1062 } else { /* Window 0 */
1063 addr = pci_base_offset(adapter, off);
1064 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1067 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
1068 pci_base(adapter, off), off, addr);
1070 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1075 *(u8 *) data = readb(addr);
1078 *(u16 *) data = readw(addr);
1081 *(u32 *) data = readl(addr);
1084 *(u64 *) data = readq(addr);
1087 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
1091 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
1093 if (!ADDR_IN_WINDOW1(off))
1094 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1100 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1101 ulong off, void *data, int len)
1103 unsigned long flags = 0;
1106 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1109 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1116 write_lock_irqsave(&adapter->adapter_lock, flags);
1117 crb_win_lock(adapter);
1118 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1121 DPRINTK(1, INFO, "write data %lx to offset %llx, len=%d\n",
1122 *(unsigned long *)data, off, len);
1126 writeb(*(uint8_t *)data, (void *)off);
1129 writew(*(uint16_t *)data, (void *)off);
1132 writel(*(uint32_t *)data, (void *)off);
1135 writeq(*(uint64_t *)data, (void *)off);
1139 "writing data %lx to offset %llx, num words=%d\n",
1140 *(unsigned long *)data, off, (len>>3));
1144 crb_win_unlock(adapter);
1145 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1152 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1153 ulong off, void *data, int len)
1155 unsigned long flags = 0;
1158 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1161 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1168 write_lock_irqsave(&adapter->adapter_lock, flags);
1169 crb_win_lock(adapter);
1170 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1173 DPRINTK(1, INFO, "read from offset %lx, len=%d\n", off, len);
1177 *(uint8_t *)data = readb((void *)off);
1180 *(uint16_t *)data = readw((void *)off);
1183 *(uint32_t *)data = readl((void *)off);
1186 *(uint64_t *)data = readq((void *)off);
1192 DPRINTK(1, INFO, "read %lx\n", *(unsigned long *)data);
1195 crb_win_unlock(adapter);
1196 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1202 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
1204 adapter->hw_write_wx(adapter, off, &val, 4);
1207 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
1210 adapter->hw_read_wx(adapter, off, &val, 4);
1214 /* Change the window to 0, write and change back to window 1. */
1215 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
1217 adapter->hw_write_wx(adapter, index, &value, 4);
1220 /* Change the window to 0, read and change back to window 1. */
1221 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value)
1223 adapter->hw_read_wx(adapter, index, value, 4);
1226 void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1228 adapter->hw_write_wx(adapter, index, &value, 4);
1231 void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value)
1233 adapter->hw_read_wx(adapter, index, value, 4);
1237 * check memory access boundary.
1238 * used by test agent. support ddr access only for now
1240 static unsigned long
1241 netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1242 unsigned long long addr, int size)
1244 if (!ADDR_IN_RANGE(addr,
1245 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1246 !ADDR_IN_RANGE(addr+size-1,
1247 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1248 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1255 static int netxen_pci_set_window_warning_count;
1258 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1259 unsigned long long addr)
1261 void __iomem *offset;
1263 unsigned long long qdr_max;
1264 uint8_t func = adapter->ahw.pci_func;
1266 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1267 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1269 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1272 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1273 /* DDR network side */
1274 addr -= NETXEN_ADDR_DDR_NET;
1275 window = (addr >> 25) & 0x3ff;
1276 if (adapter->ahw.ddr_mn_window != window) {
1277 adapter->ahw.ddr_mn_window = window;
1278 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1279 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1280 writel(window, offset);
1281 /* MUST make sure window is set before we forge on... */
1284 addr -= (window * NETXEN_WINDOW_ONE);
1285 addr += NETXEN_PCI_DDR_NET;
1286 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1287 addr -= NETXEN_ADDR_OCM0;
1288 addr += NETXEN_PCI_OCM0;
1289 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1290 addr -= NETXEN_ADDR_OCM1;
1291 addr += NETXEN_PCI_OCM1;
1292 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1293 /* QDR network side */
1294 addr -= NETXEN_ADDR_QDR_NET;
1295 window = (addr >> 22) & 0x3f;
1296 if (adapter->ahw.qdr_sn_window != window) {
1297 adapter->ahw.qdr_sn_window = window;
1298 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1299 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1300 writel((window << 22), offset);
1301 /* MUST make sure window is set before we forge on... */
1304 addr -= (window * 0x400000);
1305 addr += NETXEN_PCI_QDR_NET;
1308 * peg gdb frequently accesses memory that doesn't exist,
1309 * this limits the chit chat so debugging isn't slowed down.
1311 if ((netxen_pci_set_window_warning_count++ < 8)
1312 || (netxen_pci_set_window_warning_count % 64 == 0))
1313 printk("%s: Warning:netxen_nic_pci_set_window()"
1314 " Unknown address range!\n",
1315 netxen_nic_driver_name);
1322 * Note : only 32-bit writes!
1324 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1327 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1331 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1333 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1336 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1339 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1342 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off)
1344 return readl(NETXEN_CRB_NORMALIZE(adapter, off));
1348 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1349 unsigned long long addr)
1354 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1355 /* DDR network side */
1356 window = MN_WIN(addr);
1357 adapter->ahw.ddr_mn_window = window;
1358 adapter->hw_write_wx(adapter,
1359 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1361 adapter->hw_read_wx(adapter,
1362 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1364 if ((win_read << 17) != window) {
1365 printk(KERN_INFO "Written MNwin (0x%x) != "
1366 "Read MNwin (0x%x)\n", window, win_read);
1368 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1369 } else if (ADDR_IN_RANGE(addr,
1370 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1371 if ((addr & 0x00ff800) == 0xff800) {
1372 printk("%s: QM access not handled.\n", __func__);
1376 window = OCM_WIN(addr);
1377 adapter->ahw.ddr_mn_window = window;
1378 adapter->hw_write_wx(adapter,
1379 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1381 adapter->hw_read_wx(adapter,
1382 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1384 if ((win_read >> 7) != window) {
1385 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1386 "Read OCMwin (0x%x)\n",
1387 __func__, window, win_read);
1389 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1391 } else if (ADDR_IN_RANGE(addr,
1392 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1393 /* QDR network side */
1394 window = MS_WIN(addr);
1395 adapter->ahw.qdr_sn_window = window;
1396 adapter->hw_write_wx(adapter,
1397 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1399 adapter->hw_read_wx(adapter,
1400 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1402 if (win_read != window) {
1403 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1404 "Read MSwin (0x%x)\n",
1405 __func__, window, win_read);
1407 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1411 * peg gdb frequently accesses memory that doesn't exist,
1412 * this limits the chit chat so debugging isn't slowed down.
1414 if ((netxen_pci_set_window_warning_count++ < 8)
1415 || (netxen_pci_set_window_warning_count%64 == 0)) {
1416 printk("%s: Warning:%s Unknown address range!\n",
1417 __func__, netxen_nic_driver_name);
1424 static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1425 unsigned long long addr)
1428 unsigned long long qdr_max;
1430 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1431 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1433 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1435 if (ADDR_IN_RANGE(addr,
1436 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1437 /* DDR network side */
1438 BUG(); /* MN access can not come here */
1439 } else if (ADDR_IN_RANGE(addr,
1440 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1442 } else if (ADDR_IN_RANGE(addr,
1443 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1445 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1446 /* QDR network side */
1447 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1448 if (adapter->ahw.qdr_sn_window == window)
1455 static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1456 u64 off, void *data, int size)
1458 unsigned long flags;
1462 uint8_t *mem_ptr = NULL;
1463 unsigned long mem_base;
1464 unsigned long mem_page;
1466 write_lock_irqsave(&adapter->adapter_lock, flags);
1469 * If attempting to access unknown address or straddle hw windows,
1472 start = adapter->pci_set_window(adapter, off);
1473 if ((start == -1UL) ||
1474 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1475 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1476 printk(KERN_ERR "%s out of bound pci memory access. "
1477 "offset is 0x%llx\n", netxen_nic_driver_name, off);
1481 addr = (void *)(pci_base_offset(adapter, start));
1483 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1484 mem_base = pci_resource_start(adapter->pdev, 0);
1485 mem_page = start & PAGE_MASK;
1486 /* Map two pages whenever user tries to access addresses in two
1489 if (mem_page != ((start + size - 1) & PAGE_MASK))
1490 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1492 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1493 if (mem_ptr == 0UL) {
1494 *(uint8_t *)data = 0;
1498 addr += start & (PAGE_SIZE - 1);
1499 write_lock_irqsave(&adapter->adapter_lock, flags);
1504 *(uint8_t *)data = readb(addr);
1507 *(uint16_t *)data = readw(addr);
1510 *(uint32_t *)data = readl(addr);
1513 *(uint64_t *)data = readq(addr);
1519 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1520 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1528 netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1529 void *data, int size)
1531 unsigned long flags;
1535 uint8_t *mem_ptr = NULL;
1536 unsigned long mem_base;
1537 unsigned long mem_page;
1539 write_lock_irqsave(&adapter->adapter_lock, flags);
1542 * If attempting to access unknown address or straddle hw windows,
1545 start = adapter->pci_set_window(adapter, off);
1546 if ((start == -1UL) ||
1547 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1548 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1549 printk(KERN_ERR "%s out of bound pci memory access. "
1550 "offset is 0x%llx\n", netxen_nic_driver_name, off);
1554 addr = (void *)(pci_base_offset(adapter, start));
1556 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1557 mem_base = pci_resource_start(adapter->pdev, 0);
1558 mem_page = start & PAGE_MASK;
1559 /* Map two pages whenever user tries to access addresses in two
1560 * consecutive pages.
1562 if (mem_page != ((start + size - 1) & PAGE_MASK))
1563 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1565 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1569 addr += start & (PAGE_SIZE - 1);
1570 write_lock_irqsave(&adapter->adapter_lock, flags);
1575 writeb(*(uint8_t *)data, addr);
1578 writew(*(uint16_t *)data, addr);
1581 writel(*(uint32_t *)data, addr);
1584 writeq(*(uint64_t *)data, addr);
1590 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1591 DPRINTK(1, INFO, "writing data %llx to offset %llx\n",
1592 *(unsigned long long *)data, start);
1598 #define MAX_CTL_CHECK 1000
1601 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1602 u64 off, void *data, int size)
1604 unsigned long flags, mem_crb;
1605 int i, j, ret = 0, loop, sz[2], off0;
1607 uint64_t off8, tmpw, word[2] = {0, 0};
1610 * If not MN, go check for MS or invalid.
1612 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1613 return netxen_nic_pci_mem_write_direct(adapter,
1616 off8 = off & 0xfffffff8;
1618 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1619 sz[1] = size - sz[0];
1620 loop = ((off0 + size - 1) >> 3) + 1;
1621 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1623 if ((size != 8) || (off0 != 0)) {
1624 for (i = 0; i < loop; i++) {
1625 if (adapter->pci_mem_read(adapter,
1626 off8 + (i << 3), &word[i], 8))
1633 tmpw = *((uint8_t *)data);
1636 tmpw = *((uint16_t *)data);
1639 tmpw = *((uint32_t *)data);
1643 tmpw = *((uint64_t *)data);
1646 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1647 word[0] |= tmpw << (off0 * 8);
1650 word[1] &= ~(~0ULL << (sz[1] * 8));
1651 word[1] |= tmpw >> (sz[0] * 8);
1654 write_lock_irqsave(&adapter->adapter_lock, flags);
1655 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1657 for (i = 0; i < loop; i++) {
1658 writel((uint32_t)(off8 + (i << 3)),
1659 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1661 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1662 writel(word[i] & 0xffffffff,
1663 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_LO));
1664 writel((word[i] >> 32) & 0xffffffff,
1665 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_HI));
1666 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1667 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1668 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1669 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1671 for (j = 0; j < MAX_CTL_CHECK; j++) {
1673 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1674 if ((temp & MIU_TA_CTL_BUSY) == 0)
1678 if (j >= MAX_CTL_CHECK) {
1679 printk("%s: %s Fail to write through agent\n",
1680 __func__, netxen_nic_driver_name);
1686 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1687 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1692 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1693 u64 off, void *data, int size)
1695 unsigned long flags, mem_crb;
1696 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1698 uint64_t off8, val, word[2] = {0, 0};
1702 * If not MN, go check for MS or invalid.
1704 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1705 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1707 off8 = off & 0xfffffff8;
1708 off0[0] = off & 0x7;
1710 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1711 sz[1] = size - sz[0];
1712 loop = ((off0[0] + size - 1) >> 3) + 1;
1713 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1715 write_lock_irqsave(&adapter->adapter_lock, flags);
1716 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1718 for (i = 0; i < loop; i++) {
1719 writel((uint32_t)(off8 + (i << 3)),
1720 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1722 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1723 writel(MIU_TA_CTL_ENABLE,
1724 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1725 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1726 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1728 for (j = 0; j < MAX_CTL_CHECK; j++) {
1730 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1731 if ((temp & MIU_TA_CTL_BUSY) == 0)
1735 if (j >= MAX_CTL_CHECK) {
1736 printk(KERN_ERR "%s: %s Fail to read through agent\n",
1737 __func__, netxen_nic_driver_name);
1741 start = off0[i] >> 2;
1742 end = (off0[i] + sz[i] - 1) >> 2;
1743 for (k = start; k <= end; k++) {
1744 word[i] |= ((uint64_t) readl(
1746 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1750 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1751 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1753 if (j >= MAX_CTL_CHECK)
1759 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1760 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1765 *(uint8_t *)data = val;
1768 *(uint16_t *)data = val;
1771 *(uint32_t *)data = val;
1774 *(uint64_t *)data = val;
1777 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1782 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1783 u64 off, void *data, int size)
1785 int i, j, ret = 0, loop, sz[2], off0;
1787 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1790 * If not MN, go check for MS or invalid.
1792 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1793 mem_crb = NETXEN_CRB_QDR_NET;
1795 mem_crb = NETXEN_CRB_DDR_NET;
1796 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1797 return netxen_nic_pci_mem_write_direct(adapter,
1801 off8 = off & 0xfffffff8;
1803 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1804 sz[1] = size - sz[0];
1805 loop = ((off0 + size - 1) >> 3) + 1;
1807 if ((size != 8) || (off0 != 0)) {
1808 for (i = 0; i < loop; i++) {
1809 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1817 tmpw = *((uint8_t *)data);
1820 tmpw = *((uint16_t *)data);
1823 tmpw = *((uint32_t *)data);
1827 tmpw = *((uint64_t *)data);
1831 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1832 word[0] |= tmpw << (off0 * 8);
1835 word[1] &= ~(~0ULL << (sz[1] * 8));
1836 word[1] |= tmpw >> (sz[0] * 8);
1840 * don't lock here - write_wx gets the lock if each time
1841 * write_lock_irqsave(&adapter->adapter_lock, flags);
1842 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1845 for (i = 0; i < loop; i++) {
1846 temp = off8 + (i << 3);
1847 adapter->hw_write_wx(adapter,
1848 mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4);
1850 adapter->hw_write_wx(adapter,
1851 mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4);
1852 temp = word[i] & 0xffffffff;
1853 adapter->hw_write_wx(adapter,
1854 mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4);
1855 temp = (word[i] >> 32) & 0xffffffff;
1856 adapter->hw_write_wx(adapter,
1857 mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4);
1858 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1859 adapter->hw_write_wx(adapter,
1860 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1861 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1862 adapter->hw_write_wx(adapter,
1863 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1865 for (j = 0; j < MAX_CTL_CHECK; j++) {
1866 adapter->hw_read_wx(adapter,
1867 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1868 if ((temp & MIU_TA_CTL_BUSY) == 0)
1872 if (j >= MAX_CTL_CHECK) {
1873 printk(KERN_ERR "%s: Fail to write through agent\n",
1874 netxen_nic_driver_name);
1881 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1882 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1888 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1889 u64 off, void *data, int size)
1891 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1893 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1896 * If not MN, go check for MS or invalid.
1899 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1900 mem_crb = NETXEN_CRB_QDR_NET;
1902 mem_crb = NETXEN_CRB_DDR_NET;
1903 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1904 return netxen_nic_pci_mem_read_direct(adapter,
1908 off8 = off & 0xfffffff8;
1909 off0[0] = off & 0x7;
1911 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1912 sz[1] = size - sz[0];
1913 loop = ((off0[0] + size - 1) >> 3) + 1;
1916 * don't lock here - write_wx gets the lock if each time
1917 * write_lock_irqsave(&adapter->adapter_lock, flags);
1918 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1921 for (i = 0; i < loop; i++) {
1922 temp = off8 + (i << 3);
1923 adapter->hw_write_wx(adapter,
1924 mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4);
1926 adapter->hw_write_wx(adapter,
1927 mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4);
1928 temp = MIU_TA_CTL_ENABLE;
1929 adapter->hw_write_wx(adapter,
1930 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1931 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1932 adapter->hw_write_wx(adapter,
1933 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1935 for (j = 0; j < MAX_CTL_CHECK; j++) {
1936 adapter->hw_read_wx(adapter,
1937 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1938 if ((temp & MIU_TA_CTL_BUSY) == 0)
1942 if (j >= MAX_CTL_CHECK) {
1943 printk(KERN_ERR "%s: Fail to read through agent\n",
1944 netxen_nic_driver_name);
1948 start = off0[i] >> 2;
1949 end = (off0[i] + sz[i] - 1) >> 2;
1950 for (k = start; k <= end; k++) {
1951 adapter->hw_read_wx(adapter,
1952 mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4);
1953 word[i] |= ((uint64_t)temp << (32 * k));
1958 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1959 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1962 if (j >= MAX_CTL_CHECK)
1968 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1969 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1974 *(uint8_t *)data = val;
1977 *(uint16_t *)data = val;
1980 *(uint32_t *)data = val;
1983 *(uint64_t *)data = val;
1986 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1991 * Note : only 32-bit writes!
1993 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1996 adapter->hw_write_wx(adapter, off, &data, 4);
2001 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
2004 adapter->hw_read_wx(adapter, off, &temp, 4);
2008 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
2011 adapter->hw_write_wx(adapter, off, &data, 4);
2014 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off)
2017 adapter->hw_read_wx(adapter, off, &temp, 4);
2023 netxen_nic_erase_pxe(struct netxen_adapter *adapter)
2025 if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) {
2026 printk(KERN_ERR "%s: erase pxe failed\n",
2027 netxen_nic_driver_name);
2034 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2037 int addr = NETXEN_BRDCFG_START;
2038 struct netxen_board_info *boardinfo;
2042 boardinfo = &adapter->ahw.boardcfg;
2043 ptr32 = (u32 *) boardinfo;
2045 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
2047 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
2051 addr += sizeof(u32);
2053 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
2054 printk("%s: ERROR reading %s board config."
2055 " Read %x, expected %x\n", netxen_nic_driver_name,
2056 netxen_nic_driver_name,
2057 boardinfo->magic, NETXEN_BDINFO_MAGIC);
2060 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
2061 printk("%s: Unknown board config version."
2062 " Read %x, expected %x\n", netxen_nic_driver_name,
2063 boardinfo->header_version, NETXEN_BDINFO_VERSION);
2067 DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
2068 switch ((netxen_brdtype_t) boardinfo->board_type) {
2069 case NETXEN_BRDTYPE_P2_SB35_4G:
2070 adapter->ahw.board_type = NETXEN_NIC_GBE;
2072 case NETXEN_BRDTYPE_P2_SB31_10G:
2073 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
2074 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
2075 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
2076 case NETXEN_BRDTYPE_P3_HMEZ:
2077 case NETXEN_BRDTYPE_P3_XG_LOM:
2078 case NETXEN_BRDTYPE_P3_10G_CX4:
2079 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
2080 case NETXEN_BRDTYPE_P3_IMEZ:
2081 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
2082 case NETXEN_BRDTYPE_P3_10G_XFP:
2083 case NETXEN_BRDTYPE_P3_10000_BASE_T:
2085 adapter->ahw.board_type = NETXEN_NIC_XGBE;
2087 case NETXEN_BRDTYPE_P1_BD:
2088 case NETXEN_BRDTYPE_P1_SB:
2089 case NETXEN_BRDTYPE_P1_SMAX:
2090 case NETXEN_BRDTYPE_P1_SOCK:
2091 case NETXEN_BRDTYPE_P3_REF_QG:
2092 case NETXEN_BRDTYPE_P3_4_GB:
2093 case NETXEN_BRDTYPE_P3_4_GB_MM:
2095 adapter->ahw.board_type = NETXEN_NIC_GBE;
2098 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
2099 boardinfo->board_type);
2106 /* NIU access sections */
2108 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
2110 netxen_nic_write_w0(adapter,
2111 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2116 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
2118 new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
2119 if (adapter->physical_port == 0)
2120 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
2123 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
2128 void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
2130 netxen_niu_gbe_init_port(adapter, adapter->physical_port);
2134 netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
2135 unsigned long off, int data)
2137 adapter->hw_write_wx(adapter, off, &data, 4);
2140 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2146 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
2147 if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
2148 if (adapter->phy_read
2151 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2153 if (netxen_get_phy_link(status)) {
2154 switch (netxen_get_phy_speed(status)) {
2156 adapter->link_speed = SPEED_10;
2159 adapter->link_speed = SPEED_100;
2162 adapter->link_speed = SPEED_1000;
2165 adapter->link_speed = -1;
2168 switch (netxen_get_phy_duplex(status)) {
2170 adapter->link_duplex = DUPLEX_HALF;
2173 adapter->link_duplex = DUPLEX_FULL;
2176 adapter->link_duplex = -1;
2179 if (adapter->phy_read
2182 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
2184 adapter->link_autoneg = autoneg;
2189 adapter->link_speed = -1;
2190 adapter->link_duplex = -1;
2195 void netxen_nic_flash_print(struct netxen_adapter *adapter)
2200 char brd_name[NETXEN_MAX_SHORT_NAME];
2201 char serial_num[32];
2205 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
2207 adapter->driver_mismatch = 0;
2209 ptr32 = (u32 *)&serial_num;
2210 addr = NETXEN_USER_START +
2211 offsetof(struct netxen_new_user_info, serial_num);
2212 for (i = 0; i < 8; i++) {
2213 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
2214 printk("%s: ERROR reading %s board userarea.\n",
2215 netxen_nic_driver_name,
2216 netxen_nic_driver_name);
2217 adapter->driver_mismatch = 1;
2221 addr += sizeof(u32);
2224 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4);
2225 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4);
2226 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4);
2228 adapter->fw_major = fw_major;
2230 if (adapter->portnum == 0) {
2231 get_brd_name_by_type(board_info->board_type, brd_name);
2233 printk("NetXen %s Board S/N %s Chip id 0x%x\n",
2234 brd_name, serial_num, board_info->chip_id);
2235 printk("NetXen Firmware version %d.%d.%d\n", fw_major,
2236 fw_minor, fw_build);
2239 if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
2240 adapter->driver_mismatch = 1;
2242 if (fw_minor != _NETXEN_NIC_LINUX_MINOR &&
2243 fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) {
2244 adapter->driver_mismatch = 1;
2246 if (adapter->driver_mismatch) {
2247 printk(KERN_ERR "%s: driver and firmware version mismatch\n",
2248 adapter->netdev->name);