2 * Copyright (C) 2003 - 2006 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
30 * Source file for NIC routines to access the Phantom hardware
34 #include "netxen_nic.h"
35 #include "netxen_nic_hw.h"
36 #include "netxen_nic_phan_reg.h"
41 struct netxen_recv_crb recv_crb_registers[] = {
46 /* crb_rcv_producer: */
48 NETXEN_NIC_REG(0x100),
50 NETXEN_NIC_REG(0x110),
54 /* crb_sts_consumer: */
55 NETXEN_NIC_REG(0x138),
61 /* crb_rcv_producer: */
63 NETXEN_NIC_REG(0x144),
65 NETXEN_NIC_REG(0x154),
69 /* crb_sts_consumer: */
70 NETXEN_NIC_REG(0x17c),
76 /* crb_rcv_producer: */
78 NETXEN_NIC_REG(0x1d8),
80 NETXEN_NIC_REG(0x1f8),
84 /* crb_sts_consumer: */
85 NETXEN_NIC_REG(0x220),
91 /* crb_rcv_producer: */
93 NETXEN_NIC_REG(0x22c),
95 NETXEN_NIC_REG(0x23c),
99 /* crb_sts_consumer: */
100 NETXEN_NIC_REG(0x264),
104 static u64 ctx_addr_sig_regs[][3] = {
105 {NETXEN_NIC_REG(0x188), NETXEN_NIC_REG(0x18c), NETXEN_NIC_REG(0x1c0)},
106 {NETXEN_NIC_REG(0x190), NETXEN_NIC_REG(0x194), NETXEN_NIC_REG(0x1c4)},
107 {NETXEN_NIC_REG(0x198), NETXEN_NIC_REG(0x19c), NETXEN_NIC_REG(0x1c8)},
108 {NETXEN_NIC_REG(0x1a0), NETXEN_NIC_REG(0x1a4), NETXEN_NIC_REG(0x1cc)}
110 #define CRB_CTX_ADDR_REG_LO(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][0])
111 #define CRB_CTX_ADDR_REG_HI(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][2])
112 #define CRB_CTX_SIGNATURE_REG(FUNC_ID) (ctx_addr_sig_regs[FUNC_ID][1])
115 /* PCI Windowing for DDR regions. */
117 #define ADDR_IN_RANGE(addr, low, high) \
118 (((addr) <= (high)) && ((addr) >= (low)))
120 #define NETXEN_FLASH_BASE (NETXEN_BOOTLD_START)
121 #define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE)
122 #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
123 #define NETXEN_MIN_MTU 64
124 #define NETXEN_ETH_FCS_SIZE 4
125 #define NETXEN_ENET_HEADER_SIZE 14
126 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
127 #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
128 #define NETXEN_NIU_HDRSIZE (0x1 << 6)
129 #define NETXEN_NIU_TLRSIZE (0x1 << 5)
131 #define lower32(x) ((u32)((x) & 0xffffffff))
133 ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff))
135 #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
136 #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
137 #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
138 #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
140 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
142 static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
143 unsigned long long addr);
144 void netxen_free_hw_resources(struct netxen_adapter *adapter);
146 int netxen_nic_set_mac(struct net_device *netdev, void *p)
148 struct netxen_adapter *adapter = netdev_priv(netdev);
149 struct sockaddr *addr = p;
151 if (netif_running(netdev))
154 if (!is_valid_ether_addr(addr->sa_data))
155 return -EADDRNOTAVAIL;
157 DPRINTK(INFO, "valid ether addr\n");
158 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
160 if (adapter->macaddr_set)
161 adapter->macaddr_set(adapter, addr->sa_data);
167 * netxen_nic_set_multi - Multicast
169 void netxen_nic_set_multi(struct net_device *netdev)
171 struct netxen_adapter *adapter = netdev_priv(netdev);
172 struct dev_mc_list *mc_ptr;
174 mc_ptr = netdev->mc_list;
175 if (netdev->flags & IFF_PROMISC) {
176 if (adapter->set_promisc)
177 adapter->set_promisc(adapter,
178 NETXEN_NIU_PROMISC_MODE);
180 if (adapter->unset_promisc)
181 adapter->unset_promisc(adapter,
182 NETXEN_NIU_NON_PROMISC_MODE);
187 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
188 * @returns 0 on success, negative on failure
190 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
192 struct netxen_adapter *adapter = netdev_priv(netdev);
193 int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
195 if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
196 printk(KERN_ERR "%s: %s %d is not supported.\n",
197 netxen_nic_driver_name, netdev->name, mtu);
201 if (adapter->set_mtu)
202 adapter->set_mtu(adapter, mtu);
209 * check if the firmware has been downloaded and ready to run and
210 * setup the address for the descriptors in the adapter
212 int netxen_nic_hw_resources(struct netxen_adapter *adapter)
214 struct netxen_hardware_context *hw = &adapter->ahw;
217 int loops = 0, err = 0;
219 struct netxen_recv_context *recv_ctx;
220 struct netxen_rcv_desc_ctx *rcv_desc;
221 int func_id = adapter->portnum;
223 DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE,
224 PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE));
225 DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM,
226 pci_base_offset(adapter, NETXEN_CRB_CAM));
227 DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE,
228 pci_base_offset(adapter, NETXEN_CAM_RAM_BASE));
231 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
232 DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
236 state = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_RCVPEG_STATE));
237 while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
240 state = readl(NETXEN_CRB_NORMALIZE(adapter,
245 printk(KERN_ERR "Rcv Peg initialization not complete:"
251 adapter->intr_scheme = readl(
252 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_CAPABILITIES_FW));
253 adapter->msi_mode = readl(
254 NETXEN_CRB_NORMALIZE(adapter, CRB_NIC_MSI_MODE_FW));
256 addr = pci_alloc_consistent(adapter->pdev,
257 sizeof(struct netxen_ring_ctx) + sizeof(uint32_t),
258 &adapter->ctx_desc_phys_addr);
261 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
265 memset(addr, 0, sizeof(struct netxen_ring_ctx));
266 adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
267 adapter->ctx_desc->ctx_id = cpu_to_le32(adapter->portnum);
268 adapter->ctx_desc->cmd_consumer_offset =
269 cpu_to_le64(adapter->ctx_desc_phys_addr +
270 sizeof(struct netxen_ring_ctx));
271 adapter->cmd_consumer = (__le32 *) (((char *)addr) +
272 sizeof(struct netxen_ring_ctx));
274 addr = pci_alloc_consistent(adapter->pdev,
275 sizeof(struct cmd_desc_type0) *
276 adapter->max_tx_desc_count,
277 &hw->cmd_desc_phys_addr);
280 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
281 netxen_free_hw_resources(adapter);
285 adapter->ctx_desc->cmd_ring_addr =
286 cpu_to_le64(hw->cmd_desc_phys_addr);
287 adapter->ctx_desc->cmd_ring_size =
288 cpu_to_le32(adapter->max_tx_desc_count);
290 hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
292 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
293 recv_ctx = &adapter->recv_ctx[ctx];
295 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
296 rcv_desc = &recv_ctx->rcv_desc[ring];
297 addr = pci_alloc_consistent(adapter->pdev,
299 &rcv_desc->phys_addr);
301 DPRINTK(ERR, "bad return from "
302 "pci_alloc_consistent\n");
303 netxen_free_hw_resources(adapter);
307 rcv_desc->desc_head = (struct rcv_desc *)addr;
308 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr =
309 cpu_to_le64(rcv_desc->phys_addr);
310 adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
311 cpu_to_le32(rcv_desc->max_rx_desc_count);
312 rcv_desc->crb_rcv_producer =
313 recv_crb_registers[adapter->portnum].
314 crb_rcv_producer[ring];
317 addr = pci_alloc_consistent(adapter->pdev, STATUS_DESC_RINGSIZE,
318 &recv_ctx->rcv_status_desc_phys_addr);
320 DPRINTK(ERR, "bad return from"
321 " pci_alloc_consistent\n");
322 netxen_free_hw_resources(adapter);
326 recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
327 adapter->ctx_desc->sts_ring_addr =
328 cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
329 adapter->ctx_desc->sts_ring_size =
330 cpu_to_le32(adapter->max_rx_desc_count);
331 recv_ctx->crb_sts_consumer =
332 recv_crb_registers[adapter->portnum].crb_sts_consumer;
337 writel(lower32(adapter->ctx_desc_phys_addr),
338 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO(func_id)));
339 writel(upper32(adapter->ctx_desc_phys_addr),
340 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI(func_id)));
341 writel(NETXEN_CTX_SIGNATURE | func_id,
342 NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG(func_id)));
346 void netxen_free_hw_resources(struct netxen_adapter *adapter)
348 struct netxen_recv_context *recv_ctx;
349 struct netxen_rcv_desc_ctx *rcv_desc;
352 if (adapter->ctx_desc != NULL) {
353 pci_free_consistent(adapter->pdev,
354 sizeof(struct netxen_ring_ctx) +
357 adapter->ctx_desc_phys_addr);
358 adapter->ctx_desc = NULL;
361 if (adapter->ahw.cmd_desc_head != NULL) {
362 pci_free_consistent(adapter->pdev,
363 sizeof(struct cmd_desc_type0) *
364 adapter->max_tx_desc_count,
365 adapter->ahw.cmd_desc_head,
366 adapter->ahw.cmd_desc_phys_addr);
367 adapter->ahw.cmd_desc_head = NULL;
370 for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
371 recv_ctx = &adapter->recv_ctx[ctx];
372 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
373 rcv_desc = &recv_ctx->rcv_desc[ring];
375 if (rcv_desc->desc_head != NULL) {
376 pci_free_consistent(adapter->pdev,
379 rcv_desc->phys_addr);
380 rcv_desc->desc_head = NULL;
384 if (recv_ctx->rcv_status_desc_head != NULL) {
385 pci_free_consistent(adapter->pdev,
386 STATUS_DESC_RINGSIZE,
387 recv_ctx->rcv_status_desc_head,
389 rcv_status_desc_phys_addr);
390 recv_ctx->rcv_status_desc_head = NULL;
395 void netxen_tso_check(struct netxen_adapter *adapter,
396 struct cmd_desc_type0 *desc, struct sk_buff *skb)
399 desc->total_hdr_length = (sizeof(struct ethhdr) +
400 ip_hdrlen(skb) + tcp_hdrlen(skb));
401 netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO);
402 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
403 if (ip_hdr(skb)->protocol == IPPROTO_TCP) {
404 netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT);
405 } else if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
406 netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT);
411 desc->tcp_hdr_offset = skb_transport_offset(skb);
412 desc->ip_hdr_offset = skb_network_offset(skb);
415 int netxen_is_flash_supported(struct netxen_adapter *adapter)
417 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
418 int addr, val01, val02, i, j;
420 /* if the flash size less than 4Mb, make huge war cry and die */
421 for (j = 1; j < 4; j++) {
422 addr = j * NETXEN_NIC_WINDOW_MARGIN;
423 for (i = 0; i < ARRAY_SIZE(locs); i++) {
424 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
425 && netxen_rom_fast_read(adapter, (addr + locs[i]),
437 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
438 int size, __le32 * buf)
446 for (i = 0; i < size / sizeof(u32); i++) {
447 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
449 *ptr32 = cpu_to_le32(v);
453 if ((char *)buf + size > (char *)ptr32) {
455 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
457 local = cpu_to_le32(v);
458 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
464 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[])
466 __le32 *pmac = (__le32 *) & mac[0];
468 if (netxen_get_flash_block(adapter,
470 offsetof(struct netxen_new_user_info,
472 FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
475 if (*mac == cpu_to_le64(~0ULL)) {
476 if (netxen_get_flash_block(adapter,
477 NETXEN_USER_START_OLD +
478 offsetof(struct netxen_user_old_info,
480 FLASH_NUM_PORTS * sizeof(u64),
483 if (*mac == cpu_to_le64(~0ULL))
490 * Changes the CRB window to the specified window.
492 void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
494 void __iomem *offset;
498 if (adapter->curr_window == wndw)
500 switch(adapter->ahw.pci_func) {
502 offset = PCI_OFFSET_SECOND_RANGE(adapter,
503 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
506 offset = PCI_OFFSET_SECOND_RANGE(adapter,
507 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F1));
510 offset = PCI_OFFSET_SECOND_RANGE(adapter,
511 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F2));
514 offset = PCI_OFFSET_SECOND_RANGE(adapter,
515 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW_F3));
518 printk(KERN_INFO "Changing the window for PCI function "
519 "%d\n", adapter->ahw.pci_func);
520 offset = PCI_OFFSET_SECOND_RANGE(adapter,
521 NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
525 * Move the CRB window.
526 * We need to write to the "direct access" region of PCI
527 * to avoid a race condition where the window register has
528 * not been successfully written across CRB before the target
529 * register address is received by PCI. The direct region bypasses
534 wndw = NETXEN_WINDOW_ONE;
536 writel(wndw, offset);
538 /* MUST make sure window is set before we forge on... */
539 while ((tmp = readl(offset)) != wndw) {
540 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
541 "registered properly: 0x%08x.\n",
542 netxen_nic_driver_name, __FUNCTION__, tmp);
549 if (wndw == NETXEN_WINDOW_ONE)
550 adapter->curr_window = 1;
552 adapter->curr_window = 0;
555 int netxen_load_firmware(struct netxen_adapter *adapter)
559 u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
563 size = NETXEN_FIRMWARE_LEN;
564 writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
566 for (i = 0; i < size; i++) {
568 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0)
571 off = netxen_nic_pci_set_window(adapter, memaddr);
572 addr = pci_base_offset(adapter, off);
575 if (readl(addr) == data)
581 printk(KERN_ERR "%s: firmware load aborted, write failed at 0x%x\n",
582 netxen_nic_driver_name, memaddr);
589 /* make sure Casper is powered on */
591 NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL));
592 writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
598 netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
603 if (ADDR_IN_WINDOW1(off)) {
604 addr = NETXEN_CRB_NORMALIZE(adapter, off);
605 } else { /* Window 0 */
606 addr = pci_base_offset(adapter, off);
607 netxen_nic_pci_change_crbwindow(adapter, 0);
610 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
611 " data %llx len %d\n",
612 pci_base(adapter, off), off, addr,
613 *(unsigned long long *)data, len);
615 netxen_nic_pci_change_crbwindow(adapter, 1);
621 writeb(*(u8 *) data, addr);
624 writew(*(u16 *) data, addr);
627 writel(*(u32 *) data, addr);
630 writeq(*(u64 *) data, addr);
634 "writing data %lx to offset %llx, num words=%d\n",
635 *(unsigned long *)data, off, (len >> 3));
637 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
641 if (!ADDR_IN_WINDOW1(off))
642 netxen_nic_pci_change_crbwindow(adapter, 1);
648 netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
653 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
654 addr = NETXEN_CRB_NORMALIZE(adapter, off);
655 } else { /* Window 0 */
656 addr = pci_base_offset(adapter, off);
657 netxen_nic_pci_change_crbwindow(adapter, 0);
660 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
661 pci_base(adapter, off), off, addr);
663 netxen_nic_pci_change_crbwindow(adapter, 1);
668 *(u8 *) data = readb(addr);
671 *(u16 *) data = readw(addr);
674 *(u32 *) data = readl(addr);
677 *(u64 *) data = readq(addr);
680 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
684 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
686 if (!ADDR_IN_WINDOW1(off))
687 netxen_nic_pci_change_crbwindow(adapter, 1);
692 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
693 { /* Only for window 1 */
696 addr = NETXEN_CRB_NORMALIZE(adapter, off);
697 DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
698 pci_base(adapter, off), off, addr, val);
703 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
704 { /* Only for window 1 */
708 addr = NETXEN_CRB_NORMALIZE(adapter, off);
709 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
710 pci_base(adapter, off), off, addr);
717 /* Change the window to 0, write and change back to window 1. */
718 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
722 netxen_nic_pci_change_crbwindow(adapter, 0);
723 addr = pci_base_offset(adapter, index);
725 netxen_nic_pci_change_crbwindow(adapter, 1);
728 /* Change the window to 0, read and change back to window 1. */
729 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value)
733 addr = pci_base_offset(adapter, index);
735 netxen_nic_pci_change_crbwindow(adapter, 0);
736 *value = readl(addr);
737 netxen_nic_pci_change_crbwindow(adapter, 1);
740 static int netxen_pci_set_window_warning_count;
742 static unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
743 unsigned long long addr)
745 static int ddr_mn_window = -1;
746 static int qdr_sn_window = -1;
749 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
750 /* DDR network side */
751 addr -= NETXEN_ADDR_DDR_NET;
752 window = (addr >> 25) & 0x3ff;
753 if (ddr_mn_window != window) {
754 ddr_mn_window = window;
755 writel(window, PCI_OFFSET_SECOND_RANGE(adapter,
757 (PCIX_MN_WINDOW(adapter->ahw.pci_func))));
758 /* MUST make sure window is set before we forge on... */
759 readl(PCI_OFFSET_SECOND_RANGE(adapter,
761 (PCIX_MN_WINDOW(adapter->ahw.pci_func))));
763 addr -= (window * NETXEN_WINDOW_ONE);
764 addr += NETXEN_PCI_DDR_NET;
765 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
766 addr -= NETXEN_ADDR_OCM0;
767 addr += NETXEN_PCI_OCM0;
768 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
769 addr -= NETXEN_ADDR_OCM1;
770 addr += NETXEN_PCI_OCM1;
773 (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) {
774 /* QDR network side */
775 addr -= NETXEN_ADDR_QDR_NET;
776 window = (addr >> 22) & 0x3f;
777 if (qdr_sn_window != window) {
778 qdr_sn_window = window;
779 writel((window << 22),
780 PCI_OFFSET_SECOND_RANGE(adapter,
782 (PCIX_SN_WINDOW(adapter->ahw.pci_func))));
783 /* MUST make sure window is set before we forge on... */
784 readl(PCI_OFFSET_SECOND_RANGE(adapter,
786 (PCIX_SN_WINDOW(adapter->ahw.pci_func))));
788 addr -= (window * 0x400000);
789 addr += NETXEN_PCI_QDR_NET;
792 * peg gdb frequently accesses memory that doesn't exist,
793 * this limits the chit chat so debugging isn't slowed down.
795 if ((netxen_pci_set_window_warning_count++ < 8)
796 || (netxen_pci_set_window_warning_count % 64 == 0))
797 printk("%s: Warning:netxen_nic_pci_set_window()"
798 " Unknown address range!\n",
799 netxen_nic_driver_name);
807 netxen_nic_erase_pxe(struct netxen_adapter *adapter)
809 if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) {
810 printk(KERN_ERR "%s: erase pxe failed\n",
811 netxen_nic_driver_name);
818 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
821 int addr = NETXEN_BRDCFG_START;
822 struct netxen_board_info *boardinfo;
826 boardinfo = &adapter->ahw.boardcfg;
827 ptr32 = (u32 *) boardinfo;
829 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
831 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
837 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
838 printk("%s: ERROR reading %s board config."
839 " Read %x, expected %x\n", netxen_nic_driver_name,
840 netxen_nic_driver_name,
841 boardinfo->magic, NETXEN_BDINFO_MAGIC);
844 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
845 printk("%s: Unknown board config version."
846 " Read %x, expected %x\n", netxen_nic_driver_name,
847 boardinfo->header_version, NETXEN_BDINFO_VERSION);
851 DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
852 switch ((netxen_brdtype_t) boardinfo->board_type) {
853 case NETXEN_BRDTYPE_P2_SB35_4G:
854 adapter->ahw.board_type = NETXEN_NIC_GBE;
856 case NETXEN_BRDTYPE_P2_SB31_10G:
857 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
858 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
859 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
860 adapter->ahw.board_type = NETXEN_NIC_XGBE;
862 case NETXEN_BRDTYPE_P1_BD:
863 case NETXEN_BRDTYPE_P1_SB:
864 case NETXEN_BRDTYPE_P1_SMAX:
865 case NETXEN_BRDTYPE_P1_SOCK:
866 adapter->ahw.board_type = NETXEN_NIC_GBE;
869 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
870 boardinfo->board_type);
877 /* NIU access sections */
879 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
881 netxen_nic_write_w0(adapter,
882 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
887 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
889 new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
890 if (adapter->physical_port == 0)
891 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
894 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
899 void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
901 netxen_niu_gbe_init_port(adapter, adapter->physical_port);
905 netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off,
910 if (ADDR_IN_WINDOW1(off)) {
911 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
913 netxen_nic_pci_change_crbwindow(adapter, 0);
914 addr = pci_base_offset(adapter, off);
916 netxen_nic_pci_change_crbwindow(adapter, 1);
920 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
926 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
927 if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
928 if (adapter->phy_read
931 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
933 if (netxen_get_phy_link(status)) {
934 switch (netxen_get_phy_speed(status)) {
936 adapter->link_speed = SPEED_10;
939 adapter->link_speed = SPEED_100;
942 adapter->link_speed = SPEED_1000;
945 adapter->link_speed = -1;
948 switch (netxen_get_phy_duplex(status)) {
950 adapter->link_duplex = DUPLEX_HALF;
953 adapter->link_duplex = DUPLEX_FULL;
956 adapter->link_duplex = -1;
959 if (adapter->phy_read
962 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
964 adapter->link_autoneg = autoneg;
969 adapter->link_speed = -1;
970 adapter->link_duplex = -1;
975 void netxen_nic_flash_print(struct netxen_adapter *adapter)
980 char brd_name[NETXEN_MAX_SHORT_NAME];
985 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
987 adapter->driver_mismatch = 0;
989 ptr32 = (u32 *)&serial_num;
990 addr = NETXEN_USER_START +
991 offsetof(struct netxen_new_user_info, serial_num);
992 for (i = 0; i < 8; i++) {
993 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
994 printk("%s: ERROR reading %s board userarea.\n",
995 netxen_nic_driver_name,
996 netxen_nic_driver_name);
997 adapter->driver_mismatch = 1;
1001 addr += sizeof(u32);
1004 fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
1005 NETXEN_FW_VERSION_MAJOR));
1006 fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
1007 NETXEN_FW_VERSION_MINOR));
1009 readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
1011 if (adapter->portnum == 0) {
1012 get_brd_name_by_type(board_info->board_type, brd_name);
1014 printk("NetXen %s Board S/N %s Chip id 0x%x\n",
1015 brd_name, serial_num, board_info->chip_id);
1016 printk("NetXen Firmware version %d.%d.%d\n", fw_major,
1017 fw_minor, fw_build);
1020 if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
1021 adapter->driver_mismatch = 1;
1023 if (fw_minor != _NETXEN_NIC_LINUX_MINOR &&
1024 fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) {
1025 adapter->driver_mismatch = 1;
1027 if (adapter->driver_mismatch) {
1028 printk(KERN_ERR "%s: driver and firmware version mismatch\n",
1029 adapter->netdev->name);
1033 switch (adapter->ahw.board_type) {
1034 case NETXEN_NIC_GBE:
1035 dev_info(&adapter->pdev->dev, "%s: GbE port initialized\n",
1036 adapter->netdev->name);
1038 case NETXEN_NIC_XGBE:
1039 dev_info(&adapter->pdev->dev, "%s: XGbE port initialized\n",
1040 adapter->netdev->name);