2 * Copyright (C) 2003 - 2006 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
30 * Source file for NIC routines to access the Phantom hardware
34 #include "netxen_nic.h"
35 #include "netxen_nic_hw.h"
36 #include "netxen_nic_phan_reg.h"
41 #define MASK(n) ((1ULL<<(n))-1)
42 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
43 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
44 #define MS_WIN(addr) (addr & 0x0ffc0000)
46 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
48 #define CRB_BLK(off) ((off >> 20) & 0x3f)
49 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
50 #define CRB_WINDOW_2M (0x130060)
51 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
52 #define CRB_INDIRECT_2M (0x1e0000UL)
54 #define CRB_WIN_LOCK_TIMEOUT 100000000
55 static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
56 {{{0, 0, 0, 0} } }, /* 0: PCI */
57 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
58 {1, 0x0110000, 0x0120000, 0x130000},
59 {1, 0x0120000, 0x0122000, 0x124000},
60 {1, 0x0130000, 0x0132000, 0x126000},
61 {1, 0x0140000, 0x0142000, 0x128000},
62 {1, 0x0150000, 0x0152000, 0x12a000},
63 {1, 0x0160000, 0x0170000, 0x110000},
64 {1, 0x0170000, 0x0172000, 0x12e000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {1, 0x01e0000, 0x01e0800, 0x122000},
72 {0, 0x0000000, 0x0000000, 0x000000} } },
73 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
74 {{{0, 0, 0, 0} } }, /* 3: */
75 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
76 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
77 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
78 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
79 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {1, 0x08f0000, 0x08f2000, 0x172000} } },
95 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {1, 0x09f0000, 0x09f2000, 0x176000} } },
111 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
127 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
143 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
144 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
145 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
146 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
147 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
148 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
149 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
150 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
151 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
152 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
153 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
154 {{{0, 0, 0, 0} } }, /* 23: */
155 {{{0, 0, 0, 0} } }, /* 24: */
156 {{{0, 0, 0, 0} } }, /* 25: */
157 {{{0, 0, 0, 0} } }, /* 26: */
158 {{{0, 0, 0, 0} } }, /* 27: */
159 {{{0, 0, 0, 0} } }, /* 28: */
160 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
161 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
162 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
163 {{{0} } }, /* 32: PCI */
164 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
165 {1, 0x2110000, 0x2120000, 0x130000},
166 {1, 0x2120000, 0x2122000, 0x124000},
167 {1, 0x2130000, 0x2132000, 0x126000},
168 {1, 0x2140000, 0x2142000, 0x128000},
169 {1, 0x2150000, 0x2152000, 0x12a000},
170 {1, 0x2160000, 0x2170000, 0x110000},
171 {1, 0x2170000, 0x2172000, 0x12e000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000} } },
180 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
186 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
187 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
188 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
189 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
190 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
191 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
192 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
193 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
194 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
195 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
196 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
197 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
199 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
200 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
201 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
202 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
203 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
204 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
205 {{{0} } }, /* 59: I2C0 */
206 {{{0} } }, /* 60: I2C1 */
207 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
208 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
209 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
213 * top 12 bits of crb internal address (hub, agent)
215 static unsigned crb_hub_agt[64] =
218 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
219 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
220 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
222 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
223 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
224 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
225 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
226 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
227 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
228 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
229 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
230 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
231 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
232 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
233 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
234 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
235 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
236 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
237 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
238 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
239 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
240 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
241 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
242 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
243 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
245 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
246 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
248 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
250 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
251 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
257 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
259 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
260 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
261 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
262 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
263 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
264 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
265 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
266 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
267 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
268 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
270 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
272 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
273 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
275 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
276 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
277 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
283 /* PCI Windowing for DDR regions. */
285 #define ADDR_IN_RANGE(addr, low, high) \
286 (((addr) <= (high)) && ((addr) >= (low)))
288 #define NETXEN_MAX_MTU 8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
289 #define NETXEN_MIN_MTU 64
290 #define NETXEN_ETH_FCS_SIZE 4
291 #define NETXEN_ENET_HEADER_SIZE 14
292 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
293 #define NETXEN_FIRMWARE_LEN ((16 * 1024) / 4)
294 #define NETXEN_NIU_HDRSIZE (0x1 << 6)
295 #define NETXEN_NIU_TLRSIZE (0x1 << 5)
297 #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
298 #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
299 #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
300 #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
302 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
304 int netxen_nic_set_mac(struct net_device *netdev, void *p)
306 struct netxen_adapter *adapter = netdev_priv(netdev);
307 struct sockaddr *addr = p;
309 if (netif_running(netdev))
312 if (!is_valid_ether_addr(addr->sa_data))
313 return -EADDRNOTAVAIL;
315 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
317 if (adapter->macaddr_set)
318 adapter->macaddr_set(adapter, addr->sa_data);
323 #define NETXEN_UNICAST_ADDR(port, index) \
324 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
325 #define NETXEN_MCAST_ADDR(port, index) \
326 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
327 #define MAC_HI(addr) \
328 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
329 #define MAC_LO(addr) \
330 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
333 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
336 u16 port = adapter->physical_port;
337 u8 *addr = adapter->netdev->dev_addr;
339 if (adapter->mc_enabled)
342 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
343 val |= (1UL << (28+port));
344 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
346 /* add broadcast addr to filter */
348 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
349 netxen_crb_writelit_adapter(adapter,
350 NETXEN_UNICAST_ADDR(port, 0)+4, val);
352 /* add station addr to filter */
354 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
356 netxen_crb_writelit_adapter(adapter,
357 NETXEN_UNICAST_ADDR(port, 1)+4, val);
359 adapter->mc_enabled = 1;
364 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
367 u16 port = adapter->physical_port;
368 u8 *addr = adapter->netdev->dev_addr;
370 if (!adapter->mc_enabled)
373 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
374 val &= ~(1UL << (28+port));
375 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
378 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
380 netxen_crb_writelit_adapter(adapter,
381 NETXEN_UNICAST_ADDR(port, 0)+4, val);
383 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
384 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
386 adapter->mc_enabled = 0;
391 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
395 u16 port = adapter->physical_port;
400 netxen_crb_writelit_adapter(adapter,
401 NETXEN_MCAST_ADDR(port, index), hi);
402 netxen_crb_writelit_adapter(adapter,
403 NETXEN_MCAST_ADDR(port, index)+4, lo);
409 * netxen_nic_set_multi - Multicast
411 void netxen_nic_set_multi(struct net_device *netdev)
413 struct netxen_adapter *adapter = netdev_priv(netdev);
414 struct dev_mc_list *mc_ptr;
418 memset(null_addr, 0, 6);
420 if (netdev->flags & IFF_PROMISC) {
422 adapter->set_promisc(adapter,
423 NETXEN_NIU_PROMISC_MODE);
425 /* Full promiscuous mode */
426 netxen_nic_disable_mcast_filter(adapter);
431 if (netdev->mc_count == 0) {
432 adapter->set_promisc(adapter,
433 NETXEN_NIU_NON_PROMISC_MODE);
434 netxen_nic_disable_mcast_filter(adapter);
438 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
439 if (netdev->flags & IFF_ALLMULTI ||
440 netdev->mc_count > adapter->max_mc_count) {
441 netxen_nic_disable_mcast_filter(adapter);
445 netxen_nic_enable_mcast_filter(adapter);
447 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
448 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
450 if (index != netdev->mc_count)
451 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
452 netxen_nic_driver_name, netdev->name);
454 /* Clear out remaining addresses */
455 for (; index < adapter->max_mc_count; index++)
456 netxen_nic_set_mcast_addr(adapter, index, null_addr);
460 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
461 * @returns 0 on success, negative on failure
463 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
465 struct netxen_adapter *adapter = netdev_priv(netdev);
466 int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
468 if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
469 printk(KERN_ERR "%s: %s %d is not supported.\n",
470 netxen_nic_driver_name, netdev->name, mtu);
474 if (adapter->set_mtu)
475 adapter->set_mtu(adapter, mtu);
481 void netxen_tso_check(struct netxen_adapter *adapter,
482 struct cmd_desc_type0 *desc, struct sk_buff *skb)
485 desc->total_hdr_length = (sizeof(struct ethhdr) +
486 ip_hdrlen(skb) + tcp_hdrlen(skb));
487 netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO);
488 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
489 if (ip_hdr(skb)->protocol == IPPROTO_TCP) {
490 netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT);
491 } else if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
492 netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT);
497 desc->tcp_hdr_offset = skb_transport_offset(skb);
498 desc->ip_hdr_offset = skb_network_offset(skb);
501 int netxen_is_flash_supported(struct netxen_adapter *adapter)
503 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
504 int addr, val01, val02, i, j;
506 /* if the flash size less than 4Mb, make huge war cry and die */
507 for (j = 1; j < 4; j++) {
508 addr = j * NETXEN_NIC_WINDOW_MARGIN;
509 for (i = 0; i < ARRAY_SIZE(locs); i++) {
510 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
511 && netxen_rom_fast_read(adapter, (addr + locs[i]),
523 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
524 int size, __le32 * buf)
532 for (i = 0; i < size / sizeof(u32); i++) {
533 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
535 *ptr32 = cpu_to_le32(v);
539 if ((char *)buf + size > (char *)ptr32) {
541 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
543 local = cpu_to_le32(v);
544 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
550 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[])
552 __le32 *pmac = (__le32 *) & mac[0];
554 if (netxen_get_flash_block(adapter,
556 offsetof(struct netxen_new_user_info,
558 FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
561 if (*mac == cpu_to_le64(~0ULL)) {
562 if (netxen_get_flash_block(adapter,
563 NETXEN_USER_START_OLD +
564 offsetof(struct netxen_user_old_info,
566 FLASH_NUM_PORTS * sizeof(u64),
569 if (*mac == cpu_to_le64(~0ULL))
575 #define CRB_WIN_LOCK_TIMEOUT 100000000
577 static int crb_win_lock(struct netxen_adapter *adapter)
579 int done = 0, timeout = 0;
582 /* acquire semaphore3 from PCI HW block */
583 adapter->hw_read_wx(adapter,
584 NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4);
587 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
592 netxen_crb_writelit_adapter(adapter,
593 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
597 static void crb_win_unlock(struct netxen_adapter *adapter)
601 adapter->hw_read_wx(adapter,
602 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4);
606 * Changes the CRB window to the specified window.
609 netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
611 void __iomem *offset;
614 uint8_t func = adapter->ahw.pci_func;
616 if (adapter->curr_window == wndw)
619 * Move the CRB window.
620 * We need to write to the "direct access" region of PCI
621 * to avoid a race condition where the window register has
622 * not been successfully written across CRB before the target
623 * register address is received by PCI. The direct region bypasses
626 offset = PCI_OFFSET_SECOND_RANGE(adapter,
627 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
630 wndw = NETXEN_WINDOW_ONE;
632 writel(wndw, offset);
634 /* MUST make sure window is set before we forge on... */
635 while ((tmp = readl(offset)) != wndw) {
636 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
637 "registered properly: 0x%08x.\n",
638 netxen_nic_driver_name, __func__, tmp);
645 if (wndw == NETXEN_WINDOW_ONE)
646 adapter->curr_window = 1;
648 adapter->curr_window = 0;
652 * Return -1 if off is not valid,
653 * 1 if window access is needed. 'off' is set to offset from
654 * CRB space in 128M pci map
655 * 0 if no window access is needed. 'off' is set to 2M addr
656 * In: 'off' is offset from base in 128M pci map
659 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
662 unsigned long end = *off + len;
663 crb_128M_2M_sub_block_map_t *m;
666 if (*off >= NETXEN_CRB_MAX)
669 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
670 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
671 (ulong)adapter->ahw.pci_base0;
675 if (*off < NETXEN_PCI_CRBSPACE)
678 *off -= NETXEN_PCI_CRBSPACE;
684 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
686 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
687 *off = *off + m->start_2M - m->start_128M +
688 (ulong)adapter->ahw.pci_base0;
693 * Not in direct map, use crb window
699 * In: 'off' is offset from CRB space in 128M pci map
700 * Out: 'off' is 2M pci map addr
701 * side effect: lock crb window
704 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
708 adapter->crb_win = CRB_HI(*off);
709 writel(adapter->crb_win, (void *)(CRB_WINDOW_2M +
710 adapter->ahw.pci_base0));
712 * Read back value to make sure write has gone through before trying
715 win_read = readl((void *)(CRB_WINDOW_2M + adapter->ahw.pci_base0));
716 if (win_read != adapter->crb_win) {
717 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
718 "Read crbwin (0x%x), off=0x%lx\n",
719 __func__, adapter->crb_win, win_read, *off);
721 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
722 (ulong)adapter->ahw.pci_base0;
725 int netxen_load_firmware(struct netxen_adapter *adapter)
729 u32 flashaddr = NETXEN_BOOTLD_START, memaddr = NETXEN_BOOTLD_START;
731 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START)/4;
733 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
734 adapter->pci_write_normalize(adapter,
735 NETXEN_ROMUSB_GLB_CAS_RST, 1);
737 for (i = 0; i < size; i++) {
738 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0)
741 adapter->pci_mem_write(adapter, memaddr, &data, 4);
748 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
749 adapter->pci_write_normalize(adapter,
750 NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
752 adapter->pci_write_normalize(adapter,
753 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
754 adapter->pci_write_normalize(adapter,
755 NETXEN_ROMUSB_GLB_CAS_RST, 0);
762 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
763 ulong off, void *data, int len)
767 if (ADDR_IN_WINDOW1(off)) {
768 addr = NETXEN_CRB_NORMALIZE(adapter, off);
769 } else { /* Window 0 */
770 addr = pci_base_offset(adapter, off);
771 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
774 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
775 " data %llx len %d\n",
776 pci_base(adapter, off), off, addr,
777 *(unsigned long long *)data, len);
779 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
785 writeb(*(u8 *) data, addr);
788 writew(*(u16 *) data, addr);
791 writel(*(u32 *) data, addr);
794 writeq(*(u64 *) data, addr);
798 "writing data %lx to offset %llx, num words=%d\n",
799 *(unsigned long *)data, off, (len >> 3));
801 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
805 if (!ADDR_IN_WINDOW1(off))
806 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
812 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
813 ulong off, void *data, int len)
817 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
818 addr = NETXEN_CRB_NORMALIZE(adapter, off);
819 } else { /* Window 0 */
820 addr = pci_base_offset(adapter, off);
821 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
824 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
825 pci_base(adapter, off), off, addr);
827 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
832 *(u8 *) data = readb(addr);
835 *(u16 *) data = readw(addr);
838 *(u32 *) data = readl(addr);
841 *(u64 *) data = readq(addr);
844 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
848 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
850 if (!ADDR_IN_WINDOW1(off))
851 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
857 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
858 ulong off, void *data, int len)
860 unsigned long flags = 0;
863 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
866 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
873 write_lock_irqsave(&adapter->adapter_lock, flags);
874 crb_win_lock(adapter);
875 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
878 DPRINTK(1, INFO, "write data %lx to offset %llx, len=%d\n",
879 *(unsigned long *)data, off, len);
883 writeb(*(uint8_t *)data, (void *)off);
886 writew(*(uint16_t *)data, (void *)off);
889 writel(*(uint32_t *)data, (void *)off);
892 writeq(*(uint64_t *)data, (void *)off);
896 "writing data %lx to offset %llx, num words=%d\n",
897 *(unsigned long *)data, off, (len>>3));
901 crb_win_unlock(adapter);
902 write_unlock_irqrestore(&adapter->adapter_lock, flags);
909 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
910 ulong off, void *data, int len)
912 unsigned long flags = 0;
915 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
918 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
925 write_lock_irqsave(&adapter->adapter_lock, flags);
926 crb_win_lock(adapter);
927 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
930 DPRINTK(1, INFO, "read from offset %lx, len=%d\n", off, len);
934 *(uint8_t *)data = readb((void *)off);
937 *(uint16_t *)data = readw((void *)off);
940 *(uint32_t *)data = readl((void *)off);
943 *(uint64_t *)data = readq((void *)off);
949 DPRINTK(1, INFO, "read %lx\n", *(unsigned long *)data);
952 crb_win_unlock(adapter);
953 write_unlock_irqrestore(&adapter->adapter_lock, flags);
959 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
961 adapter->hw_write_wx(adapter, off, &val, 4);
964 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
967 adapter->hw_read_wx(adapter, off, &val, 4);
971 /* Change the window to 0, write and change back to window 1. */
972 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
974 adapter->hw_write_wx(adapter, index, &value, 4);
977 /* Change the window to 0, read and change back to window 1. */
978 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value)
980 adapter->hw_read_wx(adapter, index, value, 4);
983 void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
985 adapter->hw_write_wx(adapter, index, &value, 4);
988 void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value)
990 adapter->hw_read_wx(adapter, index, value, 4);
994 * check memory access boundary.
995 * used by test agent. support ddr access only for now
998 netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
999 unsigned long long addr, int size)
1001 if (!ADDR_IN_RANGE(addr,
1002 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1003 !ADDR_IN_RANGE(addr+size-1,
1004 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1005 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1012 static int netxen_pci_set_window_warning_count;
1015 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1016 unsigned long long addr)
1018 void __iomem *offset;
1020 unsigned long long qdr_max;
1021 uint8_t func = adapter->ahw.pci_func;
1023 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1024 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1026 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1029 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1030 /* DDR network side */
1031 addr -= NETXEN_ADDR_DDR_NET;
1032 window = (addr >> 25) & 0x3ff;
1033 if (adapter->ahw.ddr_mn_window != window) {
1034 adapter->ahw.ddr_mn_window = window;
1035 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1036 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1037 writel(window, offset);
1038 /* MUST make sure window is set before we forge on... */
1041 addr -= (window * NETXEN_WINDOW_ONE);
1042 addr += NETXEN_PCI_DDR_NET;
1043 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1044 addr -= NETXEN_ADDR_OCM0;
1045 addr += NETXEN_PCI_OCM0;
1046 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1047 addr -= NETXEN_ADDR_OCM1;
1048 addr += NETXEN_PCI_OCM1;
1049 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1050 /* QDR network side */
1051 addr -= NETXEN_ADDR_QDR_NET;
1052 window = (addr >> 22) & 0x3f;
1053 if (adapter->ahw.qdr_sn_window != window) {
1054 adapter->ahw.qdr_sn_window = window;
1055 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1056 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1057 writel((window << 22), offset);
1058 /* MUST make sure window is set before we forge on... */
1061 addr -= (window * 0x400000);
1062 addr += NETXEN_PCI_QDR_NET;
1065 * peg gdb frequently accesses memory that doesn't exist,
1066 * this limits the chit chat so debugging isn't slowed down.
1068 if ((netxen_pci_set_window_warning_count++ < 8)
1069 || (netxen_pci_set_window_warning_count % 64 == 0))
1070 printk("%s: Warning:netxen_nic_pci_set_window()"
1071 " Unknown address range!\n",
1072 netxen_nic_driver_name);
1079 * Note : only 32-bit writes!
1081 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1084 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1088 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1090 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1093 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1096 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1099 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off)
1101 return readl(NETXEN_CRB_NORMALIZE(adapter, off));
1105 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1106 unsigned long long addr)
1111 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1112 /* DDR network side */
1113 window = MN_WIN(addr);
1114 adapter->ahw.ddr_mn_window = window;
1115 adapter->hw_write_wx(adapter,
1116 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1118 adapter->hw_read_wx(adapter,
1119 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1121 if ((win_read << 17) != window) {
1122 printk(KERN_INFO "Written MNwin (0x%x) != "
1123 "Read MNwin (0x%x)\n", window, win_read);
1125 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1126 } else if (ADDR_IN_RANGE(addr,
1127 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1128 if ((addr & 0x00ff800) == 0xff800) {
1129 printk("%s: QM access not handled.\n", __func__);
1133 window = OCM_WIN(addr);
1134 adapter->ahw.ddr_mn_window = window;
1135 adapter->hw_write_wx(adapter,
1136 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1138 adapter->hw_read_wx(adapter,
1139 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1141 if ((win_read >> 7) != window) {
1142 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1143 "Read OCMwin (0x%x)\n",
1144 __func__, window, win_read);
1146 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1148 } else if (ADDR_IN_RANGE(addr,
1149 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1150 /* QDR network side */
1151 window = MS_WIN(addr);
1152 adapter->ahw.qdr_sn_window = window;
1153 adapter->hw_write_wx(adapter,
1154 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1156 adapter->hw_read_wx(adapter,
1157 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1159 if (win_read != window) {
1160 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1161 "Read MSwin (0x%x)\n",
1162 __func__, window, win_read);
1164 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1168 * peg gdb frequently accesses memory that doesn't exist,
1169 * this limits the chit chat so debugging isn't slowed down.
1171 if ((netxen_pci_set_window_warning_count++ < 8)
1172 || (netxen_pci_set_window_warning_count%64 == 0)) {
1173 printk("%s: Warning:%s Unknown address range!\n",
1174 __func__, netxen_nic_driver_name);
1181 static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1182 unsigned long long addr)
1185 unsigned long long qdr_max;
1187 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1188 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1190 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1192 if (ADDR_IN_RANGE(addr,
1193 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1194 /* DDR network side */
1195 BUG(); /* MN access can not come here */
1196 } else if (ADDR_IN_RANGE(addr,
1197 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1199 } else if (ADDR_IN_RANGE(addr,
1200 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1202 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1203 /* QDR network side */
1204 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1205 if (adapter->ahw.qdr_sn_window == window)
1212 static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1213 u64 off, void *data, int size)
1215 unsigned long flags;
1219 uint8_t *mem_ptr = NULL;
1220 unsigned long mem_base;
1221 unsigned long mem_page;
1223 write_lock_irqsave(&adapter->adapter_lock, flags);
1226 * If attempting to access unknown address or straddle hw windows,
1229 start = adapter->pci_set_window(adapter, off);
1230 if ((start == -1UL) ||
1231 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1232 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1233 printk(KERN_ERR "%s out of bound pci memory access. "
1234 "offset is 0x%llx\n", netxen_nic_driver_name, off);
1238 addr = (void *)(pci_base_offset(adapter, start));
1240 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1241 mem_base = pci_resource_start(adapter->pdev, 0);
1242 mem_page = start & PAGE_MASK;
1243 /* Map two pages whenever user tries to access addresses in two
1246 if (mem_page != ((start + size - 1) & PAGE_MASK))
1247 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1249 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1250 if (mem_ptr == 0UL) {
1251 *(uint8_t *)data = 0;
1255 addr += start & (PAGE_SIZE - 1);
1256 write_lock_irqsave(&adapter->adapter_lock, flags);
1261 *(uint8_t *)data = readb(addr);
1264 *(uint16_t *)data = readw(addr);
1267 *(uint32_t *)data = readl(addr);
1270 *(uint64_t *)data = readq(addr);
1276 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1277 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1285 netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1286 void *data, int size)
1288 unsigned long flags;
1292 uint8_t *mem_ptr = NULL;
1293 unsigned long mem_base;
1294 unsigned long mem_page;
1296 write_lock_irqsave(&adapter->adapter_lock, flags);
1299 * If attempting to access unknown address or straddle hw windows,
1302 start = adapter->pci_set_window(adapter, off);
1303 if ((start == -1UL) ||
1304 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1305 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1306 printk(KERN_ERR "%s out of bound pci memory access. "
1307 "offset is 0x%llx\n", netxen_nic_driver_name, off);
1311 addr = (void *)(pci_base_offset(adapter, start));
1313 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1314 mem_base = pci_resource_start(adapter->pdev, 0);
1315 mem_page = start & PAGE_MASK;
1316 /* Map two pages whenever user tries to access addresses in two
1317 * consecutive pages.
1319 if (mem_page != ((start + size - 1) & PAGE_MASK))
1320 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1322 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1326 addr += start & (PAGE_SIZE - 1);
1327 write_lock_irqsave(&adapter->adapter_lock, flags);
1332 writeb(*(uint8_t *)data, addr);
1335 writew(*(uint16_t *)data, addr);
1338 writel(*(uint32_t *)data, addr);
1341 writeq(*(uint64_t *)data, addr);
1347 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1348 DPRINTK(1, INFO, "writing data %llx to offset %llx\n",
1349 *(unsigned long long *)data, start);
1355 #define MAX_CTL_CHECK 1000
1358 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1359 u64 off, void *data, int size)
1361 unsigned long flags, mem_crb;
1362 int i, j, ret = 0, loop, sz[2], off0;
1364 uint64_t off8, tmpw, word[2] = {0, 0};
1367 * If not MN, go check for MS or invalid.
1369 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1370 return netxen_nic_pci_mem_write_direct(adapter,
1373 off8 = off & 0xfffffff8;
1375 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1376 sz[1] = size - sz[0];
1377 loop = ((off0 + size - 1) >> 3) + 1;
1378 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1380 if ((size != 8) || (off0 != 0)) {
1381 for (i = 0; i < loop; i++) {
1382 if (adapter->pci_mem_read(adapter,
1383 off8 + (i << 3), &word[i], 8))
1390 tmpw = *((uint8_t *)data);
1393 tmpw = *((uint16_t *)data);
1396 tmpw = *((uint32_t *)data);
1400 tmpw = *((uint64_t *)data);
1403 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1404 word[0] |= tmpw << (off0 * 8);
1407 word[1] &= ~(~0ULL << (sz[1] * 8));
1408 word[1] |= tmpw >> (sz[0] * 8);
1411 write_lock_irqsave(&adapter->adapter_lock, flags);
1412 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1414 for (i = 0; i < loop; i++) {
1415 writel((uint32_t)(off8 + (i << 3)),
1416 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1418 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1419 writel(word[i] & 0xffffffff,
1420 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_LO));
1421 writel((word[i] >> 32) & 0xffffffff,
1422 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_HI));
1423 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1424 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1425 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1426 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1428 for (j = 0; j < MAX_CTL_CHECK; j++) {
1430 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1431 if ((temp & MIU_TA_CTL_BUSY) == 0)
1435 if (j >= MAX_CTL_CHECK) {
1436 printk("%s: %s Fail to write through agent\n",
1437 __func__, netxen_nic_driver_name);
1443 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1444 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1449 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1450 u64 off, void *data, int size)
1452 unsigned long flags, mem_crb;
1453 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1455 uint64_t off8, val, word[2] = {0, 0};
1459 * If not MN, go check for MS or invalid.
1461 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1462 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1464 off8 = off & 0xfffffff8;
1465 off0[0] = off & 0x7;
1467 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1468 sz[1] = size - sz[0];
1469 loop = ((off0[0] + size - 1) >> 3) + 1;
1470 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1472 write_lock_irqsave(&adapter->adapter_lock, flags);
1473 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1475 for (i = 0; i < loop; i++) {
1476 writel((uint32_t)(off8 + (i << 3)),
1477 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1479 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1480 writel(MIU_TA_CTL_ENABLE,
1481 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1482 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1483 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1485 for (j = 0; j < MAX_CTL_CHECK; j++) {
1487 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1488 if ((temp & MIU_TA_CTL_BUSY) == 0)
1492 if (j >= MAX_CTL_CHECK) {
1493 printk(KERN_ERR "%s: %s Fail to read through agent\n",
1494 __func__, netxen_nic_driver_name);
1498 start = off0[i] >> 2;
1499 end = (off0[i] + sz[i] - 1) >> 2;
1500 for (k = start; k <= end; k++) {
1501 word[i] |= ((uint64_t) readl(
1503 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1507 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1508 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1510 if (j >= MAX_CTL_CHECK)
1516 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1517 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1522 *(uint8_t *)data = val;
1525 *(uint16_t *)data = val;
1528 *(uint32_t *)data = val;
1531 *(uint64_t *)data = val;
1534 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1539 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1540 u64 off, void *data, int size)
1542 int i, j, ret = 0, loop, sz[2], off0;
1544 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1547 * If not MN, go check for MS or invalid.
1549 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1550 mem_crb = NETXEN_CRB_QDR_NET;
1552 mem_crb = NETXEN_CRB_DDR_NET;
1553 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1554 return netxen_nic_pci_mem_write_direct(adapter,
1558 off8 = off & 0xfffffff8;
1560 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1561 sz[1] = size - sz[0];
1562 loop = ((off0 + size - 1) >> 3) + 1;
1564 if ((size != 8) || (off0 != 0)) {
1565 for (i = 0; i < loop; i++) {
1566 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1574 tmpw = *((uint8_t *)data);
1577 tmpw = *((uint16_t *)data);
1580 tmpw = *((uint32_t *)data);
1584 tmpw = *((uint64_t *)data);
1588 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1589 word[0] |= tmpw << (off0 * 8);
1592 word[1] &= ~(~0ULL << (sz[1] * 8));
1593 word[1] |= tmpw >> (sz[0] * 8);
1597 * don't lock here - write_wx gets the lock if each time
1598 * write_lock_irqsave(&adapter->adapter_lock, flags);
1599 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1602 for (i = 0; i < loop; i++) {
1603 temp = off8 + (i << 3);
1604 adapter->hw_write_wx(adapter,
1605 mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4);
1607 adapter->hw_write_wx(adapter,
1608 mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4);
1609 temp = word[i] & 0xffffffff;
1610 adapter->hw_write_wx(adapter,
1611 mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4);
1612 temp = (word[i] >> 32) & 0xffffffff;
1613 adapter->hw_write_wx(adapter,
1614 mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4);
1615 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1616 adapter->hw_write_wx(adapter,
1617 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1618 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1619 adapter->hw_write_wx(adapter,
1620 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1622 for (j = 0; j < MAX_CTL_CHECK; j++) {
1623 adapter->hw_read_wx(adapter,
1624 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1625 if ((temp & MIU_TA_CTL_BUSY) == 0)
1629 if (j >= MAX_CTL_CHECK) {
1630 printk(KERN_ERR "%s: Fail to write through agent\n",
1631 netxen_nic_driver_name);
1638 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1639 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1645 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1646 u64 off, void *data, int size)
1648 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1650 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1653 * If not MN, go check for MS or invalid.
1656 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1657 mem_crb = NETXEN_CRB_QDR_NET;
1659 mem_crb = NETXEN_CRB_DDR_NET;
1660 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1661 return netxen_nic_pci_mem_read_direct(adapter,
1665 off8 = off & 0xfffffff8;
1666 off0[0] = off & 0x7;
1668 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1669 sz[1] = size - sz[0];
1670 loop = ((off0[0] + size - 1) >> 3) + 1;
1673 * don't lock here - write_wx gets the lock if each time
1674 * write_lock_irqsave(&adapter->adapter_lock, flags);
1675 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1678 for (i = 0; i < loop; i++) {
1679 temp = off8 + (i << 3);
1680 adapter->hw_write_wx(adapter,
1681 mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4);
1683 adapter->hw_write_wx(adapter,
1684 mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4);
1685 temp = MIU_TA_CTL_ENABLE;
1686 adapter->hw_write_wx(adapter,
1687 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1688 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1689 adapter->hw_write_wx(adapter,
1690 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1692 for (j = 0; j < MAX_CTL_CHECK; j++) {
1693 adapter->hw_read_wx(adapter,
1694 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1695 if ((temp & MIU_TA_CTL_BUSY) == 0)
1699 if (j >= MAX_CTL_CHECK) {
1700 printk(KERN_ERR "%s: Fail to read through agent\n",
1701 netxen_nic_driver_name);
1705 start = off0[i] >> 2;
1706 end = (off0[i] + sz[i] - 1) >> 2;
1707 for (k = start; k <= end; k++) {
1708 adapter->hw_read_wx(adapter,
1709 mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4);
1710 word[i] |= ((uint64_t)temp << (32 * k));
1715 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1716 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1719 if (j >= MAX_CTL_CHECK)
1725 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1726 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1731 *(uint8_t *)data = val;
1734 *(uint16_t *)data = val;
1737 *(uint32_t *)data = val;
1740 *(uint64_t *)data = val;
1743 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1748 * Note : only 32-bit writes!
1750 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1753 adapter->hw_write_wx(adapter, off, &data, 4);
1758 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
1761 adapter->hw_read_wx(adapter, off, &temp, 4);
1765 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1768 adapter->hw_write_wx(adapter, off, &data, 4);
1771 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off)
1774 adapter->hw_read_wx(adapter, off, &temp, 4);
1780 netxen_nic_erase_pxe(struct netxen_adapter *adapter)
1782 if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) {
1783 printk(KERN_ERR "%s: erase pxe failed\n",
1784 netxen_nic_driver_name);
1791 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1794 int addr = NETXEN_BRDCFG_START;
1795 struct netxen_board_info *boardinfo;
1799 boardinfo = &adapter->ahw.boardcfg;
1800 ptr32 = (u32 *) boardinfo;
1802 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
1804 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
1808 addr += sizeof(u32);
1810 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
1811 printk("%s: ERROR reading %s board config."
1812 " Read %x, expected %x\n", netxen_nic_driver_name,
1813 netxen_nic_driver_name,
1814 boardinfo->magic, NETXEN_BDINFO_MAGIC);
1817 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
1818 printk("%s: Unknown board config version."
1819 " Read %x, expected %x\n", netxen_nic_driver_name,
1820 boardinfo->header_version, NETXEN_BDINFO_VERSION);
1824 DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
1825 switch ((netxen_brdtype_t) boardinfo->board_type) {
1826 case NETXEN_BRDTYPE_P2_SB35_4G:
1827 adapter->ahw.board_type = NETXEN_NIC_GBE;
1829 case NETXEN_BRDTYPE_P2_SB31_10G:
1830 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1831 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1832 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
1833 case NETXEN_BRDTYPE_P3_HMEZ:
1834 case NETXEN_BRDTYPE_P3_XG_LOM:
1835 case NETXEN_BRDTYPE_P3_10G_CX4:
1836 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1837 case NETXEN_BRDTYPE_P3_IMEZ:
1838 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
1839 case NETXEN_BRDTYPE_P3_10G_XFP:
1840 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1842 adapter->ahw.board_type = NETXEN_NIC_XGBE;
1844 case NETXEN_BRDTYPE_P1_BD:
1845 case NETXEN_BRDTYPE_P1_SB:
1846 case NETXEN_BRDTYPE_P1_SMAX:
1847 case NETXEN_BRDTYPE_P1_SOCK:
1848 case NETXEN_BRDTYPE_P3_REF_QG:
1849 case NETXEN_BRDTYPE_P3_4_GB:
1850 case NETXEN_BRDTYPE_P3_4_GB_MM:
1852 adapter->ahw.board_type = NETXEN_NIC_GBE;
1855 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
1856 boardinfo->board_type);
1863 /* NIU access sections */
1865 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
1867 netxen_nic_write_w0(adapter,
1868 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
1873 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1875 new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
1876 if (adapter->physical_port == 0)
1877 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
1880 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
1885 void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
1887 netxen_niu_gbe_init_port(adapter, adapter->physical_port);
1891 netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1892 unsigned long off, int data)
1894 adapter->hw_write_wx(adapter, off, &data, 4);
1897 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
1903 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
1904 if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
1905 if (adapter->phy_read
1908 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1910 if (netxen_get_phy_link(status)) {
1911 switch (netxen_get_phy_speed(status)) {
1913 adapter->link_speed = SPEED_10;
1916 adapter->link_speed = SPEED_100;
1919 adapter->link_speed = SPEED_1000;
1922 adapter->link_speed = -1;
1925 switch (netxen_get_phy_duplex(status)) {
1927 adapter->link_duplex = DUPLEX_HALF;
1930 adapter->link_duplex = DUPLEX_FULL;
1933 adapter->link_duplex = -1;
1936 if (adapter->phy_read
1939 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1941 adapter->link_autoneg = autoneg;
1946 adapter->link_speed = -1;
1947 adapter->link_duplex = -1;
1952 void netxen_nic_flash_print(struct netxen_adapter *adapter)
1957 char brd_name[NETXEN_MAX_SHORT_NAME];
1958 char serial_num[32];
1962 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
1964 adapter->driver_mismatch = 0;
1966 ptr32 = (u32 *)&serial_num;
1967 addr = NETXEN_USER_START +
1968 offsetof(struct netxen_new_user_info, serial_num);
1969 for (i = 0; i < 8; i++) {
1970 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
1971 printk("%s: ERROR reading %s board userarea.\n",
1972 netxen_nic_driver_name,
1973 netxen_nic_driver_name);
1974 adapter->driver_mismatch = 1;
1978 addr += sizeof(u32);
1981 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4);
1982 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4);
1983 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4);
1985 adapter->fw_major = fw_major;
1987 if (adapter->portnum == 0) {
1988 get_brd_name_by_type(board_info->board_type, brd_name);
1990 printk("NetXen %s Board S/N %s Chip id 0x%x\n",
1991 brd_name, serial_num, board_info->chip_id);
1992 printk("NetXen Firmware version %d.%d.%d\n", fw_major,
1993 fw_minor, fw_build);
1996 if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
1997 adapter->driver_mismatch = 1;
1999 if (fw_minor != _NETXEN_NIC_LINUX_MINOR &&
2000 fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) {
2001 adapter->driver_mismatch = 1;
2003 if (adapter->driver_mismatch) {
2004 printk(KERN_ERR "%s: driver and firmware version mismatch\n",
2005 adapter->netdev->name);