2 * Copyright (C) 2003 - 2006 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
30 #ifndef _NETXEN_NIC_H_
31 #define _NETXEN_NIC_H_
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/types.h>
36 #include <linux/compiler.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
39 #include <linux/init.h>
40 #include <linux/ioport.h>
41 #include <linux/pci.h>
42 #include <linux/netdevice.h>
43 #include <linux/etherdevice.h>
46 #include <linux/tcp.h>
47 #include <linux/skbuff.h>
48 #include <linux/version.h>
50 #include <linux/ethtool.h>
51 #include <linux/mii.h>
52 #include <linux/interrupt.h>
53 #include <linux/timer.h>
56 #include <linux/mman.h>
58 #include <asm/system.h>
60 #include <asm/byteorder.h>
61 #include <asm/uaccess.h>
62 #include <asm/pgtable.h>
64 #include "netxen_nic_hw.h"
66 #define _NETXEN_NIC_LINUX_MAJOR 3
67 #define _NETXEN_NIC_LINUX_MINOR 4
68 #define _NETXEN_NIC_LINUX_SUBVERSION 18
69 #define NETXEN_NIC_LINUX_VERSIONID "3.4.18"
71 #define NETXEN_NUM_FLASH_SECTORS (64)
72 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
73 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
74 * NETXEN_FLASH_SECTOR_SIZE)
76 #define PHAN_VENDOR_ID 0x4040
78 #define RCV_DESC_RINGSIZE \
79 (sizeof(struct rcv_desc) * adapter->max_rx_desc_count)
80 #define STATUS_DESC_RINGSIZE \
81 (sizeof(struct status_desc)* adapter->max_rx_desc_count)
82 #define LRO_DESC_RINGSIZE \
83 (sizeof(rcvDesc_t) * adapter->max_lro_rx_desc_count)
85 (sizeof(struct netxen_cmd_buffer) * adapter->max_tx_desc_count)
86 #define RCV_BUFFSIZE \
87 (sizeof(struct netxen_rx_buffer) * rds_ring->max_rx_desc_count)
88 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
90 #define NETXEN_NETDEV_STATUS 0x1
91 #define NETXEN_RCV_PRODUCER_OFFSET 0
92 #define NETXEN_RCV_PEG_DB_ID 2
93 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
94 #define FLASH_SUCCESS 0
96 #define ADDR_IN_WINDOW1(off) \
97 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
100 * normalize a 64MB crb address to 32MB PCI window
101 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
103 #define NETXEN_CRB_NORMAL(reg) \
104 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
106 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
107 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
109 #define DB_NORMALIZE(adapter, off) \
110 (adapter->ahw.db_base + (off))
112 #define NX_P2_C0 0x24
113 #define NX_P2_C1 0x25
114 #define NX_P3_A0 0x30
115 #define NX_P3_A2 0x30
116 #define NX_P3_B0 0x40
117 #define NX_P3_B1 0x41
119 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
120 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
122 #define FIRST_PAGE_GROUP_START 0
123 #define FIRST_PAGE_GROUP_END 0x100000
125 #define SECOND_PAGE_GROUP_START 0x6000000
126 #define SECOND_PAGE_GROUP_END 0x68BC000
128 #define THIRD_PAGE_GROUP_START 0x70E4000
129 #define THIRD_PAGE_GROUP_END 0x8000000
131 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
132 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
133 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
135 #define P2_MAX_MTU (8000)
136 #define P3_MAX_MTU (9600)
137 #define NX_ETHERMTU 1500
138 #define NX_MAX_ETHERHDR 32 /* This contains some padding */
140 #define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
141 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
142 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
143 #define NX_CT_DEFAULT_RX_BUF_LEN 2048
145 #define MAX_RX_BUFFER_LENGTH 1760
146 #define MAX_RX_JUMBO_BUFFER_LENGTH 8062
147 #define MAX_RX_LRO_BUFFER_LENGTH ((48*1024)-512)
148 #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2)
149 #define RX_JUMBO_DMA_MAP_LEN \
150 (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
151 #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2)
154 * Maximum number of ring contexts
156 #define MAX_RING_CTX 1
158 /* Opcodes to be used with the commands */
159 #define TX_ETHER_PKT 0x01
160 #define TX_TCP_PKT 0x02
161 #define TX_UDP_PKT 0x03
162 #define TX_IP_PKT 0x04
163 #define TX_TCP_LSO 0x05
164 #define TX_TCP_LSO6 0x06
165 #define TX_IPSEC 0x07
166 #define TX_IPSEC_CMD 0x0a
167 #define TX_TCPV6_PKT 0x0b
168 #define TX_UDPV6_PKT 0x0c
170 /* The following opcodes are for internal consumption. */
171 #define NETXEN_CONTROL_OP 0x10
172 #define PEGNET_REQUEST 0x11
174 #define MAX_NUM_CARDS 4
176 #define MAX_BUFFERS_PER_CMD 32
179 * Following are the states of the Phantom. Phantom will set them and
180 * Host will read to check if the fields are correct.
182 #define PHAN_INITIALIZE_START 0xff00
183 #define PHAN_INITIALIZE_FAILED 0xffff
184 #define PHAN_INITIALIZE_COMPLETE 0xff01
186 /* Host writes the following to notify that it has done the init-handshake */
187 #define PHAN_INITIALIZE_ACK 0xf00f
189 #define NUM_RCV_DESC_RINGS 3 /* No of Rcv Descriptor contexts */
191 /* descriptor types */
192 #define RCV_DESC_NORMAL 0x01
193 #define RCV_DESC_JUMBO 0x02
194 #define RCV_DESC_LRO 0x04
195 #define RCV_DESC_NORMAL_CTXID 0
196 #define RCV_DESC_JUMBO_CTXID 1
197 #define RCV_DESC_LRO_CTXID 2
199 #define RCV_DESC_TYPE(ID) \
200 ((ID == RCV_DESC_JUMBO_CTXID) \
202 : ((ID == RCV_DESC_LRO_CTXID) \
206 #define MAX_CMD_DESCRIPTORS 4096
207 #define MAX_RCV_DESCRIPTORS 16384
208 #define MAX_CMD_DESCRIPTORS_HOST (MAX_CMD_DESCRIPTORS / 4)
209 #define MAX_RCV_DESCRIPTORS_1G (MAX_RCV_DESCRIPTORS / 4)
210 #define MAX_RCV_DESCRIPTORS_10G 8192
211 #define MAX_JUMBO_RCV_DESCRIPTORS 1024
212 #define MAX_LRO_RCV_DESCRIPTORS 64
213 #define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS
214 #define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS
215 #define MAX_RCV_DESC MAX_RCV_DESCRIPTORS
216 #define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS
217 #define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8)
218 #define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \
219 MAX_LRO_RCV_DESCRIPTORS)
220 #define MIN_TX_COUNT 4096
221 #define MIN_RX_COUNT 4096
222 #define NETXEN_CTX_SIGNATURE 0xdee0
223 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
224 #define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */
226 #define PHAN_PEG_RCV_INITIALIZED 0xff01
227 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
229 #define get_next_index(index, length) \
230 (((index) + 1) & ((length) - 1))
232 #define get_index_range(index,length,count) \
233 (((index) + (count)) & ((length) - 1))
235 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
236 #define MPORT_MULTI_FUNCTION_MODE 0x2222
238 #include "netxen_nic_phan_reg.h"
241 * NetXen host-peg signal message structure
243 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
244 * Bit 2 : priv_id => must be 1
245 * Bit 3-17 : count => for doorbell
246 * Bit 18-27 : ctx_id => Context id
250 typedef u32 netxen_ctx_msg;
252 #define netxen_set_msg_peg_id(config_word, val) \
253 ((config_word) &= ~3, (config_word) |= val & 3)
254 #define netxen_set_msg_privid(config_word) \
255 ((config_word) |= 1 << 2)
256 #define netxen_set_msg_count(config_word, val) \
257 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
258 #define netxen_set_msg_ctxid(config_word, val) \
259 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
260 #define netxen_set_msg_opcode(config_word, val) \
261 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
263 struct netxen_rcv_context {
264 __le64 rcv_ring_addr;
265 __le32 rcv_ring_size;
269 struct netxen_ring_ctx {
271 /* one command ring */
272 __le64 cmd_consumer_offset;
273 __le64 cmd_ring_addr;
274 __le32 cmd_ring_size;
277 /* three receive rings */
278 struct netxen_rcv_context rcv_ctx[3];
280 /* one status ring */
281 __le64 sts_ring_addr;
282 __le32 sts_ring_size;
285 } __attribute__ ((aligned(64)));
288 * Following data structures describe the descriptors that will be used.
289 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
290 * we are doing LSO (above the 1500 size packet) only.
294 * The size of reference handle been changed to 16 bits to pass the MSS fields
298 #define FLAGS_CHECKSUM_ENABLED 0x01
299 #define FLAGS_LSO_ENABLED 0x02
300 #define FLAGS_IPSEC_SA_ADD 0x04
301 #define FLAGS_IPSEC_SA_DELETE 0x08
302 #define FLAGS_VLAN_TAGGED 0x10
304 #define netxen_set_cmd_desc_port(cmd_desc, var) \
305 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
306 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
307 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
309 #define netxen_set_cmd_desc_flags(cmd_desc, val) \
310 (cmd_desc)->flags_opcode = ((cmd_desc)->flags_opcode & \
311 ~cpu_to_le16(0x7f)) | cpu_to_le16((val) & 0x7f)
312 #define netxen_set_cmd_desc_opcode(cmd_desc, val) \
313 (cmd_desc)->flags_opcode = ((cmd_desc)->flags_opcode & \
314 ~cpu_to_le16((u16)0x3f << 7)) | cpu_to_le16(((val) & 0x3f) << 7)
316 #define netxen_set_cmd_desc_num_of_buff(cmd_desc, val) \
317 (cmd_desc)->num_of_buffers_total_length = \
318 ((cmd_desc)->num_of_buffers_total_length & \
319 ~cpu_to_le32(0xff)) | cpu_to_le32((val) & 0xff)
320 #define netxen_set_cmd_desc_totallength(cmd_desc, val) \
321 (cmd_desc)->num_of_buffers_total_length = \
322 ((cmd_desc)->num_of_buffers_total_length & \
323 ~cpu_to_le32((u32)0xffffff << 8)) | \
324 cpu_to_le32(((val) & 0xffffff) << 8)
326 #define netxen_get_cmd_desc_opcode(cmd_desc) \
327 ((le16_to_cpu((cmd_desc)->flags_opcode) >> 7) & 0x003f)
328 #define netxen_get_cmd_desc_totallength(cmd_desc) \
329 ((le32_to_cpu((cmd_desc)->num_of_buffers_total_length) >> 8) & 0xffffff)
331 struct cmd_desc_type0 {
332 u8 tcp_hdr_offset; /* For LSO only */
333 u8 ip_hdr_offset; /* For LSO only */
334 /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
336 /* Bit pattern: 0-7 total number of segments,
337 8-31 Total size of the packet */
338 __le32 num_of_buffers_total_length;
341 __le32 addr_low_part2;
342 __le32 addr_high_part2;
347 __le16 reference_handle; /* changed to u16 to add mss */
348 __le16 mss; /* passed by NDIS_PACKET for LSO */
349 /* Bit pattern 0-3 port, 0-3 ctx id */
351 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
352 __le16 conn_id; /* IPSec offoad only */
356 __le32 addr_low_part3;
357 __le32 addr_high_part3;
363 __le32 addr_low_part1;
364 __le32 addr_high_part1;
369 __le16 buffer1_length;
370 __le16 buffer2_length;
371 __le16 buffer3_length;
372 __le16 buffer4_length;
376 __le32 addr_low_part4;
377 __le32 addr_high_part4;
384 } __attribute__ ((aligned(64)));
386 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
388 __le16 reference_handle;
390 __le32 buffer_length; /* allocated buffer length (usually 2K) */
394 /* opcode field in status_desc */
395 #define NETXEN_NIC_RXPKT_DESC 0x04
396 #define NETXEN_OLD_RXPKT_DESC 0x3f
398 /* for status field in status_desc */
399 #define STATUS_NEED_CKSUM (1)
400 #define STATUS_CKSUM_OK (2)
402 /* owner bits of status_desc */
403 #define STATUS_OWNER_HOST (0x1)
404 #define STATUS_OWNER_PHANTOM (0x2)
406 #define NETXEN_PROT_IP (1)
407 #define NETXEN_PROT_UNKNOWN (0)
409 /* Note: sizeof(status_desc) should always be a mutliple of 2 */
411 #define netxen_get_sts_desc_lro_cnt(status_desc) \
412 ((status_desc)->lro & 0x7F)
413 #define netxen_get_sts_desc_lro_last_frag(status_desc) \
414 (((status_desc)->lro & 0x80) >> 7)
416 #define netxen_get_sts_port(sts_data) \
418 #define netxen_get_sts_status(sts_data) \
419 (((sts_data) >> 4) & 0x0F)
420 #define netxen_get_sts_type(sts_data) \
421 (((sts_data) >> 8) & 0x0F)
422 #define netxen_get_sts_totallength(sts_data) \
423 (((sts_data) >> 12) & 0xFFFF)
424 #define netxen_get_sts_refhandle(sts_data) \
425 (((sts_data) >> 28) & 0xFFFF)
426 #define netxen_get_sts_prot(sts_data) \
427 (((sts_data) >> 44) & 0x0F)
428 #define netxen_get_sts_pkt_offset(sts_data) \
429 (((sts_data) >> 48) & 0x1F)
430 #define netxen_get_sts_opcode(sts_data) \
431 (((sts_data) >> 58) & 0x03F)
433 #define netxen_get_sts_owner(status_desc) \
434 ((le64_to_cpu((status_desc)->status_desc_data) >> 56) & 0x03)
435 #define netxen_set_sts_owner(status_desc, val) { \
436 (status_desc)->status_desc_data = \
437 ((status_desc)->status_desc_data & \
438 ~cpu_to_le64(0x3ULL << 56)) | \
439 cpu_to_le64((u64)((val) & 0x3) << 56); \
443 /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
444 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
445 53-55 desc_cnt, 56-57 owner, 58-63 opcode
447 __le64 status_desc_data;
455 /* Bit pattern: 0-6 lro_count indicates frag
456 * sequence, 7 last_frag indicates last frag
460 /* chained buffers */
465 __le16 frag_handles[4];
468 } __attribute__ ((aligned(16)));
471 NETXEN_RCV_PEG_0 = 0,
474 /* The version of the main data structure */
475 #define NETXEN_BDINFO_VERSION 1
477 /* Magic number to let user know flash is programmed */
478 #define NETXEN_BDINFO_MAGIC 0x12345678
480 /* Max number of Gig ports on a Phantom board */
481 #define NETXEN_MAX_PORTS 4
484 NETXEN_BRDTYPE_P1_BD = 0x0000,
485 NETXEN_BRDTYPE_P1_SB = 0x0001,
486 NETXEN_BRDTYPE_P1_SMAX = 0x0002,
487 NETXEN_BRDTYPE_P1_SOCK = 0x0003,
489 NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
490 NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
491 NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
492 NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
493 NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,
495 NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
496 NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
497 NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f,
499 NETXEN_BRDTYPE_P3_REF_QG = 0x0021,
500 NETXEN_BRDTYPE_P3_HMEZ = 0x0022,
501 NETXEN_BRDTYPE_P3_10G_CX4_LP = 0x0023,
502 NETXEN_BRDTYPE_P3_4_GB = 0x0024,
503 NETXEN_BRDTYPE_P3_IMEZ = 0x0025,
504 NETXEN_BRDTYPE_P3_10G_SFP_PLUS = 0x0026,
505 NETXEN_BRDTYPE_P3_10000_BASE_T = 0x0027,
506 NETXEN_BRDTYPE_P3_XG_LOM = 0x0028,
507 NETXEN_BRDTYPE_P3_4_GB_MM = 0x0029,
508 NETXEN_BRDTYPE_P3_10G_CX4 = 0x0031,
509 NETXEN_BRDTYPE_P3_10G_XFP = 0x0032
514 NETXEN_BRDMFG_INVENTEC = 1
518 MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */
519 MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */
520 MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */
521 MEM_ORG_256Mbx4 = 0x3,
522 MEM_ORG_256Mbx8 = 0x4,
523 MEM_ORG_256Mbx16 = 0x5,
524 MEM_ORG_512Mbx4 = 0x6,
525 MEM_ORG_512Mbx8 = 0x7,
526 MEM_ORG_512Mbx16 = 0x8,
529 MEM_ORG_1Gbx16 = 0xb,
532 MEM_ORG_2Gbx16 = 0xe,
533 MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */
534 MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */
535 } netxen_mn_mem_org_t;
538 MEM_ORG_512Kx36 = 0x0,
541 } netxen_sn_mem_org_t;
546 MEM_DEPTH_16MB = 0x3,
547 MEM_DEPTH_32MB = 0x4,
548 MEM_DEPTH_64MB = 0x5,
549 MEM_DEPTH_128MB = 0x6,
550 MEM_DEPTH_256MB = 0x7,
551 MEM_DEPTH_512MB = 0x8,
556 MEM_DEPTH_16GB = 0xd,
558 } netxen_mem_depth_t;
560 struct netxen_board_info {
572 u32 port_mask; /* available niu ports */
573 u32 peg_mask; /* available pegs */
574 u32 icache_ok; /* can we run with icache? */
575 u32 dcache_ok; /* can we run with dcache? */
583 /* MN-related config */
584 u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
585 u32 mn_sync_shift_cclk;
586 u32 mn_sync_shift_mclk;
588 u32 mn_crystal_freq; /* in MHz */
589 u32 mn_speed; /* in MHz */
592 u32 mn_ranks_0; /* ranks per slot */
593 u32 mn_ranks_1; /* ranks per slot */
604 u32 mn_mode_reg; /* MIU DDR Mode Register */
605 u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
606 u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
607 u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
608 u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
610 /* SN-related config */
611 u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
612 u32 sn_pt_mode; /* pass through mode */
627 u32 magic; /* indicates flash has been initialized */
634 #define FLASH_NUM_PORTS (4)
636 struct netxen_flash_mac_addr {
640 struct netxen_user_old_info {
652 /* primary image status */
654 u32 secondary_present;
656 /* MAC address , 4 ports */
657 struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
659 #define FLASH_NUM_MAC_PER_PORT 32
660 struct netxen_user_info {
661 u8 flash_md5[16 * 64];
668 /* primary image status */
670 u32 secondary_present;
672 /* MAC address , 4 ports, 32 address per port */
673 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
677 /* Any user defined data */
681 * Flash Layout - new format.
683 struct netxen_new_user_info {
684 u8 flash_md5[16 * 64];
691 /* primary image status */
693 u32 secondary_present;
695 /* MAC address , 4 ports, 32 address per port */
696 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
700 /* Any user defined data */
703 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
704 #define SECONDARY_IMAGE_ABSENT 0xffffffff
705 #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
706 #define PRIMARY_IMAGE_BAD 0xffffffff
708 /* Flash memory map */
710 NETXEN_CRBINIT_START = 0, /* Crbinit section */
711 NETXEN_BRDCFG_START = 0x4000, /* board config */
712 NETXEN_INITCODE_START = 0x6000, /* pegtune code */
713 NETXEN_BOOTLD_START = 0x10000, /* bootld */
714 NETXEN_IMAGE_START = 0x43000, /* compressed image */
715 NETXEN_SECONDARY_START = 0x200000, /* backup images */
716 NETXEN_PXE_START = 0x3E0000, /* user defined region */
717 NETXEN_USER_START = 0x3E8000, /* User defined region for new boards */
718 NETXEN_FIXED_START = 0x3F0000 /* backup of crbinit */
719 } netxen_flash_map_t;
721 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */
723 #define NETXEN_FLASH_START (NETXEN_CRBINIT_START)
724 #define NETXEN_INIT_SECTOR (0)
725 #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START)
726 #define NETXEN_FLASH_CRBINIT_SIZE (0x4000)
727 #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
728 #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
729 #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START)
730 #define NETXEN_NUM_PRIMARY_SECTORS (0x20)
731 #define NETXEN_NUM_CONFIG_SECTORS (1)
732 #define PFX "NetXen: "
733 extern char netxen_nic_driver_name[];
735 /* Note: Make sure to not call this before adapter->port is valid */
736 #if !defined(NETXEN_DEBUG)
737 #define DPRINTK(klevel, fmt, args...) do { \
740 #define DPRINTK(klevel, fmt, args...) do { \
741 printk(KERN_##klevel PFX "%s: %s: " fmt, __FUNCTION__,\
742 (adapter != NULL && adapter->netdev != NULL) ? \
743 adapter->netdev->name : NULL, \
747 /* Number of status descriptors to handle per interrupt */
748 #define MAX_STATUS_HANDLE (128)
751 * netxen_skb_frag{} is to contain mapping info for each SG list. This
752 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
754 struct netxen_skb_frag {
759 #define _netxen_set_bits(config_word, start, bits, val) {\
760 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
761 unsigned long long __tvalue = (val); \
762 (config_word) &= ~__tmask; \
763 (config_word) |= (((__tvalue) << (start)) & __tmask); \
766 #define _netxen_clear_bits(config_word, start, bits) {\
767 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \
768 (config_word) &= ~__tmask; \
771 /* Following defines are for the state of the buffers */
772 #define NETXEN_BUFFER_FREE 0
773 #define NETXEN_BUFFER_BUSY 1
776 * There will be one netxen_buffer per skb packet. These will be
777 * used to save the dma info for pci_unmap_page()
779 struct netxen_cmd_buffer {
781 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
787 unsigned long time_stamp;
791 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
792 struct netxen_rx_buffer {
793 struct list_head list;
798 u32 lro_expected_frags;
799 u32 lro_current_frags;
804 #define NETXEN_NIC_GBE 0x01
805 #define NETXEN_NIC_XGBE 0x02
808 * One hardware_context{} per adapter
809 * contains interrupt info as well shared hardware info.
811 struct netxen_hardware_context {
812 void __iomem *pci_base0;
813 void __iomem *pci_base1;
814 void __iomem *pci_base2;
815 unsigned long first_page_group_end;
816 unsigned long first_page_group_start;
817 void __iomem *db_base;
818 unsigned long db_len;
819 unsigned long pci_len0;
824 unsigned long mn_win_crb;
825 unsigned long ms_win_crb;
829 struct netxen_board_info boardcfg;
831 /* Address of cmd ring in Phantom */
832 struct cmd_desc_type0 *cmd_desc_head;
833 dma_addr_t cmd_desc_phys_addr;
834 struct netxen_adapter *adapter;
838 #define RCV_RING_LRO RCV_DESC_LRO
840 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
841 #define ETHERNET_FCS_SIZE 4
843 struct netxen_adapter_stats {
861 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
862 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
864 struct nx_host_rds_ring {
867 dma_addr_t phys_addr;
868 u32 crb_rcv_producer; /* reg offset */
869 struct rcv_desc *desc_head; /* address of rx ring in Phantom */
870 u32 max_rx_desc_count;
873 struct netxen_rx_buffer *rx_buf_arr; /* rx buffers for receive */
874 struct list_head free_list;
879 * Receive context. There is one such structure per instance of the
880 * receive processing. Any state information that is relevant to
881 * the receive, and is must be in this structure. The global data may be
884 struct netxen_recv_context {
889 struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS];
890 u32 status_rx_consumer;
891 u32 crb_sts_consumer; /* reg offset */
892 dma_addr_t rcv_status_desc_phys_addr;
893 struct status_desc *rcv_status_desc_head;
896 /* New HW context creation */
898 #define NX_OS_CRB_RETRY_COUNT 4000
899 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
900 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
902 #define NX_CDRP_CLEAR 0x00000000
903 #define NX_CDRP_CMD_BIT 0x80000000
906 * All responses must have the NX_CDRP_CMD_BIT cleared
907 * in the crb NX_CDRP_CRB_OFFSET.
909 #define NX_CDRP_FORM_RSP(rsp) (rsp)
910 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
912 #define NX_CDRP_RSP_OK 0x00000001
913 #define NX_CDRP_RSP_FAIL 0x00000002
914 #define NX_CDRP_RSP_TIMEOUT 0x00000003
917 * All commands must have the NX_CDRP_CMD_BIT set in
918 * the crb NX_CDRP_CRB_OFFSET.
920 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
921 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
923 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
924 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
925 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
926 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
927 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
928 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
929 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
930 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
931 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
932 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
933 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
934 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
935 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
936 #define NX_CDRP_CMD_SET_MTU 0x00000012
937 #define NX_CDRP_CMD_MAX 0x00000013
939 #define NX_RCODE_SUCCESS 0
940 #define NX_RCODE_NO_HOST_MEM 1
941 #define NX_RCODE_NO_HOST_RESOURCE 2
942 #define NX_RCODE_NO_CARD_CRB 3
943 #define NX_RCODE_NO_CARD_MEM 4
944 #define NX_RCODE_NO_CARD_RESOURCE 5
945 #define NX_RCODE_INVALID_ARGS 6
946 #define NX_RCODE_INVALID_ACTION 7
947 #define NX_RCODE_INVALID_STATE 8
948 #define NX_RCODE_NOT_SUPPORTED 9
949 #define NX_RCODE_NOT_PERMITTED 10
950 #define NX_RCODE_NOT_READY 11
951 #define NX_RCODE_DOES_NOT_EXIST 12
952 #define NX_RCODE_ALREADY_EXISTS 13
953 #define NX_RCODE_BAD_SIGNATURE 14
954 #define NX_RCODE_CMD_NOT_IMPL 15
955 #define NX_RCODE_CMD_INVALID 16
956 #define NX_RCODE_TIMEOUT 17
957 #define NX_RCODE_CMD_FAILED 18
958 #define NX_RCODE_MAX_EXCEEDED 19
959 #define NX_RCODE_MAX 20
961 #define NX_DESTROY_CTX_RESET 0
962 #define NX_DESTROY_CTX_D3_RESET 1
963 #define NX_DESTROY_CTX_MAX 2
968 #define NX_CAP_BIT(class, bit) (1 << bit)
969 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
970 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
971 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
972 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
973 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
974 #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
975 #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
976 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
977 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
982 #define NX_HOST_CTX_STATE_FREED 0
983 #define NX_HOST_CTX_STATE_ALLOCATED 1
984 #define NX_HOST_CTX_STATE_ACTIVE 2
985 #define NX_HOST_CTX_STATE_DISABLED 3
986 #define NX_HOST_CTX_STATE_QUIESCED 4
987 #define NX_HOST_CTX_STATE_MAX 5
994 u64 host_phys_addr; /* Ring base addr */
995 u32 ring_size; /* Ring entries */
997 u16 rsvd; /* Padding */
998 } nx_hostrq_sds_ring_t;
1001 u64 host_phys_addr; /* Ring base addr */
1002 u64 buff_size; /* Packet buffer size */
1003 u32 ring_size; /* Ring entries */
1004 u32 ring_kind; /* Class of ring */
1005 } nx_hostrq_rds_ring_t;
1008 u64 host_rsp_dma_addr; /* Response dma'd here */
1009 u32 capabilities[4]; /* Flag bit vector */
1010 u32 host_int_crb_mode; /* Interrupt crb usage */
1011 u32 host_rds_crb_mode; /* RDS crb usage */
1012 /* These ring offsets are relative to data[0] below */
1013 u32 rds_ring_offset; /* Offset to RDS config */
1014 u32 sds_ring_offset; /* Offset to SDS config */
1015 u16 num_rds_rings; /* Count of RDS rings */
1016 u16 num_sds_rings; /* Count of SDS rings */
1017 u16 rsvd1; /* Padding */
1018 u16 rsvd2; /* Padding */
1019 u8 reserved[128]; /* reserve space for future expansion*/
1020 /* MUST BE 64-bit aligned.
1021 The following is packed:
1022 - N hostrq_rds_rings
1023 - N hostrq_sds_rings */
1025 } nx_hostrq_rx_ctx_t;
1028 u32 host_producer_crb; /* Crb to use */
1029 u32 rsvd1; /* Padding */
1030 } nx_cardrsp_rds_ring_t;
1033 u32 host_consumer_crb; /* Crb to use */
1034 u32 interrupt_crb; /* Crb to use */
1035 } nx_cardrsp_sds_ring_t;
1038 /* These ring offsets are relative to data[0] below */
1039 u32 rds_ring_offset; /* Offset to RDS config */
1040 u32 sds_ring_offset; /* Offset to SDS config */
1041 u32 host_ctx_state; /* Starting State */
1042 u32 num_fn_per_port; /* How many PCI fn share the port */
1043 u16 num_rds_rings; /* Count of RDS rings */
1044 u16 num_sds_rings; /* Count of SDS rings */
1045 u16 context_id; /* Handle for context */
1046 u8 phys_port; /* Physical id of port */
1047 u8 virt_port; /* Virtual/Logical id of port */
1048 u8 reserved[128]; /* save space for future expansion */
1049 /* MUST BE 64-bit aligned.
1050 The following is packed:
1051 - N cardrsp_rds_rings
1052 - N cardrs_sds_rings */
1054 } nx_cardrsp_rx_ctx_t;
1056 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
1057 (sizeof(HOSTRQ_RX) + \
1058 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
1059 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
1061 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
1062 (sizeof(CARDRSP_RX) + \
1063 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
1064 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
1071 u64 host_phys_addr; /* Ring base addr */
1072 u32 ring_size; /* Ring entries */
1073 u32 rsvd; /* Padding */
1074 } nx_hostrq_cds_ring_t;
1077 u64 host_rsp_dma_addr; /* Response dma'd here */
1078 u64 cmd_cons_dma_addr; /* */
1079 u64 dummy_dma_addr; /* */
1080 u32 capabilities[4]; /* Flag bit vector */
1081 u32 host_int_crb_mode; /* Interrupt crb usage */
1082 u32 rsvd1; /* Padding */
1083 u16 rsvd2; /* Padding */
1086 u16 rsvd3; /* Padding */
1087 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
1088 u8 reserved[128]; /* future expansion */
1089 } nx_hostrq_tx_ctx_t;
1092 u32 host_producer_crb; /* Crb to use */
1093 u32 interrupt_crb; /* Crb to use */
1094 } nx_cardrsp_cds_ring_t;
1097 u32 host_ctx_state; /* Starting state */
1098 u16 context_id; /* Handle for context */
1099 u8 phys_port; /* Physical id of port */
1100 u8 virt_port; /* Virtual/Logical id of port */
1101 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
1102 u8 reserved[128]; /* future expansion */
1103 } nx_cardrsp_tx_ctx_t;
1105 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
1106 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
1110 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
1111 #define NX_HOST_RDS_CRB_MODE_SHARED 1
1112 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
1113 #define NX_HOST_RDS_CRB_MODE_MAX 3
1115 #define NX_HOST_INT_CRB_MODE_UNIQUE 0
1116 #define NX_HOST_INT_CRB_MODE_SHARED 1
1117 #define NX_HOST_INT_CRB_MODE_NORX 2
1118 #define NX_HOST_INT_CRB_MODE_NOTX 3
1119 #define NX_HOST_INT_CRB_MODE_NORXTX 4
1124 #define MC_COUNT_P2 16
1125 #define MC_COUNT_P3 38
1127 #define NETXEN_MAC_NOOP 0
1128 #define NETXEN_MAC_ADD 1
1129 #define NETXEN_MAC_DEL 2
1131 typedef struct nx_mac_list_s {
1132 struct nx_mac_list_s *next;
1133 uint8_t mac_addr[MAX_ADDR_LEN];
1148 #define MAX_PENDING_DESC_BLOCK_SIZE 64
1150 #define NETXEN_NIC_MSI_ENABLED 0x02
1151 #define NETXEN_NIC_MSIX_ENABLED 0x04
1152 #define NETXEN_IS_MSI_FAMILY(adapter) \
1153 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1155 #define MSIX_ENTRIES_PER_ADAPTER 8
1156 #define NETXEN_MSIX_TBL_SPACE 8192
1157 #define NETXEN_PCI_REG_MSIX_TBL 0x44
1159 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
1161 struct netxen_dummy_dma {
1163 dma_addr_t phys_addr;
1166 struct netxen_adapter {
1167 struct netxen_hardware_context ahw;
1169 struct net_device *netdev;
1170 struct pci_dev *pdev;
1172 struct napi_struct napi;
1173 struct net_device_stats net_stats;
1180 uint8_t max_mc_count;
1181 nx_mac_list_t *mac_list;
1183 struct netxen_legacy_intr_set legacy_intr;
1186 struct work_struct watchdog_task;
1187 struct timer_list watchdog_timer;
1188 struct work_struct tx_timeout_task;
1192 rwlock_t adapter_lock;
1197 __le32 *cmd_consumer;
1198 u32 last_cmd_consumer;
1199 u32 crb_addr_cmd_producer;
1200 u32 crb_addr_cmd_consumer;
1202 u32 max_tx_desc_count;
1203 u32 max_rx_desc_count;
1204 u32 max_jumbo_rx_desc_count;
1205 u32 max_lro_rx_desc_count;
1211 int driver_mismatch;
1217 u8 max_possible_rss_rings;
1218 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1220 struct netxen_adapter_stats stats;
1229 struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */
1232 * Receive instances. These can be either one per port,
1233 * or one per peg, etc.
1235 struct netxen_recv_context recv_ctx[MAX_RCV_CTX];
1238 struct netxen_dummy_dma dummy_dma;
1240 /* Context interface shared between card and host */
1241 struct netxen_ring_ctx *ctx_desc;
1242 dma_addr_t ctx_desc_phys_addr;
1245 int (*enable_phy_interrupts) (struct netxen_adapter *);
1246 int (*disable_phy_interrupts) (struct netxen_adapter *);
1247 int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
1248 int (*set_mtu) (struct netxen_adapter *, int);
1249 int (*set_promisc) (struct netxen_adapter *, netxen_niu_prom_mode_t);
1250 int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
1251 int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
1252 int (*init_port) (struct netxen_adapter *, int);
1253 int (*stop_port) (struct netxen_adapter *);
1255 int (*hw_read_wx)(struct netxen_adapter *, ulong, void *, int);
1256 int (*hw_write_wx)(struct netxen_adapter *, ulong, void *, int);
1257 int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1258 int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1259 int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1260 u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1261 void (*pci_write_normalize)(struct netxen_adapter *, u64, u32);
1262 u32 (*pci_read_normalize)(struct netxen_adapter *, u64);
1263 unsigned long (*pci_set_window)(struct netxen_adapter *,
1264 unsigned long long);
1265 }; /* netxen_adapter structure */
1268 * NetXen dma watchdog control structure
1270 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
1271 * Bit 1 : disable_request => 1 req disable dma watchdog
1272 * Bit 2 : enable_request => 1 req enable dma watchdog
1276 #define netxen_set_dma_watchdog_disable_req(config_word) \
1277 _netxen_set_bits(config_word, 1, 1, 1)
1278 #define netxen_set_dma_watchdog_enable_req(config_word) \
1279 _netxen_set_bits(config_word, 2, 1, 1)
1280 #define netxen_get_dma_watchdog_enabled(config_word) \
1281 ((config_word) & 0x1)
1282 #define netxen_get_dma_watchdog_disabled(config_word) \
1283 (((config_word) >> 1) & 0x1)
1285 /* Max number of xmit producer threads that can run simultaneously */
1286 #define MAX_XMIT_PRODUCERS 16
1288 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
1289 ((adapter)->ahw.pci_base0 + (off))
1290 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
1291 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
1292 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
1293 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
1295 static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
1298 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1299 return (adapter->ahw.pci_base0 + off);
1300 } else if ((off < SECOND_PAGE_GROUP_END) &&
1301 (off >= SECOND_PAGE_GROUP_START)) {
1302 return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
1303 } else if ((off < THIRD_PAGE_GROUP_END) &&
1304 (off >= THIRD_PAGE_GROUP_START)) {
1305 return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
1310 static inline void __iomem *pci_base(struct netxen_adapter *adapter,
1313 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1314 return adapter->ahw.pci_base0;
1315 } else if ((off < SECOND_PAGE_GROUP_END) &&
1316 (off >= SECOND_PAGE_GROUP_START)) {
1317 return adapter->ahw.pci_base1;
1318 } else if ((off < THIRD_PAGE_GROUP_END) &&
1319 (off >= THIRD_PAGE_GROUP_START)) {
1320 return adapter->ahw.pci_base2;
1325 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1326 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1327 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1328 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1329 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1331 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1332 long reg, __u32 val);
1334 /* Functions available from netxen_nic_hw.c */
1335 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1336 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1337 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
1338 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
1339 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
1340 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value);
1341 void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value);
1342 void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value);
1344 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1346 int netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1347 ulong off, void *data, int len);
1348 int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1349 ulong off, void *data, int len);
1350 int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1351 u64 off, void *data, int size);
1352 int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1353 u64 off, void *data, int size);
1354 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1356 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1357 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1359 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1360 unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1361 unsigned long long addr);
1362 void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1365 int netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1366 ulong off, void *data, int len);
1367 int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1368 ulong off, void *data, int len);
1369 int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1370 u64 off, void *data, int size);
1371 int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1372 u64 off, void *data, int size);
1373 void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1374 unsigned long off, int data);
1375 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1377 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1378 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1380 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1381 unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1382 unsigned long long addr);
1384 /* Functions from netxen_nic_init.c */
1385 void netxen_free_adapter_offload(struct netxen_adapter *adapter);
1386 int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
1387 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1388 int netxen_receive_peg_ready(struct netxen_adapter *adapter);
1389 int netxen_load_firmware(struct netxen_adapter *adapter);
1390 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1392 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1393 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1394 u8 *bytes, size_t size);
1395 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1396 u8 *bytes, size_t size);
1397 int netxen_flash_unlock(struct netxen_adapter *adapter);
1398 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1399 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1400 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1401 void netxen_halt_pegs(struct netxen_adapter *adapter);
1403 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1405 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1406 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1408 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1409 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1411 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1412 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1414 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1415 int netxen_init_firmware(struct netxen_adapter *adapter);
1416 void netxen_tso_check(struct netxen_adapter *adapter,
1417 struct cmd_desc_type0 *desc, struct sk_buff *skb);
1418 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1419 void netxen_watchdog_task(struct work_struct *work);
1420 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ctx,
1422 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1423 u32 netxen_process_rcv_ring(struct netxen_adapter *adapter, int ctx, int max);
1424 void netxen_p2_nic_set_multi(struct net_device *netdev);
1425 void netxen_p3_nic_set_multi(struct net_device *netdev);
1427 u32 nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, u32 mtu);
1428 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1430 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1431 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1433 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1434 uint32_t crb_producer);
1437 * NetXen Board information
1440 #define NETXEN_MAX_SHORT_NAME 32
1441 struct netxen_brdinfo {
1442 netxen_brdtype_t brdtype; /* type of board */
1443 long ports; /* max no of physical ports */
1444 char short_name[NETXEN_MAX_SHORT_NAME];
1447 static const struct netxen_brdinfo netxen_boards[] = {
1448 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1449 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1450 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1451 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1452 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1453 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1454 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1455 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1456 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1457 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1458 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1459 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1460 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1461 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1462 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "Quad GB - March Madness"},
1463 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1464 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1467 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1469 static inline void get_brd_name_by_type(u32 type, char *name)
1472 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1473 if (netxen_boards[i].brdtype == type) {
1474 strcpy(name, netxen_boards[i].short_name);
1485 dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1489 /* check if already inactive */
1490 if (adapter->hw_read_wx(adapter,
1491 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1492 printk(KERN_ERR "failed to read dma watchdog status\n");
1494 if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
1497 /* Send the disable request */
1498 netxen_set_dma_watchdog_disable_req(ctrl);
1499 netxen_crb_writelit_adapter(adapter,
1500 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1506 dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
1510 if (adapter->hw_read_wx(adapter,
1511 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1512 printk(KERN_ERR "failed to read dma watchdog status\n");
1514 return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
1518 dma_watchdog_wakeup(struct netxen_adapter *adapter)
1522 if (adapter->hw_read_wx(adapter,
1523 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1524 printk(KERN_ERR "failed to read dma watchdog status\n");
1526 if (netxen_get_dma_watchdog_enabled(ctrl))
1529 /* send the wakeup request */
1530 netxen_set_dma_watchdog_enable_req(ctrl);
1532 netxen_crb_writelit_adapter(adapter,
1533 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1539 int netxen_is_flash_supported(struct netxen_adapter *adapter);
1540 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[]);
1541 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1542 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1545 extern struct ethtool_ops netxen_nic_ethtool_ops;
1547 #endif /* __NETXEN_NIC_H_ */