drivers/net/myri10ge/myri10ge.c

   1 /*************************************************************************
   2  * myri10ge.c: Myricom Myri-10G Ethernet driver.
   3  *
   4  * Copyright (C) 2005 - 2007 Myricom, Inc.
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. Neither the name of Myricom, Inc. nor the names of its contributors
  16  *    may be used to endorse or promote products derived from this software
  17  *    without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  *
  32  * If the eeprom on your board is not recent enough, you will need to get a
  33  * newer firmware image at:
  34  *   http://www.myri.com/scs/download-Myri10GE.html
  35  *
  36  * Contact Information:
  37  *   <help@myri.com>
  38  *   Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
  39  *************************************************************************/
  40
  41 #include <linux/tcp.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/skbuff.h>
  44 #include <linux/string.h>
  45 #include <linux/module.h>
  46 #include <linux/pci.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/etherdevice.h>
  49 #include <linux/if_ether.h>
  50 #include <linux/if_vlan.h>
  51 #include <linux/inet_lro.h>
  52 #include <linux/dca.h>
  53 #include <linux/ip.h>
  54 #include <linux/inet.h>
  55 #include <linux/in.h>
  56 #include <linux/ethtool.h>
  57 #include <linux/firmware.h>
  58 #include <linux/delay.h>
  59 #include <linux/version.h>
  60 #include <linux/timer.h>
  61 #include <linux/vmalloc.h>
  62 #include <linux/crc32.h>
  63 #include <linux/moduleparam.h>
  64 #include <linux/io.h>
  65 #include <linux/log2.h>
  66 #include <net/checksum.h>
  67 #include <net/ip.h>
  68 #include <net/tcp.h>
  69 #include <asm/byteorder.h>
  70 #include <asm/io.h>
  71 #include <asm/processor.h>
  72 #ifdef CONFIG_MTRR
  73 #include <asm/mtrr.h>
  74 #endif
  75
  76 #include "myri10ge_mcp.h"
  77 #include "myri10ge_mcp_gen_header.h"
  78
  79 #define MYRI10GE_VERSION_STR "1.3.99-1.347"
  80
  81 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
  82 MODULE_AUTHOR("Maintainer: help@myri.com");
  83 MODULE_VERSION(MYRI10GE_VERSION_STR);
  84 MODULE_LICENSE("Dual BSD/GPL");
  85
  86 #define MYRI10GE_MAX_ETHER_MTU 9014
  87
  88 #define MYRI10GE_ETH_STOPPED 0
  89 #define MYRI10GE_ETH_STOPPING 1
  90 #define MYRI10GE_ETH_STARTING 2
  91 #define MYRI10GE_ETH_RUNNING 3
  92 #define MYRI10GE_ETH_OPEN_FAILED 4
  93
  94 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
  95 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
  96 #define MYRI10GE_MAX_LRO_DESCRIPTORS 8
  97 #define MYRI10GE_LRO_MAX_PKTS 64
  98
  99 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
 100 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
 101
 102 #define MYRI10GE_ALLOC_ORDER 0
 103 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
 104 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
 105
 106 struct myri10ge_rx_buffer_state {
 107         struct page *page;
 108         int page_offset;
 109          DECLARE_PCI_UNMAP_ADDR(bus)
 110          DECLARE_PCI_UNMAP_LEN(len)
 111 };
 112
 113 struct myri10ge_tx_buffer_state {
 114         struct sk_buff *skb;
 115         int last;
 116          DECLARE_PCI_UNMAP_ADDR(bus)
 117          DECLARE_PCI_UNMAP_LEN(len)
 118 };
 119
 120 struct myri10ge_cmd {
 121         u32 data0;
 122         u32 data1;
 123         u32 data2;
 124 };
 125
 126 struct myri10ge_rx_buf {
 127         struct mcp_kreq_ether_recv __iomem *lanai;      /* lanai ptr for recv ring */
 128         u8 __iomem *wc_fifo;    /* w/c rx dma addr fifo address */
 129         struct mcp_kreq_ether_recv *shadow;     /* host shadow of recv ring */
 130         struct myri10ge_rx_buffer_state *info;
 131         struct page *page;
 132         dma_addr_t bus;
 133         int page_offset;
 134         int cnt;
 135         int fill_cnt;
 136         int alloc_fail;
 137         int mask;               /* number of rx slots -1 */
 138         int watchdog_needed;
 139 };
 140
 141 struct myri10ge_tx_buf {
 142         struct mcp_kreq_ether_send __iomem *lanai;      /* lanai ptr for sendq */
 143         u8 __iomem *wc_fifo;    /* w/c send fifo address */
 144         struct mcp_kreq_ether_send *req_list;   /* host shadow of sendq */
 145         char *req_bytes;
 146         struct myri10ge_tx_buffer_state *info;
 147         int mask;               /* number of transmit slots -1  */
 148         int req ____cacheline_aligned;  /* transmit slots submitted     */
 149         int pkt_start;          /* packets started */
 150         int stop_queue;
 151         int linearized;
 152         int done ____cacheline_aligned; /* transmit slots completed     */
 153         int pkt_done;           /* packets completed */
 154         int wake_queue;
 155 };
 156
 157 struct myri10ge_rx_done {
 158         struct mcp_slot *entry;
 159         dma_addr_t bus;
 160         int cnt;
 161         int idx;
 162         struct net_lro_mgr lro_mgr;
 163         struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
 164 };
 165
 166 struct myri10ge_slice_netstats {
 167         unsigned long rx_packets;
 168         unsigned long tx_packets;
 169         unsigned long rx_bytes;
 170         unsigned long tx_bytes;
 171         unsigned long rx_dropped;
 172         unsigned long tx_dropped;
 173 };
 174
 175 struct myri10ge_slice_state {
 176         struct myri10ge_tx_buf tx;      /* transmit ring        */
 177         struct myri10ge_rx_buf rx_small;
 178         struct myri10ge_rx_buf rx_big;
 179         struct myri10ge_rx_done rx_done;
 180         struct net_device *dev;
 181         struct napi_struct napi;
 182         struct myri10ge_priv *mgp;
 183         struct myri10ge_slice_netstats stats;
 184         __be32 __iomem *irq_claim;
 185         struct mcp_irq_data *fw_stats;
 186         dma_addr_t fw_stats_bus;
 187         int watchdog_tx_done;
 188         int watchdog_tx_req;
 189 #ifdef CONFIG_DCA
 190         int cached_dca_tag;
 191         int cpu;
 192         __be32 __iomem *dca_tag;
 193 #endif
 194         char irq_desc[32];
 195 };
 196
 197 struct myri10ge_priv {
 198         struct myri10ge_slice_state *ss;
 199         int tx_boundary;        /* boundary transmits cannot cross */
 200         int num_slices;
 201         int running;            /* running?             */
 202         int csum_flag;          /* rx_csums?            */
 203         int small_bytes;
 204         int big_bytes;
 205         int max_intr_slots;
 206         struct net_device *dev;
 207         struct net_device_stats stats;
 208         spinlock_t stats_lock;
 209         u8 __iomem *sram;
 210         int sram_size;
 211         unsigned long board_span;
 212         unsigned long iomem_base;
 213         __be32 __iomem *irq_deassert;
 214         char *mac_addr_string;
 215         struct mcp_cmd_response *cmd;
 216         dma_addr_t cmd_bus;
 217         struct pci_dev *pdev;
 218         int msi_enabled;
 219         int msix_enabled;
 220         struct msix_entry *msix_vectors;
 221 #ifdef CONFIG_DCA
 222         int dca_enabled;
 223 #endif
 224         u32 link_state;
 225         unsigned int rdma_tags_available;
 226         int intr_coal_delay;
 227         __be32 __iomem *intr_coal_delay_ptr;
 228         int mtrr;
 229         int wc_enabled;
 230         int down_cnt;
 231         wait_queue_head_t down_wq;
 232         struct work_struct watchdog_work;
 233         struct timer_list watchdog_timer;
 234         int watchdog_resets;
 235         int watchdog_pause;
 236         int pause;
 237         char *fw_name;
 238         char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
 239         char *product_code_string;
 240         char fw_version[128];
 241         int fw_ver_major;
 242         int fw_ver_minor;
 243         int fw_ver_tiny;
 244         int adopted_rx_filter_bug;
 245         u8 mac_addr[6];         /* eeprom mac address */
 246         unsigned long serial_number;
 247         int vendor_specific_offset;
 248         int fw_multicast_support;
 249         unsigned long features;
 250         u32 max_tso6;
 251         u32 read_dma;
 252         u32 write_dma;
 253         u32 read_write_dma;
 254         u32 link_changes;
 255         u32 msg_enable;
 256 };
 257
 258 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
 259 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
 260 static char *myri10ge_fw_rss_unaligned = "myri10ge_rss_ethp_z8e.dat";
 261 static char *myri10ge_fw_rss_aligned = "myri10ge_rss_eth_z8e.dat";
 262
 263 static char *myri10ge_fw_name = NULL;
 264 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
 265 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
 266
 267 static int myri10ge_ecrc_enable = 1;
 268 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
 269 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
 270
 271 static int myri10ge_small_bytes = -1;   /* -1 == auto */
 272 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
 273 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
 274
 275 static int myri10ge_msi = 1;    /* enable msi by default */
 276 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
 277 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
 278
 279 static int myri10ge_intr_coal_delay = 75;
 280 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
 281 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
 282
 283 static int myri10ge_flow_control = 1;
 284 module_param(myri10ge_flow_control, int, S_IRUGO);
 285 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
 286
 287 static int myri10ge_deassert_wait = 1;
 288 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
 289 MODULE_PARM_DESC(myri10ge_deassert_wait,
 290                  "Wait when deasserting legacy interrupts");
 291
 292 static int myri10ge_force_firmware = 0;
 293 module_param(myri10ge_force_firmware, int, S_IRUGO);
 294 MODULE_PARM_DESC(myri10ge_force_firmware,
 295                  "Force firmware to assume aligned completions");
 296
 297 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
 298 module_param(myri10ge_initial_mtu, int, S_IRUGO);
 299 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
 300
 301 static int myri10ge_napi_weight = 64;
 302 module_param(myri10ge_napi_weight, int, S_IRUGO);
 303 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
 304
 305 static int myri10ge_watchdog_timeout = 1;
 306 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
 307 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
 308
 309 static int myri10ge_max_irq_loops = 1048576;
 310 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
 311 MODULE_PARM_DESC(myri10ge_max_irq_loops,
 312                  "Set stuck legacy IRQ detection threshold");
 313
 314 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
 315
 316 static int myri10ge_debug = -1; /* defaults above */
 317 module_param(myri10ge_debug, int, 0);
 318 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
 319
 320 static int myri10ge_lro = 1;
 321 module_param(myri10ge_lro, int, S_IRUGO);
 322 MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
 323
 324 static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
 325 module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
 326 MODULE_PARM_DESC(myri10ge_lro_max_pkts,
 327                  "Number of LRO packets to be aggregated");
 328
 329 static int myri10ge_fill_thresh = 256;
 330 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
 331 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
 332
 333 static int myri10ge_reset_recover = 1;
 334
 335 static int myri10ge_wcfifo = 0;
 336 module_param(myri10ge_wcfifo, int, S_IRUGO);
 337 MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled");
 338
 339 static int myri10ge_max_slices = 1;
 340 module_param(myri10ge_max_slices, int, S_IRUGO);
 341 MODULE_PARM_DESC(myri10ge_max_slices, "Max tx/rx queues");
 342
 343 static int myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
 344 module_param(myri10ge_rss_hash, int, S_IRUGO);
 345 MODULE_PARM_DESC(myri10ge_rss_hash, "Type of RSS hashing to do");
 346
 347 static int myri10ge_dca = 1;
 348 module_param(myri10ge_dca, int, S_IRUGO);
 349 MODULE_PARM_DESC(myri10ge_dca, "Enable DCA if possible");
 350
 351 #define MYRI10GE_FW_OFFSET 1024*1024
 352 #define MYRI10GE_HIGHPART_TO_U32(X) \
 353 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
 354 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
 355
 356 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
 357
 358 static void myri10ge_set_multicast_list(struct net_device *dev);
 359 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
 360
 361 static inline void put_be32(__be32 val, __be32 __iomem * p)
 362 {
 363         __raw_writel((__force __u32) val, (__force void __iomem *)p);
 364 }
 365
 366 static int
 367 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
 368                   struct myri10ge_cmd *data, int atomic)
 369 {
 370         struct mcp_cmd *buf;
 371         char buf_bytes[sizeof(*buf) + 8];
 372         struct mcp_cmd_response *response = mgp->cmd;
 373         char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
 374         u32 dma_low, dma_high, result, value;
 375         int sleep_total = 0;
 376
 377         /* ensure buf is aligned to 8 bytes */
 378         buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
 379
 380         buf->data0 = htonl(data->data0);
 381         buf->data1 = htonl(data->data1);
 382         buf->data2 = htonl(data->data2);
 383         buf->cmd = htonl(cmd);
 384         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 385         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 386
 387         buf->response_addr.low = htonl(dma_low);
 388         buf->response_addr.high = htonl(dma_high);
 389         response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
 390         mb();
 391         myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
 392
 393         /* wait up to 15ms. Longest command is the DMA benchmark,
 394          * which is capped at 5ms, but runs from a timeout handler
 395          * that runs every 7.8ms. So a 15ms timeout leaves us with
 396          * a 2.2ms margin
 397          */
 398         if (atomic) {
 399                 /* if atomic is set, do not sleep,
 400                  * and try to get the completion quickly
 401                  * (1ms will be enough for those commands) */
 402                 for (sleep_total = 0;
 403                      sleep_total < 1000
 404                      && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
 405                      sleep_total += 10) {
 406                         udelay(10);
 407                         mb();
 408                 }
 409         } else {
 410                 /* use msleep for most command */
 411                 for (sleep_total = 0;
 412                      sleep_total < 15
 413                      && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
 414                      sleep_total++)
 415                         msleep(1);
 416         }
 417
 418         result = ntohl(response->result);
 419         value = ntohl(response->data);
 420         if (result != MYRI10GE_NO_RESPONSE_RESULT) {
 421                 if (result == 0) {
 422                         data->data0 = value;
 423                         return 0;
 424                 } else if (result == MXGEFW_CMD_UNKNOWN) {
 425                         return -ENOSYS;
 426                 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
 427                         return -E2BIG;
 428                 } else {
 429                         dev_err(&mgp->pdev->dev,
 430                                 "command %d failed, result = %d\n",
 431                                 cmd, result);
 432                         return -ENXIO;
 433                 }
 434         }
 435
 436         dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
 437                 cmd, result);
 438         return -EAGAIN;
 439 }
 440
 441 /*
 442  * The eeprom strings on the lanaiX have the format
 443  * SN=x\0
 444  * MAC=x:x:x:x:x:x\0
 445  * PT:ddd mmm xx xx:xx:xx xx\0
 446  * PV:ddd mmm xx xx:xx:xx xx\0
 447  */
 448 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
 449 {
 450         char *ptr, *limit;
 451         int i;
 452
 453         ptr = mgp->eeprom_strings;
 454         limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
 455
 456         while (*ptr != '\0' && ptr < limit) {
 457                 if (memcmp(ptr, "MAC=", 4) == 0) {
 458                         ptr += 4;
 459                         mgp->mac_addr_string = ptr;
 460                         for (i = 0; i < 6; i++) {
 461                                 if ((ptr + 2) > limit)
 462                                         goto abort;
 463                                 mgp->mac_addr[i] =
 464                                     simple_strtoul(ptr, &ptr, 16);
 465                                 ptr += 1;
 466                         }
 467                 }
 468                 if (memcmp(ptr, "PC=", 3) == 0) {
 469                         ptr += 3;
 470                         mgp->product_code_string = ptr;
 471                 }
 472                 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
 473                         ptr += 3;
 474                         mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
 475                 }
 476                 while (ptr < limit && *ptr++) ;
 477         }
 478
 479         return 0;
 480
 481 abort:
 482         dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
 483         return -ENXIO;
 484 }
 485
 486 /*
 487  * Enable or disable periodic RDMAs from the host to make certain
 488  * chipsets resend dropped PCIe messages
 489  */
 490
 491 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
 492 {
 493         char __iomem *submit;
 494         __be32 buf[16] __attribute__ ((__aligned__(8)));
 495         u32 dma_low, dma_high;
 496         int i;
 497
 498         /* clear confirmation addr */
 499         mgp->cmd->data = 0;
 500         mb();
 501
 502         /* send a rdma command to the PCIe engine, and wait for the
 503          * response in the confirmation address.  The firmware should
 504          * write a -1 there to indicate it is alive and well
 505          */
 506         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 507         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 508
 509         buf[0] = htonl(dma_high);       /* confirm addr MSW */
 510         buf[1] = htonl(dma_low);        /* confirm addr LSW */
 511         buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
 512         buf[3] = htonl(dma_high);       /* dummy addr MSW */
 513         buf[4] = htonl(dma_low);        /* dummy addr LSW */
 514         buf[5] = htonl(enable); /* enable? */
 515
 516         submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
 517
 518         myri10ge_pio_copy(submit, &buf, sizeof(buf));
 519         for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
 520                 msleep(1);
 521         if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
 522                 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
 523                         (enable ? "enable" : "disable"));
 524 }
 525
 526 static int
 527 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
 528                            struct mcp_gen_header *hdr)
 529 {
 530         struct device *dev = &mgp->pdev->dev;
 531
 532         /* check firmware type */
 533         if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
 534                 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
 535                 return -EINVAL;
 536         }
 537
 538         /* save firmware version for ethtool */
 539         strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
 540
 541         sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
 542                &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
 543
 544         if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
 545               && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
 546                 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
 547                 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
 548                         MXGEFW_VERSION_MINOR);
 549                 return -EINVAL;
 550         }
 551         return 0;
 552 }
 553
 554 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
 555 {
 556         unsigned crc, reread_crc;
 557         const struct firmware *fw;
 558         struct device *dev = &mgp->pdev->dev;
 559         struct mcp_gen_header *hdr;
 560         size_t hdr_offset;
 561         int status;
 562         unsigned i;
 563
 564         if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
 565                 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
 566                         mgp->fw_name);
 567                 status = -EINVAL;
 568                 goto abort_with_nothing;
 569         }
 570
 571         /* check size */
 572
 573         if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
 574             fw->size < MCP_HEADER_PTR_OFFSET + 4) {
 575                 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
 576                 status = -EINVAL;
 577                 goto abort_with_fw;
 578         }
 579
 580         /* check id */
 581         hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
 582         if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
 583                 dev_err(dev, "Bad firmware file\n");
 584                 status = -EINVAL;
 585                 goto abort_with_fw;
 586         }
 587         hdr = (void *)(fw->data + hdr_offset);
 588
 589         status = myri10ge_validate_firmware(mgp, hdr);
 590         if (status != 0)
 591                 goto abort_with_fw;
 592
 593         crc = crc32(~0, fw->data, fw->size);
 594         for (i = 0; i < fw->size; i += 256) {
 595                 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
 596                                   fw->data + i,
 597                                   min(256U, (unsigned)(fw->size - i)));
 598                 mb();
 599                 readb(mgp->sram);
 600         }
 601         /* corruption checking is good for parity recovery and buggy chipset */
 602         memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
 603         reread_crc = crc32(~0, fw->data, fw->size);
 604         if (crc != reread_crc) {
 605                 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
 606                         (unsigned)fw->size, reread_crc, crc);
 607                 status = -EIO;
 608                 goto abort_with_fw;
 609         }
 610         *size = (u32) fw->size;
 611
 612 abort_with_fw:
 613         release_firmware(fw);
 614
 615 abort_with_nothing:
 616         return status;
 617 }
 618
 619 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
 620 {
 621         struct mcp_gen_header *hdr;
 622         struct device *dev = &mgp->pdev->dev;
 623         const size_t bytes = sizeof(struct mcp_gen_header);
 624         size_t hdr_offset;
 625         int status;
 626
 627         /* find running firmware header */
 628         hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
 629
 630         if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
 631                 dev_err(dev, "Running firmware has bad header offset (%d)\n",
 632                         (int)hdr_offset);
 633                 return -EIO;
 634         }
 635
 636         /* copy header of running firmware from SRAM to host memory to
 637          * validate firmware */
 638         hdr = kmalloc(bytes, GFP_KERNEL);
 639         if (hdr == NULL) {
 640                 dev_err(dev, "could not malloc firmware hdr\n");
 641                 return -ENOMEM;
 642         }
 643         memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
 644         status = myri10ge_validate_firmware(mgp, hdr);
 645         kfree(hdr);
 646
 647         /* check to see if adopted firmware has bug where adopting
 648          * it will cause broadcasts to be filtered unless the NIC
 649          * is kept in ALLMULTI mode */
 650         if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
 651             mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
 652                 mgp->adopted_rx_filter_bug = 1;
 653                 dev_warn(dev, "Adopting fw %d.%d.%d: "
 654                          "working around rx filter bug\n",
 655                          mgp->fw_ver_major, mgp->fw_ver_minor,
 656                          mgp->fw_ver_tiny);
 657         }
 658         return status;
 659 }
 660
 661 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
 662 {
 663         struct myri10ge_cmd cmd;
 664         int status;
 665
 666         /* probe for IPv6 TSO support */
 667         mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
 668         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
 669                                    &cmd, 0);
 670         if (status == 0) {
 671                 mgp->max_tso6 = cmd.data0;
 672                 mgp->features |= NETIF_F_TSO6;
 673         }
 674
 675         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
 676         if (status != 0) {
 677                 dev_err(&mgp->pdev->dev,
 678                         "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
 679                 return -ENXIO;
 680         }
 681
 682         mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
 683
 684         return 0;
 685 }
 686
 687 static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
 688 {
 689         char __iomem *submit;
 690         __be32 buf[16] __attribute__ ((__aligned__(8)));
 691         u32 dma_low, dma_high, size;
 692         int status, i;
 693
 694         size = 0;
 695         status = myri10ge_load_hotplug_firmware(mgp, &size);
 696         if (status) {
 697                 if (!adopt)
 698                         return status;
 699                 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
 700
 701                 /* Do not attempt to adopt firmware if there
 702                  * was a bad crc */
 703                 if (status == -EIO)
 704                         return status;
 705
 706                 status = myri10ge_adopt_running_firmware(mgp);
 707                 if (status != 0) {
 708                         dev_err(&mgp->pdev->dev,
 709                                 "failed to adopt running firmware\n");
 710                         return status;
 711                 }
 712                 dev_info(&mgp->pdev->dev,
 713                          "Successfully adopted running firmware\n");
 714                 if (mgp->tx_boundary == 4096) {
 715                         dev_warn(&mgp->pdev->dev,
 716                                  "Using firmware currently running on NIC"
 717                                  ".  For optimal\n");
 718                         dev_warn(&mgp->pdev->dev,
 719                                  "performance consider loading optimized "
 720                                  "firmware\n");
 721                         dev_warn(&mgp->pdev->dev, "via hotplug\n");
 722                 }
 723
 724                 mgp->fw_name = "adopted";
 725                 mgp->tx_boundary = 2048;
 726                 myri10ge_dummy_rdma(mgp, 1);
 727                 status = myri10ge_get_firmware_capabilities(mgp);
 728                 return status;
 729         }
 730
 731         /* clear confirmation addr */
 732         mgp->cmd->data = 0;
 733         mb();
 734
 735         /* send a reload command to the bootstrap MCP, and wait for the
 736          *  response in the confirmation address.  The firmware should
 737          * write a -1 there to indicate it is alive and well
 738          */
 739         dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
 740         dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
 741
 742         buf[0] = htonl(dma_high);       /* confirm addr MSW */
 743         buf[1] = htonl(dma_low);        /* confirm addr LSW */
 744         buf[2] = MYRI10GE_NO_CONFIRM_DATA;      /* confirm data */
 745
 746         /* FIX: All newest firmware should un-protect the bottom of
 747          * the sram before handoff. However, the very first interfaces
 748          * do not. Therefore the handoff copy must skip the first 8 bytes
 749          */
 750         buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
 751         buf[4] = htonl(size - 8);       /* length of code */
 752         buf[5] = htonl(8);      /* where to copy to */
 753         buf[6] = htonl(0);      /* where to jump to */
 754
 755         submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
 756
 757         myri10ge_pio_copy(submit, &buf, sizeof(buf));
 758         mb();
 759         msleep(1);
 760         mb();
 761         i = 0;
 762         while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
 763                 msleep(1 << i);
 764                 i++;
 765         }
 766         if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
 767                 dev_err(&mgp->pdev->dev, "handoff failed\n");
 768                 return -ENXIO;
 769         }
 770         myri10ge_dummy_rdma(mgp, 1);
 771         status = myri10ge_get_firmware_capabilities(mgp);
 772
 773         return status;
 774 }
 775
 776 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
 777 {
 778         struct myri10ge_cmd cmd;
 779         int status;
 780
 781         cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
 782                      | (addr[2] << 8) | addr[3]);
 783
 784         cmd.data1 = ((addr[4] << 8) | (addr[5]));
 785
 786         status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
 787         return status;
 788 }
 789
 790 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
 791 {
 792         struct myri10ge_cmd cmd;
 793         int status, ctl;
 794
 795         ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
 796         status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
 797
 798         if (status) {
 799                 printk(KERN_ERR
 800                        "myri10ge: %s: Failed to set flow control mode\n",
 801                        mgp->dev->name);
 802                 return status;
 803         }
 804         mgp->pause = pause;
 805         return 0;
 806 }
 807
 808 static void
 809 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
 810 {
 811         struct myri10ge_cmd cmd;
 812         int status, ctl;
 813
 814         ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
 815         status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
 816         if (status)
 817                 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
 818                        mgp->dev->name);
 819 }
 820
 821 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
 822 {
 823         struct myri10ge_cmd cmd;
 824         int status;
 825         u32 len;
 826         struct page *dmatest_page;
 827         dma_addr_t dmatest_bus;
 828         char *test = " ";
 829
 830         dmatest_page = alloc_page(GFP_KERNEL);
 831         if (!dmatest_page)
 832                 return -ENOMEM;
 833         dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
 834                                    DMA_BIDIRECTIONAL);
 835
 836         /* Run a small DMA test.
 837          * The magic multipliers to the length tell the firmware
 838          * to do DMA read, write, or read+write tests.  The
 839          * results are returned in cmd.data0.  The upper 16
 840          * bits or the return is the number of transfers completed.
 841          * The lower 16 bits is the time in 0.5us ticks that the
 842          * transfers took to complete.
 843          */
 844
 845         len = mgp->tx_boundary;
 846
 847         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 848         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 849         cmd.data2 = len * 0x10000;
 850         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 851         if (status != 0) {
 852                 test = "read";
 853                 goto abort;
 854         }
 855         mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
 856         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 857         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 858         cmd.data2 = len * 0x1;
 859         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 860         if (status != 0) {
 861                 test = "write";
 862                 goto abort;
 863         }
 864         mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
 865
 866         cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
 867         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
 868         cmd.data2 = len * 0x10001;
 869         status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
 870         if (status != 0) {
 871                 test = "read/write";
 872                 goto abort;
 873         }
 874         mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
 875             (cmd.data0 & 0xffff);
 876
 877 abort:
 878         pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
 879         put_page(dmatest_page);
 880
 881         if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
 882                 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
 883                          test, status);
 884
 885         return status;
 886 }
 887
 888 static int myri10ge_reset(struct myri10ge_priv *mgp)
 889 {
 890         struct myri10ge_cmd cmd;
 891         struct myri10ge_slice_state *ss;
 892         int i, status;
 893         size_t bytes;
 894 #ifdef CONFIG_DCA
 895         unsigned long dca_tag_off;
 896 #endif
 897
 898         /* try to send a reset command to the card to see if it
 899          * is alive */
 900         memset(&cmd, 0, sizeof(cmd));
 901         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
 902         if (status != 0) {
 903                 dev_err(&mgp->pdev->dev, "failed reset\n");
 904                 return -ENXIO;
 905         }
 906
 907         (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
 908         /*
 909          * Use non-ndis mcp_slot (eg, 4 bytes total,
 910          * no toeplitz hash value returned.  Older firmware will
 911          * not understand this command, but will use the correct
 912          * sized mcp_slot, so we ignore error returns
 913          */
 914         cmd.data0 = MXGEFW_RSS_MCP_SLOT_TYPE_MIN;
 915         (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
 916
 917         /* Now exchange information about interrupts  */
 918
 919         bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
 920         cmd.data0 = (u32) bytes;
 921         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
 922
 923         /*
 924          * Even though we already know how many slices are supported
 925          * via myri10ge_probe_slices() MXGEFW_CMD_GET_MAX_RSS_QUEUES
 926          * has magic side effects, and must be called after a reset.
 927          * It must be called prior to calling any RSS related cmds,
 928          * including assigning an interrupt queue for anything but
 929          * slice 0.  It must also be called *after*
 930          * MXGEFW_CMD_SET_INTRQ_SIZE, since the intrq size is used by
 931          * the firmware to compute offsets.
 932          */
 933
 934         if (mgp->num_slices > 1) {
 935
 936                 /* ask the maximum number of slices it supports */
 937                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
 938                                            &cmd, 0);
 939                 if (status != 0) {
 940                         dev_err(&mgp->pdev->dev,
 941                                 "failed to get number of slices\n");
 942                 }
 943
 944                 /*
 945                  * MXGEFW_CMD_ENABLE_RSS_QUEUES must be called prior
 946                  * to setting up the interrupt queue DMA
 947                  */
 948
 949                 cmd.data0 = mgp->num_slices;
 950                 cmd.data1 = 1;  /* use MSI-X */
 951                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
 952                                            &cmd, 0);
 953                 if (status != 0) {
 954                         dev_err(&mgp->pdev->dev,
 955                                 "failed to set number of slices\n");
 956
 957                         return status;
 958                 }
 959         }
 960         for (i = 0; i < mgp->num_slices; i++) {
 961                 ss = &mgp->ss[i];
 962                 cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->rx_done.bus);
 963                 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->rx_done.bus);
 964                 cmd.data2 = i;
 965                 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
 966                                             &cmd, 0);
 967         };
 968
 969         status |=
 970             myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
 971         for (i = 0; i < mgp->num_slices; i++) {
 972                 ss = &mgp->ss[i];
 973                 ss->irq_claim =
 974                     (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
 975         }
 976         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
 977                                     &cmd, 0);
 978         mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
 979
 980         status |= myri10ge_send_cmd
 981             (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
 982         mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
 983         if (status != 0) {
 984                 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
 985                 return status;
 986         }
 987         put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
 988
 989 #ifdef CONFIG_DCA
 990         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
 991         dca_tag_off = cmd.data0;
 992         for (i = 0; i < mgp->num_slices; i++) {
 993                 ss = &mgp->ss[i];
 994                 if (status == 0) {
 995                         ss->dca_tag = (__iomem __be32 *)
 996                             (mgp->sram + dca_tag_off + 4 * i);
 997                 } else {
 998                         ss->dca_tag = NULL;
 999                 }
1000         }
1001 #endif                          /* CONFIG_DCA */
1002
1003         /* reset mcp/driver shared state back to 0 */
1004
1005         mgp->link_changes = 0;
1006         for (i = 0; i < mgp->num_slices; i++) {
1007                 ss = &mgp->ss[i];
1008
1009                 memset(ss->rx_done.entry, 0, bytes);
1010                 ss->tx.req = 0;
1011                 ss->tx.done = 0;
1012                 ss->tx.pkt_start = 0;
1013                 ss->tx.pkt_done = 0;
1014                 ss->rx_big.cnt = 0;
1015                 ss->rx_small.cnt = 0;
1016                 ss->rx_done.idx = 0;
1017                 ss->rx_done.cnt = 0;
1018                 ss->tx.wake_queue = 0;
1019                 ss->tx.stop_queue = 0;
1020         }
1021
1022         status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
1023         myri10ge_change_pause(mgp, mgp->pause);
1024         myri10ge_set_multicast_list(mgp->dev);
1025         return status;
1026 }
1027
1028 #ifdef CONFIG_DCA
1029 static void
1030 myri10ge_write_dca(struct myri10ge_slice_state *ss, int cpu, int tag)
1031 {
1032         ss->cpu = cpu;
1033         ss->cached_dca_tag = tag;
1034         put_be32(htonl(tag), ss->dca_tag);
1035 }
1036
1037 static inline void myri10ge_update_dca(struct myri10ge_slice_state *ss)
1038 {
1039         int cpu = get_cpu();
1040         int tag;
1041
1042         if (cpu != ss->cpu) {
1043                 tag = dca_get_tag(cpu);
1044                 if (ss->cached_dca_tag != tag)
1045                         myri10ge_write_dca(ss, cpu, tag);
1046         }
1047         put_cpu();
1048 }
1049
1050 static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1051 {
1052         int err, i;
1053         struct pci_dev *pdev = mgp->pdev;
1054
1055         if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1056                 return;
1057         if (!myri10ge_dca) {
1058                 dev_err(&pdev->dev, "dca disabled by administrator\n");
1059                 return;
1060         }
1061         err = dca_add_requester(&pdev->dev);
1062         if (err) {
1063                 dev_err(&pdev->dev,
1064                         "dca_add_requester() failed, err=%d\n", err);
1065                 return;
1066         }
1067         mgp->dca_enabled = 1;
1068         for (i = 0; i < mgp->num_slices; i++)
1069                 myri10ge_write_dca(&mgp->ss[i], -1, 0);
1070 }
1071
1072 static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1073 {
1074         struct pci_dev *pdev = mgp->pdev;
1075         int err;
1076
1077         if (!mgp->dca_enabled)
1078                 return;
1079         mgp->dca_enabled = 0;
1080         err = dca_remove_requester(&pdev->dev);
1081 }
1082
1083 static int myri10ge_notify_dca_device(struct device *dev, void *data)
1084 {
1085         struct myri10ge_priv *mgp;
1086         unsigned long event;
1087
1088         mgp = dev_get_drvdata(dev);
1089         event = *(unsigned long *)data;
1090
1091         if (event == DCA_PROVIDER_ADD)
1092                 myri10ge_setup_dca(mgp);
1093         else if (event == DCA_PROVIDER_REMOVE)
1094                 myri10ge_teardown_dca(mgp);
1095         return 0;
1096 }
1097 #endif                          /* CONFIG_DCA */
1098
1099 static inline void
1100 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
1101                     struct mcp_kreq_ether_recv *src)
1102 {
1103         __be32 low;
1104
1105         low = src->addr_low;
1106         src->addr_low = htonl(DMA_32BIT_MASK);
1107         myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
1108         mb();
1109         myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
1110         mb();
1111         src->addr_low = low;
1112         put_be32(low, &dst->addr_low);
1113         mb();
1114 }
1115
1116 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
1117 {
1118         struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
1119
1120         if ((skb->protocol == htons(ETH_P_8021Q)) &&
1121             (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
1122              vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
1123                 skb->csum = hw_csum;
1124                 skb->ip_summed = CHECKSUM_COMPLETE;
1125         }
1126 }
1127
1128 static inline void
1129 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
1130                       struct skb_frag_struct *rx_frags, int len, int hlen)
1131 {
1132         struct skb_frag_struct *skb_frags;
1133
1134         skb->len = skb->data_len = len;
1135         skb->truesize = len + sizeof(struct sk_buff);
1136         /* attach the page(s) */
1137
1138         skb_frags = skb_shinfo(skb)->frags;
1139         while (len > 0) {
1140                 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
1141                 len -= rx_frags->size;
1142                 skb_frags++;
1143                 rx_frags++;
1144                 skb_shinfo(skb)->nr_frags++;
1145         }
1146
1147         /* pskb_may_pull is not available in irq context, but
1148          * skb_pull() (for ether_pad and eth_type_trans()) requires
1149          * the beginning of the packet in skb_headlen(), move it
1150          * manually */
1151         skb_copy_to_linear_data(skb, va, hlen);
1152         skb_shinfo(skb)->frags[0].page_offset += hlen;
1153         skb_shinfo(skb)->frags[0].size -= hlen;
1154         skb->data_len -= hlen;
1155         skb->tail += hlen;
1156         skb_pull(skb, MXGEFW_PAD);
1157 }
1158
1159 static void
1160 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1161                         int bytes, int watchdog)
1162 {
1163         struct page *page;
1164         int idx;
1165
1166         if (unlikely(rx->watchdog_needed && !watchdog))
1167                 return;
1168
1169         /* try to refill entire ring */
1170         while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
1171                 idx = rx->fill_cnt & rx->mask;
1172                 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
1173                         /* we can use part of previous page */
1174                         get_page(rx->page);
1175                 } else {
1176                         /* we need a new page */
1177                         page =
1178                             alloc_pages(GFP_ATOMIC | __GFP_COMP,
1179                                         MYRI10GE_ALLOC_ORDER);
1180                         if (unlikely(page == NULL)) {
1181                                 if (rx->fill_cnt - rx->cnt < 16)
1182                                         rx->watchdog_needed = 1;
1183                                 return;
1184                         }
1185                         rx->page = page;
1186                         rx->page_offset = 0;
1187                         rx->bus = pci_map_page(mgp->pdev, page, 0,
1188                                                MYRI10GE_ALLOC_SIZE,
1189                                                PCI_DMA_FROMDEVICE);
1190                 }
1191                 rx->info[idx].page = rx->page;
1192                 rx->info[idx].page_offset = rx->page_offset;
1193                 /* note that this is the address of the start of the
1194                  * page */
1195                 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1196                 rx->shadow[idx].addr_low =
1197                     htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1198                 rx->shadow[idx].addr_high =
1199                     htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1200
1201                 /* start next packet on a cacheline boundary */
1202                 rx->page_offset += SKB_DATA_ALIGN(bytes);
1203
1204 #if MYRI10GE_ALLOC_SIZE > 4096
1205                 /* don't cross a 4KB boundary */
1206                 if ((rx->page_offset >> 12) !=
1207                     ((rx->page_offset + bytes - 1) >> 12))
1208                         rx->page_offset = (rx->page_offset + 4096) & ~4095;
1209 #endif
1210                 rx->fill_cnt++;
1211
1212                 /* copy 8 descriptors to the firmware at a time */
1213                 if ((idx & 7) == 7) {
1214                         if (rx->wc_fifo == NULL)
1215                                 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1216                                                     &rx->shadow[idx - 7]);
1217                         else {
1218                                 mb();
1219                                 myri10ge_pio_copy(rx->wc_fifo,
1220                                                   &rx->shadow[idx - 7], 64);
1221                         }
1222                 }
1223         }
1224 }
1225
1226 static inline void
1227 myri10ge_unmap_rx_page(struct pci_dev *pdev,
1228                        struct myri10ge_rx_buffer_state *info, int bytes)
1229 {
1230         /* unmap the recvd page if we're the only or last user of it */
1231         if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1232             (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1233                 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1234                                       & ~(MYRI10GE_ALLOC_SIZE - 1)),
1235                                MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1236         }
1237 }
1238
1239 #define MYRI10GE_HLEN 64        /* The number of bytes to copy from a
1240                                  * page into an skb */
1241
1242 static inline int
1243 myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
1244                  int bytes, int len, __wsum csum)
1245 {
1246         struct myri10ge_priv *mgp = ss->mgp;
1247         struct sk_buff *skb;
1248         struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1249         int i, idx, hlen, remainder;
1250         struct pci_dev *pdev = mgp->pdev;
1251         struct net_device *dev = mgp->dev;
1252         u8 *va;
1253
1254         len += MXGEFW_PAD;
1255         idx = rx->cnt & rx->mask;
1256         va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1257         prefetch(va);
1258         /* Fill skb_frag_struct(s) with data from our receive */
1259         for (i = 0, remainder = len; remainder > 0; i++) {
1260                 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1261                 rx_frags[i].page = rx->info[idx].page;
1262                 rx_frags[i].page_offset = rx->info[idx].page_offset;
1263                 if (remainder < MYRI10GE_ALLOC_SIZE)
1264                         rx_frags[i].size = remainder;
1265                 else
1266                         rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1267                 rx->cnt++;
1268                 idx = rx->cnt & rx->mask;
1269                 remainder -= MYRI10GE_ALLOC_SIZE;
1270         }
1271
1272         if (mgp->csum_flag && myri10ge_lro) {
1273                 rx_frags[0].page_offset += MXGEFW_PAD;
1274                 rx_frags[0].size -= MXGEFW_PAD;
1275                 len -= MXGEFW_PAD;
1276                 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
1277                                   /* opaque, will come back in get_frag_header */
1278                                   len, len,
1279                                   (void *)(__force unsigned long)csum, csum);
1280
1281                 return 1;
1282         }
1283
1284         hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1285
1286         /* allocate an skb to attach the page(s) to. This is done
1287          * after trying LRO, so as to avoid skb allocation overheads */
1288
1289         skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1290         if (unlikely(skb == NULL)) {
1291                 mgp->stats.rx_dropped++;
1292                 do {
1293                         i--;
1294                         put_page(rx_frags[i].page);
1295                 } while (i != 0);
1296                 return 0;
1297         }
1298
1299         /* Attach the pages to the skb, and trim off any padding */
1300         myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1301         if (skb_shinfo(skb)->frags[0].size <= 0) {
1302                 put_page(skb_shinfo(skb)->frags[0].page);
1303                 skb_shinfo(skb)->nr_frags = 0;
1304         }
1305         skb->protocol = eth_type_trans(skb, dev);
1306
1307         if (mgp->csum_flag) {
1308                 if ((skb->protocol == htons(ETH_P_IP)) ||
1309                     (skb->protocol == htons(ETH_P_IPV6))) {
1310                         skb->csum = csum;
1311                         skb->ip_summed = CHECKSUM_COMPLETE;
1312                 } else
1313                         myri10ge_vlan_ip_csum(skb, csum);
1314         }
1315         netif_receive_skb(skb);
1316         dev->last_rx = jiffies;
1317         return 1;
1318 }
1319
1320 static inline void
1321 myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
1322 {
1323         struct pci_dev *pdev = ss->mgp->pdev;
1324         struct myri10ge_tx_buf *tx = &ss->tx;
1325         struct sk_buff *skb;
1326         int idx, len;
1327
1328         while (tx->pkt_done != mcp_index) {
1329                 idx = tx->done & tx->mask;
1330                 skb = tx->info[idx].skb;
1331
1332                 /* Mark as free */
1333                 tx->info[idx].skb = NULL;
1334                 if (tx->info[idx].last) {
1335                         tx->pkt_done++;
1336                         tx->info[idx].last = 0;
1337                 }
1338                 tx->done++;
1339                 len = pci_unmap_len(&tx->info[idx], len);
1340                 pci_unmap_len_set(&tx->info[idx], len, 0);
1341                 if (skb) {
1342                         ss->stats.tx_bytes += skb->len;
1343                         ss->stats.tx_packets++;
1344                         dev_kfree_skb_irq(skb);
1345                         if (len)
1346                                 pci_unmap_single(pdev,
1347                                                  pci_unmap_addr(&tx->info[idx],
1348                                                                 bus), len,
1349                                                  PCI_DMA_TODEVICE);
1350                 } else {
1351                         if (len)
1352                                 pci_unmap_page(pdev,
1353                                                pci_unmap_addr(&tx->info[idx],
1354                                                               bus), len,
1355                                                PCI_DMA_TODEVICE);
1356                 }
1357         }
1358         /* start the queue if we've stopped it */
1359         if (netif_queue_stopped(ss->dev)
1360             && tx->req - tx->done < (tx->mask >> 1)) {
1361                 tx->wake_queue++;
1362                 netif_wake_queue(ss->dev);
1363         }
1364 }
1365
1366 static inline int
1367 myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
1368 {
1369         struct myri10ge_rx_done *rx_done = &ss->rx_done;
1370         struct myri10ge_priv *mgp = ss->mgp;
1371         unsigned long rx_bytes = 0;
1372         unsigned long rx_packets = 0;
1373         unsigned long rx_ok;
1374
1375         int idx = rx_done->idx;
1376         int cnt = rx_done->cnt;
1377         int work_done = 0;
1378         u16 length;
1379         __wsum checksum;
1380
1381         while (rx_done->entry[idx].length != 0 && work_done < budget) {
1382                 length = ntohs(rx_done->entry[idx].length);
1383                 rx_done->entry[idx].length = 0;
1384                 checksum = csum_unfold(rx_done->entry[idx].checksum);
1385                 if (length <= mgp->small_bytes)
1386                         rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
1387                                                  mgp->small_bytes,
1388                                                  length, checksum);
1389                 else
1390                         rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
1391                                                  mgp->big_bytes,
1392                                                  length, checksum);
1393                 rx_packets += rx_ok;
1394                 rx_bytes += rx_ok * (unsigned long)length;
1395                 cnt++;
1396                 idx = cnt & (mgp->max_intr_slots - 1);
1397                 work_done++;
1398         }
1399         rx_done->idx = idx;
1400         rx_done->cnt = cnt;
1401         ss->stats.rx_packets += rx_packets;
1402         ss->stats.rx_bytes += rx_bytes;
1403
1404         if (myri10ge_lro)
1405                 lro_flush_all(&rx_done->lro_mgr);
1406
1407         /* restock receive rings if needed */
1408         if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1409                 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1410                                         mgp->small_bytes + MXGEFW_PAD, 0);
1411         if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1412                 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1413
1414         return work_done;
1415 }
1416
1417 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1418 {
1419         struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
1420
1421         if (unlikely(stats->stats_updated)) {
1422                 unsigned link_up = ntohl(stats->link_up);
1423                 if (mgp->link_state != link_up) {
1424                         mgp->link_state = link_up;
1425
1426                         if (mgp->link_state == MXGEFW_LINK_UP) {
1427                                 if (netif_msg_link(mgp))
1428                                         printk(KERN_INFO
1429                                                "myri10ge: %s: link up\n",
1430                                                mgp->dev->name);
1431                                 netif_carrier_on(mgp->dev);
1432                                 mgp->link_changes++;
1433                         } else {
1434                                 if (netif_msg_link(mgp))
1435                                         printk(KERN_INFO
1436                                                "myri10ge: %s: link %s\n",
1437                                                mgp->dev->name,
1438                                                (link_up == MXGEFW_LINK_MYRINET ?
1439                                                 "mismatch (Myrinet detected)" :
1440                                                 "down"));
1441                                 netif_carrier_off(mgp->dev);
1442                                 mgp->link_changes++;
1443                         }
1444                 }
1445                 if (mgp->rdma_tags_available !=
1446                     ntohl(stats->rdma_tags_available)) {
1447                         mgp->rdma_tags_available =
1448                             ntohl(stats->rdma_tags_available);
1449                         printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1450                                "%d tags left\n", mgp->dev->name,
1451                                mgp->rdma_tags_available);
1452                 }
1453                 mgp->down_cnt += stats->link_down;
1454                 if (stats->link_down)
1455                         wake_up(&mgp->down_wq);
1456         }
1457 }
1458
1459 static int myri10ge_poll(struct napi_struct *napi, int budget)
1460 {
1461         struct myri10ge_slice_state *ss =
1462             container_of(napi, struct myri10ge_slice_state, napi);
1463         struct net_device *netdev = ss->mgp->dev;
1464         int work_done;
1465
1466 #ifdef CONFIG_DCA
1467         if (ss->mgp->dca_enabled)
1468                 myri10ge_update_dca(ss);
1469 #endif
1470
1471         /* process as many rx events as NAPI will allow */
1472         work_done = myri10ge_clean_rx_done(ss, budget);
1473
1474         if (work_done < budget) {
1475                 netif_rx_complete(netdev, napi);
1476                 put_be32(htonl(3), ss->irq_claim);
1477         }
1478         return work_done;
1479 }
1480
1481 static irqreturn_t myri10ge_intr(int irq, void *arg)
1482 {
1483         struct myri10ge_slice_state *ss = arg;
1484         struct myri10ge_priv *mgp = ss->mgp;
1485         struct mcp_irq_data *stats = ss->fw_stats;
1486         struct myri10ge_tx_buf *tx = &ss->tx;
1487         u32 send_done_count;
1488         int i;
1489
1490         /* an interrupt on a non-zero slice is implicitly valid
1491          * since MSI-X irqs are not shared */
1492         if (ss != mgp->ss) {
1493                 netif_rx_schedule(ss->dev, &ss->napi);
1494                 return (IRQ_HANDLED);
1495         }
1496
1497         /* make sure it is our IRQ, and that the DMA has finished */
1498         if (unlikely(!stats->valid))
1499                 return (IRQ_NONE);
1500
1501         /* low bit indicates receives are present, so schedule
1502          * napi poll handler */
1503         if (stats->valid & 1)
1504                 netif_rx_schedule(ss->dev, &ss->napi);
1505
1506         if (!mgp->msi_enabled && !mgp->msix_enabled) {
1507                 put_be32(0, mgp->irq_deassert);
1508                 if (!myri10ge_deassert_wait)
1509                         stats->valid = 0;
1510                 mb();
1511         } else
1512                 stats->valid = 0;
1513
1514         /* Wait for IRQ line to go low, if using INTx */
1515         i = 0;
1516         while (1) {
1517                 i++;
1518                 /* check for transmit completes and receives */
1519                 send_done_count = ntohl(stats->send_done_count);
1520                 if (send_done_count != tx->pkt_done)
1521                         myri10ge_tx_done(ss, (int)send_done_count);
1522                 if (unlikely(i > myri10ge_max_irq_loops)) {
1523                         printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1524                                mgp->dev->name);
1525                         stats->valid = 0;
1526                         schedule_work(&mgp->watchdog_work);
1527                 }
1528                 if (likely(stats->valid == 0))
1529                         break;
1530                 cpu_relax();
1531                 barrier();
1532         }
1533
1534         myri10ge_check_statblock(mgp);
1535
1536         put_be32(htonl(3), ss->irq_claim + 1);
1537         return (IRQ_HANDLED);
1538 }
1539
1540 static int
1541 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1542 {
1543         struct myri10ge_priv *mgp = netdev_priv(netdev);
1544         char *ptr;
1545         int i;
1546
1547         cmd->autoneg = AUTONEG_DISABLE;
1548         cmd->speed = SPEED_10000;
1549         cmd->duplex = DUPLEX_FULL;
1550
1551         /*
1552          * parse the product code to deterimine the interface type
1553          * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1554          * after the 3rd dash in the driver's cached copy of the
1555          * EEPROM's product code string.
1556          */
1557         ptr = mgp->product_code_string;
1558         if (ptr == NULL) {
1559                 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
1560                        netdev->name);
1561                 return 0;
1562         }
1563         for (i = 0; i < 3; i++, ptr++) {
1564                 ptr = strchr(ptr, '-');
1565                 if (ptr == NULL) {
1566                         printk(KERN_ERR "myri10ge: %s: Invalid product "
1567                                "code %s\n", netdev->name,
1568                                mgp->product_code_string);
1569                         return 0;
1570                 }
1571         }
1572         if (*ptr == 'R' || *ptr == 'Q') {
1573                 /* We've found either an XFP or quad ribbon fiber */
1574                 cmd->port = PORT_FIBRE;
1575         }
1576         return 0;
1577 }
1578
1579 static void
1580 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1581 {
1582         struct myri10ge_priv *mgp = netdev_priv(netdev);
1583
1584         strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1585         strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1586         strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1587         strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1588 }
1589
1590 static int
1591 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1592 {
1593         struct myri10ge_priv *mgp = netdev_priv(netdev);
1594
1595         coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1596         return 0;
1597 }
1598
1599 static int
1600 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1601 {
1602         struct myri10ge_priv *mgp = netdev_priv(netdev);
1603
1604         mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1605         put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1606         return 0;
1607 }
1608
1609 static void
1610 myri10ge_get_pauseparam(struct net_device *netdev,
1611                         struct ethtool_pauseparam *pause)
1612 {
1613         struct myri10ge_priv *mgp = netdev_priv(netdev);
1614
1615         pause->autoneg = 0;
1616         pause->rx_pause = mgp->pause;
1617         pause->tx_pause = mgp->pause;
1618 }
1619
1620 static int
1621 myri10ge_set_pauseparam(struct net_device *netdev,
1622                         struct ethtool_pauseparam *pause)
1623 {
1624         struct myri10ge_priv *mgp = netdev_priv(netdev);
1625
1626         if (pause->tx_pause != mgp->pause)
1627                 return myri10ge_change_pause(mgp, pause->tx_pause);
1628         if (pause->rx_pause != mgp->pause)
1629                 return myri10ge_change_pause(mgp, pause->tx_pause);
1630         if (pause->autoneg != 0)
1631                 return -EINVAL;
1632         return 0;
1633 }
1634
1635 static void
1636 myri10ge_get_ringparam(struct net_device *netdev,
1637                        struct ethtool_ringparam *ring)
1638 {
1639         struct myri10ge_priv *mgp = netdev_priv(netdev);
1640
1641         ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1642         ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
1643         ring->rx_jumbo_max_pending = 0;
1644         ring->tx_max_pending = mgp->ss[0].rx_small.mask + 1;
1645         ring->rx_mini_pending = ring->rx_mini_max_pending;
1646         ring->rx_pending = ring->rx_max_pending;
1647         ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1648         ring->tx_pending = ring->tx_max_pending;
1649 }
1650
1651 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1652 {
1653         struct myri10ge_priv *mgp = netdev_priv(netdev);
1654
1655         if (mgp->csum_flag)
1656                 return 1;
1657         else
1658                 return 0;
1659 }
1660
1661 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1662 {
1663         struct myri10ge_priv *mgp = netdev_priv(netdev);
1664
1665         if (csum_enabled)
1666                 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1667         else
1668                 mgp->csum_flag = 0;
1669         return 0;
1670 }
1671
1672 static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1673 {
1674         struct myri10ge_priv *mgp = netdev_priv(netdev);
1675         unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1676
1677         if (tso_enabled)
1678                 netdev->features |= flags;
1679         else
1680                 netdev->features &= ~flags;
1681         return 0;
1682 }
1683
1684 static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
1685         "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1686         "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1687         "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1688         "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1689         "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1690         "tx_heartbeat_errors", "tx_window_errors",
1691         /* device-specific stats */
1692         "tx_boundary", "WC", "irq", "MSI", "MSIX",
1693         "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1694         "serial_number", "watchdog_resets",
1695 #ifdef CONFIG_DCA
1696         "dca_capable", "dca_enabled",
1697 #endif
1698         "link_changes", "link_up", "dropped_link_overflow",
1699         "dropped_link_error_or_filtered",
1700         "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1701         "dropped_unicast_filtered", "dropped_multicast_filtered",
1702         "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1703         "dropped_no_big_buffer"
1704 };
1705
1706 static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1707         "----------- slice ---------",
1708         "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1709         "rx_small_cnt", "rx_big_cnt",
1710         "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1711             "LRO flushed",
1712         "LRO avg aggr", "LRO no_desc"
1713 };
1714
1715 #define MYRI10GE_NET_STATS_LEN      21
1716 #define MYRI10GE_MAIN_STATS_LEN  ARRAY_SIZE(myri10ge_gstrings_main_stats)
1717 #define MYRI10GE_SLICE_STATS_LEN  ARRAY_SIZE(myri10ge_gstrings_slice_stats)
1718
1719 static void
1720 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1721 {
1722         struct myri10ge_priv *mgp = netdev_priv(netdev);
1723         int i;
1724
1725         switch (stringset) {
1726         case ETH_SS_STATS:
1727                 memcpy(data, *myri10ge_gstrings_main_stats,
1728                        sizeof(myri10ge_gstrings_main_stats));
1729                 data += sizeof(myri10ge_gstrings_main_stats);
1730                 for (i = 0; i < mgp->num_slices; i++) {
1731                         memcpy(data, *myri10ge_gstrings_slice_stats,
1732                                sizeof(myri10ge_gstrings_slice_stats));
1733                         data += sizeof(myri10ge_gstrings_slice_stats);
1734                 }
1735                 break;
1736         }
1737 }
1738
1739 static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1740 {
1741         struct myri10ge_priv *mgp = netdev_priv(netdev);
1742
1743         switch (sset) {
1744         case ETH_SS_STATS:
1745                 return MYRI10GE_MAIN_STATS_LEN +
1746                     mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
1747         default:
1748                 return -EOPNOTSUPP;
1749         }
1750 }
1751
1752 static void
1753 myri10ge_get_ethtool_stats(struct net_device *netdev,
1754                            struct ethtool_stats *stats, u64 * data)
1755 {
1756         struct myri10ge_priv *mgp = netdev_priv(netdev);
1757         struct myri10ge_slice_state *ss;
1758         int slice;
1759         int i;
1760
1761         for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1762                 data[i] = ((unsigned long *)&mgp->stats)[i];
1763
1764         data[i++] = (unsigned int)mgp->tx_boundary;
1765         data[i++] = (unsigned int)mgp->wc_enabled;
1766         data[i++] = (unsigned int)mgp->pdev->irq;
1767         data[i++] = (unsigned int)mgp->msi_enabled;
1768         data[i++] = (unsigned int)mgp->msix_enabled;
1769         data[i++] = (unsigned int)mgp->read_dma;
1770         data[i++] = (unsigned int)mgp->write_dma;
1771         data[i++] = (unsigned int)mgp->read_write_dma;
1772         data[i++] = (unsigned int)mgp->serial_number;
1773         data[i++] = (unsigned int)mgp->watchdog_resets;
1774 #ifdef CONFIG_DCA
1775         data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1776         data[i++] = (unsigned int)(mgp->dca_enabled);
1777 #endif
1778         data[i++] = (unsigned int)mgp->link_changes;
1779
1780         /* firmware stats are useful only in the first slice */
1781         ss = &mgp->ss[0];
1782         data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1783         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
1784         data[i++] =
1785             (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1786         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1787         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1788         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1789         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
1790         data[i++] =
1791             (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1792         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1793         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1794         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1795         data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1796
1797         for (slice = 0; slice < mgp->num_slices; slice++) {
1798                 ss = &mgp->ss[slice];
1799                 data[i++] = slice;
1800                 data[i++] = (unsigned int)ss->tx.pkt_start;
1801                 data[i++] = (unsigned int)ss->tx.pkt_done;
1802                 data[i++] = (unsigned int)ss->tx.req;
1803                 data[i++] = (unsigned int)ss->tx.done;
1804                 data[i++] = (unsigned int)ss->rx_small.cnt;
1805                 data[i++] = (unsigned int)ss->rx_big.cnt;
1806                 data[i++] = (unsigned int)ss->tx.wake_queue;
1807                 data[i++] = (unsigned int)ss->tx.stop_queue;
1808                 data[i++] = (unsigned int)ss->tx.linearized;
1809                 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1810                 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1811                 if (ss->rx_done.lro_mgr.stats.flushed)
1812                         data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1813                             ss->rx_done.lro_mgr.stats.flushed;
1814                 else
1815                         data[i++] = 0;
1816                 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1817         }
1818 }
1819
1820 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1821 {
1822         struct myri10ge_priv *mgp = netdev_priv(netdev);
1823         mgp->msg_enable = value;
1824 }
1825
1826 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1827 {
1828         struct myri10ge_priv *mgp = netdev_priv(netdev);
1829         return mgp->msg_enable;
1830 }
1831
1832 static const struct ethtool_ops myri10ge_ethtool_ops = {
1833         .get_settings = myri10ge_get_settings,
1834         .get_drvinfo = myri10ge_get_drvinfo,
1835         .get_coalesce = myri10ge_get_coalesce,
1836         .set_coalesce = myri10ge_set_coalesce,
1837         .get_pauseparam = myri10ge_get_pauseparam,
1838         .set_pauseparam = myri10ge_set_pauseparam,
1839         .get_ringparam = myri10ge_get_ringparam,
1840         .get_rx_csum = myri10ge_get_rx_csum,
1841         .set_rx_csum = myri10ge_set_rx_csum,
1842         .set_tx_csum = ethtool_op_set_tx_hw_csum,
1843         .set_sg = ethtool_op_set_sg,
1844         .set_tso = myri10ge_set_tso,
1845         .get_link = ethtool_op_get_link,
1846         .get_strings = myri10ge_get_strings,
1847         .get_sset_count = myri10ge_get_sset_count,
1848         .get_ethtool_stats = myri10ge_get_ethtool_stats,
1849         .set_msglevel = myri10ge_set_msglevel,
1850         .get_msglevel = myri10ge_get_msglevel
1851 };
1852
1853 static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
1854 {
1855         struct myri10ge_priv *mgp = ss->mgp;
1856         struct myri10ge_cmd cmd;
1857         struct net_device *dev = mgp->dev;
1858         int tx_ring_size, rx_ring_size;
1859         int tx_ring_entries, rx_ring_entries;
1860         int i, slice, status;
1861         size_t bytes;
1862
1863         /* get ring sizes */
1864         slice = ss - mgp->ss;
1865         cmd.data0 = slice;
1866         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1867         tx_ring_size = cmd.data0;
1868         cmd.data0 = slice;
1869         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1870         if (status != 0)
1871                 return status;
1872         rx_ring_size = cmd.data0;
1873
1874         tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1875         rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1876         ss->tx.mask = tx_ring_entries - 1;
1877         ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
1878
1879         status = -ENOMEM;
1880
1881         /* allocate the host shadow rings */
1882
1883         bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1884             * sizeof(*ss->tx.req_list);
1885         ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1886         if (ss->tx.req_bytes == NULL)
1887                 goto abort_with_nothing;
1888
1889         /* ensure req_list entries are aligned to 8 bytes */
1890         ss->tx.req_list = (struct mcp_kreq_ether_send *)
1891             ALIGN((unsigned long)ss->tx.req_bytes, 8);
1892
1893         bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1894         ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1895         if (ss->rx_small.shadow == NULL)
1896                 goto abort_with_tx_req_bytes;
1897
1898         bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1899         ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1900         if (ss->rx_big.shadow == NULL)
1901                 goto abort_with_rx_small_shadow;
1902
1903         /* allocate the host info rings */
1904
1905         bytes = tx_ring_entries * sizeof(*ss->tx.info);
1906         ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1907         if (ss->tx.info == NULL)
1908                 goto abort_with_rx_big_shadow;
1909
1910         bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1911         ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1912         if (ss->rx_small.info == NULL)
1913                 goto abort_with_tx_info;
1914
1915         bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1916         ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1917         if (ss->rx_big.info == NULL)
1918                 goto abort_with_rx_small_info;
1919
1920         /* Fill the receive rings */
1921         ss->rx_big.cnt = 0;
1922         ss->rx_small.cnt = 0;
1923         ss->rx_big.fill_cnt = 0;
1924         ss->rx_small.fill_cnt = 0;
1925         ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1926         ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1927         ss->rx_small.watchdog_needed = 0;
1928         ss->rx_big.watchdog_needed = 0;
1929         myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1930                                 mgp->small_bytes + MXGEFW_PAD, 0);
1931
1932         if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
1933                 printk(KERN_ERR
1934                        "myri10ge: %s:slice-%d: alloced only %d small bufs\n",
1935                        dev->name, slice, ss->rx_small.fill_cnt);
1936                 goto abort_with_rx_small_ring;
1937         }
1938
1939         myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1940         if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
1941                 printk(KERN_ERR
1942                        "myri10ge: %s:slice-%d: alloced only %d big bufs\n",
1943                        dev->name, slice, ss->rx_big.fill_cnt);
1944                 goto abort_with_rx_big_ring;
1945         }
1946
1947         return 0;
1948
1949 abort_with_rx_big_ring:
1950         for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1951                 int idx = i & ss->rx_big.mask;
1952                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
1953                                        mgp->big_bytes);
1954                 put_page(ss->rx_big.info[idx].page);
1955         }
1956
1957 abort_with_rx_small_ring:
1958         for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
1959                 int idx = i & ss->rx_small.mask;
1960                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
1961                                        mgp->small_bytes + MXGEFW_PAD);
1962                 put_page(ss->rx_small.info[idx].page);
1963         }
1964
1965         kfree(ss->rx_big.info);
1966
1967 abort_with_rx_small_info:
1968         kfree(ss->rx_small.info);
1969
1970 abort_with_tx_info:
1971         kfree(ss->tx.info);
1972
1973 abort_with_rx_big_shadow:
1974         kfree(ss->rx_big.shadow);
1975
1976 abort_with_rx_small_shadow:
1977         kfree(ss->rx_small.shadow);
1978
1979 abort_with_tx_req_bytes:
1980         kfree(ss->tx.req_bytes);
1981         ss->tx.req_bytes = NULL;
1982         ss->tx.req_list = NULL;
1983
1984 abort_with_nothing:
1985         return status;
1986 }
1987
1988 static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
1989 {
1990         struct myri10ge_priv *mgp = ss->mgp;
1991         struct sk_buff *skb;
1992         struct myri10ge_tx_buf *tx;
1993         int i, len, idx;
1994
1995         /* If not allocated, skip it */
1996         if (ss->tx.req_list == NULL)
1997                 return;
1998
1999         for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
2000                 idx = i & ss->rx_big.mask;
2001                 if (i == ss->rx_big.fill_cnt - 1)
2002                         ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
2003                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2004                                        mgp->big_bytes);
2005                 put_page(ss->rx_big.info[idx].page);
2006         }
2007
2008         for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
2009                 idx = i & ss->rx_small.mask;
2010                 if (i == ss->rx_small.fill_cnt - 1)
2011                         ss->rx_small.info[idx].page_offset =
2012                             MYRI10GE_ALLOC_SIZE;
2013                 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2014                                        mgp->small_bytes + MXGEFW_PAD);
2015                 put_page(ss->rx_small.info[idx].page);
2016         }
2017         tx = &ss->tx;
2018         while (tx->done != tx->req) {
2019                 idx = tx->done & tx->mask;
2020                 skb = tx->info[idx].skb;
2021
2022                 /* Mark as free */
2023                 tx->info[idx].skb = NULL;
2024                 tx->done++;
2025                 len = pci_unmap_len(&tx->info[idx], len);
2026                 pci_unmap_len_set(&tx->info[idx], len, 0);
2027                 if (skb) {
2028                         ss->stats.tx_dropped++;
2029                         dev_kfree_skb_any(skb);
2030                         if (len)
2031                                 pci_unmap_single(mgp->pdev,
2032                                                  pci_unmap_addr(&tx->info[idx],
2033                                                                 bus), len,
2034                                                  PCI_DMA_TODEVICE);
2035                 } else {
2036                         if (len)
2037                                 pci_unmap_page(mgp->pdev,
2038                                                pci_unmap_addr(&tx->info[idx],
2039                                                               bus), len,
2040                                                PCI_DMA_TODEVICE);
2041                 }
2042         }
2043         kfree(ss->rx_big.info);
2044
2045         kfree(ss->rx_small.info);
2046
2047         kfree(ss->tx.info);
2048
2049         kfree(ss->rx_big.shadow);
2050
2051         kfree(ss->rx_small.shadow);
2052
2053         kfree(ss->tx.req_bytes);
2054         ss->tx.req_bytes = NULL;
2055         ss->tx.req_list = NULL;
2056 }
2057
2058 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2059 {
2060         struct pci_dev *pdev = mgp->pdev;
2061         struct myri10ge_slice_state *ss;
2062         struct net_device *netdev = mgp->dev;
2063         int i;
2064         int status;
2065
2066         mgp->msi_enabled = 0;
2067         mgp->msix_enabled = 0;
2068         status = 0;
2069         if (myri10ge_msi) {
2070                 if (mgp->num_slices > 1) {
2071                         status =
2072                             pci_enable_msix(pdev, mgp->msix_vectors,
2073                                             mgp->num_slices);
2074                         if (status == 0) {
2075                                 mgp->msix_enabled = 1;
2076                         } else {
2077                                 dev_err(&pdev->dev,
2078                                         "Error %d setting up MSI-X\n", status);
2079                                 return status;
2080                         }
2081                 }
2082                 if (mgp->msix_enabled == 0) {
2083                         status = pci_enable_msi(pdev);
2084                         if (status != 0) {
2085                                 dev_err(&pdev->dev,
2086                                         "Error %d setting up MSI; falling back to xPIC\n",
2087                                         status);
2088                         } else {
2089                                 mgp->msi_enabled = 1;
2090                         }
2091                 }
2092         }
2093         if (mgp->msix_enabled) {
2094                 for (i = 0; i < mgp->num_slices; i++) {
2095                         ss = &mgp->ss[i];
2096                         snprintf(ss->irq_desc, sizeof(ss->irq_desc),
2097                                  "%s:slice-%d", netdev->name, i);
2098                         status = request_irq(mgp->msix_vectors[i].vector,
2099                                              myri10ge_intr, 0, ss->irq_desc,
2100                                              ss);
2101                         if (status != 0) {
2102                                 dev_err(&pdev->dev,
2103                                         "slice %d failed to allocate IRQ\n", i);
2104                                 i--;
2105                                 while (i >= 0) {
2106                                         free_irq(mgp->msix_vectors[i].vector,
2107                                                  &mgp->ss[i]);
2108                                         i--;
2109                                 }
2110                                 pci_disable_msix(pdev);
2111                                 return status;
2112                         }
2113                 }
2114         } else {
2115                 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2116                                      mgp->dev->name, &mgp->ss[0]);
2117                 if (status != 0) {
2118                         dev_err(&pdev->dev, "failed to allocate IRQ\n");
2119                         if (mgp->msi_enabled)
2120                                 pci_disable_msi(pdev);
2121                 }
2122         }
2123         return status;
2124 }
2125
2126 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2127 {
2128         struct pci_dev *pdev = mgp->pdev;
2129         int i;
2130
2131         if (mgp->msix_enabled) {
2132                 for (i = 0; i < mgp->num_slices; i++)
2133                         free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2134         } else {
2135                 free_irq(pdev->irq, &mgp->ss[0]);
2136         }
2137         if (mgp->msi_enabled)
2138                 pci_disable_msi(pdev);
2139         if (mgp->msix_enabled)
2140                 pci_disable_msix(pdev);
2141 }
2142
2143 static int
2144 myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
2145                          void **ip_hdr, void **tcpudp_hdr,
2146                          u64 * hdr_flags, void *priv)
2147 {
2148         struct ethhdr *eh;
2149         struct vlan_ethhdr *veh;
2150         struct iphdr *iph;
2151         u8 *va = page_address(frag->page) + frag->page_offset;
2152         unsigned long ll_hlen;
2153         /* passed opaque through lro_receive_frags() */
2154         __wsum csum = (__force __wsum) (unsigned long)priv;
2155
2156         /* find the mac header, aborting if not IPv4 */
2157
2158         eh = (struct ethhdr *)va;
2159         *mac_hdr = eh;
2160         ll_hlen = ETH_HLEN;
2161         if (eh->h_proto != htons(ETH_P_IP)) {
2162                 if (eh->h_proto == htons(ETH_P_8021Q)) {
2163                         veh = (struct vlan_ethhdr *)va;
2164                         if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
2165                                 return -1;
2166
2167                         ll_hlen += VLAN_HLEN;
2168
2169                         /*
2170                          *  HW checksum starts ETH_HLEN bytes into
2171                          *  frame, so we must subtract off the VLAN
2172                          *  header's checksum before csum can be used
2173                          */
2174                         csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
2175                                                            VLAN_HLEN, 0));
2176                 } else {
2177                         return -1;
2178                 }
2179         }
2180         *hdr_flags = LRO_IPV4;
2181
2182         iph = (struct iphdr *)(va + ll_hlen);
2183         *ip_hdr = iph;
2184         if (iph->protocol != IPPROTO_TCP)
2185                 return -1;
2186         *hdr_flags |= LRO_TCP;
2187         *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
2188
2189         /* verify the IP checksum */
2190         if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
2191                 return -1;
2192
2193         /* verify the  checksum */
2194         if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
2195                                        ntohs(iph->tot_len) - (iph->ihl << 2),
2196                                        IPPROTO_TCP, csum)))
2197                 return -1;
2198
2199         return 0;
2200 }
2201
2202 static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2203 {
2204         struct myri10ge_cmd cmd;
2205         struct myri10ge_slice_state *ss;
2206         int status;
2207
2208         ss = &mgp->ss[slice];
2209         cmd.data0 = 0;          /* single slice for now */
2210         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
2211         ss->tx.lanai = (struct mcp_kreq_ether_send __iomem *)
2212             (mgp->sram + cmd.data0);
2213
2214         cmd.data0 = slice;
2215         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2216                                     &cmd, 0);
2217         ss->rx_small.lanai = (struct mcp_kreq_ether_recv __iomem *)
2218             (mgp->sram + cmd.data0);
2219
2220         cmd.data0 = slice;
2221         status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2222         ss->rx_big.lanai = (struct mcp_kreq_ether_recv __iomem *)
2223             (mgp->sram + cmd.data0);
2224
2225         if (myri10ge_wcfifo && mgp->wc_enabled) {
2226                 ss->tx.wc_fifo = (u8 __iomem *)
2227                     mgp->sram + MXGEFW_ETH_SEND_4 + 64 * slice;
2228                 ss->rx_small.wc_fifo = (u8 __iomem *)
2229                     mgp->sram + MXGEFW_ETH_RECV_SMALL + 64 * slice;
2230                 ss->rx_big.wc_fifo = (u8 __iomem *)
2231                     mgp->sram + MXGEFW_ETH_RECV_BIG + 64 * slice;
2232         } else {
2233                 ss->tx.wc_fifo = NULL;
2234                 ss->rx_small.wc_fifo = NULL;
2235                 ss->rx_big.wc_fifo = NULL;
2236         }
2237         return status;
2238
2239 }
2240
2241 static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2242 {
2243         struct myri10ge_cmd cmd;
2244         struct myri10ge_slice_state *ss;
2245         int status;
2246
2247         ss = &mgp->ss[slice];
2248         cmd.data0 = MYRI10GE_LOWPART_TO_U32(ss->fw_stats_bus);
2249         cmd.data1 = MYRI10GE_HIGHPART_TO_U32(ss->fw_stats_bus);
2250         cmd.data2 = sizeof(struct mcp_irq_data);
2251         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2252         if (status == -ENOSYS) {
2253                 dma_addr_t bus = ss->fw_stats_bus;
2254                 if (slice != 0)
2255                         return -EINVAL;
2256                 bus += offsetof(struct mcp_irq_data, send_done_count);
2257                 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2258                 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2259                 status = myri10ge_send_cmd(mgp,
2260                                            MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2261                                            &cmd, 0);
2262                 /* Firmware cannot support multicast without STATS_DMA_V2 */
2263                 mgp->fw_multicast_support = 0;
2264         } else {
2265                 mgp->fw_multicast_support = 1;
2266         }
2267         return 0;
2268 }
2269
2270 static int myri10ge_open(struct net_device *dev)
2271 {
2272         struct myri10ge_slice_state *ss;
2273         struct myri10ge_priv *mgp = netdev_priv(dev);
2274         struct myri10ge_cmd cmd;
2275         int i, status, big_pow2, slice;
2276         u8 *itable;
2277         struct net_lro_mgr *lro_mgr;
2278
2279         if (mgp->running != MYRI10GE_ETH_STOPPED)
2280                 return -EBUSY;
2281
2282         mgp->running = MYRI10GE_ETH_STARTING;
2283         status = myri10ge_reset(mgp);
2284         if (status != 0) {
2285                 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
2286                 goto abort_with_nothing;
2287         }
2288
2289         if (mgp->num_slices > 1) {
2290                 cmd.data0 = mgp->num_slices;
2291                 cmd.data1 = 1;  /* use MSI-X */
2292                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2293                                            &cmd, 0);
2294                 if (status != 0) {
2295                         printk(KERN_ERR
2296                                "myri10ge: %s: failed to set number of slices\n",
2297                                dev->name);
2298                         goto abort_with_nothing;
2299                 }
2300                 /* setup the indirection table */
2301                 cmd.data0 = mgp->num_slices;
2302                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2303                                            &cmd, 0);
2304
2305                 status |= myri10ge_send_cmd(mgp,
2306                                             MXGEFW_CMD_GET_RSS_TABLE_OFFSET,
2307                                             &cmd, 0);
2308                 if (status != 0) {
2309                         printk(KERN_ERR
2310                                "myri10ge: %s: failed to setup rss tables\n",
2311                                dev->name);
2312                 }
2313
2314                 /* just enable an identity mapping */
2315                 itable = mgp->sram + cmd.data0;
2316                 for (i = 0; i < mgp->num_slices; i++)
2317                         __raw_writeb(i, &itable[i]);
2318
2319                 cmd.data0 = 1;
2320                 cmd.data1 = myri10ge_rss_hash;
2321                 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2322                                            &cmd, 0);
2323                 if (status != 0) {
2324                         printk(KERN_ERR
2325                                "myri10ge: %s: failed to enable slices\n",
2326                                dev->name);
2327                         goto abort_with_nothing;
2328                 }
2329         }
2330
2331         status = myri10ge_request_irq(mgp);
2332         if (status != 0)
2333                 goto abort_with_nothing;
2334
2335         /* decide what small buffer size to use.  For good TCP rx
2336          * performance, it is important to not receive 1514 byte
2337          * frames into jumbo buffers, as it confuses the socket buffer
2338          * accounting code, leading to drops and erratic performance.
2339          */
2340
2341         if (dev->mtu <= ETH_DATA_LEN)
2342                 /* enough for a TCP header */
2343                 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2344                     ? (128 - MXGEFW_PAD)
2345                     : (SMP_CACHE_BYTES - MXGEFW_PAD);
2346         else
2347                 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
2348                 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
2349
2350         /* Override the small buffer size? */
2351         if (myri10ge_small_bytes > 0)
2352                 mgp->small_bytes = myri10ge_small_bytes;
2353
2354         /* Firmware needs the big buff size as a power of 2.  Lie and
2355          * tell him the buffer is larger, because we only use 1
2356          * buffer/pkt, and the mtu will prevent overruns.
2357          */
2358         big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2359         if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
2360                 while (!is_power_of_2(big_pow2))
2361                         big_pow2++;
2362                 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2363         } else {
2364                 big_pow2 = MYRI10GE_ALLOC_SIZE;
2365                 mgp->big_bytes = big_pow2;
2366         }
2367
2368         /* setup the per-slice data structures */
2369         for (slice = 0; slice < mgp->num_slices; slice++) {
2370                 ss = &mgp->ss[slice];
2371
2372                 status = myri10ge_get_txrx(mgp, slice);
2373                 if (status != 0) {
2374                         printk(KERN_ERR
2375                                "myri10ge: %s: failed to get ring sizes or locations\n",
2376                                dev->name);
2377                         goto abort_with_rings;
2378                 }
2379                 status = myri10ge_allocate_rings(ss);
2380                 if (status != 0)
2381                         goto abort_with_rings;
2382                 if (slice == 0)
2383                         status = myri10ge_set_stats(mgp, slice);
2384                 if (status) {
2385                         printk(KERN_ERR
2386                                "myri10ge: %s: Couldn't set stats DMA\n",
2387                                dev->name);
2388                         goto abort_with_rings;
2389                 }
2390
2391                 lro_mgr = &ss->rx_done.lro_mgr;
2392                 lro_mgr->dev = dev;
2393                 lro_mgr->features = LRO_F_NAPI;
2394                 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2395                 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2396                 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2397                 lro_mgr->lro_arr = ss->rx_done.lro_desc;
2398                 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2399                 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2400                 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2401                         lro_mgr->max_aggr = MAX_SKB_FRAGS;
2402
2403                 /* must happen prior to any irq */
2404                 napi_enable(&(ss)->napi);
2405         }
2406
2407         /* now give firmware buffers sizes, and MTU */
2408         cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2409         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2410         cmd.data0 = mgp->small_bytes;
2411         status |=
2412             myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2413         cmd.data0 = big_pow2;
2414         status |=
2415             myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2416         if (status) {
2417                 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2418                        dev->name);
2419                 goto abort_with_rings;
2420         }
2421
2422         /*
2423          * Set Linux style TSO mode; this is needed only on newer
2424          *  firmware versions.  Older versions default to Linux
2425          *  style TSO
2426          */
2427         cmd.data0 = 0;
2428         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2429         if (status && status != -ENOSYS) {
2430                 printk(KERN_ERR "myri10ge: %s: Couldn't set TSO mode\n",
2431                        dev->name);
2432                 goto abort_with_rings;
2433         }
2434
2435         mgp->link_state = ~0U;
2436         mgp->rdma_tags_available = 15;
2437
2438         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2439         if (status) {
2440                 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2441                        dev->name);
2442                 goto abort_with_rings;
2443         }
2444
2445         mgp->running = MYRI10GE_ETH_RUNNING;
2446         mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2447         add_timer(&mgp->watchdog_timer);
2448         netif_wake_queue(dev);
2449         return 0;
2450
2451 abort_with_rings:
2452         for (i = 0; i < mgp->num_slices; i++)
2453                 myri10ge_free_rings(&mgp->ss[i]);
2454
2455         myri10ge_free_irq(mgp);
2456
2457 abort_with_nothing:
2458         mgp->running = MYRI10GE_ETH_STOPPED;
2459         return -ENOMEM;
2460 }
2461
2462 static int myri10ge_close(struct net_device *dev)
2463 {
2464         struct myri10ge_priv *mgp = netdev_priv(dev);
2465         struct myri10ge_cmd cmd;
2466         int status, old_down_cnt;
2467         int i;
2468
2469         if (mgp->running != MYRI10GE_ETH_RUNNING)
2470                 return 0;
2471
2472         if (mgp->ss[0].tx.req_bytes == NULL)
2473                 return 0;
2474
2475         del_timer_sync(&mgp->watchdog_timer);
2476         mgp->running = MYRI10GE_ETH_STOPPING;
2477         for (i = 0; i < mgp->num_slices; i++) {
2478                 napi_disable(&mgp->ss[i].napi);
2479         }
2480         netif_carrier_off(dev);
2481         netif_stop_queue(dev);
2482         old_down_cnt = mgp->down_cnt;
2483         mb();
2484         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2485         if (status)
2486                 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2487                        dev->name);
2488
2489         wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2490         if (old_down_cnt == mgp->down_cnt)
2491                 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2492
2493         netif_tx_disable(dev);
2494         myri10ge_free_irq(mgp);
2495         for (i = 0; i < mgp->num_slices; i++)
2496                 myri10ge_free_rings(&mgp->ss[i]);
2497
2498         mgp->running = MYRI10GE_ETH_STOPPED;
2499         return 0;
2500 }
2501
2502 /* copy an array of struct mcp_kreq_ether_send's to the mcp.  Copy
2503  * backwards one at a time and handle ring wraps */
2504
2505 static inline void
2506 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2507                               struct mcp_kreq_ether_send *src, int cnt)
2508 {
2509         int idx, starting_slot;
2510         starting_slot = tx->req;
2511         while (cnt > 1) {
2512                 cnt--;
2513                 idx = (starting_slot + cnt) & tx->mask;
2514                 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2515                 mb();
2516         }
2517 }
2518
2519 /*
2520  * copy an array of struct mcp_kreq_ether_send's to the mcp.  Copy
2521  * at most 32 bytes at a time, so as to avoid involving the software
2522  * pio handler in the nic.   We re-write the first segment's flags
2523  * to mark them valid only after writing the entire chain.
2524  */
2525
2526 static inline void
2527 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2528                     int cnt)
2529 {
2530         int idx, i;
2531         struct mcp_kreq_ether_send __iomem *dstp, *dst;
2532         struct mcp_kreq_ether_send *srcp;
2533         u8 last_flags;
2534
2535         idx = tx->req & tx->mask;
2536
2537         last_flags = src->flags;
2538         src->flags = 0;
2539         mb();
2540         dst = dstp = &tx->lanai[idx];
2541         srcp = src;
2542
2543         if ((idx + cnt) < tx->mask) {
2544                 for (i = 0; i < (cnt - 1); i += 2) {
2545                         myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2546                         mb();   /* force write every 32 bytes */
2547                         srcp += 2;
2548                         dstp += 2;
2549                 }
2550         } else {
2551                 /* submit all but the first request, and ensure
2552                  * that it is submitted below */
2553                 myri10ge_submit_req_backwards(tx, src, cnt);
2554                 i = 0;
2555         }
2556         if (i < cnt) {
2557                 /* submit the first request */
2558                 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2559                 mb();           /* barrier before setting valid flag */
2560         }
2561
2562         /* re-write the last 32-bits with the valid flags */
2563         src->flags = last_flags;
2564         put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
2565         tx->req += cnt;
2566         mb();
2567 }
2568
2569 static inline void
2570 myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
2571                        struct mcp_kreq_ether_send *src, int cnt)
2572 {
2573         tx->req += cnt;
2574         mb();
2575         while (cnt >= 4) {
2576                 myri10ge_pio_copy(tx->wc_fifo, src, 64);
2577                 mb();
2578                 src += 4;
2579                 cnt -= 4;
2580         }
2581         if (cnt > 0) {
2582                 /* pad it to 64 bytes.  The src is 64 bytes bigger than it
2583                  * needs to be so that we don't overrun it */
2584                 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2585                                   src, 64);
2586                 mb();
2587         }
2588 }
2589
2590 /*
2591  * Transmit a packet.  We need to split the packet so that a single
2592  * segment does not cross myri10ge->tx_boundary, so this makes segment
2593  * counting tricky.  So rather than try to count segments up front, we
2594  * just give up if there are too few segments to hold a reasonably
2595  * fragmented packet currently available.  If we run
2596  * out of segments while preparing a packet for DMA, we just linearize
2597  * it and try again.
2598  */
2599
2600 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2601 {
2602         struct myri10ge_priv *mgp = netdev_priv(dev);
2603         struct myri10ge_slice_state *ss;
2604         struct mcp_kreq_ether_send *req;
2605         struct myri10ge_tx_buf *tx;
2606         struct skb_frag_struct *frag;
2607         dma_addr_t bus;
2608         u32 low;
2609         __be32 high_swapped;
2610         unsigned int len;
2611         int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2612         u16 pseudo_hdr_offset, cksum_offset;
2613         int cum_len, seglen, boundary, rdma_count;
2614         u8 flags, odd_flag;
2615
2616         /* always transmit through slot 0 */
2617         ss = mgp->ss;
2618         tx = &ss->tx;
2619 again:
2620         req = tx->req_list;
2621         avail = tx->mask - 1 - (tx->req - tx->done);
2622
2623         mss = 0;
2624         max_segments = MXGEFW_MAX_SEND_DESC;
2625
2626         if (skb_is_gso(skb)) {
2627                 mss = skb_shinfo(skb)->gso_size;
2628                 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2629         }
2630
2631         if ((unlikely(avail < max_segments))) {
2632                 /* we are out of transmit resources */
2633                 tx->stop_queue++;
2634                 netif_stop_queue(dev);
2635                 return 1;
2636         }
2637
2638         /* Setup checksum offloading, if needed */
2639         cksum_offset = 0;
2640         pseudo_hdr_offset = 0;
2641         odd_flag = 0;
2642         flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2643         if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2644                 cksum_offset = skb_transport_offset(skb);
2645                 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2646                 /* If the headers are excessively large, then we must
2647                  * fall back to a software checksum */
2648                 if (unlikely(!mss && (cksum_offset > 255 ||
2649                                       pseudo_hdr_offset > 127))) {
2650                         if (skb_checksum_help(skb))
2651                                 goto drop;
2652                         cksum_offset = 0;
2653                         pseudo_hdr_offset = 0;
2654                 } else {
2655                         odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2656                         flags |= MXGEFW_FLAGS_CKSUM;
2657                 }
2658         }
2659
2660         cum_len = 0;
2661
2662         if (mss) {              /* TSO */
2663                 /* this removes any CKSUM flag from before */
2664                 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2665
2666                 /* negative cum_len signifies to the
2667                  * send loop that we are still in the
2668                  * header portion of the TSO packet.
2669                  * TSO header can be at most 1KB long */
2670                 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2671
2672                 /* for IPv6 TSO, the checksum offset stores the
2673                  * TCP header length, to save the firmware from
2674                  * the need to parse the headers */
2675                 if (skb_is_gso_v6(skb)) {
2676                         cksum_offset = tcp_hdrlen(skb);
2677                         /* Can only handle headers <= max_tso6 long */
2678                         if (unlikely(-cum_len > mgp->max_tso6))
2679                                 return myri10ge_sw_tso(skb, dev);
2680                 }
2681                 /* for TSO, pseudo_hdr_offset holds mss.
2682                  * The firmware figures out where to put
2683                  * the checksum by parsing the header. */
2684                 pseudo_hdr_offset = mss;
2685         } else
2686                 /* Mark small packets, and pad out tiny packets */
2687         if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2688                 flags |= MXGEFW_FLAGS_SMALL;
2689
2690                 /* pad frames to at least ETH_ZLEN bytes */
2691                 if (unlikely(skb->len < ETH_ZLEN)) {
2692                         if (skb_padto(skb, ETH_ZLEN)) {
2693                                 /* The packet is gone, so we must
2694                                  * return 0 */
2695                                 ss->stats.tx_dropped += 1;
2696                                 return 0;
2697                         }
2698                         /* adjust the len to account for the zero pad
2699                          * so that the nic can know how long it is */
2700                         skb->len = ETH_ZLEN;
2701                 }
2702         }
2703
2704         /* map the skb for DMA */
2705         len = skb->len - skb->data_len;
2706         idx = tx->req & tx->mask;
2707         tx->info[idx].skb = skb;
2708         bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2709         pci_unmap_addr_set(&tx->info[idx], bus, bus);
2710         pci_unmap_len_set(&tx->info[idx], len, len);
2711
2712         frag_cnt = skb_shinfo(skb)->nr_frags;
2713         frag_idx = 0;
2714         count = 0;
2715         rdma_count = 0;
2716
2717         /* "rdma_count" is the number of RDMAs belonging to the
2718          * current packet BEFORE the current send request. For
2719          * non-TSO packets, this is equal to "count".
2720          * For TSO packets, rdma_count needs to be reset
2721          * to 0 after a segment cut.
2722          *
2723          * The rdma_count field of the send request is
2724          * the number of RDMAs of the packet starting at
2725          * that request. For TSO send requests with one ore more cuts
2726          * in the middle, this is the number of RDMAs starting
2727          * after the last cut in the request. All previous
2728          * segments before the last cut implicitly have 1 RDMA.
2729          *
2730          * Since the number of RDMAs is not known beforehand,
2731          * it must be filled-in retroactively - after each
2732          * segmentation cut or at the end of the entire packet.
2733          */
2734
2735         while (1) {
2736                 /* Break the SKB or Fragment up into pieces which
2737                  * do not cross mgp->tx_boundary */
2738                 low = MYRI10GE_LOWPART_TO_U32(bus);
2739                 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2740                 while (len) {
2741                         u8 flags_next;
2742                         int cum_len_next;
2743
2744                         if (unlikely(count == max_segments))
2745                                 goto abort_linearize;
2746
2747                         boundary =
2748                             (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
2749                         seglen = boundary - low;
2750                         if (seglen > len)
2751                                 seglen = len;
2752                         flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2753                         cum_len_next = cum_len + seglen;
2754                         if (mss) {      /* TSO */
2755                                 (req - rdma_count)->rdma_count = rdma_count + 1;
2756
2757                                 if (likely(cum_len >= 0)) {     /* payload */
2758                                         int next_is_first, chop;
2759
2760                                         chop = (cum_len_next > mss);
2761                                         cum_len_next = cum_len_next % mss;
2762                                         next_is_first = (cum_len_next == 0);
2763                                         flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2764                                         flags_next |= next_is_first *
2765                                             MXGEFW_FLAGS_FIRST;
2766                                         rdma_count |= -(chop | next_is_first);
2767                                         rdma_count += chop & !next_is_first;
2768                                 } else if (likely(cum_len_next >= 0)) { /* header ends */
2769                                         int small;
2770
2771                                         rdma_count = -1;
2772                                         cum_len_next = 0;
2773                                         seglen = -cum_len;
2774                                         small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2775                                         flags_next = MXGEFW_FLAGS_TSO_PLD |
2776                                             MXGEFW_FLAGS_FIRST |
2777                                             (small * MXGEFW_FLAGS_SMALL);
2778                                 }
2779                         }
2780                         req->addr_high = high_swapped;
2781                         req->addr_low = htonl(low);
2782                         req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2783                         req->pad = 0;   /* complete solid 16-byte block; does this matter? */
2784                         req->rdma_count = 1;
2785                         req->length = htons(seglen);
2786                         req->cksum_offset = cksum_offset;
2787                         req->flags = flags | ((cum_len & 1) * odd_flag);
2788
2789                         low += seglen;
2790                         len -= seglen;
2791                         cum_len = cum_len_next;
2792                         flags = flags_next;
2793                         req++;
2794                         count++;
2795                         rdma_count++;
2796                         if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2797                                 if (unlikely(cksum_offset > seglen))
2798                                         cksum_offset -= seglen;
2799                                 else
2800                                         cksum_offset = 0;
2801                         }
2802                 }
2803                 if (frag_idx == frag_cnt)
2804                         break;
2805
2806                 /* map next fragment for DMA */
2807                 idx = (count + tx->req) & tx->mask;
2808                 frag = &skb_shinfo(skb)->frags[frag_idx];
2809                 frag_idx++;
2810                 len = frag->size;
2811                 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2812                                    len, PCI_DMA_TODEVICE);
2813                 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2814                 pci_unmap_len_set(&tx->info[idx], len, len);
2815         }
2816
2817         (req - rdma_count)->rdma_count = rdma_count;
2818         if (mss)
2819                 do {
2820                         req--;
2821                         req->flags |= MXGEFW_FLAGS_TSO_LAST;
2822                 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2823                                          MXGEFW_FLAGS_FIRST)));
2824         idx = ((count - 1) + tx->req) & tx->mask;
2825         tx->info[idx].last = 1;
2826         if (tx->wc_fifo == NULL)
2827                 myri10ge_submit_req(tx, tx->req_list, count);
2828         else
2829                 myri10ge_submit_req_wc(tx, tx->req_list, count);
2830         tx->pkt_start++;
2831         if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2832                 tx->stop_queue++;
2833                 netif_stop_queue(dev);
2834         }
2835         dev->trans_start = jiffies;
2836         return 0;
2837
2838 abort_linearize:
2839         /* Free any DMA resources we've alloced and clear out the skb
2840          * slot so as to not trip up assertions, and to avoid a
2841          * double-free if linearizing fails */
2842
2843         last_idx = (idx + 1) & tx->mask;
2844         idx = tx->req & tx->mask;
2845         tx->info[idx].skb = NULL;
2846         do {
2847                 len = pci_unmap_len(&tx->info[idx], len);
2848                 if (len) {
2849                         if (tx->info[idx].skb != NULL)
2850                                 pci_unmap_single(mgp->pdev,
2851                                                  pci_unmap_addr(&tx->info[idx],
2852                                                                 bus), len,
2853                                                  PCI_DMA_TODEVICE);
2854                         else
2855                                 pci_unmap_page(mgp->pdev,
2856                                                pci_unmap_addr(&tx->info[idx],
2857                                                               bus), len,
2858                                                PCI_DMA_TODEVICE);
2859                         pci_unmap_len_set(&tx->info[idx], len, 0);
2860                         tx->info[idx].skb = NULL;
2861                 }
2862                 idx = (idx + 1) & tx->mask;
2863         } while (idx != last_idx);
2864         if (skb_is_gso(skb)) {
2865                 printk(KERN_ERR
2866                        "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2867                        mgp->dev->name);
2868                 goto drop;
2869         }
2870
2871         if (skb_linearize(skb))
2872                 goto drop;
2873
2874         tx->linearized++;
2875         goto again;
2876
2877 drop:
2878         dev_kfree_skb_any(skb);
2879         ss->stats.tx_dropped += 1;
2880         return 0;
2881
2882 }
2883
2884 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2885 {
2886         struct sk_buff *segs, *curr;
2887         struct myri10ge_priv *mgp = netdev_priv(dev);
2888         int status;
2889
2890         segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
2891         if (IS_ERR(segs))
2892                 goto drop;
2893
2894         while (segs) {
2895                 curr = segs;
2896                 segs = segs->next;
2897                 curr->next = NULL;
2898                 status = myri10ge_xmit(curr, dev);
2899                 if (status != 0) {
2900                         dev_kfree_skb_any(curr);
2901                         if (segs != NULL) {
2902                                 curr = segs;
2903                                 segs = segs->next;
2904                                 curr->next = NULL;
2905                                 dev_kfree_skb_any(segs);
2906                         }
2907                         goto drop;
2908                 }
2909         }
2910         dev_kfree_skb_any(skb);
2911         return 0;
2912
2913 drop:
2914         dev_kfree_skb_any(skb);
2915         mgp->stats.tx_dropped += 1;
2916         return 0;
2917 }
2918
2919 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2920 {
2921         struct myri10ge_priv *mgp = netdev_priv(dev);
2922         struct myri10ge_slice_netstats *slice_stats;
2923         struct net_device_stats *stats = &mgp->stats;
2924         int i;
2925
2926         memset(stats, 0, sizeof(*stats));
2927         for (i = 0; i < mgp->num_slices; i++) {
2928                 slice_stats = &mgp->ss[i].stats;
2929                 stats->rx_packets += slice_stats->rx_packets;
2930                 stats->tx_packets += slice_stats->tx_packets;
2931                 stats->rx_bytes += slice_stats->rx_bytes;
2932                 stats->tx_bytes += slice_stats->tx_bytes;
2933                 stats->rx_dropped += slice_stats->rx_dropped;
2934                 stats->tx_dropped += slice_stats->tx_dropped;
2935         }
2936         return stats;
2937 }
2938
2939 static void myri10ge_set_multicast_list(struct net_device *dev)
2940 {
2941         struct myri10ge_priv *mgp = netdev_priv(dev);
2942         struct myri10ge_cmd cmd;
2943         struct dev_mc_list *mc_list;
2944         __be32 data[2] = { 0, 0 };
2945         int err;
2946         DECLARE_MAC_BUF(mac);
2947
2948         /* can be called from atomic contexts,
2949          * pass 1 to force atomicity in myri10ge_send_cmd() */
2950         myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2951
2952         /* This firmware is known to not support multicast */
2953         if (!mgp->fw_multicast_support)
2954                 return;
2955
2956         /* Disable multicast filtering */
2957
2958         err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2959         if (err != 0) {
2960                 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2961                        " error status: %d\n", dev->name, err);
2962                 goto abort;
2963         }
2964
2965         if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
2966                 /* request to disable multicast filtering, so quit here */
2967                 return;
2968         }
2969
2970         /* Flush the filters */
2971
2972         err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2973                                 &cmd, 1);
2974         if (err != 0) {
2975                 printk(KERN_ERR
2976                        "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2977                        ", error status: %d\n", dev->name, err);
2978                 goto abort;
2979         }
2980
2981         /* Walk the multicast list, and add each address */
2982         for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
2983                 memcpy(data, &mc_list->dmi_addr, 6);
2984                 cmd.data0 = ntohl(data[0]);
2985                 cmd.data1 = ntohl(data[1]);
2986                 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2987                                         &cmd, 1);
2988
2989                 if (err != 0) {
2990                         printk(KERN_ERR "myri10ge: %s: Failed "
2991                                "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2992                                "%d\t", dev->name, err);
2993                         printk(KERN_ERR "MAC %s\n",
2994                                print_mac(mac, mc_list->dmi_addr));
2995                         goto abort;
2996                 }
2997         }
2998         /* Enable multicast filtering */
2999         err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3000         if (err != 0) {
3001                 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
3002                        "error status: %d\n", dev->name, err);
3003                 goto abort;
3004         }
3005
3006         return;
3007
3008 abort:
3009         return;
3010 }
3011
3012 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
3013 {
3014         struct sockaddr *sa = addr;
3015         struct myri10ge_priv *mgp = netdev_priv(dev);
3016         int status;
3017
3018         if (!is_valid_ether_addr(sa->sa_data))
3019                 return -EADDRNOTAVAIL;
3020
3021         status = myri10ge_update_mac_address(mgp, sa->sa_data);
3022         if (status != 0) {
3023                 printk(KERN_ERR
3024                        "myri10ge: %s: changing mac address failed with %d\n",
3025                        dev->name, status);
3026                 return status;
3027         }
3028
3029         /* change the dev structure */
3030         memcpy(dev->dev_addr, sa->sa_data, 6);
3031         return 0;
3032 }
3033
3034 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
3035 {
3036         struct myri10ge_priv *mgp = netdev_priv(dev);
3037         int error = 0;
3038
3039         if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
3040                 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
3041                        dev->name, new_mtu);
3042                 return -EINVAL;
3043         }
3044         printk(KERN_INFO "%s: changing mtu from %d to %d\n",
3045                dev->name, dev->mtu, new_mtu);
3046         if (mgp->running) {
3047                 /* if we change the mtu on an active device, we must
3048                  * reset the device so the firmware sees the change */
3049                 myri10ge_close(dev);
3050                 dev->mtu = new_mtu;
3051                 myri10ge_open(dev);
3052         } else
3053                 dev->mtu = new_mtu;
3054
3055         return error;
3056 }
3057
3058 /*
3059  * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
3060  * Only do it if the bridge is a root port since we don't want to disturb
3061  * any other device, except if forced with myri10ge_ecrc_enable > 1.
3062  */
3063
3064 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3065 {
3066         struct pci_dev *bridge = mgp->pdev->bus->self;
3067         struct device *dev = &mgp->pdev->dev;
3068         unsigned cap;
3069         unsigned err_cap;
3070         u16 val;
3071         u8 ext_type;
3072         int ret;
3073
3074         if (!myri10ge_ecrc_enable || !bridge)
3075                 return;
3076
3077         /* check that the bridge is a root port */
3078         cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
3079         pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
3080         ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3081         if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
3082                 if (myri10ge_ecrc_enable > 1) {
3083                         struct pci_dev *prev_bridge, *old_bridge = bridge;
3084
3085                         /* Walk the hierarchy up to the root port
3086                          * where ECRC has to be enabled */
3087                         do {
3088                                 prev_bridge = bridge;
3089                                 bridge = bridge->bus->self;
3090                                 if (!bridge || prev_bridge == bridge) {
3091                                         dev_err(dev,
3092                                                 "Failed to find root port"
3093                                                 " to force ECRC\n");
3094                                         return;
3095                                 }
3096                                 cap =
3097                                     pci_find_capability(bridge, PCI_CAP_ID_EXP);
3098                                 pci_read_config_word(bridge,
3099                                                      cap + PCI_CAP_FLAGS, &val);
3100                                 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
3101                         } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
3102
3103                         dev_info(dev,
3104                                  "Forcing ECRC on non-root port %s"
3105                                  " (enabling on root port %s)\n",
3106                                  pci_name(old_bridge), pci_name(bridge));
3107                 } else {
3108                         dev_err(dev,
3109                                 "Not enabling ECRC on non-root port %s\n",
3110                                 pci_name(bridge));
3111                         return;
3112                 }
3113         }
3114
3115         cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
3116         if (!cap)
3117                 return;
3118
3119         ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
3120         if (ret) {
3121                 dev_err(dev, "failed reading ext-conf-space of %s\n",
3122                         pci_name(bridge));
3123                 dev_err(dev, "\t pci=nommconf in use? "
3124                         "or buggy/incomplete/absent ACPI MCFG attr?\n");
3125                 return;
3126         }
3127         if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
3128                 return;
3129
3130         err_cap |= PCI_ERR_CAP_ECRC_GENE;
3131         pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
3132         dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
3133 }
3134
3135 /*
3136  * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
3137  * when the PCI-E Completion packets are aligned on an 8-byte
3138  * boundary.  Some PCI-E chip sets always align Completion packets; on
3139  * the ones that do not, the alignment can be enforced by enabling
3140  * ECRC generation (if supported).
3141  *
3142  * When PCI-E Completion packets are not aligned, it is actually more
3143  * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
3144  *
3145  * If the driver can neither enable ECRC nor verify that it has
3146  * already been enabled, then it must use a firmware image which works
3147  * around unaligned completion packets (myri10ge_rss_ethp_z8e.dat), and it
3148  * should also ensure that it never gives the device a Read-DMA which is
3149  * larger than 2KB by setting the tx_boundary to 2KB.  If ECRC is
3150  * enabled, then the driver should use the aligned (myri10ge_rss_eth_z8e.dat)
3151  * firmware image, and set tx_boundary to 4KB.
3152  */
3153
3154 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
3155 {
3156         struct pci_dev *pdev = mgp->pdev;
3157         struct device *dev = &pdev->dev;
3158         int status;
3159
3160         mgp->tx_boundary = 4096;
3161         /*
3162          * Verify the max read request size was set to 4KB
3163          * before trying the test with 4KB.
3164          */
3165         status = pcie_get_readrq(pdev);
3166         if (status < 0) {
3167                 dev_err(dev, "Couldn't read max read req size: %d\n", status);
3168                 goto abort;
3169         }
3170         if (status != 4096) {
3171                 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
3172                 mgp->tx_boundary = 2048;
3173         }
3174         /*
3175          * load the optimized firmware (which assumes aligned PCIe
3176          * completions) in order to see if it works on this host.
3177          */
3178         mgp->fw_name = myri10ge_fw_aligned;
3179         status = myri10ge_load_firmware(mgp, 1);
3180         if (status != 0) {
3181                 goto abort;
3182         }
3183
3184         /*
3185          * Enable ECRC if possible
3186          */
3187         myri10ge_enable_ecrc(mgp);
3188
3189         /*
3190          * Run a DMA test which watches for unaligned completions and
3191          * aborts on the first one seen.
3192          */
3193
3194         status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3195         if (status == 0)
3196                 return;         /* keep the aligned firmware */
3197
3198         if (status != -E2BIG)
3199                 dev_warn(dev, "DMA test failed: %d\n", status);
3200         if (status == -ENOSYS)
3201                 dev_warn(dev, "Falling back to ethp! "
3202                          "Please install up to date fw\n");
3203 abort:
3204         /* fall back to using the unaligned firmware */
3205         mgp->tx_boundary = 2048;
3206         mgp->fw_name = myri10ge_fw_unaligned;
3207
3208 }
3209
3210 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3211 {
3212         if (myri10ge_force_firmware == 0) {
3213                 int link_width, exp_cap;
3214                 u16 lnk;
3215
3216                 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
3217                 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
3218                 link_width = (lnk >> 4) & 0x3f;
3219
3220                 /* Check to see if Link is less than 8 or if the
3221                  * upstream bridge is known to provide aligned
3222                  * completions */
3223                 if (link_width < 8) {
3224                         dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3225                                  link_width);
3226                         mgp->tx_boundary = 4096;
3227                         mgp->fw_name = myri10ge_fw_aligned;
3228                 } else {
3229                         myri10ge_firmware_probe(mgp);
3230                 }
3231         } else {
3232                 if (myri10ge_force_firmware == 1) {
3233                         dev_info(&mgp->pdev->dev,
3234                                  "Assuming aligned completions (forced)\n");
3235                         mgp->tx_boundary = 4096;
3236                         mgp->fw_name = myri10ge_fw_aligned;
3237                 } else {
3238                         dev_info(&mgp->pdev->dev,
3239                                  "Assuming unaligned completions (forced)\n");
3240                         mgp->tx_boundary = 2048;
3241                         mgp->fw_name = myri10ge_fw_unaligned;
3242                 }
3243         }
3244         if (myri10ge_fw_name != NULL) {
3245                 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3246                          myri10ge_fw_name);
3247                 mgp->fw_name = myri10ge_fw_name;
3248         }
3249 }
3250
3251 #ifdef CONFIG_PM
3252 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
3253 {
3254         struct myri10ge_priv *mgp;
3255         struct net_device *netdev;
3256
3257         mgp = pci_get_drvdata(pdev);
3258         if (mgp == NULL)
3259                 return -EINVAL;
3260         netdev = mgp->dev;
3261
3262         netif_device_detach(netdev);
3263         if (netif_running(netdev)) {
3264                 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
3265                 rtnl_lock();
3266                 myri10ge_close(netdev);
3267                 rtnl_unlock();
3268         }
3269         myri10ge_dummy_rdma(mgp, 0);
3270         pci_save_state(pdev);
3271         pci_disable_device(pdev);
3272
3273         return pci_set_power_state(pdev, pci_choose_state(pdev, state));
3274 }
3275
3276 static int myri10ge_resume(struct pci_dev *pdev)
3277 {
3278         struct myri10ge_priv *mgp;
3279         struct net_device *netdev;
3280         int status;
3281         u16 vendor;
3282
3283         mgp = pci_get_drvdata(pdev);
3284         if (mgp == NULL)
3285                 return -EINVAL;
3286         netdev = mgp->dev;
3287         pci_set_power_state(pdev, 0);   /* zeros conf space as a side effect */
3288         msleep(5);              /* give card time to respond */
3289         pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3290         if (vendor == 0xffff) {
3291                 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
3292                        mgp->dev->name);
3293                 return -EIO;
3294         }
3295
3296         status = pci_restore_state(pdev);
3297         if (status)
3298                 return status;
3299
3300         status = pci_enable_device(pdev);
3301         if (status) {
3302                 dev_err(&pdev->dev, "failed to enable device\n");
3303                 return status;
3304         }
3305
3306         pci_set_master(pdev);
3307
3308         myri10ge_reset(mgp);
3309         myri10ge_dummy_rdma(mgp, 1);
3310
3311         /* Save configuration space to be restored if the
3312          * nic resets due to a parity error */
3313         pci_save_state(pdev);
3314
3315         if (netif_running(netdev)) {
3316                 rtnl_lock();
3317                 status = myri10ge_open(netdev);
3318                 rtnl_unlock();
3319                 if (status != 0)
3320                         goto abort_with_enabled;
3321
3322         }
3323         netif_device_attach(netdev);
3324
3325         return 0;
3326
3327 abort_with_enabled:
3328         pci_disable_device(pdev);
3329         return -EIO;
3330
3331 }
3332 #endif                          /* CONFIG_PM */
3333
3334 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3335 {
3336         struct pci_dev *pdev = mgp->pdev;
3337         int vs = mgp->vendor_specific_offset;
3338         u32 reboot;
3339
3340         /*enter read32 mode */
3341         pci_write_config_byte(pdev, vs + 0x10, 0x3);
3342
3343         /*read REBOOT_STATUS (0xfffffff0) */
3344         pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
3345         pci_read_config_dword(pdev, vs + 0x14, &reboot);
3346         return reboot;
3347 }
3348
3349 /*
3350  * This watchdog is used to check whether the board has suffered
3351  * from a parity error and needs to be recovered.
3352  */
3353 static void myri10ge_watchdog(struct work_struct *work)
3354 {
3355         struct myri10ge_priv *mgp =
3356             container_of(work, struct myri10ge_priv, watchdog_work);
3357         struct myri10ge_tx_buf *tx;
3358         u32 reboot;
3359         int status;
3360         int i;
3361         u16 cmd, vendor;
3362
3363         mgp->watchdog_resets++;
3364         pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3365         if ((cmd & PCI_COMMAND_MASTER) == 0) {
3366                 /* Bus master DMA disabled?  Check to see
3367                  * if the card rebooted due to a parity error
3368                  * For now, just report it */
3369                 reboot = myri10ge_read_reboot(mgp);
3370                 printk(KERN_ERR
3371                        "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
3372                        mgp->dev->name, reboot,
3373                        myri10ge_reset_recover ? " " : " not");
3374                 if (myri10ge_reset_recover == 0)
3375                         return;
3376
3377                 myri10ge_reset_recover--;
3378
3379                 /*
3380                  * A rebooted nic will come back with config space as
3381                  * it was after power was applied to PCIe bus.
3382                  * Attempt to restore config space which was saved
3383                  * when the driver was loaded, or the last time the
3384                  * nic was resumed from power saving mode.
3385                  */
3386                 pci_restore_state(mgp->pdev);
3387
3388                 /* save state again for accounting reasons */
3389                 pci_save_state(mgp->pdev);
3390
3391         } else {
3392                 /* if we get back -1's from our slot, perhaps somebody
3393                  * powered off our card.  Don't try to reset it in
3394                  * this case */
3395                 if (cmd == 0xffff) {
3396                         pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3397                         if (vendor == 0xffff) {
3398                                 printk(KERN_ERR
3399                                        "myri10ge: %s: device disappeared!\n",
3400                                        mgp->dev->name);
3401                                 return;
3402                         }
3403                 }
3404                 /* Perhaps it is a software error.  Try to reset */
3405
3406                 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3407                        mgp->dev->name);
3408                 for (i = 0; i < mgp->num_slices; i++) {
3409                         tx = &mgp->ss[i].tx;
3410                         printk(KERN_INFO
3411                                "myri10ge: %s: (%d): %d %d %d %d %d\n",
3412                                mgp->dev->name, i, tx->req, tx->done,
3413                                tx->pkt_start, tx->pkt_done,
3414                                (int)ntohl(mgp->ss[i].fw_stats->
3415                                           send_done_count));
3416                         msleep(2000);
3417                         printk(KERN_INFO
3418                                "myri10ge: %s: (%d): %d %d %d %d %d\n",
3419                                mgp->dev->name, i, tx->req, tx->done,
3420                                tx->pkt_start, tx->pkt_done,
3421                                (int)ntohl(mgp->ss[i].fw_stats->
3422                                           send_done_count));
3423                 }
3424         }
3425         rtnl_lock();
3426         myri10ge_close(mgp->dev);
3427         status = myri10ge_load_firmware(mgp, 1);
3428         if (status != 0)
3429                 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3430                        mgp->dev->name);
3431         else
3432                 myri10ge_open(mgp->dev);
3433         rtnl_unlock();
3434 }
3435
3436 /*
3437  * We use our own timer routine rather than relying upon
3438  * netdev->tx_timeout because we have a very large hardware transmit
3439  * queue.  Due to the large queue, the netdev->tx_timeout function
3440  * cannot detect a NIC with a parity error in a timely fashion if the
3441  * NIC is lightly loaded.
3442  */
3443 static void myri10ge_watchdog_timer(unsigned long arg)
3444 {
3445         struct myri10ge_priv *mgp;
3446         struct myri10ge_slice_state *ss;
3447         int i, reset_needed;
3448         u32 rx_pause_cnt;
3449
3450         mgp = (struct myri10ge_priv *)arg;
3451
3452         rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3453         for (i = 0, reset_needed = 0;
3454              i < mgp->num_slices && reset_needed == 0; ++i) {
3455
3456                 ss = &mgp->ss[i];
3457                 if (ss->rx_small.watchdog_needed) {
3458                         myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3459                                                 mgp->small_bytes + MXGEFW_PAD,
3460                                                 1);
3461                         if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3462                             myri10ge_fill_thresh)
3463                                 ss->rx_small.watchdog_needed = 0;
3464                 }
3465                 if (ss->rx_big.watchdog_needed) {
3466                         myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3467                                                 mgp->big_bytes, 1);
3468                         if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3469                             myri10ge_fill_thresh)
3470                                 ss->rx_big.watchdog_needed = 0;
3471                 }
3472
3473                 if (ss->tx.req != ss->tx.done &&
3474                     ss->tx.done == ss->watchdog_tx_done &&
3475                     ss->watchdog_tx_req != ss->watchdog_tx_done) {
3476                         /* nic seems like it might be stuck.. */
3477                         if (rx_pause_cnt != mgp->watchdog_pause) {
3478                                 if (net_ratelimit())
3479                                         printk(KERN_WARNING "myri10ge %s:"
3480                                                "TX paused, check link partner\n",
3481                                                mgp->dev->name);
3482                         } else {
3483                                 reset_needed = 1;
3484                         }
3485                 }
3486                 ss->watchdog_tx_done = ss->tx.done;
3487                 ss->watchdog_tx_req = ss->tx.req;
3488         }
3489         mgp->watchdog_pause = rx_pause_cnt;
3490
3491         if (reset_needed) {
3492                 schedule_work(&mgp->watchdog_work);
3493         } else {
3494                 /* rearm timer */
3495                 mod_timer(&mgp->watchdog_timer,
3496                           jiffies + myri10ge_watchdog_timeout * HZ);
3497         }
3498 }
3499
3500 static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3501 {
3502         struct myri10ge_slice_state *ss;
3503         struct pci_dev *pdev = mgp->pdev;
3504         size_t bytes;
3505         int i;
3506
3507         if (mgp->ss == NULL)
3508                 return;
3509
3510         for (i = 0; i < mgp->num_slices; i++) {
3511                 ss = &mgp->ss[i];
3512                 if (ss->rx_done.entry != NULL) {
3513                         bytes = mgp->max_intr_slots *
3514                             sizeof(*ss->rx_done.entry);
3515                         dma_free_coherent(&pdev->dev, bytes,
3516                                           ss->rx_done.entry, ss->rx_done.bus);
3517                         ss->rx_done.entry = NULL;
3518                 }
3519                 if (ss->fw_stats != NULL) {
3520                         bytes = sizeof(*ss->fw_stats);
3521                         dma_free_coherent(&pdev->dev, bytes,
3522                                           ss->fw_stats, ss->fw_stats_bus);
3523                         ss->fw_stats = NULL;
3524                 }
3525         }
3526         kfree(mgp->ss);
3527         mgp->ss = NULL;
3528 }
3529
3530 static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3531 {
3532         struct myri10ge_slice_state *ss;
3533         struct pci_dev *pdev = mgp->pdev;
3534         size_t bytes;
3535         int i;
3536
3537         bytes = sizeof(*mgp->ss) * mgp->num_slices;
3538         mgp->ss = kzalloc(bytes, GFP_KERNEL);
3539         if (mgp->ss == NULL) {
3540                 return -ENOMEM;
3541         }
3542
3543         for (i = 0; i < mgp->num_slices; i++) {
3544                 ss = &mgp->ss[i];
3545                 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3546                 ss->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3547                                                        &ss->rx_done.bus,
3548                                                        GFP_KERNEL);
3549                 if (ss->rx_done.entry == NULL)
3550                         goto abort;
3551                 memset(ss->rx_done.entry, 0, bytes);
3552                 bytes = sizeof(*ss->fw_stats);
3553                 ss->fw_stats = dma_alloc_coherent(&pdev->dev, bytes,
3554                                                   &ss->fw_stats_bus,
3555                                                   GFP_KERNEL);
3556                 if (ss->fw_stats == NULL)
3557                         goto abort;
3558                 ss->mgp = mgp;
3559                 ss->dev = mgp->dev;
3560                 netif_napi_add(ss->dev, &ss->napi, myri10ge_poll,
3561                                myri10ge_napi_weight);
3562         }
3563         return 0;
3564 abort:
3565         myri10ge_free_slices(mgp);
3566         return -ENOMEM;
3567 }
3568
3569 /*
3570  * This function determines the number of slices supported.
3571  * The number slices is the minumum of the number of CPUS,
3572  * the number of MSI-X irqs supported, the number of slices
3573  * supported by the firmware
3574  */
3575 static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3576 {
3577         struct myri10ge_cmd cmd;
3578         struct pci_dev *pdev = mgp->pdev;
3579         char *old_fw;
3580         int i, status, ncpus, msix_cap;
3581
3582         mgp->num_slices = 1;
3583         msix_cap = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
3584         ncpus = num_online_cpus();
3585
3586         if (myri10ge_max_slices == 1 || msix_cap == 0 ||
3587             (myri10ge_max_slices == -1 && ncpus < 2))
3588                 return;
3589
3590         /* try to load the slice aware rss firmware */
3591         old_fw = mgp->fw_name;
3592         if (old_fw == myri10ge_fw_aligned)
3593                 mgp->fw_name = myri10ge_fw_rss_aligned;
3594         else
3595                 mgp->fw_name = myri10ge_fw_rss_unaligned;
3596         status = myri10ge_load_firmware(mgp, 0);
3597         if (status != 0) {
3598                 dev_info(&pdev->dev, "Rss firmware not found\n");
3599                 return;
3600         }
3601
3602         /* hit the board with a reset to ensure it is alive */
3603         memset(&cmd, 0, sizeof(cmd));
3604         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3605         if (status != 0) {
3606                 dev_err(&mgp->pdev->dev, "failed reset\n");
3607                 goto abort_with_fw;
3608                 return;
3609         }
3610
3611         mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3612
3613         /* tell it the size of the interrupt queues */
3614         cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3615         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3616         if (status != 0) {
3617                 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3618                 goto abort_with_fw;
3619         }
3620
3621         /* ask the maximum number of slices it supports */
3622         status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3623         if (status != 0)
3624                 goto abort_with_fw;
3625         else
3626                 mgp->num_slices = cmd.data0;
3627
3628         /* Only allow multiple slices if MSI-X is usable */
3629         if (!myri10ge_msi) {
3630                 goto abort_with_fw;
3631         }
3632
3633         /* if the admin did not specify a limit to how many
3634          * slices we should use, cap it automatically to the
3635          * number of CPUs currently online */
3636         if (myri10ge_max_slices == -1)
3637                 myri10ge_max_slices = ncpus;
3638
3639         if (mgp->num_slices > myri10ge_max_slices)
3640                 mgp->num_slices = myri10ge_max_slices;
3641
3642         /* Now try to allocate as many MSI-X vectors as we have
3643          * slices. We give up on MSI-X if we can only get a single
3644          * vector. */
3645
3646         mgp->msix_vectors = kzalloc(mgp->num_slices *
3647                                     sizeof(*mgp->msix_vectors), GFP_KERNEL);
3648         if (mgp->msix_vectors == NULL)
3649                 goto disable_msix;
3650         for (i = 0; i < mgp->num_slices; i++) {
3651                 mgp->msix_vectors[i].entry = i;
3652         }
3653
3654         while (mgp->num_slices > 1) {
3655                 /* make sure it is a power of two */
3656                 while (!is_power_of_2(mgp->num_slices))
3657                         mgp->num_slices--;
3658                 if (mgp->num_slices == 1)
3659                         goto disable_msix;
3660                 status = pci_enable_msix(pdev, mgp->msix_vectors,
3661                                          mgp->num_slices);
3662                 if (status == 0) {
3663                         pci_disable_msix(pdev);
3664                         return;
3665                 }
3666                 if (status > 0)
3667                         mgp->num_slices = status;
3668                 else
3669                         goto disable_msix;
3670         }
3671
3672 disable_msix:
3673         if (mgp->msix_vectors != NULL) {
3674                 kfree(mgp->msix_vectors);
3675                 mgp->msix_vectors = NULL;
3676         }
3677
3678 abort_with_fw:
3679         mgp->num_slices = 1;
3680         mgp->fw_name = old_fw;
3681         myri10ge_load_firmware(mgp, 0);
3682 }
3683
3684 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3685 {
3686         struct net_device *netdev;
3687         struct myri10ge_priv *mgp;
3688         struct device *dev = &pdev->dev;
3689         int i;
3690         int status = -ENXIO;
3691         int dac_enabled;
3692
3693         netdev = alloc_etherdev(sizeof(*mgp));
3694         if (netdev == NULL) {
3695                 dev_err(dev, "Could not allocate ethernet device\n");
3696                 return -ENOMEM;
3697         }
3698
3699         SET_NETDEV_DEV(netdev, &pdev->dev);
3700
3701         mgp = netdev_priv(netdev);
3702         mgp->dev = netdev;
3703         mgp->pdev = pdev;
3704         mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3705         mgp->pause = myri10ge_flow_control;
3706         mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3707         mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3708         init_waitqueue_head(&mgp->down_wq);
3709
3710         if (pci_enable_device(pdev)) {
3711                 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3712                 status = -ENODEV;
3713                 goto abort_with_netdev;
3714         }
3715
3716         /* Find the vendor-specific cap so we can check
3717          * the reboot register later on */
3718         mgp->vendor_specific_offset
3719             = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3720
3721         /* Set our max read request to 4KB */
3722         status = pcie_set_readrq(pdev, 4096);
3723         if (status != 0) {
3724                 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3725                         status);
3726                 goto abort_with_netdev;
3727         }
3728
3729         pci_set_master(pdev);
3730         dac_enabled = 1;
3731         status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3732         if (status != 0) {
3733                 dac_enabled = 0;
3734                 dev_err(&pdev->dev,
3735                         "64-bit pci address mask was refused, "
3736                         "trying 32-bit\n");
3737                 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3738         }
3739         if (status != 0) {
3740                 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3741                 goto abort_with_netdev;
3742         }
3743         mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3744                                       &mgp->cmd_bus, GFP_KERNEL);
3745         if (mgp->cmd == NULL)
3746                 goto abort_with_netdev;
3747
3748         mgp->board_span = pci_resource_len(pdev, 0);
3749         mgp->iomem_base = pci_resource_start(pdev, 0);
3750         mgp->mtrr = -1;
3751         mgp->wc_enabled = 0;
3752 #ifdef CONFIG_MTRR
3753         mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3754                              MTRR_TYPE_WRCOMB, 1);
3755         if (mgp->mtrr >= 0)
3756                 mgp->wc_enabled = 1;
3757 #endif
3758         /* Hack.  need to get rid of these magic numbers */
3759         mgp->sram_size =
3760             2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3761         if (mgp->sram_size > mgp->board_span) {
3762                 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3763                         mgp->board_span);
3764                 goto abort_with_wc;
3765         }
3766         mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
3767         if (mgp->sram == NULL) {
3768                 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3769                         mgp->board_span, mgp->iomem_base);
3770                 status = -ENXIO;
3771                 goto abort_with_wc;
3772         }
3773         memcpy_fromio(mgp->eeprom_strings,
3774                       mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3775                       MYRI10GE_EEPROM_STRINGS_SIZE);
3776         memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3777         status = myri10ge_read_mac_addr(mgp);
3778         if (status)
3779                 goto abort_with_ioremap;
3780
3781         for (i = 0; i < ETH_ALEN; i++)
3782                 netdev->dev_addr[i] = mgp->mac_addr[i];
3783
3784         myri10ge_select_firmware(mgp);
3785
3786         status = myri10ge_load_firmware(mgp, 1);
3787         if (status != 0) {
3788                 dev_err(&pdev->dev, "failed to load firmware\n");
3789                 goto abort_with_ioremap;
3790         }
3791         myri10ge_probe_slices(mgp);
3792         status = myri10ge_alloc_slices(mgp);
3793         if (status != 0) {
3794                 dev_err(&pdev->dev, "failed to alloc slice state\n");
3795                 goto abort_with_firmware;
3796         }
3797
3798         status = myri10ge_reset(mgp);
3799         if (status != 0) {
3800                 dev_err(&pdev->dev, "failed reset\n");
3801                 goto abort_with_slices;
3802         }
3803 #ifdef CONFIG_DCA
3804         myri10ge_setup_dca(mgp);
3805 #endif
3806         pci_set_drvdata(pdev, mgp);
3807         if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3808                 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3809         if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3810                 myri10ge_initial_mtu = 68;
3811         netdev->mtu = myri10ge_initial_mtu;
3812         netdev->open = myri10ge_open;
3813         netdev->stop = myri10ge_close;
3814         netdev->hard_start_xmit = myri10ge_xmit;
3815         netdev->get_stats = myri10ge_get_stats;
3816         netdev->base_addr = mgp->iomem_base;
3817         netdev->change_mtu = myri10ge_change_mtu;
3818         netdev->set_multicast_list = myri10ge_set_multicast_list;
3819         netdev->set_mac_address = myri10ge_set_mac_address;
3820         netdev->features = mgp->features;
3821         if (dac_enabled)
3822                 netdev->features |= NETIF_F_HIGHDMA;
3823
3824         /* make sure we can get an irq, and that MSI can be
3825          * setup (if available).  Also ensure netdev->irq
3826          * is set to correct value if MSI is enabled */
3827         status = myri10ge_request_irq(mgp);
3828         if (status != 0)
3829                 goto abort_with_firmware;
3830         netdev->irq = pdev->irq;
3831         myri10ge_free_irq(mgp);
3832
3833         /* Save configuration space to be restored if the
3834          * nic resets due to a parity error */
3835         pci_save_state(pdev);
3836
3837         /* Setup the watchdog timer */
3838         setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3839                     (unsigned long)mgp);
3840
3841         SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
3842         INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3843         status = register_netdev(netdev);
3844         if (status != 0) {
3845                 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3846                 goto abort_with_state;
3847         }
3848         if (mgp->msix_enabled)
3849                 dev_info(dev, "%d MSI-X IRQs, tx bndry %d, fw %s, WC %s\n",
3850                          mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3851                          (mgp->wc_enabled ? "Enabled" : "Disabled"));
3852         else
3853                 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3854                          mgp->msi_enabled ? "MSI" : "xPIC",
3855                          netdev->irq, mgp->tx_boundary, mgp->fw_name,
3856                          (mgp->wc_enabled ? "Enabled" : "Disabled"));
3857
3858         return 0;
3859
3860 abort_with_state:
3861         pci_restore_state(pdev);
3862
3863 abort_with_slices:
3864         myri10ge_free_slices(mgp);
3865
3866 abort_with_firmware:
3867         myri10ge_dummy_rdma(mgp, 0);
3868
3869 abort_with_ioremap:
3870         iounmap(mgp->sram);
3871
3872 abort_with_wc:
3873 #ifdef CONFIG_MTRR
3874         if (mgp->mtrr >= 0)
3875                 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3876 #endif
3877         dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3878                           mgp->cmd, mgp->cmd_bus);
3879
3880 abort_with_netdev:
3881
3882         free_netdev(netdev);
3883         return status;
3884 }
3885
3886 /*
3887  * myri10ge_remove
3888  *
3889  * Does what is necessary to shutdown one Myrinet device. Called
3890  *   once for each Myrinet card by the kernel when a module is
3891  *   unloaded.
3892  */
3893 static void myri10ge_remove(struct pci_dev *pdev)
3894 {
3895         struct myri10ge_priv *mgp;
3896         struct net_device *netdev;
3897
3898         mgp = pci_get_drvdata(pdev);
3899         if (mgp == NULL)
3900                 return;
3901
3902         flush_scheduled_work();
3903         netdev = mgp->dev;
3904         unregister_netdev(netdev);
3905
3906 #ifdef CONFIG_DCA
3907         myri10ge_teardown_dca(mgp);
3908 #endif
3909         myri10ge_dummy_rdma(mgp, 0);
3910
3911         /* avoid a memory leak */
3912         pci_restore_state(pdev);
3913
3914         iounmap(mgp->sram);
3915
3916 #ifdef CONFIG_MTRR
3917         if (mgp->mtrr >= 0)
3918                 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3919 #endif
3920         myri10ge_free_slices(mgp);
3921         if (mgp->msix_vectors != NULL)
3922                 kfree(mgp->msix_vectors);
3923         dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3924                           mgp->cmd, mgp->cmd_bus);
3925
3926         free_netdev(netdev);
3927         pci_set_drvdata(pdev, NULL);
3928 }
3929
3930 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E      0x0008
3931 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9    0x0009
3932
3933 static struct pci_device_id myri10ge_pci_tbl[] = {
3934         {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
3935         {PCI_DEVICE
3936          (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
3937         {0},
3938 };
3939
3940 static struct pci_driver myri10ge_driver = {
3941         .name = "myri10ge",
3942         .probe = myri10ge_probe,
3943         .remove = myri10ge_remove,
3944         .id_table = myri10ge_pci_tbl,
3945 #ifdef CONFIG_PM
3946         .suspend = myri10ge_suspend,
3947         .resume = myri10ge_resume,
3948 #endif
3949 };
3950
3951 #ifdef CONFIG_DCA
3952 static int
3953 myri10ge_notify_dca(struct notifier_block *nb, unsigned long event, void *p)
3954 {
3955         int err = driver_for_each_device(&myri10ge_driver.driver,
3956                                          NULL, &event,
3957                                          myri10ge_notify_dca_device);
3958
3959         if (err)
3960                 return NOTIFY_BAD;
3961         return NOTIFY_DONE;
3962 }
3963
3964 static struct notifier_block myri10ge_dca_notifier = {
3965         .notifier_call = myri10ge_notify_dca,
3966         .next = NULL,
3967         .priority = 0,
3968 };
3969 #endif                          /* CONFIG_DCA */
3970
3971 static __init int myri10ge_init_module(void)
3972 {
3973         printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3974                MYRI10GE_VERSION_STR);
3975
3976         if (myri10ge_rss_hash > MXGEFW_RSS_HASH_TYPE_SRC_PORT ||
3977             myri10ge_rss_hash < MXGEFW_RSS_HASH_TYPE_IPV4) {
3978                 printk(KERN_ERR
3979                        "%s: Illegal rssh hash type %d, defaulting to source port\n",
3980                        myri10ge_driver.name, myri10ge_rss_hash);
3981                 myri10ge_rss_hash = MXGEFW_RSS_HASH_TYPE_SRC_PORT;
3982         }
3983 #ifdef CONFIG_DCA
3984         dca_register_notify(&myri10ge_dca_notifier);
3985 #endif
3986
3987         return pci_register_driver(&myri10ge_driver);
3988 }
3989
3990 module_init(myri10ge_init_module);
3991
3992 static __exit void myri10ge_cleanup_module(void)
3993 {
3994 #ifdef CONFIG_DCA
3995         dca_unregister_notify(&myri10ge_dca_notifier);
3996 #endif
3997         pci_unregister_driver(&myri10ge_driver);
3998 }
3999
4000 module_exit(myri10ge_cleanup_module);