1 #ifndef __MV643XX_ETH_H__
2 #define __MV643XX_ETH_H__
4 #include <linux/module.h>
5 #include <linux/kernel.h>
6 #include <linux/spinlock.h>
7 #include <linux/workqueue.h>
10 #include <linux/mv643xx.h>
12 /* Checksum offload for Tx works for most packets, but
13 * fails if previous packet sent did not use hw csum
15 #define MV643XX_CHECKSUM_OFFLOAD_TX
17 #define MV643XX_TX_FAST_REFILL
21 * Number of RX / TX descriptors on RX / TX rings.
22 * Note that allocating RX descriptors is done by allocating the RX
23 * ring AND a preallocated RX buffers (skb's) for each descriptor.
24 * The TX descriptors only allocates the TX descriptors ring,
25 * with no pre allocated TX buffers (skb's are allocated by higher layers.
28 /* Default TX ring size is 1000 descriptors */
29 #define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
31 /* Default RX ring size is 400 descriptors */
32 #define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
34 #define MV643XX_TX_COAL 100
36 #define MV643XX_RX_COAL 100
39 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
40 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
42 #define MAX_DESCS_PER_SKB 1
45 #define ETH_VLAN_HLEN 4
47 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
48 #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
49 ETH_VLAN_HLEN + ETH_FCS_LEN)
50 #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + ETH_DMA_ALIGN)
52 #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
53 #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
55 #define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
56 #define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
57 #define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
58 #define ETH_INT_CAUSE_EXT 0x00000002
59 #define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
61 #define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
62 #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
63 #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
64 #define ETH_INT_CAUSE_PHY 0x00010000
65 #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY)
67 #define ETH_INT_MASK_ALL 0x00000000
68 #define ETH_INT_MASK_ALL_EXT 0x00000000
70 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
71 #define PHY_WAIT_MICRO_SECONDS 10
73 /* Buffer offset from buffer pointer */
74 #define RX_BUF_OFFSET 0x2
76 /* Gigabit Ethernet Unit Global Registers */
78 /* MIB Counters register definitions */
79 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
80 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
81 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
82 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
83 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
84 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
85 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
86 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
87 #define ETH_MIB_FRAMES_64_OCTETS 0x20
88 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
89 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
90 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
91 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
92 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
93 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
94 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
95 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
96 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
97 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
98 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
99 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
100 #define ETH_MIB_FC_SENT 0x54
101 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
102 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
103 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
104 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
105 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
106 #define ETH_MIB_JABBER_RECEIVED 0x6c
107 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
108 #define ETH_MIB_BAD_CRC_EVENT 0x74
109 #define ETH_MIB_COLLISION 0x78
110 #define ETH_MIB_LATE_COLLISION 0x7c
112 /* Port serial status reg (PSR) */
113 #define ETH_INTERFACE_PCM 0x00000001
114 #define ETH_LINK_IS_UP 0x00000002
115 #define ETH_PORT_AT_FULL_DUPLEX 0x00000004
116 #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
117 #define ETH_GMII_SPEED_1000 0x00000010
118 #define ETH_MII_SPEED_100 0x00000020
119 #define ETH_TX_IN_PROGRESS 0x00000080
120 #define ETH_BYPASS_ACTIVE 0x00000100
121 #define ETH_PORT_AT_PARTITION_STATE 0x00000200
122 #define ETH_PORT_TX_FIFO_EMPTY 0x00000400
125 #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
126 #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
127 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
128 #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
130 /* Interrupt Cause Register Bit Definitions */
132 /* SDMA command status fields macros */
134 /* Tx & Rx descriptors status */
135 #define ETH_ERROR_SUMMARY 0x00000001
137 /* Tx & Rx descriptors command */
138 #define ETH_BUFFER_OWNED_BY_DMA 0x80000000
140 /* Tx descriptors status */
141 #define ETH_LC_ERROR 0
142 #define ETH_UR_ERROR 0x00000002
143 #define ETH_RL_ERROR 0x00000004
144 #define ETH_LLC_SNAP_FORMAT 0x00000200
146 /* Rx descriptors status */
147 #define ETH_OVERRUN_ERROR 0x00000002
148 #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
149 #define ETH_RESOURCE_ERROR 0x00000006
150 #define ETH_VLAN_TAGGED 0x00080000
151 #define ETH_BPDU_FRAME 0x00100000
152 #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
153 #define ETH_OTHER_FRAME_TYPE 0x00400000
154 #define ETH_LAYER_2_IS_ETH_V_2 0x00800000
155 #define ETH_FRAME_TYPE_IP_V_4 0x01000000
156 #define ETH_FRAME_HEADER_OK 0x02000000
157 #define ETH_RX_LAST_DESC 0x04000000
158 #define ETH_RX_FIRST_DESC 0x08000000
159 #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
160 #define ETH_RX_ENABLE_INTERRUPT 0x20000000
161 #define ETH_LAYER_4_CHECKSUM_OK 0x40000000
163 /* Rx descriptors byte count */
164 #define ETH_FRAME_FRAGMENTED 0x00000004
166 /* Tx descriptors command */
167 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
168 #define ETH_FRAME_SET_TO_VLAN 0x00008000
169 #define ETH_UDP_FRAME 0x00010000
170 #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
171 #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
172 #define ETH_ZERO_PADDING 0x00080000
173 #define ETH_TX_LAST_DESC 0x00100000
174 #define ETH_TX_FIRST_DESC 0x00200000
175 #define ETH_GEN_CRC 0x00400000
176 #define ETH_TX_ENABLE_INTERRUPT 0x00800000
177 #define ETH_AUTO_MODE 0x40000000
179 #define ETH_TX_IHL_SHIFT 11
183 typedef enum _eth_func_ret_status {
184 ETH_OK, /* Returned as expected. */
185 ETH_ERROR, /* Fundamental error. */
186 ETH_RETRY, /* Could not process request. Try later.*/
187 ETH_END_OF_JOB, /* Ring has nothing to process. */
188 ETH_QUEUE_FULL, /* Ring resource error. */
189 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
190 } ETH_FUNC_RET_STATUS;
192 typedef enum _eth_target {
200 /* These are for big-endian machines. Little endian needs different
203 #if defined(__BIG_ENDIAN)
205 u16 byte_cnt; /* Descriptor buffer byte count */
206 u16 buf_size; /* Buffer size */
207 u32 cmd_sts; /* Descriptor command status */
208 u32 next_desc_ptr; /* Next descriptor pointer */
209 u32 buf_ptr; /* Descriptor buffer pointer */
213 u16 byte_cnt; /* buffer byte count */
214 u16 l4i_chk; /* CPU provided TCP checksum */
215 u32 cmd_sts; /* Command/status field */
216 u32 next_desc_ptr; /* Pointer to next descriptor */
217 u32 buf_ptr; /* pointer to buffer for this descriptor*/
220 #elif defined(__LITTLE_ENDIAN)
222 u32 cmd_sts; /* Descriptor command status */
223 u16 buf_size; /* Buffer size */
224 u16 byte_cnt; /* Descriptor buffer byte count */
225 u32 buf_ptr; /* Descriptor buffer pointer */
226 u32 next_desc_ptr; /* Next descriptor pointer */
230 u32 cmd_sts; /* Command/status field */
231 u16 l4i_chk; /* CPU provided TCP checksum */
232 u16 byte_cnt; /* buffer byte count */
233 u32 buf_ptr; /* pointer to buffer for this descriptor*/
234 u32 next_desc_ptr; /* Pointer to next descriptor */
237 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
240 /* Unified struct for Rx and Tx operations. The user is not required to */
241 /* be familier with neither Tx nor Rx descriptors. */
243 unsigned short byte_cnt; /* Descriptor buffer byte count */
244 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
245 unsigned int cmd_sts; /* Descriptor command status */
246 dma_addr_t buf_ptr; /* Descriptor buffer pointer */
247 struct sk_buff *return_info; /* User resource return information */
250 /* Ethernet port specific information */
252 struct mv643xx_mib_counters {
253 u64 good_octets_received;
254 u32 bad_octets_received;
255 u32 internal_mac_transmit_err;
256 u32 good_frames_received;
257 u32 bad_frames_received;
258 u32 broadcast_frames_received;
259 u32 multicast_frames_received;
260 u32 frames_64_octets;
261 u32 frames_65_to_127_octets;
262 u32 frames_128_to_255_octets;
263 u32 frames_256_to_511_octets;
264 u32 frames_512_to_1023_octets;
265 u32 frames_1024_to_max_octets;
266 u64 good_octets_sent;
267 u32 good_frames_sent;
268 u32 excessive_collision;
269 u32 multicast_frames_sent;
270 u32 broadcast_frames_sent;
271 u32 unrec_mac_control_received;
273 u32 good_fc_received;
275 u32 undersize_received;
276 u32 fragments_received;
277 u32 oversize_received;
279 u32 mac_receive_error;
285 struct mv643xx_private {
286 int port_num; /* User Ethernet port number */
288 u32 rx_sram_addr; /* Base address of rx sram area */
289 u32 rx_sram_size; /* Size of rx sram area */
290 u32 tx_sram_addr; /* Base address of tx sram area */
291 u32 tx_sram_size; /* Size of tx sram area */
293 int rx_resource_err; /* Rx ring resource error flag */
295 /* Tx/Rx rings managment indexes fields. For driver use */
297 /* Next available and first returning Rx resource */
298 int rx_curr_desc_q, rx_used_desc_q;
300 /* Next available and first returning Tx resource */
301 int tx_curr_desc_q, tx_used_desc_q;
303 #ifdef MV643XX_TX_FAST_REFILL
304 u32 tx_clean_threshold;
307 struct eth_rx_desc *p_rx_desc_area;
308 dma_addr_t rx_desc_dma;
309 int rx_desc_area_size;
310 struct sk_buff **rx_skb;
312 struct eth_tx_desc *p_tx_desc_area;
313 dma_addr_t tx_desc_dma;
314 int tx_desc_area_size;
315 struct sk_buff **tx_skb;
317 struct work_struct tx_timeout_task;
319 struct net_device_stats stats;
320 struct mv643xx_mib_counters mib_counters;
322 /* Size of Tx Ring per queue */
324 /* Number of tx descriptors in use */
326 /* Size of Rx Ring per queue */
328 /* Number of rx descriptors in use */
332 * Used in case RX Ring is empty, which can be caused when
333 * system does not have resources (skb's)
335 struct timer_list timeout;
339 struct mii_if_info mii;
342 /* Port operation control routines */
343 static void eth_port_init(struct mv643xx_private *mp);
344 static void eth_port_reset(unsigned int eth_port_num);
345 static void eth_port_start(struct net_device *dev);
347 /* Port MAC address routines */
348 static void eth_port_uc_addr_set(unsigned int eth_port_num,
349 unsigned char *p_addr);
351 /* PHY and MIB routines */
352 static void ethernet_phy_reset(unsigned int eth_port_num);
354 static void eth_port_write_smi_reg(unsigned int eth_port_num,
355 unsigned int phy_reg, unsigned int value);
357 static void eth_port_read_smi_reg(unsigned int eth_port_num,
358 unsigned int phy_reg, unsigned int *value);
360 static void eth_clear_mib_counters(unsigned int eth_port_num);
362 /* Port data flow control routines */
363 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
364 struct pkt_info *p_pkt_info);
365 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
366 struct pkt_info *p_pkt_info);
368 #endif /* __MV643XX_ETH_H__ */