2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.3";
60 #define MV643XX_ETH_TX_FAST_REFILL
63 * Registers shared between all ports.
65 #define PHY_ADDR 0x0000
66 #define SMI_REG 0x0004
67 #define SMI_BUSY 0x10000000
68 #define SMI_READ_VALID 0x08000000
69 #define SMI_OPCODE_READ 0x04000000
70 #define SMI_OPCODE_WRITE 0x00000000
71 #define ERR_INT_CAUSE 0x0080
72 #define ERR_INT_SMI_DONE 0x00000010
73 #define ERR_INT_MASK 0x0084
74 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77 #define WINDOW_BAR_ENABLE 0x0290
78 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
83 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
84 #define UNICAST_PROMISCUOUS_MODE 0x00000001
85 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
86 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
87 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
88 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
89 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
90 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
91 #define TX_FIFO_EMPTY 0x00000400
92 #define TX_IN_PROGRESS 0x00000080
93 #define PORT_SPEED_MASK 0x00000030
94 #define PORT_SPEED_1000 0x00000010
95 #define PORT_SPEED_100 0x00000020
96 #define PORT_SPEED_10 0x00000000
97 #define FLOW_CONTROL_ENABLED 0x00000008
98 #define FULL_DUPLEX 0x00000004
99 #define LINK_UP 0x00000002
100 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
101 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
102 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
103 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
104 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
105 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
106 #define INT_TX_END_0 0x00080000
107 #define INT_TX_END 0x07f80000
108 #define INT_RX 0x000003fc
109 #define INT_EXT 0x00000002
110 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
111 #define INT_EXT_LINK_PHY 0x00110000
112 #define INT_EXT_TX 0x000000ff
113 #define INT_MASK(p) (0x0468 + ((p) << 10))
114 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
115 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
116 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
117 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
118 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
119 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
120 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
121 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
122 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
123 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
124 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
125 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
126 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
127 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
128 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
129 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
133 * SDMA configuration register.
135 #define RX_BURST_SIZE_16_64BIT (4 << 1)
136 #define BLM_RX_NO_SWAP (1 << 4)
137 #define BLM_TX_NO_SWAP (1 << 5)
138 #define TX_BURST_SIZE_16_64BIT (4 << 22)
140 #if defined(__BIG_ENDIAN)
141 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
142 RX_BURST_SIZE_16_64BIT | \
143 TX_BURST_SIZE_16_64BIT
144 #elif defined(__LITTLE_ENDIAN)
145 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
146 RX_BURST_SIZE_16_64BIT | \
149 TX_BURST_SIZE_16_64BIT
151 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
156 * Port serial control register.
158 #define SET_MII_SPEED_TO_100 (1 << 24)
159 #define SET_GMII_SPEED_TO_1000 (1 << 23)
160 #define SET_FULL_DUPLEX_MODE (1 << 21)
161 #define MAX_RX_PACKET_9700BYTE (5 << 17)
162 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
163 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
164 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
165 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
166 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
167 #define FORCE_LINK_PASS (1 << 1)
168 #define SERIAL_PORT_ENABLE (1 << 0)
170 #define DEFAULT_RX_QUEUE_SIZE 400
171 #define DEFAULT_TX_QUEUE_SIZE 800
177 #if defined(__BIG_ENDIAN)
179 u16 byte_cnt; /* Descriptor buffer byte count */
180 u16 buf_size; /* Buffer size */
181 u32 cmd_sts; /* Descriptor command status */
182 u32 next_desc_ptr; /* Next descriptor pointer */
183 u32 buf_ptr; /* Descriptor buffer pointer */
187 u16 byte_cnt; /* buffer byte count */
188 u16 l4i_chk; /* CPU provided TCP checksum */
189 u32 cmd_sts; /* Command/status field */
190 u32 next_desc_ptr; /* Pointer to next descriptor */
191 u32 buf_ptr; /* pointer to buffer for this descriptor*/
193 #elif defined(__LITTLE_ENDIAN)
195 u32 cmd_sts; /* Descriptor command status */
196 u16 buf_size; /* Buffer size */
197 u16 byte_cnt; /* Descriptor buffer byte count */
198 u32 buf_ptr; /* Descriptor buffer pointer */
199 u32 next_desc_ptr; /* Next descriptor pointer */
203 u32 cmd_sts; /* Command/status field */
204 u16 l4i_chk; /* CPU provided TCP checksum */
205 u16 byte_cnt; /* buffer byte count */
206 u32 buf_ptr; /* pointer to buffer for this descriptor*/
207 u32 next_desc_ptr; /* Pointer to next descriptor */
210 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
213 /* RX & TX descriptor command */
214 #define BUFFER_OWNED_BY_DMA 0x80000000
216 /* RX & TX descriptor status */
217 #define ERROR_SUMMARY 0x00000001
219 /* RX descriptor status */
220 #define LAYER_4_CHECKSUM_OK 0x40000000
221 #define RX_ENABLE_INTERRUPT 0x20000000
222 #define RX_FIRST_DESC 0x08000000
223 #define RX_LAST_DESC 0x04000000
225 /* TX descriptor command */
226 #define TX_ENABLE_INTERRUPT 0x00800000
227 #define GEN_CRC 0x00400000
228 #define TX_FIRST_DESC 0x00200000
229 #define TX_LAST_DESC 0x00100000
230 #define ZERO_PADDING 0x00080000
231 #define GEN_IP_V4_CHECKSUM 0x00040000
232 #define GEN_TCP_UDP_CHECKSUM 0x00020000
233 #define UDP_FRAME 0x00010000
234 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
235 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
237 #define TX_IHL_SHIFT 11
240 /* global *******************************************************************/
241 struct mv643xx_eth_shared_private {
243 * Ethernet controller base address.
248 * Points at the right SMI instance to use.
250 struct mv643xx_eth_shared_private *smi;
253 * Protects access to SMI_REG, which is shared between ports.
255 struct mutex phy_lock;
258 * If we have access to the error interrupt pin (which is
259 * somewhat misnamed as it not only reflects internal errors
260 * but also reflects SMI completion), use that to wait for
261 * SMI access completion instead of polling the SMI busy bit.
264 wait_queue_head_t smi_busy_wait;
267 * Per-port MBUS window access register value.
272 * Hardware-specific parameters.
275 int extended_rx_coal_limit;
276 int tx_bw_control_moved;
280 /* per-port *****************************************************************/
281 struct mib_counters {
282 u64 good_octets_received;
283 u32 bad_octets_received;
284 u32 internal_mac_transmit_err;
285 u32 good_frames_received;
286 u32 bad_frames_received;
287 u32 broadcast_frames_received;
288 u32 multicast_frames_received;
289 u32 frames_64_octets;
290 u32 frames_65_to_127_octets;
291 u32 frames_128_to_255_octets;
292 u32 frames_256_to_511_octets;
293 u32 frames_512_to_1023_octets;
294 u32 frames_1024_to_max_octets;
295 u64 good_octets_sent;
296 u32 good_frames_sent;
297 u32 excessive_collision;
298 u32 multicast_frames_sent;
299 u32 broadcast_frames_sent;
300 u32 unrec_mac_control_received;
302 u32 good_fc_received;
304 u32 undersize_received;
305 u32 fragments_received;
306 u32 oversize_received;
308 u32 mac_receive_error;
323 struct rx_desc *rx_desc_area;
324 dma_addr_t rx_desc_dma;
325 int rx_desc_area_size;
326 struct sk_buff **rx_skb;
338 struct tx_desc *tx_desc_area;
339 dma_addr_t tx_desc_dma;
340 int tx_desc_area_size;
341 struct sk_buff **tx_skb;
344 struct mv643xx_eth_private {
345 struct mv643xx_eth_shared_private *shared;
348 struct net_device *dev;
354 struct mib_counters mib_counters;
355 struct work_struct tx_timeout_task;
356 struct mii_if_info mii;
361 int default_rx_ring_size;
362 unsigned long rx_desc_sram_addr;
363 int rx_desc_sram_size;
365 struct napi_struct napi;
366 struct timer_list rx_oom;
367 struct rx_queue rxq[8];
372 int default_tx_ring_size;
373 unsigned long tx_desc_sram_addr;
374 int tx_desc_sram_size;
376 struct tx_queue txq[8];
377 #ifdef MV643XX_ETH_TX_FAST_REFILL
378 int tx_clean_threshold;
383 /* port register accessors **************************************************/
384 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
386 return readl(mp->shared->base + offset);
389 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
391 writel(data, mp->shared->base + offset);
395 /* rxq/txq helper functions *************************************************/
396 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
398 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
401 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
403 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
406 static void rxq_enable(struct rx_queue *rxq)
408 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
409 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
412 static void rxq_disable(struct rx_queue *rxq)
414 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
415 u8 mask = 1 << rxq->index;
417 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
418 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
422 static void txq_reset_hw_ptr(struct tx_queue *txq)
424 struct mv643xx_eth_private *mp = txq_to_mp(txq);
425 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
428 addr = (u32)txq->tx_desc_dma;
429 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
433 static void txq_enable(struct tx_queue *txq)
435 struct mv643xx_eth_private *mp = txq_to_mp(txq);
436 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
439 static void txq_disable(struct tx_queue *txq)
441 struct mv643xx_eth_private *mp = txq_to_mp(txq);
442 u8 mask = 1 << txq->index;
444 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
445 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
449 static void __txq_maybe_wake(struct tx_queue *txq)
451 struct mv643xx_eth_private *mp = txq_to_mp(txq);
454 * netif_{stop,wake}_queue() flow control only applies to
457 BUG_ON(txq->index != 0);
459 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
460 netif_wake_queue(mp->dev);
464 /* rx ***********************************************************************/
465 static void txq_reclaim(struct tx_queue *txq, int force);
467 static int rxq_refill(struct rx_queue *rxq, int budget, int *oom)
473 * Reserve 2+14 bytes for an ethernet header (the hardware
474 * automatically prepends 2 bytes of dummy data to each
475 * received packet), 16 bytes for up to four VLAN tags, and
476 * 4 bytes for the trailing FCS -- 36 bytes total.
478 skb_size = rxq_to_mp(rxq)->dev->mtu + 36;
481 * Make sure that the skb size is a multiple of 8 bytes, as
482 * the lower three bits of the receive descriptor's buffer
483 * size field are ignored by the hardware.
485 skb_size = (skb_size + 7) & ~7;
488 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
493 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
499 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
501 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
504 rxq->rx_desc_count++;
506 rx = rxq->rx_used_desc++;
507 if (rxq->rx_used_desc == rxq->rx_ring_size)
508 rxq->rx_used_desc = 0;
510 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
511 skb_size, DMA_FROM_DEVICE);
512 rxq->rx_desc_area[rx].buf_size = skb_size;
513 rxq->rx_skb[rx] = skb;
515 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
520 * The hardware automatically prepends 2 bytes of
521 * dummy data to each received packet, so that the
522 * IP header ends up 16-byte aligned.
530 static int rxq_process(struct rx_queue *rxq, int budget)
532 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
533 struct net_device_stats *stats = &mp->dev->stats;
537 while (rx < budget && rxq->rx_desc_count) {
538 struct rx_desc *rx_desc;
539 unsigned int cmd_sts;
542 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
544 cmd_sts = rx_desc->cmd_sts;
545 if (cmd_sts & BUFFER_OWNED_BY_DMA)
549 skb = rxq->rx_skb[rxq->rx_curr_desc];
550 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
553 if (rxq->rx_curr_desc == rxq->rx_ring_size)
554 rxq->rx_curr_desc = 0;
556 dma_unmap_single(NULL, rx_desc->buf_ptr,
557 rx_desc->buf_size, DMA_FROM_DEVICE);
558 rxq->rx_desc_count--;
564 * Note that the descriptor byte count includes 2 dummy
565 * bytes automatically inserted by the hardware at the
566 * start of the packet (which we don't count), and a 4
567 * byte CRC at the end of the packet (which we do count).
570 stats->rx_bytes += rx_desc->byte_cnt - 2;
573 * In case we received a packet without first / last bits
574 * on, or the error summary bit is set, the packet needs
577 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
578 (RX_FIRST_DESC | RX_LAST_DESC))
579 || (cmd_sts & ERROR_SUMMARY)) {
582 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
583 (RX_FIRST_DESC | RX_LAST_DESC)) {
585 dev_printk(KERN_ERR, &mp->dev->dev,
586 "received packet spanning "
587 "multiple descriptors\n");
590 if (cmd_sts & ERROR_SUMMARY)
596 * The -4 is for the CRC in the trailer of the
599 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
601 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
602 skb->ip_summed = CHECKSUM_UNNECESSARY;
604 (cmd_sts & 0x0007fff8) >> 3);
606 skb->protocol = eth_type_trans(skb, mp->dev);
607 netif_receive_skb(skb);
610 mp->dev->last_rx = jiffies;
616 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
618 struct mv643xx_eth_private *mp;
623 mp = container_of(napi, struct mv643xx_eth_private, napi);
625 #ifdef MV643XX_ETH_TX_FAST_REFILL
626 if (++mp->tx_clean_threshold > 5) {
627 mp->tx_clean_threshold = 0;
628 for (i = 0; i < mp->txq_count; i++)
629 txq_reclaim(mp->txq + i, 0);
631 spin_lock_irq(&mp->lock);
632 __txq_maybe_wake(mp->txq);
633 spin_unlock_irq(&mp->lock);
639 for (i = mp->rxq_count - 1; work_done < budget && i >= 0; i--) {
640 struct rx_queue *rxq = mp->rxq + i;
642 work_done += rxq_process(rxq, budget - work_done);
643 work_done += rxq_refill(rxq, budget - work_done, &oom);
646 if (work_done < budget) {
648 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
649 netif_rx_complete(mp->dev, napi);
650 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
656 static inline void oom_timer_wrapper(unsigned long data)
658 struct mv643xx_eth_private *mp = (void *)data;
660 napi_schedule(&mp->napi);
664 /* tx ***********************************************************************/
665 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
669 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
670 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
671 if (fragp->size <= 8 && fragp->page_offset & 7)
678 static int txq_alloc_desc_index(struct tx_queue *txq)
682 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
684 tx_desc_curr = txq->tx_curr_desc++;
685 if (txq->tx_curr_desc == txq->tx_ring_size)
686 txq->tx_curr_desc = 0;
688 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
693 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
695 int nr_frags = skb_shinfo(skb)->nr_frags;
698 for (frag = 0; frag < nr_frags; frag++) {
699 skb_frag_t *this_frag;
701 struct tx_desc *desc;
703 this_frag = &skb_shinfo(skb)->frags[frag];
704 tx_index = txq_alloc_desc_index(txq);
705 desc = &txq->tx_desc_area[tx_index];
708 * The last fragment will generate an interrupt
709 * which will free the skb on TX completion.
711 if (frag == nr_frags - 1) {
712 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
713 ZERO_PADDING | TX_LAST_DESC |
715 txq->tx_skb[tx_index] = skb;
717 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
718 txq->tx_skb[tx_index] = NULL;
722 desc->byte_cnt = this_frag->size;
723 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
724 this_frag->page_offset,
730 static inline __be16 sum16_as_be(__sum16 sum)
732 return (__force __be16)sum;
735 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
737 struct mv643xx_eth_private *mp = txq_to_mp(txq);
738 int nr_frags = skb_shinfo(skb)->nr_frags;
740 struct tx_desc *desc;
744 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
746 tx_index = txq_alloc_desc_index(txq);
747 desc = &txq->tx_desc_area[tx_index];
750 txq_submit_frag_skb(txq, skb);
752 length = skb_headlen(skb);
753 txq->tx_skb[tx_index] = NULL;
755 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
757 txq->tx_skb[tx_index] = skb;
760 desc->byte_cnt = length;
761 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
763 if (skb->ip_summed == CHECKSUM_PARTIAL) {
766 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
767 skb->protocol != htons(ETH_P_8021Q));
769 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
771 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
773 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
774 switch (mac_hdr_len - ETH_HLEN) {
778 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
781 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
784 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
785 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
789 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
790 "mac header length is %d?!\n", mac_hdr_len);
794 switch (ip_hdr(skb)->protocol) {
796 cmd_sts |= UDP_FRAME;
797 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
800 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
806 /* Errata BTS #50, IHL must be 5 if no HW checksum */
807 cmd_sts |= 5 << TX_IHL_SHIFT;
811 /* ensure all other descriptors are written before first cmd_sts */
813 desc->cmd_sts = cmd_sts;
815 /* clear TX_END interrupt status */
816 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
817 rdl(mp, INT_CAUSE(mp->port_num));
819 /* ensure all descriptors are written before poking hardware */
823 txq->tx_desc_count += nr_frags + 1;
826 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
828 struct mv643xx_eth_private *mp = netdev_priv(dev);
829 struct net_device_stats *stats = &dev->stats;
830 struct tx_queue *txq;
833 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
835 dev_printk(KERN_DEBUG, &dev->dev,
836 "failed to linearize skb with tiny "
837 "unaligned fragment\n");
838 return NETDEV_TX_BUSY;
841 spin_lock_irqsave(&mp->lock, flags);
845 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
846 spin_unlock_irqrestore(&mp->lock, flags);
847 if (txq->index == 0 && net_ratelimit())
848 dev_printk(KERN_ERR, &dev->dev,
849 "primary tx queue full?!\n");
854 txq_submit_skb(txq, skb);
855 stats->tx_bytes += skb->len;
857 dev->trans_start = jiffies;
859 if (txq->index == 0) {
862 entries_left = txq->tx_ring_size - txq->tx_desc_count;
863 if (entries_left < MAX_SKB_FRAGS + 1)
864 netif_stop_queue(dev);
867 spin_unlock_irqrestore(&mp->lock, flags);
873 /* tx rate control **********************************************************/
875 * Set total maximum TX rate (shared by all TX queues for this port)
876 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
878 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
884 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
885 if (token_rate > 1023)
888 mtu = (mp->dev->mtu + 255) >> 8;
892 bucket_size = (burst + 255) >> 8;
893 if (bucket_size > 65535)
896 if (mp->shared->tx_bw_control_moved) {
897 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
898 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
899 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
901 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
902 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
903 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
907 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
909 struct mv643xx_eth_private *mp = txq_to_mp(txq);
913 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
914 if (token_rate > 1023)
917 bucket_size = (burst + 255) >> 8;
918 if (bucket_size > 65535)
921 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
922 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
923 (bucket_size << 10) | token_rate);
926 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
928 struct mv643xx_eth_private *mp = txq_to_mp(txq);
933 * Turn on fixed priority mode.
935 if (mp->shared->tx_bw_control_moved)
936 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
938 off = TXQ_FIX_PRIO_CONF(mp->port_num);
941 val |= 1 << txq->index;
945 static void txq_set_wrr(struct tx_queue *txq, int weight)
947 struct mv643xx_eth_private *mp = txq_to_mp(txq);
952 * Turn off fixed priority mode.
954 if (mp->shared->tx_bw_control_moved)
955 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
957 off = TXQ_FIX_PRIO_CONF(mp->port_num);
960 val &= ~(1 << txq->index);
964 * Configure WRR weight for this queue.
966 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
969 val = (val & ~0xff) | (weight & 0xff);
974 /* mii management interface *************************************************/
975 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
977 struct mv643xx_eth_shared_private *msp = dev_id;
979 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
980 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
981 wake_up(&msp->smi_busy_wait);
988 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
990 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
993 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
995 if (msp->err_interrupt == NO_IRQ) {
998 for (i = 0; !smi_is_done(msp); i++) {
1007 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1008 msecs_to_jiffies(100)))
1014 static int smi_reg_read(struct mv643xx_eth_private *mp,
1015 unsigned int addr, unsigned int reg)
1017 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
1018 void __iomem *smi_reg = msp->base + SMI_REG;
1021 mutex_lock(&msp->phy_lock);
1023 if (smi_wait_ready(msp)) {
1024 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1029 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1031 if (smi_wait_ready(msp)) {
1032 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1037 ret = readl(smi_reg);
1038 if (!(ret & SMI_READ_VALID)) {
1039 printk("%s: SMI bus read not valid\n", mp->dev->name);
1047 mutex_unlock(&msp->phy_lock);
1052 static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1053 unsigned int reg, unsigned int value)
1055 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
1056 void __iomem *smi_reg = msp->base + SMI_REG;
1058 mutex_lock(&msp->phy_lock);
1060 if (smi_wait_ready(msp)) {
1061 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1062 mutex_unlock(&msp->phy_lock);
1066 writel(SMI_OPCODE_WRITE | (reg << 21) |
1067 (addr << 16) | (value & 0xffff), smi_reg);
1069 mutex_unlock(&msp->phy_lock);
1075 /* mib counters *************************************************************/
1076 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1078 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1081 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1085 for (i = 0; i < 0x80; i += 4)
1089 static void mib_counters_update(struct mv643xx_eth_private *mp)
1091 struct mib_counters *p = &mp->mib_counters;
1093 p->good_octets_received += mib_read(mp, 0x00);
1094 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1095 p->bad_octets_received += mib_read(mp, 0x08);
1096 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1097 p->good_frames_received += mib_read(mp, 0x10);
1098 p->bad_frames_received += mib_read(mp, 0x14);
1099 p->broadcast_frames_received += mib_read(mp, 0x18);
1100 p->multicast_frames_received += mib_read(mp, 0x1c);
1101 p->frames_64_octets += mib_read(mp, 0x20);
1102 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1103 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1104 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1105 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1106 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1107 p->good_octets_sent += mib_read(mp, 0x38);
1108 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1109 p->good_frames_sent += mib_read(mp, 0x40);
1110 p->excessive_collision += mib_read(mp, 0x44);
1111 p->multicast_frames_sent += mib_read(mp, 0x48);
1112 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1113 p->unrec_mac_control_received += mib_read(mp, 0x50);
1114 p->fc_sent += mib_read(mp, 0x54);
1115 p->good_fc_received += mib_read(mp, 0x58);
1116 p->bad_fc_received += mib_read(mp, 0x5c);
1117 p->undersize_received += mib_read(mp, 0x60);
1118 p->fragments_received += mib_read(mp, 0x64);
1119 p->oversize_received += mib_read(mp, 0x68);
1120 p->jabber_received += mib_read(mp, 0x6c);
1121 p->mac_receive_error += mib_read(mp, 0x70);
1122 p->bad_crc_event += mib_read(mp, 0x74);
1123 p->collision += mib_read(mp, 0x78);
1124 p->late_collision += mib_read(mp, 0x7c);
1128 /* ethtool ******************************************************************/
1129 struct mv643xx_eth_stats {
1130 char stat_string[ETH_GSTRING_LEN];
1137 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1138 offsetof(struct net_device, stats.m), -1 }
1140 #define MIBSTAT(m) \
1141 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1142 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1144 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1153 MIBSTAT(good_octets_received),
1154 MIBSTAT(bad_octets_received),
1155 MIBSTAT(internal_mac_transmit_err),
1156 MIBSTAT(good_frames_received),
1157 MIBSTAT(bad_frames_received),
1158 MIBSTAT(broadcast_frames_received),
1159 MIBSTAT(multicast_frames_received),
1160 MIBSTAT(frames_64_octets),
1161 MIBSTAT(frames_65_to_127_octets),
1162 MIBSTAT(frames_128_to_255_octets),
1163 MIBSTAT(frames_256_to_511_octets),
1164 MIBSTAT(frames_512_to_1023_octets),
1165 MIBSTAT(frames_1024_to_max_octets),
1166 MIBSTAT(good_octets_sent),
1167 MIBSTAT(good_frames_sent),
1168 MIBSTAT(excessive_collision),
1169 MIBSTAT(multicast_frames_sent),
1170 MIBSTAT(broadcast_frames_sent),
1171 MIBSTAT(unrec_mac_control_received),
1173 MIBSTAT(good_fc_received),
1174 MIBSTAT(bad_fc_received),
1175 MIBSTAT(undersize_received),
1176 MIBSTAT(fragments_received),
1177 MIBSTAT(oversize_received),
1178 MIBSTAT(jabber_received),
1179 MIBSTAT(mac_receive_error),
1180 MIBSTAT(bad_crc_event),
1182 MIBSTAT(late_collision),
1185 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1187 struct mv643xx_eth_private *mp = netdev_priv(dev);
1190 err = mii_ethtool_gset(&mp->mii, cmd);
1193 * The MAC does not support 1000baseT_Half.
1195 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1196 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1201 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1203 struct mv643xx_eth_private *mp = netdev_priv(dev);
1206 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1208 cmd->supported = SUPPORTED_MII;
1209 cmd->advertising = ADVERTISED_MII;
1210 switch (port_status & PORT_SPEED_MASK) {
1212 cmd->speed = SPEED_10;
1214 case PORT_SPEED_100:
1215 cmd->speed = SPEED_100;
1217 case PORT_SPEED_1000:
1218 cmd->speed = SPEED_1000;
1224 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1225 cmd->port = PORT_MII;
1226 cmd->phy_address = 0;
1227 cmd->transceiver = XCVR_INTERNAL;
1228 cmd->autoneg = AUTONEG_DISABLE;
1235 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1237 struct mv643xx_eth_private *mp = netdev_priv(dev);
1240 * The MAC does not support 1000baseT_Half.
1242 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1244 return mii_ethtool_sset(&mp->mii, cmd);
1247 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1252 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1253 struct ethtool_drvinfo *drvinfo)
1255 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1256 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1257 strncpy(drvinfo->fw_version, "N/A", 32);
1258 strncpy(drvinfo->bus_info, "platform", 32);
1259 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1262 static int mv643xx_eth_nway_reset(struct net_device *dev)
1264 struct mv643xx_eth_private *mp = netdev_priv(dev);
1266 return mii_nway_restart(&mp->mii);
1269 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1274 static u32 mv643xx_eth_get_link(struct net_device *dev)
1276 struct mv643xx_eth_private *mp = netdev_priv(dev);
1278 return mii_link_ok(&mp->mii);
1281 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1286 static void mv643xx_eth_get_strings(struct net_device *dev,
1287 uint32_t stringset, uint8_t *data)
1291 if (stringset == ETH_SS_STATS) {
1292 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1293 memcpy(data + i * ETH_GSTRING_LEN,
1294 mv643xx_eth_stats[i].stat_string,
1300 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1301 struct ethtool_stats *stats,
1304 struct mv643xx_eth_private *mp = netdev_priv(dev);
1307 mib_counters_update(mp);
1309 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1310 const struct mv643xx_eth_stats *stat;
1313 stat = mv643xx_eth_stats + i;
1315 if (stat->netdev_off >= 0)
1316 p = ((void *)mp->dev) + stat->netdev_off;
1318 p = ((void *)mp) + stat->mp_off;
1320 data[i] = (stat->sizeof_stat == 8) ?
1321 *(uint64_t *)p : *(uint32_t *)p;
1325 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1327 if (sset == ETH_SS_STATS)
1328 return ARRAY_SIZE(mv643xx_eth_stats);
1333 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1334 .get_settings = mv643xx_eth_get_settings,
1335 .set_settings = mv643xx_eth_set_settings,
1336 .get_drvinfo = mv643xx_eth_get_drvinfo,
1337 .nway_reset = mv643xx_eth_nway_reset,
1338 .get_link = mv643xx_eth_get_link,
1339 .set_sg = ethtool_op_set_sg,
1340 .get_strings = mv643xx_eth_get_strings,
1341 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1342 .get_sset_count = mv643xx_eth_get_sset_count,
1345 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1346 .get_settings = mv643xx_eth_get_settings_phyless,
1347 .set_settings = mv643xx_eth_set_settings_phyless,
1348 .get_drvinfo = mv643xx_eth_get_drvinfo,
1349 .nway_reset = mv643xx_eth_nway_reset_phyless,
1350 .get_link = mv643xx_eth_get_link_phyless,
1351 .set_sg = ethtool_op_set_sg,
1352 .get_strings = mv643xx_eth_get_strings,
1353 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1354 .get_sset_count = mv643xx_eth_get_sset_count,
1358 /* address handling *********************************************************/
1359 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1364 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1365 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1367 addr[0] = (mac_h >> 24) & 0xff;
1368 addr[1] = (mac_h >> 16) & 0xff;
1369 addr[2] = (mac_h >> 8) & 0xff;
1370 addr[3] = mac_h & 0xff;
1371 addr[4] = (mac_l >> 8) & 0xff;
1372 addr[5] = mac_l & 0xff;
1375 static void init_mac_tables(struct mv643xx_eth_private *mp)
1379 for (i = 0; i < 0x100; i += 4) {
1380 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1381 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1384 for (i = 0; i < 0x10; i += 4)
1385 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1388 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1389 int table, unsigned char entry)
1391 unsigned int table_reg;
1393 /* Set "accepts frame bit" at specified table entry */
1394 table_reg = rdl(mp, table + (entry & 0xfc));
1395 table_reg |= 0x01 << (8 * (entry & 3));
1396 wrl(mp, table + (entry & 0xfc), table_reg);
1399 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1405 mac_l = (addr[4] << 8) | addr[5];
1406 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1408 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1409 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1411 table = UNICAST_TABLE(mp->port_num);
1412 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1415 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1417 struct mv643xx_eth_private *mp = netdev_priv(dev);
1419 /* +2 is for the offset of the HW addr type */
1420 memcpy(dev->dev_addr, addr + 2, 6);
1422 init_mac_tables(mp);
1423 uc_addr_set(mp, dev->dev_addr);
1428 static int addr_crc(unsigned char *addr)
1433 for (i = 0; i < 6; i++) {
1436 crc = (crc ^ addr[i]) << 8;
1437 for (j = 7; j >= 0; j--) {
1438 if (crc & (0x100 << j))
1446 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1448 struct mv643xx_eth_private *mp = netdev_priv(dev);
1450 struct dev_addr_list *addr;
1453 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1454 if (dev->flags & IFF_PROMISC)
1455 port_config |= UNICAST_PROMISCUOUS_MODE;
1457 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1458 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1460 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1461 int port_num = mp->port_num;
1462 u32 accept = 0x01010101;
1464 for (i = 0; i < 0x100; i += 4) {
1465 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1466 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1471 for (i = 0; i < 0x100; i += 4) {
1472 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1473 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1476 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1477 u8 *a = addr->da_addr;
1480 if (addr->da_addrlen != 6)
1483 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1484 table = SPECIAL_MCAST_TABLE(mp->port_num);
1485 set_filter_table_entry(mp, table, a[5]);
1487 int crc = addr_crc(a);
1489 table = OTHER_MCAST_TABLE(mp->port_num);
1490 set_filter_table_entry(mp, table, crc);
1496 /* rx/tx queue initialisation ***********************************************/
1497 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1499 struct rx_queue *rxq = mp->rxq + index;
1500 struct rx_desc *rx_desc;
1506 rxq->rx_ring_size = mp->default_rx_ring_size;
1508 rxq->rx_desc_count = 0;
1509 rxq->rx_curr_desc = 0;
1510 rxq->rx_used_desc = 0;
1512 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1514 if (index == 0 && size <= mp->rx_desc_sram_size) {
1515 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1516 mp->rx_desc_sram_size);
1517 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1519 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1524 if (rxq->rx_desc_area == NULL) {
1525 dev_printk(KERN_ERR, &mp->dev->dev,
1526 "can't allocate rx ring (%d bytes)\n", size);
1529 memset(rxq->rx_desc_area, 0, size);
1531 rxq->rx_desc_area_size = size;
1532 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1534 if (rxq->rx_skb == NULL) {
1535 dev_printk(KERN_ERR, &mp->dev->dev,
1536 "can't allocate rx skb ring\n");
1540 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1541 for (i = 0; i < rxq->rx_ring_size; i++) {
1545 if (nexti == rxq->rx_ring_size)
1548 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1549 nexti * sizeof(struct rx_desc);
1556 if (index == 0 && size <= mp->rx_desc_sram_size)
1557 iounmap(rxq->rx_desc_area);
1559 dma_free_coherent(NULL, size,
1567 static void rxq_deinit(struct rx_queue *rxq)
1569 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1574 for (i = 0; i < rxq->rx_ring_size; i++) {
1575 if (rxq->rx_skb[i]) {
1576 dev_kfree_skb(rxq->rx_skb[i]);
1577 rxq->rx_desc_count--;
1581 if (rxq->rx_desc_count) {
1582 dev_printk(KERN_ERR, &mp->dev->dev,
1583 "error freeing rx ring -- %d skbs stuck\n",
1584 rxq->rx_desc_count);
1587 if (rxq->index == 0 &&
1588 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1589 iounmap(rxq->rx_desc_area);
1591 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1592 rxq->rx_desc_area, rxq->rx_desc_dma);
1597 static int txq_init(struct mv643xx_eth_private *mp, int index)
1599 struct tx_queue *txq = mp->txq + index;
1600 struct tx_desc *tx_desc;
1606 txq->tx_ring_size = mp->default_tx_ring_size;
1608 txq->tx_desc_count = 0;
1609 txq->tx_curr_desc = 0;
1610 txq->tx_used_desc = 0;
1612 size = txq->tx_ring_size * sizeof(struct tx_desc);
1614 if (index == 0 && size <= mp->tx_desc_sram_size) {
1615 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1616 mp->tx_desc_sram_size);
1617 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1619 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1624 if (txq->tx_desc_area == NULL) {
1625 dev_printk(KERN_ERR, &mp->dev->dev,
1626 "can't allocate tx ring (%d bytes)\n", size);
1629 memset(txq->tx_desc_area, 0, size);
1631 txq->tx_desc_area_size = size;
1632 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1634 if (txq->tx_skb == NULL) {
1635 dev_printk(KERN_ERR, &mp->dev->dev,
1636 "can't allocate tx skb ring\n");
1640 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1641 for (i = 0; i < txq->tx_ring_size; i++) {
1642 struct tx_desc *txd = tx_desc + i;
1646 if (nexti == txq->tx_ring_size)
1650 txd->next_desc_ptr = txq->tx_desc_dma +
1651 nexti * sizeof(struct tx_desc);
1658 if (index == 0 && size <= mp->tx_desc_sram_size)
1659 iounmap(txq->tx_desc_area);
1661 dma_free_coherent(NULL, size,
1669 static void txq_reclaim(struct tx_queue *txq, int force)
1671 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1672 unsigned long flags;
1674 spin_lock_irqsave(&mp->lock, flags);
1675 while (txq->tx_desc_count > 0) {
1677 struct tx_desc *desc;
1679 struct sk_buff *skb;
1683 tx_index = txq->tx_used_desc;
1684 desc = &txq->tx_desc_area[tx_index];
1685 cmd_sts = desc->cmd_sts;
1687 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1690 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1693 txq->tx_used_desc = tx_index + 1;
1694 if (txq->tx_used_desc == txq->tx_ring_size)
1695 txq->tx_used_desc = 0;
1696 txq->tx_desc_count--;
1698 addr = desc->buf_ptr;
1699 count = desc->byte_cnt;
1700 skb = txq->tx_skb[tx_index];
1701 txq->tx_skb[tx_index] = NULL;
1703 if (cmd_sts & ERROR_SUMMARY) {
1704 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1705 mp->dev->stats.tx_errors++;
1709 * Drop mp->lock while we free the skb.
1711 spin_unlock_irqrestore(&mp->lock, flags);
1713 if (cmd_sts & TX_FIRST_DESC)
1714 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1716 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1719 dev_kfree_skb_irq(skb);
1721 spin_lock_irqsave(&mp->lock, flags);
1723 spin_unlock_irqrestore(&mp->lock, flags);
1726 static void txq_deinit(struct tx_queue *txq)
1728 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1731 txq_reclaim(txq, 1);
1733 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1735 if (txq->index == 0 &&
1736 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1737 iounmap(txq->tx_desc_area);
1739 dma_free_coherent(NULL, txq->tx_desc_area_size,
1740 txq->tx_desc_area, txq->tx_desc_dma);
1746 /* netdev ops and related ***************************************************/
1747 static void handle_link_event(struct mv643xx_eth_private *mp)
1749 struct net_device *dev = mp->dev;
1755 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1756 if (!(port_status & LINK_UP)) {
1757 if (netif_carrier_ok(dev)) {
1760 printk(KERN_INFO "%s: link down\n", dev->name);
1762 netif_carrier_off(dev);
1764 for (i = 0; i < mp->txq_count; i++) {
1765 struct tx_queue *txq = mp->txq + i;
1767 txq_reclaim(txq, 1);
1768 txq_reset_hw_ptr(txq);
1774 switch (port_status & PORT_SPEED_MASK) {
1778 case PORT_SPEED_100:
1781 case PORT_SPEED_1000:
1788 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1789 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1791 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1792 "flow control %sabled\n", dev->name,
1793 speed, duplex ? "full" : "half",
1796 if (!netif_carrier_ok(dev))
1797 netif_carrier_on(dev);
1800 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1802 struct net_device *dev = (struct net_device *)dev_id;
1803 struct mv643xx_eth_private *mp = netdev_priv(dev);
1807 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1808 (INT_TX_END | INT_RX | INT_EXT);
1813 if (int_cause & INT_EXT) {
1814 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1815 & (INT_EXT_LINK_PHY | INT_EXT_TX);
1816 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1819 if (int_cause_ext & INT_EXT_LINK_PHY)
1820 handle_link_event(mp);
1823 * RxBuffer or RxError set for any of the 8 queues?
1825 if (int_cause & INT_RX) {
1826 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_RX));
1827 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1828 rdl(mp, INT_MASK(mp->port_num));
1830 napi_schedule(&mp->napi);
1834 * TxBuffer or TxError set for any of the 8 queues?
1836 if (int_cause_ext & INT_EXT_TX) {
1839 for (i = 0; i < mp->txq_count; i++)
1840 txq_reclaim(mp->txq + i, 0);
1843 * Enough space again in the primary TX queue for a
1846 spin_lock(&mp->lock);
1847 __txq_maybe_wake(mp->txq);
1848 spin_unlock(&mp->lock);
1852 * Any TxEnd interrupts?
1854 if (int_cause & INT_TX_END) {
1857 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1859 spin_lock(&mp->lock);
1860 for (i = 0; i < 8; i++) {
1861 struct tx_queue *txq = mp->txq + i;
1865 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1869 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1870 expected_ptr = (u32)txq->tx_desc_dma +
1871 txq->tx_curr_desc * sizeof(struct tx_desc);
1873 if (hw_desc_ptr != expected_ptr)
1876 spin_unlock(&mp->lock);
1882 static void phy_reset(struct mv643xx_eth_private *mp)
1886 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1891 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1895 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1896 } while (data >= 0 && data & BMCR_RESET);
1899 static void port_start(struct mv643xx_eth_private *mp)
1905 * Perform PHY reset, if there is a PHY.
1907 if (mp->phy_addr != -1) {
1908 struct ethtool_cmd cmd;
1910 mv643xx_eth_get_settings(mp->dev, &cmd);
1912 mv643xx_eth_set_settings(mp->dev, &cmd);
1916 * Configure basic link parameters.
1918 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1920 pscr |= SERIAL_PORT_ENABLE;
1921 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1923 pscr |= DO_NOT_FORCE_LINK_FAIL;
1924 if (mp->phy_addr == -1)
1925 pscr |= FORCE_LINK_PASS;
1926 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1928 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1931 * Configure TX path and queues.
1933 tx_set_rate(mp, 1000000000, 16777216);
1934 for (i = 0; i < mp->txq_count; i++) {
1935 struct tx_queue *txq = mp->txq + i;
1937 txq_reset_hw_ptr(txq);
1938 txq_set_rate(txq, 1000000000, 16777216);
1939 txq_set_fixed_prio_mode(txq);
1943 * Add configured unicast address to address filter table.
1945 uc_addr_set(mp, mp->dev->dev_addr);
1948 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1949 * frames to RX queue #0.
1951 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1954 * Treat BPDUs as normal multicasts, and disable partition mode.
1956 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1959 * Enable the receive queues.
1961 for (i = 0; i < mp->rxq_count; i++) {
1962 struct rx_queue *rxq = mp->rxq + i;
1963 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
1966 addr = (u32)rxq->rx_desc_dma;
1967 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1974 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1976 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1979 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1980 if (mp->shared->extended_rx_coal_limit) {
1984 val |= (coal & 0x8000) << 10;
1985 val |= (coal & 0x7fff) << 7;
1990 val |= (coal & 0x3fff) << 8;
1992 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1995 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1997 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2001 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2004 static int mv643xx_eth_open(struct net_device *dev)
2006 struct mv643xx_eth_private *mp = netdev_priv(dev);
2011 wrl(mp, INT_CAUSE(mp->port_num), 0);
2012 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2013 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2015 err = request_irq(dev->irq, mv643xx_eth_irq,
2016 IRQF_SHARED, dev->name, dev);
2018 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2022 init_mac_tables(mp);
2024 napi_enable(&mp->napi);
2027 for (i = 0; i < mp->rxq_count; i++) {
2028 err = rxq_init(mp, i);
2031 rxq_deinit(mp->rxq + i);
2035 rxq_refill(mp->rxq + i, INT_MAX, &oom);
2039 mp->rx_oom.expires = jiffies + (HZ / 10);
2040 add_timer(&mp->rx_oom);
2043 for (i = 0; i < mp->txq_count; i++) {
2044 err = txq_init(mp, i);
2047 txq_deinit(mp->txq + i);
2052 netif_carrier_off(dev);
2059 wrl(mp, INT_MASK_EXT(mp->port_num), INT_EXT_LINK_PHY | INT_EXT_TX);
2060 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2066 for (i = 0; i < mp->rxq_count; i++)
2067 rxq_deinit(mp->rxq + i);
2069 free_irq(dev->irq, dev);
2074 static void port_reset(struct mv643xx_eth_private *mp)
2079 for (i = 0; i < mp->rxq_count; i++)
2080 rxq_disable(mp->rxq + i);
2081 for (i = 0; i < mp->txq_count; i++)
2082 txq_disable(mp->txq + i);
2085 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2087 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2092 /* Reset the Enable bit in the Configuration Register */
2093 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2094 data &= ~(SERIAL_PORT_ENABLE |
2095 DO_NOT_FORCE_LINK_FAIL |
2097 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2100 static int mv643xx_eth_stop(struct net_device *dev)
2102 struct mv643xx_eth_private *mp = netdev_priv(dev);
2105 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2106 rdl(mp, INT_MASK(mp->port_num));
2108 napi_disable(&mp->napi);
2110 del_timer_sync(&mp->rx_oom);
2112 netif_carrier_off(dev);
2114 free_irq(dev->irq, dev);
2117 mib_counters_update(mp);
2119 for (i = 0; i < mp->rxq_count; i++)
2120 rxq_deinit(mp->rxq + i);
2121 for (i = 0; i < mp->txq_count; i++)
2122 txq_deinit(mp->txq + i);
2127 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2129 struct mv643xx_eth_private *mp = netdev_priv(dev);
2131 if (mp->phy_addr != -1)
2132 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2137 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2139 struct mv643xx_eth_private *mp = netdev_priv(dev);
2141 if (new_mtu < 64 || new_mtu > 9500)
2145 tx_set_rate(mp, 1000000000, 16777216);
2147 if (!netif_running(dev))
2151 * Stop and then re-open the interface. This will allocate RX
2152 * skbs of the new MTU.
2153 * There is a possible danger that the open will not succeed,
2154 * due to memory being full.
2156 mv643xx_eth_stop(dev);
2157 if (mv643xx_eth_open(dev)) {
2158 dev_printk(KERN_ERR, &dev->dev,
2159 "fatal error on re-opening device after "
2166 static void tx_timeout_task(struct work_struct *ugly)
2168 struct mv643xx_eth_private *mp;
2170 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2171 if (netif_running(mp->dev)) {
2172 netif_stop_queue(mp->dev);
2175 netif_wake_queue(mp->dev);
2179 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2181 struct mv643xx_eth_private *mp = netdev_priv(dev);
2183 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2185 schedule_work(&mp->tx_timeout_task);
2188 #ifdef CONFIG_NET_POLL_CONTROLLER
2189 static void mv643xx_eth_netpoll(struct net_device *dev)
2191 struct mv643xx_eth_private *mp = netdev_priv(dev);
2193 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2194 rdl(mp, INT_MASK(mp->port_num));
2196 mv643xx_eth_irq(dev->irq, dev);
2198 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2202 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2204 struct mv643xx_eth_private *mp = netdev_priv(dev);
2205 return smi_reg_read(mp, addr, reg);
2208 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2210 struct mv643xx_eth_private *mp = netdev_priv(dev);
2211 smi_reg_write(mp, addr, reg, val);
2215 /* platform glue ************************************************************/
2217 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2218 struct mbus_dram_target_info *dram)
2220 void __iomem *base = msp->base;
2225 for (i = 0; i < 6; i++) {
2226 writel(0, base + WINDOW_BASE(i));
2227 writel(0, base + WINDOW_SIZE(i));
2229 writel(0, base + WINDOW_REMAP_HIGH(i));
2235 for (i = 0; i < dram->num_cs; i++) {
2236 struct mbus_dram_window *cs = dram->cs + i;
2238 writel((cs->base & 0xffff0000) |
2239 (cs->mbus_attr << 8) |
2240 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2241 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2243 win_enable &= ~(1 << i);
2244 win_protect |= 3 << (2 * i);
2247 writel(win_enable, base + WINDOW_BAR_ENABLE);
2248 msp->win_protect = win_protect;
2251 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2254 * Check whether we have a 14-bit coal limit field in bits
2255 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2256 * SDMA config register.
2258 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2259 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2260 msp->extended_rx_coal_limit = 1;
2262 msp->extended_rx_coal_limit = 0;
2265 * Check whether the TX rate control registers are in the
2266 * old or the new place.
2268 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2269 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2270 msp->tx_bw_control_moved = 1;
2272 msp->tx_bw_control_moved = 0;
2275 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2277 static int mv643xx_eth_version_printed = 0;
2278 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2279 struct mv643xx_eth_shared_private *msp;
2280 struct resource *res;
2283 if (!mv643xx_eth_version_printed++)
2284 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2285 "driver version %s\n", mv643xx_eth_driver_version);
2288 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2293 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2296 memset(msp, 0, sizeof(*msp));
2298 msp->base = ioremap(res->start, res->end - res->start + 1);
2299 if (msp->base == NULL)
2303 if (pd != NULL && pd->shared_smi != NULL)
2304 msp->smi = platform_get_drvdata(pd->shared_smi);
2306 mutex_init(&msp->phy_lock);
2308 msp->err_interrupt = NO_IRQ;
2309 init_waitqueue_head(&msp->smi_busy_wait);
2312 * Check whether the error interrupt is hooked up.
2314 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2318 err = request_irq(res->start, mv643xx_eth_err_irq,
2319 IRQF_SHARED, "mv643xx_eth", msp);
2321 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2322 msp->err_interrupt = res->start;
2327 * (Re-)program MBUS remapping windows if we are asked to.
2329 if (pd != NULL && pd->dram != NULL)
2330 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2333 * Detect hardware parameters.
2335 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2336 infer_hw_params(msp);
2338 platform_set_drvdata(pdev, msp);
2348 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2350 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2352 if (msp->err_interrupt != NO_IRQ)
2353 free_irq(msp->err_interrupt, msp);
2360 static struct platform_driver mv643xx_eth_shared_driver = {
2361 .probe = mv643xx_eth_shared_probe,
2362 .remove = mv643xx_eth_shared_remove,
2364 .name = MV643XX_ETH_SHARED_NAME,
2365 .owner = THIS_MODULE,
2369 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2371 int addr_shift = 5 * mp->port_num;
2374 data = rdl(mp, PHY_ADDR);
2375 data &= ~(0x1f << addr_shift);
2376 data |= (phy_addr & 0x1f) << addr_shift;
2377 wrl(mp, PHY_ADDR, data);
2380 static int phy_addr_get(struct mv643xx_eth_private *mp)
2384 data = rdl(mp, PHY_ADDR);
2386 return (data >> (5 * mp->port_num)) & 0x1f;
2389 static void set_params(struct mv643xx_eth_private *mp,
2390 struct mv643xx_eth_platform_data *pd)
2392 struct net_device *dev = mp->dev;
2394 if (is_valid_ether_addr(pd->mac_addr))
2395 memcpy(dev->dev_addr, pd->mac_addr, 6);
2397 uc_addr_get(mp, dev->dev_addr);
2399 if (pd->phy_addr == MV643XX_ETH_PHY_NONE) {
2402 if (pd->phy_addr != MV643XX_ETH_PHY_ADDR_DEFAULT) {
2403 mp->phy_addr = pd->phy_addr & 0x3f;
2404 phy_addr_set(mp, mp->phy_addr);
2406 mp->phy_addr = phy_addr_get(mp);
2410 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2411 if (pd->rx_queue_size)
2412 mp->default_rx_ring_size = pd->rx_queue_size;
2413 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2414 mp->rx_desc_sram_size = pd->rx_sram_size;
2416 mp->rxq_count = pd->rx_queue_count ? : 1;
2418 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2419 if (pd->tx_queue_size)
2420 mp->default_tx_ring_size = pd->tx_queue_size;
2421 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2422 mp->tx_desc_sram_size = pd->tx_sram_size;
2424 mp->txq_count = pd->tx_queue_count ? : 1;
2427 static int phy_detect(struct mv643xx_eth_private *mp)
2432 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2436 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2439 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2443 if (((data ^ data2) & BMCR_ANENABLE) == 0)
2446 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
2451 static int phy_init(struct mv643xx_eth_private *mp,
2452 struct mv643xx_eth_platform_data *pd)
2454 struct ethtool_cmd cmd;
2457 err = phy_detect(mp);
2459 dev_printk(KERN_INFO, &mp->dev->dev,
2460 "no PHY detected at addr %d\n", mp->phy_addr);
2465 mp->mii.phy_id = mp->phy_addr;
2466 mp->mii.phy_id_mask = 0x3f;
2467 mp->mii.reg_num_mask = 0x1f;
2468 mp->mii.dev = mp->dev;
2469 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2470 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2472 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2474 memset(&cmd, 0, sizeof(cmd));
2476 cmd.port = PORT_MII;
2477 cmd.transceiver = XCVR_INTERNAL;
2478 cmd.phy_address = mp->phy_addr;
2479 if (pd->speed == 0) {
2480 cmd.autoneg = AUTONEG_ENABLE;
2481 cmd.speed = SPEED_100;
2482 cmd.advertising = ADVERTISED_10baseT_Half |
2483 ADVERTISED_10baseT_Full |
2484 ADVERTISED_100baseT_Half |
2485 ADVERTISED_100baseT_Full;
2486 if (mp->mii.supports_gmii)
2487 cmd.advertising |= ADVERTISED_1000baseT_Full;
2489 cmd.autoneg = AUTONEG_DISABLE;
2490 cmd.speed = pd->speed;
2491 cmd.duplex = pd->duplex;
2494 mv643xx_eth_set_settings(mp->dev, &cmd);
2499 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2503 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2504 if (pscr & SERIAL_PORT_ENABLE) {
2505 pscr &= ~SERIAL_PORT_ENABLE;
2506 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2509 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2510 if (mp->phy_addr == -1) {
2511 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2512 if (speed == SPEED_1000)
2513 pscr |= SET_GMII_SPEED_TO_1000;
2514 else if (speed == SPEED_100)
2515 pscr |= SET_MII_SPEED_TO_100;
2517 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2519 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2520 if (duplex == DUPLEX_FULL)
2521 pscr |= SET_FULL_DUPLEX_MODE;
2524 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2527 static int mv643xx_eth_probe(struct platform_device *pdev)
2529 struct mv643xx_eth_platform_data *pd;
2530 struct mv643xx_eth_private *mp;
2531 struct net_device *dev;
2532 struct resource *res;
2533 DECLARE_MAC_BUF(mac);
2536 pd = pdev->dev.platform_data;
2538 dev_printk(KERN_ERR, &pdev->dev,
2539 "no mv643xx_eth_platform_data\n");
2543 if (pd->shared == NULL) {
2544 dev_printk(KERN_ERR, &pdev->dev,
2545 "no mv643xx_eth_platform_data->shared\n");
2549 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2553 mp = netdev_priv(dev);
2554 platform_set_drvdata(pdev, mp);
2556 mp->shared = platform_get_drvdata(pd->shared);
2557 mp->port_num = pd->port_number;
2563 spin_lock_init(&mp->lock);
2565 mib_counters_clear(mp);
2566 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2568 if (mp->phy_addr != -1) {
2569 err = phy_init(mp, pd);
2573 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2575 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2577 init_pscr(mp, pd->speed, pd->duplex);
2579 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2581 init_timer(&mp->rx_oom);
2582 mp->rx_oom.data = (unsigned long)mp;
2583 mp->rx_oom.function = oom_timer_wrapper;
2586 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2588 dev->irq = res->start;
2590 dev->hard_start_xmit = mv643xx_eth_xmit;
2591 dev->open = mv643xx_eth_open;
2592 dev->stop = mv643xx_eth_stop;
2593 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2594 dev->set_mac_address = mv643xx_eth_set_mac_address;
2595 dev->do_ioctl = mv643xx_eth_ioctl;
2596 dev->change_mtu = mv643xx_eth_change_mtu;
2597 dev->tx_timeout = mv643xx_eth_tx_timeout;
2598 #ifdef CONFIG_NET_POLL_CONTROLLER
2599 dev->poll_controller = mv643xx_eth_netpoll;
2601 dev->watchdog_timeo = 2 * HZ;
2604 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2605 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2607 SET_NETDEV_DEV(dev, &pdev->dev);
2609 if (mp->shared->win_protect)
2610 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2612 err = register_netdev(dev);
2616 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2617 mp->port_num, print_mac(mac, dev->dev_addr));
2619 if (mp->tx_desc_sram_size > 0)
2620 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2630 static int mv643xx_eth_remove(struct platform_device *pdev)
2632 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2634 unregister_netdev(mp->dev);
2635 flush_scheduled_work();
2636 free_netdev(mp->dev);
2638 platform_set_drvdata(pdev, NULL);
2643 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2645 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2647 /* Mask all interrupts on ethernet port */
2648 wrl(mp, INT_MASK(mp->port_num), 0);
2649 rdl(mp, INT_MASK(mp->port_num));
2651 if (netif_running(mp->dev))
2655 static struct platform_driver mv643xx_eth_driver = {
2656 .probe = mv643xx_eth_probe,
2657 .remove = mv643xx_eth_remove,
2658 .shutdown = mv643xx_eth_shutdown,
2660 .name = MV643XX_ETH_NAME,
2661 .owner = THIS_MODULE,
2665 static int __init mv643xx_eth_init_module(void)
2669 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2671 rc = platform_driver_register(&mv643xx_eth_driver);
2673 platform_driver_unregister(&mv643xx_eth_shared_driver);
2678 module_init(mv643xx_eth_init_module);
2680 static void __exit mv643xx_eth_cleanup_module(void)
2682 platform_driver_unregister(&mv643xx_eth_driver);
2683 platform_driver_unregister(&mv643xx_eth_shared_driver);
2685 module_exit(mv643xx_eth_cleanup_module);
2687 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2688 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2689 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2690 MODULE_LICENSE("GPL");
2691 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2692 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);