2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.1";
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_NAPI
62 #define MV643XX_ETH_TX_FAST_REFILL
64 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
65 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
67 #define MAX_DESCS_PER_SKB 1
71 * Registers shared between all ports.
73 #define PHY_ADDR 0x0000
74 #define SMI_REG 0x0004
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
84 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
85 #define UNICAST_PROMISCUOUS_MODE 0x00000001
86 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
92 #define TX_FIFO_EMPTY 0x00000400
93 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
94 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
95 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
96 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
97 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
98 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
99 #define INT_TX_END_0 0x00080000
100 #define INT_TX_END 0x07f80000
101 #define INT_RX 0x0007fbfc
102 #define INT_EXT 0x00000002
103 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
104 #define INT_EXT_LINK 0x00100000
105 #define INT_EXT_PHY 0x00010000
106 #define INT_EXT_TX_ERROR_0 0x00000100
107 #define INT_EXT_TX_0 0x00000001
108 #define INT_EXT_TX 0x0000ffff
109 #define INT_MASK(p) (0x0468 + ((p) << 10))
110 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
111 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
112 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
113 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
114 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
115 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
116 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
117 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
118 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
119 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
120 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
121 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
122 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
123 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
124 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
125 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
129 * SDMA configuration register.
131 #define RX_BURST_SIZE_4_64BIT (2 << 1)
132 #define BLM_RX_NO_SWAP (1 << 4)
133 #define BLM_TX_NO_SWAP (1 << 5)
134 #define TX_BURST_SIZE_4_64BIT (2 << 22)
136 #if defined(__BIG_ENDIAN)
137 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
138 RX_BURST_SIZE_4_64BIT | \
139 TX_BURST_SIZE_4_64BIT
140 #elif defined(__LITTLE_ENDIAN)
141 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
142 RX_BURST_SIZE_4_64BIT | \
145 TX_BURST_SIZE_4_64BIT
147 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
152 * Port serial control register.
154 #define SET_MII_SPEED_TO_100 (1 << 24)
155 #define SET_GMII_SPEED_TO_1000 (1 << 23)
156 #define SET_FULL_DUPLEX_MODE (1 << 21)
157 #define MAX_RX_PACKET_1522BYTE (1 << 17)
158 #define MAX_RX_PACKET_9700BYTE (5 << 17)
159 #define MAX_RX_PACKET_MASK (7 << 17)
160 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
161 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
162 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
163 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
164 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
165 #define FORCE_LINK_PASS (1 << 1)
166 #define SERIAL_PORT_ENABLE (1 << 0)
168 #define DEFAULT_RX_QUEUE_SIZE 400
169 #define DEFAULT_TX_QUEUE_SIZE 800
175 #if defined(__BIG_ENDIAN)
177 u16 byte_cnt; /* Descriptor buffer byte count */
178 u16 buf_size; /* Buffer size */
179 u32 cmd_sts; /* Descriptor command status */
180 u32 next_desc_ptr; /* Next descriptor pointer */
181 u32 buf_ptr; /* Descriptor buffer pointer */
185 u16 byte_cnt; /* buffer byte count */
186 u16 l4i_chk; /* CPU provided TCP checksum */
187 u32 cmd_sts; /* Command/status field */
188 u32 next_desc_ptr; /* Pointer to next descriptor */
189 u32 buf_ptr; /* pointer to buffer for this descriptor*/
191 #elif defined(__LITTLE_ENDIAN)
193 u32 cmd_sts; /* Descriptor command status */
194 u16 buf_size; /* Buffer size */
195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 u32 next_desc_ptr; /* Next descriptor pointer */
201 u32 cmd_sts; /* Command/status field */
202 u16 l4i_chk; /* CPU provided TCP checksum */
203 u16 byte_cnt; /* buffer byte count */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 u32 next_desc_ptr; /* Pointer to next descriptor */
208 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
211 /* RX & TX descriptor command */
212 #define BUFFER_OWNED_BY_DMA 0x80000000
214 /* RX & TX descriptor status */
215 #define ERROR_SUMMARY 0x00000001
217 /* RX descriptor status */
218 #define LAYER_4_CHECKSUM_OK 0x40000000
219 #define RX_ENABLE_INTERRUPT 0x20000000
220 #define RX_FIRST_DESC 0x08000000
221 #define RX_LAST_DESC 0x04000000
223 /* TX descriptor command */
224 #define TX_ENABLE_INTERRUPT 0x00800000
225 #define GEN_CRC 0x00400000
226 #define TX_FIRST_DESC 0x00200000
227 #define TX_LAST_DESC 0x00100000
228 #define ZERO_PADDING 0x00080000
229 #define GEN_IP_V4_CHECKSUM 0x00040000
230 #define GEN_TCP_UDP_CHECKSUM 0x00020000
231 #define UDP_FRAME 0x00010000
233 #define TX_IHL_SHIFT 11
236 /* global *******************************************************************/
237 struct mv643xx_eth_shared_private {
239 * Ethernet controller base address.
244 * Protects access to SMI_REG, which is shared between ports.
249 * Per-port MBUS window access register value.
254 * Hardware-specific parameters.
257 int extended_rx_coal_limit;
258 int tx_bw_control_moved;
262 /* per-port *****************************************************************/
263 struct mib_counters {
264 u64 good_octets_received;
265 u32 bad_octets_received;
266 u32 internal_mac_transmit_err;
267 u32 good_frames_received;
268 u32 bad_frames_received;
269 u32 broadcast_frames_received;
270 u32 multicast_frames_received;
271 u32 frames_64_octets;
272 u32 frames_65_to_127_octets;
273 u32 frames_128_to_255_octets;
274 u32 frames_256_to_511_octets;
275 u32 frames_512_to_1023_octets;
276 u32 frames_1024_to_max_octets;
277 u64 good_octets_sent;
278 u32 good_frames_sent;
279 u32 excessive_collision;
280 u32 multicast_frames_sent;
281 u32 broadcast_frames_sent;
282 u32 unrec_mac_control_received;
284 u32 good_fc_received;
286 u32 undersize_received;
287 u32 fragments_received;
288 u32 oversize_received;
290 u32 mac_receive_error;
305 struct rx_desc *rx_desc_area;
306 dma_addr_t rx_desc_dma;
307 int rx_desc_area_size;
308 struct sk_buff **rx_skb;
310 struct timer_list rx_oom;
322 struct tx_desc *tx_desc_area;
323 dma_addr_t tx_desc_dma;
324 int tx_desc_area_size;
325 struct sk_buff **tx_skb;
328 struct mv643xx_eth_private {
329 struct mv643xx_eth_shared_private *shared;
332 struct net_device *dev;
334 struct mv643xx_eth_shared_private *shared_smi;
339 struct mib_counters mib_counters;
340 struct work_struct tx_timeout_task;
341 struct mii_if_info mii;
346 int default_rx_ring_size;
347 unsigned long rx_desc_sram_addr;
348 int rx_desc_sram_size;
351 struct napi_struct napi;
352 struct rx_queue rxq[8];
357 int default_tx_ring_size;
358 unsigned long tx_desc_sram_addr;
359 int tx_desc_sram_size;
362 struct tx_queue txq[8];
363 #ifdef MV643XX_ETH_TX_FAST_REFILL
364 int tx_clean_threshold;
369 /* port register accessors **************************************************/
370 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
372 return readl(mp->shared->base + offset);
375 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
377 writel(data, mp->shared->base + offset);
381 /* rxq/txq helper functions *************************************************/
382 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
384 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
387 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
389 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
392 static void rxq_enable(struct rx_queue *rxq)
394 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
395 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
398 static void rxq_disable(struct rx_queue *rxq)
400 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
401 u8 mask = 1 << rxq->index;
403 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
404 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
408 static void txq_reset_hw_ptr(struct tx_queue *txq)
410 struct mv643xx_eth_private *mp = txq_to_mp(txq);
411 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
414 addr = (u32)txq->tx_desc_dma;
415 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
419 static void txq_enable(struct tx_queue *txq)
421 struct mv643xx_eth_private *mp = txq_to_mp(txq);
422 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
425 static void txq_disable(struct tx_queue *txq)
427 struct mv643xx_eth_private *mp = txq_to_mp(txq);
428 u8 mask = 1 << txq->index;
430 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
431 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
435 static void __txq_maybe_wake(struct tx_queue *txq)
437 struct mv643xx_eth_private *mp = txq_to_mp(txq);
440 * netif_{stop,wake}_queue() flow control only applies to
443 BUG_ON(txq->index != mp->txq_primary);
445 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
446 netif_wake_queue(mp->dev);
450 /* rx ***********************************************************************/
451 static void txq_reclaim(struct tx_queue *txq, int force);
453 static void rxq_refill(struct rx_queue *rxq)
455 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
458 spin_lock_irqsave(&mp->lock, flags);
460 while (rxq->rx_desc_count < rxq->rx_ring_size) {
467 * Reserve 2+14 bytes for an ethernet header (the
468 * hardware automatically prepends 2 bytes of dummy
469 * data to each received packet), 4 bytes for a VLAN
470 * header, and 4 bytes for the trailing FCS -- 24
473 skb_size = mp->dev->mtu + 24;
475 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
479 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
481 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
483 rxq->rx_desc_count++;
484 rx = rxq->rx_used_desc;
485 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
487 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
488 skb_size, DMA_FROM_DEVICE);
489 rxq->rx_desc_area[rx].buf_size = skb_size;
490 rxq->rx_skb[rx] = skb;
492 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
497 * The hardware automatically prepends 2 bytes of
498 * dummy data to each received packet, so that the
499 * IP header ends up 16-byte aligned.
504 if (rxq->rx_desc_count != rxq->rx_ring_size) {
505 rxq->rx_oom.expires = jiffies + (HZ / 10);
506 add_timer(&rxq->rx_oom);
509 spin_unlock_irqrestore(&mp->lock, flags);
512 static inline void rxq_refill_timer_wrapper(unsigned long data)
514 rxq_refill((struct rx_queue *)data);
517 static int rxq_process(struct rx_queue *rxq, int budget)
519 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
520 struct net_device_stats *stats = &mp->dev->stats;
524 while (rx < budget) {
525 struct rx_desc *rx_desc;
526 unsigned int cmd_sts;
530 spin_lock_irqsave(&mp->lock, flags);
532 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
534 cmd_sts = rx_desc->cmd_sts;
535 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
536 spin_unlock_irqrestore(&mp->lock, flags);
541 skb = rxq->rx_skb[rxq->rx_curr_desc];
542 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
544 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
546 spin_unlock_irqrestore(&mp->lock, flags);
548 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
549 mp->dev->mtu + 24, DMA_FROM_DEVICE);
550 rxq->rx_desc_count--;
556 * Note that the descriptor byte count includes 2 dummy
557 * bytes automatically inserted by the hardware at the
558 * start of the packet (which we don't count), and a 4
559 * byte CRC at the end of the packet (which we do count).
562 stats->rx_bytes += rx_desc->byte_cnt - 2;
565 * In case we received a packet without first / last bits
566 * on, or the error summary bit is set, the packet needs
569 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
570 (RX_FIRST_DESC | RX_LAST_DESC))
571 || (cmd_sts & ERROR_SUMMARY)) {
574 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
575 (RX_FIRST_DESC | RX_LAST_DESC)) {
577 dev_printk(KERN_ERR, &mp->dev->dev,
578 "received packet spanning "
579 "multiple descriptors\n");
582 if (cmd_sts & ERROR_SUMMARY)
585 dev_kfree_skb_irq(skb);
588 * The -4 is for the CRC in the trailer of the
591 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
593 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
594 skb->ip_summed = CHECKSUM_UNNECESSARY;
596 (cmd_sts & 0x0007fff8) >> 3);
598 skb->protocol = eth_type_trans(skb, mp->dev);
599 #ifdef MV643XX_ETH_NAPI
600 netif_receive_skb(skb);
606 mp->dev->last_rx = jiffies;
614 #ifdef MV643XX_ETH_NAPI
615 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
617 struct mv643xx_eth_private *mp;
621 mp = container_of(napi, struct mv643xx_eth_private, napi);
623 #ifdef MV643XX_ETH_TX_FAST_REFILL
624 if (++mp->tx_clean_threshold > 5) {
625 mp->tx_clean_threshold = 0;
626 for (i = 0; i < 8; i++)
627 if (mp->txq_mask & (1 << i))
628 txq_reclaim(mp->txq + i, 0);
633 for (i = 7; rx < budget && i >= 0; i--)
634 if (mp->rxq_mask & (1 << i))
635 rx += rxq_process(mp->rxq + i, budget - rx);
638 netif_rx_complete(mp->dev, napi);
639 wrl(mp, INT_CAUSE(mp->port_num), 0);
640 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
641 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
649 /* tx ***********************************************************************/
650 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
654 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
655 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
656 if (fragp->size <= 8 && fragp->page_offset & 7)
663 static int txq_alloc_desc_index(struct tx_queue *txq)
667 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
669 tx_desc_curr = txq->tx_curr_desc;
670 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
672 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
677 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
679 int nr_frags = skb_shinfo(skb)->nr_frags;
682 for (frag = 0; frag < nr_frags; frag++) {
683 skb_frag_t *this_frag;
685 struct tx_desc *desc;
687 this_frag = &skb_shinfo(skb)->frags[frag];
688 tx_index = txq_alloc_desc_index(txq);
689 desc = &txq->tx_desc_area[tx_index];
692 * The last fragment will generate an interrupt
693 * which will free the skb on TX completion.
695 if (frag == nr_frags - 1) {
696 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
697 ZERO_PADDING | TX_LAST_DESC |
699 txq->tx_skb[tx_index] = skb;
701 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
702 txq->tx_skb[tx_index] = NULL;
706 desc->byte_cnt = this_frag->size;
707 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
708 this_frag->page_offset,
714 static inline __be16 sum16_as_be(__sum16 sum)
716 return (__force __be16)sum;
719 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
721 struct mv643xx_eth_private *mp = txq_to_mp(txq);
722 int nr_frags = skb_shinfo(skb)->nr_frags;
724 struct tx_desc *desc;
728 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
730 tx_index = txq_alloc_desc_index(txq);
731 desc = &txq->tx_desc_area[tx_index];
734 txq_submit_frag_skb(txq, skb);
736 length = skb_headlen(skb);
737 txq->tx_skb[tx_index] = NULL;
739 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
741 txq->tx_skb[tx_index] = skb;
744 desc->byte_cnt = length;
745 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
747 if (skb->ip_summed == CHECKSUM_PARTIAL) {
748 BUG_ON(skb->protocol != htons(ETH_P_IP));
750 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
752 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
754 switch (ip_hdr(skb)->protocol) {
756 cmd_sts |= UDP_FRAME;
757 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
760 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
766 /* Errata BTS #50, IHL must be 5 if no HW checksum */
767 cmd_sts |= 5 << TX_IHL_SHIFT;
771 /* ensure all other descriptors are written before first cmd_sts */
773 desc->cmd_sts = cmd_sts;
775 /* clear TX_END interrupt status */
776 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
777 rdl(mp, INT_CAUSE(mp->port_num));
779 /* ensure all descriptors are written before poking hardware */
783 txq->tx_desc_count += nr_frags + 1;
786 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
788 struct mv643xx_eth_private *mp = netdev_priv(dev);
789 struct net_device_stats *stats = &dev->stats;
790 struct tx_queue *txq;
793 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
795 dev_printk(KERN_DEBUG, &dev->dev,
796 "failed to linearize skb with tiny "
797 "unaligned fragment\n");
798 return NETDEV_TX_BUSY;
801 spin_lock_irqsave(&mp->lock, flags);
803 txq = mp->txq + mp->txq_primary;
805 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
806 spin_unlock_irqrestore(&mp->lock, flags);
807 if (txq->index == mp->txq_primary && net_ratelimit())
808 dev_printk(KERN_ERR, &dev->dev,
809 "primary tx queue full?!\n");
814 txq_submit_skb(txq, skb);
815 stats->tx_bytes += skb->len;
817 dev->trans_start = jiffies;
819 if (txq->index == mp->txq_primary) {
822 entries_left = txq->tx_ring_size - txq->tx_desc_count;
823 if (entries_left < MAX_DESCS_PER_SKB)
824 netif_stop_queue(dev);
827 spin_unlock_irqrestore(&mp->lock, flags);
833 /* tx rate control **********************************************************/
835 * Set total maximum TX rate (shared by all TX queues for this port)
836 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
838 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
844 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
845 if (token_rate > 1023)
848 mtu = (mp->dev->mtu + 255) >> 8;
852 bucket_size = (burst + 255) >> 8;
853 if (bucket_size > 65535)
856 if (mp->shared->tx_bw_control_moved) {
857 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
858 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
859 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
861 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
862 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
863 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
867 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
869 struct mv643xx_eth_private *mp = txq_to_mp(txq);
873 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
874 if (token_rate > 1023)
877 bucket_size = (burst + 255) >> 8;
878 if (bucket_size > 65535)
881 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
882 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
883 (bucket_size << 10) | token_rate);
886 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
888 struct mv643xx_eth_private *mp = txq_to_mp(txq);
893 * Turn on fixed priority mode.
895 if (mp->shared->tx_bw_control_moved)
896 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
898 off = TXQ_FIX_PRIO_CONF(mp->port_num);
901 val |= 1 << txq->index;
905 static void txq_set_wrr(struct tx_queue *txq, int weight)
907 struct mv643xx_eth_private *mp = txq_to_mp(txq);
912 * Turn off fixed priority mode.
914 if (mp->shared->tx_bw_control_moved)
915 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
917 off = TXQ_FIX_PRIO_CONF(mp->port_num);
920 val &= ~(1 << txq->index);
924 * Configure WRR weight for this queue.
926 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
929 val = (val & ~0xff) | (weight & 0xff);
934 /* mii management interface *************************************************/
935 #define SMI_BUSY 0x10000000
936 #define SMI_READ_VALID 0x08000000
937 #define SMI_OPCODE_READ 0x04000000
938 #define SMI_OPCODE_WRITE 0x00000000
940 static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
941 unsigned int reg, unsigned int *value)
943 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
947 /* the SMI register is a shared resource */
948 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
950 /* wait for the SMI register to become available */
951 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
953 printk("%s: PHY busy timeout\n", mp->dev->name);
959 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
961 /* now wait for the data to be valid */
962 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
964 printk("%s: PHY read timeout\n", mp->dev->name);
970 *value = readl(smi_reg) & 0xffff;
972 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
975 static void smi_reg_write(struct mv643xx_eth_private *mp,
977 unsigned int reg, unsigned int value)
979 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
983 /* the SMI register is a shared resource */
984 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
986 /* wait for the SMI register to become available */
987 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
989 printk("%s: PHY busy timeout\n", mp->dev->name);
995 writel(SMI_OPCODE_WRITE | (reg << 21) |
996 (addr << 16) | (value & 0xffff), smi_reg);
998 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1002 /* mib counters *************************************************************/
1003 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1005 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1008 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1012 for (i = 0; i < 0x80; i += 4)
1016 static void mib_counters_update(struct mv643xx_eth_private *mp)
1018 struct mib_counters *p = &mp->mib_counters;
1020 p->good_octets_received += mib_read(mp, 0x00);
1021 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1022 p->bad_octets_received += mib_read(mp, 0x08);
1023 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1024 p->good_frames_received += mib_read(mp, 0x10);
1025 p->bad_frames_received += mib_read(mp, 0x14);
1026 p->broadcast_frames_received += mib_read(mp, 0x18);
1027 p->multicast_frames_received += mib_read(mp, 0x1c);
1028 p->frames_64_octets += mib_read(mp, 0x20);
1029 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1030 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1031 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1032 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1033 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1034 p->good_octets_sent += mib_read(mp, 0x38);
1035 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1036 p->good_frames_sent += mib_read(mp, 0x40);
1037 p->excessive_collision += mib_read(mp, 0x44);
1038 p->multicast_frames_sent += mib_read(mp, 0x48);
1039 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1040 p->unrec_mac_control_received += mib_read(mp, 0x50);
1041 p->fc_sent += mib_read(mp, 0x54);
1042 p->good_fc_received += mib_read(mp, 0x58);
1043 p->bad_fc_received += mib_read(mp, 0x5c);
1044 p->undersize_received += mib_read(mp, 0x60);
1045 p->fragments_received += mib_read(mp, 0x64);
1046 p->oversize_received += mib_read(mp, 0x68);
1047 p->jabber_received += mib_read(mp, 0x6c);
1048 p->mac_receive_error += mib_read(mp, 0x70);
1049 p->bad_crc_event += mib_read(mp, 0x74);
1050 p->collision += mib_read(mp, 0x78);
1051 p->late_collision += mib_read(mp, 0x7c);
1055 /* ethtool ******************************************************************/
1056 struct mv643xx_eth_stats {
1057 char stat_string[ETH_GSTRING_LEN];
1064 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1065 offsetof(struct net_device, stats.m), -1 }
1067 #define MIBSTAT(m) \
1068 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1069 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1071 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1080 MIBSTAT(good_octets_received),
1081 MIBSTAT(bad_octets_received),
1082 MIBSTAT(internal_mac_transmit_err),
1083 MIBSTAT(good_frames_received),
1084 MIBSTAT(bad_frames_received),
1085 MIBSTAT(broadcast_frames_received),
1086 MIBSTAT(multicast_frames_received),
1087 MIBSTAT(frames_64_octets),
1088 MIBSTAT(frames_65_to_127_octets),
1089 MIBSTAT(frames_128_to_255_octets),
1090 MIBSTAT(frames_256_to_511_octets),
1091 MIBSTAT(frames_512_to_1023_octets),
1092 MIBSTAT(frames_1024_to_max_octets),
1093 MIBSTAT(good_octets_sent),
1094 MIBSTAT(good_frames_sent),
1095 MIBSTAT(excessive_collision),
1096 MIBSTAT(multicast_frames_sent),
1097 MIBSTAT(broadcast_frames_sent),
1098 MIBSTAT(unrec_mac_control_received),
1100 MIBSTAT(good_fc_received),
1101 MIBSTAT(bad_fc_received),
1102 MIBSTAT(undersize_received),
1103 MIBSTAT(fragments_received),
1104 MIBSTAT(oversize_received),
1105 MIBSTAT(jabber_received),
1106 MIBSTAT(mac_receive_error),
1107 MIBSTAT(bad_crc_event),
1109 MIBSTAT(late_collision),
1112 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1114 struct mv643xx_eth_private *mp = netdev_priv(dev);
1117 spin_lock_irq(&mp->lock);
1118 err = mii_ethtool_gset(&mp->mii, cmd);
1119 spin_unlock_irq(&mp->lock);
1122 * The MAC does not support 1000baseT_Half.
1124 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1125 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1130 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1132 cmd->supported = SUPPORTED_MII;
1133 cmd->advertising = ADVERTISED_MII;
1134 cmd->speed = SPEED_1000;
1135 cmd->duplex = DUPLEX_FULL;
1136 cmd->port = PORT_MII;
1137 cmd->phy_address = 0;
1138 cmd->transceiver = XCVR_INTERNAL;
1139 cmd->autoneg = AUTONEG_DISABLE;
1146 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1148 struct mv643xx_eth_private *mp = netdev_priv(dev);
1152 * The MAC does not support 1000baseT_Half.
1154 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1156 spin_lock_irq(&mp->lock);
1157 err = mii_ethtool_sset(&mp->mii, cmd);
1158 spin_unlock_irq(&mp->lock);
1163 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1168 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1169 struct ethtool_drvinfo *drvinfo)
1171 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1172 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1173 strncpy(drvinfo->fw_version, "N/A", 32);
1174 strncpy(drvinfo->bus_info, "platform", 32);
1175 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1178 static int mv643xx_eth_nway_reset(struct net_device *dev)
1180 struct mv643xx_eth_private *mp = netdev_priv(dev);
1182 return mii_nway_restart(&mp->mii);
1185 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1190 static u32 mv643xx_eth_get_link(struct net_device *dev)
1192 struct mv643xx_eth_private *mp = netdev_priv(dev);
1194 return mii_link_ok(&mp->mii);
1197 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1202 static void mv643xx_eth_get_strings(struct net_device *dev,
1203 uint32_t stringset, uint8_t *data)
1207 if (stringset == ETH_SS_STATS) {
1208 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1209 memcpy(data + i * ETH_GSTRING_LEN,
1210 mv643xx_eth_stats[i].stat_string,
1216 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1217 struct ethtool_stats *stats,
1220 struct mv643xx_eth_private *mp = dev->priv;
1223 mib_counters_update(mp);
1225 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1226 const struct mv643xx_eth_stats *stat;
1229 stat = mv643xx_eth_stats + i;
1231 if (stat->netdev_off >= 0)
1232 p = ((void *)mp->dev) + stat->netdev_off;
1234 p = ((void *)mp) + stat->mp_off;
1236 data[i] = (stat->sizeof_stat == 8) ?
1237 *(uint64_t *)p : *(uint32_t *)p;
1241 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1243 if (sset == ETH_SS_STATS)
1244 return ARRAY_SIZE(mv643xx_eth_stats);
1249 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1250 .get_settings = mv643xx_eth_get_settings,
1251 .set_settings = mv643xx_eth_set_settings,
1252 .get_drvinfo = mv643xx_eth_get_drvinfo,
1253 .nway_reset = mv643xx_eth_nway_reset,
1254 .get_link = mv643xx_eth_get_link,
1255 .set_sg = ethtool_op_set_sg,
1256 .get_strings = mv643xx_eth_get_strings,
1257 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1258 .get_sset_count = mv643xx_eth_get_sset_count,
1261 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1262 .get_settings = mv643xx_eth_get_settings_phyless,
1263 .set_settings = mv643xx_eth_set_settings_phyless,
1264 .get_drvinfo = mv643xx_eth_get_drvinfo,
1265 .nway_reset = mv643xx_eth_nway_reset_phyless,
1266 .get_link = mv643xx_eth_get_link_phyless,
1267 .set_sg = ethtool_op_set_sg,
1268 .get_strings = mv643xx_eth_get_strings,
1269 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1270 .get_sset_count = mv643xx_eth_get_sset_count,
1274 /* address handling *********************************************************/
1275 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1280 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1281 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1283 addr[0] = (mac_h >> 24) & 0xff;
1284 addr[1] = (mac_h >> 16) & 0xff;
1285 addr[2] = (mac_h >> 8) & 0xff;
1286 addr[3] = mac_h & 0xff;
1287 addr[4] = (mac_l >> 8) & 0xff;
1288 addr[5] = mac_l & 0xff;
1291 static void init_mac_tables(struct mv643xx_eth_private *mp)
1295 for (i = 0; i < 0x100; i += 4) {
1296 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1297 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1300 for (i = 0; i < 0x10; i += 4)
1301 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1304 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1305 int table, unsigned char entry)
1307 unsigned int table_reg;
1309 /* Set "accepts frame bit" at specified table entry */
1310 table_reg = rdl(mp, table + (entry & 0xfc));
1311 table_reg |= 0x01 << (8 * (entry & 3));
1312 wrl(mp, table + (entry & 0xfc), table_reg);
1315 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1321 mac_l = (addr[4] << 8) | addr[5];
1322 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1324 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1325 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1327 table = UNICAST_TABLE(mp->port_num);
1328 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1331 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1333 struct mv643xx_eth_private *mp = netdev_priv(dev);
1335 /* +2 is for the offset of the HW addr type */
1336 memcpy(dev->dev_addr, addr + 2, 6);
1338 init_mac_tables(mp);
1339 uc_addr_set(mp, dev->dev_addr);
1344 static int addr_crc(unsigned char *addr)
1349 for (i = 0; i < 6; i++) {
1352 crc = (crc ^ addr[i]) << 8;
1353 for (j = 7; j >= 0; j--) {
1354 if (crc & (0x100 << j))
1362 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1364 struct mv643xx_eth_private *mp = netdev_priv(dev);
1366 struct dev_addr_list *addr;
1369 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1370 if (dev->flags & IFF_PROMISC)
1371 port_config |= UNICAST_PROMISCUOUS_MODE;
1373 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1374 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1376 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1377 int port_num = mp->port_num;
1378 u32 accept = 0x01010101;
1380 for (i = 0; i < 0x100; i += 4) {
1381 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1382 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1387 for (i = 0; i < 0x100; i += 4) {
1388 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1389 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1392 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1393 u8 *a = addr->da_addr;
1396 if (addr->da_addrlen != 6)
1399 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1400 table = SPECIAL_MCAST_TABLE(mp->port_num);
1401 set_filter_table_entry(mp, table, a[5]);
1403 int crc = addr_crc(a);
1405 table = OTHER_MCAST_TABLE(mp->port_num);
1406 set_filter_table_entry(mp, table, crc);
1412 /* rx/tx queue initialisation ***********************************************/
1413 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1415 struct rx_queue *rxq = mp->rxq + index;
1416 struct rx_desc *rx_desc;
1422 rxq->rx_ring_size = mp->default_rx_ring_size;
1424 rxq->rx_desc_count = 0;
1425 rxq->rx_curr_desc = 0;
1426 rxq->rx_used_desc = 0;
1428 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1430 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
1431 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1432 mp->rx_desc_sram_size);
1433 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1435 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1440 if (rxq->rx_desc_area == NULL) {
1441 dev_printk(KERN_ERR, &mp->dev->dev,
1442 "can't allocate rx ring (%d bytes)\n", size);
1445 memset(rxq->rx_desc_area, 0, size);
1447 rxq->rx_desc_area_size = size;
1448 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1450 if (rxq->rx_skb == NULL) {
1451 dev_printk(KERN_ERR, &mp->dev->dev,
1452 "can't allocate rx skb ring\n");
1456 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1457 for (i = 0; i < rxq->rx_ring_size; i++) {
1458 int nexti = (i + 1) % rxq->rx_ring_size;
1459 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1460 nexti * sizeof(struct rx_desc);
1463 init_timer(&rxq->rx_oom);
1464 rxq->rx_oom.data = (unsigned long)rxq;
1465 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1471 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
1472 iounmap(rxq->rx_desc_area);
1474 dma_free_coherent(NULL, size,
1482 static void rxq_deinit(struct rx_queue *rxq)
1484 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1489 del_timer_sync(&rxq->rx_oom);
1491 for (i = 0; i < rxq->rx_ring_size; i++) {
1492 if (rxq->rx_skb[i]) {
1493 dev_kfree_skb(rxq->rx_skb[i]);
1494 rxq->rx_desc_count--;
1498 if (rxq->rx_desc_count) {
1499 dev_printk(KERN_ERR, &mp->dev->dev,
1500 "error freeing rx ring -- %d skbs stuck\n",
1501 rxq->rx_desc_count);
1504 if (rxq->index == mp->rxq_primary &&
1505 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1506 iounmap(rxq->rx_desc_area);
1508 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1509 rxq->rx_desc_area, rxq->rx_desc_dma);
1514 static int txq_init(struct mv643xx_eth_private *mp, int index)
1516 struct tx_queue *txq = mp->txq + index;
1517 struct tx_desc *tx_desc;
1523 txq->tx_ring_size = mp->default_tx_ring_size;
1525 txq->tx_desc_count = 0;
1526 txq->tx_curr_desc = 0;
1527 txq->tx_used_desc = 0;
1529 size = txq->tx_ring_size * sizeof(struct tx_desc);
1531 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
1532 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1533 mp->tx_desc_sram_size);
1534 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1536 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1541 if (txq->tx_desc_area == NULL) {
1542 dev_printk(KERN_ERR, &mp->dev->dev,
1543 "can't allocate tx ring (%d bytes)\n", size);
1546 memset(txq->tx_desc_area, 0, size);
1548 txq->tx_desc_area_size = size;
1549 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1551 if (txq->tx_skb == NULL) {
1552 dev_printk(KERN_ERR, &mp->dev->dev,
1553 "can't allocate tx skb ring\n");
1557 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1558 for (i = 0; i < txq->tx_ring_size; i++) {
1559 struct tx_desc *txd = tx_desc + i;
1560 int nexti = (i + 1) % txq->tx_ring_size;
1563 txd->next_desc_ptr = txq->tx_desc_dma +
1564 nexti * sizeof(struct tx_desc);
1571 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
1572 iounmap(txq->tx_desc_area);
1574 dma_free_coherent(NULL, size,
1582 static void txq_reclaim(struct tx_queue *txq, int force)
1584 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1585 unsigned long flags;
1587 spin_lock_irqsave(&mp->lock, flags);
1588 while (txq->tx_desc_count > 0) {
1590 struct tx_desc *desc;
1592 struct sk_buff *skb;
1596 tx_index = txq->tx_used_desc;
1597 desc = &txq->tx_desc_area[tx_index];
1598 cmd_sts = desc->cmd_sts;
1600 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1603 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1606 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1607 txq->tx_desc_count--;
1609 addr = desc->buf_ptr;
1610 count = desc->byte_cnt;
1611 skb = txq->tx_skb[tx_index];
1612 txq->tx_skb[tx_index] = NULL;
1614 if (cmd_sts & ERROR_SUMMARY) {
1615 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1616 mp->dev->stats.tx_errors++;
1620 * Drop mp->lock while we free the skb.
1622 spin_unlock_irqrestore(&mp->lock, flags);
1624 if (cmd_sts & TX_FIRST_DESC)
1625 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1627 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1630 dev_kfree_skb_irq(skb);
1632 spin_lock_irqsave(&mp->lock, flags);
1634 spin_unlock_irqrestore(&mp->lock, flags);
1637 static void txq_deinit(struct tx_queue *txq)
1639 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1642 txq_reclaim(txq, 1);
1644 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1646 if (txq->index == mp->txq_primary &&
1647 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1648 iounmap(txq->tx_desc_area);
1650 dma_free_coherent(NULL, txq->tx_desc_area_size,
1651 txq->tx_desc_area, txq->tx_desc_dma);
1657 /* netdev ops and related ***************************************************/
1658 static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
1663 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1665 /* clear speed, duplex and rx buffer size fields */
1666 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1667 SET_GMII_SPEED_TO_1000 |
1668 SET_FULL_DUPLEX_MODE |
1669 MAX_RX_PACKET_MASK);
1671 if (speed == SPEED_1000) {
1672 pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
1674 if (speed == SPEED_100)
1675 pscr_n |= SET_MII_SPEED_TO_100;
1676 pscr_n |= MAX_RX_PACKET_1522BYTE;
1679 if (duplex == DUPLEX_FULL)
1680 pscr_n |= SET_FULL_DUPLEX_MODE;
1682 if (pscr_n != pscr_o) {
1683 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1684 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1688 for (i = 0; i < 8; i++)
1689 if (mp->txq_mask & (1 << i))
1690 txq_disable(mp->txq + i);
1692 pscr_o &= ~SERIAL_PORT_ENABLE;
1693 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1694 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1695 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1697 for (i = 0; i < 8; i++)
1698 if (mp->txq_mask & (1 << i))
1699 txq_enable(mp->txq + i);
1704 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1706 struct net_device *dev = (struct net_device *)dev_id;
1707 struct mv643xx_eth_private *mp = netdev_priv(dev);
1711 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1712 (INT_TX_END | INT_RX | INT_EXT);
1717 if (int_cause & INT_EXT) {
1718 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1719 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1720 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1723 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
1724 if (mp->phy_addr == -1 || mii_link_ok(&mp->mii)) {
1725 if (mp->phy_addr != -1) {
1726 struct ethtool_cmd cmd;
1728 mii_ethtool_gset(&mp->mii, &cmd);
1729 update_pscr(mp, cmd.speed, cmd.duplex);
1732 if (!netif_carrier_ok(dev)) {
1733 netif_carrier_on(dev);
1734 netif_wake_queue(dev);
1736 } else if (netif_carrier_ok(dev)) {
1739 netif_stop_queue(dev);
1740 netif_carrier_off(dev);
1742 for (i = 0; i < 8; i++) {
1743 struct tx_queue *txq = mp->txq + i;
1745 if (mp->txq_mask & (1 << i)) {
1746 txq_reclaim(txq, 1);
1747 txq_reset_hw_ptr(txq);
1754 * RxBuffer or RxError set for any of the 8 queues?
1756 #ifdef MV643XX_ETH_NAPI
1757 if (int_cause & INT_RX) {
1758 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1759 rdl(mp, INT_MASK(mp->port_num));
1761 netif_rx_schedule(dev, &mp->napi);
1764 if (int_cause & INT_RX) {
1767 for (i = 7; i >= 0; i--)
1768 if (mp->rxq_mask & (1 << i))
1769 rxq_process(mp->rxq + i, INT_MAX);
1774 * TxBuffer or TxError set for any of the 8 queues?
1776 if (int_cause_ext & INT_EXT_TX) {
1779 for (i = 0; i < 8; i++)
1780 if (mp->txq_mask & (1 << i))
1781 txq_reclaim(mp->txq + i, 0);
1784 * Enough space again in the primary TX queue for a
1787 if (netif_carrier_ok(dev)) {
1788 spin_lock(&mp->lock);
1789 __txq_maybe_wake(mp->txq + mp->txq_primary);
1790 spin_unlock(&mp->lock);
1795 * Any TxEnd interrupts?
1797 if (int_cause & INT_TX_END) {
1800 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1802 spin_lock(&mp->lock);
1803 for (i = 0; i < 8; i++) {
1804 struct tx_queue *txq = mp->txq + i;
1808 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1812 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1813 expected_ptr = (u32)txq->tx_desc_dma +
1814 txq->tx_curr_desc * sizeof(struct tx_desc);
1816 if (hw_desc_ptr != expected_ptr)
1819 spin_unlock(&mp->lock);
1825 static void phy_reset(struct mv643xx_eth_private *mp)
1829 smi_reg_read(mp, mp->phy_addr, 0, &data);
1831 smi_reg_write(mp, mp->phy_addr, 0, data);
1835 smi_reg_read(mp, mp->phy_addr, 0, &data);
1836 } while (data & 0x8000);
1839 static void port_start(struct mv643xx_eth_private *mp)
1845 * Configure basic link parameters.
1847 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1848 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1849 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1850 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1851 DISABLE_AUTO_NEG_SPEED_GMII |
1852 DISABLE_AUTO_NEG_FOR_DUPLEX |
1853 DO_NOT_FORCE_LINK_FAIL |
1854 SERIAL_PORT_CONTROL_RESERVED;
1855 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1856 pscr |= SERIAL_PORT_ENABLE;
1857 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1859 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1862 * Perform PHY reset, if there is a PHY.
1864 if (mp->phy_addr != -1) {
1865 struct ethtool_cmd cmd;
1867 mv643xx_eth_get_settings(mp->dev, &cmd);
1869 mv643xx_eth_set_settings(mp->dev, &cmd);
1873 * Configure TX path and queues.
1875 tx_set_rate(mp, 1000000000, 16777216);
1876 for (i = 0; i < 8; i++) {
1877 struct tx_queue *txq = mp->txq + i;
1879 if ((mp->txq_mask & (1 << i)) == 0)
1882 txq_reset_hw_ptr(txq);
1883 txq_set_rate(txq, 1000000000, 16777216);
1884 txq_set_fixed_prio_mode(txq);
1888 * Add configured unicast address to address filter table.
1890 uc_addr_set(mp, mp->dev->dev_addr);
1893 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1894 * frames to RX queue #0.
1896 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1899 * Treat BPDUs as normal multicasts, and disable partition mode.
1901 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1904 * Enable the receive queues.
1906 for (i = 0; i < 8; i++) {
1907 struct rx_queue *rxq = mp->rxq + i;
1908 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
1911 if ((mp->rxq_mask & (1 << i)) == 0)
1914 addr = (u32)rxq->rx_desc_dma;
1915 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1922 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1924 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1927 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1928 if (mp->shared->extended_rx_coal_limit) {
1932 val |= (coal & 0x8000) << 10;
1933 val |= (coal & 0x7fff) << 7;
1938 val |= (coal & 0x3fff) << 8;
1940 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1943 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1945 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1949 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
1952 static int mv643xx_eth_open(struct net_device *dev)
1954 struct mv643xx_eth_private *mp = netdev_priv(dev);
1958 wrl(mp, INT_CAUSE(mp->port_num), 0);
1959 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1960 rdl(mp, INT_CAUSE_EXT(mp->port_num));
1962 err = request_irq(dev->irq, mv643xx_eth_irq,
1963 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1966 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
1970 init_mac_tables(mp);
1972 for (i = 0; i < 8; i++) {
1973 if ((mp->rxq_mask & (1 << i)) == 0)
1976 err = rxq_init(mp, i);
1979 if (mp->rxq_mask & (1 << i))
1980 rxq_deinit(mp->rxq + i);
1984 rxq_refill(mp->rxq + i);
1987 for (i = 0; i < 8; i++) {
1988 if ((mp->txq_mask & (1 << i)) == 0)
1991 err = txq_init(mp, i);
1994 if (mp->txq_mask & (1 << i))
1995 txq_deinit(mp->txq + i);
2000 #ifdef MV643XX_ETH_NAPI
2001 napi_enable(&mp->napi);
2009 wrl(mp, INT_MASK_EXT(mp->port_num),
2010 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
2012 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2018 for (i = 0; i < 8; i++)
2019 if (mp->rxq_mask & (1 << i))
2020 rxq_deinit(mp->rxq + i);
2022 free_irq(dev->irq, dev);
2027 static void port_reset(struct mv643xx_eth_private *mp)
2032 for (i = 0; i < 8; i++) {
2033 if (mp->rxq_mask & (1 << i))
2034 rxq_disable(mp->rxq + i);
2035 if (mp->txq_mask & (1 << i))
2036 txq_disable(mp->txq + i);
2038 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
2041 /* Reset the Enable bit in the Configuration Register */
2042 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2043 data &= ~(SERIAL_PORT_ENABLE |
2044 DO_NOT_FORCE_LINK_FAIL |
2046 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2049 static int mv643xx_eth_stop(struct net_device *dev)
2051 struct mv643xx_eth_private *mp = netdev_priv(dev);
2054 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2055 rdl(mp, INT_MASK(mp->port_num));
2057 #ifdef MV643XX_ETH_NAPI
2058 napi_disable(&mp->napi);
2060 netif_carrier_off(dev);
2061 netif_stop_queue(dev);
2063 free_irq(dev->irq, dev);
2066 mib_counters_update(mp);
2068 for (i = 0; i < 8; i++) {
2069 if (mp->rxq_mask & (1 << i))
2070 rxq_deinit(mp->rxq + i);
2071 if (mp->txq_mask & (1 << i))
2072 txq_deinit(mp->txq + i);
2078 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2080 struct mv643xx_eth_private *mp = netdev_priv(dev);
2082 if (mp->phy_addr != -1)
2083 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2088 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2090 struct mv643xx_eth_private *mp = netdev_priv(dev);
2092 if (new_mtu < 64 || new_mtu > 9500)
2096 tx_set_rate(mp, 1000000000, 16777216);
2098 if (!netif_running(dev))
2102 * Stop and then re-open the interface. This will allocate RX
2103 * skbs of the new MTU.
2104 * There is a possible danger that the open will not succeed,
2105 * due to memory being full.
2107 mv643xx_eth_stop(dev);
2108 if (mv643xx_eth_open(dev)) {
2109 dev_printk(KERN_ERR, &dev->dev,
2110 "fatal error on re-opening device after "
2117 static void tx_timeout_task(struct work_struct *ugly)
2119 struct mv643xx_eth_private *mp;
2121 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2122 if (netif_running(mp->dev)) {
2123 netif_stop_queue(mp->dev);
2128 __txq_maybe_wake(mp->txq + mp->txq_primary);
2132 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2134 struct mv643xx_eth_private *mp = netdev_priv(dev);
2136 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2138 schedule_work(&mp->tx_timeout_task);
2141 #ifdef CONFIG_NET_POLL_CONTROLLER
2142 static void mv643xx_eth_netpoll(struct net_device *dev)
2144 struct mv643xx_eth_private *mp = netdev_priv(dev);
2146 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2147 rdl(mp, INT_MASK(mp->port_num));
2149 mv643xx_eth_irq(dev->irq, dev);
2151 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2155 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2157 struct mv643xx_eth_private *mp = netdev_priv(dev);
2160 smi_reg_read(mp, addr, reg, &val);
2165 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2167 struct mv643xx_eth_private *mp = netdev_priv(dev);
2168 smi_reg_write(mp, addr, reg, val);
2172 /* platform glue ************************************************************/
2174 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2175 struct mbus_dram_target_info *dram)
2177 void __iomem *base = msp->base;
2182 for (i = 0; i < 6; i++) {
2183 writel(0, base + WINDOW_BASE(i));
2184 writel(0, base + WINDOW_SIZE(i));
2186 writel(0, base + WINDOW_REMAP_HIGH(i));
2192 for (i = 0; i < dram->num_cs; i++) {
2193 struct mbus_dram_window *cs = dram->cs + i;
2195 writel((cs->base & 0xffff0000) |
2196 (cs->mbus_attr << 8) |
2197 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2198 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2200 win_enable &= ~(1 << i);
2201 win_protect |= 3 << (2 * i);
2204 writel(win_enable, base + WINDOW_BAR_ENABLE);
2205 msp->win_protect = win_protect;
2208 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2211 * Check whether we have a 14-bit coal limit field in bits
2212 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2213 * SDMA config register.
2215 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2216 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2217 msp->extended_rx_coal_limit = 1;
2219 msp->extended_rx_coal_limit = 0;
2222 * Check whether the TX rate control registers are in the
2223 * old or the new place.
2225 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2226 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2227 msp->tx_bw_control_moved = 1;
2229 msp->tx_bw_control_moved = 0;
2232 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2234 static int mv643xx_eth_version_printed = 0;
2235 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2236 struct mv643xx_eth_shared_private *msp;
2237 struct resource *res;
2240 if (!mv643xx_eth_version_printed++)
2241 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2244 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2249 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2252 memset(msp, 0, sizeof(*msp));
2254 msp->base = ioremap(res->start, res->end - res->start + 1);
2255 if (msp->base == NULL)
2258 spin_lock_init(&msp->phy_lock);
2261 * (Re-)program MBUS remapping windows if we are asked to.
2263 if (pd != NULL && pd->dram != NULL)
2264 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2267 * Detect hardware parameters.
2269 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2270 infer_hw_params(msp);
2272 platform_set_drvdata(pdev, msp);
2282 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2284 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2292 static struct platform_driver mv643xx_eth_shared_driver = {
2293 .probe = mv643xx_eth_shared_probe,
2294 .remove = mv643xx_eth_shared_remove,
2296 .name = MV643XX_ETH_SHARED_NAME,
2297 .owner = THIS_MODULE,
2301 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2303 int addr_shift = 5 * mp->port_num;
2306 data = rdl(mp, PHY_ADDR);
2307 data &= ~(0x1f << addr_shift);
2308 data |= (phy_addr & 0x1f) << addr_shift;
2309 wrl(mp, PHY_ADDR, data);
2312 static int phy_addr_get(struct mv643xx_eth_private *mp)
2316 data = rdl(mp, PHY_ADDR);
2318 return (data >> (5 * mp->port_num)) & 0x1f;
2321 static void set_params(struct mv643xx_eth_private *mp,
2322 struct mv643xx_eth_platform_data *pd)
2324 struct net_device *dev = mp->dev;
2326 if (is_valid_ether_addr(pd->mac_addr))
2327 memcpy(dev->dev_addr, pd->mac_addr, 6);
2329 uc_addr_get(mp, dev->dev_addr);
2331 if (pd->phy_addr == -1) {
2332 mp->shared_smi = NULL;
2335 mp->shared_smi = mp->shared;
2336 if (pd->shared_smi != NULL)
2337 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2339 if (pd->force_phy_addr || pd->phy_addr) {
2340 mp->phy_addr = pd->phy_addr & 0x3f;
2341 phy_addr_set(mp, mp->phy_addr);
2343 mp->phy_addr = phy_addr_get(mp);
2347 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2348 if (pd->rx_queue_size)
2349 mp->default_rx_ring_size = pd->rx_queue_size;
2350 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2351 mp->rx_desc_sram_size = pd->rx_sram_size;
2353 if (pd->rx_queue_mask)
2354 mp->rxq_mask = pd->rx_queue_mask;
2356 mp->rxq_mask = 0x01;
2357 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2359 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2360 if (pd->tx_queue_size)
2361 mp->default_tx_ring_size = pd->tx_queue_size;
2362 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2363 mp->tx_desc_sram_size = pd->tx_sram_size;
2365 if (pd->tx_queue_mask)
2366 mp->txq_mask = pd->tx_queue_mask;
2368 mp->txq_mask = 0x01;
2369 mp->txq_primary = fls(mp->txq_mask) - 1;
2372 static int phy_detect(struct mv643xx_eth_private *mp)
2377 smi_reg_read(mp, mp->phy_addr, 0, &data);
2378 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
2380 smi_reg_read(mp, mp->phy_addr, 0, &data2);
2381 if (((data ^ data2) & 0x1000) == 0)
2384 smi_reg_write(mp, mp->phy_addr, 0, data);
2389 static int phy_init(struct mv643xx_eth_private *mp,
2390 struct mv643xx_eth_platform_data *pd)
2392 struct ethtool_cmd cmd;
2395 err = phy_detect(mp);
2397 dev_printk(KERN_INFO, &mp->dev->dev,
2398 "no PHY detected at addr %d\n", mp->phy_addr);
2403 mp->mii.phy_id = mp->phy_addr;
2404 mp->mii.phy_id_mask = 0x3f;
2405 mp->mii.reg_num_mask = 0x1f;
2406 mp->mii.dev = mp->dev;
2407 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2408 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2410 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2412 memset(&cmd, 0, sizeof(cmd));
2414 cmd.port = PORT_MII;
2415 cmd.transceiver = XCVR_INTERNAL;
2416 cmd.phy_address = mp->phy_addr;
2417 if (pd->speed == 0) {
2418 cmd.autoneg = AUTONEG_ENABLE;
2419 cmd.speed = SPEED_100;
2420 cmd.advertising = ADVERTISED_10baseT_Half |
2421 ADVERTISED_10baseT_Full |
2422 ADVERTISED_100baseT_Half |
2423 ADVERTISED_100baseT_Full;
2424 if (mp->mii.supports_gmii)
2425 cmd.advertising |= ADVERTISED_1000baseT_Full;
2427 cmd.autoneg = AUTONEG_DISABLE;
2428 cmd.speed = pd->speed;
2429 cmd.duplex = pd->duplex;
2432 update_pscr(mp, cmd.speed, cmd.duplex);
2433 mv643xx_eth_set_settings(mp->dev, &cmd);
2438 static int mv643xx_eth_probe(struct platform_device *pdev)
2440 struct mv643xx_eth_platform_data *pd;
2441 struct mv643xx_eth_private *mp;
2442 struct net_device *dev;
2443 struct resource *res;
2444 DECLARE_MAC_BUF(mac);
2447 pd = pdev->dev.platform_data;
2449 dev_printk(KERN_ERR, &pdev->dev,
2450 "no mv643xx_eth_platform_data\n");
2454 if (pd->shared == NULL) {
2455 dev_printk(KERN_ERR, &pdev->dev,
2456 "no mv643xx_eth_platform_data->shared\n");
2460 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2464 mp = netdev_priv(dev);
2465 platform_set_drvdata(pdev, mp);
2467 mp->shared = platform_get_drvdata(pd->shared);
2468 mp->port_num = pd->port_number;
2471 #ifdef MV643XX_ETH_NAPI
2472 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2477 spin_lock_init(&mp->lock);
2479 mib_counters_clear(mp);
2480 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2482 if (mp->phy_addr != -1) {
2483 err = phy_init(mp, pd);
2487 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2489 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2493 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2495 dev->irq = res->start;
2497 dev->hard_start_xmit = mv643xx_eth_xmit;
2498 dev->open = mv643xx_eth_open;
2499 dev->stop = mv643xx_eth_stop;
2500 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2501 dev->set_mac_address = mv643xx_eth_set_mac_address;
2502 dev->do_ioctl = mv643xx_eth_ioctl;
2503 dev->change_mtu = mv643xx_eth_change_mtu;
2504 dev->tx_timeout = mv643xx_eth_tx_timeout;
2505 #ifdef CONFIG_NET_POLL_CONTROLLER
2506 dev->poll_controller = mv643xx_eth_netpoll;
2508 dev->watchdog_timeo = 2 * HZ;
2511 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2513 * Zero copy can only work if we use Discovery II memory. Else, we will
2514 * have to map the buffers to ISA memory which is only 16 MB
2516 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2519 SET_NETDEV_DEV(dev, &pdev->dev);
2521 if (mp->shared->win_protect)
2522 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2524 err = register_netdev(dev);
2528 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2529 mp->port_num, print_mac(mac, dev->dev_addr));
2531 if (dev->features & NETIF_F_SG)
2532 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
2534 if (dev->features & NETIF_F_IP_CSUM)
2535 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
2537 #ifdef MV643XX_ETH_NAPI
2538 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
2541 if (mp->tx_desc_sram_size > 0)
2542 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2552 static int mv643xx_eth_remove(struct platform_device *pdev)
2554 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2556 unregister_netdev(mp->dev);
2557 flush_scheduled_work();
2558 free_netdev(mp->dev);
2560 platform_set_drvdata(pdev, NULL);
2565 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2567 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2569 /* Mask all interrupts on ethernet port */
2570 wrl(mp, INT_MASK(mp->port_num), 0);
2571 rdl(mp, INT_MASK(mp->port_num));
2573 if (netif_running(mp->dev))
2577 static struct platform_driver mv643xx_eth_driver = {
2578 .probe = mv643xx_eth_probe,
2579 .remove = mv643xx_eth_remove,
2580 .shutdown = mv643xx_eth_shutdown,
2582 .name = MV643XX_ETH_NAME,
2583 .owner = THIS_MODULE,
2587 static int __init mv643xx_eth_init_module(void)
2591 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2593 rc = platform_driver_register(&mv643xx_eth_driver);
2595 platform_driver_unregister(&mv643xx_eth_shared_driver);
2600 module_init(mv643xx_eth_init_module);
2602 static void __exit mv643xx_eth_cleanup_module(void)
2604 platform_driver_unregister(&mv643xx_eth_driver);
2605 platform_driver_unregister(&mv643xx_eth_shared_driver);
2607 module_exit(mv643xx_eth_cleanup_module);
2609 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2610 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2611 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2612 MODULE_LICENSE("GPL");
2613 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2614 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);