2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.3";
62 * Registers shared between all ports.
64 #define PHY_ADDR 0x0000
65 #define SMI_REG 0x0004
66 #define SMI_BUSY 0x10000000
67 #define SMI_READ_VALID 0x08000000
68 #define SMI_OPCODE_READ 0x04000000
69 #define SMI_OPCODE_WRITE 0x00000000
70 #define ERR_INT_CAUSE 0x0080
71 #define ERR_INT_SMI_DONE 0x00000010
72 #define ERR_INT_MASK 0x0084
73 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
74 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
75 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
76 #define WINDOW_BAR_ENABLE 0x0290
77 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
82 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
83 #define UNICAST_PROMISCUOUS_MODE 0x00000001
84 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
85 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
86 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
87 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
88 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
89 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
90 #define TX_FIFO_EMPTY 0x00000400
91 #define TX_IN_PROGRESS 0x00000080
92 #define PORT_SPEED_MASK 0x00000030
93 #define PORT_SPEED_1000 0x00000010
94 #define PORT_SPEED_100 0x00000020
95 #define PORT_SPEED_10 0x00000000
96 #define FLOW_CONTROL_ENABLED 0x00000008
97 #define FULL_DUPLEX 0x00000004
98 #define LINK_UP 0x00000002
99 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
100 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
101 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
102 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
103 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
104 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
105 #define INT_TX_END 0x07f80000
106 #define INT_RX 0x000003fc
107 #define INT_EXT 0x00000002
108 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
109 #define INT_EXT_LINK_PHY 0x00110000
110 #define INT_EXT_TX 0x000000ff
111 #define INT_MASK(p) (0x0468 + ((p) << 10))
112 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
113 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
114 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
115 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
116 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
117 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
118 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
119 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
120 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
121 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
122 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
123 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
124 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
125 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
126 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
127 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
131 * SDMA configuration register.
133 #define RX_BURST_SIZE_16_64BIT (4 << 1)
134 #define BLM_RX_NO_SWAP (1 << 4)
135 #define BLM_TX_NO_SWAP (1 << 5)
136 #define TX_BURST_SIZE_16_64BIT (4 << 22)
138 #if defined(__BIG_ENDIAN)
139 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
140 RX_BURST_SIZE_16_64BIT | \
141 TX_BURST_SIZE_16_64BIT
142 #elif defined(__LITTLE_ENDIAN)
143 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
144 RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT
149 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
154 * Port serial control register.
156 #define SET_MII_SPEED_TO_100 (1 << 24)
157 #define SET_GMII_SPEED_TO_1000 (1 << 23)
158 #define SET_FULL_DUPLEX_MODE (1 << 21)
159 #define MAX_RX_PACKET_9700BYTE (5 << 17)
160 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
161 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
162 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
163 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
164 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
165 #define FORCE_LINK_PASS (1 << 1)
166 #define SERIAL_PORT_ENABLE (1 << 0)
168 #define DEFAULT_RX_QUEUE_SIZE 400
169 #define DEFAULT_TX_QUEUE_SIZE 800
175 #if defined(__BIG_ENDIAN)
177 u16 byte_cnt; /* Descriptor buffer byte count */
178 u16 buf_size; /* Buffer size */
179 u32 cmd_sts; /* Descriptor command status */
180 u32 next_desc_ptr; /* Next descriptor pointer */
181 u32 buf_ptr; /* Descriptor buffer pointer */
185 u16 byte_cnt; /* buffer byte count */
186 u16 l4i_chk; /* CPU provided TCP checksum */
187 u32 cmd_sts; /* Command/status field */
188 u32 next_desc_ptr; /* Pointer to next descriptor */
189 u32 buf_ptr; /* pointer to buffer for this descriptor*/
191 #elif defined(__LITTLE_ENDIAN)
193 u32 cmd_sts; /* Descriptor command status */
194 u16 buf_size; /* Buffer size */
195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 u32 next_desc_ptr; /* Next descriptor pointer */
201 u32 cmd_sts; /* Command/status field */
202 u16 l4i_chk; /* CPU provided TCP checksum */
203 u16 byte_cnt; /* buffer byte count */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 u32 next_desc_ptr; /* Pointer to next descriptor */
208 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
211 /* RX & TX descriptor command */
212 #define BUFFER_OWNED_BY_DMA 0x80000000
214 /* RX & TX descriptor status */
215 #define ERROR_SUMMARY 0x00000001
217 /* RX descriptor status */
218 #define LAYER_4_CHECKSUM_OK 0x40000000
219 #define RX_ENABLE_INTERRUPT 0x20000000
220 #define RX_FIRST_DESC 0x08000000
221 #define RX_LAST_DESC 0x04000000
223 /* TX descriptor command */
224 #define TX_ENABLE_INTERRUPT 0x00800000
225 #define GEN_CRC 0x00400000
226 #define TX_FIRST_DESC 0x00200000
227 #define TX_LAST_DESC 0x00100000
228 #define ZERO_PADDING 0x00080000
229 #define GEN_IP_V4_CHECKSUM 0x00040000
230 #define GEN_TCP_UDP_CHECKSUM 0x00020000
231 #define UDP_FRAME 0x00010000
232 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
233 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
235 #define TX_IHL_SHIFT 11
238 /* global *******************************************************************/
239 struct mv643xx_eth_shared_private {
241 * Ethernet controller base address.
246 * Points at the right SMI instance to use.
248 struct mv643xx_eth_shared_private *smi;
251 * Protects access to SMI_REG, which is shared between ports.
253 struct mutex phy_lock;
256 * If we have access to the error interrupt pin (which is
257 * somewhat misnamed as it not only reflects internal errors
258 * but also reflects SMI completion), use that to wait for
259 * SMI access completion instead of polling the SMI busy bit.
262 wait_queue_head_t smi_busy_wait;
265 * Per-port MBUS window access register value.
270 * Hardware-specific parameters.
273 int extended_rx_coal_limit;
274 int tx_bw_control_moved;
278 /* per-port *****************************************************************/
279 struct mib_counters {
280 u64 good_octets_received;
281 u32 bad_octets_received;
282 u32 internal_mac_transmit_err;
283 u32 good_frames_received;
284 u32 bad_frames_received;
285 u32 broadcast_frames_received;
286 u32 multicast_frames_received;
287 u32 frames_64_octets;
288 u32 frames_65_to_127_octets;
289 u32 frames_128_to_255_octets;
290 u32 frames_256_to_511_octets;
291 u32 frames_512_to_1023_octets;
292 u32 frames_1024_to_max_octets;
293 u64 good_octets_sent;
294 u32 good_frames_sent;
295 u32 excessive_collision;
296 u32 multicast_frames_sent;
297 u32 broadcast_frames_sent;
298 u32 unrec_mac_control_received;
300 u32 good_fc_received;
302 u32 undersize_received;
303 u32 fragments_received;
304 u32 oversize_received;
306 u32 mac_receive_error;
321 struct rx_desc *rx_desc_area;
322 dma_addr_t rx_desc_dma;
323 int rx_desc_area_size;
324 struct sk_buff **rx_skb;
336 struct tx_desc *tx_desc_area;
337 dma_addr_t tx_desc_dma;
338 int tx_desc_area_size;
339 struct sk_buff **tx_skb;
341 unsigned long tx_packets;
342 unsigned long tx_bytes;
343 unsigned long tx_dropped;
346 struct mv643xx_eth_private {
347 struct mv643xx_eth_shared_private *shared;
350 struct net_device *dev;
354 struct mib_counters mib_counters;
355 struct work_struct tx_timeout_task;
356 struct mii_if_info mii;
358 struct napi_struct napi;
369 int default_rx_ring_size;
370 unsigned long rx_desc_sram_addr;
371 int rx_desc_sram_size;
373 struct timer_list rx_oom;
374 struct rx_queue rxq[8];
379 int default_tx_ring_size;
380 unsigned long tx_desc_sram_addr;
381 int tx_desc_sram_size;
383 struct tx_queue txq[8];
387 /* port register accessors **************************************************/
388 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
390 return readl(mp->shared->base + offset);
393 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
395 writel(data, mp->shared->base + offset);
399 /* rxq/txq helper functions *************************************************/
400 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
402 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
405 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
407 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
410 static void rxq_enable(struct rx_queue *rxq)
412 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
413 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
416 static void rxq_disable(struct rx_queue *rxq)
418 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
419 u8 mask = 1 << rxq->index;
421 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
422 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
426 static void txq_reset_hw_ptr(struct tx_queue *txq)
428 struct mv643xx_eth_private *mp = txq_to_mp(txq);
429 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
432 addr = (u32)txq->tx_desc_dma;
433 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
437 static void txq_enable(struct tx_queue *txq)
439 struct mv643xx_eth_private *mp = txq_to_mp(txq);
440 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
443 static void txq_disable(struct tx_queue *txq)
445 struct mv643xx_eth_private *mp = txq_to_mp(txq);
446 u8 mask = 1 << txq->index;
448 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
449 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
453 static void txq_maybe_wake(struct tx_queue *txq)
455 struct mv643xx_eth_private *mp = txq_to_mp(txq);
456 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
458 if (netif_tx_queue_stopped(nq)) {
459 __netif_tx_lock(nq, smp_processor_id());
460 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
461 netif_tx_wake_queue(nq);
462 __netif_tx_unlock(nq);
467 /* rx napi ******************************************************************/
468 static int rxq_process(struct rx_queue *rxq, int budget)
470 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
471 struct net_device_stats *stats = &mp->dev->stats;
475 while (rx < budget && rxq->rx_desc_count) {
476 struct rx_desc *rx_desc;
477 unsigned int cmd_sts;
480 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
482 cmd_sts = rx_desc->cmd_sts;
483 if (cmd_sts & BUFFER_OWNED_BY_DMA)
487 skb = rxq->rx_skb[rxq->rx_curr_desc];
488 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
491 if (rxq->rx_curr_desc == rxq->rx_ring_size)
492 rxq->rx_curr_desc = 0;
494 dma_unmap_single(NULL, rx_desc->buf_ptr,
495 rx_desc->buf_size, DMA_FROM_DEVICE);
496 rxq->rx_desc_count--;
499 mp->work_rx_refill |= 1 << rxq->index;
504 * Note that the descriptor byte count includes 2 dummy
505 * bytes automatically inserted by the hardware at the
506 * start of the packet (which we don't count), and a 4
507 * byte CRC at the end of the packet (which we do count).
510 stats->rx_bytes += rx_desc->byte_cnt - 2;
513 * In case we received a packet without first / last bits
514 * on, or the error summary bit is set, the packet needs
517 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
518 (RX_FIRST_DESC | RX_LAST_DESC))
519 || (cmd_sts & ERROR_SUMMARY)) {
522 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
523 (RX_FIRST_DESC | RX_LAST_DESC)) {
525 dev_printk(KERN_ERR, &mp->dev->dev,
526 "received packet spanning "
527 "multiple descriptors\n");
530 if (cmd_sts & ERROR_SUMMARY)
536 * The -4 is for the CRC in the trailer of the
539 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
541 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
542 skb->ip_summed = CHECKSUM_UNNECESSARY;
544 (cmd_sts & 0x0007fff8) >> 3);
546 skb->protocol = eth_type_trans(skb, mp->dev);
547 netif_receive_skb(skb);
550 mp->dev->last_rx = jiffies;
554 mp->work_rx &= ~(1 << rxq->index);
559 static int rxq_refill(struct rx_queue *rxq, int budget)
561 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
566 * Reserve 2+14 bytes for an ethernet header (the hardware
567 * automatically prepends 2 bytes of dummy data to each
568 * received packet), 16 bytes for up to four VLAN tags, and
569 * 4 bytes for the trailing FCS -- 36 bytes total.
571 skb_size = rxq_to_mp(rxq)->dev->mtu + 36;
574 * Make sure that the skb size is a multiple of 8 bytes, as
575 * the lower three bits of the receive descriptor's buffer
576 * size field are ignored by the hardware.
578 skb_size = (skb_size + 7) & ~7;
581 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
586 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
588 mp->work_rx_oom |= 1 << rxq->index;
592 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
594 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
597 rxq->rx_desc_count++;
599 rx = rxq->rx_used_desc++;
600 if (rxq->rx_used_desc == rxq->rx_ring_size)
601 rxq->rx_used_desc = 0;
603 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
604 skb_size, DMA_FROM_DEVICE);
605 rxq->rx_desc_area[rx].buf_size = skb_size;
606 rxq->rx_skb[rx] = skb;
608 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
613 * The hardware automatically prepends 2 bytes of
614 * dummy data to each received packet, so that the
615 * IP header ends up 16-byte aligned.
620 if (refilled < budget)
621 mp->work_rx_refill &= ~(1 << rxq->index);
628 /* tx ***********************************************************************/
629 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
633 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
634 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
635 if (fragp->size <= 8 && fragp->page_offset & 7)
642 static int txq_alloc_desc_index(struct tx_queue *txq)
646 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
648 tx_desc_curr = txq->tx_curr_desc++;
649 if (txq->tx_curr_desc == txq->tx_ring_size)
650 txq->tx_curr_desc = 0;
652 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
657 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
659 int nr_frags = skb_shinfo(skb)->nr_frags;
662 for (frag = 0; frag < nr_frags; frag++) {
663 skb_frag_t *this_frag;
665 struct tx_desc *desc;
667 this_frag = &skb_shinfo(skb)->frags[frag];
668 tx_index = txq_alloc_desc_index(txq);
669 desc = &txq->tx_desc_area[tx_index];
672 * The last fragment will generate an interrupt
673 * which will free the skb on TX completion.
675 if (frag == nr_frags - 1) {
676 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
677 ZERO_PADDING | TX_LAST_DESC |
679 txq->tx_skb[tx_index] = skb;
681 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
682 txq->tx_skb[tx_index] = NULL;
686 desc->byte_cnt = this_frag->size;
687 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
688 this_frag->page_offset,
694 static inline __be16 sum16_as_be(__sum16 sum)
696 return (__force __be16)sum;
699 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
701 struct mv643xx_eth_private *mp = txq_to_mp(txq);
702 int nr_frags = skb_shinfo(skb)->nr_frags;
704 struct tx_desc *desc;
708 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
710 tx_index = txq_alloc_desc_index(txq);
711 desc = &txq->tx_desc_area[tx_index];
714 txq_submit_frag_skb(txq, skb);
716 length = skb_headlen(skb);
717 txq->tx_skb[tx_index] = NULL;
719 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
721 txq->tx_skb[tx_index] = skb;
724 desc->byte_cnt = length;
725 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
727 if (skb->ip_summed == CHECKSUM_PARTIAL) {
730 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
731 skb->protocol != htons(ETH_P_8021Q));
733 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
735 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
737 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
738 switch (mac_hdr_len - ETH_HLEN) {
742 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
745 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
748 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
749 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
753 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
754 "mac header length is %d?!\n", mac_hdr_len);
758 switch (ip_hdr(skb)->protocol) {
760 cmd_sts |= UDP_FRAME;
761 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
764 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
770 /* Errata BTS #50, IHL must be 5 if no HW checksum */
771 cmd_sts |= 5 << TX_IHL_SHIFT;
775 /* ensure all other descriptors are written before first cmd_sts */
777 desc->cmd_sts = cmd_sts;
779 /* clear TX_END status */
780 mp->work_tx_end &= ~(1 << txq->index);
782 /* ensure all descriptors are written before poking hardware */
786 txq->tx_desc_count += nr_frags + 1;
789 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
791 struct mv643xx_eth_private *mp = netdev_priv(dev);
793 struct tx_queue *txq;
794 struct netdev_queue *nq;
797 queue = skb_get_queue_mapping(skb);
798 txq = mp->txq + queue;
799 nq = netdev_get_tx_queue(dev, queue);
801 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
803 dev_printk(KERN_DEBUG, &dev->dev,
804 "failed to linearize skb with tiny "
805 "unaligned fragment\n");
806 return NETDEV_TX_BUSY;
809 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
811 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
816 txq_submit_skb(txq, skb);
817 txq->tx_bytes += skb->len;
819 dev->trans_start = jiffies;
821 entries_left = txq->tx_ring_size - txq->tx_desc_count;
822 if (entries_left < MAX_SKB_FRAGS + 1)
823 netif_tx_stop_queue(nq);
829 /* tx napi ******************************************************************/
830 static void txq_kick(struct tx_queue *txq)
832 struct mv643xx_eth_private *mp = txq_to_mp(txq);
833 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
837 __netif_tx_lock(nq, smp_processor_id());
839 if (rdl(mp, TXQ_COMMAND(mp->port_num)) & (1 << txq->index))
842 hw_desc_ptr = rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index));
843 expected_ptr = (u32)txq->tx_desc_dma +
844 txq->tx_curr_desc * sizeof(struct tx_desc);
846 if (hw_desc_ptr != expected_ptr)
850 __netif_tx_unlock(nq);
852 mp->work_tx_end &= ~(1 << txq->index);
855 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
857 struct mv643xx_eth_private *mp = txq_to_mp(txq);
858 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
861 __netif_tx_lock(nq, smp_processor_id());
864 while (reclaimed < budget && txq->tx_desc_count > 0) {
866 struct tx_desc *desc;
872 tx_index = txq->tx_used_desc;
873 desc = &txq->tx_desc_area[tx_index];
874 cmd_sts = desc->cmd_sts;
876 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
879 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
882 txq->tx_used_desc = tx_index + 1;
883 if (txq->tx_used_desc == txq->tx_ring_size)
884 txq->tx_used_desc = 0;
887 txq->tx_desc_count--;
889 addr = desc->buf_ptr;
890 count = desc->byte_cnt;
891 skb = txq->tx_skb[tx_index];
892 txq->tx_skb[tx_index] = NULL;
894 if (cmd_sts & ERROR_SUMMARY) {
895 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
896 mp->dev->stats.tx_errors++;
900 * Drop tx queue lock while we free the skb.
902 __netif_tx_unlock(nq);
904 if (cmd_sts & TX_FIRST_DESC)
905 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
907 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
912 __netif_tx_lock(nq, smp_processor_id());
915 __netif_tx_unlock(nq);
917 if (reclaimed < budget)
918 mp->work_tx &= ~(1 << txq->index);
924 /* tx rate control **********************************************************/
926 * Set total maximum TX rate (shared by all TX queues for this port)
927 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
929 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
935 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
936 if (token_rate > 1023)
939 mtu = (mp->dev->mtu + 255) >> 8;
943 bucket_size = (burst + 255) >> 8;
944 if (bucket_size > 65535)
947 if (mp->shared->tx_bw_control_moved) {
948 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
949 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
950 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
952 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
953 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
954 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
958 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
960 struct mv643xx_eth_private *mp = txq_to_mp(txq);
964 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
965 if (token_rate > 1023)
968 bucket_size = (burst + 255) >> 8;
969 if (bucket_size > 65535)
972 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
973 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
974 (bucket_size << 10) | token_rate);
977 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
979 struct mv643xx_eth_private *mp = txq_to_mp(txq);
984 * Turn on fixed priority mode.
986 if (mp->shared->tx_bw_control_moved)
987 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
989 off = TXQ_FIX_PRIO_CONF(mp->port_num);
992 val |= 1 << txq->index;
996 static void txq_set_wrr(struct tx_queue *txq, int weight)
998 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1003 * Turn off fixed priority mode.
1005 if (mp->shared->tx_bw_control_moved)
1006 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
1008 off = TXQ_FIX_PRIO_CONF(mp->port_num);
1011 val &= ~(1 << txq->index);
1015 * Configure WRR weight for this queue.
1017 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
1020 val = (val & ~0xff) | (weight & 0xff);
1025 /* mii management interface *************************************************/
1026 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1028 struct mv643xx_eth_shared_private *msp = dev_id;
1030 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1031 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1032 wake_up(&msp->smi_busy_wait);
1039 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1041 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1044 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1046 if (msp->err_interrupt == NO_IRQ) {
1049 for (i = 0; !smi_is_done(msp); i++) {
1058 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1059 msecs_to_jiffies(100)))
1065 static int smi_reg_read(struct mv643xx_eth_private *mp,
1066 unsigned int addr, unsigned int reg)
1068 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
1069 void __iomem *smi_reg = msp->base + SMI_REG;
1072 mutex_lock(&msp->phy_lock);
1074 if (smi_wait_ready(msp)) {
1075 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1080 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1082 if (smi_wait_ready(msp)) {
1083 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1088 ret = readl(smi_reg);
1089 if (!(ret & SMI_READ_VALID)) {
1090 printk("%s: SMI bus read not valid\n", mp->dev->name);
1098 mutex_unlock(&msp->phy_lock);
1103 static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1104 unsigned int reg, unsigned int value)
1106 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
1107 void __iomem *smi_reg = msp->base + SMI_REG;
1109 mutex_lock(&msp->phy_lock);
1111 if (smi_wait_ready(msp)) {
1112 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1113 mutex_unlock(&msp->phy_lock);
1117 writel(SMI_OPCODE_WRITE | (reg << 21) |
1118 (addr << 16) | (value & 0xffff), smi_reg);
1120 mutex_unlock(&msp->phy_lock);
1126 /* statistics ***************************************************************/
1127 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1129 struct mv643xx_eth_private *mp = netdev_priv(dev);
1130 struct net_device_stats *stats = &dev->stats;
1131 unsigned long tx_packets = 0;
1132 unsigned long tx_bytes = 0;
1133 unsigned long tx_dropped = 0;
1136 for (i = 0; i < mp->txq_count; i++) {
1137 struct tx_queue *txq = mp->txq + i;
1139 tx_packets += txq->tx_packets;
1140 tx_bytes += txq->tx_bytes;
1141 tx_dropped += txq->tx_dropped;
1144 stats->tx_packets = tx_packets;
1145 stats->tx_bytes = tx_bytes;
1146 stats->tx_dropped = tx_dropped;
1151 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1153 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1156 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1160 for (i = 0; i < 0x80; i += 4)
1164 static void mib_counters_update(struct mv643xx_eth_private *mp)
1166 struct mib_counters *p = &mp->mib_counters;
1168 p->good_octets_received += mib_read(mp, 0x00);
1169 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1170 p->bad_octets_received += mib_read(mp, 0x08);
1171 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1172 p->good_frames_received += mib_read(mp, 0x10);
1173 p->bad_frames_received += mib_read(mp, 0x14);
1174 p->broadcast_frames_received += mib_read(mp, 0x18);
1175 p->multicast_frames_received += mib_read(mp, 0x1c);
1176 p->frames_64_octets += mib_read(mp, 0x20);
1177 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1178 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1179 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1180 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1181 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1182 p->good_octets_sent += mib_read(mp, 0x38);
1183 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1184 p->good_frames_sent += mib_read(mp, 0x40);
1185 p->excessive_collision += mib_read(mp, 0x44);
1186 p->multicast_frames_sent += mib_read(mp, 0x48);
1187 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1188 p->unrec_mac_control_received += mib_read(mp, 0x50);
1189 p->fc_sent += mib_read(mp, 0x54);
1190 p->good_fc_received += mib_read(mp, 0x58);
1191 p->bad_fc_received += mib_read(mp, 0x5c);
1192 p->undersize_received += mib_read(mp, 0x60);
1193 p->fragments_received += mib_read(mp, 0x64);
1194 p->oversize_received += mib_read(mp, 0x68);
1195 p->jabber_received += mib_read(mp, 0x6c);
1196 p->mac_receive_error += mib_read(mp, 0x70);
1197 p->bad_crc_event += mib_read(mp, 0x74);
1198 p->collision += mib_read(mp, 0x78);
1199 p->late_collision += mib_read(mp, 0x7c);
1203 /* ethtool ******************************************************************/
1204 struct mv643xx_eth_stats {
1205 char stat_string[ETH_GSTRING_LEN];
1212 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1213 offsetof(struct net_device, stats.m), -1 }
1215 #define MIBSTAT(m) \
1216 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1217 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1219 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1228 MIBSTAT(good_octets_received),
1229 MIBSTAT(bad_octets_received),
1230 MIBSTAT(internal_mac_transmit_err),
1231 MIBSTAT(good_frames_received),
1232 MIBSTAT(bad_frames_received),
1233 MIBSTAT(broadcast_frames_received),
1234 MIBSTAT(multicast_frames_received),
1235 MIBSTAT(frames_64_octets),
1236 MIBSTAT(frames_65_to_127_octets),
1237 MIBSTAT(frames_128_to_255_octets),
1238 MIBSTAT(frames_256_to_511_octets),
1239 MIBSTAT(frames_512_to_1023_octets),
1240 MIBSTAT(frames_1024_to_max_octets),
1241 MIBSTAT(good_octets_sent),
1242 MIBSTAT(good_frames_sent),
1243 MIBSTAT(excessive_collision),
1244 MIBSTAT(multicast_frames_sent),
1245 MIBSTAT(broadcast_frames_sent),
1246 MIBSTAT(unrec_mac_control_received),
1248 MIBSTAT(good_fc_received),
1249 MIBSTAT(bad_fc_received),
1250 MIBSTAT(undersize_received),
1251 MIBSTAT(fragments_received),
1252 MIBSTAT(oversize_received),
1253 MIBSTAT(jabber_received),
1254 MIBSTAT(mac_receive_error),
1255 MIBSTAT(bad_crc_event),
1257 MIBSTAT(late_collision),
1260 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1262 struct mv643xx_eth_private *mp = netdev_priv(dev);
1265 err = mii_ethtool_gset(&mp->mii, cmd);
1268 * The MAC does not support 1000baseT_Half.
1270 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1271 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1276 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1278 struct mv643xx_eth_private *mp = netdev_priv(dev);
1281 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1283 cmd->supported = SUPPORTED_MII;
1284 cmd->advertising = ADVERTISED_MII;
1285 switch (port_status & PORT_SPEED_MASK) {
1287 cmd->speed = SPEED_10;
1289 case PORT_SPEED_100:
1290 cmd->speed = SPEED_100;
1292 case PORT_SPEED_1000:
1293 cmd->speed = SPEED_1000;
1299 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1300 cmd->port = PORT_MII;
1301 cmd->phy_address = 0;
1302 cmd->transceiver = XCVR_INTERNAL;
1303 cmd->autoneg = AUTONEG_DISABLE;
1310 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1312 struct mv643xx_eth_private *mp = netdev_priv(dev);
1315 * The MAC does not support 1000baseT_Half.
1317 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1319 return mii_ethtool_sset(&mp->mii, cmd);
1322 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1327 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1328 struct ethtool_drvinfo *drvinfo)
1330 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1331 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1332 strncpy(drvinfo->fw_version, "N/A", 32);
1333 strncpy(drvinfo->bus_info, "platform", 32);
1334 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1337 static int mv643xx_eth_nway_reset(struct net_device *dev)
1339 struct mv643xx_eth_private *mp = netdev_priv(dev);
1341 return mii_nway_restart(&mp->mii);
1344 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1349 static u32 mv643xx_eth_get_link(struct net_device *dev)
1351 struct mv643xx_eth_private *mp = netdev_priv(dev);
1353 return mii_link_ok(&mp->mii);
1356 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1361 static void mv643xx_eth_get_strings(struct net_device *dev,
1362 uint32_t stringset, uint8_t *data)
1366 if (stringset == ETH_SS_STATS) {
1367 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1368 memcpy(data + i * ETH_GSTRING_LEN,
1369 mv643xx_eth_stats[i].stat_string,
1375 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1376 struct ethtool_stats *stats,
1379 struct mv643xx_eth_private *mp = netdev_priv(dev);
1382 mv643xx_eth_get_stats(dev);
1383 mib_counters_update(mp);
1385 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1386 const struct mv643xx_eth_stats *stat;
1389 stat = mv643xx_eth_stats + i;
1391 if (stat->netdev_off >= 0)
1392 p = ((void *)mp->dev) + stat->netdev_off;
1394 p = ((void *)mp) + stat->mp_off;
1396 data[i] = (stat->sizeof_stat == 8) ?
1397 *(uint64_t *)p : *(uint32_t *)p;
1401 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1403 if (sset == ETH_SS_STATS)
1404 return ARRAY_SIZE(mv643xx_eth_stats);
1409 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1410 .get_settings = mv643xx_eth_get_settings,
1411 .set_settings = mv643xx_eth_set_settings,
1412 .get_drvinfo = mv643xx_eth_get_drvinfo,
1413 .nway_reset = mv643xx_eth_nway_reset,
1414 .get_link = mv643xx_eth_get_link,
1415 .set_sg = ethtool_op_set_sg,
1416 .get_strings = mv643xx_eth_get_strings,
1417 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1418 .get_sset_count = mv643xx_eth_get_sset_count,
1421 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1422 .get_settings = mv643xx_eth_get_settings_phyless,
1423 .set_settings = mv643xx_eth_set_settings_phyless,
1424 .get_drvinfo = mv643xx_eth_get_drvinfo,
1425 .nway_reset = mv643xx_eth_nway_reset_phyless,
1426 .get_link = mv643xx_eth_get_link_phyless,
1427 .set_sg = ethtool_op_set_sg,
1428 .get_strings = mv643xx_eth_get_strings,
1429 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1430 .get_sset_count = mv643xx_eth_get_sset_count,
1434 /* address handling *********************************************************/
1435 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1440 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1441 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1443 addr[0] = (mac_h >> 24) & 0xff;
1444 addr[1] = (mac_h >> 16) & 0xff;
1445 addr[2] = (mac_h >> 8) & 0xff;
1446 addr[3] = mac_h & 0xff;
1447 addr[4] = (mac_l >> 8) & 0xff;
1448 addr[5] = mac_l & 0xff;
1451 static void init_mac_tables(struct mv643xx_eth_private *mp)
1455 for (i = 0; i < 0x100; i += 4) {
1456 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1457 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1460 for (i = 0; i < 0x10; i += 4)
1461 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1464 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1465 int table, unsigned char entry)
1467 unsigned int table_reg;
1469 /* Set "accepts frame bit" at specified table entry */
1470 table_reg = rdl(mp, table + (entry & 0xfc));
1471 table_reg |= 0x01 << (8 * (entry & 3));
1472 wrl(mp, table + (entry & 0xfc), table_reg);
1475 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1481 mac_l = (addr[4] << 8) | addr[5];
1482 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1484 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1485 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1487 table = UNICAST_TABLE(mp->port_num);
1488 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1491 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1493 struct mv643xx_eth_private *mp = netdev_priv(dev);
1495 /* +2 is for the offset of the HW addr type */
1496 memcpy(dev->dev_addr, addr + 2, 6);
1498 init_mac_tables(mp);
1499 uc_addr_set(mp, dev->dev_addr);
1504 static int addr_crc(unsigned char *addr)
1509 for (i = 0; i < 6; i++) {
1512 crc = (crc ^ addr[i]) << 8;
1513 for (j = 7; j >= 0; j--) {
1514 if (crc & (0x100 << j))
1522 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1524 struct mv643xx_eth_private *mp = netdev_priv(dev);
1526 struct dev_addr_list *addr;
1529 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1530 if (dev->flags & IFF_PROMISC)
1531 port_config |= UNICAST_PROMISCUOUS_MODE;
1533 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1534 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1536 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1537 int port_num = mp->port_num;
1538 u32 accept = 0x01010101;
1540 for (i = 0; i < 0x100; i += 4) {
1541 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1542 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1547 for (i = 0; i < 0x100; i += 4) {
1548 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1549 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1552 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1553 u8 *a = addr->da_addr;
1556 if (addr->da_addrlen != 6)
1559 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1560 table = SPECIAL_MCAST_TABLE(mp->port_num);
1561 set_filter_table_entry(mp, table, a[5]);
1563 int crc = addr_crc(a);
1565 table = OTHER_MCAST_TABLE(mp->port_num);
1566 set_filter_table_entry(mp, table, crc);
1572 /* rx/tx queue initialisation ***********************************************/
1573 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1575 struct rx_queue *rxq = mp->rxq + index;
1576 struct rx_desc *rx_desc;
1582 rxq->rx_ring_size = mp->default_rx_ring_size;
1584 rxq->rx_desc_count = 0;
1585 rxq->rx_curr_desc = 0;
1586 rxq->rx_used_desc = 0;
1588 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1590 if (index == 0 && size <= mp->rx_desc_sram_size) {
1591 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1592 mp->rx_desc_sram_size);
1593 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1595 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1600 if (rxq->rx_desc_area == NULL) {
1601 dev_printk(KERN_ERR, &mp->dev->dev,
1602 "can't allocate rx ring (%d bytes)\n", size);
1605 memset(rxq->rx_desc_area, 0, size);
1607 rxq->rx_desc_area_size = size;
1608 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1610 if (rxq->rx_skb == NULL) {
1611 dev_printk(KERN_ERR, &mp->dev->dev,
1612 "can't allocate rx skb ring\n");
1616 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1617 for (i = 0; i < rxq->rx_ring_size; i++) {
1621 if (nexti == rxq->rx_ring_size)
1624 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1625 nexti * sizeof(struct rx_desc);
1632 if (index == 0 && size <= mp->rx_desc_sram_size)
1633 iounmap(rxq->rx_desc_area);
1635 dma_free_coherent(NULL, size,
1643 static void rxq_deinit(struct rx_queue *rxq)
1645 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1650 for (i = 0; i < rxq->rx_ring_size; i++) {
1651 if (rxq->rx_skb[i]) {
1652 dev_kfree_skb(rxq->rx_skb[i]);
1653 rxq->rx_desc_count--;
1657 if (rxq->rx_desc_count) {
1658 dev_printk(KERN_ERR, &mp->dev->dev,
1659 "error freeing rx ring -- %d skbs stuck\n",
1660 rxq->rx_desc_count);
1663 if (rxq->index == 0 &&
1664 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1665 iounmap(rxq->rx_desc_area);
1667 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1668 rxq->rx_desc_area, rxq->rx_desc_dma);
1673 static int txq_init(struct mv643xx_eth_private *mp, int index)
1675 struct tx_queue *txq = mp->txq + index;
1676 struct tx_desc *tx_desc;
1682 txq->tx_ring_size = mp->default_tx_ring_size;
1684 txq->tx_desc_count = 0;
1685 txq->tx_curr_desc = 0;
1686 txq->tx_used_desc = 0;
1688 size = txq->tx_ring_size * sizeof(struct tx_desc);
1690 if (index == 0 && size <= mp->tx_desc_sram_size) {
1691 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1692 mp->tx_desc_sram_size);
1693 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1695 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1700 if (txq->tx_desc_area == NULL) {
1701 dev_printk(KERN_ERR, &mp->dev->dev,
1702 "can't allocate tx ring (%d bytes)\n", size);
1705 memset(txq->tx_desc_area, 0, size);
1707 txq->tx_desc_area_size = size;
1708 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1710 if (txq->tx_skb == NULL) {
1711 dev_printk(KERN_ERR, &mp->dev->dev,
1712 "can't allocate tx skb ring\n");
1716 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1717 for (i = 0; i < txq->tx_ring_size; i++) {
1718 struct tx_desc *txd = tx_desc + i;
1722 if (nexti == txq->tx_ring_size)
1726 txd->next_desc_ptr = txq->tx_desc_dma +
1727 nexti * sizeof(struct tx_desc);
1733 if (index == 0 && size <= mp->tx_desc_sram_size)
1734 iounmap(txq->tx_desc_area);
1736 dma_free_coherent(NULL, size,
1744 static void txq_deinit(struct tx_queue *txq)
1746 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1749 txq_reclaim(txq, txq->tx_ring_size, 1);
1751 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1753 if (txq->index == 0 &&
1754 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1755 iounmap(txq->tx_desc_area);
1757 dma_free_coherent(NULL, txq->tx_desc_area_size,
1758 txq->tx_desc_area, txq->tx_desc_dma);
1764 /* netdev ops and related ***************************************************/
1765 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1770 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1771 (INT_TX_END | INT_RX | INT_EXT);
1776 if (int_cause & INT_EXT)
1777 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num));
1779 int_cause &= INT_TX_END | INT_RX;
1781 wrl(mp, INT_CAUSE(mp->port_num), ~int_cause);
1782 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1783 ~(rdl(mp, TXQ_COMMAND(mp->port_num)) & 0xff);
1784 mp->work_rx |= (int_cause & INT_RX) >> 2;
1787 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1788 if (int_cause_ext) {
1789 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1790 if (int_cause_ext & INT_EXT_LINK_PHY)
1792 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1798 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1800 struct net_device *dev = (struct net_device *)dev_id;
1801 struct mv643xx_eth_private *mp = netdev_priv(dev);
1803 if (unlikely(!mv643xx_eth_collect_events(mp)))
1806 wrl(mp, INT_MASK(mp->port_num), 0);
1807 napi_schedule(&mp->napi);
1812 static void handle_link_event(struct mv643xx_eth_private *mp)
1814 struct net_device *dev = mp->dev;
1820 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1821 if (!(port_status & LINK_UP)) {
1822 if (netif_carrier_ok(dev)) {
1825 printk(KERN_INFO "%s: link down\n", dev->name);
1827 netif_carrier_off(dev);
1829 for (i = 0; i < mp->txq_count; i++) {
1830 struct tx_queue *txq = mp->txq + i;
1832 txq_reclaim(txq, txq->tx_ring_size, 1);
1833 txq_reset_hw_ptr(txq);
1839 switch (port_status & PORT_SPEED_MASK) {
1843 case PORT_SPEED_100:
1846 case PORT_SPEED_1000:
1853 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1854 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1856 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1857 "flow control %sabled\n", dev->name,
1858 speed, duplex ? "full" : "half",
1861 if (!netif_carrier_ok(dev))
1862 netif_carrier_on(dev);
1865 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1867 struct mv643xx_eth_private *mp;
1870 mp = container_of(napi, struct mv643xx_eth_private, napi);
1872 mp->work_rx_refill |= mp->work_rx_oom;
1873 mp->work_rx_oom = 0;
1876 while (work_done < budget) {
1881 if (mp->work_link) {
1883 handle_link_event(mp);
1887 queue_mask = mp->work_tx | mp->work_tx_end |
1888 mp->work_rx | mp->work_rx_refill;
1890 if (mv643xx_eth_collect_events(mp))
1895 queue = fls(queue_mask) - 1;
1896 queue_mask = 1 << queue;
1898 work_tbd = budget - work_done;
1902 if (mp->work_tx_end & queue_mask) {
1903 txq_kick(mp->txq + queue);
1904 } else if (mp->work_tx & queue_mask) {
1905 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1906 txq_maybe_wake(mp->txq + queue);
1907 } else if (mp->work_rx & queue_mask) {
1908 work_done += rxq_process(mp->rxq + queue, work_tbd);
1909 } else if (mp->work_rx_refill & queue_mask) {
1910 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1916 if (work_done < budget) {
1917 if (mp->work_rx_oom)
1918 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1919 napi_complete(napi);
1920 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
1926 static inline void oom_timer_wrapper(unsigned long data)
1928 struct mv643xx_eth_private *mp = (void *)data;
1930 napi_schedule(&mp->napi);
1933 static void phy_reset(struct mv643xx_eth_private *mp)
1937 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1942 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1946 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1947 } while (data >= 0 && data & BMCR_RESET);
1950 static void port_start(struct mv643xx_eth_private *mp)
1956 * Perform PHY reset, if there is a PHY.
1958 if (mp->phy_addr != -1) {
1959 struct ethtool_cmd cmd;
1961 mv643xx_eth_get_settings(mp->dev, &cmd);
1963 mv643xx_eth_set_settings(mp->dev, &cmd);
1967 * Configure basic link parameters.
1969 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1971 pscr |= SERIAL_PORT_ENABLE;
1972 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1974 pscr |= DO_NOT_FORCE_LINK_FAIL;
1975 if (mp->phy_addr == -1)
1976 pscr |= FORCE_LINK_PASS;
1977 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1979 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1982 * Configure TX path and queues.
1984 tx_set_rate(mp, 1000000000, 16777216);
1985 for (i = 0; i < mp->txq_count; i++) {
1986 struct tx_queue *txq = mp->txq + i;
1988 txq_reset_hw_ptr(txq);
1989 txq_set_rate(txq, 1000000000, 16777216);
1990 txq_set_fixed_prio_mode(txq);
1994 * Add configured unicast address to address filter table.
1996 uc_addr_set(mp, mp->dev->dev_addr);
1999 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2000 * frames to RX queue #0.
2002 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
2005 * Treat BPDUs as normal multicasts, and disable partition mode.
2007 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
2010 * Enable the receive queues.
2012 for (i = 0; i < mp->rxq_count; i++) {
2013 struct rx_queue *rxq = mp->rxq + i;
2014 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
2017 addr = (u32)rxq->rx_desc_dma;
2018 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2025 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2027 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2030 val = rdl(mp, SDMA_CONFIG(mp->port_num));
2031 if (mp->shared->extended_rx_coal_limit) {
2035 val |= (coal & 0x8000) << 10;
2036 val |= (coal & 0x7fff) << 7;
2041 val |= (coal & 0x3fff) << 8;
2043 wrl(mp, SDMA_CONFIG(mp->port_num), val);
2046 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2048 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2052 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2055 static int mv643xx_eth_open(struct net_device *dev)
2057 struct mv643xx_eth_private *mp = netdev_priv(dev);
2061 wrl(mp, INT_CAUSE(mp->port_num), 0);
2062 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2063 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2065 err = request_irq(dev->irq, mv643xx_eth_irq,
2066 IRQF_SHARED, dev->name, dev);
2068 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2072 init_mac_tables(mp);
2074 napi_enable(&mp->napi);
2076 for (i = 0; i < mp->rxq_count; i++) {
2077 err = rxq_init(mp, i);
2080 rxq_deinit(mp->rxq + i);
2084 rxq_refill(mp->rxq + i, INT_MAX);
2087 if (mp->work_rx_oom) {
2088 mp->rx_oom.expires = jiffies + (HZ / 10);
2089 add_timer(&mp->rx_oom);
2092 for (i = 0; i < mp->txq_count; i++) {
2093 err = txq_init(mp, i);
2096 txq_deinit(mp->txq + i);
2101 netif_carrier_off(dev);
2108 wrl(mp, INT_MASK_EXT(mp->port_num), INT_EXT_LINK_PHY | INT_EXT_TX);
2109 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2115 for (i = 0; i < mp->rxq_count; i++)
2116 rxq_deinit(mp->rxq + i);
2118 free_irq(dev->irq, dev);
2123 static void port_reset(struct mv643xx_eth_private *mp)
2128 for (i = 0; i < mp->rxq_count; i++)
2129 rxq_disable(mp->rxq + i);
2130 for (i = 0; i < mp->txq_count; i++)
2131 txq_disable(mp->txq + i);
2134 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2136 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2141 /* Reset the Enable bit in the Configuration Register */
2142 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2143 data &= ~(SERIAL_PORT_ENABLE |
2144 DO_NOT_FORCE_LINK_FAIL |
2146 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2149 static int mv643xx_eth_stop(struct net_device *dev)
2151 struct mv643xx_eth_private *mp = netdev_priv(dev);
2154 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2155 rdl(mp, INT_MASK(mp->port_num));
2157 napi_disable(&mp->napi);
2159 del_timer_sync(&mp->rx_oom);
2161 netif_carrier_off(dev);
2163 free_irq(dev->irq, dev);
2166 mv643xx_eth_get_stats(dev);
2167 mib_counters_update(mp);
2169 for (i = 0; i < mp->rxq_count; i++)
2170 rxq_deinit(mp->rxq + i);
2171 for (i = 0; i < mp->txq_count; i++)
2172 txq_deinit(mp->txq + i);
2177 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2179 struct mv643xx_eth_private *mp = netdev_priv(dev);
2181 if (mp->phy_addr != -1)
2182 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2187 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2189 struct mv643xx_eth_private *mp = netdev_priv(dev);
2191 if (new_mtu < 64 || new_mtu > 9500)
2195 tx_set_rate(mp, 1000000000, 16777216);
2197 if (!netif_running(dev))
2201 * Stop and then re-open the interface. This will allocate RX
2202 * skbs of the new MTU.
2203 * There is a possible danger that the open will not succeed,
2204 * due to memory being full.
2206 mv643xx_eth_stop(dev);
2207 if (mv643xx_eth_open(dev)) {
2208 dev_printk(KERN_ERR, &dev->dev,
2209 "fatal error on re-opening device after "
2216 static void tx_timeout_task(struct work_struct *ugly)
2218 struct mv643xx_eth_private *mp;
2220 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2221 if (netif_running(mp->dev)) {
2222 netif_tx_stop_all_queues(mp->dev);
2225 netif_tx_wake_all_queues(mp->dev);
2229 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2231 struct mv643xx_eth_private *mp = netdev_priv(dev);
2233 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2235 schedule_work(&mp->tx_timeout_task);
2238 #ifdef CONFIG_NET_POLL_CONTROLLER
2239 static void mv643xx_eth_netpoll(struct net_device *dev)
2241 struct mv643xx_eth_private *mp = netdev_priv(dev);
2243 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2244 rdl(mp, INT_MASK(mp->port_num));
2246 mv643xx_eth_irq(dev->irq, dev);
2248 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2252 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2254 struct mv643xx_eth_private *mp = netdev_priv(dev);
2255 return smi_reg_read(mp, addr, reg);
2258 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2260 struct mv643xx_eth_private *mp = netdev_priv(dev);
2261 smi_reg_write(mp, addr, reg, val);
2265 /* platform glue ************************************************************/
2267 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2268 struct mbus_dram_target_info *dram)
2270 void __iomem *base = msp->base;
2275 for (i = 0; i < 6; i++) {
2276 writel(0, base + WINDOW_BASE(i));
2277 writel(0, base + WINDOW_SIZE(i));
2279 writel(0, base + WINDOW_REMAP_HIGH(i));
2285 for (i = 0; i < dram->num_cs; i++) {
2286 struct mbus_dram_window *cs = dram->cs + i;
2288 writel((cs->base & 0xffff0000) |
2289 (cs->mbus_attr << 8) |
2290 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2291 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2293 win_enable &= ~(1 << i);
2294 win_protect |= 3 << (2 * i);
2297 writel(win_enable, base + WINDOW_BAR_ENABLE);
2298 msp->win_protect = win_protect;
2301 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2304 * Check whether we have a 14-bit coal limit field in bits
2305 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2306 * SDMA config register.
2308 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2309 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2310 msp->extended_rx_coal_limit = 1;
2312 msp->extended_rx_coal_limit = 0;
2315 * Check whether the TX rate control registers are in the
2316 * old or the new place.
2318 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2319 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2320 msp->tx_bw_control_moved = 1;
2322 msp->tx_bw_control_moved = 0;
2325 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2327 static int mv643xx_eth_version_printed = 0;
2328 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2329 struct mv643xx_eth_shared_private *msp;
2330 struct resource *res;
2333 if (!mv643xx_eth_version_printed++)
2334 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2335 "driver version %s\n", mv643xx_eth_driver_version);
2338 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2343 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2346 memset(msp, 0, sizeof(*msp));
2348 msp->base = ioremap(res->start, res->end - res->start + 1);
2349 if (msp->base == NULL)
2353 if (pd != NULL && pd->shared_smi != NULL)
2354 msp->smi = platform_get_drvdata(pd->shared_smi);
2356 mutex_init(&msp->phy_lock);
2358 msp->err_interrupt = NO_IRQ;
2359 init_waitqueue_head(&msp->smi_busy_wait);
2362 * Check whether the error interrupt is hooked up.
2364 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2368 err = request_irq(res->start, mv643xx_eth_err_irq,
2369 IRQF_SHARED, "mv643xx_eth", msp);
2371 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2372 msp->err_interrupt = res->start;
2377 * (Re-)program MBUS remapping windows if we are asked to.
2379 if (pd != NULL && pd->dram != NULL)
2380 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2383 * Detect hardware parameters.
2385 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2386 infer_hw_params(msp);
2388 platform_set_drvdata(pdev, msp);
2398 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2400 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2402 if (msp->err_interrupt != NO_IRQ)
2403 free_irq(msp->err_interrupt, msp);
2410 static struct platform_driver mv643xx_eth_shared_driver = {
2411 .probe = mv643xx_eth_shared_probe,
2412 .remove = mv643xx_eth_shared_remove,
2414 .name = MV643XX_ETH_SHARED_NAME,
2415 .owner = THIS_MODULE,
2419 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2421 int addr_shift = 5 * mp->port_num;
2424 data = rdl(mp, PHY_ADDR);
2425 data &= ~(0x1f << addr_shift);
2426 data |= (phy_addr & 0x1f) << addr_shift;
2427 wrl(mp, PHY_ADDR, data);
2430 static int phy_addr_get(struct mv643xx_eth_private *mp)
2434 data = rdl(mp, PHY_ADDR);
2436 return (data >> (5 * mp->port_num)) & 0x1f;
2439 static void set_params(struct mv643xx_eth_private *mp,
2440 struct mv643xx_eth_platform_data *pd)
2442 struct net_device *dev = mp->dev;
2444 if (is_valid_ether_addr(pd->mac_addr))
2445 memcpy(dev->dev_addr, pd->mac_addr, 6);
2447 uc_addr_get(mp, dev->dev_addr);
2449 if (pd->phy_addr == MV643XX_ETH_PHY_NONE) {
2452 if (pd->phy_addr != MV643XX_ETH_PHY_ADDR_DEFAULT) {
2453 mp->phy_addr = pd->phy_addr & 0x3f;
2454 phy_addr_set(mp, mp->phy_addr);
2456 mp->phy_addr = phy_addr_get(mp);
2460 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2461 if (pd->rx_queue_size)
2462 mp->default_rx_ring_size = pd->rx_queue_size;
2463 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2464 mp->rx_desc_sram_size = pd->rx_sram_size;
2466 mp->rxq_count = pd->rx_queue_count ? : 1;
2468 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2469 if (pd->tx_queue_size)
2470 mp->default_tx_ring_size = pd->tx_queue_size;
2471 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2472 mp->tx_desc_sram_size = pd->tx_sram_size;
2474 mp->txq_count = pd->tx_queue_count ? : 1;
2477 static int phy_detect(struct mv643xx_eth_private *mp)
2482 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2486 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2489 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2493 if (((data ^ data2) & BMCR_ANENABLE) == 0)
2496 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
2501 static int phy_init(struct mv643xx_eth_private *mp,
2502 struct mv643xx_eth_platform_data *pd)
2504 struct ethtool_cmd cmd;
2507 err = phy_detect(mp);
2509 dev_printk(KERN_INFO, &mp->dev->dev,
2510 "no PHY detected at addr %d\n", mp->phy_addr);
2515 mp->mii.phy_id = mp->phy_addr;
2516 mp->mii.phy_id_mask = 0x3f;
2517 mp->mii.reg_num_mask = 0x1f;
2518 mp->mii.dev = mp->dev;
2519 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2520 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2522 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2524 memset(&cmd, 0, sizeof(cmd));
2526 cmd.port = PORT_MII;
2527 cmd.transceiver = XCVR_INTERNAL;
2528 cmd.phy_address = mp->phy_addr;
2529 if (pd->speed == 0) {
2530 cmd.autoneg = AUTONEG_ENABLE;
2531 cmd.speed = SPEED_100;
2532 cmd.advertising = ADVERTISED_10baseT_Half |
2533 ADVERTISED_10baseT_Full |
2534 ADVERTISED_100baseT_Half |
2535 ADVERTISED_100baseT_Full;
2536 if (mp->mii.supports_gmii)
2537 cmd.advertising |= ADVERTISED_1000baseT_Full;
2539 cmd.autoneg = AUTONEG_DISABLE;
2540 cmd.speed = pd->speed;
2541 cmd.duplex = pd->duplex;
2544 mv643xx_eth_set_settings(mp->dev, &cmd);
2549 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2553 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2554 if (pscr & SERIAL_PORT_ENABLE) {
2555 pscr &= ~SERIAL_PORT_ENABLE;
2556 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2559 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2560 if (mp->phy_addr == -1) {
2561 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2562 if (speed == SPEED_1000)
2563 pscr |= SET_GMII_SPEED_TO_1000;
2564 else if (speed == SPEED_100)
2565 pscr |= SET_MII_SPEED_TO_100;
2567 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2569 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2570 if (duplex == DUPLEX_FULL)
2571 pscr |= SET_FULL_DUPLEX_MODE;
2574 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2577 static int mv643xx_eth_probe(struct platform_device *pdev)
2579 struct mv643xx_eth_platform_data *pd;
2580 struct mv643xx_eth_private *mp;
2581 struct net_device *dev;
2582 struct resource *res;
2583 DECLARE_MAC_BUF(mac);
2586 pd = pdev->dev.platform_data;
2588 dev_printk(KERN_ERR, &pdev->dev,
2589 "no mv643xx_eth_platform_data\n");
2593 if (pd->shared == NULL) {
2594 dev_printk(KERN_ERR, &pdev->dev,
2595 "no mv643xx_eth_platform_data->shared\n");
2599 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2603 mp = netdev_priv(dev);
2604 platform_set_drvdata(pdev, mp);
2606 mp->shared = platform_get_drvdata(pd->shared);
2607 mp->port_num = pd->port_number;
2612 dev->real_num_tx_queues = mp->txq_count;
2614 mib_counters_clear(mp);
2615 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2617 if (mp->phy_addr != -1) {
2618 err = phy_init(mp, pd);
2622 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2624 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2626 init_pscr(mp, pd->speed, pd->duplex);
2628 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2630 init_timer(&mp->rx_oom);
2631 mp->rx_oom.data = (unsigned long)mp;
2632 mp->rx_oom.function = oom_timer_wrapper;
2635 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2637 dev->irq = res->start;
2639 dev->get_stats = mv643xx_eth_get_stats;
2640 dev->hard_start_xmit = mv643xx_eth_xmit;
2641 dev->open = mv643xx_eth_open;
2642 dev->stop = mv643xx_eth_stop;
2643 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2644 dev->set_mac_address = mv643xx_eth_set_mac_address;
2645 dev->do_ioctl = mv643xx_eth_ioctl;
2646 dev->change_mtu = mv643xx_eth_change_mtu;
2647 dev->tx_timeout = mv643xx_eth_tx_timeout;
2648 #ifdef CONFIG_NET_POLL_CONTROLLER
2649 dev->poll_controller = mv643xx_eth_netpoll;
2651 dev->watchdog_timeo = 2 * HZ;
2654 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2655 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2657 SET_NETDEV_DEV(dev, &pdev->dev);
2659 if (mp->shared->win_protect)
2660 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2662 err = register_netdev(dev);
2666 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2667 mp->port_num, print_mac(mac, dev->dev_addr));
2669 if (mp->tx_desc_sram_size > 0)
2670 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2680 static int mv643xx_eth_remove(struct platform_device *pdev)
2682 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2684 unregister_netdev(mp->dev);
2685 flush_scheduled_work();
2686 free_netdev(mp->dev);
2688 platform_set_drvdata(pdev, NULL);
2693 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2695 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2697 /* Mask all interrupts on ethernet port */
2698 wrl(mp, INT_MASK(mp->port_num), 0);
2699 rdl(mp, INT_MASK(mp->port_num));
2701 if (netif_running(mp->dev))
2705 static struct platform_driver mv643xx_eth_driver = {
2706 .probe = mv643xx_eth_probe,
2707 .remove = mv643xx_eth_remove,
2708 .shutdown = mv643xx_eth_shutdown,
2710 .name = MV643XX_ETH_NAME,
2711 .owner = THIS_MODULE,
2715 static int __init mv643xx_eth_init_module(void)
2719 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2721 rc = platform_driver_register(&mv643xx_eth_driver);
2723 platform_driver_unregister(&mv643xx_eth_shared_driver);
2728 module_init(mv643xx_eth_init_module);
2730 static void __exit mv643xx_eth_cleanup_module(void)
2732 platform_driver_unregister(&mv643xx_eth_driver);
2733 platform_driver_unregister(&mv643xx_eth_shared_driver);
2735 module_exit(mv643xx_eth_cleanup_module);
2737 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2738 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2739 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2740 MODULE_LICENSE("GPL");
2741 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2742 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);