2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.3";
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_NAPI
62 #define MV643XX_ETH_TX_FAST_REFILL
64 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
65 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
67 #define MAX_DESCS_PER_SKB 1
71 * Registers shared between all ports.
73 #define PHY_ADDR 0x0000
74 #define SMI_REG 0x0004
75 #define SMI_BUSY 0x10000000
76 #define SMI_READ_VALID 0x08000000
77 #define SMI_OPCODE_READ 0x04000000
78 #define SMI_OPCODE_WRITE 0x00000000
79 #define ERR_INT_CAUSE 0x0080
80 #define ERR_INT_SMI_DONE 0x00000010
81 #define ERR_INT_MASK 0x0084
82 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
83 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
84 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
85 #define WINDOW_BAR_ENABLE 0x0290
86 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
91 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
92 #define UNICAST_PROMISCUOUS_MODE 0x00000001
93 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
94 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
95 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
96 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
97 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
98 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
99 #define TX_FIFO_EMPTY 0x00000400
100 #define TX_IN_PROGRESS 0x00000080
101 #define PORT_SPEED_MASK 0x00000030
102 #define PORT_SPEED_1000 0x00000010
103 #define PORT_SPEED_100 0x00000020
104 #define PORT_SPEED_10 0x00000000
105 #define FLOW_CONTROL_ENABLED 0x00000008
106 #define FULL_DUPLEX 0x00000004
107 #define LINK_UP 0x00000002
108 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
109 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
110 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
111 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
112 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
113 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
114 #define INT_TX_END_0 0x00080000
115 #define INT_TX_END 0x07f80000
116 #define INT_RX 0x0007fbfc
117 #define INT_EXT 0x00000002
118 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
119 #define INT_EXT_LINK 0x00100000
120 #define INT_EXT_PHY 0x00010000
121 #define INT_EXT_TX_ERROR_0 0x00000100
122 #define INT_EXT_TX_0 0x00000001
123 #define INT_EXT_TX 0x0000ffff
124 #define INT_MASK(p) (0x0468 + ((p) << 10))
125 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
126 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
127 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
128 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
129 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
130 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
131 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
132 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
133 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
134 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
135 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
136 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
137 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
138 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
139 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
140 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
144 * SDMA configuration register.
146 #define RX_BURST_SIZE_16_64BIT (4 << 1)
147 #define BLM_RX_NO_SWAP (1 << 4)
148 #define BLM_TX_NO_SWAP (1 << 5)
149 #define TX_BURST_SIZE_16_64BIT (4 << 22)
151 #if defined(__BIG_ENDIAN)
152 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
153 RX_BURST_SIZE_16_64BIT | \
154 TX_BURST_SIZE_16_64BIT
155 #elif defined(__LITTLE_ENDIAN)
156 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
157 RX_BURST_SIZE_16_64BIT | \
160 TX_BURST_SIZE_16_64BIT
162 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
167 * Port serial control register.
169 #define SET_MII_SPEED_TO_100 (1 << 24)
170 #define SET_GMII_SPEED_TO_1000 (1 << 23)
171 #define SET_FULL_DUPLEX_MODE (1 << 21)
172 #define MAX_RX_PACKET_9700BYTE (5 << 17)
173 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
174 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
175 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
176 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
177 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
178 #define FORCE_LINK_PASS (1 << 1)
179 #define SERIAL_PORT_ENABLE (1 << 0)
181 #define DEFAULT_RX_QUEUE_SIZE 400
182 #define DEFAULT_TX_QUEUE_SIZE 800
188 #if defined(__BIG_ENDIAN)
190 u16 byte_cnt; /* Descriptor buffer byte count */
191 u16 buf_size; /* Buffer size */
192 u32 cmd_sts; /* Descriptor command status */
193 u32 next_desc_ptr; /* Next descriptor pointer */
194 u32 buf_ptr; /* Descriptor buffer pointer */
198 u16 byte_cnt; /* buffer byte count */
199 u16 l4i_chk; /* CPU provided TCP checksum */
200 u32 cmd_sts; /* Command/status field */
201 u32 next_desc_ptr; /* Pointer to next descriptor */
202 u32 buf_ptr; /* pointer to buffer for this descriptor*/
204 #elif defined(__LITTLE_ENDIAN)
206 u32 cmd_sts; /* Descriptor command status */
207 u16 buf_size; /* Buffer size */
208 u16 byte_cnt; /* Descriptor buffer byte count */
209 u32 buf_ptr; /* Descriptor buffer pointer */
210 u32 next_desc_ptr; /* Next descriptor pointer */
214 u32 cmd_sts; /* Command/status field */
215 u16 l4i_chk; /* CPU provided TCP checksum */
216 u16 byte_cnt; /* buffer byte count */
217 u32 buf_ptr; /* pointer to buffer for this descriptor*/
218 u32 next_desc_ptr; /* Pointer to next descriptor */
221 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
224 /* RX & TX descriptor command */
225 #define BUFFER_OWNED_BY_DMA 0x80000000
227 /* RX & TX descriptor status */
228 #define ERROR_SUMMARY 0x00000001
230 /* RX descriptor status */
231 #define LAYER_4_CHECKSUM_OK 0x40000000
232 #define RX_ENABLE_INTERRUPT 0x20000000
233 #define RX_FIRST_DESC 0x08000000
234 #define RX_LAST_DESC 0x04000000
236 /* TX descriptor command */
237 #define TX_ENABLE_INTERRUPT 0x00800000
238 #define GEN_CRC 0x00400000
239 #define TX_FIRST_DESC 0x00200000
240 #define TX_LAST_DESC 0x00100000
241 #define ZERO_PADDING 0x00080000
242 #define GEN_IP_V4_CHECKSUM 0x00040000
243 #define GEN_TCP_UDP_CHECKSUM 0x00020000
244 #define UDP_FRAME 0x00010000
245 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
246 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
248 #define TX_IHL_SHIFT 11
251 /* global *******************************************************************/
252 struct mv643xx_eth_shared_private {
254 * Ethernet controller base address.
259 * Protects access to SMI_REG, which is shared between ports.
261 struct mutex phy_lock;
264 * If we have access to the error interrupt pin (which is
265 * somewhat misnamed as it not only reflects internal errors
266 * but also reflects SMI completion), use that to wait for
267 * SMI access completion instead of polling the SMI busy bit.
270 wait_queue_head_t smi_busy_wait;
273 * Per-port MBUS window access register value.
278 * Hardware-specific parameters.
281 int extended_rx_coal_limit;
282 int tx_bw_control_moved;
286 /* per-port *****************************************************************/
287 struct mib_counters {
288 u64 good_octets_received;
289 u32 bad_octets_received;
290 u32 internal_mac_transmit_err;
291 u32 good_frames_received;
292 u32 bad_frames_received;
293 u32 broadcast_frames_received;
294 u32 multicast_frames_received;
295 u32 frames_64_octets;
296 u32 frames_65_to_127_octets;
297 u32 frames_128_to_255_octets;
298 u32 frames_256_to_511_octets;
299 u32 frames_512_to_1023_octets;
300 u32 frames_1024_to_max_octets;
301 u64 good_octets_sent;
302 u32 good_frames_sent;
303 u32 excessive_collision;
304 u32 multicast_frames_sent;
305 u32 broadcast_frames_sent;
306 u32 unrec_mac_control_received;
308 u32 good_fc_received;
310 u32 undersize_received;
311 u32 fragments_received;
312 u32 oversize_received;
314 u32 mac_receive_error;
329 struct rx_desc *rx_desc_area;
330 dma_addr_t rx_desc_dma;
331 int rx_desc_area_size;
332 struct sk_buff **rx_skb;
334 struct timer_list rx_oom;
346 struct tx_desc *tx_desc_area;
347 dma_addr_t tx_desc_dma;
348 int tx_desc_area_size;
349 struct sk_buff **tx_skb;
352 struct mv643xx_eth_private {
353 struct mv643xx_eth_shared_private *shared;
356 struct net_device *dev;
358 struct mv643xx_eth_shared_private *shared_smi;
363 struct mib_counters mib_counters;
364 struct work_struct tx_timeout_task;
365 struct mii_if_info mii;
370 int default_rx_ring_size;
371 unsigned long rx_desc_sram_addr;
372 int rx_desc_sram_size;
375 struct napi_struct napi;
376 struct rx_queue rxq[8];
381 int default_tx_ring_size;
382 unsigned long tx_desc_sram_addr;
383 int tx_desc_sram_size;
386 struct tx_queue txq[8];
387 #ifdef MV643XX_ETH_TX_FAST_REFILL
388 int tx_clean_threshold;
393 /* port register accessors **************************************************/
394 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
396 return readl(mp->shared->base + offset);
399 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
401 writel(data, mp->shared->base + offset);
405 /* rxq/txq helper functions *************************************************/
406 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
408 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
411 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
413 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
416 static void rxq_enable(struct rx_queue *rxq)
418 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
419 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
422 static void rxq_disable(struct rx_queue *rxq)
424 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
425 u8 mask = 1 << rxq->index;
427 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
428 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
432 static void txq_reset_hw_ptr(struct tx_queue *txq)
434 struct mv643xx_eth_private *mp = txq_to_mp(txq);
435 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
438 addr = (u32)txq->tx_desc_dma;
439 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
443 static void txq_enable(struct tx_queue *txq)
445 struct mv643xx_eth_private *mp = txq_to_mp(txq);
446 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
449 static void txq_disable(struct tx_queue *txq)
451 struct mv643xx_eth_private *mp = txq_to_mp(txq);
452 u8 mask = 1 << txq->index;
454 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
455 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
459 static void __txq_maybe_wake(struct tx_queue *txq)
461 struct mv643xx_eth_private *mp = txq_to_mp(txq);
464 * netif_{stop,wake}_queue() flow control only applies to
467 BUG_ON(txq->index != mp->txq_primary);
469 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
470 netif_wake_queue(mp->dev);
474 /* rx ***********************************************************************/
475 static void txq_reclaim(struct tx_queue *txq, int force);
477 static void rxq_refill(struct rx_queue *rxq)
479 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
482 spin_lock_irqsave(&mp->lock, flags);
484 while (rxq->rx_desc_count < rxq->rx_ring_size) {
491 * Reserve 2+14 bytes for an ethernet header (the
492 * hardware automatically prepends 2 bytes of dummy
493 * data to each received packet), 16 bytes for up to
494 * four VLAN tags, and 4 bytes for the trailing FCS
497 skb_size = mp->dev->mtu + 36;
500 * Make sure that the skb size is a multiple of 8
501 * bytes, as the lower three bits of the receive
502 * descriptor's buffer size field are ignored by
505 skb_size = (skb_size + 7) & ~7;
507 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
511 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
513 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
515 rxq->rx_desc_count++;
517 rx = rxq->rx_used_desc++;
518 if (rxq->rx_used_desc == rxq->rx_ring_size)
519 rxq->rx_used_desc = 0;
521 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
522 skb_size, DMA_FROM_DEVICE);
523 rxq->rx_desc_area[rx].buf_size = skb_size;
524 rxq->rx_skb[rx] = skb;
526 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
531 * The hardware automatically prepends 2 bytes of
532 * dummy data to each received packet, so that the
533 * IP header ends up 16-byte aligned.
538 if (rxq->rx_desc_count != rxq->rx_ring_size)
539 mod_timer(&rxq->rx_oom, jiffies + (HZ / 10));
541 spin_unlock_irqrestore(&mp->lock, flags);
544 static inline void rxq_refill_timer_wrapper(unsigned long data)
546 rxq_refill((struct rx_queue *)data);
549 static int rxq_process(struct rx_queue *rxq, int budget)
551 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
552 struct net_device_stats *stats = &mp->dev->stats;
556 while (rx < budget && rxq->rx_desc_count) {
557 struct rx_desc *rx_desc;
558 unsigned int cmd_sts;
562 spin_lock_irqsave(&mp->lock, flags);
564 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
566 cmd_sts = rx_desc->cmd_sts;
567 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
568 spin_unlock_irqrestore(&mp->lock, flags);
573 skb = rxq->rx_skb[rxq->rx_curr_desc];
574 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
577 if (rxq->rx_curr_desc == rxq->rx_ring_size)
578 rxq->rx_curr_desc = 0;
580 spin_unlock_irqrestore(&mp->lock, flags);
582 dma_unmap_single(NULL, rx_desc->buf_ptr,
583 rx_desc->buf_size, DMA_FROM_DEVICE);
584 rxq->rx_desc_count--;
590 * Note that the descriptor byte count includes 2 dummy
591 * bytes automatically inserted by the hardware at the
592 * start of the packet (which we don't count), and a 4
593 * byte CRC at the end of the packet (which we do count).
596 stats->rx_bytes += rx_desc->byte_cnt - 2;
599 * In case we received a packet without first / last bits
600 * on, or the error summary bit is set, the packet needs
603 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
604 (RX_FIRST_DESC | RX_LAST_DESC))
605 || (cmd_sts & ERROR_SUMMARY)) {
608 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
609 (RX_FIRST_DESC | RX_LAST_DESC)) {
611 dev_printk(KERN_ERR, &mp->dev->dev,
612 "received packet spanning "
613 "multiple descriptors\n");
616 if (cmd_sts & ERROR_SUMMARY)
619 dev_kfree_skb_irq(skb);
622 * The -4 is for the CRC in the trailer of the
625 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
627 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
628 skb->ip_summed = CHECKSUM_UNNECESSARY;
630 (cmd_sts & 0x0007fff8) >> 3);
632 skb->protocol = eth_type_trans(skb, mp->dev);
633 #ifdef MV643XX_ETH_NAPI
634 netif_receive_skb(skb);
640 mp->dev->last_rx = jiffies;
648 #ifdef MV643XX_ETH_NAPI
649 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
651 struct mv643xx_eth_private *mp;
655 mp = container_of(napi, struct mv643xx_eth_private, napi);
657 #ifdef MV643XX_ETH_TX_FAST_REFILL
658 if (++mp->tx_clean_threshold > 5) {
659 mp->tx_clean_threshold = 0;
660 for (i = 0; i < 8; i++)
661 if (mp->txq_mask & (1 << i))
662 txq_reclaim(mp->txq + i, 0);
664 if (netif_carrier_ok(mp->dev)) {
665 spin_lock_irq(&mp->lock);
666 __txq_maybe_wake(mp->txq + mp->txq_primary);
667 spin_unlock_irq(&mp->lock);
673 for (i = 7; rx < budget && i >= 0; i--)
674 if (mp->rxq_mask & (1 << i))
675 rx += rxq_process(mp->rxq + i, budget - rx);
678 netif_rx_complete(mp->dev, napi);
679 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
687 /* tx ***********************************************************************/
688 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
692 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
693 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
694 if (fragp->size <= 8 && fragp->page_offset & 7)
701 static int txq_alloc_desc_index(struct tx_queue *txq)
705 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
707 tx_desc_curr = txq->tx_curr_desc++;
708 if (txq->tx_curr_desc == txq->tx_ring_size)
709 txq->tx_curr_desc = 0;
711 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
716 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
718 int nr_frags = skb_shinfo(skb)->nr_frags;
721 for (frag = 0; frag < nr_frags; frag++) {
722 skb_frag_t *this_frag;
724 struct tx_desc *desc;
726 this_frag = &skb_shinfo(skb)->frags[frag];
727 tx_index = txq_alloc_desc_index(txq);
728 desc = &txq->tx_desc_area[tx_index];
731 * The last fragment will generate an interrupt
732 * which will free the skb on TX completion.
734 if (frag == nr_frags - 1) {
735 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
736 ZERO_PADDING | TX_LAST_DESC |
738 txq->tx_skb[tx_index] = skb;
740 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
741 txq->tx_skb[tx_index] = NULL;
745 desc->byte_cnt = this_frag->size;
746 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
747 this_frag->page_offset,
753 static inline __be16 sum16_as_be(__sum16 sum)
755 return (__force __be16)sum;
758 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
760 struct mv643xx_eth_private *mp = txq_to_mp(txq);
761 int nr_frags = skb_shinfo(skb)->nr_frags;
763 struct tx_desc *desc;
767 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
769 tx_index = txq_alloc_desc_index(txq);
770 desc = &txq->tx_desc_area[tx_index];
773 txq_submit_frag_skb(txq, skb);
775 length = skb_headlen(skb);
776 txq->tx_skb[tx_index] = NULL;
778 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
780 txq->tx_skb[tx_index] = skb;
783 desc->byte_cnt = length;
784 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
786 if (skb->ip_summed == CHECKSUM_PARTIAL) {
789 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
790 skb->protocol != htons(ETH_P_8021Q));
792 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
794 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
796 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
797 switch (mac_hdr_len - ETH_HLEN) {
801 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
804 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
807 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
808 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
812 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
813 "mac header length is %d?!\n", mac_hdr_len);
817 switch (ip_hdr(skb)->protocol) {
819 cmd_sts |= UDP_FRAME;
820 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
823 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
829 /* Errata BTS #50, IHL must be 5 if no HW checksum */
830 cmd_sts |= 5 << TX_IHL_SHIFT;
834 /* ensure all other descriptors are written before first cmd_sts */
836 desc->cmd_sts = cmd_sts;
838 /* clear TX_END interrupt status */
839 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
840 rdl(mp, INT_CAUSE(mp->port_num));
842 /* ensure all descriptors are written before poking hardware */
846 txq->tx_desc_count += nr_frags + 1;
849 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
851 struct mv643xx_eth_private *mp = netdev_priv(dev);
852 struct net_device_stats *stats = &dev->stats;
853 struct tx_queue *txq;
856 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
858 dev_printk(KERN_DEBUG, &dev->dev,
859 "failed to linearize skb with tiny "
860 "unaligned fragment\n");
861 return NETDEV_TX_BUSY;
864 spin_lock_irqsave(&mp->lock, flags);
866 txq = mp->txq + mp->txq_primary;
868 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
869 spin_unlock_irqrestore(&mp->lock, flags);
870 if (txq->index == mp->txq_primary && net_ratelimit())
871 dev_printk(KERN_ERR, &dev->dev,
872 "primary tx queue full?!\n");
877 txq_submit_skb(txq, skb);
878 stats->tx_bytes += skb->len;
880 dev->trans_start = jiffies;
882 if (txq->index == mp->txq_primary) {
885 entries_left = txq->tx_ring_size - txq->tx_desc_count;
886 if (entries_left < MAX_DESCS_PER_SKB)
887 netif_stop_queue(dev);
890 spin_unlock_irqrestore(&mp->lock, flags);
896 /* tx rate control **********************************************************/
898 * Set total maximum TX rate (shared by all TX queues for this port)
899 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
901 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
907 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
908 if (token_rate > 1023)
911 mtu = (mp->dev->mtu + 255) >> 8;
915 bucket_size = (burst + 255) >> 8;
916 if (bucket_size > 65535)
919 if (mp->shared->tx_bw_control_moved) {
920 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
921 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
922 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
924 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
925 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
926 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
930 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
932 struct mv643xx_eth_private *mp = txq_to_mp(txq);
936 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
937 if (token_rate > 1023)
940 bucket_size = (burst + 255) >> 8;
941 if (bucket_size > 65535)
944 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
945 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
946 (bucket_size << 10) | token_rate);
949 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
951 struct mv643xx_eth_private *mp = txq_to_mp(txq);
956 * Turn on fixed priority mode.
958 if (mp->shared->tx_bw_control_moved)
959 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
961 off = TXQ_FIX_PRIO_CONF(mp->port_num);
964 val |= 1 << txq->index;
968 static void txq_set_wrr(struct tx_queue *txq, int weight)
970 struct mv643xx_eth_private *mp = txq_to_mp(txq);
975 * Turn off fixed priority mode.
977 if (mp->shared->tx_bw_control_moved)
978 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
980 off = TXQ_FIX_PRIO_CONF(mp->port_num);
983 val &= ~(1 << txq->index);
987 * Configure WRR weight for this queue.
989 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
992 val = (val & ~0xff) | (weight & 0xff);
997 /* mii management interface *************************************************/
998 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1000 struct mv643xx_eth_shared_private *msp = dev_id;
1002 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1003 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1004 wake_up(&msp->smi_busy_wait);
1011 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1013 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1016 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1018 if (msp->err_interrupt == NO_IRQ) {
1021 for (i = 0; !smi_is_done(msp); i++) {
1030 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1031 msecs_to_jiffies(100)))
1037 static int smi_reg_read(struct mv643xx_eth_private *mp,
1038 unsigned int addr, unsigned int reg)
1040 struct mv643xx_eth_shared_private *msp = mp->shared_smi;
1041 void __iomem *smi_reg = msp->base + SMI_REG;
1044 mutex_lock(&msp->phy_lock);
1046 if (smi_wait_ready(msp)) {
1047 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1052 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1054 if (smi_wait_ready(msp)) {
1055 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1060 ret = readl(smi_reg);
1061 if (!(ret & SMI_READ_VALID)) {
1062 printk("%s: SMI bus read not valid\n", mp->dev->name);
1070 mutex_unlock(&msp->phy_lock);
1075 static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1076 unsigned int reg, unsigned int value)
1078 struct mv643xx_eth_shared_private *msp = mp->shared_smi;
1079 void __iomem *smi_reg = msp->base + SMI_REG;
1081 mutex_lock(&msp->phy_lock);
1083 if (smi_wait_ready(msp)) {
1084 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1085 mutex_unlock(&msp->phy_lock);
1089 writel(SMI_OPCODE_WRITE | (reg << 21) |
1090 (addr << 16) | (value & 0xffff), smi_reg);
1092 mutex_unlock(&msp->phy_lock);
1098 /* mib counters *************************************************************/
1099 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1101 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1104 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1108 for (i = 0; i < 0x80; i += 4)
1112 static void mib_counters_update(struct mv643xx_eth_private *mp)
1114 struct mib_counters *p = &mp->mib_counters;
1116 p->good_octets_received += mib_read(mp, 0x00);
1117 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1118 p->bad_octets_received += mib_read(mp, 0x08);
1119 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1120 p->good_frames_received += mib_read(mp, 0x10);
1121 p->bad_frames_received += mib_read(mp, 0x14);
1122 p->broadcast_frames_received += mib_read(mp, 0x18);
1123 p->multicast_frames_received += mib_read(mp, 0x1c);
1124 p->frames_64_octets += mib_read(mp, 0x20);
1125 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1126 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1127 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1128 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1129 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1130 p->good_octets_sent += mib_read(mp, 0x38);
1131 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1132 p->good_frames_sent += mib_read(mp, 0x40);
1133 p->excessive_collision += mib_read(mp, 0x44);
1134 p->multicast_frames_sent += mib_read(mp, 0x48);
1135 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1136 p->unrec_mac_control_received += mib_read(mp, 0x50);
1137 p->fc_sent += mib_read(mp, 0x54);
1138 p->good_fc_received += mib_read(mp, 0x58);
1139 p->bad_fc_received += mib_read(mp, 0x5c);
1140 p->undersize_received += mib_read(mp, 0x60);
1141 p->fragments_received += mib_read(mp, 0x64);
1142 p->oversize_received += mib_read(mp, 0x68);
1143 p->jabber_received += mib_read(mp, 0x6c);
1144 p->mac_receive_error += mib_read(mp, 0x70);
1145 p->bad_crc_event += mib_read(mp, 0x74);
1146 p->collision += mib_read(mp, 0x78);
1147 p->late_collision += mib_read(mp, 0x7c);
1151 /* ethtool ******************************************************************/
1152 struct mv643xx_eth_stats {
1153 char stat_string[ETH_GSTRING_LEN];
1160 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1161 offsetof(struct net_device, stats.m), -1 }
1163 #define MIBSTAT(m) \
1164 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1165 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1167 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1176 MIBSTAT(good_octets_received),
1177 MIBSTAT(bad_octets_received),
1178 MIBSTAT(internal_mac_transmit_err),
1179 MIBSTAT(good_frames_received),
1180 MIBSTAT(bad_frames_received),
1181 MIBSTAT(broadcast_frames_received),
1182 MIBSTAT(multicast_frames_received),
1183 MIBSTAT(frames_64_octets),
1184 MIBSTAT(frames_65_to_127_octets),
1185 MIBSTAT(frames_128_to_255_octets),
1186 MIBSTAT(frames_256_to_511_octets),
1187 MIBSTAT(frames_512_to_1023_octets),
1188 MIBSTAT(frames_1024_to_max_octets),
1189 MIBSTAT(good_octets_sent),
1190 MIBSTAT(good_frames_sent),
1191 MIBSTAT(excessive_collision),
1192 MIBSTAT(multicast_frames_sent),
1193 MIBSTAT(broadcast_frames_sent),
1194 MIBSTAT(unrec_mac_control_received),
1196 MIBSTAT(good_fc_received),
1197 MIBSTAT(bad_fc_received),
1198 MIBSTAT(undersize_received),
1199 MIBSTAT(fragments_received),
1200 MIBSTAT(oversize_received),
1201 MIBSTAT(jabber_received),
1202 MIBSTAT(mac_receive_error),
1203 MIBSTAT(bad_crc_event),
1205 MIBSTAT(late_collision),
1208 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1210 struct mv643xx_eth_private *mp = netdev_priv(dev);
1213 err = mii_ethtool_gset(&mp->mii, cmd);
1216 * The MAC does not support 1000baseT_Half.
1218 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1219 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1224 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1226 struct mv643xx_eth_private *mp = netdev_priv(dev);
1229 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1231 cmd->supported = SUPPORTED_MII;
1232 cmd->advertising = ADVERTISED_MII;
1233 switch (port_status & PORT_SPEED_MASK) {
1235 cmd->speed = SPEED_10;
1237 case PORT_SPEED_100:
1238 cmd->speed = SPEED_100;
1240 case PORT_SPEED_1000:
1241 cmd->speed = SPEED_1000;
1247 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1248 cmd->port = PORT_MII;
1249 cmd->phy_address = 0;
1250 cmd->transceiver = XCVR_INTERNAL;
1251 cmd->autoneg = AUTONEG_DISABLE;
1258 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1260 struct mv643xx_eth_private *mp = netdev_priv(dev);
1263 * The MAC does not support 1000baseT_Half.
1265 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1267 return mii_ethtool_sset(&mp->mii, cmd);
1270 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1275 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1276 struct ethtool_drvinfo *drvinfo)
1278 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1279 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1280 strncpy(drvinfo->fw_version, "N/A", 32);
1281 strncpy(drvinfo->bus_info, "platform", 32);
1282 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1285 static int mv643xx_eth_nway_reset(struct net_device *dev)
1287 struct mv643xx_eth_private *mp = netdev_priv(dev);
1289 return mii_nway_restart(&mp->mii);
1292 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1297 static u32 mv643xx_eth_get_link(struct net_device *dev)
1299 struct mv643xx_eth_private *mp = netdev_priv(dev);
1301 return mii_link_ok(&mp->mii);
1304 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1309 static void mv643xx_eth_get_strings(struct net_device *dev,
1310 uint32_t stringset, uint8_t *data)
1314 if (stringset == ETH_SS_STATS) {
1315 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1316 memcpy(data + i * ETH_GSTRING_LEN,
1317 mv643xx_eth_stats[i].stat_string,
1323 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1324 struct ethtool_stats *stats,
1327 struct mv643xx_eth_private *mp = netdev_priv(dev);
1330 mib_counters_update(mp);
1332 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1333 const struct mv643xx_eth_stats *stat;
1336 stat = mv643xx_eth_stats + i;
1338 if (stat->netdev_off >= 0)
1339 p = ((void *)mp->dev) + stat->netdev_off;
1341 p = ((void *)mp) + stat->mp_off;
1343 data[i] = (stat->sizeof_stat == 8) ?
1344 *(uint64_t *)p : *(uint32_t *)p;
1348 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1350 if (sset == ETH_SS_STATS)
1351 return ARRAY_SIZE(mv643xx_eth_stats);
1356 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1357 .get_settings = mv643xx_eth_get_settings,
1358 .set_settings = mv643xx_eth_set_settings,
1359 .get_drvinfo = mv643xx_eth_get_drvinfo,
1360 .nway_reset = mv643xx_eth_nway_reset,
1361 .get_link = mv643xx_eth_get_link,
1362 .set_sg = ethtool_op_set_sg,
1363 .get_strings = mv643xx_eth_get_strings,
1364 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1365 .get_sset_count = mv643xx_eth_get_sset_count,
1368 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1369 .get_settings = mv643xx_eth_get_settings_phyless,
1370 .set_settings = mv643xx_eth_set_settings_phyless,
1371 .get_drvinfo = mv643xx_eth_get_drvinfo,
1372 .nway_reset = mv643xx_eth_nway_reset_phyless,
1373 .get_link = mv643xx_eth_get_link_phyless,
1374 .set_sg = ethtool_op_set_sg,
1375 .get_strings = mv643xx_eth_get_strings,
1376 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1377 .get_sset_count = mv643xx_eth_get_sset_count,
1381 /* address handling *********************************************************/
1382 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1387 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1388 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1390 addr[0] = (mac_h >> 24) & 0xff;
1391 addr[1] = (mac_h >> 16) & 0xff;
1392 addr[2] = (mac_h >> 8) & 0xff;
1393 addr[3] = mac_h & 0xff;
1394 addr[4] = (mac_l >> 8) & 0xff;
1395 addr[5] = mac_l & 0xff;
1398 static void init_mac_tables(struct mv643xx_eth_private *mp)
1402 for (i = 0; i < 0x100; i += 4) {
1403 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1404 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1407 for (i = 0; i < 0x10; i += 4)
1408 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1411 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1412 int table, unsigned char entry)
1414 unsigned int table_reg;
1416 /* Set "accepts frame bit" at specified table entry */
1417 table_reg = rdl(mp, table + (entry & 0xfc));
1418 table_reg |= 0x01 << (8 * (entry & 3));
1419 wrl(mp, table + (entry & 0xfc), table_reg);
1422 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1428 mac_l = (addr[4] << 8) | addr[5];
1429 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1431 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1432 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1434 table = UNICAST_TABLE(mp->port_num);
1435 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1438 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1440 struct mv643xx_eth_private *mp = netdev_priv(dev);
1442 /* +2 is for the offset of the HW addr type */
1443 memcpy(dev->dev_addr, addr + 2, 6);
1445 init_mac_tables(mp);
1446 uc_addr_set(mp, dev->dev_addr);
1451 static int addr_crc(unsigned char *addr)
1456 for (i = 0; i < 6; i++) {
1459 crc = (crc ^ addr[i]) << 8;
1460 for (j = 7; j >= 0; j--) {
1461 if (crc & (0x100 << j))
1469 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1471 struct mv643xx_eth_private *mp = netdev_priv(dev);
1473 struct dev_addr_list *addr;
1476 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1477 if (dev->flags & IFF_PROMISC)
1478 port_config |= UNICAST_PROMISCUOUS_MODE;
1480 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1481 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1483 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1484 int port_num = mp->port_num;
1485 u32 accept = 0x01010101;
1487 for (i = 0; i < 0x100; i += 4) {
1488 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1489 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1494 for (i = 0; i < 0x100; i += 4) {
1495 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1496 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1499 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1500 u8 *a = addr->da_addr;
1503 if (addr->da_addrlen != 6)
1506 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1507 table = SPECIAL_MCAST_TABLE(mp->port_num);
1508 set_filter_table_entry(mp, table, a[5]);
1510 int crc = addr_crc(a);
1512 table = OTHER_MCAST_TABLE(mp->port_num);
1513 set_filter_table_entry(mp, table, crc);
1519 /* rx/tx queue initialisation ***********************************************/
1520 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1522 struct rx_queue *rxq = mp->rxq + index;
1523 struct rx_desc *rx_desc;
1529 rxq->rx_ring_size = mp->default_rx_ring_size;
1531 rxq->rx_desc_count = 0;
1532 rxq->rx_curr_desc = 0;
1533 rxq->rx_used_desc = 0;
1535 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1537 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
1538 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1539 mp->rx_desc_sram_size);
1540 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1542 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1547 if (rxq->rx_desc_area == NULL) {
1548 dev_printk(KERN_ERR, &mp->dev->dev,
1549 "can't allocate rx ring (%d bytes)\n", size);
1552 memset(rxq->rx_desc_area, 0, size);
1554 rxq->rx_desc_area_size = size;
1555 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1557 if (rxq->rx_skb == NULL) {
1558 dev_printk(KERN_ERR, &mp->dev->dev,
1559 "can't allocate rx skb ring\n");
1563 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1564 for (i = 0; i < rxq->rx_ring_size; i++) {
1568 if (nexti == rxq->rx_ring_size)
1571 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1572 nexti * sizeof(struct rx_desc);
1575 init_timer(&rxq->rx_oom);
1576 rxq->rx_oom.data = (unsigned long)rxq;
1577 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1583 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
1584 iounmap(rxq->rx_desc_area);
1586 dma_free_coherent(NULL, size,
1594 static void rxq_deinit(struct rx_queue *rxq)
1596 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1601 del_timer_sync(&rxq->rx_oom);
1603 for (i = 0; i < rxq->rx_ring_size; i++) {
1604 if (rxq->rx_skb[i]) {
1605 dev_kfree_skb(rxq->rx_skb[i]);
1606 rxq->rx_desc_count--;
1610 if (rxq->rx_desc_count) {
1611 dev_printk(KERN_ERR, &mp->dev->dev,
1612 "error freeing rx ring -- %d skbs stuck\n",
1613 rxq->rx_desc_count);
1616 if (rxq->index == mp->rxq_primary &&
1617 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1618 iounmap(rxq->rx_desc_area);
1620 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1621 rxq->rx_desc_area, rxq->rx_desc_dma);
1626 static int txq_init(struct mv643xx_eth_private *mp, int index)
1628 struct tx_queue *txq = mp->txq + index;
1629 struct tx_desc *tx_desc;
1635 txq->tx_ring_size = mp->default_tx_ring_size;
1637 txq->tx_desc_count = 0;
1638 txq->tx_curr_desc = 0;
1639 txq->tx_used_desc = 0;
1641 size = txq->tx_ring_size * sizeof(struct tx_desc);
1643 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
1644 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1645 mp->tx_desc_sram_size);
1646 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1648 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1653 if (txq->tx_desc_area == NULL) {
1654 dev_printk(KERN_ERR, &mp->dev->dev,
1655 "can't allocate tx ring (%d bytes)\n", size);
1658 memset(txq->tx_desc_area, 0, size);
1660 txq->tx_desc_area_size = size;
1661 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1663 if (txq->tx_skb == NULL) {
1664 dev_printk(KERN_ERR, &mp->dev->dev,
1665 "can't allocate tx skb ring\n");
1669 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1670 for (i = 0; i < txq->tx_ring_size; i++) {
1671 struct tx_desc *txd = tx_desc + i;
1675 if (nexti == txq->tx_ring_size)
1679 txd->next_desc_ptr = txq->tx_desc_dma +
1680 nexti * sizeof(struct tx_desc);
1687 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
1688 iounmap(txq->tx_desc_area);
1690 dma_free_coherent(NULL, size,
1698 static void txq_reclaim(struct tx_queue *txq, int force)
1700 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1701 unsigned long flags;
1703 spin_lock_irqsave(&mp->lock, flags);
1704 while (txq->tx_desc_count > 0) {
1706 struct tx_desc *desc;
1708 struct sk_buff *skb;
1712 tx_index = txq->tx_used_desc;
1713 desc = &txq->tx_desc_area[tx_index];
1714 cmd_sts = desc->cmd_sts;
1716 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1719 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1722 txq->tx_used_desc = tx_index + 1;
1723 if (txq->tx_used_desc == txq->tx_ring_size)
1724 txq->tx_used_desc = 0;
1725 txq->tx_desc_count--;
1727 addr = desc->buf_ptr;
1728 count = desc->byte_cnt;
1729 skb = txq->tx_skb[tx_index];
1730 txq->tx_skb[tx_index] = NULL;
1732 if (cmd_sts & ERROR_SUMMARY) {
1733 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1734 mp->dev->stats.tx_errors++;
1738 * Drop mp->lock while we free the skb.
1740 spin_unlock_irqrestore(&mp->lock, flags);
1742 if (cmd_sts & TX_FIRST_DESC)
1743 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1745 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1748 dev_kfree_skb_irq(skb);
1750 spin_lock_irqsave(&mp->lock, flags);
1752 spin_unlock_irqrestore(&mp->lock, flags);
1755 static void txq_deinit(struct tx_queue *txq)
1757 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1760 txq_reclaim(txq, 1);
1762 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1764 if (txq->index == mp->txq_primary &&
1765 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1766 iounmap(txq->tx_desc_area);
1768 dma_free_coherent(NULL, txq->tx_desc_area_size,
1769 txq->tx_desc_area, txq->tx_desc_dma);
1775 /* netdev ops and related ***************************************************/
1776 static void handle_link_event(struct mv643xx_eth_private *mp)
1778 struct net_device *dev = mp->dev;
1784 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1785 if (!(port_status & LINK_UP)) {
1786 if (netif_carrier_ok(dev)) {
1789 printk(KERN_INFO "%s: link down\n", dev->name);
1791 netif_carrier_off(dev);
1792 netif_stop_queue(dev);
1794 for (i = 0; i < 8; i++) {
1795 struct tx_queue *txq = mp->txq + i;
1797 if (mp->txq_mask & (1 << i)) {
1798 txq_reclaim(txq, 1);
1799 txq_reset_hw_ptr(txq);
1806 switch (port_status & PORT_SPEED_MASK) {
1810 case PORT_SPEED_100:
1813 case PORT_SPEED_1000:
1820 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1821 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1823 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1824 "flow control %sabled\n", dev->name,
1825 speed, duplex ? "full" : "half",
1828 if (!netif_carrier_ok(dev)) {
1829 netif_carrier_on(dev);
1830 netif_wake_queue(dev);
1834 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1836 struct net_device *dev = (struct net_device *)dev_id;
1837 struct mv643xx_eth_private *mp = netdev_priv(dev);
1841 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1842 (INT_TX_END | INT_RX | INT_EXT);
1847 if (int_cause & INT_EXT) {
1848 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1849 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1850 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1853 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK))
1854 handle_link_event(mp);
1857 * RxBuffer or RxError set for any of the 8 queues?
1859 #ifdef MV643XX_ETH_NAPI
1860 if (int_cause & INT_RX) {
1861 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_RX));
1862 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1863 rdl(mp, INT_MASK(mp->port_num));
1865 netif_rx_schedule(dev, &mp->napi);
1868 if (int_cause & INT_RX) {
1871 for (i = 7; i >= 0; i--)
1872 if (mp->rxq_mask & (1 << i))
1873 rxq_process(mp->rxq + i, INT_MAX);
1878 * TxBuffer or TxError set for any of the 8 queues?
1880 if (int_cause_ext & INT_EXT_TX) {
1883 for (i = 0; i < 8; i++)
1884 if (mp->txq_mask & (1 << i))
1885 txq_reclaim(mp->txq + i, 0);
1888 * Enough space again in the primary TX queue for a
1891 if (netif_carrier_ok(dev)) {
1892 spin_lock(&mp->lock);
1893 __txq_maybe_wake(mp->txq + mp->txq_primary);
1894 spin_unlock(&mp->lock);
1899 * Any TxEnd interrupts?
1901 if (int_cause & INT_TX_END) {
1904 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1906 spin_lock(&mp->lock);
1907 for (i = 0; i < 8; i++) {
1908 struct tx_queue *txq = mp->txq + i;
1912 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1916 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1917 expected_ptr = (u32)txq->tx_desc_dma +
1918 txq->tx_curr_desc * sizeof(struct tx_desc);
1920 if (hw_desc_ptr != expected_ptr)
1923 spin_unlock(&mp->lock);
1929 static void phy_reset(struct mv643xx_eth_private *mp)
1933 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1938 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1942 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1943 } while (data >= 0 && data & BMCR_RESET);
1946 static void port_start(struct mv643xx_eth_private *mp)
1952 * Perform PHY reset, if there is a PHY.
1954 if (mp->phy_addr != -1) {
1955 struct ethtool_cmd cmd;
1957 mv643xx_eth_get_settings(mp->dev, &cmd);
1959 mv643xx_eth_set_settings(mp->dev, &cmd);
1963 * Configure basic link parameters.
1965 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1967 pscr |= SERIAL_PORT_ENABLE;
1968 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1970 pscr |= DO_NOT_FORCE_LINK_FAIL;
1971 if (mp->phy_addr == -1)
1972 pscr |= FORCE_LINK_PASS;
1973 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1975 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1978 * Configure TX path and queues.
1980 tx_set_rate(mp, 1000000000, 16777216);
1981 for (i = 0; i < 8; i++) {
1982 struct tx_queue *txq = mp->txq + i;
1984 if ((mp->txq_mask & (1 << i)) == 0)
1987 txq_reset_hw_ptr(txq);
1988 txq_set_rate(txq, 1000000000, 16777216);
1989 txq_set_fixed_prio_mode(txq);
1993 * Add configured unicast address to address filter table.
1995 uc_addr_set(mp, mp->dev->dev_addr);
1998 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1999 * frames to RX queue #0.
2001 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
2004 * Treat BPDUs as normal multicasts, and disable partition mode.
2006 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
2009 * Enable the receive queues.
2011 for (i = 0; i < 8; i++) {
2012 struct rx_queue *rxq = mp->rxq + i;
2013 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
2016 if ((mp->rxq_mask & (1 << i)) == 0)
2019 addr = (u32)rxq->rx_desc_dma;
2020 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2027 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2029 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2032 val = rdl(mp, SDMA_CONFIG(mp->port_num));
2033 if (mp->shared->extended_rx_coal_limit) {
2037 val |= (coal & 0x8000) << 10;
2038 val |= (coal & 0x7fff) << 7;
2043 val |= (coal & 0x3fff) << 8;
2045 wrl(mp, SDMA_CONFIG(mp->port_num), val);
2048 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2050 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2054 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2057 static int mv643xx_eth_open(struct net_device *dev)
2059 struct mv643xx_eth_private *mp = netdev_priv(dev);
2063 wrl(mp, INT_CAUSE(mp->port_num), 0);
2064 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2065 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2067 err = request_irq(dev->irq, mv643xx_eth_irq,
2068 IRQF_SHARED, dev->name, dev);
2070 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2074 init_mac_tables(mp);
2076 for (i = 0; i < 8; i++) {
2077 if ((mp->rxq_mask & (1 << i)) == 0)
2080 err = rxq_init(mp, i);
2083 if (mp->rxq_mask & (1 << i))
2084 rxq_deinit(mp->rxq + i);
2088 rxq_refill(mp->rxq + i);
2091 for (i = 0; i < 8; i++) {
2092 if ((mp->txq_mask & (1 << i)) == 0)
2095 err = txq_init(mp, i);
2098 if (mp->txq_mask & (1 << i))
2099 txq_deinit(mp->txq + i);
2104 #ifdef MV643XX_ETH_NAPI
2105 napi_enable(&mp->napi);
2108 netif_carrier_off(dev);
2109 netif_stop_queue(dev);
2116 wrl(mp, INT_MASK_EXT(mp->port_num),
2117 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
2119 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2125 for (i = 0; i < 8; i++)
2126 if (mp->rxq_mask & (1 << i))
2127 rxq_deinit(mp->rxq + i);
2129 free_irq(dev->irq, dev);
2134 static void port_reset(struct mv643xx_eth_private *mp)
2139 for (i = 0; i < 8; i++) {
2140 if (mp->rxq_mask & (1 << i))
2141 rxq_disable(mp->rxq + i);
2142 if (mp->txq_mask & (1 << i))
2143 txq_disable(mp->txq + i);
2147 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2149 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2154 /* Reset the Enable bit in the Configuration Register */
2155 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2156 data &= ~(SERIAL_PORT_ENABLE |
2157 DO_NOT_FORCE_LINK_FAIL |
2159 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2162 static int mv643xx_eth_stop(struct net_device *dev)
2164 struct mv643xx_eth_private *mp = netdev_priv(dev);
2167 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2168 rdl(mp, INT_MASK(mp->port_num));
2170 #ifdef MV643XX_ETH_NAPI
2171 napi_disable(&mp->napi);
2173 netif_carrier_off(dev);
2174 netif_stop_queue(dev);
2176 free_irq(dev->irq, dev);
2179 mib_counters_update(mp);
2181 for (i = 0; i < 8; i++) {
2182 if (mp->rxq_mask & (1 << i))
2183 rxq_deinit(mp->rxq + i);
2184 if (mp->txq_mask & (1 << i))
2185 txq_deinit(mp->txq + i);
2191 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2193 struct mv643xx_eth_private *mp = netdev_priv(dev);
2195 if (mp->phy_addr != -1)
2196 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2201 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2203 struct mv643xx_eth_private *mp = netdev_priv(dev);
2205 if (new_mtu < 64 || new_mtu > 9500)
2209 tx_set_rate(mp, 1000000000, 16777216);
2211 if (!netif_running(dev))
2215 * Stop and then re-open the interface. This will allocate RX
2216 * skbs of the new MTU.
2217 * There is a possible danger that the open will not succeed,
2218 * due to memory being full.
2220 mv643xx_eth_stop(dev);
2221 if (mv643xx_eth_open(dev)) {
2222 dev_printk(KERN_ERR, &dev->dev,
2223 "fatal error on re-opening device after "
2230 static void tx_timeout_task(struct work_struct *ugly)
2232 struct mv643xx_eth_private *mp;
2234 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2235 if (netif_running(mp->dev)) {
2236 netif_stop_queue(mp->dev);
2241 __txq_maybe_wake(mp->txq + mp->txq_primary);
2245 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2247 struct mv643xx_eth_private *mp = netdev_priv(dev);
2249 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2251 schedule_work(&mp->tx_timeout_task);
2254 #ifdef CONFIG_NET_POLL_CONTROLLER
2255 static void mv643xx_eth_netpoll(struct net_device *dev)
2257 struct mv643xx_eth_private *mp = netdev_priv(dev);
2259 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2260 rdl(mp, INT_MASK(mp->port_num));
2262 mv643xx_eth_irq(dev->irq, dev);
2264 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2268 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2270 struct mv643xx_eth_private *mp = netdev_priv(dev);
2271 return smi_reg_read(mp, addr, reg);
2274 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2276 struct mv643xx_eth_private *mp = netdev_priv(dev);
2277 smi_reg_write(mp, addr, reg, val);
2281 /* platform glue ************************************************************/
2283 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2284 struct mbus_dram_target_info *dram)
2286 void __iomem *base = msp->base;
2291 for (i = 0; i < 6; i++) {
2292 writel(0, base + WINDOW_BASE(i));
2293 writel(0, base + WINDOW_SIZE(i));
2295 writel(0, base + WINDOW_REMAP_HIGH(i));
2301 for (i = 0; i < dram->num_cs; i++) {
2302 struct mbus_dram_window *cs = dram->cs + i;
2304 writel((cs->base & 0xffff0000) |
2305 (cs->mbus_attr << 8) |
2306 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2307 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2309 win_enable &= ~(1 << i);
2310 win_protect |= 3 << (2 * i);
2313 writel(win_enable, base + WINDOW_BAR_ENABLE);
2314 msp->win_protect = win_protect;
2317 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2320 * Check whether we have a 14-bit coal limit field in bits
2321 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2322 * SDMA config register.
2324 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2325 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2326 msp->extended_rx_coal_limit = 1;
2328 msp->extended_rx_coal_limit = 0;
2331 * Check whether the TX rate control registers are in the
2332 * old or the new place.
2334 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2335 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2336 msp->tx_bw_control_moved = 1;
2338 msp->tx_bw_control_moved = 0;
2341 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2343 static int mv643xx_eth_version_printed = 0;
2344 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2345 struct mv643xx_eth_shared_private *msp;
2346 struct resource *res;
2349 if (!mv643xx_eth_version_printed++)
2350 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2351 "driver version %s\n", mv643xx_eth_driver_version);
2354 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2359 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2362 memset(msp, 0, sizeof(*msp));
2364 msp->base = ioremap(res->start, res->end - res->start + 1);
2365 if (msp->base == NULL)
2368 mutex_init(&msp->phy_lock);
2370 msp->err_interrupt = NO_IRQ;
2371 init_waitqueue_head(&msp->smi_busy_wait);
2374 * Check whether the error interrupt is hooked up.
2376 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2380 err = request_irq(res->start, mv643xx_eth_err_irq,
2381 IRQF_SHARED, "mv643xx_eth", msp);
2383 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2384 msp->err_interrupt = res->start;
2389 * (Re-)program MBUS remapping windows if we are asked to.
2391 if (pd != NULL && pd->dram != NULL)
2392 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2395 * Detect hardware parameters.
2397 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2398 infer_hw_params(msp);
2400 platform_set_drvdata(pdev, msp);
2410 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2412 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2414 if (msp->err_interrupt != NO_IRQ)
2415 free_irq(msp->err_interrupt, msp);
2422 static struct platform_driver mv643xx_eth_shared_driver = {
2423 .probe = mv643xx_eth_shared_probe,
2424 .remove = mv643xx_eth_shared_remove,
2426 .name = MV643XX_ETH_SHARED_NAME,
2427 .owner = THIS_MODULE,
2431 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2433 int addr_shift = 5 * mp->port_num;
2436 data = rdl(mp, PHY_ADDR);
2437 data &= ~(0x1f << addr_shift);
2438 data |= (phy_addr & 0x1f) << addr_shift;
2439 wrl(mp, PHY_ADDR, data);
2442 static int phy_addr_get(struct mv643xx_eth_private *mp)
2446 data = rdl(mp, PHY_ADDR);
2448 return (data >> (5 * mp->port_num)) & 0x1f;
2451 static void set_params(struct mv643xx_eth_private *mp,
2452 struct mv643xx_eth_platform_data *pd)
2454 struct net_device *dev = mp->dev;
2456 if (is_valid_ether_addr(pd->mac_addr))
2457 memcpy(dev->dev_addr, pd->mac_addr, 6);
2459 uc_addr_get(mp, dev->dev_addr);
2461 if (pd->phy_addr == -1) {
2462 mp->shared_smi = NULL;
2465 mp->shared_smi = mp->shared;
2466 if (pd->shared_smi != NULL)
2467 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2469 if (pd->force_phy_addr || pd->phy_addr) {
2470 mp->phy_addr = pd->phy_addr & 0x3f;
2471 phy_addr_set(mp, mp->phy_addr);
2473 mp->phy_addr = phy_addr_get(mp);
2477 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2478 if (pd->rx_queue_size)
2479 mp->default_rx_ring_size = pd->rx_queue_size;
2480 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2481 mp->rx_desc_sram_size = pd->rx_sram_size;
2483 if (pd->rx_queue_mask)
2484 mp->rxq_mask = pd->rx_queue_mask;
2486 mp->rxq_mask = 0x01;
2487 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2489 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2490 if (pd->tx_queue_size)
2491 mp->default_tx_ring_size = pd->tx_queue_size;
2492 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2493 mp->tx_desc_sram_size = pd->tx_sram_size;
2495 if (pd->tx_queue_mask)
2496 mp->txq_mask = pd->tx_queue_mask;
2498 mp->txq_mask = 0x01;
2499 mp->txq_primary = fls(mp->txq_mask) - 1;
2502 static int phy_detect(struct mv643xx_eth_private *mp)
2507 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2511 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2514 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2518 if (((data ^ data2) & BMCR_ANENABLE) == 0)
2521 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
2526 static int phy_init(struct mv643xx_eth_private *mp,
2527 struct mv643xx_eth_platform_data *pd)
2529 struct ethtool_cmd cmd;
2532 err = phy_detect(mp);
2534 dev_printk(KERN_INFO, &mp->dev->dev,
2535 "no PHY detected at addr %d\n", mp->phy_addr);
2540 mp->mii.phy_id = mp->phy_addr;
2541 mp->mii.phy_id_mask = 0x3f;
2542 mp->mii.reg_num_mask = 0x1f;
2543 mp->mii.dev = mp->dev;
2544 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2545 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2547 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2549 memset(&cmd, 0, sizeof(cmd));
2551 cmd.port = PORT_MII;
2552 cmd.transceiver = XCVR_INTERNAL;
2553 cmd.phy_address = mp->phy_addr;
2554 if (pd->speed == 0) {
2555 cmd.autoneg = AUTONEG_ENABLE;
2556 cmd.speed = SPEED_100;
2557 cmd.advertising = ADVERTISED_10baseT_Half |
2558 ADVERTISED_10baseT_Full |
2559 ADVERTISED_100baseT_Half |
2560 ADVERTISED_100baseT_Full;
2561 if (mp->mii.supports_gmii)
2562 cmd.advertising |= ADVERTISED_1000baseT_Full;
2564 cmd.autoneg = AUTONEG_DISABLE;
2565 cmd.speed = pd->speed;
2566 cmd.duplex = pd->duplex;
2569 mv643xx_eth_set_settings(mp->dev, &cmd);
2574 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2578 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2579 if (pscr & SERIAL_PORT_ENABLE) {
2580 pscr &= ~SERIAL_PORT_ENABLE;
2581 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2584 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2585 if (mp->phy_addr == -1) {
2586 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2587 if (speed == SPEED_1000)
2588 pscr |= SET_GMII_SPEED_TO_1000;
2589 else if (speed == SPEED_100)
2590 pscr |= SET_MII_SPEED_TO_100;
2592 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2594 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2595 if (duplex == DUPLEX_FULL)
2596 pscr |= SET_FULL_DUPLEX_MODE;
2599 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2602 static int mv643xx_eth_probe(struct platform_device *pdev)
2604 struct mv643xx_eth_platform_data *pd;
2605 struct mv643xx_eth_private *mp;
2606 struct net_device *dev;
2607 struct resource *res;
2608 DECLARE_MAC_BUF(mac);
2611 pd = pdev->dev.platform_data;
2613 dev_printk(KERN_ERR, &pdev->dev,
2614 "no mv643xx_eth_platform_data\n");
2618 if (pd->shared == NULL) {
2619 dev_printk(KERN_ERR, &pdev->dev,
2620 "no mv643xx_eth_platform_data->shared\n");
2624 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2628 mp = netdev_priv(dev);
2629 platform_set_drvdata(pdev, mp);
2631 mp->shared = platform_get_drvdata(pd->shared);
2632 mp->port_num = pd->port_number;
2635 #ifdef MV643XX_ETH_NAPI
2636 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2641 spin_lock_init(&mp->lock);
2643 mib_counters_clear(mp);
2644 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2646 if (mp->phy_addr != -1) {
2647 err = phy_init(mp, pd);
2651 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2653 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2655 init_pscr(mp, pd->speed, pd->duplex);
2658 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2660 dev->irq = res->start;
2662 dev->hard_start_xmit = mv643xx_eth_xmit;
2663 dev->open = mv643xx_eth_open;
2664 dev->stop = mv643xx_eth_stop;
2665 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2666 dev->set_mac_address = mv643xx_eth_set_mac_address;
2667 dev->do_ioctl = mv643xx_eth_ioctl;
2668 dev->change_mtu = mv643xx_eth_change_mtu;
2669 dev->tx_timeout = mv643xx_eth_tx_timeout;
2670 #ifdef CONFIG_NET_POLL_CONTROLLER
2671 dev->poll_controller = mv643xx_eth_netpoll;
2673 dev->watchdog_timeo = 2 * HZ;
2676 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2678 * Zero copy can only work if we use Discovery II memory. Else, we will
2679 * have to map the buffers to ISA memory which is only 16 MB
2681 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2682 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2685 SET_NETDEV_DEV(dev, &pdev->dev);
2687 if (mp->shared->win_protect)
2688 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2690 err = register_netdev(dev);
2694 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2695 mp->port_num, print_mac(mac, dev->dev_addr));
2697 if (dev->features & NETIF_F_SG)
2698 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
2700 if (dev->features & NETIF_F_IP_CSUM)
2701 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
2703 #ifdef MV643XX_ETH_NAPI
2704 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
2707 if (mp->tx_desc_sram_size > 0)
2708 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2718 static int mv643xx_eth_remove(struct platform_device *pdev)
2720 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2722 unregister_netdev(mp->dev);
2723 flush_scheduled_work();
2724 free_netdev(mp->dev);
2726 platform_set_drvdata(pdev, NULL);
2731 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2733 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2735 /* Mask all interrupts on ethernet port */
2736 wrl(mp, INT_MASK(mp->port_num), 0);
2737 rdl(mp, INT_MASK(mp->port_num));
2739 if (netif_running(mp->dev))
2743 static struct platform_driver mv643xx_eth_driver = {
2744 .probe = mv643xx_eth_probe,
2745 .remove = mv643xx_eth_remove,
2746 .shutdown = mv643xx_eth_shutdown,
2748 .name = MV643XX_ETH_NAME,
2749 .owner = THIS_MODULE,
2753 static int __init mv643xx_eth_init_module(void)
2757 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2759 rc = platform_driver_register(&mv643xx_eth_driver);
2761 platform_driver_unregister(&mv643xx_eth_shared_driver);
2766 module_init(mv643xx_eth_init_module);
2768 static void __exit mv643xx_eth_cleanup_module(void)
2770 platform_driver_unregister(&mv643xx_eth_driver);
2771 platform_driver_unregister(&mv643xx_eth_shared_driver);
2773 module_exit(mv643xx_eth_cleanup_module);
2775 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2776 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2777 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2778 MODULE_LICENSE("GPL");
2779 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2780 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);