2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.3";
62 * Registers shared between all ports.
64 #define PHY_ADDR 0x0000
65 #define SMI_REG 0x0004
66 #define SMI_BUSY 0x10000000
67 #define SMI_READ_VALID 0x08000000
68 #define SMI_OPCODE_READ 0x04000000
69 #define SMI_OPCODE_WRITE 0x00000000
70 #define ERR_INT_CAUSE 0x0080
71 #define ERR_INT_SMI_DONE 0x00000010
72 #define ERR_INT_MASK 0x0084
73 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
74 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
75 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
76 #define WINDOW_BAR_ENABLE 0x0290
77 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
82 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
83 #define UNICAST_PROMISCUOUS_MODE 0x00000001
84 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
85 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
86 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
87 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
88 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
89 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
90 #define TX_FIFO_EMPTY 0x00000400
91 #define TX_IN_PROGRESS 0x00000080
92 #define PORT_SPEED_MASK 0x00000030
93 #define PORT_SPEED_1000 0x00000010
94 #define PORT_SPEED_100 0x00000020
95 #define PORT_SPEED_10 0x00000000
96 #define FLOW_CONTROL_ENABLED 0x00000008
97 #define FULL_DUPLEX 0x00000004
98 #define LINK_UP 0x00000002
99 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
100 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
101 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
102 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
103 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
104 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
105 #define INT_TX_END 0x07f80000
106 #define INT_RX 0x000003fc
107 #define INT_EXT 0x00000002
108 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
109 #define INT_EXT_LINK_PHY 0x00110000
110 #define INT_EXT_TX 0x000000ff
111 #define INT_MASK(p) (0x0468 + ((p) << 10))
112 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
113 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
114 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
115 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
116 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
117 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
118 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
119 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
120 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
121 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
122 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
123 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
124 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
125 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
126 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
127 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
131 * SDMA configuration register.
133 #define RX_BURST_SIZE_16_64BIT (4 << 1)
134 #define BLM_RX_NO_SWAP (1 << 4)
135 #define BLM_TX_NO_SWAP (1 << 5)
136 #define TX_BURST_SIZE_16_64BIT (4 << 22)
138 #if defined(__BIG_ENDIAN)
139 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
140 RX_BURST_SIZE_16_64BIT | \
141 TX_BURST_SIZE_16_64BIT
142 #elif defined(__LITTLE_ENDIAN)
143 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
144 RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT
149 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
154 * Port serial control register.
156 #define SET_MII_SPEED_TO_100 (1 << 24)
157 #define SET_GMII_SPEED_TO_1000 (1 << 23)
158 #define SET_FULL_DUPLEX_MODE (1 << 21)
159 #define MAX_RX_PACKET_9700BYTE (5 << 17)
160 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
161 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
162 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
163 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
164 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
165 #define FORCE_LINK_PASS (1 << 1)
166 #define SERIAL_PORT_ENABLE (1 << 0)
168 #define DEFAULT_RX_QUEUE_SIZE 128
169 #define DEFAULT_TX_QUEUE_SIZE 256
175 #if defined(__BIG_ENDIAN)
177 u16 byte_cnt; /* Descriptor buffer byte count */
178 u16 buf_size; /* Buffer size */
179 u32 cmd_sts; /* Descriptor command status */
180 u32 next_desc_ptr; /* Next descriptor pointer */
181 u32 buf_ptr; /* Descriptor buffer pointer */
185 u16 byte_cnt; /* buffer byte count */
186 u16 l4i_chk; /* CPU provided TCP checksum */
187 u32 cmd_sts; /* Command/status field */
188 u32 next_desc_ptr; /* Pointer to next descriptor */
189 u32 buf_ptr; /* pointer to buffer for this descriptor*/
191 #elif defined(__LITTLE_ENDIAN)
193 u32 cmd_sts; /* Descriptor command status */
194 u16 buf_size; /* Buffer size */
195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 u32 next_desc_ptr; /* Next descriptor pointer */
201 u32 cmd_sts; /* Command/status field */
202 u16 l4i_chk; /* CPU provided TCP checksum */
203 u16 byte_cnt; /* buffer byte count */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 u32 next_desc_ptr; /* Pointer to next descriptor */
208 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
211 /* RX & TX descriptor command */
212 #define BUFFER_OWNED_BY_DMA 0x80000000
214 /* RX & TX descriptor status */
215 #define ERROR_SUMMARY 0x00000001
217 /* RX descriptor status */
218 #define LAYER_4_CHECKSUM_OK 0x40000000
219 #define RX_ENABLE_INTERRUPT 0x20000000
220 #define RX_FIRST_DESC 0x08000000
221 #define RX_LAST_DESC 0x04000000
223 /* TX descriptor command */
224 #define TX_ENABLE_INTERRUPT 0x00800000
225 #define GEN_CRC 0x00400000
226 #define TX_FIRST_DESC 0x00200000
227 #define TX_LAST_DESC 0x00100000
228 #define ZERO_PADDING 0x00080000
229 #define GEN_IP_V4_CHECKSUM 0x00040000
230 #define GEN_TCP_UDP_CHECKSUM 0x00020000
231 #define UDP_FRAME 0x00010000
232 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
233 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
235 #define TX_IHL_SHIFT 11
238 /* global *******************************************************************/
239 struct mv643xx_eth_shared_private {
241 * Ethernet controller base address.
246 * Points at the right SMI instance to use.
248 struct mv643xx_eth_shared_private *smi;
251 * Protects access to SMI_REG, which is shared between ports.
253 struct mutex phy_lock;
256 * If we have access to the error interrupt pin (which is
257 * somewhat misnamed as it not only reflects internal errors
258 * but also reflects SMI completion), use that to wait for
259 * SMI access completion instead of polling the SMI busy bit.
262 wait_queue_head_t smi_busy_wait;
265 * Per-port MBUS window access register value.
270 * Hardware-specific parameters.
273 int extended_rx_coal_limit;
277 #define TX_BW_CONTROL_ABSENT 0
278 #define TX_BW_CONTROL_OLD_LAYOUT 1
279 #define TX_BW_CONTROL_NEW_LAYOUT 2
282 /* per-port *****************************************************************/
283 struct mib_counters {
284 u64 good_octets_received;
285 u32 bad_octets_received;
286 u32 internal_mac_transmit_err;
287 u32 good_frames_received;
288 u32 bad_frames_received;
289 u32 broadcast_frames_received;
290 u32 multicast_frames_received;
291 u32 frames_64_octets;
292 u32 frames_65_to_127_octets;
293 u32 frames_128_to_255_octets;
294 u32 frames_256_to_511_octets;
295 u32 frames_512_to_1023_octets;
296 u32 frames_1024_to_max_octets;
297 u64 good_octets_sent;
298 u32 good_frames_sent;
299 u32 excessive_collision;
300 u32 multicast_frames_sent;
301 u32 broadcast_frames_sent;
302 u32 unrec_mac_control_received;
304 u32 good_fc_received;
306 u32 undersize_received;
307 u32 fragments_received;
308 u32 oversize_received;
310 u32 mac_receive_error;
325 struct rx_desc *rx_desc_area;
326 dma_addr_t rx_desc_dma;
327 int rx_desc_area_size;
328 struct sk_buff **rx_skb;
340 struct tx_desc *tx_desc_area;
341 dma_addr_t tx_desc_dma;
342 int tx_desc_area_size;
344 struct sk_buff_head tx_skb;
346 unsigned long tx_packets;
347 unsigned long tx_bytes;
348 unsigned long tx_dropped;
351 struct mv643xx_eth_private {
352 struct mv643xx_eth_shared_private *shared;
355 struct net_device *dev;
359 struct mib_counters mib_counters;
360 struct work_struct tx_timeout_task;
361 struct mii_if_info mii;
363 struct napi_struct napi;
374 int default_rx_ring_size;
375 unsigned long rx_desc_sram_addr;
376 int rx_desc_sram_size;
378 struct timer_list rx_oom;
379 struct rx_queue rxq[8];
384 int default_tx_ring_size;
385 unsigned long tx_desc_sram_addr;
386 int tx_desc_sram_size;
388 struct tx_queue txq[8];
392 /* port register accessors **************************************************/
393 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
395 return readl(mp->shared->base + offset);
398 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
400 writel(data, mp->shared->base + offset);
404 /* rxq/txq helper functions *************************************************/
405 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
407 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
410 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
412 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
415 static void rxq_enable(struct rx_queue *rxq)
417 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
418 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
421 static void rxq_disable(struct rx_queue *rxq)
423 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
424 u8 mask = 1 << rxq->index;
426 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
427 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
431 static void txq_reset_hw_ptr(struct tx_queue *txq)
433 struct mv643xx_eth_private *mp = txq_to_mp(txq);
434 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
437 addr = (u32)txq->tx_desc_dma;
438 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
442 static void txq_enable(struct tx_queue *txq)
444 struct mv643xx_eth_private *mp = txq_to_mp(txq);
445 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
448 static void txq_disable(struct tx_queue *txq)
450 struct mv643xx_eth_private *mp = txq_to_mp(txq);
451 u8 mask = 1 << txq->index;
453 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
454 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
458 static void txq_maybe_wake(struct tx_queue *txq)
460 struct mv643xx_eth_private *mp = txq_to_mp(txq);
461 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
463 if (netif_tx_queue_stopped(nq)) {
464 __netif_tx_lock(nq, smp_processor_id());
465 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
466 netif_tx_wake_queue(nq);
467 __netif_tx_unlock(nq);
472 /* rx napi ******************************************************************/
473 static int rxq_process(struct rx_queue *rxq, int budget)
475 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
476 struct net_device_stats *stats = &mp->dev->stats;
480 while (rx < budget && rxq->rx_desc_count) {
481 struct rx_desc *rx_desc;
482 unsigned int cmd_sts;
486 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
488 cmd_sts = rx_desc->cmd_sts;
489 if (cmd_sts & BUFFER_OWNED_BY_DMA)
493 skb = rxq->rx_skb[rxq->rx_curr_desc];
494 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
497 if (rxq->rx_curr_desc == rxq->rx_ring_size)
498 rxq->rx_curr_desc = 0;
500 dma_unmap_single(NULL, rx_desc->buf_ptr,
501 rx_desc->buf_size, DMA_FROM_DEVICE);
502 rxq->rx_desc_count--;
505 mp->work_rx_refill |= 1 << rxq->index;
507 byte_cnt = rx_desc->byte_cnt;
512 * Note that the descriptor byte count includes 2 dummy
513 * bytes automatically inserted by the hardware at the
514 * start of the packet (which we don't count), and a 4
515 * byte CRC at the end of the packet (which we do count).
518 stats->rx_bytes += byte_cnt - 2;
521 * In case we received a packet without first / last bits
522 * on, or the error summary bit is set, the packet needs
525 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
526 (RX_FIRST_DESC | RX_LAST_DESC))
527 || (cmd_sts & ERROR_SUMMARY)) {
530 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
531 (RX_FIRST_DESC | RX_LAST_DESC)) {
533 dev_printk(KERN_ERR, &mp->dev->dev,
534 "received packet spanning "
535 "multiple descriptors\n");
538 if (cmd_sts & ERROR_SUMMARY)
544 * The -4 is for the CRC in the trailer of the
547 skb_put(skb, byte_cnt - 2 - 4);
549 if (cmd_sts & LAYER_4_CHECKSUM_OK)
550 skb->ip_summed = CHECKSUM_UNNECESSARY;
551 skb->protocol = eth_type_trans(skb, mp->dev);
552 netif_receive_skb(skb);
555 mp->dev->last_rx = jiffies;
559 mp->work_rx &= ~(1 << rxq->index);
564 static int rxq_refill(struct rx_queue *rxq, int budget)
566 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
571 * Reserve 2+14 bytes for an ethernet header (the hardware
572 * automatically prepends 2 bytes of dummy data to each
573 * received packet), 16 bytes for up to four VLAN tags, and
574 * 4 bytes for the trailing FCS -- 36 bytes total.
576 skb_size = rxq_to_mp(rxq)->dev->mtu + 36;
579 * Make sure that the skb size is a multiple of 8 bytes, as
580 * the lower three bits of the receive descriptor's buffer
581 * size field are ignored by the hardware.
583 skb_size = (skb_size + 7) & ~7;
586 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
591 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
593 mp->work_rx_oom |= 1 << rxq->index;
597 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
599 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
602 rxq->rx_desc_count++;
604 rx = rxq->rx_used_desc++;
605 if (rxq->rx_used_desc == rxq->rx_ring_size)
606 rxq->rx_used_desc = 0;
608 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
609 skb_size, DMA_FROM_DEVICE);
610 rxq->rx_desc_area[rx].buf_size = skb_size;
611 rxq->rx_skb[rx] = skb;
613 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
618 * The hardware automatically prepends 2 bytes of
619 * dummy data to each received packet, so that the
620 * IP header ends up 16-byte aligned.
625 if (refilled < budget)
626 mp->work_rx_refill &= ~(1 << rxq->index);
633 /* tx ***********************************************************************/
634 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
638 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
639 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
640 if (fragp->size <= 8 && fragp->page_offset & 7)
647 static int txq_alloc_desc_index(struct tx_queue *txq)
651 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
653 tx_desc_curr = txq->tx_curr_desc++;
654 if (txq->tx_curr_desc == txq->tx_ring_size)
655 txq->tx_curr_desc = 0;
657 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
662 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
664 int nr_frags = skb_shinfo(skb)->nr_frags;
667 for (frag = 0; frag < nr_frags; frag++) {
668 skb_frag_t *this_frag;
670 struct tx_desc *desc;
672 this_frag = &skb_shinfo(skb)->frags[frag];
673 tx_index = txq_alloc_desc_index(txq);
674 desc = &txq->tx_desc_area[tx_index];
677 * The last fragment will generate an interrupt
678 * which will free the skb on TX completion.
680 if (frag == nr_frags - 1) {
681 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
682 ZERO_PADDING | TX_LAST_DESC |
685 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
689 desc->byte_cnt = this_frag->size;
690 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
691 this_frag->page_offset,
697 static inline __be16 sum16_as_be(__sum16 sum)
699 return (__force __be16)sum;
702 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
704 struct mv643xx_eth_private *mp = txq_to_mp(txq);
705 int nr_frags = skb_shinfo(skb)->nr_frags;
707 struct tx_desc *desc;
711 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
713 tx_index = txq_alloc_desc_index(txq);
714 desc = &txq->tx_desc_area[tx_index];
717 txq_submit_frag_skb(txq, skb);
718 length = skb_headlen(skb);
720 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
724 desc->byte_cnt = length;
725 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
727 if (skb->ip_summed == CHECKSUM_PARTIAL) {
730 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
731 skb->protocol != htons(ETH_P_8021Q));
733 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
735 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
737 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
738 switch (mac_hdr_len - ETH_HLEN) {
742 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
745 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
748 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
749 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
753 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
754 "mac header length is %d?!\n", mac_hdr_len);
758 switch (ip_hdr(skb)->protocol) {
760 cmd_sts |= UDP_FRAME;
761 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
764 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
770 /* Errata BTS #50, IHL must be 5 if no HW checksum */
771 cmd_sts |= 5 << TX_IHL_SHIFT;
775 __skb_queue_tail(&txq->tx_skb, skb);
777 /* ensure all other descriptors are written before first cmd_sts */
779 desc->cmd_sts = cmd_sts;
781 /* clear TX_END status */
782 mp->work_tx_end &= ~(1 << txq->index);
784 /* ensure all descriptors are written before poking hardware */
788 txq->tx_desc_count += nr_frags + 1;
791 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
793 struct mv643xx_eth_private *mp = netdev_priv(dev);
795 struct tx_queue *txq;
796 struct netdev_queue *nq;
799 queue = skb_get_queue_mapping(skb);
800 txq = mp->txq + queue;
801 nq = netdev_get_tx_queue(dev, queue);
803 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
805 dev_printk(KERN_DEBUG, &dev->dev,
806 "failed to linearize skb with tiny "
807 "unaligned fragment\n");
808 return NETDEV_TX_BUSY;
811 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
813 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
818 txq_submit_skb(txq, skb);
819 txq->tx_bytes += skb->len;
821 dev->trans_start = jiffies;
823 entries_left = txq->tx_ring_size - txq->tx_desc_count;
824 if (entries_left < MAX_SKB_FRAGS + 1)
825 netif_tx_stop_queue(nq);
831 /* tx napi ******************************************************************/
832 static void txq_kick(struct tx_queue *txq)
834 struct mv643xx_eth_private *mp = txq_to_mp(txq);
835 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
839 __netif_tx_lock(nq, smp_processor_id());
841 if (rdl(mp, TXQ_COMMAND(mp->port_num)) & (1 << txq->index))
844 hw_desc_ptr = rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index));
845 expected_ptr = (u32)txq->tx_desc_dma +
846 txq->tx_curr_desc * sizeof(struct tx_desc);
848 if (hw_desc_ptr != expected_ptr)
852 __netif_tx_unlock(nq);
854 mp->work_tx_end &= ~(1 << txq->index);
857 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
859 struct mv643xx_eth_private *mp = txq_to_mp(txq);
860 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
863 __netif_tx_lock(nq, smp_processor_id());
866 while (reclaimed < budget && txq->tx_desc_count > 0) {
868 struct tx_desc *desc;
872 tx_index = txq->tx_used_desc;
873 desc = &txq->tx_desc_area[tx_index];
874 cmd_sts = desc->cmd_sts;
876 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
879 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
882 txq->tx_used_desc = tx_index + 1;
883 if (txq->tx_used_desc == txq->tx_ring_size)
884 txq->tx_used_desc = 0;
887 txq->tx_desc_count--;
890 if (cmd_sts & TX_LAST_DESC)
891 skb = __skb_dequeue(&txq->tx_skb);
893 if (cmd_sts & ERROR_SUMMARY) {
894 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
895 mp->dev->stats.tx_errors++;
898 if (cmd_sts & TX_FIRST_DESC) {
899 dma_unmap_single(NULL, desc->buf_ptr,
900 desc->byte_cnt, DMA_TO_DEVICE);
902 dma_unmap_page(NULL, desc->buf_ptr,
903 desc->byte_cnt, DMA_TO_DEVICE);
910 __netif_tx_unlock(nq);
912 if (reclaimed < budget)
913 mp->work_tx &= ~(1 << txq->index);
919 /* tx rate control **********************************************************/
921 * Set total maximum TX rate (shared by all TX queues for this port)
922 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
924 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
930 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
931 if (token_rate > 1023)
934 mtu = (mp->dev->mtu + 255) >> 8;
938 bucket_size = (burst + 255) >> 8;
939 if (bucket_size > 65535)
942 switch (mp->shared->tx_bw_control) {
943 case TX_BW_CONTROL_OLD_LAYOUT:
944 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
945 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
946 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
948 case TX_BW_CONTROL_NEW_LAYOUT:
949 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
950 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
951 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
956 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
958 struct mv643xx_eth_private *mp = txq_to_mp(txq);
962 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
963 if (token_rate > 1023)
966 bucket_size = (burst + 255) >> 8;
967 if (bucket_size > 65535)
970 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
971 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
972 (bucket_size << 10) | token_rate);
975 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
977 struct mv643xx_eth_private *mp = txq_to_mp(txq);
982 * Turn on fixed priority mode.
985 switch (mp->shared->tx_bw_control) {
986 case TX_BW_CONTROL_OLD_LAYOUT:
987 off = TXQ_FIX_PRIO_CONF(mp->port_num);
989 case TX_BW_CONTROL_NEW_LAYOUT:
990 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
996 val |= 1 << txq->index;
1001 static void txq_set_wrr(struct tx_queue *txq, int weight)
1003 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1008 * Turn off fixed priority mode.
1011 switch (mp->shared->tx_bw_control) {
1012 case TX_BW_CONTROL_OLD_LAYOUT:
1013 off = TXQ_FIX_PRIO_CONF(mp->port_num);
1015 case TX_BW_CONTROL_NEW_LAYOUT:
1016 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
1022 val &= ~(1 << txq->index);
1026 * Configure WRR weight for this queue.
1028 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
1031 val = (val & ~0xff) | (weight & 0xff);
1037 /* mii management interface *************************************************/
1038 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1040 struct mv643xx_eth_shared_private *msp = dev_id;
1042 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1043 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1044 wake_up(&msp->smi_busy_wait);
1051 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1053 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1056 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1058 if (msp->err_interrupt == NO_IRQ) {
1061 for (i = 0; !smi_is_done(msp); i++) {
1070 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1071 msecs_to_jiffies(100)))
1077 static int smi_reg_read(struct mv643xx_eth_private *mp,
1078 unsigned int addr, unsigned int reg)
1080 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
1081 void __iomem *smi_reg = msp->base + SMI_REG;
1084 mutex_lock(&msp->phy_lock);
1086 if (smi_wait_ready(msp)) {
1087 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1092 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1094 if (smi_wait_ready(msp)) {
1095 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1100 ret = readl(smi_reg);
1101 if (!(ret & SMI_READ_VALID)) {
1102 printk("%s: SMI bus read not valid\n", mp->dev->name);
1110 mutex_unlock(&msp->phy_lock);
1115 static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1116 unsigned int reg, unsigned int value)
1118 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
1119 void __iomem *smi_reg = msp->base + SMI_REG;
1121 mutex_lock(&msp->phy_lock);
1123 if (smi_wait_ready(msp)) {
1124 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1125 mutex_unlock(&msp->phy_lock);
1129 writel(SMI_OPCODE_WRITE | (reg << 21) |
1130 (addr << 16) | (value & 0xffff), smi_reg);
1132 mutex_unlock(&msp->phy_lock);
1138 /* statistics ***************************************************************/
1139 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1141 struct mv643xx_eth_private *mp = netdev_priv(dev);
1142 struct net_device_stats *stats = &dev->stats;
1143 unsigned long tx_packets = 0;
1144 unsigned long tx_bytes = 0;
1145 unsigned long tx_dropped = 0;
1148 for (i = 0; i < mp->txq_count; i++) {
1149 struct tx_queue *txq = mp->txq + i;
1151 tx_packets += txq->tx_packets;
1152 tx_bytes += txq->tx_bytes;
1153 tx_dropped += txq->tx_dropped;
1156 stats->tx_packets = tx_packets;
1157 stats->tx_bytes = tx_bytes;
1158 stats->tx_dropped = tx_dropped;
1163 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1165 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1168 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1172 for (i = 0; i < 0x80; i += 4)
1176 static void mib_counters_update(struct mv643xx_eth_private *mp)
1178 struct mib_counters *p = &mp->mib_counters;
1180 p->good_octets_received += mib_read(mp, 0x00);
1181 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1182 p->bad_octets_received += mib_read(mp, 0x08);
1183 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1184 p->good_frames_received += mib_read(mp, 0x10);
1185 p->bad_frames_received += mib_read(mp, 0x14);
1186 p->broadcast_frames_received += mib_read(mp, 0x18);
1187 p->multicast_frames_received += mib_read(mp, 0x1c);
1188 p->frames_64_octets += mib_read(mp, 0x20);
1189 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1190 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1191 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1192 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1193 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1194 p->good_octets_sent += mib_read(mp, 0x38);
1195 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1196 p->good_frames_sent += mib_read(mp, 0x40);
1197 p->excessive_collision += mib_read(mp, 0x44);
1198 p->multicast_frames_sent += mib_read(mp, 0x48);
1199 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1200 p->unrec_mac_control_received += mib_read(mp, 0x50);
1201 p->fc_sent += mib_read(mp, 0x54);
1202 p->good_fc_received += mib_read(mp, 0x58);
1203 p->bad_fc_received += mib_read(mp, 0x5c);
1204 p->undersize_received += mib_read(mp, 0x60);
1205 p->fragments_received += mib_read(mp, 0x64);
1206 p->oversize_received += mib_read(mp, 0x68);
1207 p->jabber_received += mib_read(mp, 0x6c);
1208 p->mac_receive_error += mib_read(mp, 0x70);
1209 p->bad_crc_event += mib_read(mp, 0x74);
1210 p->collision += mib_read(mp, 0x78);
1211 p->late_collision += mib_read(mp, 0x7c);
1215 /* ethtool ******************************************************************/
1216 struct mv643xx_eth_stats {
1217 char stat_string[ETH_GSTRING_LEN];
1224 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1225 offsetof(struct net_device, stats.m), -1 }
1227 #define MIBSTAT(m) \
1228 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1229 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1231 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1240 MIBSTAT(good_octets_received),
1241 MIBSTAT(bad_octets_received),
1242 MIBSTAT(internal_mac_transmit_err),
1243 MIBSTAT(good_frames_received),
1244 MIBSTAT(bad_frames_received),
1245 MIBSTAT(broadcast_frames_received),
1246 MIBSTAT(multicast_frames_received),
1247 MIBSTAT(frames_64_octets),
1248 MIBSTAT(frames_65_to_127_octets),
1249 MIBSTAT(frames_128_to_255_octets),
1250 MIBSTAT(frames_256_to_511_octets),
1251 MIBSTAT(frames_512_to_1023_octets),
1252 MIBSTAT(frames_1024_to_max_octets),
1253 MIBSTAT(good_octets_sent),
1254 MIBSTAT(good_frames_sent),
1255 MIBSTAT(excessive_collision),
1256 MIBSTAT(multicast_frames_sent),
1257 MIBSTAT(broadcast_frames_sent),
1258 MIBSTAT(unrec_mac_control_received),
1260 MIBSTAT(good_fc_received),
1261 MIBSTAT(bad_fc_received),
1262 MIBSTAT(undersize_received),
1263 MIBSTAT(fragments_received),
1264 MIBSTAT(oversize_received),
1265 MIBSTAT(jabber_received),
1266 MIBSTAT(mac_receive_error),
1267 MIBSTAT(bad_crc_event),
1269 MIBSTAT(late_collision),
1272 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1274 struct mv643xx_eth_private *mp = netdev_priv(dev);
1277 err = mii_ethtool_gset(&mp->mii, cmd);
1280 * The MAC does not support 1000baseT_Half.
1282 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1283 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1288 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1290 struct mv643xx_eth_private *mp = netdev_priv(dev);
1293 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1295 cmd->supported = SUPPORTED_MII;
1296 cmd->advertising = ADVERTISED_MII;
1297 switch (port_status & PORT_SPEED_MASK) {
1299 cmd->speed = SPEED_10;
1301 case PORT_SPEED_100:
1302 cmd->speed = SPEED_100;
1304 case PORT_SPEED_1000:
1305 cmd->speed = SPEED_1000;
1311 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1312 cmd->port = PORT_MII;
1313 cmd->phy_address = 0;
1314 cmd->transceiver = XCVR_INTERNAL;
1315 cmd->autoneg = AUTONEG_DISABLE;
1322 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1324 struct mv643xx_eth_private *mp = netdev_priv(dev);
1327 * The MAC does not support 1000baseT_Half.
1329 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1331 return mii_ethtool_sset(&mp->mii, cmd);
1334 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1339 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1340 struct ethtool_drvinfo *drvinfo)
1342 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1343 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1344 strncpy(drvinfo->fw_version, "N/A", 32);
1345 strncpy(drvinfo->bus_info, "platform", 32);
1346 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1349 static int mv643xx_eth_nway_reset(struct net_device *dev)
1351 struct mv643xx_eth_private *mp = netdev_priv(dev);
1353 return mii_nway_restart(&mp->mii);
1356 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1361 static u32 mv643xx_eth_get_link(struct net_device *dev)
1363 struct mv643xx_eth_private *mp = netdev_priv(dev);
1365 return mii_link_ok(&mp->mii);
1368 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1373 static void mv643xx_eth_get_strings(struct net_device *dev,
1374 uint32_t stringset, uint8_t *data)
1378 if (stringset == ETH_SS_STATS) {
1379 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1380 memcpy(data + i * ETH_GSTRING_LEN,
1381 mv643xx_eth_stats[i].stat_string,
1387 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1388 struct ethtool_stats *stats,
1391 struct mv643xx_eth_private *mp = netdev_priv(dev);
1394 mv643xx_eth_get_stats(dev);
1395 mib_counters_update(mp);
1397 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1398 const struct mv643xx_eth_stats *stat;
1401 stat = mv643xx_eth_stats + i;
1403 if (stat->netdev_off >= 0)
1404 p = ((void *)mp->dev) + stat->netdev_off;
1406 p = ((void *)mp) + stat->mp_off;
1408 data[i] = (stat->sizeof_stat == 8) ?
1409 *(uint64_t *)p : *(uint32_t *)p;
1413 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1415 if (sset == ETH_SS_STATS)
1416 return ARRAY_SIZE(mv643xx_eth_stats);
1421 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1422 .get_settings = mv643xx_eth_get_settings,
1423 .set_settings = mv643xx_eth_set_settings,
1424 .get_drvinfo = mv643xx_eth_get_drvinfo,
1425 .nway_reset = mv643xx_eth_nway_reset,
1426 .get_link = mv643xx_eth_get_link,
1427 .set_sg = ethtool_op_set_sg,
1428 .get_strings = mv643xx_eth_get_strings,
1429 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1430 .get_sset_count = mv643xx_eth_get_sset_count,
1433 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1434 .get_settings = mv643xx_eth_get_settings_phyless,
1435 .set_settings = mv643xx_eth_set_settings_phyless,
1436 .get_drvinfo = mv643xx_eth_get_drvinfo,
1437 .nway_reset = mv643xx_eth_nway_reset_phyless,
1438 .get_link = mv643xx_eth_get_link_phyless,
1439 .set_sg = ethtool_op_set_sg,
1440 .get_strings = mv643xx_eth_get_strings,
1441 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1442 .get_sset_count = mv643xx_eth_get_sset_count,
1446 /* address handling *********************************************************/
1447 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1452 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1453 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1455 addr[0] = (mac_h >> 24) & 0xff;
1456 addr[1] = (mac_h >> 16) & 0xff;
1457 addr[2] = (mac_h >> 8) & 0xff;
1458 addr[3] = mac_h & 0xff;
1459 addr[4] = (mac_l >> 8) & 0xff;
1460 addr[5] = mac_l & 0xff;
1463 static void init_mac_tables(struct mv643xx_eth_private *mp)
1467 for (i = 0; i < 0x100; i += 4) {
1468 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1469 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1472 for (i = 0; i < 0x10; i += 4)
1473 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1476 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1477 int table, unsigned char entry)
1479 unsigned int table_reg;
1481 /* Set "accepts frame bit" at specified table entry */
1482 table_reg = rdl(mp, table + (entry & 0xfc));
1483 table_reg |= 0x01 << (8 * (entry & 3));
1484 wrl(mp, table + (entry & 0xfc), table_reg);
1487 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1493 mac_l = (addr[4] << 8) | addr[5];
1494 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1496 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1497 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1499 table = UNICAST_TABLE(mp->port_num);
1500 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1503 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1505 struct mv643xx_eth_private *mp = netdev_priv(dev);
1507 /* +2 is for the offset of the HW addr type */
1508 memcpy(dev->dev_addr, addr + 2, 6);
1510 init_mac_tables(mp);
1511 uc_addr_set(mp, dev->dev_addr);
1516 static int addr_crc(unsigned char *addr)
1521 for (i = 0; i < 6; i++) {
1524 crc = (crc ^ addr[i]) << 8;
1525 for (j = 7; j >= 0; j--) {
1526 if (crc & (0x100 << j))
1534 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1536 struct mv643xx_eth_private *mp = netdev_priv(dev);
1538 struct dev_addr_list *addr;
1541 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1542 if (dev->flags & IFF_PROMISC)
1543 port_config |= UNICAST_PROMISCUOUS_MODE;
1545 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1546 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1548 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1549 int port_num = mp->port_num;
1550 u32 accept = 0x01010101;
1552 for (i = 0; i < 0x100; i += 4) {
1553 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1554 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1559 for (i = 0; i < 0x100; i += 4) {
1560 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1561 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1564 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1565 u8 *a = addr->da_addr;
1568 if (addr->da_addrlen != 6)
1571 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1572 table = SPECIAL_MCAST_TABLE(mp->port_num);
1573 set_filter_table_entry(mp, table, a[5]);
1575 int crc = addr_crc(a);
1577 table = OTHER_MCAST_TABLE(mp->port_num);
1578 set_filter_table_entry(mp, table, crc);
1584 /* rx/tx queue initialisation ***********************************************/
1585 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1587 struct rx_queue *rxq = mp->rxq + index;
1588 struct rx_desc *rx_desc;
1594 rxq->rx_ring_size = mp->default_rx_ring_size;
1596 rxq->rx_desc_count = 0;
1597 rxq->rx_curr_desc = 0;
1598 rxq->rx_used_desc = 0;
1600 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1602 if (index == 0 && size <= mp->rx_desc_sram_size) {
1603 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1604 mp->rx_desc_sram_size);
1605 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1607 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1612 if (rxq->rx_desc_area == NULL) {
1613 dev_printk(KERN_ERR, &mp->dev->dev,
1614 "can't allocate rx ring (%d bytes)\n", size);
1617 memset(rxq->rx_desc_area, 0, size);
1619 rxq->rx_desc_area_size = size;
1620 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1622 if (rxq->rx_skb == NULL) {
1623 dev_printk(KERN_ERR, &mp->dev->dev,
1624 "can't allocate rx skb ring\n");
1628 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1629 for (i = 0; i < rxq->rx_ring_size; i++) {
1633 if (nexti == rxq->rx_ring_size)
1636 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1637 nexti * sizeof(struct rx_desc);
1644 if (index == 0 && size <= mp->rx_desc_sram_size)
1645 iounmap(rxq->rx_desc_area);
1647 dma_free_coherent(NULL, size,
1655 static void rxq_deinit(struct rx_queue *rxq)
1657 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1662 for (i = 0; i < rxq->rx_ring_size; i++) {
1663 if (rxq->rx_skb[i]) {
1664 dev_kfree_skb(rxq->rx_skb[i]);
1665 rxq->rx_desc_count--;
1669 if (rxq->rx_desc_count) {
1670 dev_printk(KERN_ERR, &mp->dev->dev,
1671 "error freeing rx ring -- %d skbs stuck\n",
1672 rxq->rx_desc_count);
1675 if (rxq->index == 0 &&
1676 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1677 iounmap(rxq->rx_desc_area);
1679 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1680 rxq->rx_desc_area, rxq->rx_desc_dma);
1685 static int txq_init(struct mv643xx_eth_private *mp, int index)
1687 struct tx_queue *txq = mp->txq + index;
1688 struct tx_desc *tx_desc;
1694 txq->tx_ring_size = mp->default_tx_ring_size;
1696 txq->tx_desc_count = 0;
1697 txq->tx_curr_desc = 0;
1698 txq->tx_used_desc = 0;
1700 size = txq->tx_ring_size * sizeof(struct tx_desc);
1702 if (index == 0 && size <= mp->tx_desc_sram_size) {
1703 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1704 mp->tx_desc_sram_size);
1705 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1707 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1712 if (txq->tx_desc_area == NULL) {
1713 dev_printk(KERN_ERR, &mp->dev->dev,
1714 "can't allocate tx ring (%d bytes)\n", size);
1717 memset(txq->tx_desc_area, 0, size);
1719 txq->tx_desc_area_size = size;
1721 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1722 for (i = 0; i < txq->tx_ring_size; i++) {
1723 struct tx_desc *txd = tx_desc + i;
1727 if (nexti == txq->tx_ring_size)
1731 txd->next_desc_ptr = txq->tx_desc_dma +
1732 nexti * sizeof(struct tx_desc);
1735 skb_queue_head_init(&txq->tx_skb);
1740 static void txq_deinit(struct tx_queue *txq)
1742 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1745 txq_reclaim(txq, txq->tx_ring_size, 1);
1747 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1749 if (txq->index == 0 &&
1750 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1751 iounmap(txq->tx_desc_area);
1753 dma_free_coherent(NULL, txq->tx_desc_area_size,
1754 txq->tx_desc_area, txq->tx_desc_dma);
1758 /* netdev ops and related ***************************************************/
1759 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1764 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1765 (INT_TX_END | INT_RX | INT_EXT);
1770 if (int_cause & INT_EXT)
1771 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num));
1773 int_cause &= INT_TX_END | INT_RX;
1775 wrl(mp, INT_CAUSE(mp->port_num), ~int_cause);
1776 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1777 ~(rdl(mp, TXQ_COMMAND(mp->port_num)) & 0xff);
1778 mp->work_rx |= (int_cause & INT_RX) >> 2;
1781 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1782 if (int_cause_ext) {
1783 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1784 if (int_cause_ext & INT_EXT_LINK_PHY)
1786 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1792 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1794 struct net_device *dev = (struct net_device *)dev_id;
1795 struct mv643xx_eth_private *mp = netdev_priv(dev);
1797 if (unlikely(!mv643xx_eth_collect_events(mp)))
1800 wrl(mp, INT_MASK(mp->port_num), 0);
1801 napi_schedule(&mp->napi);
1806 static void handle_link_event(struct mv643xx_eth_private *mp)
1808 struct net_device *dev = mp->dev;
1814 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1815 if (!(port_status & LINK_UP)) {
1816 if (netif_carrier_ok(dev)) {
1819 printk(KERN_INFO "%s: link down\n", dev->name);
1821 netif_carrier_off(dev);
1823 for (i = 0; i < mp->txq_count; i++) {
1824 struct tx_queue *txq = mp->txq + i;
1826 txq_reclaim(txq, txq->tx_ring_size, 1);
1827 txq_reset_hw_ptr(txq);
1833 switch (port_status & PORT_SPEED_MASK) {
1837 case PORT_SPEED_100:
1840 case PORT_SPEED_1000:
1847 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1848 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1850 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1851 "flow control %sabled\n", dev->name,
1852 speed, duplex ? "full" : "half",
1855 if (!netif_carrier_ok(dev))
1856 netif_carrier_on(dev);
1859 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1861 struct mv643xx_eth_private *mp;
1864 mp = container_of(napi, struct mv643xx_eth_private, napi);
1866 mp->work_rx_refill |= mp->work_rx_oom;
1867 mp->work_rx_oom = 0;
1870 while (work_done < budget) {
1875 if (mp->work_link) {
1877 handle_link_event(mp);
1881 queue_mask = mp->work_tx | mp->work_tx_end |
1882 mp->work_rx | mp->work_rx_refill;
1884 if (mv643xx_eth_collect_events(mp))
1889 queue = fls(queue_mask) - 1;
1890 queue_mask = 1 << queue;
1892 work_tbd = budget - work_done;
1896 if (mp->work_tx_end & queue_mask) {
1897 txq_kick(mp->txq + queue);
1898 } else if (mp->work_tx & queue_mask) {
1899 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1900 txq_maybe_wake(mp->txq + queue);
1901 } else if (mp->work_rx & queue_mask) {
1902 work_done += rxq_process(mp->rxq + queue, work_tbd);
1903 } else if (mp->work_rx_refill & queue_mask) {
1904 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1910 if (work_done < budget) {
1911 if (mp->work_rx_oom)
1912 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1913 napi_complete(napi);
1914 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
1920 static inline void oom_timer_wrapper(unsigned long data)
1922 struct mv643xx_eth_private *mp = (void *)data;
1924 napi_schedule(&mp->napi);
1927 static void phy_reset(struct mv643xx_eth_private *mp)
1931 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1936 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1940 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1941 } while (data >= 0 && data & BMCR_RESET);
1944 static void port_start(struct mv643xx_eth_private *mp)
1950 * Perform PHY reset, if there is a PHY.
1952 if (mp->phy_addr != -1) {
1953 struct ethtool_cmd cmd;
1955 mv643xx_eth_get_settings(mp->dev, &cmd);
1957 mv643xx_eth_set_settings(mp->dev, &cmd);
1961 * Configure basic link parameters.
1963 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1965 pscr |= SERIAL_PORT_ENABLE;
1966 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1968 pscr |= DO_NOT_FORCE_LINK_FAIL;
1969 if (mp->phy_addr == -1)
1970 pscr |= FORCE_LINK_PASS;
1971 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1973 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1976 * Configure TX path and queues.
1978 tx_set_rate(mp, 1000000000, 16777216);
1979 for (i = 0; i < mp->txq_count; i++) {
1980 struct tx_queue *txq = mp->txq + i;
1982 txq_reset_hw_ptr(txq);
1983 txq_set_rate(txq, 1000000000, 16777216);
1984 txq_set_fixed_prio_mode(txq);
1988 * Add configured unicast address to address filter table.
1990 uc_addr_set(mp, mp->dev->dev_addr);
1993 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1994 * frames to RX queue #0, and include the pseudo-header when
1995 * calculating receive checksums.
1997 wrl(mp, PORT_CONFIG(mp->port_num), 0x02000000);
2000 * Treat BPDUs as normal multicasts, and disable partition mode.
2002 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
2005 * Enable the receive queues.
2007 for (i = 0; i < mp->rxq_count; i++) {
2008 struct rx_queue *rxq = mp->rxq + i;
2009 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
2012 addr = (u32)rxq->rx_desc_dma;
2013 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2020 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2022 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2025 val = rdl(mp, SDMA_CONFIG(mp->port_num));
2026 if (mp->shared->extended_rx_coal_limit) {
2030 val |= (coal & 0x8000) << 10;
2031 val |= (coal & 0x7fff) << 7;
2036 val |= (coal & 0x3fff) << 8;
2038 wrl(mp, SDMA_CONFIG(mp->port_num), val);
2041 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2043 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2047 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2050 static int mv643xx_eth_open(struct net_device *dev)
2052 struct mv643xx_eth_private *mp = netdev_priv(dev);
2056 wrl(mp, INT_CAUSE(mp->port_num), 0);
2057 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2058 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2060 err = request_irq(dev->irq, mv643xx_eth_irq,
2061 IRQF_SHARED, dev->name, dev);
2063 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2067 init_mac_tables(mp);
2069 napi_enable(&mp->napi);
2071 for (i = 0; i < mp->rxq_count; i++) {
2072 err = rxq_init(mp, i);
2075 rxq_deinit(mp->rxq + i);
2079 rxq_refill(mp->rxq + i, INT_MAX);
2082 if (mp->work_rx_oom) {
2083 mp->rx_oom.expires = jiffies + (HZ / 10);
2084 add_timer(&mp->rx_oom);
2087 for (i = 0; i < mp->txq_count; i++) {
2088 err = txq_init(mp, i);
2091 txq_deinit(mp->txq + i);
2096 netif_carrier_off(dev);
2103 wrl(mp, INT_MASK_EXT(mp->port_num), INT_EXT_LINK_PHY | INT_EXT_TX);
2104 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2110 for (i = 0; i < mp->rxq_count; i++)
2111 rxq_deinit(mp->rxq + i);
2113 free_irq(dev->irq, dev);
2118 static void port_reset(struct mv643xx_eth_private *mp)
2123 for (i = 0; i < mp->rxq_count; i++)
2124 rxq_disable(mp->rxq + i);
2125 for (i = 0; i < mp->txq_count; i++)
2126 txq_disable(mp->txq + i);
2129 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2131 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2136 /* Reset the Enable bit in the Configuration Register */
2137 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2138 data &= ~(SERIAL_PORT_ENABLE |
2139 DO_NOT_FORCE_LINK_FAIL |
2141 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2144 static int mv643xx_eth_stop(struct net_device *dev)
2146 struct mv643xx_eth_private *mp = netdev_priv(dev);
2149 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2150 rdl(mp, INT_MASK(mp->port_num));
2152 napi_disable(&mp->napi);
2154 del_timer_sync(&mp->rx_oom);
2156 netif_carrier_off(dev);
2158 free_irq(dev->irq, dev);
2161 mv643xx_eth_get_stats(dev);
2162 mib_counters_update(mp);
2164 for (i = 0; i < mp->rxq_count; i++)
2165 rxq_deinit(mp->rxq + i);
2166 for (i = 0; i < mp->txq_count; i++)
2167 txq_deinit(mp->txq + i);
2172 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2174 struct mv643xx_eth_private *mp = netdev_priv(dev);
2176 if (mp->phy_addr != -1)
2177 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2182 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2184 struct mv643xx_eth_private *mp = netdev_priv(dev);
2186 if (new_mtu < 64 || new_mtu > 9500)
2190 tx_set_rate(mp, 1000000000, 16777216);
2192 if (!netif_running(dev))
2196 * Stop and then re-open the interface. This will allocate RX
2197 * skbs of the new MTU.
2198 * There is a possible danger that the open will not succeed,
2199 * due to memory being full.
2201 mv643xx_eth_stop(dev);
2202 if (mv643xx_eth_open(dev)) {
2203 dev_printk(KERN_ERR, &dev->dev,
2204 "fatal error on re-opening device after "
2211 static void tx_timeout_task(struct work_struct *ugly)
2213 struct mv643xx_eth_private *mp;
2215 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2216 if (netif_running(mp->dev)) {
2217 netif_tx_stop_all_queues(mp->dev);
2220 netif_tx_wake_all_queues(mp->dev);
2224 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2226 struct mv643xx_eth_private *mp = netdev_priv(dev);
2228 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2230 schedule_work(&mp->tx_timeout_task);
2233 #ifdef CONFIG_NET_POLL_CONTROLLER
2234 static void mv643xx_eth_netpoll(struct net_device *dev)
2236 struct mv643xx_eth_private *mp = netdev_priv(dev);
2238 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2239 rdl(mp, INT_MASK(mp->port_num));
2241 mv643xx_eth_irq(dev->irq, dev);
2243 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2247 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2249 struct mv643xx_eth_private *mp = netdev_priv(dev);
2250 return smi_reg_read(mp, addr, reg);
2253 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2255 struct mv643xx_eth_private *mp = netdev_priv(dev);
2256 smi_reg_write(mp, addr, reg, val);
2260 /* platform glue ************************************************************/
2262 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2263 struct mbus_dram_target_info *dram)
2265 void __iomem *base = msp->base;
2270 for (i = 0; i < 6; i++) {
2271 writel(0, base + WINDOW_BASE(i));
2272 writel(0, base + WINDOW_SIZE(i));
2274 writel(0, base + WINDOW_REMAP_HIGH(i));
2280 for (i = 0; i < dram->num_cs; i++) {
2281 struct mbus_dram_window *cs = dram->cs + i;
2283 writel((cs->base & 0xffff0000) |
2284 (cs->mbus_attr << 8) |
2285 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2286 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2288 win_enable &= ~(1 << i);
2289 win_protect |= 3 << (2 * i);
2292 writel(win_enable, base + WINDOW_BAR_ENABLE);
2293 msp->win_protect = win_protect;
2296 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2299 * Check whether we have a 14-bit coal limit field in bits
2300 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2301 * SDMA config register.
2303 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2304 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2305 msp->extended_rx_coal_limit = 1;
2307 msp->extended_rx_coal_limit = 0;
2310 * Check whether the MAC supports TX rate control, and if
2311 * yes, whether its associated registers are in the old or
2314 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2315 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1) {
2316 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2318 writel(7, msp->base + TX_BW_RATE(0));
2319 if (readl(msp->base + TX_BW_RATE(0)) & 7)
2320 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2322 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2326 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2328 static int mv643xx_eth_version_printed = 0;
2329 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2330 struct mv643xx_eth_shared_private *msp;
2331 struct resource *res;
2334 if (!mv643xx_eth_version_printed++)
2335 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2336 "driver version %s\n", mv643xx_eth_driver_version);
2339 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2344 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2347 memset(msp, 0, sizeof(*msp));
2349 msp->base = ioremap(res->start, res->end - res->start + 1);
2350 if (msp->base == NULL)
2354 if (pd != NULL && pd->shared_smi != NULL)
2355 msp->smi = platform_get_drvdata(pd->shared_smi);
2357 mutex_init(&msp->phy_lock);
2359 msp->err_interrupt = NO_IRQ;
2360 init_waitqueue_head(&msp->smi_busy_wait);
2363 * Check whether the error interrupt is hooked up.
2365 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2369 err = request_irq(res->start, mv643xx_eth_err_irq,
2370 IRQF_SHARED, "mv643xx_eth", msp);
2372 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2373 msp->err_interrupt = res->start;
2378 * (Re-)program MBUS remapping windows if we are asked to.
2380 if (pd != NULL && pd->dram != NULL)
2381 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2384 * Detect hardware parameters.
2386 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2387 infer_hw_params(msp);
2389 platform_set_drvdata(pdev, msp);
2399 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2401 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2403 if (msp->err_interrupt != NO_IRQ)
2404 free_irq(msp->err_interrupt, msp);
2411 static struct platform_driver mv643xx_eth_shared_driver = {
2412 .probe = mv643xx_eth_shared_probe,
2413 .remove = mv643xx_eth_shared_remove,
2415 .name = MV643XX_ETH_SHARED_NAME,
2416 .owner = THIS_MODULE,
2420 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2422 int addr_shift = 5 * mp->port_num;
2425 data = rdl(mp, PHY_ADDR);
2426 data &= ~(0x1f << addr_shift);
2427 data |= (phy_addr & 0x1f) << addr_shift;
2428 wrl(mp, PHY_ADDR, data);
2431 static int phy_addr_get(struct mv643xx_eth_private *mp)
2435 data = rdl(mp, PHY_ADDR);
2437 return (data >> (5 * mp->port_num)) & 0x1f;
2440 static void set_params(struct mv643xx_eth_private *mp,
2441 struct mv643xx_eth_platform_data *pd)
2443 struct net_device *dev = mp->dev;
2445 if (is_valid_ether_addr(pd->mac_addr))
2446 memcpy(dev->dev_addr, pd->mac_addr, 6);
2448 uc_addr_get(mp, dev->dev_addr);
2450 if (pd->phy_addr == MV643XX_ETH_PHY_NONE) {
2453 if (pd->phy_addr != MV643XX_ETH_PHY_ADDR_DEFAULT) {
2454 mp->phy_addr = pd->phy_addr & 0x3f;
2455 phy_addr_set(mp, mp->phy_addr);
2457 mp->phy_addr = phy_addr_get(mp);
2461 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2462 if (pd->rx_queue_size)
2463 mp->default_rx_ring_size = pd->rx_queue_size;
2464 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2465 mp->rx_desc_sram_size = pd->rx_sram_size;
2467 mp->rxq_count = pd->rx_queue_count ? : 1;
2469 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2470 if (pd->tx_queue_size)
2471 mp->default_tx_ring_size = pd->tx_queue_size;
2472 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2473 mp->tx_desc_sram_size = pd->tx_sram_size;
2475 mp->txq_count = pd->tx_queue_count ? : 1;
2478 static int phy_detect(struct mv643xx_eth_private *mp)
2483 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2487 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2490 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2494 if (((data ^ data2) & BMCR_ANENABLE) == 0)
2497 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
2502 static int phy_init(struct mv643xx_eth_private *mp,
2503 struct mv643xx_eth_platform_data *pd)
2505 struct ethtool_cmd cmd;
2508 err = phy_detect(mp);
2510 dev_printk(KERN_INFO, &mp->dev->dev,
2511 "no PHY detected at addr %d\n", mp->phy_addr);
2516 mp->mii.phy_id = mp->phy_addr;
2517 mp->mii.phy_id_mask = 0x3f;
2518 mp->mii.reg_num_mask = 0x1f;
2519 mp->mii.dev = mp->dev;
2520 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2521 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2523 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2525 memset(&cmd, 0, sizeof(cmd));
2527 cmd.port = PORT_MII;
2528 cmd.transceiver = XCVR_INTERNAL;
2529 cmd.phy_address = mp->phy_addr;
2530 if (pd->speed == 0) {
2531 cmd.autoneg = AUTONEG_ENABLE;
2532 cmd.speed = SPEED_100;
2533 cmd.advertising = ADVERTISED_10baseT_Half |
2534 ADVERTISED_10baseT_Full |
2535 ADVERTISED_100baseT_Half |
2536 ADVERTISED_100baseT_Full;
2537 if (mp->mii.supports_gmii)
2538 cmd.advertising |= ADVERTISED_1000baseT_Full;
2540 cmd.autoneg = AUTONEG_DISABLE;
2541 cmd.speed = pd->speed;
2542 cmd.duplex = pd->duplex;
2545 mv643xx_eth_set_settings(mp->dev, &cmd);
2550 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2554 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2555 if (pscr & SERIAL_PORT_ENABLE) {
2556 pscr &= ~SERIAL_PORT_ENABLE;
2557 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2560 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2561 if (mp->phy_addr == -1) {
2562 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2563 if (speed == SPEED_1000)
2564 pscr |= SET_GMII_SPEED_TO_1000;
2565 else if (speed == SPEED_100)
2566 pscr |= SET_MII_SPEED_TO_100;
2568 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2570 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2571 if (duplex == DUPLEX_FULL)
2572 pscr |= SET_FULL_DUPLEX_MODE;
2575 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2578 static int mv643xx_eth_probe(struct platform_device *pdev)
2580 struct mv643xx_eth_platform_data *pd;
2581 struct mv643xx_eth_private *mp;
2582 struct net_device *dev;
2583 struct resource *res;
2584 DECLARE_MAC_BUF(mac);
2587 pd = pdev->dev.platform_data;
2589 dev_printk(KERN_ERR, &pdev->dev,
2590 "no mv643xx_eth_platform_data\n");
2594 if (pd->shared == NULL) {
2595 dev_printk(KERN_ERR, &pdev->dev,
2596 "no mv643xx_eth_platform_data->shared\n");
2600 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2604 mp = netdev_priv(dev);
2605 platform_set_drvdata(pdev, mp);
2607 mp->shared = platform_get_drvdata(pd->shared);
2608 mp->port_num = pd->port_number;
2613 dev->real_num_tx_queues = mp->txq_count;
2615 mib_counters_clear(mp);
2616 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2618 if (mp->phy_addr != -1) {
2619 err = phy_init(mp, pd);
2623 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2625 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2627 init_pscr(mp, pd->speed, pd->duplex);
2629 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2631 init_timer(&mp->rx_oom);
2632 mp->rx_oom.data = (unsigned long)mp;
2633 mp->rx_oom.function = oom_timer_wrapper;
2636 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2638 dev->irq = res->start;
2640 dev->get_stats = mv643xx_eth_get_stats;
2641 dev->hard_start_xmit = mv643xx_eth_xmit;
2642 dev->open = mv643xx_eth_open;
2643 dev->stop = mv643xx_eth_stop;
2644 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2645 dev->set_mac_address = mv643xx_eth_set_mac_address;
2646 dev->do_ioctl = mv643xx_eth_ioctl;
2647 dev->change_mtu = mv643xx_eth_change_mtu;
2648 dev->tx_timeout = mv643xx_eth_tx_timeout;
2649 #ifdef CONFIG_NET_POLL_CONTROLLER
2650 dev->poll_controller = mv643xx_eth_netpoll;
2652 dev->watchdog_timeo = 2 * HZ;
2655 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2656 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2658 SET_NETDEV_DEV(dev, &pdev->dev);
2660 if (mp->shared->win_protect)
2661 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2663 err = register_netdev(dev);
2667 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2668 mp->port_num, print_mac(mac, dev->dev_addr));
2670 if (mp->tx_desc_sram_size > 0)
2671 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2681 static int mv643xx_eth_remove(struct platform_device *pdev)
2683 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2685 unregister_netdev(mp->dev);
2686 flush_scheduled_work();
2687 free_netdev(mp->dev);
2689 platform_set_drvdata(pdev, NULL);
2694 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2696 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2698 /* Mask all interrupts on ethernet port */
2699 wrl(mp, INT_MASK(mp->port_num), 0);
2700 rdl(mp, INT_MASK(mp->port_num));
2702 if (netif_running(mp->dev))
2706 static struct platform_driver mv643xx_eth_driver = {
2707 .probe = mv643xx_eth_probe,
2708 .remove = mv643xx_eth_remove,
2709 .shutdown = mv643xx_eth_shutdown,
2711 .name = MV643XX_ETH_NAME,
2712 .owner = THIS_MODULE,
2716 static int __init mv643xx_eth_init_module(void)
2720 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2722 rc = platform_driver_register(&mv643xx_eth_driver);
2724 platform_driver_unregister(&mv643xx_eth_shared_driver);
2729 module_init(mv643xx_eth_init_module);
2731 static void __exit mv643xx_eth_cleanup_module(void)
2733 platform_driver_unregister(&mv643xx_eth_driver);
2734 platform_driver_unregister(&mv643xx_eth_shared_driver);
2736 module_exit(mv643xx_eth_cleanup_module);
2738 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2739 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2740 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2741 MODULE_LICENSE("GPL");
2742 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2743 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);