2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.3";
62 * Registers shared between all ports.
64 #define PHY_ADDR 0x0000
65 #define SMI_REG 0x0004
66 #define SMI_BUSY 0x10000000
67 #define SMI_READ_VALID 0x08000000
68 #define SMI_OPCODE_READ 0x04000000
69 #define SMI_OPCODE_WRITE 0x00000000
70 #define ERR_INT_CAUSE 0x0080
71 #define ERR_INT_SMI_DONE 0x00000010
72 #define ERR_INT_MASK 0x0084
73 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
74 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
75 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
76 #define WINDOW_BAR_ENABLE 0x0290
77 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
82 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
83 #define UNICAST_PROMISCUOUS_MODE 0x00000001
84 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
85 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
86 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
87 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
88 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
89 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
90 #define TX_FIFO_EMPTY 0x00000400
91 #define TX_IN_PROGRESS 0x00000080
92 #define PORT_SPEED_MASK 0x00000030
93 #define PORT_SPEED_1000 0x00000010
94 #define PORT_SPEED_100 0x00000020
95 #define PORT_SPEED_10 0x00000000
96 #define FLOW_CONTROL_ENABLED 0x00000008
97 #define FULL_DUPLEX 0x00000004
98 #define LINK_UP 0x00000002
99 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
100 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
101 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
102 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
103 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
104 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
105 #define INT_TX_END 0x07f80000
106 #define INT_RX 0x000003fc
107 #define INT_EXT 0x00000002
108 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
109 #define INT_EXT_LINK_PHY 0x00110000
110 #define INT_EXT_TX 0x000000ff
111 #define INT_MASK(p) (0x0468 + ((p) << 10))
112 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
113 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
114 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
115 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
116 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
117 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
118 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
119 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
120 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
121 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
122 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
123 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
124 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
125 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
126 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
127 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
131 * SDMA configuration register.
133 #define RX_BURST_SIZE_16_64BIT (4 << 1)
134 #define BLM_RX_NO_SWAP (1 << 4)
135 #define BLM_TX_NO_SWAP (1 << 5)
136 #define TX_BURST_SIZE_16_64BIT (4 << 22)
138 #if defined(__BIG_ENDIAN)
139 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
140 RX_BURST_SIZE_16_64BIT | \
141 TX_BURST_SIZE_16_64BIT
142 #elif defined(__LITTLE_ENDIAN)
143 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
144 RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT
149 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
154 * Port serial control register.
156 #define SET_MII_SPEED_TO_100 (1 << 24)
157 #define SET_GMII_SPEED_TO_1000 (1 << 23)
158 #define SET_FULL_DUPLEX_MODE (1 << 21)
159 #define MAX_RX_PACKET_9700BYTE (5 << 17)
160 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
161 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
162 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
163 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
164 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
165 #define FORCE_LINK_PASS (1 << 1)
166 #define SERIAL_PORT_ENABLE (1 << 0)
168 #define DEFAULT_RX_QUEUE_SIZE 400
169 #define DEFAULT_TX_QUEUE_SIZE 800
175 #if defined(__BIG_ENDIAN)
177 u16 byte_cnt; /* Descriptor buffer byte count */
178 u16 buf_size; /* Buffer size */
179 u32 cmd_sts; /* Descriptor command status */
180 u32 next_desc_ptr; /* Next descriptor pointer */
181 u32 buf_ptr; /* Descriptor buffer pointer */
185 u16 byte_cnt; /* buffer byte count */
186 u16 l4i_chk; /* CPU provided TCP checksum */
187 u32 cmd_sts; /* Command/status field */
188 u32 next_desc_ptr; /* Pointer to next descriptor */
189 u32 buf_ptr; /* pointer to buffer for this descriptor*/
191 #elif defined(__LITTLE_ENDIAN)
193 u32 cmd_sts; /* Descriptor command status */
194 u16 buf_size; /* Buffer size */
195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 u32 next_desc_ptr; /* Next descriptor pointer */
201 u32 cmd_sts; /* Command/status field */
202 u16 l4i_chk; /* CPU provided TCP checksum */
203 u16 byte_cnt; /* buffer byte count */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 u32 next_desc_ptr; /* Pointer to next descriptor */
208 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
211 /* RX & TX descriptor command */
212 #define BUFFER_OWNED_BY_DMA 0x80000000
214 /* RX & TX descriptor status */
215 #define ERROR_SUMMARY 0x00000001
217 /* RX descriptor status */
218 #define LAYER_4_CHECKSUM_OK 0x40000000
219 #define RX_ENABLE_INTERRUPT 0x20000000
220 #define RX_FIRST_DESC 0x08000000
221 #define RX_LAST_DESC 0x04000000
223 /* TX descriptor command */
224 #define TX_ENABLE_INTERRUPT 0x00800000
225 #define GEN_CRC 0x00400000
226 #define TX_FIRST_DESC 0x00200000
227 #define TX_LAST_DESC 0x00100000
228 #define ZERO_PADDING 0x00080000
229 #define GEN_IP_V4_CHECKSUM 0x00040000
230 #define GEN_TCP_UDP_CHECKSUM 0x00020000
231 #define UDP_FRAME 0x00010000
232 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
233 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
235 #define TX_IHL_SHIFT 11
238 /* global *******************************************************************/
239 struct mv643xx_eth_shared_private {
241 * Ethernet controller base address.
246 * Points at the right SMI instance to use.
248 struct mv643xx_eth_shared_private *smi;
251 * Protects access to SMI_REG, which is shared between ports.
253 struct mutex phy_lock;
256 * If we have access to the error interrupt pin (which is
257 * somewhat misnamed as it not only reflects internal errors
258 * but also reflects SMI completion), use that to wait for
259 * SMI access completion instead of polling the SMI busy bit.
262 wait_queue_head_t smi_busy_wait;
265 * Per-port MBUS window access register value.
270 * Hardware-specific parameters.
273 int extended_rx_coal_limit;
274 int tx_bw_control_moved;
278 /* per-port *****************************************************************/
279 struct mib_counters {
280 u64 good_octets_received;
281 u32 bad_octets_received;
282 u32 internal_mac_transmit_err;
283 u32 good_frames_received;
284 u32 bad_frames_received;
285 u32 broadcast_frames_received;
286 u32 multicast_frames_received;
287 u32 frames_64_octets;
288 u32 frames_65_to_127_octets;
289 u32 frames_128_to_255_octets;
290 u32 frames_256_to_511_octets;
291 u32 frames_512_to_1023_octets;
292 u32 frames_1024_to_max_octets;
293 u64 good_octets_sent;
294 u32 good_frames_sent;
295 u32 excessive_collision;
296 u32 multicast_frames_sent;
297 u32 broadcast_frames_sent;
298 u32 unrec_mac_control_received;
300 u32 good_fc_received;
302 u32 undersize_received;
303 u32 fragments_received;
304 u32 oversize_received;
306 u32 mac_receive_error;
321 struct rx_desc *rx_desc_area;
322 dma_addr_t rx_desc_dma;
323 int rx_desc_area_size;
324 struct sk_buff **rx_skb;
336 struct tx_desc *tx_desc_area;
337 dma_addr_t tx_desc_dma;
338 int tx_desc_area_size;
339 struct sk_buff **tx_skb;
341 unsigned long tx_packets;
342 unsigned long tx_bytes;
343 unsigned long tx_dropped;
346 struct mv643xx_eth_private {
347 struct mv643xx_eth_shared_private *shared;
350 struct net_device *dev;
354 struct mib_counters mib_counters;
355 struct work_struct tx_timeout_task;
356 struct mii_if_info mii;
358 struct napi_struct napi;
369 int default_rx_ring_size;
370 unsigned long rx_desc_sram_addr;
371 int rx_desc_sram_size;
373 struct timer_list rx_oom;
374 struct rx_queue rxq[8];
379 int default_tx_ring_size;
380 unsigned long tx_desc_sram_addr;
381 int tx_desc_sram_size;
383 struct tx_queue txq[8];
387 /* port register accessors **************************************************/
388 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
390 return readl(mp->shared->base + offset);
393 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
395 writel(data, mp->shared->base + offset);
399 /* rxq/txq helper functions *************************************************/
400 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
402 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
405 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
407 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
410 static void rxq_enable(struct rx_queue *rxq)
412 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
413 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
416 static void rxq_disable(struct rx_queue *rxq)
418 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
419 u8 mask = 1 << rxq->index;
421 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
422 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
426 static void txq_reset_hw_ptr(struct tx_queue *txq)
428 struct mv643xx_eth_private *mp = txq_to_mp(txq);
429 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
432 addr = (u32)txq->tx_desc_dma;
433 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
437 static void txq_enable(struct tx_queue *txq)
439 struct mv643xx_eth_private *mp = txq_to_mp(txq);
440 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
443 static void txq_disable(struct tx_queue *txq)
445 struct mv643xx_eth_private *mp = txq_to_mp(txq);
446 u8 mask = 1 << txq->index;
448 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
449 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
453 static void txq_maybe_wake(struct tx_queue *txq)
455 struct mv643xx_eth_private *mp = txq_to_mp(txq);
456 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
458 if (netif_tx_queue_stopped(nq)) {
459 __netif_tx_lock(nq, smp_processor_id());
460 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
461 netif_tx_wake_queue(nq);
462 __netif_tx_unlock(nq);
467 /* rx napi ******************************************************************/
468 static int rxq_process(struct rx_queue *rxq, int budget)
470 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
471 struct net_device_stats *stats = &mp->dev->stats;
475 while (rx < budget && rxq->rx_desc_count) {
476 struct rx_desc *rx_desc;
477 unsigned int cmd_sts;
480 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
482 cmd_sts = rx_desc->cmd_sts;
483 if (cmd_sts & BUFFER_OWNED_BY_DMA)
487 skb = rxq->rx_skb[rxq->rx_curr_desc];
488 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
491 if (rxq->rx_curr_desc == rxq->rx_ring_size)
492 rxq->rx_curr_desc = 0;
494 dma_unmap_single(NULL, rx_desc->buf_ptr,
495 rx_desc->buf_size, DMA_FROM_DEVICE);
496 rxq->rx_desc_count--;
499 mp->work_rx_refill |= 1 << rxq->index;
504 * Note that the descriptor byte count includes 2 dummy
505 * bytes automatically inserted by the hardware at the
506 * start of the packet (which we don't count), and a 4
507 * byte CRC at the end of the packet (which we do count).
510 stats->rx_bytes += rx_desc->byte_cnt - 2;
513 * In case we received a packet without first / last bits
514 * on, or the error summary bit is set, the packet needs
517 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
518 (RX_FIRST_DESC | RX_LAST_DESC))
519 || (cmd_sts & ERROR_SUMMARY)) {
522 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
523 (RX_FIRST_DESC | RX_LAST_DESC)) {
525 dev_printk(KERN_ERR, &mp->dev->dev,
526 "received packet spanning "
527 "multiple descriptors\n");
530 if (cmd_sts & ERROR_SUMMARY)
536 * The -4 is for the CRC in the trailer of the
539 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
541 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
542 skb->ip_summed = CHECKSUM_UNNECESSARY;
544 (cmd_sts & 0x0007fff8) >> 3);
546 skb->protocol = eth_type_trans(skb, mp->dev);
547 netif_receive_skb(skb);
550 mp->dev->last_rx = jiffies;
554 mp->work_rx &= ~(1 << rxq->index);
559 static int rxq_refill(struct rx_queue *rxq, int budget)
561 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
566 * Reserve 2+14 bytes for an ethernet header (the hardware
567 * automatically prepends 2 bytes of dummy data to each
568 * received packet), 16 bytes for up to four VLAN tags, and
569 * 4 bytes for the trailing FCS -- 36 bytes total.
571 skb_size = rxq_to_mp(rxq)->dev->mtu + 36;
574 * Make sure that the skb size is a multiple of 8 bytes, as
575 * the lower three bits of the receive descriptor's buffer
576 * size field are ignored by the hardware.
578 skb_size = (skb_size + 7) & ~7;
581 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
586 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
588 mp->work_rx_oom |= 1 << rxq->index;
592 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
594 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
597 rxq->rx_desc_count++;
599 rx = rxq->rx_used_desc++;
600 if (rxq->rx_used_desc == rxq->rx_ring_size)
601 rxq->rx_used_desc = 0;
603 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
604 skb_size, DMA_FROM_DEVICE);
605 rxq->rx_desc_area[rx].buf_size = skb_size;
606 rxq->rx_skb[rx] = skb;
608 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
613 * The hardware automatically prepends 2 bytes of
614 * dummy data to each received packet, so that the
615 * IP header ends up 16-byte aligned.
620 if (refilled < budget)
621 mp->work_rx_refill &= ~(1 << rxq->index);
628 /* tx ***********************************************************************/
629 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
633 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
634 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
635 if (fragp->size <= 8 && fragp->page_offset & 7)
642 static int txq_alloc_desc_index(struct tx_queue *txq)
646 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
648 tx_desc_curr = txq->tx_curr_desc++;
649 if (txq->tx_curr_desc == txq->tx_ring_size)
650 txq->tx_curr_desc = 0;
652 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
657 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
659 int nr_frags = skb_shinfo(skb)->nr_frags;
662 for (frag = 0; frag < nr_frags; frag++) {
663 skb_frag_t *this_frag;
665 struct tx_desc *desc;
667 this_frag = &skb_shinfo(skb)->frags[frag];
668 tx_index = txq_alloc_desc_index(txq);
669 desc = &txq->tx_desc_area[tx_index];
672 * The last fragment will generate an interrupt
673 * which will free the skb on TX completion.
675 if (frag == nr_frags - 1) {
676 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
677 ZERO_PADDING | TX_LAST_DESC |
679 txq->tx_skb[tx_index] = skb;
681 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
682 txq->tx_skb[tx_index] = NULL;
686 desc->byte_cnt = this_frag->size;
687 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
688 this_frag->page_offset,
694 static inline __be16 sum16_as_be(__sum16 sum)
696 return (__force __be16)sum;
699 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
701 struct mv643xx_eth_private *mp = txq_to_mp(txq);
702 int nr_frags = skb_shinfo(skb)->nr_frags;
704 struct tx_desc *desc;
708 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
710 tx_index = txq_alloc_desc_index(txq);
711 desc = &txq->tx_desc_area[tx_index];
714 txq_submit_frag_skb(txq, skb);
716 length = skb_headlen(skb);
717 txq->tx_skb[tx_index] = NULL;
719 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
721 txq->tx_skb[tx_index] = skb;
724 desc->byte_cnt = length;
725 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
727 if (skb->ip_summed == CHECKSUM_PARTIAL) {
730 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
731 skb->protocol != htons(ETH_P_8021Q));
733 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
735 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
737 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
738 switch (mac_hdr_len - ETH_HLEN) {
742 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
745 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
748 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
749 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
753 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
754 "mac header length is %d?!\n", mac_hdr_len);
758 switch (ip_hdr(skb)->protocol) {
760 cmd_sts |= UDP_FRAME;
761 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
764 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
770 /* Errata BTS #50, IHL must be 5 if no HW checksum */
771 cmd_sts |= 5 << TX_IHL_SHIFT;
775 /* ensure all other descriptors are written before first cmd_sts */
777 desc->cmd_sts = cmd_sts;
779 /* clear TX_END status */
780 mp->work_tx_end &= ~(1 << txq->index);
782 /* ensure all descriptors are written before poking hardware */
786 txq->tx_desc_count += nr_frags + 1;
789 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
791 struct mv643xx_eth_private *mp = netdev_priv(dev);
793 struct tx_queue *txq;
794 struct netdev_queue *nq;
797 queue = skb_get_queue_mapping(skb);
798 txq = mp->txq + queue;
799 nq = netdev_get_tx_queue(dev, queue);
801 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
803 dev_printk(KERN_DEBUG, &dev->dev,
804 "failed to linearize skb with tiny "
805 "unaligned fragment\n");
806 return NETDEV_TX_BUSY;
809 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
811 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
816 txq_submit_skb(txq, skb);
817 txq->tx_bytes += skb->len;
819 dev->trans_start = jiffies;
821 entries_left = txq->tx_ring_size - txq->tx_desc_count;
822 if (entries_left < MAX_SKB_FRAGS + 1)
823 netif_tx_stop_queue(nq);
829 /* tx napi ******************************************************************/
830 static void txq_kick(struct tx_queue *txq)
832 struct mv643xx_eth_private *mp = txq_to_mp(txq);
833 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
837 __netif_tx_lock(nq, smp_processor_id());
839 if (rdl(mp, TXQ_COMMAND(mp->port_num)) & (1 << txq->index))
842 hw_desc_ptr = rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index));
843 expected_ptr = (u32)txq->tx_desc_dma +
844 txq->tx_curr_desc * sizeof(struct tx_desc);
846 if (hw_desc_ptr != expected_ptr)
850 __netif_tx_unlock(nq);
852 mp->work_tx_end &= ~(1 << txq->index);
855 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
857 struct mv643xx_eth_private *mp = txq_to_mp(txq);
858 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
861 __netif_tx_lock(nq, smp_processor_id());
864 while (reclaimed < budget && txq->tx_desc_count > 0) {
866 struct tx_desc *desc;
870 tx_index = txq->tx_used_desc;
871 desc = &txq->tx_desc_area[tx_index];
872 cmd_sts = desc->cmd_sts;
874 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
877 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
880 txq->tx_used_desc = tx_index + 1;
881 if (txq->tx_used_desc == txq->tx_ring_size)
882 txq->tx_used_desc = 0;
885 txq->tx_desc_count--;
887 skb = txq->tx_skb[tx_index];
888 txq->tx_skb[tx_index] = NULL;
890 if (cmd_sts & ERROR_SUMMARY) {
891 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
892 mp->dev->stats.tx_errors++;
895 if (cmd_sts & TX_FIRST_DESC) {
896 dma_unmap_single(NULL, desc->buf_ptr,
897 desc->byte_cnt, DMA_TO_DEVICE);
899 dma_unmap_page(NULL, desc->buf_ptr,
900 desc->byte_cnt, DMA_TO_DEVICE);
907 __netif_tx_unlock(nq);
909 if (reclaimed < budget)
910 mp->work_tx &= ~(1 << txq->index);
916 /* tx rate control **********************************************************/
918 * Set total maximum TX rate (shared by all TX queues for this port)
919 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
921 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
927 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
928 if (token_rate > 1023)
931 mtu = (mp->dev->mtu + 255) >> 8;
935 bucket_size = (burst + 255) >> 8;
936 if (bucket_size > 65535)
939 if (mp->shared->tx_bw_control_moved) {
940 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
941 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
942 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
944 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
945 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
946 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
950 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
952 struct mv643xx_eth_private *mp = txq_to_mp(txq);
956 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
957 if (token_rate > 1023)
960 bucket_size = (burst + 255) >> 8;
961 if (bucket_size > 65535)
964 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
965 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
966 (bucket_size << 10) | token_rate);
969 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
971 struct mv643xx_eth_private *mp = txq_to_mp(txq);
976 * Turn on fixed priority mode.
978 if (mp->shared->tx_bw_control_moved)
979 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
981 off = TXQ_FIX_PRIO_CONF(mp->port_num);
984 val |= 1 << txq->index;
988 static void txq_set_wrr(struct tx_queue *txq, int weight)
990 struct mv643xx_eth_private *mp = txq_to_mp(txq);
995 * Turn off fixed priority mode.
997 if (mp->shared->tx_bw_control_moved)
998 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
1000 off = TXQ_FIX_PRIO_CONF(mp->port_num);
1003 val &= ~(1 << txq->index);
1007 * Configure WRR weight for this queue.
1009 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
1012 val = (val & ~0xff) | (weight & 0xff);
1017 /* mii management interface *************************************************/
1018 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1020 struct mv643xx_eth_shared_private *msp = dev_id;
1022 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1023 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1024 wake_up(&msp->smi_busy_wait);
1031 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1033 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1036 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1038 if (msp->err_interrupt == NO_IRQ) {
1041 for (i = 0; !smi_is_done(msp); i++) {
1050 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1051 msecs_to_jiffies(100)))
1057 static int smi_reg_read(struct mv643xx_eth_private *mp,
1058 unsigned int addr, unsigned int reg)
1060 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
1061 void __iomem *smi_reg = msp->base + SMI_REG;
1064 mutex_lock(&msp->phy_lock);
1066 if (smi_wait_ready(msp)) {
1067 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1072 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1074 if (smi_wait_ready(msp)) {
1075 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1080 ret = readl(smi_reg);
1081 if (!(ret & SMI_READ_VALID)) {
1082 printk("%s: SMI bus read not valid\n", mp->dev->name);
1090 mutex_unlock(&msp->phy_lock);
1095 static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1096 unsigned int reg, unsigned int value)
1098 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
1099 void __iomem *smi_reg = msp->base + SMI_REG;
1101 mutex_lock(&msp->phy_lock);
1103 if (smi_wait_ready(msp)) {
1104 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1105 mutex_unlock(&msp->phy_lock);
1109 writel(SMI_OPCODE_WRITE | (reg << 21) |
1110 (addr << 16) | (value & 0xffff), smi_reg);
1112 mutex_unlock(&msp->phy_lock);
1118 /* statistics ***************************************************************/
1119 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1121 struct mv643xx_eth_private *mp = netdev_priv(dev);
1122 struct net_device_stats *stats = &dev->stats;
1123 unsigned long tx_packets = 0;
1124 unsigned long tx_bytes = 0;
1125 unsigned long tx_dropped = 0;
1128 for (i = 0; i < mp->txq_count; i++) {
1129 struct tx_queue *txq = mp->txq + i;
1131 tx_packets += txq->tx_packets;
1132 tx_bytes += txq->tx_bytes;
1133 tx_dropped += txq->tx_dropped;
1136 stats->tx_packets = tx_packets;
1137 stats->tx_bytes = tx_bytes;
1138 stats->tx_dropped = tx_dropped;
1143 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1145 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1148 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1152 for (i = 0; i < 0x80; i += 4)
1156 static void mib_counters_update(struct mv643xx_eth_private *mp)
1158 struct mib_counters *p = &mp->mib_counters;
1160 p->good_octets_received += mib_read(mp, 0x00);
1161 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1162 p->bad_octets_received += mib_read(mp, 0x08);
1163 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1164 p->good_frames_received += mib_read(mp, 0x10);
1165 p->bad_frames_received += mib_read(mp, 0x14);
1166 p->broadcast_frames_received += mib_read(mp, 0x18);
1167 p->multicast_frames_received += mib_read(mp, 0x1c);
1168 p->frames_64_octets += mib_read(mp, 0x20);
1169 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1170 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1171 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1172 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1173 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1174 p->good_octets_sent += mib_read(mp, 0x38);
1175 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1176 p->good_frames_sent += mib_read(mp, 0x40);
1177 p->excessive_collision += mib_read(mp, 0x44);
1178 p->multicast_frames_sent += mib_read(mp, 0x48);
1179 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1180 p->unrec_mac_control_received += mib_read(mp, 0x50);
1181 p->fc_sent += mib_read(mp, 0x54);
1182 p->good_fc_received += mib_read(mp, 0x58);
1183 p->bad_fc_received += mib_read(mp, 0x5c);
1184 p->undersize_received += mib_read(mp, 0x60);
1185 p->fragments_received += mib_read(mp, 0x64);
1186 p->oversize_received += mib_read(mp, 0x68);
1187 p->jabber_received += mib_read(mp, 0x6c);
1188 p->mac_receive_error += mib_read(mp, 0x70);
1189 p->bad_crc_event += mib_read(mp, 0x74);
1190 p->collision += mib_read(mp, 0x78);
1191 p->late_collision += mib_read(mp, 0x7c);
1195 /* ethtool ******************************************************************/
1196 struct mv643xx_eth_stats {
1197 char stat_string[ETH_GSTRING_LEN];
1204 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1205 offsetof(struct net_device, stats.m), -1 }
1207 #define MIBSTAT(m) \
1208 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1209 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1211 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1220 MIBSTAT(good_octets_received),
1221 MIBSTAT(bad_octets_received),
1222 MIBSTAT(internal_mac_transmit_err),
1223 MIBSTAT(good_frames_received),
1224 MIBSTAT(bad_frames_received),
1225 MIBSTAT(broadcast_frames_received),
1226 MIBSTAT(multicast_frames_received),
1227 MIBSTAT(frames_64_octets),
1228 MIBSTAT(frames_65_to_127_octets),
1229 MIBSTAT(frames_128_to_255_octets),
1230 MIBSTAT(frames_256_to_511_octets),
1231 MIBSTAT(frames_512_to_1023_octets),
1232 MIBSTAT(frames_1024_to_max_octets),
1233 MIBSTAT(good_octets_sent),
1234 MIBSTAT(good_frames_sent),
1235 MIBSTAT(excessive_collision),
1236 MIBSTAT(multicast_frames_sent),
1237 MIBSTAT(broadcast_frames_sent),
1238 MIBSTAT(unrec_mac_control_received),
1240 MIBSTAT(good_fc_received),
1241 MIBSTAT(bad_fc_received),
1242 MIBSTAT(undersize_received),
1243 MIBSTAT(fragments_received),
1244 MIBSTAT(oversize_received),
1245 MIBSTAT(jabber_received),
1246 MIBSTAT(mac_receive_error),
1247 MIBSTAT(bad_crc_event),
1249 MIBSTAT(late_collision),
1252 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1254 struct mv643xx_eth_private *mp = netdev_priv(dev);
1257 err = mii_ethtool_gset(&mp->mii, cmd);
1260 * The MAC does not support 1000baseT_Half.
1262 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1263 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1268 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1270 struct mv643xx_eth_private *mp = netdev_priv(dev);
1273 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1275 cmd->supported = SUPPORTED_MII;
1276 cmd->advertising = ADVERTISED_MII;
1277 switch (port_status & PORT_SPEED_MASK) {
1279 cmd->speed = SPEED_10;
1281 case PORT_SPEED_100:
1282 cmd->speed = SPEED_100;
1284 case PORT_SPEED_1000:
1285 cmd->speed = SPEED_1000;
1291 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1292 cmd->port = PORT_MII;
1293 cmd->phy_address = 0;
1294 cmd->transceiver = XCVR_INTERNAL;
1295 cmd->autoneg = AUTONEG_DISABLE;
1302 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1304 struct mv643xx_eth_private *mp = netdev_priv(dev);
1307 * The MAC does not support 1000baseT_Half.
1309 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1311 return mii_ethtool_sset(&mp->mii, cmd);
1314 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1319 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1320 struct ethtool_drvinfo *drvinfo)
1322 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1323 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1324 strncpy(drvinfo->fw_version, "N/A", 32);
1325 strncpy(drvinfo->bus_info, "platform", 32);
1326 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1329 static int mv643xx_eth_nway_reset(struct net_device *dev)
1331 struct mv643xx_eth_private *mp = netdev_priv(dev);
1333 return mii_nway_restart(&mp->mii);
1336 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1341 static u32 mv643xx_eth_get_link(struct net_device *dev)
1343 struct mv643xx_eth_private *mp = netdev_priv(dev);
1345 return mii_link_ok(&mp->mii);
1348 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1353 static void mv643xx_eth_get_strings(struct net_device *dev,
1354 uint32_t stringset, uint8_t *data)
1358 if (stringset == ETH_SS_STATS) {
1359 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1360 memcpy(data + i * ETH_GSTRING_LEN,
1361 mv643xx_eth_stats[i].stat_string,
1367 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1368 struct ethtool_stats *stats,
1371 struct mv643xx_eth_private *mp = netdev_priv(dev);
1374 mv643xx_eth_get_stats(dev);
1375 mib_counters_update(mp);
1377 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1378 const struct mv643xx_eth_stats *stat;
1381 stat = mv643xx_eth_stats + i;
1383 if (stat->netdev_off >= 0)
1384 p = ((void *)mp->dev) + stat->netdev_off;
1386 p = ((void *)mp) + stat->mp_off;
1388 data[i] = (stat->sizeof_stat == 8) ?
1389 *(uint64_t *)p : *(uint32_t *)p;
1393 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1395 if (sset == ETH_SS_STATS)
1396 return ARRAY_SIZE(mv643xx_eth_stats);
1401 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1402 .get_settings = mv643xx_eth_get_settings,
1403 .set_settings = mv643xx_eth_set_settings,
1404 .get_drvinfo = mv643xx_eth_get_drvinfo,
1405 .nway_reset = mv643xx_eth_nway_reset,
1406 .get_link = mv643xx_eth_get_link,
1407 .set_sg = ethtool_op_set_sg,
1408 .get_strings = mv643xx_eth_get_strings,
1409 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1410 .get_sset_count = mv643xx_eth_get_sset_count,
1413 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1414 .get_settings = mv643xx_eth_get_settings_phyless,
1415 .set_settings = mv643xx_eth_set_settings_phyless,
1416 .get_drvinfo = mv643xx_eth_get_drvinfo,
1417 .nway_reset = mv643xx_eth_nway_reset_phyless,
1418 .get_link = mv643xx_eth_get_link_phyless,
1419 .set_sg = ethtool_op_set_sg,
1420 .get_strings = mv643xx_eth_get_strings,
1421 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1422 .get_sset_count = mv643xx_eth_get_sset_count,
1426 /* address handling *********************************************************/
1427 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1432 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1433 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1435 addr[0] = (mac_h >> 24) & 0xff;
1436 addr[1] = (mac_h >> 16) & 0xff;
1437 addr[2] = (mac_h >> 8) & 0xff;
1438 addr[3] = mac_h & 0xff;
1439 addr[4] = (mac_l >> 8) & 0xff;
1440 addr[5] = mac_l & 0xff;
1443 static void init_mac_tables(struct mv643xx_eth_private *mp)
1447 for (i = 0; i < 0x100; i += 4) {
1448 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1449 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1452 for (i = 0; i < 0x10; i += 4)
1453 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1456 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1457 int table, unsigned char entry)
1459 unsigned int table_reg;
1461 /* Set "accepts frame bit" at specified table entry */
1462 table_reg = rdl(mp, table + (entry & 0xfc));
1463 table_reg |= 0x01 << (8 * (entry & 3));
1464 wrl(mp, table + (entry & 0xfc), table_reg);
1467 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1473 mac_l = (addr[4] << 8) | addr[5];
1474 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1476 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1477 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1479 table = UNICAST_TABLE(mp->port_num);
1480 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1483 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1485 struct mv643xx_eth_private *mp = netdev_priv(dev);
1487 /* +2 is for the offset of the HW addr type */
1488 memcpy(dev->dev_addr, addr + 2, 6);
1490 init_mac_tables(mp);
1491 uc_addr_set(mp, dev->dev_addr);
1496 static int addr_crc(unsigned char *addr)
1501 for (i = 0; i < 6; i++) {
1504 crc = (crc ^ addr[i]) << 8;
1505 for (j = 7; j >= 0; j--) {
1506 if (crc & (0x100 << j))
1514 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1516 struct mv643xx_eth_private *mp = netdev_priv(dev);
1518 struct dev_addr_list *addr;
1521 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1522 if (dev->flags & IFF_PROMISC)
1523 port_config |= UNICAST_PROMISCUOUS_MODE;
1525 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1526 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1528 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1529 int port_num = mp->port_num;
1530 u32 accept = 0x01010101;
1532 for (i = 0; i < 0x100; i += 4) {
1533 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1534 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1539 for (i = 0; i < 0x100; i += 4) {
1540 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1541 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1544 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1545 u8 *a = addr->da_addr;
1548 if (addr->da_addrlen != 6)
1551 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1552 table = SPECIAL_MCAST_TABLE(mp->port_num);
1553 set_filter_table_entry(mp, table, a[5]);
1555 int crc = addr_crc(a);
1557 table = OTHER_MCAST_TABLE(mp->port_num);
1558 set_filter_table_entry(mp, table, crc);
1564 /* rx/tx queue initialisation ***********************************************/
1565 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1567 struct rx_queue *rxq = mp->rxq + index;
1568 struct rx_desc *rx_desc;
1574 rxq->rx_ring_size = mp->default_rx_ring_size;
1576 rxq->rx_desc_count = 0;
1577 rxq->rx_curr_desc = 0;
1578 rxq->rx_used_desc = 0;
1580 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1582 if (index == 0 && size <= mp->rx_desc_sram_size) {
1583 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1584 mp->rx_desc_sram_size);
1585 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1587 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1592 if (rxq->rx_desc_area == NULL) {
1593 dev_printk(KERN_ERR, &mp->dev->dev,
1594 "can't allocate rx ring (%d bytes)\n", size);
1597 memset(rxq->rx_desc_area, 0, size);
1599 rxq->rx_desc_area_size = size;
1600 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1602 if (rxq->rx_skb == NULL) {
1603 dev_printk(KERN_ERR, &mp->dev->dev,
1604 "can't allocate rx skb ring\n");
1608 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1609 for (i = 0; i < rxq->rx_ring_size; i++) {
1613 if (nexti == rxq->rx_ring_size)
1616 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1617 nexti * sizeof(struct rx_desc);
1624 if (index == 0 && size <= mp->rx_desc_sram_size)
1625 iounmap(rxq->rx_desc_area);
1627 dma_free_coherent(NULL, size,
1635 static void rxq_deinit(struct rx_queue *rxq)
1637 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1642 for (i = 0; i < rxq->rx_ring_size; i++) {
1643 if (rxq->rx_skb[i]) {
1644 dev_kfree_skb(rxq->rx_skb[i]);
1645 rxq->rx_desc_count--;
1649 if (rxq->rx_desc_count) {
1650 dev_printk(KERN_ERR, &mp->dev->dev,
1651 "error freeing rx ring -- %d skbs stuck\n",
1652 rxq->rx_desc_count);
1655 if (rxq->index == 0 &&
1656 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1657 iounmap(rxq->rx_desc_area);
1659 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1660 rxq->rx_desc_area, rxq->rx_desc_dma);
1665 static int txq_init(struct mv643xx_eth_private *mp, int index)
1667 struct tx_queue *txq = mp->txq + index;
1668 struct tx_desc *tx_desc;
1674 txq->tx_ring_size = mp->default_tx_ring_size;
1676 txq->tx_desc_count = 0;
1677 txq->tx_curr_desc = 0;
1678 txq->tx_used_desc = 0;
1680 size = txq->tx_ring_size * sizeof(struct tx_desc);
1682 if (index == 0 && size <= mp->tx_desc_sram_size) {
1683 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1684 mp->tx_desc_sram_size);
1685 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1687 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1692 if (txq->tx_desc_area == NULL) {
1693 dev_printk(KERN_ERR, &mp->dev->dev,
1694 "can't allocate tx ring (%d bytes)\n", size);
1697 memset(txq->tx_desc_area, 0, size);
1699 txq->tx_desc_area_size = size;
1700 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1702 if (txq->tx_skb == NULL) {
1703 dev_printk(KERN_ERR, &mp->dev->dev,
1704 "can't allocate tx skb ring\n");
1708 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1709 for (i = 0; i < txq->tx_ring_size; i++) {
1710 struct tx_desc *txd = tx_desc + i;
1714 if (nexti == txq->tx_ring_size)
1718 txd->next_desc_ptr = txq->tx_desc_dma +
1719 nexti * sizeof(struct tx_desc);
1725 if (index == 0 && size <= mp->tx_desc_sram_size)
1726 iounmap(txq->tx_desc_area);
1728 dma_free_coherent(NULL, size,
1736 static void txq_deinit(struct tx_queue *txq)
1738 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1741 txq_reclaim(txq, txq->tx_ring_size, 1);
1743 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1745 if (txq->index == 0 &&
1746 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1747 iounmap(txq->tx_desc_area);
1749 dma_free_coherent(NULL, txq->tx_desc_area_size,
1750 txq->tx_desc_area, txq->tx_desc_dma);
1756 /* netdev ops and related ***************************************************/
1757 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1762 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1763 (INT_TX_END | INT_RX | INT_EXT);
1768 if (int_cause & INT_EXT)
1769 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num));
1771 int_cause &= INT_TX_END | INT_RX;
1773 wrl(mp, INT_CAUSE(mp->port_num), ~int_cause);
1774 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1775 ~(rdl(mp, TXQ_COMMAND(mp->port_num)) & 0xff);
1776 mp->work_rx |= (int_cause & INT_RX) >> 2;
1779 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1780 if (int_cause_ext) {
1781 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1782 if (int_cause_ext & INT_EXT_LINK_PHY)
1784 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1790 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1792 struct net_device *dev = (struct net_device *)dev_id;
1793 struct mv643xx_eth_private *mp = netdev_priv(dev);
1795 if (unlikely(!mv643xx_eth_collect_events(mp)))
1798 wrl(mp, INT_MASK(mp->port_num), 0);
1799 napi_schedule(&mp->napi);
1804 static void handle_link_event(struct mv643xx_eth_private *mp)
1806 struct net_device *dev = mp->dev;
1812 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1813 if (!(port_status & LINK_UP)) {
1814 if (netif_carrier_ok(dev)) {
1817 printk(KERN_INFO "%s: link down\n", dev->name);
1819 netif_carrier_off(dev);
1821 for (i = 0; i < mp->txq_count; i++) {
1822 struct tx_queue *txq = mp->txq + i;
1824 txq_reclaim(txq, txq->tx_ring_size, 1);
1825 txq_reset_hw_ptr(txq);
1831 switch (port_status & PORT_SPEED_MASK) {
1835 case PORT_SPEED_100:
1838 case PORT_SPEED_1000:
1845 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1846 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1848 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1849 "flow control %sabled\n", dev->name,
1850 speed, duplex ? "full" : "half",
1853 if (!netif_carrier_ok(dev))
1854 netif_carrier_on(dev);
1857 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1859 struct mv643xx_eth_private *mp;
1862 mp = container_of(napi, struct mv643xx_eth_private, napi);
1864 mp->work_rx_refill |= mp->work_rx_oom;
1865 mp->work_rx_oom = 0;
1868 while (work_done < budget) {
1873 if (mp->work_link) {
1875 handle_link_event(mp);
1879 queue_mask = mp->work_tx | mp->work_tx_end |
1880 mp->work_rx | mp->work_rx_refill;
1882 if (mv643xx_eth_collect_events(mp))
1887 queue = fls(queue_mask) - 1;
1888 queue_mask = 1 << queue;
1890 work_tbd = budget - work_done;
1894 if (mp->work_tx_end & queue_mask) {
1895 txq_kick(mp->txq + queue);
1896 } else if (mp->work_tx & queue_mask) {
1897 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1898 txq_maybe_wake(mp->txq + queue);
1899 } else if (mp->work_rx & queue_mask) {
1900 work_done += rxq_process(mp->rxq + queue, work_tbd);
1901 } else if (mp->work_rx_refill & queue_mask) {
1902 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1908 if (work_done < budget) {
1909 if (mp->work_rx_oom)
1910 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1911 napi_complete(napi);
1912 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
1918 static inline void oom_timer_wrapper(unsigned long data)
1920 struct mv643xx_eth_private *mp = (void *)data;
1922 napi_schedule(&mp->napi);
1925 static void phy_reset(struct mv643xx_eth_private *mp)
1929 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1934 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1938 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1939 } while (data >= 0 && data & BMCR_RESET);
1942 static void port_start(struct mv643xx_eth_private *mp)
1948 * Perform PHY reset, if there is a PHY.
1950 if (mp->phy_addr != -1) {
1951 struct ethtool_cmd cmd;
1953 mv643xx_eth_get_settings(mp->dev, &cmd);
1955 mv643xx_eth_set_settings(mp->dev, &cmd);
1959 * Configure basic link parameters.
1961 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1963 pscr |= SERIAL_PORT_ENABLE;
1964 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1966 pscr |= DO_NOT_FORCE_LINK_FAIL;
1967 if (mp->phy_addr == -1)
1968 pscr |= FORCE_LINK_PASS;
1969 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1971 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1974 * Configure TX path and queues.
1976 tx_set_rate(mp, 1000000000, 16777216);
1977 for (i = 0; i < mp->txq_count; i++) {
1978 struct tx_queue *txq = mp->txq + i;
1980 txq_reset_hw_ptr(txq);
1981 txq_set_rate(txq, 1000000000, 16777216);
1982 txq_set_fixed_prio_mode(txq);
1986 * Add configured unicast address to address filter table.
1988 uc_addr_set(mp, mp->dev->dev_addr);
1991 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1992 * frames to RX queue #0.
1994 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1997 * Treat BPDUs as normal multicasts, and disable partition mode.
1999 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
2002 * Enable the receive queues.
2004 for (i = 0; i < mp->rxq_count; i++) {
2005 struct rx_queue *rxq = mp->rxq + i;
2006 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
2009 addr = (u32)rxq->rx_desc_dma;
2010 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2017 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2019 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2022 val = rdl(mp, SDMA_CONFIG(mp->port_num));
2023 if (mp->shared->extended_rx_coal_limit) {
2027 val |= (coal & 0x8000) << 10;
2028 val |= (coal & 0x7fff) << 7;
2033 val |= (coal & 0x3fff) << 8;
2035 wrl(mp, SDMA_CONFIG(mp->port_num), val);
2038 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2040 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2044 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2047 static int mv643xx_eth_open(struct net_device *dev)
2049 struct mv643xx_eth_private *mp = netdev_priv(dev);
2053 wrl(mp, INT_CAUSE(mp->port_num), 0);
2054 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2055 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2057 err = request_irq(dev->irq, mv643xx_eth_irq,
2058 IRQF_SHARED, dev->name, dev);
2060 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2064 init_mac_tables(mp);
2066 napi_enable(&mp->napi);
2068 for (i = 0; i < mp->rxq_count; i++) {
2069 err = rxq_init(mp, i);
2072 rxq_deinit(mp->rxq + i);
2076 rxq_refill(mp->rxq + i, INT_MAX);
2079 if (mp->work_rx_oom) {
2080 mp->rx_oom.expires = jiffies + (HZ / 10);
2081 add_timer(&mp->rx_oom);
2084 for (i = 0; i < mp->txq_count; i++) {
2085 err = txq_init(mp, i);
2088 txq_deinit(mp->txq + i);
2093 netif_carrier_off(dev);
2100 wrl(mp, INT_MASK_EXT(mp->port_num), INT_EXT_LINK_PHY | INT_EXT_TX);
2101 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2107 for (i = 0; i < mp->rxq_count; i++)
2108 rxq_deinit(mp->rxq + i);
2110 free_irq(dev->irq, dev);
2115 static void port_reset(struct mv643xx_eth_private *mp)
2120 for (i = 0; i < mp->rxq_count; i++)
2121 rxq_disable(mp->rxq + i);
2122 for (i = 0; i < mp->txq_count; i++)
2123 txq_disable(mp->txq + i);
2126 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2128 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2133 /* Reset the Enable bit in the Configuration Register */
2134 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2135 data &= ~(SERIAL_PORT_ENABLE |
2136 DO_NOT_FORCE_LINK_FAIL |
2138 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2141 static int mv643xx_eth_stop(struct net_device *dev)
2143 struct mv643xx_eth_private *mp = netdev_priv(dev);
2146 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2147 rdl(mp, INT_MASK(mp->port_num));
2149 napi_disable(&mp->napi);
2151 del_timer_sync(&mp->rx_oom);
2153 netif_carrier_off(dev);
2155 free_irq(dev->irq, dev);
2158 mv643xx_eth_get_stats(dev);
2159 mib_counters_update(mp);
2161 for (i = 0; i < mp->rxq_count; i++)
2162 rxq_deinit(mp->rxq + i);
2163 for (i = 0; i < mp->txq_count; i++)
2164 txq_deinit(mp->txq + i);
2169 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2171 struct mv643xx_eth_private *mp = netdev_priv(dev);
2173 if (mp->phy_addr != -1)
2174 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2179 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2181 struct mv643xx_eth_private *mp = netdev_priv(dev);
2183 if (new_mtu < 64 || new_mtu > 9500)
2187 tx_set_rate(mp, 1000000000, 16777216);
2189 if (!netif_running(dev))
2193 * Stop and then re-open the interface. This will allocate RX
2194 * skbs of the new MTU.
2195 * There is a possible danger that the open will not succeed,
2196 * due to memory being full.
2198 mv643xx_eth_stop(dev);
2199 if (mv643xx_eth_open(dev)) {
2200 dev_printk(KERN_ERR, &dev->dev,
2201 "fatal error on re-opening device after "
2208 static void tx_timeout_task(struct work_struct *ugly)
2210 struct mv643xx_eth_private *mp;
2212 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2213 if (netif_running(mp->dev)) {
2214 netif_tx_stop_all_queues(mp->dev);
2217 netif_tx_wake_all_queues(mp->dev);
2221 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2223 struct mv643xx_eth_private *mp = netdev_priv(dev);
2225 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2227 schedule_work(&mp->tx_timeout_task);
2230 #ifdef CONFIG_NET_POLL_CONTROLLER
2231 static void mv643xx_eth_netpoll(struct net_device *dev)
2233 struct mv643xx_eth_private *mp = netdev_priv(dev);
2235 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2236 rdl(mp, INT_MASK(mp->port_num));
2238 mv643xx_eth_irq(dev->irq, dev);
2240 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2244 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2246 struct mv643xx_eth_private *mp = netdev_priv(dev);
2247 return smi_reg_read(mp, addr, reg);
2250 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2252 struct mv643xx_eth_private *mp = netdev_priv(dev);
2253 smi_reg_write(mp, addr, reg, val);
2257 /* platform glue ************************************************************/
2259 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2260 struct mbus_dram_target_info *dram)
2262 void __iomem *base = msp->base;
2267 for (i = 0; i < 6; i++) {
2268 writel(0, base + WINDOW_BASE(i));
2269 writel(0, base + WINDOW_SIZE(i));
2271 writel(0, base + WINDOW_REMAP_HIGH(i));
2277 for (i = 0; i < dram->num_cs; i++) {
2278 struct mbus_dram_window *cs = dram->cs + i;
2280 writel((cs->base & 0xffff0000) |
2281 (cs->mbus_attr << 8) |
2282 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2283 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2285 win_enable &= ~(1 << i);
2286 win_protect |= 3 << (2 * i);
2289 writel(win_enable, base + WINDOW_BAR_ENABLE);
2290 msp->win_protect = win_protect;
2293 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2296 * Check whether we have a 14-bit coal limit field in bits
2297 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2298 * SDMA config register.
2300 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2301 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2302 msp->extended_rx_coal_limit = 1;
2304 msp->extended_rx_coal_limit = 0;
2307 * Check whether the TX rate control registers are in the
2308 * old or the new place.
2310 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2311 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2312 msp->tx_bw_control_moved = 1;
2314 msp->tx_bw_control_moved = 0;
2317 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2319 static int mv643xx_eth_version_printed = 0;
2320 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2321 struct mv643xx_eth_shared_private *msp;
2322 struct resource *res;
2325 if (!mv643xx_eth_version_printed++)
2326 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2327 "driver version %s\n", mv643xx_eth_driver_version);
2330 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2335 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2338 memset(msp, 0, sizeof(*msp));
2340 msp->base = ioremap(res->start, res->end - res->start + 1);
2341 if (msp->base == NULL)
2345 if (pd != NULL && pd->shared_smi != NULL)
2346 msp->smi = platform_get_drvdata(pd->shared_smi);
2348 mutex_init(&msp->phy_lock);
2350 msp->err_interrupt = NO_IRQ;
2351 init_waitqueue_head(&msp->smi_busy_wait);
2354 * Check whether the error interrupt is hooked up.
2356 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2360 err = request_irq(res->start, mv643xx_eth_err_irq,
2361 IRQF_SHARED, "mv643xx_eth", msp);
2363 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2364 msp->err_interrupt = res->start;
2369 * (Re-)program MBUS remapping windows if we are asked to.
2371 if (pd != NULL && pd->dram != NULL)
2372 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2375 * Detect hardware parameters.
2377 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2378 infer_hw_params(msp);
2380 platform_set_drvdata(pdev, msp);
2390 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2392 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2394 if (msp->err_interrupt != NO_IRQ)
2395 free_irq(msp->err_interrupt, msp);
2402 static struct platform_driver mv643xx_eth_shared_driver = {
2403 .probe = mv643xx_eth_shared_probe,
2404 .remove = mv643xx_eth_shared_remove,
2406 .name = MV643XX_ETH_SHARED_NAME,
2407 .owner = THIS_MODULE,
2411 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2413 int addr_shift = 5 * mp->port_num;
2416 data = rdl(mp, PHY_ADDR);
2417 data &= ~(0x1f << addr_shift);
2418 data |= (phy_addr & 0x1f) << addr_shift;
2419 wrl(mp, PHY_ADDR, data);
2422 static int phy_addr_get(struct mv643xx_eth_private *mp)
2426 data = rdl(mp, PHY_ADDR);
2428 return (data >> (5 * mp->port_num)) & 0x1f;
2431 static void set_params(struct mv643xx_eth_private *mp,
2432 struct mv643xx_eth_platform_data *pd)
2434 struct net_device *dev = mp->dev;
2436 if (is_valid_ether_addr(pd->mac_addr))
2437 memcpy(dev->dev_addr, pd->mac_addr, 6);
2439 uc_addr_get(mp, dev->dev_addr);
2441 if (pd->phy_addr == MV643XX_ETH_PHY_NONE) {
2444 if (pd->phy_addr != MV643XX_ETH_PHY_ADDR_DEFAULT) {
2445 mp->phy_addr = pd->phy_addr & 0x3f;
2446 phy_addr_set(mp, mp->phy_addr);
2448 mp->phy_addr = phy_addr_get(mp);
2452 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2453 if (pd->rx_queue_size)
2454 mp->default_rx_ring_size = pd->rx_queue_size;
2455 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2456 mp->rx_desc_sram_size = pd->rx_sram_size;
2458 mp->rxq_count = pd->rx_queue_count ? : 1;
2460 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2461 if (pd->tx_queue_size)
2462 mp->default_tx_ring_size = pd->tx_queue_size;
2463 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2464 mp->tx_desc_sram_size = pd->tx_sram_size;
2466 mp->txq_count = pd->tx_queue_count ? : 1;
2469 static int phy_detect(struct mv643xx_eth_private *mp)
2474 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2478 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2481 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2485 if (((data ^ data2) & BMCR_ANENABLE) == 0)
2488 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
2493 static int phy_init(struct mv643xx_eth_private *mp,
2494 struct mv643xx_eth_platform_data *pd)
2496 struct ethtool_cmd cmd;
2499 err = phy_detect(mp);
2501 dev_printk(KERN_INFO, &mp->dev->dev,
2502 "no PHY detected at addr %d\n", mp->phy_addr);
2507 mp->mii.phy_id = mp->phy_addr;
2508 mp->mii.phy_id_mask = 0x3f;
2509 mp->mii.reg_num_mask = 0x1f;
2510 mp->mii.dev = mp->dev;
2511 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2512 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2514 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2516 memset(&cmd, 0, sizeof(cmd));
2518 cmd.port = PORT_MII;
2519 cmd.transceiver = XCVR_INTERNAL;
2520 cmd.phy_address = mp->phy_addr;
2521 if (pd->speed == 0) {
2522 cmd.autoneg = AUTONEG_ENABLE;
2523 cmd.speed = SPEED_100;
2524 cmd.advertising = ADVERTISED_10baseT_Half |
2525 ADVERTISED_10baseT_Full |
2526 ADVERTISED_100baseT_Half |
2527 ADVERTISED_100baseT_Full;
2528 if (mp->mii.supports_gmii)
2529 cmd.advertising |= ADVERTISED_1000baseT_Full;
2531 cmd.autoneg = AUTONEG_DISABLE;
2532 cmd.speed = pd->speed;
2533 cmd.duplex = pd->duplex;
2536 mv643xx_eth_set_settings(mp->dev, &cmd);
2541 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2545 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2546 if (pscr & SERIAL_PORT_ENABLE) {
2547 pscr &= ~SERIAL_PORT_ENABLE;
2548 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2551 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2552 if (mp->phy_addr == -1) {
2553 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2554 if (speed == SPEED_1000)
2555 pscr |= SET_GMII_SPEED_TO_1000;
2556 else if (speed == SPEED_100)
2557 pscr |= SET_MII_SPEED_TO_100;
2559 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2561 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2562 if (duplex == DUPLEX_FULL)
2563 pscr |= SET_FULL_DUPLEX_MODE;
2566 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2569 static int mv643xx_eth_probe(struct platform_device *pdev)
2571 struct mv643xx_eth_platform_data *pd;
2572 struct mv643xx_eth_private *mp;
2573 struct net_device *dev;
2574 struct resource *res;
2575 DECLARE_MAC_BUF(mac);
2578 pd = pdev->dev.platform_data;
2580 dev_printk(KERN_ERR, &pdev->dev,
2581 "no mv643xx_eth_platform_data\n");
2585 if (pd->shared == NULL) {
2586 dev_printk(KERN_ERR, &pdev->dev,
2587 "no mv643xx_eth_platform_data->shared\n");
2591 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2595 mp = netdev_priv(dev);
2596 platform_set_drvdata(pdev, mp);
2598 mp->shared = platform_get_drvdata(pd->shared);
2599 mp->port_num = pd->port_number;
2604 dev->real_num_tx_queues = mp->txq_count;
2606 mib_counters_clear(mp);
2607 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2609 if (mp->phy_addr != -1) {
2610 err = phy_init(mp, pd);
2614 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2616 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2618 init_pscr(mp, pd->speed, pd->duplex);
2620 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2622 init_timer(&mp->rx_oom);
2623 mp->rx_oom.data = (unsigned long)mp;
2624 mp->rx_oom.function = oom_timer_wrapper;
2627 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2629 dev->irq = res->start;
2631 dev->get_stats = mv643xx_eth_get_stats;
2632 dev->hard_start_xmit = mv643xx_eth_xmit;
2633 dev->open = mv643xx_eth_open;
2634 dev->stop = mv643xx_eth_stop;
2635 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2636 dev->set_mac_address = mv643xx_eth_set_mac_address;
2637 dev->do_ioctl = mv643xx_eth_ioctl;
2638 dev->change_mtu = mv643xx_eth_change_mtu;
2639 dev->tx_timeout = mv643xx_eth_tx_timeout;
2640 #ifdef CONFIG_NET_POLL_CONTROLLER
2641 dev->poll_controller = mv643xx_eth_netpoll;
2643 dev->watchdog_timeo = 2 * HZ;
2646 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2647 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2649 SET_NETDEV_DEV(dev, &pdev->dev);
2651 if (mp->shared->win_protect)
2652 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2654 err = register_netdev(dev);
2658 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2659 mp->port_num, print_mac(mac, dev->dev_addr));
2661 if (mp->tx_desc_sram_size > 0)
2662 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2672 static int mv643xx_eth_remove(struct platform_device *pdev)
2674 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2676 unregister_netdev(mp->dev);
2677 flush_scheduled_work();
2678 free_netdev(mp->dev);
2680 platform_set_drvdata(pdev, NULL);
2685 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2687 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2689 /* Mask all interrupts on ethernet port */
2690 wrl(mp, INT_MASK(mp->port_num), 0);
2691 rdl(mp, INT_MASK(mp->port_num));
2693 if (netif_running(mp->dev))
2697 static struct platform_driver mv643xx_eth_driver = {
2698 .probe = mv643xx_eth_probe,
2699 .remove = mv643xx_eth_remove,
2700 .shutdown = mv643xx_eth_shutdown,
2702 .name = MV643XX_ETH_NAME,
2703 .owner = THIS_MODULE,
2707 static int __init mv643xx_eth_init_module(void)
2711 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2713 rc = platform_driver_register(&mv643xx_eth_driver);
2715 platform_driver_unregister(&mv643xx_eth_shared_driver);
2720 module_init(mv643xx_eth_init_module);
2722 static void __exit mv643xx_eth_cleanup_module(void)
2724 platform_driver_unregister(&mv643xx_eth_driver);
2725 platform_driver_unregister(&mv643xx_eth_shared_driver);
2727 module_exit(mv643xx_eth_cleanup_module);
2729 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2730 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2731 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2732 MODULE_LICENSE("GPL");
2733 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2734 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);