2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.3";
62 * Registers shared between all ports.
64 #define PHY_ADDR 0x0000
65 #define SMI_REG 0x0004
66 #define SMI_BUSY 0x10000000
67 #define SMI_READ_VALID 0x08000000
68 #define SMI_OPCODE_READ 0x04000000
69 #define SMI_OPCODE_WRITE 0x00000000
70 #define ERR_INT_CAUSE 0x0080
71 #define ERR_INT_SMI_DONE 0x00000010
72 #define ERR_INT_MASK 0x0084
73 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
74 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
75 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
76 #define WINDOW_BAR_ENABLE 0x0290
77 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
82 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
83 #define UNICAST_PROMISCUOUS_MODE 0x00000001
84 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
85 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
86 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
87 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
88 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
89 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
90 #define TX_FIFO_EMPTY 0x00000400
91 #define TX_IN_PROGRESS 0x00000080
92 #define PORT_SPEED_MASK 0x00000030
93 #define PORT_SPEED_1000 0x00000010
94 #define PORT_SPEED_100 0x00000020
95 #define PORT_SPEED_10 0x00000000
96 #define FLOW_CONTROL_ENABLED 0x00000008
97 #define FULL_DUPLEX 0x00000004
98 #define LINK_UP 0x00000002
99 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
100 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
101 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
102 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
103 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
104 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
105 #define INT_TX_END 0x07f80000
106 #define INT_RX 0x000003fc
107 #define INT_EXT 0x00000002
108 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
109 #define INT_EXT_LINK_PHY 0x00110000
110 #define INT_EXT_TX 0x000000ff
111 #define INT_MASK(p) (0x0468 + ((p) << 10))
112 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
113 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
114 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
115 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
116 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
117 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
118 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
119 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
120 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
121 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
122 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
123 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
124 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
125 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
126 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
127 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
131 * SDMA configuration register.
133 #define RX_BURST_SIZE_16_64BIT (4 << 1)
134 #define BLM_RX_NO_SWAP (1 << 4)
135 #define BLM_TX_NO_SWAP (1 << 5)
136 #define TX_BURST_SIZE_16_64BIT (4 << 22)
138 #if defined(__BIG_ENDIAN)
139 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
140 RX_BURST_SIZE_16_64BIT | \
141 TX_BURST_SIZE_16_64BIT
142 #elif defined(__LITTLE_ENDIAN)
143 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
144 RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT
149 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
154 * Port serial control register.
156 #define SET_MII_SPEED_TO_100 (1 << 24)
157 #define SET_GMII_SPEED_TO_1000 (1 << 23)
158 #define SET_FULL_DUPLEX_MODE (1 << 21)
159 #define MAX_RX_PACKET_9700BYTE (5 << 17)
160 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
161 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
162 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
163 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
164 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
165 #define FORCE_LINK_PASS (1 << 1)
166 #define SERIAL_PORT_ENABLE (1 << 0)
168 #define DEFAULT_RX_QUEUE_SIZE 400
169 #define DEFAULT_TX_QUEUE_SIZE 800
175 #if defined(__BIG_ENDIAN)
177 u16 byte_cnt; /* Descriptor buffer byte count */
178 u16 buf_size; /* Buffer size */
179 u32 cmd_sts; /* Descriptor command status */
180 u32 next_desc_ptr; /* Next descriptor pointer */
181 u32 buf_ptr; /* Descriptor buffer pointer */
185 u16 byte_cnt; /* buffer byte count */
186 u16 l4i_chk; /* CPU provided TCP checksum */
187 u32 cmd_sts; /* Command/status field */
188 u32 next_desc_ptr; /* Pointer to next descriptor */
189 u32 buf_ptr; /* pointer to buffer for this descriptor*/
191 #elif defined(__LITTLE_ENDIAN)
193 u32 cmd_sts; /* Descriptor command status */
194 u16 buf_size; /* Buffer size */
195 u16 byte_cnt; /* Descriptor buffer byte count */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197 u32 next_desc_ptr; /* Next descriptor pointer */
201 u32 cmd_sts; /* Command/status field */
202 u16 l4i_chk; /* CPU provided TCP checksum */
203 u16 byte_cnt; /* buffer byte count */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205 u32 next_desc_ptr; /* Pointer to next descriptor */
208 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
211 /* RX & TX descriptor command */
212 #define BUFFER_OWNED_BY_DMA 0x80000000
214 /* RX & TX descriptor status */
215 #define ERROR_SUMMARY 0x00000001
217 /* RX descriptor status */
218 #define LAYER_4_CHECKSUM_OK 0x40000000
219 #define RX_ENABLE_INTERRUPT 0x20000000
220 #define RX_FIRST_DESC 0x08000000
221 #define RX_LAST_DESC 0x04000000
223 /* TX descriptor command */
224 #define TX_ENABLE_INTERRUPT 0x00800000
225 #define GEN_CRC 0x00400000
226 #define TX_FIRST_DESC 0x00200000
227 #define TX_LAST_DESC 0x00100000
228 #define ZERO_PADDING 0x00080000
229 #define GEN_IP_V4_CHECKSUM 0x00040000
230 #define GEN_TCP_UDP_CHECKSUM 0x00020000
231 #define UDP_FRAME 0x00010000
232 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
233 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
235 #define TX_IHL_SHIFT 11
238 /* global *******************************************************************/
239 struct mv643xx_eth_shared_private {
241 * Ethernet controller base address.
246 * Points at the right SMI instance to use.
248 struct mv643xx_eth_shared_private *smi;
251 * Protects access to SMI_REG, which is shared between ports.
253 struct mutex phy_lock;
256 * If we have access to the error interrupt pin (which is
257 * somewhat misnamed as it not only reflects internal errors
258 * but also reflects SMI completion), use that to wait for
259 * SMI access completion instead of polling the SMI busy bit.
262 wait_queue_head_t smi_busy_wait;
265 * Per-port MBUS window access register value.
270 * Hardware-specific parameters.
273 int extended_rx_coal_limit;
274 int tx_bw_control_moved;
278 /* per-port *****************************************************************/
279 struct mib_counters {
280 u64 good_octets_received;
281 u32 bad_octets_received;
282 u32 internal_mac_transmit_err;
283 u32 good_frames_received;
284 u32 bad_frames_received;
285 u32 broadcast_frames_received;
286 u32 multicast_frames_received;
287 u32 frames_64_octets;
288 u32 frames_65_to_127_octets;
289 u32 frames_128_to_255_octets;
290 u32 frames_256_to_511_octets;
291 u32 frames_512_to_1023_octets;
292 u32 frames_1024_to_max_octets;
293 u64 good_octets_sent;
294 u32 good_frames_sent;
295 u32 excessive_collision;
296 u32 multicast_frames_sent;
297 u32 broadcast_frames_sent;
298 u32 unrec_mac_control_received;
300 u32 good_fc_received;
302 u32 undersize_received;
303 u32 fragments_received;
304 u32 oversize_received;
306 u32 mac_receive_error;
321 struct rx_desc *rx_desc_area;
322 dma_addr_t rx_desc_dma;
323 int rx_desc_area_size;
324 struct sk_buff **rx_skb;
336 struct tx_desc *tx_desc_area;
337 dma_addr_t tx_desc_dma;
338 int tx_desc_area_size;
339 struct sk_buff **tx_skb;
342 struct mv643xx_eth_private {
343 struct mv643xx_eth_shared_private *shared;
346 struct net_device *dev;
352 struct mib_counters mib_counters;
353 struct work_struct tx_timeout_task;
354 struct mii_if_info mii;
356 struct napi_struct napi;
367 int default_rx_ring_size;
368 unsigned long rx_desc_sram_addr;
369 int rx_desc_sram_size;
371 struct timer_list rx_oom;
372 struct rx_queue rxq[8];
377 int default_tx_ring_size;
378 unsigned long tx_desc_sram_addr;
379 int tx_desc_sram_size;
381 struct tx_queue txq[8];
385 /* port register accessors **************************************************/
386 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
388 return readl(mp->shared->base + offset);
391 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
393 writel(data, mp->shared->base + offset);
397 /* rxq/txq helper functions *************************************************/
398 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
400 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
403 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
405 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
408 static void rxq_enable(struct rx_queue *rxq)
410 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
411 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
414 static void rxq_disable(struct rx_queue *rxq)
416 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
417 u8 mask = 1 << rxq->index;
419 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
420 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
424 static void txq_reset_hw_ptr(struct tx_queue *txq)
426 struct mv643xx_eth_private *mp = txq_to_mp(txq);
427 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
430 addr = (u32)txq->tx_desc_dma;
431 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
435 static void txq_enable(struct tx_queue *txq)
437 struct mv643xx_eth_private *mp = txq_to_mp(txq);
438 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
441 static void txq_disable(struct tx_queue *txq)
443 struct mv643xx_eth_private *mp = txq_to_mp(txq);
444 u8 mask = 1 << txq->index;
446 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
447 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
451 static void txq_maybe_wake(struct tx_queue *txq)
453 struct mv643xx_eth_private *mp = txq_to_mp(txq);
454 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
456 spin_lock(&mp->lock);
457 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
458 netif_tx_wake_queue(nq);
459 spin_unlock(&mp->lock);
463 /* rx napi ******************************************************************/
464 static int rxq_process(struct rx_queue *rxq, int budget)
466 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
467 struct net_device_stats *stats = &mp->dev->stats;
471 while (rx < budget && rxq->rx_desc_count) {
472 struct rx_desc *rx_desc;
473 unsigned int cmd_sts;
476 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
478 cmd_sts = rx_desc->cmd_sts;
479 if (cmd_sts & BUFFER_OWNED_BY_DMA)
483 skb = rxq->rx_skb[rxq->rx_curr_desc];
484 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
487 if (rxq->rx_curr_desc == rxq->rx_ring_size)
488 rxq->rx_curr_desc = 0;
490 dma_unmap_single(NULL, rx_desc->buf_ptr,
491 rx_desc->buf_size, DMA_FROM_DEVICE);
492 rxq->rx_desc_count--;
495 mp->work_rx_refill |= 1 << rxq->index;
500 * Note that the descriptor byte count includes 2 dummy
501 * bytes automatically inserted by the hardware at the
502 * start of the packet (which we don't count), and a 4
503 * byte CRC at the end of the packet (which we do count).
506 stats->rx_bytes += rx_desc->byte_cnt - 2;
509 * In case we received a packet without first / last bits
510 * on, or the error summary bit is set, the packet needs
513 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
514 (RX_FIRST_DESC | RX_LAST_DESC))
515 || (cmd_sts & ERROR_SUMMARY)) {
518 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
519 (RX_FIRST_DESC | RX_LAST_DESC)) {
521 dev_printk(KERN_ERR, &mp->dev->dev,
522 "received packet spanning "
523 "multiple descriptors\n");
526 if (cmd_sts & ERROR_SUMMARY)
532 * The -4 is for the CRC in the trailer of the
535 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
537 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
538 skb->ip_summed = CHECKSUM_UNNECESSARY;
540 (cmd_sts & 0x0007fff8) >> 3);
542 skb->protocol = eth_type_trans(skb, mp->dev);
543 netif_receive_skb(skb);
546 mp->dev->last_rx = jiffies;
550 mp->work_rx &= ~(1 << rxq->index);
555 static int rxq_refill(struct rx_queue *rxq, int budget)
557 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
562 * Reserve 2+14 bytes for an ethernet header (the hardware
563 * automatically prepends 2 bytes of dummy data to each
564 * received packet), 16 bytes for up to four VLAN tags, and
565 * 4 bytes for the trailing FCS -- 36 bytes total.
567 skb_size = rxq_to_mp(rxq)->dev->mtu + 36;
570 * Make sure that the skb size is a multiple of 8 bytes, as
571 * the lower three bits of the receive descriptor's buffer
572 * size field are ignored by the hardware.
574 skb_size = (skb_size + 7) & ~7;
577 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
582 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
584 mp->work_rx_oom |= 1 << rxq->index;
588 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
590 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
593 rxq->rx_desc_count++;
595 rx = rxq->rx_used_desc++;
596 if (rxq->rx_used_desc == rxq->rx_ring_size)
597 rxq->rx_used_desc = 0;
599 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
600 skb_size, DMA_FROM_DEVICE);
601 rxq->rx_desc_area[rx].buf_size = skb_size;
602 rxq->rx_skb[rx] = skb;
604 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
609 * The hardware automatically prepends 2 bytes of
610 * dummy data to each received packet, so that the
611 * IP header ends up 16-byte aligned.
616 if (refilled < budget)
617 mp->work_rx_refill &= ~(1 << rxq->index);
624 /* tx ***********************************************************************/
625 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
629 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
630 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
631 if (fragp->size <= 8 && fragp->page_offset & 7)
638 static int txq_alloc_desc_index(struct tx_queue *txq)
642 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
644 tx_desc_curr = txq->tx_curr_desc++;
645 if (txq->tx_curr_desc == txq->tx_ring_size)
646 txq->tx_curr_desc = 0;
648 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
653 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
655 int nr_frags = skb_shinfo(skb)->nr_frags;
658 for (frag = 0; frag < nr_frags; frag++) {
659 skb_frag_t *this_frag;
661 struct tx_desc *desc;
663 this_frag = &skb_shinfo(skb)->frags[frag];
664 tx_index = txq_alloc_desc_index(txq);
665 desc = &txq->tx_desc_area[tx_index];
668 * The last fragment will generate an interrupt
669 * which will free the skb on TX completion.
671 if (frag == nr_frags - 1) {
672 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
673 ZERO_PADDING | TX_LAST_DESC |
675 txq->tx_skb[tx_index] = skb;
677 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
678 txq->tx_skb[tx_index] = NULL;
682 desc->byte_cnt = this_frag->size;
683 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
684 this_frag->page_offset,
690 static inline __be16 sum16_as_be(__sum16 sum)
692 return (__force __be16)sum;
695 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
697 struct mv643xx_eth_private *mp = txq_to_mp(txq);
698 int nr_frags = skb_shinfo(skb)->nr_frags;
700 struct tx_desc *desc;
704 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
706 tx_index = txq_alloc_desc_index(txq);
707 desc = &txq->tx_desc_area[tx_index];
710 txq_submit_frag_skb(txq, skb);
712 length = skb_headlen(skb);
713 txq->tx_skb[tx_index] = NULL;
715 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
717 txq->tx_skb[tx_index] = skb;
720 desc->byte_cnt = length;
721 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
723 if (skb->ip_summed == CHECKSUM_PARTIAL) {
726 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
727 skb->protocol != htons(ETH_P_8021Q));
729 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
731 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
733 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
734 switch (mac_hdr_len - ETH_HLEN) {
738 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
741 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
744 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
745 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
749 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
750 "mac header length is %d?!\n", mac_hdr_len);
754 switch (ip_hdr(skb)->protocol) {
756 cmd_sts |= UDP_FRAME;
757 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
760 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
766 /* Errata BTS #50, IHL must be 5 if no HW checksum */
767 cmd_sts |= 5 << TX_IHL_SHIFT;
771 /* ensure all other descriptors are written before first cmd_sts */
773 desc->cmd_sts = cmd_sts;
775 /* clear TX_END status */
776 mp->work_tx_end &= ~(1 << txq->index);
778 /* ensure all descriptors are written before poking hardware */
782 txq->tx_desc_count += nr_frags + 1;
785 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
787 struct mv643xx_eth_private *mp = netdev_priv(dev);
788 struct net_device_stats *stats = &dev->stats;
790 struct tx_queue *txq;
791 struct netdev_queue *nq;
794 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
796 dev_printk(KERN_DEBUG, &dev->dev,
797 "failed to linearize skb with tiny "
798 "unaligned fragment\n");
799 return NETDEV_TX_BUSY;
802 queue = skb_get_queue_mapping(skb);
803 txq = mp->txq + queue;
804 nq = netdev_get_tx_queue(dev, queue);
806 spin_lock(&mp->lock);
808 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
809 spin_unlock(&mp->lock);
811 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
816 txq_submit_skb(txq, skb);
817 stats->tx_bytes += skb->len;
819 dev->trans_start = jiffies;
821 entries_left = txq->tx_ring_size - txq->tx_desc_count;
822 if (entries_left < MAX_SKB_FRAGS + 1)
823 netif_tx_stop_queue(nq);
825 spin_unlock(&mp->lock);
831 /* tx napi ******************************************************************/
832 static void txq_kick(struct tx_queue *txq)
834 struct mv643xx_eth_private *mp = txq_to_mp(txq);
838 spin_lock(&mp->lock);
840 if (rdl(mp, TXQ_COMMAND(mp->port_num)) & (1 << txq->index))
843 hw_desc_ptr = rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index));
844 expected_ptr = (u32)txq->tx_desc_dma +
845 txq->tx_curr_desc * sizeof(struct tx_desc);
847 if (hw_desc_ptr != expected_ptr)
851 spin_unlock(&mp->lock);
853 mp->work_tx_end &= ~(1 << txq->index);
856 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
858 struct mv643xx_eth_private *mp = txq_to_mp(txq);
861 spin_lock(&mp->lock);
864 while (reclaimed < budget && txq->tx_desc_count > 0) {
866 struct tx_desc *desc;
872 tx_index = txq->tx_used_desc;
873 desc = &txq->tx_desc_area[tx_index];
874 cmd_sts = desc->cmd_sts;
876 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
879 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
882 txq->tx_used_desc = tx_index + 1;
883 if (txq->tx_used_desc == txq->tx_ring_size)
884 txq->tx_used_desc = 0;
887 txq->tx_desc_count--;
889 addr = desc->buf_ptr;
890 count = desc->byte_cnt;
891 skb = txq->tx_skb[tx_index];
892 txq->tx_skb[tx_index] = NULL;
894 if (cmd_sts & ERROR_SUMMARY) {
895 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
896 mp->dev->stats.tx_errors++;
900 * Drop mp->lock while we free the skb.
902 spin_unlock(&mp->lock);
904 if (cmd_sts & TX_FIRST_DESC)
905 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
907 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
912 spin_lock(&mp->lock);
915 if (reclaimed < budget)
916 mp->work_tx &= ~(1 << txq->index);
918 spin_unlock(&mp->lock);
924 /* tx rate control **********************************************************/
926 * Set total maximum TX rate (shared by all TX queues for this port)
927 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
929 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
935 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
936 if (token_rate > 1023)
939 mtu = (mp->dev->mtu + 255) >> 8;
943 bucket_size = (burst + 255) >> 8;
944 if (bucket_size > 65535)
947 if (mp->shared->tx_bw_control_moved) {
948 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
949 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
950 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
952 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
953 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
954 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
958 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
960 struct mv643xx_eth_private *mp = txq_to_mp(txq);
964 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
965 if (token_rate > 1023)
968 bucket_size = (burst + 255) >> 8;
969 if (bucket_size > 65535)
972 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
973 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
974 (bucket_size << 10) | token_rate);
977 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
979 struct mv643xx_eth_private *mp = txq_to_mp(txq);
984 * Turn on fixed priority mode.
986 if (mp->shared->tx_bw_control_moved)
987 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
989 off = TXQ_FIX_PRIO_CONF(mp->port_num);
992 val |= 1 << txq->index;
996 static void txq_set_wrr(struct tx_queue *txq, int weight)
998 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1003 * Turn off fixed priority mode.
1005 if (mp->shared->tx_bw_control_moved)
1006 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
1008 off = TXQ_FIX_PRIO_CONF(mp->port_num);
1011 val &= ~(1 << txq->index);
1015 * Configure WRR weight for this queue.
1017 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
1020 val = (val & ~0xff) | (weight & 0xff);
1025 /* mii management interface *************************************************/
1026 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1028 struct mv643xx_eth_shared_private *msp = dev_id;
1030 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1031 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1032 wake_up(&msp->smi_busy_wait);
1039 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1041 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1044 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1046 if (msp->err_interrupt == NO_IRQ) {
1049 for (i = 0; !smi_is_done(msp); i++) {
1058 if (!wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1059 msecs_to_jiffies(100)))
1065 static int smi_reg_read(struct mv643xx_eth_private *mp,
1066 unsigned int addr, unsigned int reg)
1068 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
1069 void __iomem *smi_reg = msp->base + SMI_REG;
1072 mutex_lock(&msp->phy_lock);
1074 if (smi_wait_ready(msp)) {
1075 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1080 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1082 if (smi_wait_ready(msp)) {
1083 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1088 ret = readl(smi_reg);
1089 if (!(ret & SMI_READ_VALID)) {
1090 printk("%s: SMI bus read not valid\n", mp->dev->name);
1098 mutex_unlock(&msp->phy_lock);
1103 static int smi_reg_write(struct mv643xx_eth_private *mp, unsigned int addr,
1104 unsigned int reg, unsigned int value)
1106 struct mv643xx_eth_shared_private *msp = mp->shared->smi;
1107 void __iomem *smi_reg = msp->base + SMI_REG;
1109 mutex_lock(&msp->phy_lock);
1111 if (smi_wait_ready(msp)) {
1112 printk("%s: SMI bus busy timeout\n", mp->dev->name);
1113 mutex_unlock(&msp->phy_lock);
1117 writel(SMI_OPCODE_WRITE | (reg << 21) |
1118 (addr << 16) | (value & 0xffff), smi_reg);
1120 mutex_unlock(&msp->phy_lock);
1126 /* mib counters *************************************************************/
1127 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1129 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1132 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1136 for (i = 0; i < 0x80; i += 4)
1140 static void mib_counters_update(struct mv643xx_eth_private *mp)
1142 struct mib_counters *p = &mp->mib_counters;
1144 p->good_octets_received += mib_read(mp, 0x00);
1145 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1146 p->bad_octets_received += mib_read(mp, 0x08);
1147 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1148 p->good_frames_received += mib_read(mp, 0x10);
1149 p->bad_frames_received += mib_read(mp, 0x14);
1150 p->broadcast_frames_received += mib_read(mp, 0x18);
1151 p->multicast_frames_received += mib_read(mp, 0x1c);
1152 p->frames_64_octets += mib_read(mp, 0x20);
1153 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1154 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1155 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1156 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1157 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1158 p->good_octets_sent += mib_read(mp, 0x38);
1159 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1160 p->good_frames_sent += mib_read(mp, 0x40);
1161 p->excessive_collision += mib_read(mp, 0x44);
1162 p->multicast_frames_sent += mib_read(mp, 0x48);
1163 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1164 p->unrec_mac_control_received += mib_read(mp, 0x50);
1165 p->fc_sent += mib_read(mp, 0x54);
1166 p->good_fc_received += mib_read(mp, 0x58);
1167 p->bad_fc_received += mib_read(mp, 0x5c);
1168 p->undersize_received += mib_read(mp, 0x60);
1169 p->fragments_received += mib_read(mp, 0x64);
1170 p->oversize_received += mib_read(mp, 0x68);
1171 p->jabber_received += mib_read(mp, 0x6c);
1172 p->mac_receive_error += mib_read(mp, 0x70);
1173 p->bad_crc_event += mib_read(mp, 0x74);
1174 p->collision += mib_read(mp, 0x78);
1175 p->late_collision += mib_read(mp, 0x7c);
1179 /* ethtool ******************************************************************/
1180 struct mv643xx_eth_stats {
1181 char stat_string[ETH_GSTRING_LEN];
1188 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1189 offsetof(struct net_device, stats.m), -1 }
1191 #define MIBSTAT(m) \
1192 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1193 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1195 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1204 MIBSTAT(good_octets_received),
1205 MIBSTAT(bad_octets_received),
1206 MIBSTAT(internal_mac_transmit_err),
1207 MIBSTAT(good_frames_received),
1208 MIBSTAT(bad_frames_received),
1209 MIBSTAT(broadcast_frames_received),
1210 MIBSTAT(multicast_frames_received),
1211 MIBSTAT(frames_64_octets),
1212 MIBSTAT(frames_65_to_127_octets),
1213 MIBSTAT(frames_128_to_255_octets),
1214 MIBSTAT(frames_256_to_511_octets),
1215 MIBSTAT(frames_512_to_1023_octets),
1216 MIBSTAT(frames_1024_to_max_octets),
1217 MIBSTAT(good_octets_sent),
1218 MIBSTAT(good_frames_sent),
1219 MIBSTAT(excessive_collision),
1220 MIBSTAT(multicast_frames_sent),
1221 MIBSTAT(broadcast_frames_sent),
1222 MIBSTAT(unrec_mac_control_received),
1224 MIBSTAT(good_fc_received),
1225 MIBSTAT(bad_fc_received),
1226 MIBSTAT(undersize_received),
1227 MIBSTAT(fragments_received),
1228 MIBSTAT(oversize_received),
1229 MIBSTAT(jabber_received),
1230 MIBSTAT(mac_receive_error),
1231 MIBSTAT(bad_crc_event),
1233 MIBSTAT(late_collision),
1236 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1238 struct mv643xx_eth_private *mp = netdev_priv(dev);
1241 err = mii_ethtool_gset(&mp->mii, cmd);
1244 * The MAC does not support 1000baseT_Half.
1246 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1247 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1252 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1254 struct mv643xx_eth_private *mp = netdev_priv(dev);
1257 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1259 cmd->supported = SUPPORTED_MII;
1260 cmd->advertising = ADVERTISED_MII;
1261 switch (port_status & PORT_SPEED_MASK) {
1263 cmd->speed = SPEED_10;
1265 case PORT_SPEED_100:
1266 cmd->speed = SPEED_100;
1268 case PORT_SPEED_1000:
1269 cmd->speed = SPEED_1000;
1275 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1276 cmd->port = PORT_MII;
1277 cmd->phy_address = 0;
1278 cmd->transceiver = XCVR_INTERNAL;
1279 cmd->autoneg = AUTONEG_DISABLE;
1286 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1288 struct mv643xx_eth_private *mp = netdev_priv(dev);
1291 * The MAC does not support 1000baseT_Half.
1293 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1295 return mii_ethtool_sset(&mp->mii, cmd);
1298 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1303 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1304 struct ethtool_drvinfo *drvinfo)
1306 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1307 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1308 strncpy(drvinfo->fw_version, "N/A", 32);
1309 strncpy(drvinfo->bus_info, "platform", 32);
1310 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1313 static int mv643xx_eth_nway_reset(struct net_device *dev)
1315 struct mv643xx_eth_private *mp = netdev_priv(dev);
1317 return mii_nway_restart(&mp->mii);
1320 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1325 static u32 mv643xx_eth_get_link(struct net_device *dev)
1327 struct mv643xx_eth_private *mp = netdev_priv(dev);
1329 return mii_link_ok(&mp->mii);
1332 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1337 static void mv643xx_eth_get_strings(struct net_device *dev,
1338 uint32_t stringset, uint8_t *data)
1342 if (stringset == ETH_SS_STATS) {
1343 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1344 memcpy(data + i * ETH_GSTRING_LEN,
1345 mv643xx_eth_stats[i].stat_string,
1351 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1352 struct ethtool_stats *stats,
1355 struct mv643xx_eth_private *mp = netdev_priv(dev);
1358 mib_counters_update(mp);
1360 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1361 const struct mv643xx_eth_stats *stat;
1364 stat = mv643xx_eth_stats + i;
1366 if (stat->netdev_off >= 0)
1367 p = ((void *)mp->dev) + stat->netdev_off;
1369 p = ((void *)mp) + stat->mp_off;
1371 data[i] = (stat->sizeof_stat == 8) ?
1372 *(uint64_t *)p : *(uint32_t *)p;
1376 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1378 if (sset == ETH_SS_STATS)
1379 return ARRAY_SIZE(mv643xx_eth_stats);
1384 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1385 .get_settings = mv643xx_eth_get_settings,
1386 .set_settings = mv643xx_eth_set_settings,
1387 .get_drvinfo = mv643xx_eth_get_drvinfo,
1388 .nway_reset = mv643xx_eth_nway_reset,
1389 .get_link = mv643xx_eth_get_link,
1390 .set_sg = ethtool_op_set_sg,
1391 .get_strings = mv643xx_eth_get_strings,
1392 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1393 .get_sset_count = mv643xx_eth_get_sset_count,
1396 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1397 .get_settings = mv643xx_eth_get_settings_phyless,
1398 .set_settings = mv643xx_eth_set_settings_phyless,
1399 .get_drvinfo = mv643xx_eth_get_drvinfo,
1400 .nway_reset = mv643xx_eth_nway_reset_phyless,
1401 .get_link = mv643xx_eth_get_link_phyless,
1402 .set_sg = ethtool_op_set_sg,
1403 .get_strings = mv643xx_eth_get_strings,
1404 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1405 .get_sset_count = mv643xx_eth_get_sset_count,
1409 /* address handling *********************************************************/
1410 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1415 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1416 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1418 addr[0] = (mac_h >> 24) & 0xff;
1419 addr[1] = (mac_h >> 16) & 0xff;
1420 addr[2] = (mac_h >> 8) & 0xff;
1421 addr[3] = mac_h & 0xff;
1422 addr[4] = (mac_l >> 8) & 0xff;
1423 addr[5] = mac_l & 0xff;
1426 static void init_mac_tables(struct mv643xx_eth_private *mp)
1430 for (i = 0; i < 0x100; i += 4) {
1431 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1432 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1435 for (i = 0; i < 0x10; i += 4)
1436 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1439 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1440 int table, unsigned char entry)
1442 unsigned int table_reg;
1444 /* Set "accepts frame bit" at specified table entry */
1445 table_reg = rdl(mp, table + (entry & 0xfc));
1446 table_reg |= 0x01 << (8 * (entry & 3));
1447 wrl(mp, table + (entry & 0xfc), table_reg);
1450 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1456 mac_l = (addr[4] << 8) | addr[5];
1457 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1459 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1460 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1462 table = UNICAST_TABLE(mp->port_num);
1463 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1466 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1468 struct mv643xx_eth_private *mp = netdev_priv(dev);
1470 /* +2 is for the offset of the HW addr type */
1471 memcpy(dev->dev_addr, addr + 2, 6);
1473 init_mac_tables(mp);
1474 uc_addr_set(mp, dev->dev_addr);
1479 static int addr_crc(unsigned char *addr)
1484 for (i = 0; i < 6; i++) {
1487 crc = (crc ^ addr[i]) << 8;
1488 for (j = 7; j >= 0; j--) {
1489 if (crc & (0x100 << j))
1497 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1499 struct mv643xx_eth_private *mp = netdev_priv(dev);
1501 struct dev_addr_list *addr;
1504 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1505 if (dev->flags & IFF_PROMISC)
1506 port_config |= UNICAST_PROMISCUOUS_MODE;
1508 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1509 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1511 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1512 int port_num = mp->port_num;
1513 u32 accept = 0x01010101;
1515 for (i = 0; i < 0x100; i += 4) {
1516 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1517 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1522 for (i = 0; i < 0x100; i += 4) {
1523 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1524 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1527 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1528 u8 *a = addr->da_addr;
1531 if (addr->da_addrlen != 6)
1534 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1535 table = SPECIAL_MCAST_TABLE(mp->port_num);
1536 set_filter_table_entry(mp, table, a[5]);
1538 int crc = addr_crc(a);
1540 table = OTHER_MCAST_TABLE(mp->port_num);
1541 set_filter_table_entry(mp, table, crc);
1547 /* rx/tx queue initialisation ***********************************************/
1548 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1550 struct rx_queue *rxq = mp->rxq + index;
1551 struct rx_desc *rx_desc;
1557 rxq->rx_ring_size = mp->default_rx_ring_size;
1559 rxq->rx_desc_count = 0;
1560 rxq->rx_curr_desc = 0;
1561 rxq->rx_used_desc = 0;
1563 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1565 if (index == 0 && size <= mp->rx_desc_sram_size) {
1566 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1567 mp->rx_desc_sram_size);
1568 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1570 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1575 if (rxq->rx_desc_area == NULL) {
1576 dev_printk(KERN_ERR, &mp->dev->dev,
1577 "can't allocate rx ring (%d bytes)\n", size);
1580 memset(rxq->rx_desc_area, 0, size);
1582 rxq->rx_desc_area_size = size;
1583 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1585 if (rxq->rx_skb == NULL) {
1586 dev_printk(KERN_ERR, &mp->dev->dev,
1587 "can't allocate rx skb ring\n");
1591 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1592 for (i = 0; i < rxq->rx_ring_size; i++) {
1596 if (nexti == rxq->rx_ring_size)
1599 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1600 nexti * sizeof(struct rx_desc);
1607 if (index == 0 && size <= mp->rx_desc_sram_size)
1608 iounmap(rxq->rx_desc_area);
1610 dma_free_coherent(NULL, size,
1618 static void rxq_deinit(struct rx_queue *rxq)
1620 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1625 for (i = 0; i < rxq->rx_ring_size; i++) {
1626 if (rxq->rx_skb[i]) {
1627 dev_kfree_skb(rxq->rx_skb[i]);
1628 rxq->rx_desc_count--;
1632 if (rxq->rx_desc_count) {
1633 dev_printk(KERN_ERR, &mp->dev->dev,
1634 "error freeing rx ring -- %d skbs stuck\n",
1635 rxq->rx_desc_count);
1638 if (rxq->index == 0 &&
1639 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1640 iounmap(rxq->rx_desc_area);
1642 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1643 rxq->rx_desc_area, rxq->rx_desc_dma);
1648 static int txq_init(struct mv643xx_eth_private *mp, int index)
1650 struct tx_queue *txq = mp->txq + index;
1651 struct tx_desc *tx_desc;
1657 txq->tx_ring_size = mp->default_tx_ring_size;
1659 txq->tx_desc_count = 0;
1660 txq->tx_curr_desc = 0;
1661 txq->tx_used_desc = 0;
1663 size = txq->tx_ring_size * sizeof(struct tx_desc);
1665 if (index == 0 && size <= mp->tx_desc_sram_size) {
1666 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1667 mp->tx_desc_sram_size);
1668 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1670 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1675 if (txq->tx_desc_area == NULL) {
1676 dev_printk(KERN_ERR, &mp->dev->dev,
1677 "can't allocate tx ring (%d bytes)\n", size);
1680 memset(txq->tx_desc_area, 0, size);
1682 txq->tx_desc_area_size = size;
1683 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1685 if (txq->tx_skb == NULL) {
1686 dev_printk(KERN_ERR, &mp->dev->dev,
1687 "can't allocate tx skb ring\n");
1691 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1692 for (i = 0; i < txq->tx_ring_size; i++) {
1693 struct tx_desc *txd = tx_desc + i;
1697 if (nexti == txq->tx_ring_size)
1701 txd->next_desc_ptr = txq->tx_desc_dma +
1702 nexti * sizeof(struct tx_desc);
1708 if (index == 0 && size <= mp->tx_desc_sram_size)
1709 iounmap(txq->tx_desc_area);
1711 dma_free_coherent(NULL, size,
1719 static void txq_deinit(struct tx_queue *txq)
1721 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1724 txq_reclaim(txq, txq->tx_ring_size, 1);
1726 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1728 if (txq->index == 0 &&
1729 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1730 iounmap(txq->tx_desc_area);
1732 dma_free_coherent(NULL, txq->tx_desc_area_size,
1733 txq->tx_desc_area, txq->tx_desc_dma);
1739 /* netdev ops and related ***************************************************/
1740 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1745 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1746 (INT_TX_END | INT_RX | INT_EXT);
1751 if (int_cause & INT_EXT)
1752 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num));
1754 int_cause &= INT_TX_END | INT_RX;
1756 wrl(mp, INT_CAUSE(mp->port_num), ~int_cause);
1757 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1758 ~(rdl(mp, TXQ_COMMAND(mp->port_num)) & 0xff);
1759 mp->work_rx |= (int_cause & INT_RX) >> 2;
1762 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1763 if (int_cause_ext) {
1764 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1765 if (int_cause_ext & INT_EXT_LINK_PHY)
1767 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1773 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1775 struct net_device *dev = (struct net_device *)dev_id;
1776 struct mv643xx_eth_private *mp = netdev_priv(dev);
1778 if (unlikely(!mv643xx_eth_collect_events(mp)))
1781 wrl(mp, INT_MASK(mp->port_num), 0);
1782 napi_schedule(&mp->napi);
1787 static void handle_link_event(struct mv643xx_eth_private *mp)
1789 struct net_device *dev = mp->dev;
1795 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1796 if (!(port_status & LINK_UP)) {
1797 if (netif_carrier_ok(dev)) {
1800 printk(KERN_INFO "%s: link down\n", dev->name);
1802 netif_carrier_off(dev);
1804 for (i = 0; i < mp->txq_count; i++) {
1805 struct tx_queue *txq = mp->txq + i;
1807 txq_reclaim(txq, txq->tx_ring_size, 1);
1808 txq_reset_hw_ptr(txq);
1814 switch (port_status & PORT_SPEED_MASK) {
1818 case PORT_SPEED_100:
1821 case PORT_SPEED_1000:
1828 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1829 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1831 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1832 "flow control %sabled\n", dev->name,
1833 speed, duplex ? "full" : "half",
1836 if (!netif_carrier_ok(dev))
1837 netif_carrier_on(dev);
1840 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
1842 struct mv643xx_eth_private *mp;
1845 mp = container_of(napi, struct mv643xx_eth_private, napi);
1847 mp->work_rx_refill |= mp->work_rx_oom;
1848 mp->work_rx_oom = 0;
1851 while (work_done < budget) {
1856 if (mp->work_link) {
1858 handle_link_event(mp);
1862 queue_mask = mp->work_tx | mp->work_tx_end |
1863 mp->work_rx | mp->work_rx_refill;
1865 if (mv643xx_eth_collect_events(mp))
1870 queue = fls(queue_mask) - 1;
1871 queue_mask = 1 << queue;
1873 work_tbd = budget - work_done;
1877 if (mp->work_tx_end & queue_mask) {
1878 txq_kick(mp->txq + queue);
1879 } else if (mp->work_tx & queue_mask) {
1880 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
1881 txq_maybe_wake(mp->txq + queue);
1882 } else if (mp->work_rx & queue_mask) {
1883 work_done += rxq_process(mp->rxq + queue, work_tbd);
1884 } else if (mp->work_rx_refill & queue_mask) {
1885 work_done += rxq_refill(mp->rxq + queue, work_tbd);
1891 if (work_done < budget) {
1892 if (mp->work_rx_oom)
1893 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
1894 napi_complete(napi);
1895 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
1901 static inline void oom_timer_wrapper(unsigned long data)
1903 struct mv643xx_eth_private *mp = (void *)data;
1905 napi_schedule(&mp->napi);
1908 static void phy_reset(struct mv643xx_eth_private *mp)
1912 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1917 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data) < 0)
1921 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
1922 } while (data >= 0 && data & BMCR_RESET);
1925 static void port_start(struct mv643xx_eth_private *mp)
1931 * Perform PHY reset, if there is a PHY.
1933 if (mp->phy_addr != -1) {
1934 struct ethtool_cmd cmd;
1936 mv643xx_eth_get_settings(mp->dev, &cmd);
1938 mv643xx_eth_set_settings(mp->dev, &cmd);
1942 * Configure basic link parameters.
1944 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1946 pscr |= SERIAL_PORT_ENABLE;
1947 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1949 pscr |= DO_NOT_FORCE_LINK_FAIL;
1950 if (mp->phy_addr == -1)
1951 pscr |= FORCE_LINK_PASS;
1952 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1954 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1957 * Configure TX path and queues.
1959 tx_set_rate(mp, 1000000000, 16777216);
1960 for (i = 0; i < mp->txq_count; i++) {
1961 struct tx_queue *txq = mp->txq + i;
1963 txq_reset_hw_ptr(txq);
1964 txq_set_rate(txq, 1000000000, 16777216);
1965 txq_set_fixed_prio_mode(txq);
1969 * Add configured unicast address to address filter table.
1971 uc_addr_set(mp, mp->dev->dev_addr);
1974 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1975 * frames to RX queue #0.
1977 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1980 * Treat BPDUs as normal multicasts, and disable partition mode.
1982 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1985 * Enable the receive queues.
1987 for (i = 0; i < mp->rxq_count; i++) {
1988 struct rx_queue *rxq = mp->rxq + i;
1989 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
1992 addr = (u32)rxq->rx_desc_dma;
1993 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2000 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2002 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2005 val = rdl(mp, SDMA_CONFIG(mp->port_num));
2006 if (mp->shared->extended_rx_coal_limit) {
2010 val |= (coal & 0x8000) << 10;
2011 val |= (coal & 0x7fff) << 7;
2016 val |= (coal & 0x3fff) << 8;
2018 wrl(mp, SDMA_CONFIG(mp->port_num), val);
2021 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
2023 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2027 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2030 static int mv643xx_eth_open(struct net_device *dev)
2032 struct mv643xx_eth_private *mp = netdev_priv(dev);
2036 wrl(mp, INT_CAUSE(mp->port_num), 0);
2037 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2038 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2040 err = request_irq(dev->irq, mv643xx_eth_irq,
2041 IRQF_SHARED, dev->name, dev);
2043 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2047 init_mac_tables(mp);
2049 napi_enable(&mp->napi);
2051 for (i = 0; i < mp->rxq_count; i++) {
2052 err = rxq_init(mp, i);
2055 rxq_deinit(mp->rxq + i);
2059 rxq_refill(mp->rxq + i, INT_MAX);
2062 if (mp->work_rx_oom) {
2063 mp->rx_oom.expires = jiffies + (HZ / 10);
2064 add_timer(&mp->rx_oom);
2067 for (i = 0; i < mp->txq_count; i++) {
2068 err = txq_init(mp, i);
2071 txq_deinit(mp->txq + i);
2076 netif_carrier_off(dev);
2083 wrl(mp, INT_MASK_EXT(mp->port_num), INT_EXT_LINK_PHY | INT_EXT_TX);
2084 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2090 for (i = 0; i < mp->rxq_count; i++)
2091 rxq_deinit(mp->rxq + i);
2093 free_irq(dev->irq, dev);
2098 static void port_reset(struct mv643xx_eth_private *mp)
2103 for (i = 0; i < mp->rxq_count; i++)
2104 rxq_disable(mp->rxq + i);
2105 for (i = 0; i < mp->txq_count; i++)
2106 txq_disable(mp->txq + i);
2109 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2111 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2116 /* Reset the Enable bit in the Configuration Register */
2117 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2118 data &= ~(SERIAL_PORT_ENABLE |
2119 DO_NOT_FORCE_LINK_FAIL |
2121 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2124 static int mv643xx_eth_stop(struct net_device *dev)
2126 struct mv643xx_eth_private *mp = netdev_priv(dev);
2129 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2130 rdl(mp, INT_MASK(mp->port_num));
2132 napi_disable(&mp->napi);
2134 del_timer_sync(&mp->rx_oom);
2136 netif_carrier_off(dev);
2138 free_irq(dev->irq, dev);
2141 mib_counters_update(mp);
2143 for (i = 0; i < mp->rxq_count; i++)
2144 rxq_deinit(mp->rxq + i);
2145 for (i = 0; i < mp->txq_count; i++)
2146 txq_deinit(mp->txq + i);
2151 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2153 struct mv643xx_eth_private *mp = netdev_priv(dev);
2155 if (mp->phy_addr != -1)
2156 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2161 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2163 struct mv643xx_eth_private *mp = netdev_priv(dev);
2165 if (new_mtu < 64 || new_mtu > 9500)
2169 tx_set_rate(mp, 1000000000, 16777216);
2171 if (!netif_running(dev))
2175 * Stop and then re-open the interface. This will allocate RX
2176 * skbs of the new MTU.
2177 * There is a possible danger that the open will not succeed,
2178 * due to memory being full.
2180 mv643xx_eth_stop(dev);
2181 if (mv643xx_eth_open(dev)) {
2182 dev_printk(KERN_ERR, &dev->dev,
2183 "fatal error on re-opening device after "
2190 static void tx_timeout_task(struct work_struct *ugly)
2192 struct mv643xx_eth_private *mp;
2194 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2195 if (netif_running(mp->dev)) {
2196 netif_tx_stop_all_queues(mp->dev);
2199 netif_tx_wake_all_queues(mp->dev);
2203 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2205 struct mv643xx_eth_private *mp = netdev_priv(dev);
2207 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2209 schedule_work(&mp->tx_timeout_task);
2212 #ifdef CONFIG_NET_POLL_CONTROLLER
2213 static void mv643xx_eth_netpoll(struct net_device *dev)
2215 struct mv643xx_eth_private *mp = netdev_priv(dev);
2217 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2218 rdl(mp, INT_MASK(mp->port_num));
2220 mv643xx_eth_irq(dev->irq, dev);
2222 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2226 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2228 struct mv643xx_eth_private *mp = netdev_priv(dev);
2229 return smi_reg_read(mp, addr, reg);
2232 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2234 struct mv643xx_eth_private *mp = netdev_priv(dev);
2235 smi_reg_write(mp, addr, reg, val);
2239 /* platform glue ************************************************************/
2241 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2242 struct mbus_dram_target_info *dram)
2244 void __iomem *base = msp->base;
2249 for (i = 0; i < 6; i++) {
2250 writel(0, base + WINDOW_BASE(i));
2251 writel(0, base + WINDOW_SIZE(i));
2253 writel(0, base + WINDOW_REMAP_HIGH(i));
2259 for (i = 0; i < dram->num_cs; i++) {
2260 struct mbus_dram_window *cs = dram->cs + i;
2262 writel((cs->base & 0xffff0000) |
2263 (cs->mbus_attr << 8) |
2264 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2265 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2267 win_enable &= ~(1 << i);
2268 win_protect |= 3 << (2 * i);
2271 writel(win_enable, base + WINDOW_BAR_ENABLE);
2272 msp->win_protect = win_protect;
2275 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2278 * Check whether we have a 14-bit coal limit field in bits
2279 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2280 * SDMA config register.
2282 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2283 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2284 msp->extended_rx_coal_limit = 1;
2286 msp->extended_rx_coal_limit = 0;
2289 * Check whether the TX rate control registers are in the
2290 * old or the new place.
2292 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2293 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2294 msp->tx_bw_control_moved = 1;
2296 msp->tx_bw_control_moved = 0;
2299 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2301 static int mv643xx_eth_version_printed = 0;
2302 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2303 struct mv643xx_eth_shared_private *msp;
2304 struct resource *res;
2307 if (!mv643xx_eth_version_printed++)
2308 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2309 "driver version %s\n", mv643xx_eth_driver_version);
2312 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2317 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2320 memset(msp, 0, sizeof(*msp));
2322 msp->base = ioremap(res->start, res->end - res->start + 1);
2323 if (msp->base == NULL)
2327 if (pd != NULL && pd->shared_smi != NULL)
2328 msp->smi = platform_get_drvdata(pd->shared_smi);
2330 mutex_init(&msp->phy_lock);
2332 msp->err_interrupt = NO_IRQ;
2333 init_waitqueue_head(&msp->smi_busy_wait);
2336 * Check whether the error interrupt is hooked up.
2338 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2342 err = request_irq(res->start, mv643xx_eth_err_irq,
2343 IRQF_SHARED, "mv643xx_eth", msp);
2345 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2346 msp->err_interrupt = res->start;
2351 * (Re-)program MBUS remapping windows if we are asked to.
2353 if (pd != NULL && pd->dram != NULL)
2354 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2357 * Detect hardware parameters.
2359 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2360 infer_hw_params(msp);
2362 platform_set_drvdata(pdev, msp);
2372 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2374 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2376 if (msp->err_interrupt != NO_IRQ)
2377 free_irq(msp->err_interrupt, msp);
2384 static struct platform_driver mv643xx_eth_shared_driver = {
2385 .probe = mv643xx_eth_shared_probe,
2386 .remove = mv643xx_eth_shared_remove,
2388 .name = MV643XX_ETH_SHARED_NAME,
2389 .owner = THIS_MODULE,
2393 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2395 int addr_shift = 5 * mp->port_num;
2398 data = rdl(mp, PHY_ADDR);
2399 data &= ~(0x1f << addr_shift);
2400 data |= (phy_addr & 0x1f) << addr_shift;
2401 wrl(mp, PHY_ADDR, data);
2404 static int phy_addr_get(struct mv643xx_eth_private *mp)
2408 data = rdl(mp, PHY_ADDR);
2410 return (data >> (5 * mp->port_num)) & 0x1f;
2413 static void set_params(struct mv643xx_eth_private *mp,
2414 struct mv643xx_eth_platform_data *pd)
2416 struct net_device *dev = mp->dev;
2418 if (is_valid_ether_addr(pd->mac_addr))
2419 memcpy(dev->dev_addr, pd->mac_addr, 6);
2421 uc_addr_get(mp, dev->dev_addr);
2423 if (pd->phy_addr == MV643XX_ETH_PHY_NONE) {
2426 if (pd->phy_addr != MV643XX_ETH_PHY_ADDR_DEFAULT) {
2427 mp->phy_addr = pd->phy_addr & 0x3f;
2428 phy_addr_set(mp, mp->phy_addr);
2430 mp->phy_addr = phy_addr_get(mp);
2434 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2435 if (pd->rx_queue_size)
2436 mp->default_rx_ring_size = pd->rx_queue_size;
2437 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2438 mp->rx_desc_sram_size = pd->rx_sram_size;
2440 mp->rxq_count = pd->rx_queue_count ? : 1;
2442 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2443 if (pd->tx_queue_size)
2444 mp->default_tx_ring_size = pd->tx_queue_size;
2445 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2446 mp->tx_desc_sram_size = pd->tx_sram_size;
2448 mp->txq_count = pd->tx_queue_count ? : 1;
2451 static int phy_detect(struct mv643xx_eth_private *mp)
2456 data = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2460 if (smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE) < 0)
2463 data2 = smi_reg_read(mp, mp->phy_addr, MII_BMCR);
2467 if (((data ^ data2) & BMCR_ANENABLE) == 0)
2470 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
2475 static int phy_init(struct mv643xx_eth_private *mp,
2476 struct mv643xx_eth_platform_data *pd)
2478 struct ethtool_cmd cmd;
2481 err = phy_detect(mp);
2483 dev_printk(KERN_INFO, &mp->dev->dev,
2484 "no PHY detected at addr %d\n", mp->phy_addr);
2489 mp->mii.phy_id = mp->phy_addr;
2490 mp->mii.phy_id_mask = 0x3f;
2491 mp->mii.reg_num_mask = 0x1f;
2492 mp->mii.dev = mp->dev;
2493 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2494 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2496 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2498 memset(&cmd, 0, sizeof(cmd));
2500 cmd.port = PORT_MII;
2501 cmd.transceiver = XCVR_INTERNAL;
2502 cmd.phy_address = mp->phy_addr;
2503 if (pd->speed == 0) {
2504 cmd.autoneg = AUTONEG_ENABLE;
2505 cmd.speed = SPEED_100;
2506 cmd.advertising = ADVERTISED_10baseT_Half |
2507 ADVERTISED_10baseT_Full |
2508 ADVERTISED_100baseT_Half |
2509 ADVERTISED_100baseT_Full;
2510 if (mp->mii.supports_gmii)
2511 cmd.advertising |= ADVERTISED_1000baseT_Full;
2513 cmd.autoneg = AUTONEG_DISABLE;
2514 cmd.speed = pd->speed;
2515 cmd.duplex = pd->duplex;
2518 mv643xx_eth_set_settings(mp->dev, &cmd);
2523 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2527 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2528 if (pscr & SERIAL_PORT_ENABLE) {
2529 pscr &= ~SERIAL_PORT_ENABLE;
2530 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2533 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2534 if (mp->phy_addr == -1) {
2535 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2536 if (speed == SPEED_1000)
2537 pscr |= SET_GMII_SPEED_TO_1000;
2538 else if (speed == SPEED_100)
2539 pscr |= SET_MII_SPEED_TO_100;
2541 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2543 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2544 if (duplex == DUPLEX_FULL)
2545 pscr |= SET_FULL_DUPLEX_MODE;
2548 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2551 static int mv643xx_eth_probe(struct platform_device *pdev)
2553 struct mv643xx_eth_platform_data *pd;
2554 struct mv643xx_eth_private *mp;
2555 struct net_device *dev;
2556 struct resource *res;
2557 DECLARE_MAC_BUF(mac);
2560 pd = pdev->dev.platform_data;
2562 dev_printk(KERN_ERR, &pdev->dev,
2563 "no mv643xx_eth_platform_data\n");
2567 if (pd->shared == NULL) {
2568 dev_printk(KERN_ERR, &pdev->dev,
2569 "no mv643xx_eth_platform_data->shared\n");
2573 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2577 mp = netdev_priv(dev);
2578 platform_set_drvdata(pdev, mp);
2580 mp->shared = platform_get_drvdata(pd->shared);
2581 mp->port_num = pd->port_number;
2586 dev->real_num_tx_queues = mp->txq_count;
2588 spin_lock_init(&mp->lock);
2590 mib_counters_clear(mp);
2591 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2593 if (mp->phy_addr != -1) {
2594 err = phy_init(mp, pd);
2598 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2600 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2602 init_pscr(mp, pd->speed, pd->duplex);
2604 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2606 init_timer(&mp->rx_oom);
2607 mp->rx_oom.data = (unsigned long)mp;
2608 mp->rx_oom.function = oom_timer_wrapper;
2611 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2613 dev->irq = res->start;
2615 dev->hard_start_xmit = mv643xx_eth_xmit;
2616 dev->open = mv643xx_eth_open;
2617 dev->stop = mv643xx_eth_stop;
2618 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2619 dev->set_mac_address = mv643xx_eth_set_mac_address;
2620 dev->do_ioctl = mv643xx_eth_ioctl;
2621 dev->change_mtu = mv643xx_eth_change_mtu;
2622 dev->tx_timeout = mv643xx_eth_tx_timeout;
2623 #ifdef CONFIG_NET_POLL_CONTROLLER
2624 dev->poll_controller = mv643xx_eth_netpoll;
2626 dev->watchdog_timeo = 2 * HZ;
2629 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2630 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2632 SET_NETDEV_DEV(dev, &pdev->dev);
2634 if (mp->shared->win_protect)
2635 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2637 err = register_netdev(dev);
2641 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2642 mp->port_num, print_mac(mac, dev->dev_addr));
2644 if (mp->tx_desc_sram_size > 0)
2645 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2655 static int mv643xx_eth_remove(struct platform_device *pdev)
2657 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2659 unregister_netdev(mp->dev);
2660 flush_scheduled_work();
2661 free_netdev(mp->dev);
2663 platform_set_drvdata(pdev, NULL);
2668 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2670 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2672 /* Mask all interrupts on ethernet port */
2673 wrl(mp, INT_MASK(mp->port_num), 0);
2674 rdl(mp, INT_MASK(mp->port_num));
2676 if (netif_running(mp->dev))
2680 static struct platform_driver mv643xx_eth_driver = {
2681 .probe = mv643xx_eth_probe,
2682 .remove = mv643xx_eth_remove,
2683 .shutdown = mv643xx_eth_shutdown,
2685 .name = MV643XX_ETH_NAME,
2686 .owner = THIS_MODULE,
2690 static int __init mv643xx_eth_init_module(void)
2694 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2696 rc = platform_driver_register(&mv643xx_eth_driver);
2698 platform_driver_unregister(&mv643xx_eth_shared_driver);
2703 module_init(mv643xx_eth_init_module);
2705 static void __exit mv643xx_eth_cleanup_module(void)
2707 platform_driver_unregister(&mv643xx_eth_driver);
2708 platform_driver_unregister(&mv643xx_eth_shared_driver);
2710 module_exit(mv643xx_eth_cleanup_module);
2712 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2713 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2714 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2715 MODULE_LICENSE("GPL");
2716 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2717 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);