2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.3";
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_NAPI
62 #define MV643XX_ETH_TX_FAST_REFILL
64 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
65 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
67 #define MAX_DESCS_PER_SKB 1
71 * Registers shared between all ports.
73 #define PHY_ADDR 0x0000
74 #define SMI_REG 0x0004
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
84 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
85 #define UNICAST_PROMISCUOUS_MODE 0x00000001
86 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
92 #define TX_FIFO_EMPTY 0x00000400
93 #define TX_IN_PROGRESS 0x00000080
94 #define PORT_SPEED_MASK 0x00000030
95 #define PORT_SPEED_1000 0x00000010
96 #define PORT_SPEED_100 0x00000020
97 #define PORT_SPEED_10 0x00000000
98 #define FLOW_CONTROL_ENABLED 0x00000008
99 #define FULL_DUPLEX 0x00000004
100 #define LINK_UP 0x00000002
101 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
102 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
103 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
104 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
105 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
106 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
107 #define INT_TX_END_0 0x00080000
108 #define INT_TX_END 0x07f80000
109 #define INT_RX 0x0007fbfc
110 #define INT_EXT 0x00000002
111 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
112 #define INT_EXT_LINK 0x00100000
113 #define INT_EXT_PHY 0x00010000
114 #define INT_EXT_TX_ERROR_0 0x00000100
115 #define INT_EXT_TX_0 0x00000001
116 #define INT_EXT_TX 0x0000ffff
117 #define INT_MASK(p) (0x0468 + ((p) << 10))
118 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
119 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
120 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
121 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
122 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
123 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
124 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
125 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
126 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
127 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
128 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
129 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
130 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
131 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
132 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
133 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
137 * SDMA configuration register.
139 #define RX_BURST_SIZE_16_64BIT (4 << 1)
140 #define BLM_RX_NO_SWAP (1 << 4)
141 #define BLM_TX_NO_SWAP (1 << 5)
142 #define TX_BURST_SIZE_16_64BIT (4 << 22)
144 #if defined(__BIG_ENDIAN)
145 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
146 RX_BURST_SIZE_16_64BIT | \
147 TX_BURST_SIZE_16_64BIT
148 #elif defined(__LITTLE_ENDIAN)
149 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
150 RX_BURST_SIZE_16_64BIT | \
153 TX_BURST_SIZE_16_64BIT
155 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
160 * Port serial control register.
162 #define SET_MII_SPEED_TO_100 (1 << 24)
163 #define SET_GMII_SPEED_TO_1000 (1 << 23)
164 #define SET_FULL_DUPLEX_MODE (1 << 21)
165 #define MAX_RX_PACKET_9700BYTE (5 << 17)
166 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
167 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
168 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
169 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
170 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
171 #define FORCE_LINK_PASS (1 << 1)
172 #define SERIAL_PORT_ENABLE (1 << 0)
174 #define DEFAULT_RX_QUEUE_SIZE 400
175 #define DEFAULT_TX_QUEUE_SIZE 800
181 #if defined(__BIG_ENDIAN)
183 u16 byte_cnt; /* Descriptor buffer byte count */
184 u16 buf_size; /* Buffer size */
185 u32 cmd_sts; /* Descriptor command status */
186 u32 next_desc_ptr; /* Next descriptor pointer */
187 u32 buf_ptr; /* Descriptor buffer pointer */
191 u16 byte_cnt; /* buffer byte count */
192 u16 l4i_chk; /* CPU provided TCP checksum */
193 u32 cmd_sts; /* Command/status field */
194 u32 next_desc_ptr; /* Pointer to next descriptor */
195 u32 buf_ptr; /* pointer to buffer for this descriptor*/
197 #elif defined(__LITTLE_ENDIAN)
199 u32 cmd_sts; /* Descriptor command status */
200 u16 buf_size; /* Buffer size */
201 u16 byte_cnt; /* Descriptor buffer byte count */
202 u32 buf_ptr; /* Descriptor buffer pointer */
203 u32 next_desc_ptr; /* Next descriptor pointer */
207 u32 cmd_sts; /* Command/status field */
208 u16 l4i_chk; /* CPU provided TCP checksum */
209 u16 byte_cnt; /* buffer byte count */
210 u32 buf_ptr; /* pointer to buffer for this descriptor*/
211 u32 next_desc_ptr; /* Pointer to next descriptor */
214 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
217 /* RX & TX descriptor command */
218 #define BUFFER_OWNED_BY_DMA 0x80000000
220 /* RX & TX descriptor status */
221 #define ERROR_SUMMARY 0x00000001
223 /* RX descriptor status */
224 #define LAYER_4_CHECKSUM_OK 0x40000000
225 #define RX_ENABLE_INTERRUPT 0x20000000
226 #define RX_FIRST_DESC 0x08000000
227 #define RX_LAST_DESC 0x04000000
229 /* TX descriptor command */
230 #define TX_ENABLE_INTERRUPT 0x00800000
231 #define GEN_CRC 0x00400000
232 #define TX_FIRST_DESC 0x00200000
233 #define TX_LAST_DESC 0x00100000
234 #define ZERO_PADDING 0x00080000
235 #define GEN_IP_V4_CHECKSUM 0x00040000
236 #define GEN_TCP_UDP_CHECKSUM 0x00020000
237 #define UDP_FRAME 0x00010000
238 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
239 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
241 #define TX_IHL_SHIFT 11
244 /* global *******************************************************************/
245 struct mv643xx_eth_shared_private {
247 * Ethernet controller base address.
252 * Protects access to SMI_REG, which is shared between ports.
254 struct mutex phy_lock;
257 * Per-port MBUS window access register value.
262 * Hardware-specific parameters.
265 int extended_rx_coal_limit;
266 int tx_bw_control_moved;
270 /* per-port *****************************************************************/
271 struct mib_counters {
272 u64 good_octets_received;
273 u32 bad_octets_received;
274 u32 internal_mac_transmit_err;
275 u32 good_frames_received;
276 u32 bad_frames_received;
277 u32 broadcast_frames_received;
278 u32 multicast_frames_received;
279 u32 frames_64_octets;
280 u32 frames_65_to_127_octets;
281 u32 frames_128_to_255_octets;
282 u32 frames_256_to_511_octets;
283 u32 frames_512_to_1023_octets;
284 u32 frames_1024_to_max_octets;
285 u64 good_octets_sent;
286 u32 good_frames_sent;
287 u32 excessive_collision;
288 u32 multicast_frames_sent;
289 u32 broadcast_frames_sent;
290 u32 unrec_mac_control_received;
292 u32 good_fc_received;
294 u32 undersize_received;
295 u32 fragments_received;
296 u32 oversize_received;
298 u32 mac_receive_error;
313 struct rx_desc *rx_desc_area;
314 dma_addr_t rx_desc_dma;
315 int rx_desc_area_size;
316 struct sk_buff **rx_skb;
318 struct timer_list rx_oom;
330 struct tx_desc *tx_desc_area;
331 dma_addr_t tx_desc_dma;
332 int tx_desc_area_size;
333 struct sk_buff **tx_skb;
336 struct mv643xx_eth_private {
337 struct mv643xx_eth_shared_private *shared;
340 struct net_device *dev;
342 struct mv643xx_eth_shared_private *shared_smi;
347 struct mib_counters mib_counters;
348 struct work_struct tx_timeout_task;
349 struct mii_if_info mii;
354 int default_rx_ring_size;
355 unsigned long rx_desc_sram_addr;
356 int rx_desc_sram_size;
359 struct napi_struct napi;
360 struct rx_queue rxq[8];
365 int default_tx_ring_size;
366 unsigned long tx_desc_sram_addr;
367 int tx_desc_sram_size;
370 struct tx_queue txq[8];
371 #ifdef MV643XX_ETH_TX_FAST_REFILL
372 int tx_clean_threshold;
377 /* port register accessors **************************************************/
378 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
380 return readl(mp->shared->base + offset);
383 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
385 writel(data, mp->shared->base + offset);
389 /* rxq/txq helper functions *************************************************/
390 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
392 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
395 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
397 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
400 static void rxq_enable(struct rx_queue *rxq)
402 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
403 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
406 static void rxq_disable(struct rx_queue *rxq)
408 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
409 u8 mask = 1 << rxq->index;
411 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
412 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
416 static void txq_reset_hw_ptr(struct tx_queue *txq)
418 struct mv643xx_eth_private *mp = txq_to_mp(txq);
419 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
422 addr = (u32)txq->tx_desc_dma;
423 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
427 static void txq_enable(struct tx_queue *txq)
429 struct mv643xx_eth_private *mp = txq_to_mp(txq);
430 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
433 static void txq_disable(struct tx_queue *txq)
435 struct mv643xx_eth_private *mp = txq_to_mp(txq);
436 u8 mask = 1 << txq->index;
438 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
439 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
443 static void __txq_maybe_wake(struct tx_queue *txq)
445 struct mv643xx_eth_private *mp = txq_to_mp(txq);
448 * netif_{stop,wake}_queue() flow control only applies to
451 BUG_ON(txq->index != mp->txq_primary);
453 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
454 netif_wake_queue(mp->dev);
458 /* rx ***********************************************************************/
459 static void txq_reclaim(struct tx_queue *txq, int force);
461 static void rxq_refill(struct rx_queue *rxq)
463 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
466 spin_lock_irqsave(&mp->lock, flags);
468 while (rxq->rx_desc_count < rxq->rx_ring_size) {
475 * Reserve 2+14 bytes for an ethernet header (the
476 * hardware automatically prepends 2 bytes of dummy
477 * data to each received packet), 16 bytes for up to
478 * four VLAN tags, and 4 bytes for the trailing FCS
481 skb_size = mp->dev->mtu + 36;
484 * Make sure that the skb size is a multiple of 8
485 * bytes, as the lower three bits of the receive
486 * descriptor's buffer size field are ignored by
489 skb_size = (skb_size + 7) & ~7;
491 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
495 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
497 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
499 rxq->rx_desc_count++;
501 rx = rxq->rx_used_desc++;
502 if (rxq->rx_used_desc == rxq->rx_ring_size)
503 rxq->rx_used_desc = 0;
505 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
506 skb_size, DMA_FROM_DEVICE);
507 rxq->rx_desc_area[rx].buf_size = skb_size;
508 rxq->rx_skb[rx] = skb;
510 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
515 * The hardware automatically prepends 2 bytes of
516 * dummy data to each received packet, so that the
517 * IP header ends up 16-byte aligned.
522 if (rxq->rx_desc_count != rxq->rx_ring_size)
523 mod_timer(&rxq->rx_oom, jiffies + (HZ / 10));
525 spin_unlock_irqrestore(&mp->lock, flags);
528 static inline void rxq_refill_timer_wrapper(unsigned long data)
530 rxq_refill((struct rx_queue *)data);
533 static int rxq_process(struct rx_queue *rxq, int budget)
535 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
536 struct net_device_stats *stats = &mp->dev->stats;
540 while (rx < budget && rxq->rx_desc_count) {
541 struct rx_desc *rx_desc;
542 unsigned int cmd_sts;
546 spin_lock_irqsave(&mp->lock, flags);
548 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
550 cmd_sts = rx_desc->cmd_sts;
551 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
552 spin_unlock_irqrestore(&mp->lock, flags);
557 skb = rxq->rx_skb[rxq->rx_curr_desc];
558 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
561 if (rxq->rx_curr_desc == rxq->rx_ring_size)
562 rxq->rx_curr_desc = 0;
564 spin_unlock_irqrestore(&mp->lock, flags);
566 dma_unmap_single(NULL, rx_desc->buf_ptr,
567 rx_desc->buf_size, DMA_FROM_DEVICE);
568 rxq->rx_desc_count--;
574 * Note that the descriptor byte count includes 2 dummy
575 * bytes automatically inserted by the hardware at the
576 * start of the packet (which we don't count), and a 4
577 * byte CRC at the end of the packet (which we do count).
580 stats->rx_bytes += rx_desc->byte_cnt - 2;
583 * In case we received a packet without first / last bits
584 * on, or the error summary bit is set, the packet needs
587 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
588 (RX_FIRST_DESC | RX_LAST_DESC))
589 || (cmd_sts & ERROR_SUMMARY)) {
592 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
593 (RX_FIRST_DESC | RX_LAST_DESC)) {
595 dev_printk(KERN_ERR, &mp->dev->dev,
596 "received packet spanning "
597 "multiple descriptors\n");
600 if (cmd_sts & ERROR_SUMMARY)
603 dev_kfree_skb_irq(skb);
606 * The -4 is for the CRC in the trailer of the
609 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
611 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
612 skb->ip_summed = CHECKSUM_UNNECESSARY;
614 (cmd_sts & 0x0007fff8) >> 3);
616 skb->protocol = eth_type_trans(skb, mp->dev);
617 #ifdef MV643XX_ETH_NAPI
618 netif_receive_skb(skb);
624 mp->dev->last_rx = jiffies;
632 #ifdef MV643XX_ETH_NAPI
633 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
635 struct mv643xx_eth_private *mp;
639 mp = container_of(napi, struct mv643xx_eth_private, napi);
641 #ifdef MV643XX_ETH_TX_FAST_REFILL
642 if (++mp->tx_clean_threshold > 5) {
643 mp->tx_clean_threshold = 0;
644 for (i = 0; i < 8; i++)
645 if (mp->txq_mask & (1 << i))
646 txq_reclaim(mp->txq + i, 0);
648 if (netif_carrier_ok(mp->dev)) {
649 spin_lock_irq(&mp->lock);
650 __txq_maybe_wake(mp->txq + mp->txq_primary);
651 spin_unlock_irq(&mp->lock);
657 for (i = 7; rx < budget && i >= 0; i--)
658 if (mp->rxq_mask & (1 << i))
659 rx += rxq_process(mp->rxq + i, budget - rx);
662 netif_rx_complete(mp->dev, napi);
663 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
671 /* tx ***********************************************************************/
672 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
676 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
677 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
678 if (fragp->size <= 8 && fragp->page_offset & 7)
685 static int txq_alloc_desc_index(struct tx_queue *txq)
689 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
691 tx_desc_curr = txq->tx_curr_desc++;
692 if (txq->tx_curr_desc == txq->tx_ring_size)
693 txq->tx_curr_desc = 0;
695 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
700 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
702 int nr_frags = skb_shinfo(skb)->nr_frags;
705 for (frag = 0; frag < nr_frags; frag++) {
706 skb_frag_t *this_frag;
708 struct tx_desc *desc;
710 this_frag = &skb_shinfo(skb)->frags[frag];
711 tx_index = txq_alloc_desc_index(txq);
712 desc = &txq->tx_desc_area[tx_index];
715 * The last fragment will generate an interrupt
716 * which will free the skb on TX completion.
718 if (frag == nr_frags - 1) {
719 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
720 ZERO_PADDING | TX_LAST_DESC |
722 txq->tx_skb[tx_index] = skb;
724 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
725 txq->tx_skb[tx_index] = NULL;
729 desc->byte_cnt = this_frag->size;
730 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
731 this_frag->page_offset,
737 static inline __be16 sum16_as_be(__sum16 sum)
739 return (__force __be16)sum;
742 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
744 struct mv643xx_eth_private *mp = txq_to_mp(txq);
745 int nr_frags = skb_shinfo(skb)->nr_frags;
747 struct tx_desc *desc;
751 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
753 tx_index = txq_alloc_desc_index(txq);
754 desc = &txq->tx_desc_area[tx_index];
757 txq_submit_frag_skb(txq, skb);
759 length = skb_headlen(skb);
760 txq->tx_skb[tx_index] = NULL;
762 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
764 txq->tx_skb[tx_index] = skb;
767 desc->byte_cnt = length;
768 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
770 if (skb->ip_summed == CHECKSUM_PARTIAL) {
773 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
774 skb->protocol != htons(ETH_P_8021Q));
776 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
778 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
780 mac_hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
781 switch (mac_hdr_len - ETH_HLEN) {
785 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
788 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
791 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
792 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
796 dev_printk(KERN_ERR, &txq_to_mp(txq)->dev->dev,
797 "mac header length is %d?!\n", mac_hdr_len);
801 switch (ip_hdr(skb)->protocol) {
803 cmd_sts |= UDP_FRAME;
804 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
807 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
813 /* Errata BTS #50, IHL must be 5 if no HW checksum */
814 cmd_sts |= 5 << TX_IHL_SHIFT;
818 /* ensure all other descriptors are written before first cmd_sts */
820 desc->cmd_sts = cmd_sts;
822 /* clear TX_END interrupt status */
823 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
824 rdl(mp, INT_CAUSE(mp->port_num));
826 /* ensure all descriptors are written before poking hardware */
830 txq->tx_desc_count += nr_frags + 1;
833 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
835 struct mv643xx_eth_private *mp = netdev_priv(dev);
836 struct net_device_stats *stats = &dev->stats;
837 struct tx_queue *txq;
840 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
842 dev_printk(KERN_DEBUG, &dev->dev,
843 "failed to linearize skb with tiny "
844 "unaligned fragment\n");
845 return NETDEV_TX_BUSY;
848 spin_lock_irqsave(&mp->lock, flags);
850 txq = mp->txq + mp->txq_primary;
852 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
853 spin_unlock_irqrestore(&mp->lock, flags);
854 if (txq->index == mp->txq_primary && net_ratelimit())
855 dev_printk(KERN_ERR, &dev->dev,
856 "primary tx queue full?!\n");
861 txq_submit_skb(txq, skb);
862 stats->tx_bytes += skb->len;
864 dev->trans_start = jiffies;
866 if (txq->index == mp->txq_primary) {
869 entries_left = txq->tx_ring_size - txq->tx_desc_count;
870 if (entries_left < MAX_DESCS_PER_SKB)
871 netif_stop_queue(dev);
874 spin_unlock_irqrestore(&mp->lock, flags);
880 /* tx rate control **********************************************************/
882 * Set total maximum TX rate (shared by all TX queues for this port)
883 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
885 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
891 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
892 if (token_rate > 1023)
895 mtu = (mp->dev->mtu + 255) >> 8;
899 bucket_size = (burst + 255) >> 8;
900 if (bucket_size > 65535)
903 if (mp->shared->tx_bw_control_moved) {
904 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
905 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
906 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
908 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
909 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
910 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
914 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
916 struct mv643xx_eth_private *mp = txq_to_mp(txq);
920 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
921 if (token_rate > 1023)
924 bucket_size = (burst + 255) >> 8;
925 if (bucket_size > 65535)
928 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
929 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
930 (bucket_size << 10) | token_rate);
933 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
935 struct mv643xx_eth_private *mp = txq_to_mp(txq);
940 * Turn on fixed priority mode.
942 if (mp->shared->tx_bw_control_moved)
943 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
945 off = TXQ_FIX_PRIO_CONF(mp->port_num);
948 val |= 1 << txq->index;
952 static void txq_set_wrr(struct tx_queue *txq, int weight)
954 struct mv643xx_eth_private *mp = txq_to_mp(txq);
959 * Turn off fixed priority mode.
961 if (mp->shared->tx_bw_control_moved)
962 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
964 off = TXQ_FIX_PRIO_CONF(mp->port_num);
967 val &= ~(1 << txq->index);
971 * Configure WRR weight for this queue.
973 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
976 val = (val & ~0xff) | (weight & 0xff);
981 /* mii management interface *************************************************/
982 #define SMI_BUSY 0x10000000
983 #define SMI_READ_VALID 0x08000000
984 #define SMI_OPCODE_READ 0x04000000
985 #define SMI_OPCODE_WRITE 0x00000000
987 static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
988 unsigned int reg, unsigned int *value)
990 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
993 /* the SMI register is a shared resource */
994 mutex_lock(&mp->shared_smi->phy_lock);
996 /* wait for the SMI register to become available */
997 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
999 printk("%s: PHY busy timeout\n", mp->dev->name);
1005 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1007 /* now wait for the data to be valid */
1008 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
1010 printk("%s: PHY read timeout\n", mp->dev->name);
1016 *value = readl(smi_reg) & 0xffff;
1018 mutex_unlock(&mp->shared_smi->phy_lock);
1021 static void smi_reg_write(struct mv643xx_eth_private *mp,
1023 unsigned int reg, unsigned int value)
1025 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
1028 /* the SMI register is a shared resource */
1029 mutex_lock(&mp->shared_smi->phy_lock);
1031 /* wait for the SMI register to become available */
1032 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
1034 printk("%s: PHY busy timeout\n", mp->dev->name);
1040 writel(SMI_OPCODE_WRITE | (reg << 21) |
1041 (addr << 16) | (value & 0xffff), smi_reg);
1043 mutex_unlock(&mp->shared_smi->phy_lock);
1047 /* mib counters *************************************************************/
1048 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1050 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1053 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1057 for (i = 0; i < 0x80; i += 4)
1061 static void mib_counters_update(struct mv643xx_eth_private *mp)
1063 struct mib_counters *p = &mp->mib_counters;
1065 p->good_octets_received += mib_read(mp, 0x00);
1066 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1067 p->bad_octets_received += mib_read(mp, 0x08);
1068 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1069 p->good_frames_received += mib_read(mp, 0x10);
1070 p->bad_frames_received += mib_read(mp, 0x14);
1071 p->broadcast_frames_received += mib_read(mp, 0x18);
1072 p->multicast_frames_received += mib_read(mp, 0x1c);
1073 p->frames_64_octets += mib_read(mp, 0x20);
1074 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1075 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1076 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1077 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1078 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1079 p->good_octets_sent += mib_read(mp, 0x38);
1080 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1081 p->good_frames_sent += mib_read(mp, 0x40);
1082 p->excessive_collision += mib_read(mp, 0x44);
1083 p->multicast_frames_sent += mib_read(mp, 0x48);
1084 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1085 p->unrec_mac_control_received += mib_read(mp, 0x50);
1086 p->fc_sent += mib_read(mp, 0x54);
1087 p->good_fc_received += mib_read(mp, 0x58);
1088 p->bad_fc_received += mib_read(mp, 0x5c);
1089 p->undersize_received += mib_read(mp, 0x60);
1090 p->fragments_received += mib_read(mp, 0x64);
1091 p->oversize_received += mib_read(mp, 0x68);
1092 p->jabber_received += mib_read(mp, 0x6c);
1093 p->mac_receive_error += mib_read(mp, 0x70);
1094 p->bad_crc_event += mib_read(mp, 0x74);
1095 p->collision += mib_read(mp, 0x78);
1096 p->late_collision += mib_read(mp, 0x7c);
1100 /* ethtool ******************************************************************/
1101 struct mv643xx_eth_stats {
1102 char stat_string[ETH_GSTRING_LEN];
1109 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1110 offsetof(struct net_device, stats.m), -1 }
1112 #define MIBSTAT(m) \
1113 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1114 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1116 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1125 MIBSTAT(good_octets_received),
1126 MIBSTAT(bad_octets_received),
1127 MIBSTAT(internal_mac_transmit_err),
1128 MIBSTAT(good_frames_received),
1129 MIBSTAT(bad_frames_received),
1130 MIBSTAT(broadcast_frames_received),
1131 MIBSTAT(multicast_frames_received),
1132 MIBSTAT(frames_64_octets),
1133 MIBSTAT(frames_65_to_127_octets),
1134 MIBSTAT(frames_128_to_255_octets),
1135 MIBSTAT(frames_256_to_511_octets),
1136 MIBSTAT(frames_512_to_1023_octets),
1137 MIBSTAT(frames_1024_to_max_octets),
1138 MIBSTAT(good_octets_sent),
1139 MIBSTAT(good_frames_sent),
1140 MIBSTAT(excessive_collision),
1141 MIBSTAT(multicast_frames_sent),
1142 MIBSTAT(broadcast_frames_sent),
1143 MIBSTAT(unrec_mac_control_received),
1145 MIBSTAT(good_fc_received),
1146 MIBSTAT(bad_fc_received),
1147 MIBSTAT(undersize_received),
1148 MIBSTAT(fragments_received),
1149 MIBSTAT(oversize_received),
1150 MIBSTAT(jabber_received),
1151 MIBSTAT(mac_receive_error),
1152 MIBSTAT(bad_crc_event),
1154 MIBSTAT(late_collision),
1157 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1159 struct mv643xx_eth_private *mp = netdev_priv(dev);
1162 err = mii_ethtool_gset(&mp->mii, cmd);
1165 * The MAC does not support 1000baseT_Half.
1167 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1168 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1173 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1175 struct mv643xx_eth_private *mp = netdev_priv(dev);
1178 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1180 cmd->supported = SUPPORTED_MII;
1181 cmd->advertising = ADVERTISED_MII;
1182 switch (port_status & PORT_SPEED_MASK) {
1184 cmd->speed = SPEED_10;
1186 case PORT_SPEED_100:
1187 cmd->speed = SPEED_100;
1189 case PORT_SPEED_1000:
1190 cmd->speed = SPEED_1000;
1196 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1197 cmd->port = PORT_MII;
1198 cmd->phy_address = 0;
1199 cmd->transceiver = XCVR_INTERNAL;
1200 cmd->autoneg = AUTONEG_DISABLE;
1207 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1209 struct mv643xx_eth_private *mp = netdev_priv(dev);
1212 * The MAC does not support 1000baseT_Half.
1214 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1216 return mii_ethtool_sset(&mp->mii, cmd);
1219 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1224 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1225 struct ethtool_drvinfo *drvinfo)
1227 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1228 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1229 strncpy(drvinfo->fw_version, "N/A", 32);
1230 strncpy(drvinfo->bus_info, "platform", 32);
1231 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1234 static int mv643xx_eth_nway_reset(struct net_device *dev)
1236 struct mv643xx_eth_private *mp = netdev_priv(dev);
1238 return mii_nway_restart(&mp->mii);
1241 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1246 static u32 mv643xx_eth_get_link(struct net_device *dev)
1248 struct mv643xx_eth_private *mp = netdev_priv(dev);
1250 return mii_link_ok(&mp->mii);
1253 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1258 static void mv643xx_eth_get_strings(struct net_device *dev,
1259 uint32_t stringset, uint8_t *data)
1263 if (stringset == ETH_SS_STATS) {
1264 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1265 memcpy(data + i * ETH_GSTRING_LEN,
1266 mv643xx_eth_stats[i].stat_string,
1272 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1273 struct ethtool_stats *stats,
1276 struct mv643xx_eth_private *mp = netdev_priv(dev);
1279 mib_counters_update(mp);
1281 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1282 const struct mv643xx_eth_stats *stat;
1285 stat = mv643xx_eth_stats + i;
1287 if (stat->netdev_off >= 0)
1288 p = ((void *)mp->dev) + stat->netdev_off;
1290 p = ((void *)mp) + stat->mp_off;
1292 data[i] = (stat->sizeof_stat == 8) ?
1293 *(uint64_t *)p : *(uint32_t *)p;
1297 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1299 if (sset == ETH_SS_STATS)
1300 return ARRAY_SIZE(mv643xx_eth_stats);
1305 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1306 .get_settings = mv643xx_eth_get_settings,
1307 .set_settings = mv643xx_eth_set_settings,
1308 .get_drvinfo = mv643xx_eth_get_drvinfo,
1309 .nway_reset = mv643xx_eth_nway_reset,
1310 .get_link = mv643xx_eth_get_link,
1311 .set_sg = ethtool_op_set_sg,
1312 .get_strings = mv643xx_eth_get_strings,
1313 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1314 .get_sset_count = mv643xx_eth_get_sset_count,
1317 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1318 .get_settings = mv643xx_eth_get_settings_phyless,
1319 .set_settings = mv643xx_eth_set_settings_phyless,
1320 .get_drvinfo = mv643xx_eth_get_drvinfo,
1321 .nway_reset = mv643xx_eth_nway_reset_phyless,
1322 .get_link = mv643xx_eth_get_link_phyless,
1323 .set_sg = ethtool_op_set_sg,
1324 .get_strings = mv643xx_eth_get_strings,
1325 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1326 .get_sset_count = mv643xx_eth_get_sset_count,
1330 /* address handling *********************************************************/
1331 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1336 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1337 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1339 addr[0] = (mac_h >> 24) & 0xff;
1340 addr[1] = (mac_h >> 16) & 0xff;
1341 addr[2] = (mac_h >> 8) & 0xff;
1342 addr[3] = mac_h & 0xff;
1343 addr[4] = (mac_l >> 8) & 0xff;
1344 addr[5] = mac_l & 0xff;
1347 static void init_mac_tables(struct mv643xx_eth_private *mp)
1351 for (i = 0; i < 0x100; i += 4) {
1352 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1353 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1356 for (i = 0; i < 0x10; i += 4)
1357 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1360 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1361 int table, unsigned char entry)
1363 unsigned int table_reg;
1365 /* Set "accepts frame bit" at specified table entry */
1366 table_reg = rdl(mp, table + (entry & 0xfc));
1367 table_reg |= 0x01 << (8 * (entry & 3));
1368 wrl(mp, table + (entry & 0xfc), table_reg);
1371 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1377 mac_l = (addr[4] << 8) | addr[5];
1378 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1380 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1381 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1383 table = UNICAST_TABLE(mp->port_num);
1384 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1387 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1389 struct mv643xx_eth_private *mp = netdev_priv(dev);
1391 /* +2 is for the offset of the HW addr type */
1392 memcpy(dev->dev_addr, addr + 2, 6);
1394 init_mac_tables(mp);
1395 uc_addr_set(mp, dev->dev_addr);
1400 static int addr_crc(unsigned char *addr)
1405 for (i = 0; i < 6; i++) {
1408 crc = (crc ^ addr[i]) << 8;
1409 for (j = 7; j >= 0; j--) {
1410 if (crc & (0x100 << j))
1418 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1420 struct mv643xx_eth_private *mp = netdev_priv(dev);
1422 struct dev_addr_list *addr;
1425 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1426 if (dev->flags & IFF_PROMISC)
1427 port_config |= UNICAST_PROMISCUOUS_MODE;
1429 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1430 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1432 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1433 int port_num = mp->port_num;
1434 u32 accept = 0x01010101;
1436 for (i = 0; i < 0x100; i += 4) {
1437 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1438 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1443 for (i = 0; i < 0x100; i += 4) {
1444 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1445 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1448 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1449 u8 *a = addr->da_addr;
1452 if (addr->da_addrlen != 6)
1455 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1456 table = SPECIAL_MCAST_TABLE(mp->port_num);
1457 set_filter_table_entry(mp, table, a[5]);
1459 int crc = addr_crc(a);
1461 table = OTHER_MCAST_TABLE(mp->port_num);
1462 set_filter_table_entry(mp, table, crc);
1468 /* rx/tx queue initialisation ***********************************************/
1469 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1471 struct rx_queue *rxq = mp->rxq + index;
1472 struct rx_desc *rx_desc;
1478 rxq->rx_ring_size = mp->default_rx_ring_size;
1480 rxq->rx_desc_count = 0;
1481 rxq->rx_curr_desc = 0;
1482 rxq->rx_used_desc = 0;
1484 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1486 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
1487 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1488 mp->rx_desc_sram_size);
1489 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1491 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1496 if (rxq->rx_desc_area == NULL) {
1497 dev_printk(KERN_ERR, &mp->dev->dev,
1498 "can't allocate rx ring (%d bytes)\n", size);
1501 memset(rxq->rx_desc_area, 0, size);
1503 rxq->rx_desc_area_size = size;
1504 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1506 if (rxq->rx_skb == NULL) {
1507 dev_printk(KERN_ERR, &mp->dev->dev,
1508 "can't allocate rx skb ring\n");
1512 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1513 for (i = 0; i < rxq->rx_ring_size; i++) {
1517 if (nexti == rxq->rx_ring_size)
1520 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1521 nexti * sizeof(struct rx_desc);
1524 init_timer(&rxq->rx_oom);
1525 rxq->rx_oom.data = (unsigned long)rxq;
1526 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1532 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
1533 iounmap(rxq->rx_desc_area);
1535 dma_free_coherent(NULL, size,
1543 static void rxq_deinit(struct rx_queue *rxq)
1545 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1550 del_timer_sync(&rxq->rx_oom);
1552 for (i = 0; i < rxq->rx_ring_size; i++) {
1553 if (rxq->rx_skb[i]) {
1554 dev_kfree_skb(rxq->rx_skb[i]);
1555 rxq->rx_desc_count--;
1559 if (rxq->rx_desc_count) {
1560 dev_printk(KERN_ERR, &mp->dev->dev,
1561 "error freeing rx ring -- %d skbs stuck\n",
1562 rxq->rx_desc_count);
1565 if (rxq->index == mp->rxq_primary &&
1566 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1567 iounmap(rxq->rx_desc_area);
1569 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1570 rxq->rx_desc_area, rxq->rx_desc_dma);
1575 static int txq_init(struct mv643xx_eth_private *mp, int index)
1577 struct tx_queue *txq = mp->txq + index;
1578 struct tx_desc *tx_desc;
1584 txq->tx_ring_size = mp->default_tx_ring_size;
1586 txq->tx_desc_count = 0;
1587 txq->tx_curr_desc = 0;
1588 txq->tx_used_desc = 0;
1590 size = txq->tx_ring_size * sizeof(struct tx_desc);
1592 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
1593 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1594 mp->tx_desc_sram_size);
1595 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1597 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1602 if (txq->tx_desc_area == NULL) {
1603 dev_printk(KERN_ERR, &mp->dev->dev,
1604 "can't allocate tx ring (%d bytes)\n", size);
1607 memset(txq->tx_desc_area, 0, size);
1609 txq->tx_desc_area_size = size;
1610 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1612 if (txq->tx_skb == NULL) {
1613 dev_printk(KERN_ERR, &mp->dev->dev,
1614 "can't allocate tx skb ring\n");
1618 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1619 for (i = 0; i < txq->tx_ring_size; i++) {
1620 struct tx_desc *txd = tx_desc + i;
1624 if (nexti == txq->tx_ring_size)
1628 txd->next_desc_ptr = txq->tx_desc_dma +
1629 nexti * sizeof(struct tx_desc);
1636 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
1637 iounmap(txq->tx_desc_area);
1639 dma_free_coherent(NULL, size,
1647 static void txq_reclaim(struct tx_queue *txq, int force)
1649 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1650 unsigned long flags;
1652 spin_lock_irqsave(&mp->lock, flags);
1653 while (txq->tx_desc_count > 0) {
1655 struct tx_desc *desc;
1657 struct sk_buff *skb;
1661 tx_index = txq->tx_used_desc;
1662 desc = &txq->tx_desc_area[tx_index];
1663 cmd_sts = desc->cmd_sts;
1665 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1668 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1671 txq->tx_used_desc = tx_index + 1;
1672 if (txq->tx_used_desc == txq->tx_ring_size)
1673 txq->tx_used_desc = 0;
1674 txq->tx_desc_count--;
1676 addr = desc->buf_ptr;
1677 count = desc->byte_cnt;
1678 skb = txq->tx_skb[tx_index];
1679 txq->tx_skb[tx_index] = NULL;
1681 if (cmd_sts & ERROR_SUMMARY) {
1682 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1683 mp->dev->stats.tx_errors++;
1687 * Drop mp->lock while we free the skb.
1689 spin_unlock_irqrestore(&mp->lock, flags);
1691 if (cmd_sts & TX_FIRST_DESC)
1692 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1694 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1697 dev_kfree_skb_irq(skb);
1699 spin_lock_irqsave(&mp->lock, flags);
1701 spin_unlock_irqrestore(&mp->lock, flags);
1704 static void txq_deinit(struct tx_queue *txq)
1706 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1709 txq_reclaim(txq, 1);
1711 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1713 if (txq->index == mp->txq_primary &&
1714 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1715 iounmap(txq->tx_desc_area);
1717 dma_free_coherent(NULL, txq->tx_desc_area_size,
1718 txq->tx_desc_area, txq->tx_desc_dma);
1724 /* netdev ops and related ***************************************************/
1725 static void handle_link_event(struct mv643xx_eth_private *mp)
1727 struct net_device *dev = mp->dev;
1733 port_status = rdl(mp, PORT_STATUS(mp->port_num));
1734 if (!(port_status & LINK_UP)) {
1735 if (netif_carrier_ok(dev)) {
1738 printk(KERN_INFO "%s: link down\n", dev->name);
1740 netif_carrier_off(dev);
1741 netif_stop_queue(dev);
1743 for (i = 0; i < 8; i++) {
1744 struct tx_queue *txq = mp->txq + i;
1746 if (mp->txq_mask & (1 << i)) {
1747 txq_reclaim(txq, 1);
1748 txq_reset_hw_ptr(txq);
1755 switch (port_status & PORT_SPEED_MASK) {
1759 case PORT_SPEED_100:
1762 case PORT_SPEED_1000:
1769 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
1770 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
1772 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
1773 "flow control %sabled\n", dev->name,
1774 speed, duplex ? "full" : "half",
1777 if (!netif_carrier_ok(dev)) {
1778 netif_carrier_on(dev);
1779 netif_wake_queue(dev);
1783 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1785 struct net_device *dev = (struct net_device *)dev_id;
1786 struct mv643xx_eth_private *mp = netdev_priv(dev);
1790 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1791 (INT_TX_END | INT_RX | INT_EXT);
1796 if (int_cause & INT_EXT) {
1797 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1798 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1799 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1802 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK))
1803 handle_link_event(mp);
1806 * RxBuffer or RxError set for any of the 8 queues?
1808 #ifdef MV643XX_ETH_NAPI
1809 if (int_cause & INT_RX) {
1810 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_RX));
1811 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1812 rdl(mp, INT_MASK(mp->port_num));
1814 netif_rx_schedule(dev, &mp->napi);
1817 if (int_cause & INT_RX) {
1820 for (i = 7; i >= 0; i--)
1821 if (mp->rxq_mask & (1 << i))
1822 rxq_process(mp->rxq + i, INT_MAX);
1827 * TxBuffer or TxError set for any of the 8 queues?
1829 if (int_cause_ext & INT_EXT_TX) {
1832 for (i = 0; i < 8; i++)
1833 if (mp->txq_mask & (1 << i))
1834 txq_reclaim(mp->txq + i, 0);
1837 * Enough space again in the primary TX queue for a
1840 if (netif_carrier_ok(dev)) {
1841 spin_lock(&mp->lock);
1842 __txq_maybe_wake(mp->txq + mp->txq_primary);
1843 spin_unlock(&mp->lock);
1848 * Any TxEnd interrupts?
1850 if (int_cause & INT_TX_END) {
1853 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1855 spin_lock(&mp->lock);
1856 for (i = 0; i < 8; i++) {
1857 struct tx_queue *txq = mp->txq + i;
1861 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1865 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1866 expected_ptr = (u32)txq->tx_desc_dma +
1867 txq->tx_curr_desc * sizeof(struct tx_desc);
1869 if (hw_desc_ptr != expected_ptr)
1872 spin_unlock(&mp->lock);
1878 static void phy_reset(struct mv643xx_eth_private *mp)
1882 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
1884 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
1888 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
1889 } while (data & BMCR_RESET);
1892 static void port_start(struct mv643xx_eth_private *mp)
1898 * Perform PHY reset, if there is a PHY.
1900 if (mp->phy_addr != -1) {
1901 struct ethtool_cmd cmd;
1903 mv643xx_eth_get_settings(mp->dev, &cmd);
1905 mv643xx_eth_set_settings(mp->dev, &cmd);
1909 * Configure basic link parameters.
1911 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1913 pscr |= SERIAL_PORT_ENABLE;
1914 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1916 pscr |= DO_NOT_FORCE_LINK_FAIL;
1917 if (mp->phy_addr == -1)
1918 pscr |= FORCE_LINK_PASS;
1919 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1921 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1924 * Configure TX path and queues.
1926 tx_set_rate(mp, 1000000000, 16777216);
1927 for (i = 0; i < 8; i++) {
1928 struct tx_queue *txq = mp->txq + i;
1930 if ((mp->txq_mask & (1 << i)) == 0)
1933 txq_reset_hw_ptr(txq);
1934 txq_set_rate(txq, 1000000000, 16777216);
1935 txq_set_fixed_prio_mode(txq);
1939 * Add configured unicast address to address filter table.
1941 uc_addr_set(mp, mp->dev->dev_addr);
1944 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1945 * frames to RX queue #0.
1947 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1950 * Treat BPDUs as normal multicasts, and disable partition mode.
1952 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1955 * Enable the receive queues.
1957 for (i = 0; i < 8; i++) {
1958 struct rx_queue *rxq = mp->rxq + i;
1959 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
1962 if ((mp->rxq_mask & (1 << i)) == 0)
1965 addr = (u32)rxq->rx_desc_dma;
1966 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1973 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1975 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1978 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1979 if (mp->shared->extended_rx_coal_limit) {
1983 val |= (coal & 0x8000) << 10;
1984 val |= (coal & 0x7fff) << 7;
1989 val |= (coal & 0x3fff) << 8;
1991 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1994 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1996 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
2000 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
2003 static int mv643xx_eth_open(struct net_device *dev)
2005 struct mv643xx_eth_private *mp = netdev_priv(dev);
2009 wrl(mp, INT_CAUSE(mp->port_num), 0);
2010 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
2011 rdl(mp, INT_CAUSE_EXT(mp->port_num));
2013 err = request_irq(dev->irq, mv643xx_eth_irq,
2014 IRQF_SHARED, dev->name, dev);
2016 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2020 init_mac_tables(mp);
2022 for (i = 0; i < 8; i++) {
2023 if ((mp->rxq_mask & (1 << i)) == 0)
2026 err = rxq_init(mp, i);
2029 if (mp->rxq_mask & (1 << i))
2030 rxq_deinit(mp->rxq + i);
2034 rxq_refill(mp->rxq + i);
2037 for (i = 0; i < 8; i++) {
2038 if ((mp->txq_mask & (1 << i)) == 0)
2041 err = txq_init(mp, i);
2044 if (mp->txq_mask & (1 << i))
2045 txq_deinit(mp->txq + i);
2050 #ifdef MV643XX_ETH_NAPI
2051 napi_enable(&mp->napi);
2054 netif_carrier_off(dev);
2055 netif_stop_queue(dev);
2062 wrl(mp, INT_MASK_EXT(mp->port_num),
2063 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
2065 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2071 for (i = 0; i < 8; i++)
2072 if (mp->rxq_mask & (1 << i))
2073 rxq_deinit(mp->rxq + i);
2075 free_irq(dev->irq, dev);
2080 static void port_reset(struct mv643xx_eth_private *mp)
2085 for (i = 0; i < 8; i++) {
2086 if (mp->rxq_mask & (1 << i))
2087 rxq_disable(mp->rxq + i);
2088 if (mp->txq_mask & (1 << i))
2089 txq_disable(mp->txq + i);
2093 u32 ps = rdl(mp, PORT_STATUS(mp->port_num));
2095 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2100 /* Reset the Enable bit in the Configuration Register */
2101 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2102 data &= ~(SERIAL_PORT_ENABLE |
2103 DO_NOT_FORCE_LINK_FAIL |
2105 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2108 static int mv643xx_eth_stop(struct net_device *dev)
2110 struct mv643xx_eth_private *mp = netdev_priv(dev);
2113 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2114 rdl(mp, INT_MASK(mp->port_num));
2116 #ifdef MV643XX_ETH_NAPI
2117 napi_disable(&mp->napi);
2119 netif_carrier_off(dev);
2120 netif_stop_queue(dev);
2122 free_irq(dev->irq, dev);
2125 mib_counters_update(mp);
2127 for (i = 0; i < 8; i++) {
2128 if (mp->rxq_mask & (1 << i))
2129 rxq_deinit(mp->rxq + i);
2130 if (mp->txq_mask & (1 << i))
2131 txq_deinit(mp->txq + i);
2137 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2139 struct mv643xx_eth_private *mp = netdev_priv(dev);
2141 if (mp->phy_addr != -1)
2142 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2147 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2149 struct mv643xx_eth_private *mp = netdev_priv(dev);
2151 if (new_mtu < 64 || new_mtu > 9500)
2155 tx_set_rate(mp, 1000000000, 16777216);
2157 if (!netif_running(dev))
2161 * Stop and then re-open the interface. This will allocate RX
2162 * skbs of the new MTU.
2163 * There is a possible danger that the open will not succeed,
2164 * due to memory being full.
2166 mv643xx_eth_stop(dev);
2167 if (mv643xx_eth_open(dev)) {
2168 dev_printk(KERN_ERR, &dev->dev,
2169 "fatal error on re-opening device after "
2176 static void tx_timeout_task(struct work_struct *ugly)
2178 struct mv643xx_eth_private *mp;
2180 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2181 if (netif_running(mp->dev)) {
2182 netif_stop_queue(mp->dev);
2187 __txq_maybe_wake(mp->txq + mp->txq_primary);
2191 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2193 struct mv643xx_eth_private *mp = netdev_priv(dev);
2195 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2197 schedule_work(&mp->tx_timeout_task);
2200 #ifdef CONFIG_NET_POLL_CONTROLLER
2201 static void mv643xx_eth_netpoll(struct net_device *dev)
2203 struct mv643xx_eth_private *mp = netdev_priv(dev);
2205 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2206 rdl(mp, INT_MASK(mp->port_num));
2208 mv643xx_eth_irq(dev->irq, dev);
2210 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2214 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2216 struct mv643xx_eth_private *mp = netdev_priv(dev);
2219 smi_reg_read(mp, addr, reg, &val);
2224 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2226 struct mv643xx_eth_private *mp = netdev_priv(dev);
2227 smi_reg_write(mp, addr, reg, val);
2231 /* platform glue ************************************************************/
2233 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2234 struct mbus_dram_target_info *dram)
2236 void __iomem *base = msp->base;
2241 for (i = 0; i < 6; i++) {
2242 writel(0, base + WINDOW_BASE(i));
2243 writel(0, base + WINDOW_SIZE(i));
2245 writel(0, base + WINDOW_REMAP_HIGH(i));
2251 for (i = 0; i < dram->num_cs; i++) {
2252 struct mbus_dram_window *cs = dram->cs + i;
2254 writel((cs->base & 0xffff0000) |
2255 (cs->mbus_attr << 8) |
2256 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2257 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2259 win_enable &= ~(1 << i);
2260 win_protect |= 3 << (2 * i);
2263 writel(win_enable, base + WINDOW_BAR_ENABLE);
2264 msp->win_protect = win_protect;
2267 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2270 * Check whether we have a 14-bit coal limit field in bits
2271 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2272 * SDMA config register.
2274 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2275 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2276 msp->extended_rx_coal_limit = 1;
2278 msp->extended_rx_coal_limit = 0;
2281 * Check whether the TX rate control registers are in the
2282 * old or the new place.
2284 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2285 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2286 msp->tx_bw_control_moved = 1;
2288 msp->tx_bw_control_moved = 0;
2291 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2293 static int mv643xx_eth_version_printed = 0;
2294 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2295 struct mv643xx_eth_shared_private *msp;
2296 struct resource *res;
2299 if (!mv643xx_eth_version_printed++)
2300 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2301 "driver version %s\n", mv643xx_eth_driver_version);
2304 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2309 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2312 memset(msp, 0, sizeof(*msp));
2314 msp->base = ioremap(res->start, res->end - res->start + 1);
2315 if (msp->base == NULL)
2318 mutex_init(&msp->phy_lock);
2321 * (Re-)program MBUS remapping windows if we are asked to.
2323 if (pd != NULL && pd->dram != NULL)
2324 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2327 * Detect hardware parameters.
2329 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2330 infer_hw_params(msp);
2332 platform_set_drvdata(pdev, msp);
2342 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2344 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2352 static struct platform_driver mv643xx_eth_shared_driver = {
2353 .probe = mv643xx_eth_shared_probe,
2354 .remove = mv643xx_eth_shared_remove,
2356 .name = MV643XX_ETH_SHARED_NAME,
2357 .owner = THIS_MODULE,
2361 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2363 int addr_shift = 5 * mp->port_num;
2366 data = rdl(mp, PHY_ADDR);
2367 data &= ~(0x1f << addr_shift);
2368 data |= (phy_addr & 0x1f) << addr_shift;
2369 wrl(mp, PHY_ADDR, data);
2372 static int phy_addr_get(struct mv643xx_eth_private *mp)
2376 data = rdl(mp, PHY_ADDR);
2378 return (data >> (5 * mp->port_num)) & 0x1f;
2381 static void set_params(struct mv643xx_eth_private *mp,
2382 struct mv643xx_eth_platform_data *pd)
2384 struct net_device *dev = mp->dev;
2386 if (is_valid_ether_addr(pd->mac_addr))
2387 memcpy(dev->dev_addr, pd->mac_addr, 6);
2389 uc_addr_get(mp, dev->dev_addr);
2391 if (pd->phy_addr == -1) {
2392 mp->shared_smi = NULL;
2395 mp->shared_smi = mp->shared;
2396 if (pd->shared_smi != NULL)
2397 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2399 if (pd->force_phy_addr || pd->phy_addr) {
2400 mp->phy_addr = pd->phy_addr & 0x3f;
2401 phy_addr_set(mp, mp->phy_addr);
2403 mp->phy_addr = phy_addr_get(mp);
2407 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2408 if (pd->rx_queue_size)
2409 mp->default_rx_ring_size = pd->rx_queue_size;
2410 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2411 mp->rx_desc_sram_size = pd->rx_sram_size;
2413 if (pd->rx_queue_mask)
2414 mp->rxq_mask = pd->rx_queue_mask;
2416 mp->rxq_mask = 0x01;
2417 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2419 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2420 if (pd->tx_queue_size)
2421 mp->default_tx_ring_size = pd->tx_queue_size;
2422 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2423 mp->tx_desc_sram_size = pd->tx_sram_size;
2425 if (pd->tx_queue_mask)
2426 mp->txq_mask = pd->tx_queue_mask;
2428 mp->txq_mask = 0x01;
2429 mp->txq_primary = fls(mp->txq_mask) - 1;
2432 static int phy_detect(struct mv643xx_eth_private *mp)
2437 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data);
2438 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data ^ BMCR_ANENABLE);
2440 smi_reg_read(mp, mp->phy_addr, MII_BMCR, &data2);
2441 if (((data ^ data2) & BMCR_ANENABLE) == 0)
2444 smi_reg_write(mp, mp->phy_addr, MII_BMCR, data);
2449 static int phy_init(struct mv643xx_eth_private *mp,
2450 struct mv643xx_eth_platform_data *pd)
2452 struct ethtool_cmd cmd;
2455 err = phy_detect(mp);
2457 dev_printk(KERN_INFO, &mp->dev->dev,
2458 "no PHY detected at addr %d\n", mp->phy_addr);
2463 mp->mii.phy_id = mp->phy_addr;
2464 mp->mii.phy_id_mask = 0x3f;
2465 mp->mii.reg_num_mask = 0x1f;
2466 mp->mii.dev = mp->dev;
2467 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2468 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2470 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2472 memset(&cmd, 0, sizeof(cmd));
2474 cmd.port = PORT_MII;
2475 cmd.transceiver = XCVR_INTERNAL;
2476 cmd.phy_address = mp->phy_addr;
2477 if (pd->speed == 0) {
2478 cmd.autoneg = AUTONEG_ENABLE;
2479 cmd.speed = SPEED_100;
2480 cmd.advertising = ADVERTISED_10baseT_Half |
2481 ADVERTISED_10baseT_Full |
2482 ADVERTISED_100baseT_Half |
2483 ADVERTISED_100baseT_Full;
2484 if (mp->mii.supports_gmii)
2485 cmd.advertising |= ADVERTISED_1000baseT_Full;
2487 cmd.autoneg = AUTONEG_DISABLE;
2488 cmd.speed = pd->speed;
2489 cmd.duplex = pd->duplex;
2492 mv643xx_eth_set_settings(mp->dev, &cmd);
2497 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2501 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2502 if (pscr & SERIAL_PORT_ENABLE) {
2503 pscr &= ~SERIAL_PORT_ENABLE;
2504 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2507 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2508 if (mp->phy_addr == -1) {
2509 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2510 if (speed == SPEED_1000)
2511 pscr |= SET_GMII_SPEED_TO_1000;
2512 else if (speed == SPEED_100)
2513 pscr |= SET_MII_SPEED_TO_100;
2515 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2517 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2518 if (duplex == DUPLEX_FULL)
2519 pscr |= SET_FULL_DUPLEX_MODE;
2522 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
2525 static int mv643xx_eth_probe(struct platform_device *pdev)
2527 struct mv643xx_eth_platform_data *pd;
2528 struct mv643xx_eth_private *mp;
2529 struct net_device *dev;
2530 struct resource *res;
2531 DECLARE_MAC_BUF(mac);
2534 pd = pdev->dev.platform_data;
2536 dev_printk(KERN_ERR, &pdev->dev,
2537 "no mv643xx_eth_platform_data\n");
2541 if (pd->shared == NULL) {
2542 dev_printk(KERN_ERR, &pdev->dev,
2543 "no mv643xx_eth_platform_data->shared\n");
2547 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2551 mp = netdev_priv(dev);
2552 platform_set_drvdata(pdev, mp);
2554 mp->shared = platform_get_drvdata(pd->shared);
2555 mp->port_num = pd->port_number;
2558 #ifdef MV643XX_ETH_NAPI
2559 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2564 spin_lock_init(&mp->lock);
2566 mib_counters_clear(mp);
2567 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2569 if (mp->phy_addr != -1) {
2570 err = phy_init(mp, pd);
2574 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2576 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2578 init_pscr(mp, pd->speed, pd->duplex);
2581 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2583 dev->irq = res->start;
2585 dev->hard_start_xmit = mv643xx_eth_xmit;
2586 dev->open = mv643xx_eth_open;
2587 dev->stop = mv643xx_eth_stop;
2588 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2589 dev->set_mac_address = mv643xx_eth_set_mac_address;
2590 dev->do_ioctl = mv643xx_eth_ioctl;
2591 dev->change_mtu = mv643xx_eth_change_mtu;
2592 dev->tx_timeout = mv643xx_eth_tx_timeout;
2593 #ifdef CONFIG_NET_POLL_CONTROLLER
2594 dev->poll_controller = mv643xx_eth_netpoll;
2596 dev->watchdog_timeo = 2 * HZ;
2599 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2601 * Zero copy can only work if we use Discovery II memory. Else, we will
2602 * have to map the buffers to ISA memory which is only 16 MB
2604 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2605 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2608 SET_NETDEV_DEV(dev, &pdev->dev);
2610 if (mp->shared->win_protect)
2611 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2613 err = register_netdev(dev);
2617 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2618 mp->port_num, print_mac(mac, dev->dev_addr));
2620 if (dev->features & NETIF_F_SG)
2621 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
2623 if (dev->features & NETIF_F_IP_CSUM)
2624 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
2626 #ifdef MV643XX_ETH_NAPI
2627 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
2630 if (mp->tx_desc_sram_size > 0)
2631 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2641 static int mv643xx_eth_remove(struct platform_device *pdev)
2643 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2645 unregister_netdev(mp->dev);
2646 flush_scheduled_work();
2647 free_netdev(mp->dev);
2649 platform_set_drvdata(pdev, NULL);
2654 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2656 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2658 /* Mask all interrupts on ethernet port */
2659 wrl(mp, INT_MASK(mp->port_num), 0);
2660 rdl(mp, INT_MASK(mp->port_num));
2662 if (netif_running(mp->dev))
2666 static struct platform_driver mv643xx_eth_driver = {
2667 .probe = mv643xx_eth_probe,
2668 .remove = mv643xx_eth_remove,
2669 .shutdown = mv643xx_eth_shutdown,
2671 .name = MV643XX_ETH_NAME,
2672 .owner = THIS_MODULE,
2676 static int __init mv643xx_eth_init_module(void)
2680 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2682 rc = platform_driver_register(&mv643xx_eth_driver);
2684 platform_driver_unregister(&mv643xx_eth_shared_driver);
2689 module_init(mv643xx_eth_init_module);
2691 static void __exit mv643xx_eth_cleanup_module(void)
2693 platform_driver_unregister(&mv643xx_eth_driver);
2694 platform_driver_unregister(&mv643xx_eth_shared_driver);
2696 module_exit(mv643xx_eth_cleanup_module);
2698 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2699 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2700 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2701 MODULE_LICENSE("GPL");
2702 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2703 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);