2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.1";
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_NAPI
62 #define MV643XX_ETH_TX_FAST_REFILL
64 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
65 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
67 #define MAX_DESCS_PER_SKB 1
71 * Registers shared between all ports.
73 #define PHY_ADDR 0x0000
74 #define SMI_REG 0x0004
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
84 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
85 #define UNICAST_PROMISCUOUS_MODE 0x00000001
86 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
87 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
88 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
89 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
90 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
91 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
92 #define TX_FIFO_EMPTY 0x00000400
93 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
94 #define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
95 #define TX_BW_RATE(p) (0x0450 + ((p) << 10))
96 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
97 #define TX_BW_BURST(p) (0x045c + ((p) << 10))
98 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
99 #define INT_TX_END_0 0x00080000
100 #define INT_TX_END 0x07f80000
101 #define INT_RX 0x0007fbfc
102 #define INT_EXT 0x00000002
103 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
104 #define INT_EXT_LINK 0x00100000
105 #define INT_EXT_PHY 0x00010000
106 #define INT_EXT_TX_ERROR_0 0x00000100
107 #define INT_EXT_TX_0 0x00000001
108 #define INT_EXT_TX 0x0000ffff
109 #define INT_MASK(p) (0x0468 + ((p) << 10))
110 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
111 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
112 #define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
113 #define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
114 #define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
115 #define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
116 #define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
117 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
118 #define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
119 #define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
120 #define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
121 #define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
122 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
123 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
124 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
125 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
129 * SDMA configuration register.
131 #define RX_BURST_SIZE_4_64BIT (2 << 1)
132 #define BLM_RX_NO_SWAP (1 << 4)
133 #define BLM_TX_NO_SWAP (1 << 5)
134 #define TX_BURST_SIZE_4_64BIT (2 << 22)
136 #if defined(__BIG_ENDIAN)
137 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
138 RX_BURST_SIZE_4_64BIT | \
139 TX_BURST_SIZE_4_64BIT
140 #elif defined(__LITTLE_ENDIAN)
141 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
142 RX_BURST_SIZE_4_64BIT | \
145 TX_BURST_SIZE_4_64BIT
147 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
152 * Port serial control register.
154 #define SET_MII_SPEED_TO_100 (1 << 24)
155 #define SET_GMII_SPEED_TO_1000 (1 << 23)
156 #define SET_FULL_DUPLEX_MODE (1 << 21)
157 #define MAX_RX_PACKET_9700BYTE (5 << 17)
158 #define MAX_RX_PACKET_MASK (7 << 17)
159 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
160 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
161 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
162 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
163 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
164 #define FORCE_LINK_PASS (1 << 1)
165 #define SERIAL_PORT_ENABLE (1 << 0)
167 #define DEFAULT_RX_QUEUE_SIZE 400
168 #define DEFAULT_TX_QUEUE_SIZE 800
174 #if defined(__BIG_ENDIAN)
176 u16 byte_cnt; /* Descriptor buffer byte count */
177 u16 buf_size; /* Buffer size */
178 u32 cmd_sts; /* Descriptor command status */
179 u32 next_desc_ptr; /* Next descriptor pointer */
180 u32 buf_ptr; /* Descriptor buffer pointer */
184 u16 byte_cnt; /* buffer byte count */
185 u16 l4i_chk; /* CPU provided TCP checksum */
186 u32 cmd_sts; /* Command/status field */
187 u32 next_desc_ptr; /* Pointer to next descriptor */
188 u32 buf_ptr; /* pointer to buffer for this descriptor*/
190 #elif defined(__LITTLE_ENDIAN)
192 u32 cmd_sts; /* Descriptor command status */
193 u16 buf_size; /* Buffer size */
194 u16 byte_cnt; /* Descriptor buffer byte count */
195 u32 buf_ptr; /* Descriptor buffer pointer */
196 u32 next_desc_ptr; /* Next descriptor pointer */
200 u32 cmd_sts; /* Command/status field */
201 u16 l4i_chk; /* CPU provided TCP checksum */
202 u16 byte_cnt; /* buffer byte count */
203 u32 buf_ptr; /* pointer to buffer for this descriptor*/
204 u32 next_desc_ptr; /* Pointer to next descriptor */
207 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
210 /* RX & TX descriptor command */
211 #define BUFFER_OWNED_BY_DMA 0x80000000
213 /* RX & TX descriptor status */
214 #define ERROR_SUMMARY 0x00000001
216 /* RX descriptor status */
217 #define LAYER_4_CHECKSUM_OK 0x40000000
218 #define RX_ENABLE_INTERRUPT 0x20000000
219 #define RX_FIRST_DESC 0x08000000
220 #define RX_LAST_DESC 0x04000000
222 /* TX descriptor command */
223 #define TX_ENABLE_INTERRUPT 0x00800000
224 #define GEN_CRC 0x00400000
225 #define TX_FIRST_DESC 0x00200000
226 #define TX_LAST_DESC 0x00100000
227 #define ZERO_PADDING 0x00080000
228 #define GEN_IP_V4_CHECKSUM 0x00040000
229 #define GEN_TCP_UDP_CHECKSUM 0x00020000
230 #define UDP_FRAME 0x00010000
232 #define TX_IHL_SHIFT 11
235 /* global *******************************************************************/
236 struct mv643xx_eth_shared_private {
238 * Ethernet controller base address.
243 * Protects access to SMI_REG, which is shared between ports.
248 * Per-port MBUS window access register value.
253 * Hardware-specific parameters.
256 int extended_rx_coal_limit;
257 int tx_bw_control_moved;
261 /* per-port *****************************************************************/
262 struct mib_counters {
263 u64 good_octets_received;
264 u32 bad_octets_received;
265 u32 internal_mac_transmit_err;
266 u32 good_frames_received;
267 u32 bad_frames_received;
268 u32 broadcast_frames_received;
269 u32 multicast_frames_received;
270 u32 frames_64_octets;
271 u32 frames_65_to_127_octets;
272 u32 frames_128_to_255_octets;
273 u32 frames_256_to_511_octets;
274 u32 frames_512_to_1023_octets;
275 u32 frames_1024_to_max_octets;
276 u64 good_octets_sent;
277 u32 good_frames_sent;
278 u32 excessive_collision;
279 u32 multicast_frames_sent;
280 u32 broadcast_frames_sent;
281 u32 unrec_mac_control_received;
283 u32 good_fc_received;
285 u32 undersize_received;
286 u32 fragments_received;
287 u32 oversize_received;
289 u32 mac_receive_error;
304 struct rx_desc *rx_desc_area;
305 dma_addr_t rx_desc_dma;
306 int rx_desc_area_size;
307 struct sk_buff **rx_skb;
309 struct timer_list rx_oom;
321 struct tx_desc *tx_desc_area;
322 dma_addr_t tx_desc_dma;
323 int tx_desc_area_size;
324 struct sk_buff **tx_skb;
327 struct mv643xx_eth_private {
328 struct mv643xx_eth_shared_private *shared;
331 struct net_device *dev;
333 struct mv643xx_eth_shared_private *shared_smi;
338 struct mib_counters mib_counters;
339 struct work_struct tx_timeout_task;
340 struct mii_if_info mii;
345 int default_rx_ring_size;
346 unsigned long rx_desc_sram_addr;
347 int rx_desc_sram_size;
350 struct napi_struct napi;
351 struct rx_queue rxq[8];
356 int default_tx_ring_size;
357 unsigned long tx_desc_sram_addr;
358 int tx_desc_sram_size;
361 struct tx_queue txq[8];
362 #ifdef MV643XX_ETH_TX_FAST_REFILL
363 int tx_clean_threshold;
368 /* port register accessors **************************************************/
369 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
371 return readl(mp->shared->base + offset);
374 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
376 writel(data, mp->shared->base + offset);
380 /* rxq/txq helper functions *************************************************/
381 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
383 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
386 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
388 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
391 static void rxq_enable(struct rx_queue *rxq)
393 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
394 wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
397 static void rxq_disable(struct rx_queue *rxq)
399 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
400 u8 mask = 1 << rxq->index;
402 wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
403 while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
407 static void txq_reset_hw_ptr(struct tx_queue *txq)
409 struct mv643xx_eth_private *mp = txq_to_mp(txq);
410 int off = TXQ_CURRENT_DESC_PTR(mp->port_num, txq->index);
413 addr = (u32)txq->tx_desc_dma;
414 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
418 static void txq_enable(struct tx_queue *txq)
420 struct mv643xx_eth_private *mp = txq_to_mp(txq);
421 wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
424 static void txq_disable(struct tx_queue *txq)
426 struct mv643xx_eth_private *mp = txq_to_mp(txq);
427 u8 mask = 1 << txq->index;
429 wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
430 while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
434 static void __txq_maybe_wake(struct tx_queue *txq)
436 struct mv643xx_eth_private *mp = txq_to_mp(txq);
439 * netif_{stop,wake}_queue() flow control only applies to
442 BUG_ON(txq->index != mp->txq_primary);
444 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
445 netif_wake_queue(mp->dev);
449 /* rx ***********************************************************************/
450 static void txq_reclaim(struct tx_queue *txq, int force);
452 static void rxq_refill(struct rx_queue *rxq)
454 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
457 spin_lock_irqsave(&mp->lock, flags);
459 while (rxq->rx_desc_count < rxq->rx_ring_size) {
466 * Reserve 2+14 bytes for an ethernet header (the
467 * hardware automatically prepends 2 bytes of dummy
468 * data to each received packet), 4 bytes for a VLAN
469 * header, and 4 bytes for the trailing FCS -- 24
472 skb_size = mp->dev->mtu + 24;
474 skb = dev_alloc_skb(skb_size + dma_get_cache_alignment() - 1);
478 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
480 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
482 rxq->rx_desc_count++;
483 rx = rxq->rx_used_desc;
484 rxq->rx_used_desc = (rx + 1) % rxq->rx_ring_size;
486 rxq->rx_desc_area[rx].buf_ptr = dma_map_single(NULL, skb->data,
487 skb_size, DMA_FROM_DEVICE);
488 rxq->rx_desc_area[rx].buf_size = skb_size;
489 rxq->rx_skb[rx] = skb;
491 rxq->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
496 * The hardware automatically prepends 2 bytes of
497 * dummy data to each received packet, so that the
498 * IP header ends up 16-byte aligned.
503 if (rxq->rx_desc_count != rxq->rx_ring_size) {
504 rxq->rx_oom.expires = jiffies + (HZ / 10);
505 add_timer(&rxq->rx_oom);
508 spin_unlock_irqrestore(&mp->lock, flags);
511 static inline void rxq_refill_timer_wrapper(unsigned long data)
513 rxq_refill((struct rx_queue *)data);
516 static int rxq_process(struct rx_queue *rxq, int budget)
518 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
519 struct net_device_stats *stats = &mp->dev->stats;
523 while (rx < budget) {
524 struct rx_desc *rx_desc;
525 unsigned int cmd_sts;
529 spin_lock_irqsave(&mp->lock, flags);
531 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
533 cmd_sts = rx_desc->cmd_sts;
534 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
535 spin_unlock_irqrestore(&mp->lock, flags);
540 skb = rxq->rx_skb[rxq->rx_curr_desc];
541 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
543 rxq->rx_curr_desc = (rxq->rx_curr_desc + 1) % rxq->rx_ring_size;
545 spin_unlock_irqrestore(&mp->lock, flags);
547 dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
548 mp->dev->mtu + 24, DMA_FROM_DEVICE);
549 rxq->rx_desc_count--;
555 * Note that the descriptor byte count includes 2 dummy
556 * bytes automatically inserted by the hardware at the
557 * start of the packet (which we don't count), and a 4
558 * byte CRC at the end of the packet (which we do count).
561 stats->rx_bytes += rx_desc->byte_cnt - 2;
564 * In case we received a packet without first / last bits
565 * on, or the error summary bit is set, the packet needs
568 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
569 (RX_FIRST_DESC | RX_LAST_DESC))
570 || (cmd_sts & ERROR_SUMMARY)) {
573 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
574 (RX_FIRST_DESC | RX_LAST_DESC)) {
576 dev_printk(KERN_ERR, &mp->dev->dev,
577 "received packet spanning "
578 "multiple descriptors\n");
581 if (cmd_sts & ERROR_SUMMARY)
584 dev_kfree_skb_irq(skb);
587 * The -4 is for the CRC in the trailer of the
590 skb_put(skb, rx_desc->byte_cnt - 2 - 4);
592 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
593 skb->ip_summed = CHECKSUM_UNNECESSARY;
595 (cmd_sts & 0x0007fff8) >> 3);
597 skb->protocol = eth_type_trans(skb, mp->dev);
598 #ifdef MV643XX_ETH_NAPI
599 netif_receive_skb(skb);
605 mp->dev->last_rx = jiffies;
613 #ifdef MV643XX_ETH_NAPI
614 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
616 struct mv643xx_eth_private *mp;
620 mp = container_of(napi, struct mv643xx_eth_private, napi);
622 #ifdef MV643XX_ETH_TX_FAST_REFILL
623 if (++mp->tx_clean_threshold > 5) {
624 mp->tx_clean_threshold = 0;
625 for (i = 0; i < 8; i++)
626 if (mp->txq_mask & (1 << i))
627 txq_reclaim(mp->txq + i, 0);
629 if (netif_carrier_ok(mp->dev)) {
630 spin_lock(&mp->lock);
631 __txq_maybe_wake(mp->txq + mp->txq_primary);
632 spin_unlock(&mp->lock);
638 for (i = 7; rx < budget && i >= 0; i--)
639 if (mp->rxq_mask & (1 << i))
640 rx += rxq_process(mp->rxq + i, budget - rx);
643 netif_rx_complete(mp->dev, napi);
644 wrl(mp, INT_CAUSE(mp->port_num), 0);
645 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
646 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
654 /* tx ***********************************************************************/
655 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
659 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
660 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
661 if (fragp->size <= 8 && fragp->page_offset & 7)
668 static int txq_alloc_desc_index(struct tx_queue *txq)
672 BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
674 tx_desc_curr = txq->tx_curr_desc;
675 txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
677 BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
682 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
684 int nr_frags = skb_shinfo(skb)->nr_frags;
687 for (frag = 0; frag < nr_frags; frag++) {
688 skb_frag_t *this_frag;
690 struct tx_desc *desc;
692 this_frag = &skb_shinfo(skb)->frags[frag];
693 tx_index = txq_alloc_desc_index(txq);
694 desc = &txq->tx_desc_area[tx_index];
697 * The last fragment will generate an interrupt
698 * which will free the skb on TX completion.
700 if (frag == nr_frags - 1) {
701 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
702 ZERO_PADDING | TX_LAST_DESC |
704 txq->tx_skb[tx_index] = skb;
706 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
707 txq->tx_skb[tx_index] = NULL;
711 desc->byte_cnt = this_frag->size;
712 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
713 this_frag->page_offset,
719 static inline __be16 sum16_as_be(__sum16 sum)
721 return (__force __be16)sum;
724 static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
726 struct mv643xx_eth_private *mp = txq_to_mp(txq);
727 int nr_frags = skb_shinfo(skb)->nr_frags;
729 struct tx_desc *desc;
733 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
735 tx_index = txq_alloc_desc_index(txq);
736 desc = &txq->tx_desc_area[tx_index];
739 txq_submit_frag_skb(txq, skb);
741 length = skb_headlen(skb);
742 txq->tx_skb[tx_index] = NULL;
744 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
746 txq->tx_skb[tx_index] = skb;
749 desc->byte_cnt = length;
750 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
752 if (skb->ip_summed == CHECKSUM_PARTIAL) {
753 BUG_ON(skb->protocol != htons(ETH_P_IP));
755 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
757 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
759 switch (ip_hdr(skb)->protocol) {
761 cmd_sts |= UDP_FRAME;
762 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
765 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
771 /* Errata BTS #50, IHL must be 5 if no HW checksum */
772 cmd_sts |= 5 << TX_IHL_SHIFT;
776 /* ensure all other descriptors are written before first cmd_sts */
778 desc->cmd_sts = cmd_sts;
780 /* clear TX_END interrupt status */
781 wrl(mp, INT_CAUSE(mp->port_num), ~(INT_TX_END_0 << txq->index));
782 rdl(mp, INT_CAUSE(mp->port_num));
784 /* ensure all descriptors are written before poking hardware */
788 txq->tx_desc_count += nr_frags + 1;
791 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
793 struct mv643xx_eth_private *mp = netdev_priv(dev);
794 struct net_device_stats *stats = &dev->stats;
795 struct tx_queue *txq;
798 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
800 dev_printk(KERN_DEBUG, &dev->dev,
801 "failed to linearize skb with tiny "
802 "unaligned fragment\n");
803 return NETDEV_TX_BUSY;
806 spin_lock_irqsave(&mp->lock, flags);
808 txq = mp->txq + mp->txq_primary;
810 if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
811 spin_unlock_irqrestore(&mp->lock, flags);
812 if (txq->index == mp->txq_primary && net_ratelimit())
813 dev_printk(KERN_ERR, &dev->dev,
814 "primary tx queue full?!\n");
819 txq_submit_skb(txq, skb);
820 stats->tx_bytes += skb->len;
822 dev->trans_start = jiffies;
824 if (txq->index == mp->txq_primary) {
827 entries_left = txq->tx_ring_size - txq->tx_desc_count;
828 if (entries_left < MAX_DESCS_PER_SKB)
829 netif_stop_queue(dev);
832 spin_unlock_irqrestore(&mp->lock, flags);
838 /* tx rate control **********************************************************/
840 * Set total maximum TX rate (shared by all TX queues for this port)
841 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
843 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
849 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
850 if (token_rate > 1023)
853 mtu = (mp->dev->mtu + 255) >> 8;
857 bucket_size = (burst + 255) >> 8;
858 if (bucket_size > 65535)
861 if (mp->shared->tx_bw_control_moved) {
862 wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
863 wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
864 wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
866 wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
867 wrl(mp, TX_BW_MTU(mp->port_num), mtu);
868 wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
872 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
874 struct mv643xx_eth_private *mp = txq_to_mp(txq);
878 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
879 if (token_rate > 1023)
882 bucket_size = (burst + 255) >> 8;
883 if (bucket_size > 65535)
886 wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
887 wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
888 (bucket_size << 10) | token_rate);
891 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
893 struct mv643xx_eth_private *mp = txq_to_mp(txq);
898 * Turn on fixed priority mode.
900 if (mp->shared->tx_bw_control_moved)
901 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
903 off = TXQ_FIX_PRIO_CONF(mp->port_num);
906 val |= 1 << txq->index;
910 static void txq_set_wrr(struct tx_queue *txq, int weight)
912 struct mv643xx_eth_private *mp = txq_to_mp(txq);
917 * Turn off fixed priority mode.
919 if (mp->shared->tx_bw_control_moved)
920 off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
922 off = TXQ_FIX_PRIO_CONF(mp->port_num);
925 val &= ~(1 << txq->index);
929 * Configure WRR weight for this queue.
931 off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
934 val = (val & ~0xff) | (weight & 0xff);
939 /* mii management interface *************************************************/
940 #define SMI_BUSY 0x10000000
941 #define SMI_READ_VALID 0x08000000
942 #define SMI_OPCODE_READ 0x04000000
943 #define SMI_OPCODE_WRITE 0x00000000
945 static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
946 unsigned int reg, unsigned int *value)
948 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
952 /* the SMI register is a shared resource */
953 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
955 /* wait for the SMI register to become available */
956 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
958 printk("%s: PHY busy timeout\n", mp->dev->name);
964 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
966 /* now wait for the data to be valid */
967 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
969 printk("%s: PHY read timeout\n", mp->dev->name);
975 *value = readl(smi_reg) & 0xffff;
977 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
980 static void smi_reg_write(struct mv643xx_eth_private *mp,
982 unsigned int reg, unsigned int value)
984 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
988 /* the SMI register is a shared resource */
989 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
991 /* wait for the SMI register to become available */
992 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
994 printk("%s: PHY busy timeout\n", mp->dev->name);
1000 writel(SMI_OPCODE_WRITE | (reg << 21) |
1001 (addr << 16) | (value & 0xffff), smi_reg);
1003 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
1007 /* mib counters *************************************************************/
1008 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1010 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1013 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1017 for (i = 0; i < 0x80; i += 4)
1021 static void mib_counters_update(struct mv643xx_eth_private *mp)
1023 struct mib_counters *p = &mp->mib_counters;
1025 p->good_octets_received += mib_read(mp, 0x00);
1026 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1027 p->bad_octets_received += mib_read(mp, 0x08);
1028 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1029 p->good_frames_received += mib_read(mp, 0x10);
1030 p->bad_frames_received += mib_read(mp, 0x14);
1031 p->broadcast_frames_received += mib_read(mp, 0x18);
1032 p->multicast_frames_received += mib_read(mp, 0x1c);
1033 p->frames_64_octets += mib_read(mp, 0x20);
1034 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1035 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1036 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1037 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1038 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1039 p->good_octets_sent += mib_read(mp, 0x38);
1040 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1041 p->good_frames_sent += mib_read(mp, 0x40);
1042 p->excessive_collision += mib_read(mp, 0x44);
1043 p->multicast_frames_sent += mib_read(mp, 0x48);
1044 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1045 p->unrec_mac_control_received += mib_read(mp, 0x50);
1046 p->fc_sent += mib_read(mp, 0x54);
1047 p->good_fc_received += mib_read(mp, 0x58);
1048 p->bad_fc_received += mib_read(mp, 0x5c);
1049 p->undersize_received += mib_read(mp, 0x60);
1050 p->fragments_received += mib_read(mp, 0x64);
1051 p->oversize_received += mib_read(mp, 0x68);
1052 p->jabber_received += mib_read(mp, 0x6c);
1053 p->mac_receive_error += mib_read(mp, 0x70);
1054 p->bad_crc_event += mib_read(mp, 0x74);
1055 p->collision += mib_read(mp, 0x78);
1056 p->late_collision += mib_read(mp, 0x7c);
1060 /* ethtool ******************************************************************/
1061 struct mv643xx_eth_stats {
1062 char stat_string[ETH_GSTRING_LEN];
1069 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1070 offsetof(struct net_device, stats.m), -1 }
1072 #define MIBSTAT(m) \
1073 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1074 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1076 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1085 MIBSTAT(good_octets_received),
1086 MIBSTAT(bad_octets_received),
1087 MIBSTAT(internal_mac_transmit_err),
1088 MIBSTAT(good_frames_received),
1089 MIBSTAT(bad_frames_received),
1090 MIBSTAT(broadcast_frames_received),
1091 MIBSTAT(multicast_frames_received),
1092 MIBSTAT(frames_64_octets),
1093 MIBSTAT(frames_65_to_127_octets),
1094 MIBSTAT(frames_128_to_255_octets),
1095 MIBSTAT(frames_256_to_511_octets),
1096 MIBSTAT(frames_512_to_1023_octets),
1097 MIBSTAT(frames_1024_to_max_octets),
1098 MIBSTAT(good_octets_sent),
1099 MIBSTAT(good_frames_sent),
1100 MIBSTAT(excessive_collision),
1101 MIBSTAT(multicast_frames_sent),
1102 MIBSTAT(broadcast_frames_sent),
1103 MIBSTAT(unrec_mac_control_received),
1105 MIBSTAT(good_fc_received),
1106 MIBSTAT(bad_fc_received),
1107 MIBSTAT(undersize_received),
1108 MIBSTAT(fragments_received),
1109 MIBSTAT(oversize_received),
1110 MIBSTAT(jabber_received),
1111 MIBSTAT(mac_receive_error),
1112 MIBSTAT(bad_crc_event),
1114 MIBSTAT(late_collision),
1117 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1119 struct mv643xx_eth_private *mp = netdev_priv(dev);
1122 spin_lock_irq(&mp->lock);
1123 err = mii_ethtool_gset(&mp->mii, cmd);
1124 spin_unlock_irq(&mp->lock);
1127 * The MAC does not support 1000baseT_Half.
1129 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1130 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1135 static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1137 cmd->supported = SUPPORTED_MII;
1138 cmd->advertising = ADVERTISED_MII;
1139 cmd->speed = SPEED_1000;
1140 cmd->duplex = DUPLEX_FULL;
1141 cmd->port = PORT_MII;
1142 cmd->phy_address = 0;
1143 cmd->transceiver = XCVR_INTERNAL;
1144 cmd->autoneg = AUTONEG_DISABLE;
1151 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1153 struct mv643xx_eth_private *mp = netdev_priv(dev);
1157 * The MAC does not support 1000baseT_Half.
1159 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1161 spin_lock_irq(&mp->lock);
1162 err = mii_ethtool_sset(&mp->mii, cmd);
1163 spin_unlock_irq(&mp->lock);
1168 static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
1173 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1174 struct ethtool_drvinfo *drvinfo)
1176 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1177 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1178 strncpy(drvinfo->fw_version, "N/A", 32);
1179 strncpy(drvinfo->bus_info, "platform", 32);
1180 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1183 static int mv643xx_eth_nway_reset(struct net_device *dev)
1185 struct mv643xx_eth_private *mp = netdev_priv(dev);
1187 return mii_nway_restart(&mp->mii);
1190 static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
1195 static u32 mv643xx_eth_get_link(struct net_device *dev)
1197 struct mv643xx_eth_private *mp = netdev_priv(dev);
1199 return mii_link_ok(&mp->mii);
1202 static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
1207 static void mv643xx_eth_get_strings(struct net_device *dev,
1208 uint32_t stringset, uint8_t *data)
1212 if (stringset == ETH_SS_STATS) {
1213 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1214 memcpy(data + i * ETH_GSTRING_LEN,
1215 mv643xx_eth_stats[i].stat_string,
1221 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1222 struct ethtool_stats *stats,
1225 struct mv643xx_eth_private *mp = dev->priv;
1228 mib_counters_update(mp);
1230 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1231 const struct mv643xx_eth_stats *stat;
1234 stat = mv643xx_eth_stats + i;
1236 if (stat->netdev_off >= 0)
1237 p = ((void *)mp->dev) + stat->netdev_off;
1239 p = ((void *)mp) + stat->mp_off;
1241 data[i] = (stat->sizeof_stat == 8) ?
1242 *(uint64_t *)p : *(uint32_t *)p;
1246 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1248 if (sset == ETH_SS_STATS)
1249 return ARRAY_SIZE(mv643xx_eth_stats);
1254 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1255 .get_settings = mv643xx_eth_get_settings,
1256 .set_settings = mv643xx_eth_set_settings,
1257 .get_drvinfo = mv643xx_eth_get_drvinfo,
1258 .nway_reset = mv643xx_eth_nway_reset,
1259 .get_link = mv643xx_eth_get_link,
1260 .set_sg = ethtool_op_set_sg,
1261 .get_strings = mv643xx_eth_get_strings,
1262 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1263 .get_sset_count = mv643xx_eth_get_sset_count,
1266 static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
1267 .get_settings = mv643xx_eth_get_settings_phyless,
1268 .set_settings = mv643xx_eth_set_settings_phyless,
1269 .get_drvinfo = mv643xx_eth_get_drvinfo,
1270 .nway_reset = mv643xx_eth_nway_reset_phyless,
1271 .get_link = mv643xx_eth_get_link_phyless,
1272 .set_sg = ethtool_op_set_sg,
1273 .get_strings = mv643xx_eth_get_strings,
1274 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1275 .get_sset_count = mv643xx_eth_get_sset_count,
1279 /* address handling *********************************************************/
1280 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1285 mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
1286 mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
1288 addr[0] = (mac_h >> 24) & 0xff;
1289 addr[1] = (mac_h >> 16) & 0xff;
1290 addr[2] = (mac_h >> 8) & 0xff;
1291 addr[3] = mac_h & 0xff;
1292 addr[4] = (mac_l >> 8) & 0xff;
1293 addr[5] = mac_l & 0xff;
1296 static void init_mac_tables(struct mv643xx_eth_private *mp)
1300 for (i = 0; i < 0x100; i += 4) {
1301 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1302 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1305 for (i = 0; i < 0x10; i += 4)
1306 wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
1309 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1310 int table, unsigned char entry)
1312 unsigned int table_reg;
1314 /* Set "accepts frame bit" at specified table entry */
1315 table_reg = rdl(mp, table + (entry & 0xfc));
1316 table_reg |= 0x01 << (8 * (entry & 3));
1317 wrl(mp, table + (entry & 0xfc), table_reg);
1320 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1326 mac_l = (addr[4] << 8) | addr[5];
1327 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1329 wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
1330 wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
1332 table = UNICAST_TABLE(mp->port_num);
1333 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1336 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1338 struct mv643xx_eth_private *mp = netdev_priv(dev);
1340 /* +2 is for the offset of the HW addr type */
1341 memcpy(dev->dev_addr, addr + 2, 6);
1343 init_mac_tables(mp);
1344 uc_addr_set(mp, dev->dev_addr);
1349 static int addr_crc(unsigned char *addr)
1354 for (i = 0; i < 6; i++) {
1357 crc = (crc ^ addr[i]) << 8;
1358 for (j = 7; j >= 0; j--) {
1359 if (crc & (0x100 << j))
1367 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1369 struct mv643xx_eth_private *mp = netdev_priv(dev);
1371 struct dev_addr_list *addr;
1374 port_config = rdl(mp, PORT_CONFIG(mp->port_num));
1375 if (dev->flags & IFF_PROMISC)
1376 port_config |= UNICAST_PROMISCUOUS_MODE;
1378 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1379 wrl(mp, PORT_CONFIG(mp->port_num), port_config);
1381 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1382 int port_num = mp->port_num;
1383 u32 accept = 0x01010101;
1385 for (i = 0; i < 0x100; i += 4) {
1386 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1387 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1392 for (i = 0; i < 0x100; i += 4) {
1393 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
1394 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
1397 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1398 u8 *a = addr->da_addr;
1401 if (addr->da_addrlen != 6)
1404 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1405 table = SPECIAL_MCAST_TABLE(mp->port_num);
1406 set_filter_table_entry(mp, table, a[5]);
1408 int crc = addr_crc(a);
1410 table = OTHER_MCAST_TABLE(mp->port_num);
1411 set_filter_table_entry(mp, table, crc);
1417 /* rx/tx queue initialisation ***********************************************/
1418 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1420 struct rx_queue *rxq = mp->rxq + index;
1421 struct rx_desc *rx_desc;
1427 rxq->rx_ring_size = mp->default_rx_ring_size;
1429 rxq->rx_desc_count = 0;
1430 rxq->rx_curr_desc = 0;
1431 rxq->rx_used_desc = 0;
1433 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1435 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
1436 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1437 mp->rx_desc_sram_size);
1438 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1440 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1445 if (rxq->rx_desc_area == NULL) {
1446 dev_printk(KERN_ERR, &mp->dev->dev,
1447 "can't allocate rx ring (%d bytes)\n", size);
1450 memset(rxq->rx_desc_area, 0, size);
1452 rxq->rx_desc_area_size = size;
1453 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1455 if (rxq->rx_skb == NULL) {
1456 dev_printk(KERN_ERR, &mp->dev->dev,
1457 "can't allocate rx skb ring\n");
1461 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1462 for (i = 0; i < rxq->rx_ring_size; i++) {
1463 int nexti = (i + 1) % rxq->rx_ring_size;
1464 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1465 nexti * sizeof(struct rx_desc);
1468 init_timer(&rxq->rx_oom);
1469 rxq->rx_oom.data = (unsigned long)rxq;
1470 rxq->rx_oom.function = rxq_refill_timer_wrapper;
1476 if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
1477 iounmap(rxq->rx_desc_area);
1479 dma_free_coherent(NULL, size,
1487 static void rxq_deinit(struct rx_queue *rxq)
1489 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1494 del_timer_sync(&rxq->rx_oom);
1496 for (i = 0; i < rxq->rx_ring_size; i++) {
1497 if (rxq->rx_skb[i]) {
1498 dev_kfree_skb(rxq->rx_skb[i]);
1499 rxq->rx_desc_count--;
1503 if (rxq->rx_desc_count) {
1504 dev_printk(KERN_ERR, &mp->dev->dev,
1505 "error freeing rx ring -- %d skbs stuck\n",
1506 rxq->rx_desc_count);
1509 if (rxq->index == mp->rxq_primary &&
1510 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1511 iounmap(rxq->rx_desc_area);
1513 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1514 rxq->rx_desc_area, rxq->rx_desc_dma);
1519 static int txq_init(struct mv643xx_eth_private *mp, int index)
1521 struct tx_queue *txq = mp->txq + index;
1522 struct tx_desc *tx_desc;
1528 txq->tx_ring_size = mp->default_tx_ring_size;
1530 txq->tx_desc_count = 0;
1531 txq->tx_curr_desc = 0;
1532 txq->tx_used_desc = 0;
1534 size = txq->tx_ring_size * sizeof(struct tx_desc);
1536 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
1537 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1538 mp->tx_desc_sram_size);
1539 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1541 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1546 if (txq->tx_desc_area == NULL) {
1547 dev_printk(KERN_ERR, &mp->dev->dev,
1548 "can't allocate tx ring (%d bytes)\n", size);
1551 memset(txq->tx_desc_area, 0, size);
1553 txq->tx_desc_area_size = size;
1554 txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
1556 if (txq->tx_skb == NULL) {
1557 dev_printk(KERN_ERR, &mp->dev->dev,
1558 "can't allocate tx skb ring\n");
1562 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1563 for (i = 0; i < txq->tx_ring_size; i++) {
1564 struct tx_desc *txd = tx_desc + i;
1565 int nexti = (i + 1) % txq->tx_ring_size;
1568 txd->next_desc_ptr = txq->tx_desc_dma +
1569 nexti * sizeof(struct tx_desc);
1576 if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
1577 iounmap(txq->tx_desc_area);
1579 dma_free_coherent(NULL, size,
1587 static void txq_reclaim(struct tx_queue *txq, int force)
1589 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1590 unsigned long flags;
1592 spin_lock_irqsave(&mp->lock, flags);
1593 while (txq->tx_desc_count > 0) {
1595 struct tx_desc *desc;
1597 struct sk_buff *skb;
1601 tx_index = txq->tx_used_desc;
1602 desc = &txq->tx_desc_area[tx_index];
1603 cmd_sts = desc->cmd_sts;
1605 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
1608 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
1611 txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
1612 txq->tx_desc_count--;
1614 addr = desc->buf_ptr;
1615 count = desc->byte_cnt;
1616 skb = txq->tx_skb[tx_index];
1617 txq->tx_skb[tx_index] = NULL;
1619 if (cmd_sts & ERROR_SUMMARY) {
1620 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
1621 mp->dev->stats.tx_errors++;
1625 * Drop mp->lock while we free the skb.
1627 spin_unlock_irqrestore(&mp->lock, flags);
1629 if (cmd_sts & TX_FIRST_DESC)
1630 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1632 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1635 dev_kfree_skb_irq(skb);
1637 spin_lock_irqsave(&mp->lock, flags);
1639 spin_unlock_irqrestore(&mp->lock, flags);
1642 static void txq_deinit(struct tx_queue *txq)
1644 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1647 txq_reclaim(txq, 1);
1649 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1651 if (txq->index == mp->txq_primary &&
1652 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1653 iounmap(txq->tx_desc_area);
1655 dma_free_coherent(NULL, txq->tx_desc_area_size,
1656 txq->tx_desc_area, txq->tx_desc_dma);
1662 /* netdev ops and related ***************************************************/
1663 static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
1668 pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1670 /* clear speed, duplex and rx buffer size fields */
1671 pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
1672 SET_GMII_SPEED_TO_1000 |
1673 SET_FULL_DUPLEX_MODE |
1674 MAX_RX_PACKET_MASK);
1676 pscr_n |= MAX_RX_PACKET_9700BYTE;
1678 if (speed == SPEED_1000)
1679 pscr_n |= SET_GMII_SPEED_TO_1000;
1680 else if (speed == SPEED_100)
1681 pscr_n |= SET_MII_SPEED_TO_100;
1683 if (duplex == DUPLEX_FULL)
1684 pscr_n |= SET_FULL_DUPLEX_MODE;
1686 if (pscr_n != pscr_o) {
1687 if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
1688 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1692 for (i = 0; i < 8; i++)
1693 if (mp->txq_mask & (1 << i))
1694 txq_disable(mp->txq + i);
1696 pscr_o &= ~SERIAL_PORT_ENABLE;
1697 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
1698 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1699 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
1701 for (i = 0; i < 8; i++)
1702 if (mp->txq_mask & (1 << i))
1703 txq_enable(mp->txq + i);
1708 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1710 struct net_device *dev = (struct net_device *)dev_id;
1711 struct mv643xx_eth_private *mp = netdev_priv(dev);
1715 int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
1716 (INT_TX_END | INT_RX | INT_EXT);
1721 if (int_cause & INT_EXT) {
1722 int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
1723 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1724 wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
1727 if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
1728 if (mp->phy_addr == -1 || mii_link_ok(&mp->mii)) {
1729 if (mp->phy_addr != -1) {
1730 struct ethtool_cmd cmd;
1732 mii_ethtool_gset(&mp->mii, &cmd);
1733 update_pscr(mp, cmd.speed, cmd.duplex);
1736 if (!netif_carrier_ok(dev)) {
1737 netif_carrier_on(dev);
1738 netif_wake_queue(dev);
1740 } else if (netif_carrier_ok(dev)) {
1743 netif_stop_queue(dev);
1744 netif_carrier_off(dev);
1746 for (i = 0; i < 8; i++) {
1747 struct tx_queue *txq = mp->txq + i;
1749 if (mp->txq_mask & (1 << i)) {
1750 txq_reclaim(txq, 1);
1751 txq_reset_hw_ptr(txq);
1758 * RxBuffer or RxError set for any of the 8 queues?
1760 #ifdef MV643XX_ETH_NAPI
1761 if (int_cause & INT_RX) {
1762 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
1763 rdl(mp, INT_MASK(mp->port_num));
1765 netif_rx_schedule(dev, &mp->napi);
1768 if (int_cause & INT_RX) {
1771 for (i = 7; i >= 0; i--)
1772 if (mp->rxq_mask & (1 << i))
1773 rxq_process(mp->rxq + i, INT_MAX);
1778 * TxBuffer or TxError set for any of the 8 queues?
1780 if (int_cause_ext & INT_EXT_TX) {
1783 for (i = 0; i < 8; i++)
1784 if (mp->txq_mask & (1 << i))
1785 txq_reclaim(mp->txq + i, 0);
1788 * Enough space again in the primary TX queue for a
1791 if (netif_carrier_ok(dev)) {
1792 spin_lock(&mp->lock);
1793 __txq_maybe_wake(mp->txq + mp->txq_primary);
1794 spin_unlock(&mp->lock);
1799 * Any TxEnd interrupts?
1801 if (int_cause & INT_TX_END) {
1804 wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
1806 spin_lock(&mp->lock);
1807 for (i = 0; i < 8; i++) {
1808 struct tx_queue *txq = mp->txq + i;
1812 if ((int_cause & (INT_TX_END_0 << i)) == 0)
1816 rdl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num, i));
1817 expected_ptr = (u32)txq->tx_desc_dma +
1818 txq->tx_curr_desc * sizeof(struct tx_desc);
1820 if (hw_desc_ptr != expected_ptr)
1823 spin_unlock(&mp->lock);
1829 static void phy_reset(struct mv643xx_eth_private *mp)
1833 smi_reg_read(mp, mp->phy_addr, 0, &data);
1835 smi_reg_write(mp, mp->phy_addr, 0, data);
1839 smi_reg_read(mp, mp->phy_addr, 0, &data);
1840 } while (data & 0x8000);
1843 static void port_start(struct mv643xx_eth_private *mp)
1849 * Configure basic link parameters.
1851 pscr = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
1852 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1853 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1854 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1855 DISABLE_AUTO_NEG_SPEED_GMII |
1856 DISABLE_AUTO_NEG_FOR_DUPLEX |
1857 DO_NOT_FORCE_LINK_FAIL |
1858 SERIAL_PORT_CONTROL_RESERVED;
1859 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1860 pscr |= SERIAL_PORT_ENABLE;
1861 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr);
1863 wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1866 * Perform PHY reset, if there is a PHY.
1868 if (mp->phy_addr != -1) {
1869 struct ethtool_cmd cmd;
1871 mv643xx_eth_get_settings(mp->dev, &cmd);
1873 mv643xx_eth_set_settings(mp->dev, &cmd);
1877 * Configure TX path and queues.
1879 tx_set_rate(mp, 1000000000, 16777216);
1880 for (i = 0; i < 8; i++) {
1881 struct tx_queue *txq = mp->txq + i;
1883 if ((mp->txq_mask & (1 << i)) == 0)
1886 txq_reset_hw_ptr(txq);
1887 txq_set_rate(txq, 1000000000, 16777216);
1888 txq_set_fixed_prio_mode(txq);
1892 * Add configured unicast address to address filter table.
1894 uc_addr_set(mp, mp->dev->dev_addr);
1897 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1898 * frames to RX queue #0.
1900 wrl(mp, PORT_CONFIG(mp->port_num), 0x00000000);
1903 * Treat BPDUs as normal multicasts, and disable partition mode.
1905 wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
1908 * Enable the receive queues.
1910 for (i = 0; i < 8; i++) {
1911 struct rx_queue *rxq = mp->rxq + i;
1912 int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
1915 if ((mp->rxq_mask & (1 << i)) == 0)
1918 addr = (u32)rxq->rx_desc_dma;
1919 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
1926 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1928 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1931 val = rdl(mp, SDMA_CONFIG(mp->port_num));
1932 if (mp->shared->extended_rx_coal_limit) {
1936 val |= (coal & 0x8000) << 10;
1937 val |= (coal & 0x7fff) << 7;
1942 val |= (coal & 0x3fff) << 8;
1944 wrl(mp, SDMA_CONFIG(mp->port_num), val);
1947 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
1949 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1953 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
1956 static int mv643xx_eth_open(struct net_device *dev)
1958 struct mv643xx_eth_private *mp = netdev_priv(dev);
1962 wrl(mp, INT_CAUSE(mp->port_num), 0);
1963 wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
1964 rdl(mp, INT_CAUSE_EXT(mp->port_num));
1966 err = request_irq(dev->irq, mv643xx_eth_irq,
1967 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
1970 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
1974 init_mac_tables(mp);
1976 for (i = 0; i < 8; i++) {
1977 if ((mp->rxq_mask & (1 << i)) == 0)
1980 err = rxq_init(mp, i);
1983 if (mp->rxq_mask & (1 << i))
1984 rxq_deinit(mp->rxq + i);
1988 rxq_refill(mp->rxq + i);
1991 for (i = 0; i < 8; i++) {
1992 if ((mp->txq_mask & (1 << i)) == 0)
1995 err = txq_init(mp, i);
1998 if (mp->txq_mask & (1 << i))
1999 txq_deinit(mp->txq + i);
2004 #ifdef MV643XX_ETH_NAPI
2005 napi_enable(&mp->napi);
2013 wrl(mp, INT_MASK_EXT(mp->port_num),
2014 INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
2016 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2022 for (i = 0; i < 8; i++)
2023 if (mp->rxq_mask & (1 << i))
2024 rxq_deinit(mp->rxq + i);
2026 free_irq(dev->irq, dev);
2031 static void port_reset(struct mv643xx_eth_private *mp)
2036 for (i = 0; i < 8; i++) {
2037 if (mp->rxq_mask & (1 << i))
2038 rxq_disable(mp->rxq + i);
2039 if (mp->txq_mask & (1 << i))
2040 txq_disable(mp->txq + i);
2042 while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
2045 /* Reset the Enable bit in the Configuration Register */
2046 data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
2047 data &= ~(SERIAL_PORT_ENABLE |
2048 DO_NOT_FORCE_LINK_FAIL |
2050 wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
2053 static int mv643xx_eth_stop(struct net_device *dev)
2055 struct mv643xx_eth_private *mp = netdev_priv(dev);
2058 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2059 rdl(mp, INT_MASK(mp->port_num));
2061 #ifdef MV643XX_ETH_NAPI
2062 napi_disable(&mp->napi);
2064 netif_carrier_off(dev);
2065 netif_stop_queue(dev);
2067 free_irq(dev->irq, dev);
2070 mib_counters_update(mp);
2072 for (i = 0; i < 8; i++) {
2073 if (mp->rxq_mask & (1 << i))
2074 rxq_deinit(mp->rxq + i);
2075 if (mp->txq_mask & (1 << i))
2076 txq_deinit(mp->txq + i);
2082 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2084 struct mv643xx_eth_private *mp = netdev_priv(dev);
2086 if (mp->phy_addr != -1)
2087 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
2092 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2094 struct mv643xx_eth_private *mp = netdev_priv(dev);
2096 if (new_mtu < 64 || new_mtu > 9500)
2100 tx_set_rate(mp, 1000000000, 16777216);
2102 if (!netif_running(dev))
2106 * Stop and then re-open the interface. This will allocate RX
2107 * skbs of the new MTU.
2108 * There is a possible danger that the open will not succeed,
2109 * due to memory being full.
2111 mv643xx_eth_stop(dev);
2112 if (mv643xx_eth_open(dev)) {
2113 dev_printk(KERN_ERR, &dev->dev,
2114 "fatal error on re-opening device after "
2121 static void tx_timeout_task(struct work_struct *ugly)
2123 struct mv643xx_eth_private *mp;
2125 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2126 if (netif_running(mp->dev)) {
2127 netif_stop_queue(mp->dev);
2132 __txq_maybe_wake(mp->txq + mp->txq_primary);
2136 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2138 struct mv643xx_eth_private *mp = netdev_priv(dev);
2140 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2142 schedule_work(&mp->tx_timeout_task);
2145 #ifdef CONFIG_NET_POLL_CONTROLLER
2146 static void mv643xx_eth_netpoll(struct net_device *dev)
2148 struct mv643xx_eth_private *mp = netdev_priv(dev);
2150 wrl(mp, INT_MASK(mp->port_num), 0x00000000);
2151 rdl(mp, INT_MASK(mp->port_num));
2153 mv643xx_eth_irq(dev->irq, dev);
2155 wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
2159 static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
2161 struct mv643xx_eth_private *mp = netdev_priv(dev);
2164 smi_reg_read(mp, addr, reg, &val);
2169 static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
2171 struct mv643xx_eth_private *mp = netdev_priv(dev);
2172 smi_reg_write(mp, addr, reg, val);
2176 /* platform glue ************************************************************/
2178 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2179 struct mbus_dram_target_info *dram)
2181 void __iomem *base = msp->base;
2186 for (i = 0; i < 6; i++) {
2187 writel(0, base + WINDOW_BASE(i));
2188 writel(0, base + WINDOW_SIZE(i));
2190 writel(0, base + WINDOW_REMAP_HIGH(i));
2196 for (i = 0; i < dram->num_cs; i++) {
2197 struct mbus_dram_window *cs = dram->cs + i;
2199 writel((cs->base & 0xffff0000) |
2200 (cs->mbus_attr << 8) |
2201 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2202 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2204 win_enable &= ~(1 << i);
2205 win_protect |= 3 << (2 * i);
2208 writel(win_enable, base + WINDOW_BAR_ENABLE);
2209 msp->win_protect = win_protect;
2212 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2215 * Check whether we have a 14-bit coal limit field in bits
2216 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2217 * SDMA config register.
2219 writel(0x02000000, msp->base + SDMA_CONFIG(0));
2220 if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
2221 msp->extended_rx_coal_limit = 1;
2223 msp->extended_rx_coal_limit = 0;
2226 * Check whether the TX rate control registers are in the
2227 * old or the new place.
2229 writel(1, msp->base + TX_BW_MTU_MOVED(0));
2230 if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
2231 msp->tx_bw_control_moved = 1;
2233 msp->tx_bw_control_moved = 0;
2236 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2238 static int mv643xx_eth_version_printed = 0;
2239 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2240 struct mv643xx_eth_shared_private *msp;
2241 struct resource *res;
2244 if (!mv643xx_eth_version_printed++)
2245 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2248 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2253 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2256 memset(msp, 0, sizeof(*msp));
2258 msp->base = ioremap(res->start, res->end - res->start + 1);
2259 if (msp->base == NULL)
2262 spin_lock_init(&msp->phy_lock);
2265 * (Re-)program MBUS remapping windows if we are asked to.
2267 if (pd != NULL && pd->dram != NULL)
2268 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2271 * Detect hardware parameters.
2273 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2274 infer_hw_params(msp);
2276 platform_set_drvdata(pdev, msp);
2286 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2288 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2296 static struct platform_driver mv643xx_eth_shared_driver = {
2297 .probe = mv643xx_eth_shared_probe,
2298 .remove = mv643xx_eth_shared_remove,
2300 .name = MV643XX_ETH_SHARED_NAME,
2301 .owner = THIS_MODULE,
2305 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2307 int addr_shift = 5 * mp->port_num;
2310 data = rdl(mp, PHY_ADDR);
2311 data &= ~(0x1f << addr_shift);
2312 data |= (phy_addr & 0x1f) << addr_shift;
2313 wrl(mp, PHY_ADDR, data);
2316 static int phy_addr_get(struct mv643xx_eth_private *mp)
2320 data = rdl(mp, PHY_ADDR);
2322 return (data >> (5 * mp->port_num)) & 0x1f;
2325 static void set_params(struct mv643xx_eth_private *mp,
2326 struct mv643xx_eth_platform_data *pd)
2328 struct net_device *dev = mp->dev;
2330 if (is_valid_ether_addr(pd->mac_addr))
2331 memcpy(dev->dev_addr, pd->mac_addr, 6);
2333 uc_addr_get(mp, dev->dev_addr);
2335 if (pd->phy_addr == -1) {
2336 mp->shared_smi = NULL;
2339 mp->shared_smi = mp->shared;
2340 if (pd->shared_smi != NULL)
2341 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2343 if (pd->force_phy_addr || pd->phy_addr) {
2344 mp->phy_addr = pd->phy_addr & 0x3f;
2345 phy_addr_set(mp, mp->phy_addr);
2347 mp->phy_addr = phy_addr_get(mp);
2351 mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2352 if (pd->rx_queue_size)
2353 mp->default_rx_ring_size = pd->rx_queue_size;
2354 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2355 mp->rx_desc_sram_size = pd->rx_sram_size;
2357 if (pd->rx_queue_mask)
2358 mp->rxq_mask = pd->rx_queue_mask;
2360 mp->rxq_mask = 0x01;
2361 mp->rxq_primary = fls(mp->rxq_mask) - 1;
2363 mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2364 if (pd->tx_queue_size)
2365 mp->default_tx_ring_size = pd->tx_queue_size;
2366 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2367 mp->tx_desc_sram_size = pd->tx_sram_size;
2369 if (pd->tx_queue_mask)
2370 mp->txq_mask = pd->tx_queue_mask;
2372 mp->txq_mask = 0x01;
2373 mp->txq_primary = fls(mp->txq_mask) - 1;
2376 static int phy_detect(struct mv643xx_eth_private *mp)
2381 smi_reg_read(mp, mp->phy_addr, 0, &data);
2382 smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
2384 smi_reg_read(mp, mp->phy_addr, 0, &data2);
2385 if (((data ^ data2) & 0x1000) == 0)
2388 smi_reg_write(mp, mp->phy_addr, 0, data);
2393 static int phy_init(struct mv643xx_eth_private *mp,
2394 struct mv643xx_eth_platform_data *pd)
2396 struct ethtool_cmd cmd;
2399 err = phy_detect(mp);
2401 dev_printk(KERN_INFO, &mp->dev->dev,
2402 "no PHY detected at addr %d\n", mp->phy_addr);
2407 mp->mii.phy_id = mp->phy_addr;
2408 mp->mii.phy_id_mask = 0x3f;
2409 mp->mii.reg_num_mask = 0x1f;
2410 mp->mii.dev = mp->dev;
2411 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2412 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2414 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2416 memset(&cmd, 0, sizeof(cmd));
2418 cmd.port = PORT_MII;
2419 cmd.transceiver = XCVR_INTERNAL;
2420 cmd.phy_address = mp->phy_addr;
2421 if (pd->speed == 0) {
2422 cmd.autoneg = AUTONEG_ENABLE;
2423 cmd.speed = SPEED_100;
2424 cmd.advertising = ADVERTISED_10baseT_Half |
2425 ADVERTISED_10baseT_Full |
2426 ADVERTISED_100baseT_Half |
2427 ADVERTISED_100baseT_Full;
2428 if (mp->mii.supports_gmii)
2429 cmd.advertising |= ADVERTISED_1000baseT_Full;
2431 cmd.autoneg = AUTONEG_DISABLE;
2432 cmd.speed = pd->speed;
2433 cmd.duplex = pd->duplex;
2436 update_pscr(mp, cmd.speed, cmd.duplex);
2437 mv643xx_eth_set_settings(mp->dev, &cmd);
2442 static int mv643xx_eth_probe(struct platform_device *pdev)
2444 struct mv643xx_eth_platform_data *pd;
2445 struct mv643xx_eth_private *mp;
2446 struct net_device *dev;
2447 struct resource *res;
2448 DECLARE_MAC_BUF(mac);
2451 pd = pdev->dev.platform_data;
2453 dev_printk(KERN_ERR, &pdev->dev,
2454 "no mv643xx_eth_platform_data\n");
2458 if (pd->shared == NULL) {
2459 dev_printk(KERN_ERR, &pdev->dev,
2460 "no mv643xx_eth_platform_data->shared\n");
2464 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2468 mp = netdev_priv(dev);
2469 platform_set_drvdata(pdev, mp);
2471 mp->shared = platform_get_drvdata(pd->shared);
2472 mp->port_num = pd->port_number;
2475 #ifdef MV643XX_ETH_NAPI
2476 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2481 spin_lock_init(&mp->lock);
2483 mib_counters_clear(mp);
2484 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2486 if (mp->phy_addr != -1) {
2487 err = phy_init(mp, pd);
2491 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2493 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
2497 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2499 dev->irq = res->start;
2501 dev->hard_start_xmit = mv643xx_eth_xmit;
2502 dev->open = mv643xx_eth_open;
2503 dev->stop = mv643xx_eth_stop;
2504 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2505 dev->set_mac_address = mv643xx_eth_set_mac_address;
2506 dev->do_ioctl = mv643xx_eth_ioctl;
2507 dev->change_mtu = mv643xx_eth_change_mtu;
2508 dev->tx_timeout = mv643xx_eth_tx_timeout;
2509 #ifdef CONFIG_NET_POLL_CONTROLLER
2510 dev->poll_controller = mv643xx_eth_netpoll;
2512 dev->watchdog_timeo = 2 * HZ;
2515 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2517 * Zero copy can only work if we use Discovery II memory. Else, we will
2518 * have to map the buffers to ISA memory which is only 16 MB
2520 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2523 SET_NETDEV_DEV(dev, &pdev->dev);
2525 if (mp->shared->win_protect)
2526 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2528 err = register_netdev(dev);
2532 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
2533 mp->port_num, print_mac(mac, dev->dev_addr));
2535 if (dev->features & NETIF_F_SG)
2536 dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
2538 if (dev->features & NETIF_F_IP_CSUM)
2539 dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
2541 #ifdef MV643XX_ETH_NAPI
2542 dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
2545 if (mp->tx_desc_sram_size > 0)
2546 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2556 static int mv643xx_eth_remove(struct platform_device *pdev)
2558 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2560 unregister_netdev(mp->dev);
2561 flush_scheduled_work();
2562 free_netdev(mp->dev);
2564 platform_set_drvdata(pdev, NULL);
2569 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2571 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2573 /* Mask all interrupts on ethernet port */
2574 wrl(mp, INT_MASK(mp->port_num), 0);
2575 rdl(mp, INT_MASK(mp->port_num));
2577 if (netif_running(mp->dev))
2581 static struct platform_driver mv643xx_eth_driver = {
2582 .probe = mv643xx_eth_probe,
2583 .remove = mv643xx_eth_remove,
2584 .shutdown = mv643xx_eth_shutdown,
2586 .name = MV643XX_ETH_NAME,
2587 .owner = THIS_MODULE,
2591 static int __init mv643xx_eth_init_module(void)
2595 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2597 rc = platform_driver_register(&mv643xx_eth_driver);
2599 platform_driver_unregister(&mv643xx_eth_shared_driver);
2604 module_init(mv643xx_eth_init_module);
2606 static void __exit mv643xx_eth_cleanup_module(void)
2608 platform_driver_unregister(&mv643xx_eth_driver);
2609 platform_driver_unregister(&mv643xx_eth_shared_driver);
2611 module_exit(mv643xx_eth_cleanup_module);
2613 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2614 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2615 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2616 MODULE_LICENSE("GPL");
2617 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2618 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);