2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
42 #include <linux/mlx4/device.h>
43 #include <linux/mlx4/doorbell.h>
49 MODULE_AUTHOR("Roland Dreier");
50 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
51 MODULE_LICENSE("Dual BSD/GPL");
52 MODULE_VERSION(DRV_VERSION);
54 #ifdef CONFIG_MLX4_DEBUG
56 int mlx4_debug_level = 0;
57 module_param_named(debug_level, mlx4_debug_level, int, 0644);
58 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
60 #endif /* CONFIG_MLX4_DEBUG */
65 module_param(msi_x, int, 0444);
66 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
68 #else /* CONFIG_PCI_MSI */
72 #endif /* CONFIG_PCI_MSI */
74 static char mlx4_version[] __devinitdata =
75 DRV_NAME ": Mellanox ConnectX core driver v"
76 DRV_VERSION " (" DRV_RELDATE ")\n";
78 static struct mlx4_profile default_profile = {
81 .rdmarc_per_qp = 1 << 4,
88 static int log_num_mac = 2;
89 module_param_named(log_num_mac, log_num_mac, int, 0444);
90 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
92 static int log_num_vlan;
93 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
94 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
97 module_param_named(use_prio, use_prio, bool, 0444);
98 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
101 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
106 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
108 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
112 if (dev_cap->min_page_sz > PAGE_SIZE) {
113 mlx4_err(dev, "HCA minimum page size of %d bigger than "
114 "kernel PAGE_SIZE of %ld, aborting.\n",
115 dev_cap->min_page_sz, PAGE_SIZE);
118 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
119 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
121 dev_cap->num_ports, MLX4_MAX_PORTS);
125 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
126 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
127 "PCI resource 2 size of 0x%llx, aborting.\n",
129 (unsigned long long) pci_resource_len(dev->pdev, 2));
133 dev->caps.num_ports = dev_cap->num_ports;
134 for (i = 1; i <= dev->caps.num_ports; ++i) {
135 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
136 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
137 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
138 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
139 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
140 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
141 dev->caps.def_mac[i] = dev_cap->def_mac[i];
144 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
145 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
146 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
147 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
148 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
149 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
150 dev->caps.max_wqes = dev_cap->max_qp_sz;
151 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
152 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
153 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
154 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
155 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
156 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
157 dev->caps.num_qp_per_mgm = MLX4_QP_PER_MGM;
159 * Subtract 1 from the limit because we need to allocate a
160 * spare CQE so the HCA HW can tell the difference between an
161 * empty CQ and a full CQ.
163 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
164 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
165 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
166 dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts,
167 MLX4_MTT_ENTRY_PER_SEG);
168 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
169 dev->caps.reserved_uars = dev_cap->reserved_uars;
170 dev->caps.reserved_pds = dev_cap->reserved_pds;
171 dev->caps.mtt_entry_sz = MLX4_MTT_ENTRY_PER_SEG * dev_cap->mtt_entry_sz;
172 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
173 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
174 dev->caps.flags = dev_cap->flags;
175 dev->caps.bmme_flags = dev_cap->bmme_flags;
176 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
177 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
178 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
180 dev->caps.log_num_macs = log_num_mac;
181 dev->caps.log_num_vlans = log_num_vlan;
182 dev->caps.log_num_prios = use_prio ? 3 : 0;
184 for (i = 1; i <= dev->caps.num_ports; ++i) {
185 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
186 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
187 mlx4_warn(dev, "Requested number of MACs is too much "
188 "for port %d, reducing to %d.\n",
189 i, 1 << dev->caps.log_num_macs);
191 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
192 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
193 mlx4_warn(dev, "Requested number of VLANs is too much "
194 "for port %d, reducing to %d.\n",
195 i, 1 << dev->caps.log_num_vlans);
199 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
200 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
201 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
202 (1 << dev->caps.log_num_macs) *
203 (1 << dev->caps.log_num_vlans) *
204 (1 << dev->caps.log_num_prios) *
206 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
208 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
209 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
210 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
211 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
216 static int mlx4_load_fw(struct mlx4_dev *dev)
218 struct mlx4_priv *priv = mlx4_priv(dev);
221 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
222 GFP_HIGHUSER | __GFP_NOWARN, 0);
223 if (!priv->fw.fw_icm) {
224 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
228 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
230 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
234 err = mlx4_RUN_FW(dev);
236 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
246 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
250 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
253 struct mlx4_priv *priv = mlx4_priv(dev);
256 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
258 ((u64) (MLX4_CMPT_TYPE_QP *
259 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
260 cmpt_entry_sz, dev->caps.num_qps,
261 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
266 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
268 ((u64) (MLX4_CMPT_TYPE_SRQ *
269 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
270 cmpt_entry_sz, dev->caps.num_srqs,
271 dev->caps.reserved_srqs, 0, 0);
275 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
277 ((u64) (MLX4_CMPT_TYPE_CQ *
278 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
279 cmpt_entry_sz, dev->caps.num_cqs,
280 dev->caps.reserved_cqs, 0, 0);
284 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
286 ((u64) (MLX4_CMPT_TYPE_EQ *
287 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
289 roundup_pow_of_two(MLX4_NUM_EQ +
290 dev->caps.reserved_eqs),
291 MLX4_NUM_EQ + dev->caps.reserved_eqs, 0, 0);
298 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
301 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
304 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
310 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
311 struct mlx4_init_hca_param *init_hca, u64 icm_size)
313 struct mlx4_priv *priv = mlx4_priv(dev);
317 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
319 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
323 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
324 (unsigned long long) icm_size >> 10,
325 (unsigned long long) aux_pages << 2);
327 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
328 GFP_HIGHUSER | __GFP_NOWARN, 0);
329 if (!priv->fw.aux_icm) {
330 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
334 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
336 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
340 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
342 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
346 err = mlx4_map_eq_icm(dev, init_hca->eqc_base);
348 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
353 * Reserved MTT entries must be aligned up to a cacheline
354 * boundary, since the FW will write to them, while the driver
355 * writes to all other MTT entries. (The variable
356 * dev->caps.mtt_entry_sz below is really the MTT segment
357 * size, not the raw entry size)
359 dev->caps.reserved_mtts =
360 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
361 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
363 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
365 dev->caps.mtt_entry_sz,
366 dev->caps.num_mtt_segs,
367 dev->caps.reserved_mtts, 1, 0);
369 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
373 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
375 dev_cap->dmpt_entry_sz,
377 dev->caps.reserved_mrws, 1, 1);
379 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
383 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
385 dev_cap->qpc_entry_sz,
387 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
390 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
394 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
396 dev_cap->aux_entry_sz,
398 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
401 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
405 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
407 dev_cap->altc_entry_sz,
409 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
412 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
416 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
417 init_hca->rdmarc_base,
418 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
420 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
423 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
427 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
429 dev_cap->cqc_entry_sz,
431 dev->caps.reserved_cqs, 0, 0);
433 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
434 goto err_unmap_rdmarc;
437 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
439 dev_cap->srq_entry_sz,
441 dev->caps.reserved_srqs, 0, 0);
443 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
448 * It's not strictly required, but for simplicity just map the
449 * whole multicast group table now. The table isn't very big
450 * and it's a lot easier than trying to track ref counts.
452 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
453 init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
454 dev->caps.num_mgms + dev->caps.num_amgms,
455 dev->caps.num_mgms + dev->caps.num_amgms,
458 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
465 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
468 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
471 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
474 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
477 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
480 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
483 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
486 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
489 mlx4_unmap_eq_icm(dev);
492 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
493 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
494 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
495 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
498 mlx4_UNMAP_ICM_AUX(dev);
501 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
506 static void mlx4_free_icms(struct mlx4_dev *dev)
508 struct mlx4_priv *priv = mlx4_priv(dev);
510 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
511 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
512 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
513 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
514 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
515 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
516 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
517 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
518 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
519 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
520 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
521 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
522 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
523 mlx4_unmap_eq_icm(dev);
525 mlx4_UNMAP_ICM_AUX(dev);
526 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
529 static void mlx4_close_hca(struct mlx4_dev *dev)
531 mlx4_CLOSE_HCA(dev, 0);
534 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
537 static int mlx4_init_hca(struct mlx4_dev *dev)
539 struct mlx4_priv *priv = mlx4_priv(dev);
540 struct mlx4_adapter adapter;
541 struct mlx4_dev_cap dev_cap;
542 struct mlx4_mod_stat_cfg mlx4_cfg;
543 struct mlx4_profile profile;
544 struct mlx4_init_hca_param init_hca;
548 err = mlx4_QUERY_FW(dev);
550 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
554 err = mlx4_load_fw(dev);
556 mlx4_err(dev, "Failed to start FW, aborting.\n");
560 mlx4_cfg.log_pg_sz_m = 1;
561 mlx4_cfg.log_pg_sz = 0;
562 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
564 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
566 err = mlx4_dev_cap(dev, &dev_cap);
568 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
572 profile = default_profile;
574 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
575 if ((long long) icm_size < 0) {
580 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
582 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
586 err = mlx4_INIT_HCA(dev, &init_hca);
588 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
592 err = mlx4_QUERY_ADAPTER(dev, &adapter);
594 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
598 priv->eq_table.inta_pin = adapter.inta_pin;
599 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
611 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
616 static int mlx4_setup_hca(struct mlx4_dev *dev)
618 struct mlx4_priv *priv = mlx4_priv(dev);
621 err = mlx4_init_uar_table(dev);
623 mlx4_err(dev, "Failed to initialize "
624 "user access region table, aborting.\n");
628 err = mlx4_uar_alloc(dev, &priv->driver_uar);
630 mlx4_err(dev, "Failed to allocate driver access region, "
632 goto err_uar_table_free;
635 priv->kar = ioremap(priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
637 mlx4_err(dev, "Couldn't map kernel access region, "
643 err = mlx4_init_pd_table(dev);
645 mlx4_err(dev, "Failed to initialize "
646 "protection domain table, aborting.\n");
650 err = mlx4_init_mr_table(dev);
652 mlx4_err(dev, "Failed to initialize "
653 "memory region table, aborting.\n");
654 goto err_pd_table_free;
657 err = mlx4_init_eq_table(dev);
659 mlx4_err(dev, "Failed to initialize "
660 "event queue table, aborting.\n");
661 goto err_mr_table_free;
664 err = mlx4_cmd_use_events(dev);
666 mlx4_err(dev, "Failed to switch to event-driven "
667 "firmware commands, aborting.\n");
668 goto err_eq_table_free;
673 if (dev->flags & MLX4_FLAG_MSI_X) {
674 mlx4_warn(dev, "NOP command failed to generate MSI-X "
675 "interrupt IRQ %d).\n",
676 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
677 mlx4_warn(dev, "Trying again without MSI-X.\n");
679 mlx4_err(dev, "NOP command failed to generate interrupt "
680 "(IRQ %d), aborting.\n",
681 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
682 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
688 mlx4_dbg(dev, "NOP command IRQ test passed\n");
690 err = mlx4_init_cq_table(dev);
692 mlx4_err(dev, "Failed to initialize "
693 "completion queue table, aborting.\n");
697 err = mlx4_init_srq_table(dev);
699 mlx4_err(dev, "Failed to initialize "
700 "shared receive queue table, aborting.\n");
701 goto err_cq_table_free;
704 err = mlx4_init_qp_table(dev);
706 mlx4_err(dev, "Failed to initialize "
707 "queue pair table, aborting.\n");
708 goto err_srq_table_free;
711 err = mlx4_init_mcg_table(dev);
713 mlx4_err(dev, "Failed to initialize "
714 "multicast group table, aborting.\n");
715 goto err_qp_table_free;
721 mlx4_cleanup_qp_table(dev);
724 mlx4_cleanup_srq_table(dev);
727 mlx4_cleanup_cq_table(dev);
730 mlx4_cmd_use_polling(dev);
733 mlx4_cleanup_eq_table(dev);
736 mlx4_cleanup_mr_table(dev);
739 mlx4_cleanup_pd_table(dev);
745 mlx4_uar_free(dev, &priv->driver_uar);
748 mlx4_cleanup_uar_table(dev);
752 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
754 struct mlx4_priv *priv = mlx4_priv(dev);
755 struct msix_entry entries[MLX4_NUM_EQ];
760 for (i = 0; i < MLX4_NUM_EQ; ++i)
761 entries[i].entry = i;
763 err = pci_enable_msix(dev->pdev, entries, ARRAY_SIZE(entries));
766 mlx4_info(dev, "Only %d MSI-X vectors available, "
767 "not using MSI-X\n", err);
771 for (i = 0; i < MLX4_NUM_EQ; ++i)
772 priv->eq_table.eq[i].irq = entries[i].vector;
774 dev->flags |= MLX4_FLAG_MSI_X;
779 for (i = 0; i < MLX4_NUM_EQ; ++i)
780 priv->eq_table.eq[i].irq = dev->pdev->irq;
783 static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
785 struct mlx4_priv *priv;
786 struct mlx4_dev *dev;
789 printk(KERN_INFO PFX "Initializing %s\n",
792 err = pci_enable_device(pdev);
794 dev_err(&pdev->dev, "Cannot enable PCI device, "
800 * Check for BARs. We expect 0: 1MB
802 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
803 pci_resource_len(pdev, 0) != 1 << 20) {
804 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
806 goto err_disable_pdev;
808 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
809 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
811 goto err_disable_pdev;
814 err = pci_request_region(pdev, 0, DRV_NAME);
816 dev_err(&pdev->dev, "Cannot request control region, aborting.\n");
817 goto err_disable_pdev;
820 err = pci_request_region(pdev, 2, DRV_NAME);
822 dev_err(&pdev->dev, "Cannot request UAR region, aborting.\n");
823 goto err_release_bar0;
826 pci_set_master(pdev);
828 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
830 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
831 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
833 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
834 goto err_release_bar2;
837 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
839 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
840 "consistent PCI DMA mask.\n");
841 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
843 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
845 goto err_release_bar2;
849 priv = kzalloc(sizeof *priv, GFP_KERNEL);
851 dev_err(&pdev->dev, "Device struct alloc failed, "
854 goto err_release_bar2;
859 INIT_LIST_HEAD(&priv->ctx_list);
860 spin_lock_init(&priv->ctx_lock);
862 INIT_LIST_HEAD(&priv->pgdir_list);
863 mutex_init(&priv->pgdir_mutex);
866 * Now reset the HCA before we touch the PCI capabilities or
867 * attempt a firmware command, since a boot ROM may have left
868 * the HCA in an undefined state.
870 err = mlx4_reset(dev);
872 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
876 if (mlx4_cmd_init(dev)) {
877 mlx4_err(dev, "Failed to init command interface, aborting.\n");
881 err = mlx4_init_hca(dev);
885 mlx4_enable_msi_x(dev);
887 err = mlx4_setup_hca(dev);
888 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
889 dev->flags &= ~MLX4_FLAG_MSI_X;
890 pci_disable_msix(pdev);
891 err = mlx4_setup_hca(dev);
897 err = mlx4_register_device(dev);
901 pci_set_drvdata(pdev, dev);
906 mlx4_cleanup_mcg_table(dev);
907 mlx4_cleanup_qp_table(dev);
908 mlx4_cleanup_srq_table(dev);
909 mlx4_cleanup_cq_table(dev);
910 mlx4_cmd_use_polling(dev);
911 mlx4_cleanup_eq_table(dev);
912 mlx4_cleanup_mr_table(dev);
913 mlx4_cleanup_pd_table(dev);
914 mlx4_cleanup_uar_table(dev);
917 if (dev->flags & MLX4_FLAG_MSI_X)
918 pci_disable_msix(pdev);
923 mlx4_cmd_cleanup(dev);
929 pci_release_region(pdev, 2);
932 pci_release_region(pdev, 0);
935 pci_disable_device(pdev);
936 pci_set_drvdata(pdev, NULL);
940 static int __devinit mlx4_init_one(struct pci_dev *pdev,
941 const struct pci_device_id *id)
943 static int mlx4_version_printed;
945 if (!mlx4_version_printed) {
946 printk(KERN_INFO "%s", mlx4_version);
947 ++mlx4_version_printed;
950 return __mlx4_init_one(pdev, id);
953 static void mlx4_remove_one(struct pci_dev *pdev)
955 struct mlx4_dev *dev = pci_get_drvdata(pdev);
956 struct mlx4_priv *priv = mlx4_priv(dev);
960 mlx4_unregister_device(dev);
962 for (p = 1; p <= dev->caps.num_ports; ++p)
963 mlx4_CLOSE_PORT(dev, p);
965 mlx4_cleanup_mcg_table(dev);
966 mlx4_cleanup_qp_table(dev);
967 mlx4_cleanup_srq_table(dev);
968 mlx4_cleanup_cq_table(dev);
969 mlx4_cmd_use_polling(dev);
970 mlx4_cleanup_eq_table(dev);
971 mlx4_cleanup_mr_table(dev);
972 mlx4_cleanup_pd_table(dev);
975 mlx4_uar_free(dev, &priv->driver_uar);
976 mlx4_cleanup_uar_table(dev);
978 mlx4_cmd_cleanup(dev);
980 if (dev->flags & MLX4_FLAG_MSI_X)
981 pci_disable_msix(pdev);
984 pci_release_region(pdev, 2);
985 pci_release_region(pdev, 0);
986 pci_disable_device(pdev);
987 pci_set_drvdata(pdev, NULL);
991 int mlx4_restart_one(struct pci_dev *pdev)
993 mlx4_remove_one(pdev);
994 return __mlx4_init_one(pdev, NULL);
997 static struct pci_device_id mlx4_pci_table[] = {
998 { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
999 { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
1000 { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
1001 { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
1002 { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
1006 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
1008 static struct pci_driver mlx4_driver = {
1010 .id_table = mlx4_pci_table,
1011 .probe = mlx4_init_one,
1012 .remove = __devexit_p(mlx4_remove_one)
1015 static int __init mlx4_init(void)
1019 ret = mlx4_catas_init();
1023 ret = pci_register_driver(&mlx4_driver);
1024 return ret < 0 ? ret : 0;
1027 static void __exit mlx4_cleanup(void)
1029 pci_unregister_driver(&mlx4_driver);
1030 mlx4_catas_cleanup();
1033 module_init(mlx4_init);
1034 module_exit(mlx4_cleanup);