drivers/net/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe_common.h"
  33 #include "ixgbe_phy.h"
  34
  35 static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
  36 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
  37 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
  38
  39 /**
  40  *  ixgbe_identify_phy_generic - Get physical layer module
  41  *  @hw: pointer to hardware structure
  42  *
  43  *  Determines the physical layer module found on the current adapter.
  44  **/
  45 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  46 {
  47         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  48         u32 phy_addr;
  49
  50         if (hw->phy.type == ixgbe_phy_unknown) {
  51                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  52                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
  53                                 hw->phy.addr = phy_addr;
  54                                 ixgbe_get_phy_id(hw);
  55                                 hw->phy.type =
  56                                         ixgbe_get_phy_type_from_id(hw->phy.id);
  57                                 status = 0;
  58                                 break;
  59                         }
  60                 }
  61         } else {
  62                 status = 0;
  63         }
  64
  65         return status;
  66 }
  67
  68 /**
  69  *  ixgbe_validate_phy_addr - Determines phy address is valid
  70  *  @hw: pointer to hardware structure
  71  *
  72  **/
  73 static bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
  74 {
  75         u16 phy_id = 0;
  76         bool valid = false;
  77
  78         hw->phy.addr = phy_addr;
  79         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
  80                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
  81
  82         if (phy_id != 0xFFFF && phy_id != 0x0)
  83                 valid = true;
  84
  85         return valid;
  86 }
  87
  88 /**
  89  *  ixgbe_get_phy_id - Get the phy type
  90  *  @hw: pointer to hardware structure
  91  *
  92  **/
  93 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
  94 {
  95         u32 status;
  96         u16 phy_id_high = 0;
  97         u16 phy_id_low = 0;
  98
  99         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 100                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 101                                       &phy_id_high);
 102
 103         if (status == 0) {
 104                 hw->phy.id = (u32)(phy_id_high << 16);
 105                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 106                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 107                                               &phy_id_low);
 108                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 109                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 110         }
 111         return status;
 112 }
 113
 114 /**
 115  *  ixgbe_get_phy_type_from_id - Get the phy type
 116  *  @hw: pointer to hardware structure
 117  *
 118  **/
 119 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 120 {
 121         enum ixgbe_phy_type phy_type;
 122
 123         switch (phy_id) {
 124         case QT2022_PHY_ID:
 125                 phy_type = ixgbe_phy_qt;
 126                 break;
 127         default:
 128                 phy_type = ixgbe_phy_unknown;
 129                 break;
 130         }
 131
 132         return phy_type;
 133 }
 134
 135 /**
 136  *  ixgbe_reset_phy_generic - Performs a PHY reset
 137  *  @hw: pointer to hardware structure
 138  **/
 139 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 140 {
 141         /*
 142          * Perform soft PHY reset to the PHY_XS.
 143          * This will cause a soft reset to the PHY
 144          */
 145         return hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 146                                      IXGBE_MDIO_PHY_XS_DEV_TYPE,
 147                                      IXGBE_MDIO_PHY_XS_RESET);
 148 }
 149
 150 /**
 151  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 152  *  @hw: pointer to hardware structure
 153  *  @reg_addr: 32 bit address of PHY register to read
 154  *  @phy_data: Pointer to read data from PHY register
 155  **/
 156 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 157                                u32 device_type, u16 *phy_data)
 158 {
 159         u32 command;
 160         u32 i;
 161         u32 data;
 162         s32 status = 0;
 163         u16 gssr;
 164
 165         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 166                 gssr = IXGBE_GSSR_PHY1_SM;
 167         else
 168                 gssr = IXGBE_GSSR_PHY0_SM;
 169
 170         if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
 171                 status = IXGBE_ERR_SWFW_SYNC;
 172
 173         if (status == 0) {
 174                 /* Setup and write the address cycle command */
 175                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 176                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 177                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 178                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 179
 180                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 181
 182                 /*
 183                  * Check every 10 usec to see if the address cycle completed.
 184                  * The MDI Command bit will clear when the operation is
 185                  * complete
 186                  */
 187                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 188                         udelay(10);
 189
 190                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 191
 192                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 193                                 break;
 194                 }
 195
 196                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 197                         hw_dbg(hw, "PHY address command did not complete.\n");
 198                         status = IXGBE_ERR_PHY;
 199                 }
 200
 201                 if (status == 0) {
 202                         /*
 203                          * Address cycle complete, setup and write the read
 204                          * command
 205                          */
 206                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 207                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 208                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 209                                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 210
 211                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 212
 213                         /*
 214                          * Check every 10 usec to see if the address cycle
 215                          * completed. The MDI Command bit will clear when the
 216                          * operation is complete
 217                          */
 218                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 219                                 udelay(10);
 220
 221                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 222
 223                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 224                                         break;
 225                         }
 226
 227                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 228                                 hw_dbg(hw, "PHY read command didn't complete\n");
 229                                 status = IXGBE_ERR_PHY;
 230                         } else {
 231                                 /*
 232                                  * Read operation is complete.  Get the data
 233                                  * from MSRWD
 234                                  */
 235                                 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 236                                 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 237                                 *phy_data = (u16)(data);
 238                         }
 239                 }
 240
 241                 ixgbe_release_swfw_sync(hw, gssr);
 242         }
 243
 244         return status;
 245 }
 246
 247 /**
 248  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 249  *  @hw: pointer to hardware structure
 250  *  @reg_addr: 32 bit PHY register to write
 251  *  @device_type: 5 bit device type
 252  *  @phy_data: Data to write to the PHY register
 253  **/
 254 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 255                                 u32 device_type, u16 phy_data)
 256 {
 257         u32 command;
 258         u32 i;
 259         s32 status = 0;
 260         u16 gssr;
 261
 262         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 263                 gssr = IXGBE_GSSR_PHY1_SM;
 264         else
 265                 gssr = IXGBE_GSSR_PHY0_SM;
 266
 267         if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
 268                 status = IXGBE_ERR_SWFW_SYNC;
 269
 270         if (status == 0) {
 271                 /* Put the data in the MDI single read and write data register*/
 272                 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 273
 274                 /* Setup and write the address cycle command */
 275                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 276                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 277                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 278                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 279
 280                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 281
 282                 /*
 283                  * Check every 10 usec to see if the address cycle completed.
 284                  * The MDI Command bit will clear when the operation is
 285                  * complete
 286                  */
 287                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 288                         udelay(10);
 289
 290                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 291
 292                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 293                                 break;
 294                 }
 295
 296                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 297                         hw_dbg(hw, "PHY address cmd didn't complete\n");
 298                         status = IXGBE_ERR_PHY;
 299                 }
 300
 301                 if (status == 0) {
 302                         /*
 303                          * Address cycle complete, setup and write the write
 304                          * command
 305                          */
 306                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 307                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 308                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 309                                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 310
 311                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 312
 313                         /*
 314                          * Check every 10 usec to see if the address cycle
 315                          * completed. The MDI Command bit will clear when the
 316                          * operation is complete
 317                          */
 318                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 319                                 udelay(10);
 320
 321                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 322
 323                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 324                                         break;
 325                         }
 326
 327                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 328                                 hw_dbg(hw, "PHY address cmd didn't complete\n");
 329                                 status = IXGBE_ERR_PHY;
 330                         }
 331                 }
 332
 333                 ixgbe_release_swfw_sync(hw, gssr);
 334         }
 335
 336         return status;
 337 }
 338
 339 /**
 340  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 341  *  @hw: pointer to hardware structure
 342  *
 343  *  Restart autonegotiation and PHY and waits for completion.
 344  **/
 345 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 346 {
 347         s32 status = IXGBE_NOT_IMPLEMENTED;
 348         u32 time_out;
 349         u32 max_time_out = 10;
 350         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 351
 352         /*
 353          * Set advertisement settings in PHY based on autoneg_advertised
 354          * settings. If autoneg_advertised = 0, then advertise default values
 355          * tnx devices cannot be "forced" to a autoneg 10G and fail.  But can
 356          * for a 1G.
 357          */
 358         hw->phy.ops.read_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
 359                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 360
 361         if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
 362                 autoneg_reg &= 0xEFFF; /* 0 in bit 12 is 1G operation */
 363         else
 364                 autoneg_reg |= 0x1000; /* 1 in bit 12 is 10G/1G operation */
 365
 366         hw->phy.ops.write_reg(hw, IXGBE_MII_SPEED_SELECTION_REG,
 367                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 368
 369         /* Restart PHY autonegotiation and wait for completion */
 370         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 371                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 372
 373         autoneg_reg |= IXGBE_MII_RESTART;
 374
 375         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 376                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 377
 378         /* Wait for autonegotiation to finish */
 379         for (time_out = 0; time_out < max_time_out; time_out++) {
 380                 udelay(10);
 381                 /* Restart PHY autonegotiation and wait for completion */
 382                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 383                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 384                                               &autoneg_reg);
 385
 386                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 387                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
 388                         status = 0;
 389                         break;
 390                 }
 391         }
 392
 393         if (time_out == max_time_out)
 394                 status = IXGBE_ERR_LINK_SETUP;
 395
 396         return status;
 397 }
 398
 399 /**
 400  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 401  *  @hw: pointer to hardware structure
 402  *  @speed: new link speed
 403  *  @autoneg: true if autonegotiation enabled
 404  **/
 405 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 406                                        ixgbe_link_speed speed,
 407                                        bool autoneg,
 408                                        bool autoneg_wait_to_complete)
 409 {
 410
 411         /*
 412          * Clear autoneg_advertised and set new values based on input link
 413          * speed.
 414          */
 415         hw->phy.autoneg_advertised = 0;
 416
 417         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 418                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 419
 420         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 421                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 422
 423         /* Setup link based on the new speed settings */
 424         hw->phy.ops.setup_link(hw);
 425
 426         return 0;
 427 }
 428