drivers/net/irda/smsc-ircc2.c

   1 /*********************************************************************
   2  *
   3  * Description:   Driver for the SMC Infrared Communications Controller
   4  * Status:        Experimental.
   5  * Author:        Daniele Peri (peri@csai.unipa.it)
   6  * Created at:
   7  * Modified at:
   8  * Modified by:
   9  *
  10  *     Copyright (c) 2002      Daniele Peri
  11  *     All Rights Reserved.
  12  *     Copyright (c) 2002      Jean Tourrilhes
  13  *     Copyright (c) 2006      Linus Walleij
  14  *
  15  *
  16  * Based on smc-ircc.c:
  17  *
  18  *     Copyright (c) 2001      Stefani Seibold
  19  *     Copyright (c) 1999-2001 Dag Brattli
  20  *     Copyright (c) 1998-1999 Thomas Davis,
  21  *
  22  *      and irport.c:
  23  *
  24  *     Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
  25  *
  26  *
  27  *     This program is free software; you can redistribute it and/or
  28  *     modify it under the terms of the GNU General Public License as
  29  *     published by the Free Software Foundation; either version 2 of
  30  *     the License, or (at your option) any later version.
  31  *
  32  *     This program is distributed in the hope that it will be useful,
  33  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  34  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  35  *     GNU General Public License for more details.
  36  *
  37  *     You should have received a copy of the GNU General Public License
  38  *     along with this program; if not, write to the Free Software
  39  *     Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  40  *     MA 02111-1307 USA
  41  *
  42  ********************************************************************/
  43
  44 #include <linux/module.h>
  45 #include <linux/kernel.h>
  46 #include <linux/types.h>
  47 #include <linux/skbuff.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/ioport.h>
  50 #include <linux/delay.h>
  51 #include <linux/slab.h>
  52 #include <linux/init.h>
  53 #include <linux/rtnetlink.h>
  54 #include <linux/serial_reg.h>
  55 #include <linux/dma-mapping.h>
  56 #include <linux/pnp.h>
  57 #include <linux/platform_device.h>
  58
  59 #include <asm/io.h>
  60 #include <asm/dma.h>
  61 #include <asm/byteorder.h>
  62
  63 #include <linux/spinlock.h>
  64 #include <linux/pm.h>
  65 #ifdef CONFIG_PCI
  66 #include <linux/pci.h>
  67 #endif
  68
  69 #include <net/irda/wrapper.h>
  70 #include <net/irda/irda.h>
  71 #include <net/irda/irda_device.h>
  72
  73 #include "smsc-ircc2.h"
  74 #include "smsc-sio.h"
  75
  76
  77 MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
  78 MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
  79 MODULE_LICENSE("GPL");
  80
  81 static int smsc_nopnp = 1;
  82 module_param_named(nopnp, smsc_nopnp, bool, 0);
  83 MODULE_PARM_DESC(nopnp, "Do not use PNP to detect controller settings, defaults to true");
  84
  85 #define DMA_INVAL 255
  86 static int ircc_dma = DMA_INVAL;
  87 module_param(ircc_dma, int, 0);
  88 MODULE_PARM_DESC(ircc_dma, "DMA channel");
  89
  90 #define IRQ_INVAL 255
  91 static int ircc_irq = IRQ_INVAL;
  92 module_param(ircc_irq, int, 0);
  93 MODULE_PARM_DESC(ircc_irq, "IRQ line");
  94
  95 static int ircc_fir;
  96 module_param(ircc_fir, int, 0);
  97 MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
  98
  99 static int ircc_sir;
 100 module_param(ircc_sir, int, 0);
 101 MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
 102
 103 static int ircc_cfg;
 104 module_param(ircc_cfg, int, 0);
 105 MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
 106
 107 static int ircc_transceiver;
 108 module_param(ircc_transceiver, int, 0);
 109 MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");
 110
 111 /* Types */
 112
 113 #ifdef CONFIG_PCI
 114 struct smsc_ircc_subsystem_configuration {
 115         unsigned short vendor; /* PCI vendor ID */
 116         unsigned short device; /* PCI vendor ID */
 117         unsigned short subvendor; /* PCI subsystem vendor ID */
 118         unsigned short subdevice; /* PCI sybsystem device ID */
 119         unsigned short sir_io; /* I/O port for SIR */
 120         unsigned short fir_io; /* I/O port for FIR */
 121         unsigned char  fir_irq; /* FIR IRQ */
 122         unsigned char  fir_dma; /* FIR DMA */
 123         unsigned short cfg_base; /* I/O port for chip configuration */
 124         int (*preconfigure)(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf); /* Preconfig function */
 125         const char *name;       /* name shown as info */
 126 };
 127 #endif
 128
 129 struct smsc_transceiver {
 130         char *name;
 131         void (*set_for_speed)(int fir_base, u32 speed);
 132         int  (*probe)(int fir_base);
 133 };
 134
 135 struct smsc_chip {
 136         char *name;
 137         #if 0
 138         u8      type;
 139         #endif
 140         u16 flags;
 141         u8 devid;
 142         u8 rev;
 143 };
 144
 145 struct smsc_chip_address {
 146         unsigned int cfg_base;
 147         unsigned int type;
 148 };
 149
 150 /* Private data for each instance */
 151 struct smsc_ircc_cb {
 152         struct net_device *netdev;     /* Yes! we are some kind of netdevice */
 153         struct irlap_cb    *irlap; /* The link layer we are binded to */
 154
 155         chipio_t io;               /* IrDA controller information */
 156         iobuff_t tx_buff;          /* Transmit buffer */
 157         iobuff_t rx_buff;          /* Receive buffer */
 158         dma_addr_t tx_buff_dma;
 159         dma_addr_t rx_buff_dma;
 160
 161         struct qos_info qos;       /* QoS capabilities for this device */
 162
 163         spinlock_t lock;           /* For serializing operations */
 164
 165         __u32 new_speed;
 166         __u32 flags;               /* Interface flags */
 167
 168         int tx_buff_offsets[10];   /* Offsets between frames in tx_buff */
 169         int tx_len;                /* Number of frames in tx_buff */
 170
 171         int transceiver;
 172         struct platform_device *pldev;
 173 };
 174
 175 /* Constants */
 176
 177 #define SMSC_IRCC2_DRIVER_NAME                  "smsc-ircc2"
 178
 179 #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED        9600
 180 #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER        1
 181 #define SMSC_IRCC2_C_NET_TIMEOUT                0
 182 #define SMSC_IRCC2_C_SIR_STOP                   0
 183
 184 static const char *driver_name = SMSC_IRCC2_DRIVER_NAME;
 185
 186 /* Prototypes */
 187
 188 static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
 189 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
 190 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
 191 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
 192 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
 193 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
 194 static int  smsc_ircc_dma_receive(struct smsc_ircc_cb *self);
 195 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self);
 196 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
 197 static int  smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
 198 static int  smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
 199 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs);
 200 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self);
 201 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed);
 202 static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, u32 speed);
 203 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id);
 204 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
 205 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
 206 #if SMSC_IRCC2_C_SIR_STOP
 207 static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
 208 #endif
 209 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
 210 static int  smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
 211 static int  smsc_ircc_net_open(struct net_device *dev);
 212 static int  smsc_ircc_net_close(struct net_device *dev);
 213 static int  smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 214 #if SMSC_IRCC2_C_NET_TIMEOUT
 215 static void smsc_ircc_timeout(struct net_device *dev);
 216 #endif
 217 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
 218 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
 219 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
 220 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
 221
 222 /* Probing */
 223 static int __init smsc_ircc_look_for_chips(void);
 224 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type);
 225 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
 226 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type);
 227 static int __init smsc_superio_fdc(unsigned short cfg_base);
 228 static int __init smsc_superio_lpc(unsigned short cfg_base);
 229 #ifdef CONFIG_PCI
 230 static int __init preconfigure_smsc_chip(struct smsc_ircc_subsystem_configuration *conf);
 231 static int __init preconfigure_through_82801(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
 232 static void __init preconfigure_ali_port(struct pci_dev *dev,
 233                                          unsigned short port);
 234 static int __init preconfigure_through_ali(struct pci_dev *dev, struct smsc_ircc_subsystem_configuration *conf);
 235 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
 236                                                     unsigned short ircc_fir,
 237                                                     unsigned short ircc_sir,
 238                                                     unsigned char ircc_dma,
 239                                                     unsigned char ircc_irq);
 240 #endif
 241
 242 /* Transceivers specific functions */
 243
 244 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
 245 static int  smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
 246 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
 247 static int  smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
 248 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
 249 static int  smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
 250
 251 /* Power Management */
 252
 253 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state);
 254 static int smsc_ircc_resume(struct platform_device *dev);
 255
 256 static struct platform_driver smsc_ircc_driver = {
 257         .suspend        = smsc_ircc_suspend,
 258         .resume         = smsc_ircc_resume,
 259         .driver         = {
 260                 .name   = SMSC_IRCC2_DRIVER_NAME,
 261         },
 262 };
 263
 264 /* Transceivers for SMSC-ircc */
 265
 266 static struct smsc_transceiver smsc_transceivers[] =
 267 {
 268         { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800 },
 269         { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select },
 270         { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc },
 271         { NULL, NULL }
 272 };
 273 #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (ARRAY_SIZE(smsc_transceivers) - 1)
 274
 275 /*  SMC SuperIO chipsets definitions */
 276
 277 #define KEY55_1 0       /* SuperIO Configuration mode with Key <0x55> */
 278 #define KEY55_2 1       /* SuperIO Configuration mode with Key <0x55,0x55> */
 279 #define NoIRDA  2       /* SuperIO Chip has no IRDA Port */
 280 #define SIR     0       /* SuperIO Chip has only slow IRDA */
 281 #define FIR     4       /* SuperIO Chip has fast IRDA */
 282 #define SERx4   8       /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
 283
 284 static struct smsc_chip __initdata fdc_chips_flat[] =
 285 {
 286         /* Base address 0x3f0 or 0x370 */
 287         { "37C44",      KEY55_1|NoIRDA,         0x00, 0x00 }, /* This chip cannot be detected */
 288         { "37C665GT",   KEY55_2|NoIRDA,         0x65, 0x01 },
 289         { "37C665GT",   KEY55_2|NoIRDA,         0x66, 0x01 },
 290         { "37C669",     KEY55_2|SIR|SERx4,      0x03, 0x02 },
 291         { "37C669",     KEY55_2|SIR|SERx4,      0x04, 0x02 }, /* ID? */
 292         { "37C78",      KEY55_2|NoIRDA,         0x78, 0x00 },
 293         { "37N769",     KEY55_1|FIR|SERx4,      0x28, 0x00 },
 294         { "37N869",     KEY55_1|FIR|SERx4,      0x29, 0x00 },
 295         { NULL }
 296 };
 297
 298 static struct smsc_chip __initdata fdc_chips_paged[] =
 299 {
 300         /* Base address 0x3f0 or 0x370 */
 301         { "37B72X",     KEY55_1|SIR|SERx4,      0x4c, 0x00 },
 302         { "37B77X",     KEY55_1|SIR|SERx4,      0x43, 0x00 },
 303         { "37B78X",     KEY55_1|SIR|SERx4,      0x44, 0x00 },
 304         { "37B80X",     KEY55_1|SIR|SERx4,      0x42, 0x00 },
 305         { "37C67X",     KEY55_1|FIR|SERx4,      0x40, 0x00 },
 306         { "37C93X",     KEY55_2|SIR|SERx4,      0x02, 0x01 },
 307         { "37C93XAPM",  KEY55_1|SIR|SERx4,      0x30, 0x01 },
 308         { "37C93XFR",   KEY55_2|FIR|SERx4,      0x03, 0x01 },
 309         { "37M707",     KEY55_1|SIR|SERx4,      0x42, 0x00 },
 310         { "37M81X",     KEY55_1|SIR|SERx4,      0x4d, 0x00 },
 311         { "37N958FR",   KEY55_1|FIR|SERx4,      0x09, 0x04 },
 312         { "37N971",     KEY55_1|FIR|SERx4,      0x0a, 0x00 },
 313         { "37N972",     KEY55_1|FIR|SERx4,      0x0b, 0x00 },
 314         { NULL }
 315 };
 316
 317 static struct smsc_chip __initdata lpc_chips_flat[] =
 318 {
 319         /* Base address 0x2E or 0x4E */
 320         { "47N227",     KEY55_1|FIR|SERx4,      0x5a, 0x00 },
 321         { "47N227",     KEY55_1|FIR|SERx4,      0x7a, 0x00 },
 322         { "47N267",     KEY55_1|FIR|SERx4,      0x5e, 0x00 },
 323         { NULL }
 324 };
 325
 326 static struct smsc_chip __initdata lpc_chips_paged[] =
 327 {
 328         /* Base address 0x2E or 0x4E */
 329         { "47B27X",     KEY55_1|SIR|SERx4,      0x51, 0x00 },
 330         { "47B37X",     KEY55_1|SIR|SERx4,      0x52, 0x00 },
 331         { "47M10X",     KEY55_1|SIR|SERx4,      0x59, 0x00 },
 332         { "47M120",     KEY55_1|NoIRDA|SERx4,   0x5c, 0x00 },
 333         { "47M13X",     KEY55_1|SIR|SERx4,      0x59, 0x00 },
 334         { "47M14X",     KEY55_1|SIR|SERx4,      0x5f, 0x00 },
 335         { "47N252",     KEY55_1|FIR|SERx4,      0x0e, 0x00 },
 336         { "47S42X",     KEY55_1|SIR|SERx4,      0x57, 0x00 },
 337         { NULL }
 338 };
 339
 340 #define SMSCSIO_TYPE_FDC        1
 341 #define SMSCSIO_TYPE_LPC        2
 342 #define SMSCSIO_TYPE_FLAT       4
 343 #define SMSCSIO_TYPE_PAGED      8
 344
 345 static struct smsc_chip_address __initdata possible_addresses[] =
 346 {
 347         { 0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 348         { 0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 349         { 0xe0,  SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 350         { 0x2e,  SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 351         { 0x4e,  SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED },
 352         { 0, 0 }
 353 };
 354
 355 /* Globals */
 356
 357 static struct smsc_ircc_cb *dev_self[] = { NULL, NULL };
 358 static unsigned short dev_count;
 359
 360 static inline void register_bank(int iobase, int bank)
 361 {
 362         outb(((inb(iobase + IRCC_MASTER) & 0xf0) | (bank & 0x07)),
 363                iobase + IRCC_MASTER);
 364 }
 365
 366 /* PNP hotplug support */
 367 static const struct pnp_device_id smsc_ircc_pnp_table[] = {
 368         { .id = "SMCf010", .driver_data = 0 },
 369         /* and presumably others */
 370         { }
 371 };
 372 MODULE_DEVICE_TABLE(pnp, smsc_ircc_pnp_table);
 373
 374 static int pnp_driver_registered;
 375
 376 #ifdef CONFIG_PNP
 377 static int __init smsc_ircc_pnp_probe(struct pnp_dev *dev,
 378                                       const struct pnp_device_id *dev_id)
 379 {
 380         unsigned int firbase, sirbase;
 381         u8 dma, irq;
 382
 383         if (!(pnp_port_valid(dev, 0) && pnp_port_valid(dev, 1) &&
 384               pnp_dma_valid(dev, 0) && pnp_irq_valid(dev, 0)))
 385                 return -EINVAL;
 386
 387         sirbase = pnp_port_start(dev, 0);
 388         firbase = pnp_port_start(dev, 1);
 389         dma = pnp_dma(dev, 0);
 390         irq = pnp_irq(dev, 0);
 391
 392         if (smsc_ircc_open(firbase, sirbase, dma, irq))
 393                 return -ENODEV;
 394
 395         return 0;
 396 }
 397
 398 static struct pnp_driver smsc_ircc_pnp_driver = {
 399         .name           = "smsc-ircc2",
 400         .id_table       = smsc_ircc_pnp_table,
 401         .probe          = smsc_ircc_pnp_probe,
 402 };
 403 #else /* CONFIG_PNP */
 404 static struct pnp_driver smsc_ircc_pnp_driver;
 405 #endif
 406
 407 /*******************************************************************************
 408  *
 409  *
 410  * SMSC-ircc stuff
 411  *
 412  *
 413  *******************************************************************************/
 414
 415 static int __init smsc_ircc_legacy_probe(void)
 416 {
 417         int ret = 0;
 418
 419 #ifdef CONFIG_PCI
 420         if (smsc_ircc_preconfigure_subsystems(ircc_cfg, ircc_fir, ircc_sir, ircc_dma, ircc_irq) < 0) {
 421                 /* Ignore errors from preconfiguration */
 422                 IRDA_ERROR("%s, Preconfiguration failed !\n", driver_name);
 423         }
 424 #endif
 425
 426         if (ircc_fir > 0 && ircc_sir > 0) {
 427                 IRDA_MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
 428                 IRDA_MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
 429
 430                 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq))
 431                         ret = -ENODEV;
 432         } else {
 433                 ret = -ENODEV;
 434
 435                 /* try user provided configuration register base address */
 436                 if (ircc_cfg > 0) {
 437                         IRDA_MESSAGE(" Overriding configuration address "
 438                                      "0x%04x\n", ircc_cfg);
 439                         if (!smsc_superio_fdc(ircc_cfg))
 440                                 ret = 0;
 441                         if (!smsc_superio_lpc(ircc_cfg))
 442                                 ret = 0;
 443                 }
 444
 445                 if (smsc_ircc_look_for_chips() > 0)
 446                         ret = 0;
 447         }
 448         return ret;
 449 }
 450
 451 /*
 452  * Function smsc_ircc_init ()
 453  *
 454  *    Initialize chip. Just try to find out how many chips we are dealing with
 455  *    and where they are
 456  */
 457 static int __init smsc_ircc_init(void)
 458 {
 459         int ret;
 460
 461         IRDA_DEBUG(1, "%s\n", __func__);
 462
 463         ret = platform_driver_register(&smsc_ircc_driver);
 464         if (ret) {
 465                 IRDA_ERROR("%s, Can't register driver!\n", driver_name);
 466                 return ret;
 467         }
 468
 469         dev_count = 0;
 470
 471         if (smsc_nopnp || !pnp_platform_devices ||
 472             ircc_cfg || ircc_fir || ircc_sir ||
 473             ircc_dma != DMA_INVAL || ircc_irq != IRQ_INVAL) {
 474                 ret = smsc_ircc_legacy_probe();
 475         } else {
 476                 if (pnp_register_driver(&smsc_ircc_pnp_driver) == 0)
 477                         pnp_driver_registered = 1;
 478         }
 479
 480         if (ret) {
 481                 if (pnp_driver_registered)
 482                         pnp_unregister_driver(&smsc_ircc_pnp_driver);
 483                 platform_driver_unregister(&smsc_ircc_driver);
 484         }
 485
 486         return ret;
 487 }
 488
 489 static int smsc_ircc_net_xmit(struct sk_buff *skb, struct net_device *dev)
 490 {
 491         struct smsc_ircc_cb *self = netdev_priv(dev);
 492
 493         if (self->io.speed > 115200)
 494                 return  smsc_ircc_hard_xmit_fir(skb, dev);
 495         else
 496                 return  smsc_ircc_hard_xmit_sir(skb, dev);
 497 }
 498
 499 static const struct net_device_ops smsc_ircc_netdev_ops = {
 500         .ndo_open       = smsc_ircc_net_open,
 501         .ndo_stop       = smsc_ircc_net_close,
 502         .ndo_do_ioctl   = smsc_ircc_net_ioctl,
 503         .ndo_start_xmit = smsc_ircc_net_xmit,
 504 #if SMSC_IRCC2_C_NET_TIMEOUT
 505         .ndo_tx_timeout = smsc_ircc_timeout,
 506 #endif
 507 };
 508
 509 /*
 510  * Function smsc_ircc_open (firbase, sirbase, dma, irq)
 511  *
 512  *    Try to open driver instance
 513  *
 514  */
 515 static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
 516 {
 517         struct smsc_ircc_cb *self;
 518         struct net_device *dev;
 519         int err;
 520
 521         IRDA_DEBUG(1, "%s\n", __func__);
 522
 523         err = smsc_ircc_present(fir_base, sir_base);
 524         if (err)
 525                 goto err_out;
 526
 527         err = -ENOMEM;
 528         if (dev_count >= ARRAY_SIZE(dev_self)) {
 529                 IRDA_WARNING("%s(), too many devices!\n", __func__);
 530                 goto err_out1;
 531         }
 532
 533         /*
 534          *  Allocate new instance of the driver
 535          */
 536         dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
 537         if (!dev) {
 538                 IRDA_WARNING("%s() can't allocate net device\n", __func__);
 539                 goto err_out1;
 540         }
 541
 542 #if SMSC_IRCC2_C_NET_TIMEOUT
 543         dev->watchdog_timeo  = HZ * 2;  /* Allow enough time for speed change */
 544 #endif
 545         dev->netdev_ops = &smsc_ircc_netdev_ops;
 546
 547         self = netdev_priv(dev);
 548         self->netdev = dev;
 549
 550         /* Make ifconfig display some details */
 551         dev->base_addr = self->io.fir_base = fir_base;
 552         dev->irq = self->io.irq = irq;
 553
 554         /* Need to store self somewhere */
 555         dev_self[dev_count] = self;
 556         spin_lock_init(&self->lock);
 557
 558         self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
 559         self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
 560
 561         self->rx_buff.head =
 562                 dma_alloc_coherent(NULL, self->rx_buff.truesize,
 563                                    &self->rx_buff_dma, GFP_KERNEL);
 564         if (self->rx_buff.head == NULL) {
 565                 IRDA_ERROR("%s, Can't allocate memory for receive buffer!\n",
 566                            driver_name);
 567                 goto err_out2;
 568         }
 569
 570         self->tx_buff.head =
 571                 dma_alloc_coherent(NULL, self->tx_buff.truesize,
 572                                    &self->tx_buff_dma, GFP_KERNEL);
 573         if (self->tx_buff.head == NULL) {
 574                 IRDA_ERROR("%s, Can't allocate memory for transmit buffer!\n",
 575                            driver_name);
 576                 goto err_out3;
 577         }
 578
 579         memset(self->rx_buff.head, 0, self->rx_buff.truesize);
 580         memset(self->tx_buff.head, 0, self->tx_buff.truesize);
 581
 582         self->rx_buff.in_frame = FALSE;
 583         self->rx_buff.state = OUTSIDE_FRAME;
 584         self->tx_buff.data = self->tx_buff.head;
 585         self->rx_buff.data = self->rx_buff.head;
 586
 587         smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
 588         smsc_ircc_setup_qos(self);
 589         smsc_ircc_init_chip(self);
 590
 591         if (ircc_transceiver > 0  &&
 592             ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
 593                 self->transceiver = ircc_transceiver;
 594         else
 595                 smsc_ircc_probe_transceiver(self);
 596
 597         err = register_netdev(self->netdev);
 598         if (err) {
 599                 IRDA_ERROR("%s, Network device registration failed!\n",
 600                            driver_name);
 601                 goto err_out4;
 602         }
 603
 604         self->pldev = platform_device_register_simple(SMSC_IRCC2_DRIVER_NAME,
 605                                                       dev_count, NULL, 0);
 606         if (IS_ERR(self->pldev)) {
 607                 err = PTR_ERR(self->pldev);
 608                 goto err_out5;
 609         }
 610         platform_set_drvdata(self->pldev, self);
 611
 612         IRDA_MESSAGE("IrDA: Registered device %s\n", dev->name);
 613         dev_count++;
 614
 615         return 0;
 616
 617  err_out5:
 618         unregister_netdev(self->netdev);
 619
 620  err_out4:
 621         dma_free_coherent(NULL, self->tx_buff.truesize,
 622                           self->tx_buff.head, self->tx_buff_dma);
 623  err_out3:
 624         dma_free_coherent(NULL, self->rx_buff.truesize,
 625                           self->rx_buff.head, self->rx_buff_dma);
 626  err_out2:
 627         free_netdev(self->netdev);
 628         dev_self[dev_count] = NULL;
 629  err_out1:
 630         release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
 631         release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
 632  err_out:
 633         return err;
 634 }
 635
 636 /*
 637  * Function smsc_ircc_present(fir_base, sir_base)
 638  *
 639  *    Check the smsc-ircc chip presence
 640  *
 641  */
 642 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
 643 {
 644         unsigned char low, high, chip, config, dma, irq, version;
 645
 646         if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
 647                             driver_name)) {
 648                 IRDA_WARNING("%s: can't get fir_base of 0x%03x\n",
 649                              __func__, fir_base);
 650                 goto out1;
 651         }
 652
 653         if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
 654                             driver_name)) {
 655                 IRDA_WARNING("%s: can't get sir_base of 0x%03x\n",
 656                              __func__, sir_base);
 657                 goto out2;
 658         }
 659
 660         register_bank(fir_base, 3);
 661
 662         high    = inb(fir_base + IRCC_ID_HIGH);
 663         low     = inb(fir_base + IRCC_ID_LOW);
 664         chip    = inb(fir_base + IRCC_CHIP_ID);
 665         version = inb(fir_base + IRCC_VERSION);
 666         config  = inb(fir_base + IRCC_INTERFACE);
 667         dma     = config & IRCC_INTERFACE_DMA_MASK;
 668         irq     = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
 669
 670         if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
 671                 IRDA_WARNING("%s(), addr 0x%04x - no device found!\n",
 672                              __func__, fir_base);
 673                 goto out3;
 674         }
 675         IRDA_MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
 676                      "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
 677                      chip & 0x0f, version, fir_base, sir_base, dma, irq);
 678
 679         return 0;
 680
 681  out3:
 682         release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
 683  out2:
 684         release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
 685  out1:
 686         return -ENODEV;
 687 }
 688
 689 /*
 690  * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
 691  *
 692  *    Setup I/O
 693  *
 694  */
 695 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
 696                                unsigned int fir_base, unsigned int sir_base,
 697                                u8 dma, u8 irq)
 698 {
 699         unsigned char config, chip_dma, chip_irq;
 700
 701         register_bank(fir_base, 3);
 702         config = inb(fir_base + IRCC_INTERFACE);
 703         chip_dma = config & IRCC_INTERFACE_DMA_MASK;
 704         chip_irq = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
 705
 706         self->io.fir_base  = fir_base;
 707         self->io.sir_base  = sir_base;
 708         self->io.fir_ext   = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
 709         self->io.sir_ext   = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
 710         self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
 711         self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
 712
 713         if (irq != IRQ_INVAL) {
 714                 if (irq != chip_irq)
 715                         IRDA_MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
 716                                      driver_name, chip_irq, irq);
 717                 self->io.irq = irq;
 718         } else
 719                 self->io.irq = chip_irq;
 720
 721         if (dma != DMA_INVAL) {
 722                 if (dma != chip_dma)
 723                         IRDA_MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
 724                                      driver_name, chip_dma, dma);
 725                 self->io.dma = dma;
 726         } else
 727                 self->io.dma = chip_dma;
 728
 729 }
 730
 731 /*
 732  * Function smsc_ircc_setup_qos(self)
 733  *
 734  *    Setup qos
 735  *
 736  */
 737 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
 738 {
 739         /* Initialize QoS for this device */
 740         irda_init_max_qos_capabilies(&self->qos);
 741
 742         self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
 743                 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
 744
 745         self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
 746         self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
 747         irda_qos_bits_to_value(&self->qos);
 748 }
 749
 750 /*
 751  * Function smsc_ircc_init_chip(self)
 752  *
 753  *    Init chip
 754  *
 755  */
 756 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
 757 {
 758         int iobase = self->io.fir_base;
 759
 760         register_bank(iobase, 0);
 761         outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
 762         outb(0x00, iobase + IRCC_MASTER);
 763
 764         register_bank(iobase, 1);
 765         outb(((inb(iobase + IRCC_SCE_CFGA) & 0x87) | IRCC_CFGA_IRDA_SIR_A),
 766              iobase + IRCC_SCE_CFGA);
 767
 768 #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
 769         outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
 770              iobase + IRCC_SCE_CFGB);
 771 #else
 772         outb(((inb(iobase + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
 773              iobase + IRCC_SCE_CFGB);
 774 #endif
 775         (void) inb(iobase + IRCC_FIFO_THRESHOLD);
 776         outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase + IRCC_FIFO_THRESHOLD);
 777
 778         register_bank(iobase, 4);
 779         outb((inb(iobase + IRCC_CONTROL) & 0x30), iobase + IRCC_CONTROL);
 780
 781         register_bank(iobase, 0);
 782         outb(0, iobase + IRCC_LCR_A);
 783
 784         smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
 785
 786         /* Power on device */
 787         outb(0x00, iobase + IRCC_MASTER);
 788 }
 789
 790 /*
 791  * Function smsc_ircc_net_ioctl (dev, rq, cmd)
 792  *
 793  *    Process IOCTL commands for this device
 794  *
 795  */
 796 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 797 {
 798         struct if_irda_req *irq = (struct if_irda_req *) rq;
 799         struct smsc_ircc_cb *self;
 800         unsigned long flags;
 801         int ret = 0;
 802
 803         IRDA_ASSERT(dev != NULL, return -1;);
 804
 805         self = netdev_priv(dev);
 806
 807         IRDA_ASSERT(self != NULL, return -1;);
 808
 809         IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __func__, dev->name, cmd);
 810
 811         switch (cmd) {
 812         case SIOCSBANDWIDTH: /* Set bandwidth */
 813                 if (!capable(CAP_NET_ADMIN))
 814                         ret = -EPERM;
 815                 else {
 816                         /* Make sure we are the only one touching
 817                          * self->io.speed and the hardware - Jean II */
 818                         spin_lock_irqsave(&self->lock, flags);
 819                         smsc_ircc_change_speed(self, irq->ifr_baudrate);
 820                         spin_unlock_irqrestore(&self->lock, flags);
 821                 }
 822                 break;
 823         case SIOCSMEDIABUSY: /* Set media busy */
 824                 if (!capable(CAP_NET_ADMIN)) {
 825                         ret = -EPERM;
 826                         break;
 827                 }
 828
 829                 irda_device_set_media_busy(self->netdev, TRUE);
 830                 break;
 831         case SIOCGRECEIVING: /* Check if we are receiving right now */
 832                 irq->ifr_receiving = smsc_ircc_is_receiving(self);
 833                 break;
 834         #if 0
 835         case SIOCSDTRRTS:
 836                 if (!capable(CAP_NET_ADMIN)) {
 837                         ret = -EPERM;
 838                         break;
 839                 }
 840                 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
 841                 break;
 842         #endif
 843         default:
 844                 ret = -EOPNOTSUPP;
 845         }
 846
 847         return ret;
 848 }
 849
 850 #if SMSC_IRCC2_C_NET_TIMEOUT
 851 /*
 852  * Function smsc_ircc_timeout (struct net_device *dev)
 853  *
 854  *    The networking timeout management.
 855  *
 856  */
 857
 858 static void smsc_ircc_timeout(struct net_device *dev)
 859 {
 860         struct smsc_ircc_cb *self = netdev_priv(dev);
 861         unsigned long flags;
 862
 863         IRDA_WARNING("%s: transmit timed out, changing speed to: %d\n",
 864                      dev->name, self->io.speed);
 865         spin_lock_irqsave(&self->lock, flags);
 866         smsc_ircc_sir_start(self);
 867         smsc_ircc_change_speed(self, self->io.speed);
 868         dev->trans_start = jiffies;
 869         netif_wake_queue(dev);
 870         spin_unlock_irqrestore(&self->lock, flags);
 871 }
 872 #endif
 873
 874 /*
 875  * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
 876  *
 877  *    Transmits the current frame until FIFO is full, then
 878  *    waits until the next transmit interrupt, and continues until the
 879  *    frame is transmitted.
 880  */
 881 static int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
 882 {
 883         struct smsc_ircc_cb *self;
 884         unsigned long flags;
 885         s32 speed;
 886
 887         IRDA_DEBUG(1, "%s\n", __func__);
 888
 889         IRDA_ASSERT(dev != NULL, return 0;);
 890
 891         self = netdev_priv(dev);
 892         IRDA_ASSERT(self != NULL, return 0;);
 893
 894         netif_stop_queue(dev);
 895
 896         /* Make sure test of self->io.speed & speed change are atomic */
 897         spin_lock_irqsave(&self->lock, flags);
 898
 899         /* Check if we need to change the speed */
 900         speed = irda_get_next_speed(skb);
 901         if (speed != self->io.speed && speed != -1) {
 902                 /* Check for empty frame */
 903                 if (!skb->len) {
 904                         /*
 905                          * We send frames one by one in SIR mode (no
 906                          * pipelining), so at this point, if we were sending
 907                          * a previous frame, we just received the interrupt
 908                          * telling us it is finished (UART_IIR_THRI).
 909                          * Therefore, waiting for the transmitter to really
 910                          * finish draining the fifo won't take too long.
 911                          * And the interrupt handler is not expected to run.
 912                          * - Jean II */
 913                         smsc_ircc_sir_wait_hw_transmitter_finish(self);
 914                         smsc_ircc_change_speed(self, speed);
 915                         spin_unlock_irqrestore(&self->lock, flags);
 916                         dev_kfree_skb(skb);
 917                         return 0;
 918                 }
 919                 self->new_speed = speed;
 920         }
 921
 922         /* Init tx buffer */
 923         self->tx_buff.data = self->tx_buff.head;
 924
 925         /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
 926         self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
 927                                            self->tx_buff.truesize);
 928
 929         dev->stats.tx_bytes += self->tx_buff.len;
 930
 931         /* Turn on transmit finished interrupt. Will fire immediately!  */
 932         outb(UART_IER_THRI, self->io.sir_base + UART_IER);
 933
 934         spin_unlock_irqrestore(&self->lock, flags);
 935
 936         dev_kfree_skb(skb);
 937
 938         return 0;
 939 }
 940
 941 /*
 942  * Function smsc_ircc_set_fir_speed (self, baud)
 943  *
 944  *    Change the speed of the device
 945  *
 946  */
 947 static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
 948 {
 949         int fir_base, ir_mode, ctrl, fast;
 950
 951         IRDA_ASSERT(self != NULL, return;);
 952         fir_base = self->io.fir_base;
 953
 954         self->io.speed = speed;
 955
 956         switch (speed) {
 957         default:
 958         case 576000:
 959                 ir_mode = IRCC_CFGA_IRDA_HDLC;
 960                 ctrl = IRCC_CRC;
 961                 fast = 0;
 962                 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __func__);
 963                 break;
 964         case 1152000:
 965                 ir_mode = IRCC_CFGA_IRDA_HDLC;
 966                 ctrl = IRCC_1152 | IRCC_CRC;
 967                 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
 968                 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
 969                            __func__);
 970                 break;
 971         case 4000000:
 972                 ir_mode = IRCC_CFGA_IRDA_4PPM;
 973                 ctrl = IRCC_CRC;
 974                 fast = IRCC_LCR_A_FAST;
 975                 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
 976                            __func__);
 977                 break;
 978         }
 979         #if 0
 980         Now in tranceiver!
 981         /* This causes an interrupt */
 982         register_bank(fir_base, 0);
 983         outb((inb(fir_base + IRCC_LCR_A) &  0xbf) | fast, fir_base + IRCC_LCR_A);
 984         #endif
 985
 986         register_bank(fir_base, 1);
 987         outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base + IRCC_SCE_CFGA);
 988
 989         register_bank(fir_base, 4);
 990         outb((inb(fir_base + IRCC_CONTROL) & 0x30) | ctrl, fir_base + IRCC_CONTROL);
 991 }
 992
 993 /*
 994  * Function smsc_ircc_fir_start(self)
 995  *
 996  *    Change the speed of the device
 997  *
 998  */
 999 static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
1000 {
1001         struct net_device *dev;
1002         int fir_base;
1003
1004         IRDA_DEBUG(1, "%s\n", __func__);
1005
1006         IRDA_ASSERT(self != NULL, return;);
1007         dev = self->netdev;
1008         IRDA_ASSERT(dev != NULL, return;);
1009
1010         fir_base = self->io.fir_base;
1011
1012         /* Reset everything */
1013
1014         /* Clear FIFO */
1015         outb(inb(fir_base + IRCC_LCR_A) | IRCC_LCR_A_FIFO_RESET, fir_base + IRCC_LCR_A);
1016
1017         /* Enable interrupt */
1018         /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base + IRCC_IER);*/
1019
1020         register_bank(fir_base, 1);
1021
1022         /* Select the TX/RX interface */
1023 #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
1024         outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
1025              fir_base + IRCC_SCE_CFGB);
1026 #else
1027         outb(((inb(fir_base + IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
1028              fir_base + IRCC_SCE_CFGB);
1029 #endif
1030         (void) inb(fir_base + IRCC_FIFO_THRESHOLD);
1031
1032         /* Enable SCE interrupts */
1033         outb(0, fir_base + IRCC_MASTER);
1034         register_bank(fir_base, 0);
1035         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, fir_base + IRCC_IER);
1036         outb(IRCC_MASTER_INT_EN, fir_base + IRCC_MASTER);
1037 }
1038
1039 /*
1040  * Function smsc_ircc_fir_stop(self, baud)
1041  *
1042  *    Change the speed of the device
1043  *
1044  */
1045 static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
1046 {
1047         int fir_base;
1048
1049         IRDA_DEBUG(1, "%s\n", __func__);
1050
1051         IRDA_ASSERT(self != NULL, return;);
1052
1053         fir_base = self->io.fir_base;
1054         register_bank(fir_base, 0);
1055         /*outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);*/
1056         outb(inb(fir_base + IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base + IRCC_LCR_B);
1057 }
1058
1059
1060 /*
1061  * Function smsc_ircc_change_speed(self, baud)
1062  *
1063  *    Change the speed of the device
1064  *
1065  * This function *must* be called with spinlock held, because it may
1066  * be called from the irq handler. - Jean II
1067  */
1068 static void smsc_ircc_change_speed(struct smsc_ircc_cb *self, u32 speed)
1069 {
1070         struct net_device *dev;
1071         int last_speed_was_sir;
1072
1073         IRDA_DEBUG(0, "%s() changing speed to: %d\n", __func__, speed);
1074
1075         IRDA_ASSERT(self != NULL, return;);
1076         dev = self->netdev;
1077
1078         last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
1079
1080         #if 0
1081         /* Temp Hack */
1082         speed= 1152000;
1083         self->io.speed = speed;
1084         last_speed_was_sir = 0;
1085         smsc_ircc_fir_start(self);
1086         #endif
1087
1088         if (self->io.speed == 0)
1089                 smsc_ircc_sir_start(self);
1090
1091         #if 0
1092         if (!last_speed_was_sir) speed = self->io.speed;
1093         #endif
1094
1095         if (self->io.speed != speed)
1096                 smsc_ircc_set_transceiver_for_speed(self, speed);
1097
1098         self->io.speed = speed;
1099
1100         if (speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1101                 if (!last_speed_was_sir) {
1102                         smsc_ircc_fir_stop(self);
1103                         smsc_ircc_sir_start(self);
1104                 }
1105                 smsc_ircc_set_sir_speed(self, speed);
1106         } else {
1107                 if (last_speed_was_sir) {
1108                         #if SMSC_IRCC2_C_SIR_STOP
1109                         smsc_ircc_sir_stop(self);
1110                         #endif
1111                         smsc_ircc_fir_start(self);
1112                 }
1113                 smsc_ircc_set_fir_speed(self, speed);
1114
1115                 #if 0
1116                 self->tx_buff.len = 10;
1117                 self->tx_buff.data = self->tx_buff.head;
1118
1119                 smsc_ircc_dma_xmit(self, 4000);
1120                 #endif
1121                 /* Be ready for incoming frames */
1122                 smsc_ircc_dma_receive(self);
1123         }
1124
1125         netif_wake_queue(dev);
1126 }
1127
1128 /*
1129  * Function smsc_ircc_set_sir_speed (self, speed)
1130  *
1131  *    Set speed of IrDA port to specified baudrate
1132  *
1133  */
1134 static void smsc_ircc_set_sir_speed(struct smsc_ircc_cb *self, __u32 speed)
1135 {
1136         int iobase;
1137         int fcr;    /* FIFO control reg */
1138         int lcr;    /* Line control reg */
1139         int divisor;
1140
1141         IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __func__, speed);
1142
1143         IRDA_ASSERT(self != NULL, return;);
1144         iobase = self->io.sir_base;
1145
1146         /* Update accounting for new speed */
1147         self->io.speed = speed;
1148
1149         /* Turn off interrupts */
1150         outb(0, iobase + UART_IER);
1151
1152         divisor = SMSC_IRCC2_MAX_SIR_SPEED / speed;
1153
1154         fcr = UART_FCR_ENABLE_FIFO;
1155
1156         /*
1157          * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1158          * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1159          * about this timeout since it will always be fast enough.
1160          */
1161         fcr |= self->io.speed < 38400 ?
1162                 UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
1163
1164         /* IrDA ports use 8N1 */
1165         lcr = UART_LCR_WLEN8;
1166
1167         outb(UART_LCR_DLAB | lcr, iobase + UART_LCR); /* Set DLAB */
1168         outb(divisor & 0xff,      iobase + UART_DLL); /* Set speed */
1169         outb(divisor >> 8,        iobase + UART_DLM);
1170         outb(lcr,                 iobase + UART_LCR); /* Set 8N1 */
1171         outb(fcr,                 iobase + UART_FCR); /* Enable FIFO's */
1172
1173         /* Turn on interrups */
1174         outb(UART_IER_RLSI | UART_IER_RDI | UART_IER_THRI, iobase + UART_IER);
1175
1176         IRDA_DEBUG(2, "%s() speed changed to: %d\n", __func__, speed);
1177 }
1178
1179
1180 /*
1181  * Function smsc_ircc_hard_xmit_fir (skb, dev)
1182  *
1183  *    Transmit the frame!
1184  *
1185  */
1186 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1187 {
1188         struct smsc_ircc_cb *self;
1189         unsigned long flags;
1190         s32 speed;
1191         int mtt;
1192
1193         IRDA_ASSERT(dev != NULL, return 0;);
1194         self = netdev_priv(dev);
1195         IRDA_ASSERT(self != NULL, return 0;);
1196
1197         netif_stop_queue(dev);
1198
1199         /* Make sure test of self->io.speed & speed change are atomic */
1200         spin_lock_irqsave(&self->lock, flags);
1201
1202         /* Check if we need to change the speed after this frame */
1203         speed = irda_get_next_speed(skb);
1204         if (speed != self->io.speed && speed != -1) {
1205                 /* Check for empty frame */
1206                 if (!skb->len) {
1207                         /* Note : you should make sure that speed changes
1208                          * are not going to corrupt any outgoing frame.
1209                          * Look at nsc-ircc for the gory details - Jean II */
1210                         smsc_ircc_change_speed(self, speed);
1211                         spin_unlock_irqrestore(&self->lock, flags);
1212                         dev_kfree_skb(skb);
1213                         return 0;
1214                 }
1215
1216                 self->new_speed = speed;
1217         }
1218
1219         skb_copy_from_linear_data(skb, self->tx_buff.head, skb->len);
1220
1221         self->tx_buff.len = skb->len;
1222         self->tx_buff.data = self->tx_buff.head;
1223
1224         mtt = irda_get_mtt(skb);
1225         if (mtt) {
1226                 int bofs;
1227
1228                 /*
1229                  * Compute how many BOFs (STA or PA's) we need to waste the
1230                  * min turn time given the speed of the link.
1231                  */
1232                 bofs = mtt * (self->io.speed / 1000) / 8000;
1233                 if (bofs > 4095)
1234                         bofs = 4095;
1235
1236                 smsc_ircc_dma_xmit(self, bofs);
1237         } else {
1238                 /* Transmit frame */
1239                 smsc_ircc_dma_xmit(self, 0);
1240         }
1241
1242         spin_unlock_irqrestore(&self->lock, flags);
1243         dev_kfree_skb(skb);
1244
1245         return 0;
1246 }
1247
1248 /*
1249  * Function smsc_ircc_dma_xmit (self, bofs)
1250  *
1251  *    Transmit data using DMA
1252  *
1253  */
1254 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int bofs)
1255 {
1256         int iobase = self->io.fir_base;
1257         u8 ctrl;
1258
1259         IRDA_DEBUG(3, "%s\n", __func__);
1260 #if 1
1261         /* Disable Rx */
1262         register_bank(iobase, 0);
1263         outb(0x00, iobase + IRCC_LCR_B);
1264 #endif
1265         register_bank(iobase, 1);
1266         outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1267              iobase + IRCC_SCE_CFGB);
1268
1269         self->io.direction = IO_XMIT;
1270
1271         /* Set BOF additional count for generating the min turn time */
1272         register_bank(iobase, 4);
1273         outb(bofs & 0xff, iobase + IRCC_BOF_COUNT_LO);
1274         ctrl = inb(iobase + IRCC_CONTROL) & 0xf0;
1275         outb(ctrl | ((bofs >> 8) & 0x0f), iobase + IRCC_BOF_COUNT_HI);
1276
1277         /* Set max Tx frame size */
1278         outb(self->tx_buff.len >> 8, iobase + IRCC_TX_SIZE_HI);
1279         outb(self->tx_buff.len & 0xff, iobase + IRCC_TX_SIZE_LO);
1280
1281         /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1282
1283         /* Enable burst mode chip Tx DMA */
1284         register_bank(iobase, 1);
1285         outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1286              IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1287
1288         /* Setup DMA controller (must be done after enabling chip DMA) */
1289         irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
1290                        DMA_TX_MODE);
1291
1292         /* Enable interrupt */
1293
1294         register_bank(iobase, 0);
1295         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1296         outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1297
1298         /* Enable transmit */
1299         outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase + IRCC_LCR_B);
1300 }
1301
1302 /*
1303  * Function smsc_ircc_dma_xmit_complete (self)
1304  *
1305  *    The transfer of a frame in finished. This function will only be called
1306  *    by the interrupt handler
1307  *
1308  */
1309 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self)
1310 {
1311         int iobase = self->io.fir_base;
1312
1313         IRDA_DEBUG(3, "%s\n", __func__);
1314 #if 0
1315         /* Disable Tx */
1316         register_bank(iobase, 0);
1317         outb(0x00, iobase + IRCC_LCR_B);
1318 #endif
1319         register_bank(iobase, 1);
1320         outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1321              iobase + IRCC_SCE_CFGB);
1322
1323         /* Check for underrun! */
1324         register_bank(iobase, 0);
1325         if (inb(iobase + IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1326                 self->netdev->stats.tx_errors++;
1327                 self->netdev->stats.tx_fifo_errors++;
1328
1329                 /* Reset error condition */
1330                 register_bank(iobase, 0);
1331                 outb(IRCC_MASTER_ERROR_RESET, iobase + IRCC_MASTER);
1332                 outb(0x00, iobase + IRCC_MASTER);
1333         } else {
1334                 self->netdev->stats.tx_packets++;
1335                 self->netdev->stats.tx_bytes += self->tx_buff.len;
1336         }
1337
1338         /* Check if it's time to change the speed */
1339         if (self->new_speed) {
1340                 smsc_ircc_change_speed(self, self->new_speed);
1341                 self->new_speed = 0;
1342         }
1343
1344         netif_wake_queue(self->netdev);
1345 }
1346
1347 /*
1348  * Function smsc_ircc_dma_receive(self)
1349  *
1350  *    Get ready for receiving a frame. The device will initiate a DMA
1351  *    if it starts to receive a frame.
1352  *
1353  */
1354 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self)
1355 {
1356         int iobase = self->io.fir_base;
1357 #if 0
1358         /* Turn off chip DMA */
1359         register_bank(iobase, 1);
1360         outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1361              iobase + IRCC_SCE_CFGB);
1362 #endif
1363
1364         /* Disable Tx */
1365         register_bank(iobase, 0);
1366         outb(0x00, iobase + IRCC_LCR_B);
1367
1368         /* Turn off chip DMA */
1369         register_bank(iobase, 1);
1370         outb(inb(iobase + IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1371              iobase + IRCC_SCE_CFGB);
1372
1373         self->io.direction = IO_RECV;
1374         self->rx_buff.data = self->rx_buff.head;
1375
1376         /* Set max Rx frame size */
1377         register_bank(iobase, 4);
1378         outb((2050 >> 8) & 0x0f, iobase + IRCC_RX_SIZE_HI);
1379         outb(2050 & 0xff, iobase + IRCC_RX_SIZE_LO);
1380
1381         /* Setup DMA controller */
1382         irda_setup_dma(self->io.dma, self->rx_buff_dma, self->rx_buff.truesize,
1383                        DMA_RX_MODE);
1384
1385         /* Enable burst mode chip Rx DMA */
1386         register_bank(iobase, 1);
1387         outb(inb(iobase + IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1388              IRCC_CFGB_DMA_BURST, iobase + IRCC_SCE_CFGB);
1389
1390         /* Enable interrupt */
1391         register_bank(iobase, 0);
1392         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1393         outb(IRCC_MASTER_INT_EN, iobase + IRCC_MASTER);
1394
1395         /* Enable receiver */
1396         register_bank(iobase, 0);
1397         outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1398              iobase + IRCC_LCR_B);
1399
1400         return 0;
1401 }
1402
1403 /*
1404  * Function smsc_ircc_dma_receive_complete(self)
1405  *
1406  *    Finished with receiving frames
1407  *
1408  */
1409 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self)
1410 {
1411         struct sk_buff *skb;
1412         int len, msgcnt, lsr;
1413         int iobase = self->io.fir_base;
1414
1415         register_bank(iobase, 0);
1416
1417         IRDA_DEBUG(3, "%s\n", __func__);
1418 #if 0
1419         /* Disable Rx */
1420         register_bank(iobase, 0);
1421         outb(0x00, iobase + IRCC_LCR_B);
1422 #endif
1423         register_bank(iobase, 0);
1424         outb(inb(iobase + IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase + IRCC_LSAR);
1425         lsr= inb(iobase + IRCC_LSR);
1426         msgcnt = inb(iobase + IRCC_LCR_B) & 0x08;
1427
1428         IRDA_DEBUG(2, "%s: dma count = %d\n", __func__,
1429                    get_dma_residue(self->io.dma));
1430
1431         len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1432
1433         /* Look for errors */
1434         if (lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1435                 self->netdev->stats.rx_errors++;
1436                 if (lsr & IRCC_LSR_FRAME_ERROR)
1437                         self->netdev->stats.rx_frame_errors++;
1438                 if (lsr & IRCC_LSR_CRC_ERROR)
1439                         self->netdev->stats.rx_crc_errors++;
1440                 if (lsr & IRCC_LSR_SIZE_ERROR)
1441                         self->netdev->stats.rx_length_errors++;
1442                 if (lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN))
1443                         self->netdev->stats.rx_length_errors++;
1444                 return;
1445         }
1446
1447         /* Remove CRC */
1448         len -= self->io.speed < 4000000 ? 2 : 4;
1449
1450         if (len < 2 || len > 2050) {
1451                 IRDA_WARNING("%s(), bogus len=%d\n", __func__, len);
1452                 return;
1453         }
1454         IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __func__, msgcnt, len);
1455
1456         skb = dev_alloc_skb(len + 1);
1457         if (!skb) {
1458                 IRDA_WARNING("%s(), memory squeeze, dropping frame.\n",
1459                              __func__);
1460                 return;
1461         }
1462         /* Make sure IP header gets aligned */
1463         skb_reserve(skb, 1);
1464
1465         memcpy(skb_put(skb, len), self->rx_buff.data, len);
1466         self->netdev->stats.rx_packets++;
1467         self->netdev->stats.rx_bytes += len;
1468
1469         skb->dev = self->netdev;
1470         skb_reset_mac_header(skb);
1471         skb->protocol = htons(ETH_P_IRDA);
1472         netif_rx(skb);
1473 }
1474
1475 /*
1476  * Function smsc_ircc_sir_receive (self)
1477  *
1478  *    Receive one frame from the infrared port
1479  *
1480  */
1481 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1482 {
1483         int boguscount = 0;
1484         int iobase;
1485
1486         IRDA_ASSERT(self != NULL, return;);
1487
1488         iobase = self->io.sir_base;
1489
1490         /*
1491          * Receive all characters in Rx FIFO, unwrap and unstuff them.
1492          * async_unwrap_char will deliver all found frames
1493          */
1494         do {
1495                 async_unwrap_char(self->netdev, &self->netdev->stats, &self->rx_buff,
1496                                   inb(iobase + UART_RX));
1497
1498                 /* Make sure we don't stay here to long */
1499                 if (boguscount++ > 32) {
1500                         IRDA_DEBUG(2, "%s(), breaking!\n", __func__);
1501                         break;
1502                 }
1503         } while (inb(iobase + UART_LSR) & UART_LSR_DR);
1504 }
1505
1506
1507 /*
1508  * Function smsc_ircc_interrupt (irq, dev_id, regs)
1509  *
1510  *    An interrupt from the chip has arrived. Time to do some work
1511  *
1512  */
1513 static irqreturn_t smsc_ircc_interrupt(int dummy, void *dev_id)
1514 {
1515         struct net_device *dev = dev_id;
1516         struct smsc_ircc_cb *self = netdev_priv(dev);
1517         int iobase, iir, lcra, lsr;
1518         irqreturn_t ret = IRQ_NONE;
1519
1520         /* Serialise the interrupt handler in various CPUs, stop Tx path */
1521         spin_lock(&self->lock);
1522
1523         /* Check if we should use the SIR interrupt handler */
1524         if (self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
1525                 ret = smsc_ircc_interrupt_sir(dev);
1526                 goto irq_ret_unlock;
1527         }
1528
1529         iobase = self->io.fir_base;
1530
1531         register_bank(iobase, 0);
1532         iir = inb(iobase + IRCC_IIR);
1533         if (iir == 0)
1534                 goto irq_ret_unlock;
1535         ret = IRQ_HANDLED;
1536
1537         /* Disable interrupts */
1538         outb(0, iobase + IRCC_IER);
1539         lcra = inb(iobase + IRCC_LCR_A);
1540         lsr = inb(iobase + IRCC_LSR);
1541
1542         IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __func__, iir);
1543
1544         if (iir & IRCC_IIR_EOM) {
1545                 if (self->io.direction == IO_RECV)
1546                         smsc_ircc_dma_receive_complete(self);
1547                 else
1548                         smsc_ircc_dma_xmit_complete(self);
1549
1550                 smsc_ircc_dma_receive(self);
1551         }
1552
1553         if (iir & IRCC_IIR_ACTIVE_FRAME) {
1554                 /*printk(KERN_WARNING "%s(): Active Frame\n", __func__);*/
1555         }
1556
1557         /* Enable interrupts again */
1558
1559         register_bank(iobase, 0);
1560         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase + IRCC_IER);
1561
1562  irq_ret_unlock:
1563         spin_unlock(&self->lock);
1564
1565         return ret;
1566 }
1567
1568 /*
1569  * Function irport_interrupt_sir (irq, dev_id)
1570  *
1571  *    Interrupt handler for SIR modes
1572  */
1573 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1574 {
1575         struct smsc_ircc_cb *self = netdev_priv(dev);
1576         int boguscount = 0;
1577         int iobase;
1578         int iir, lsr;
1579
1580         /* Already locked comming here in smsc_ircc_interrupt() */
1581         /*spin_lock(&self->lock);*/
1582
1583         iobase = self->io.sir_base;
1584
1585         iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1586         if (iir == 0)
1587                 return IRQ_NONE;
1588         while (iir) {
1589                 /* Clear interrupt */
1590                 lsr = inb(iobase + UART_LSR);
1591
1592                 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1593                             __func__, iir, lsr, iobase);
1594
1595                 switch (iir) {
1596                 case UART_IIR_RLSI:
1597                         IRDA_DEBUG(2, "%s(), RLSI\n", __func__);
1598                         break;
1599                 case UART_IIR_RDI:
1600                         /* Receive interrupt */
1601                         smsc_ircc_sir_receive(self);
1602                         break;
1603                 case UART_IIR_THRI:
1604                         if (lsr & UART_LSR_THRE)
1605                                 /* Transmitter ready for data */
1606                                 smsc_ircc_sir_write_wakeup(self);
1607                         break;
1608                 default:
1609                         IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1610                                    __func__, iir);
1611                         break;
1612                 }
1613
1614                 /* Make sure we don't stay here to long */
1615                 if (boguscount++ > 100)
1616                         break;
1617
1618                 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1619         }
1620         /*spin_unlock(&self->lock);*/
1621         return IRQ_HANDLED;
1622 }
1623
1624
1625 #if 0 /* unused */
1626 /*
1627  * Function ircc_is_receiving (self)
1628  *
1629  *    Return TRUE is we are currently receiving a frame
1630  *
1631  */
1632 static int ircc_is_receiving(struct smsc_ircc_cb *self)
1633 {
1634         int status = FALSE;
1635         /* int iobase; */
1636
1637         IRDA_DEBUG(1, "%s\n", __func__);
1638
1639         IRDA_ASSERT(self != NULL, return FALSE;);
1640
1641         IRDA_DEBUG(0, "%s: dma count = %d\n", __func__,
1642                    get_dma_residue(self->io.dma));
1643
1644         status = (self->rx_buff.state != OUTSIDE_FRAME);
1645
1646         return status;
1647 }
1648 #endif /* unused */
1649
1650 static int smsc_ircc_request_irq(struct smsc_ircc_cb *self)
1651 {
1652         int error;
1653
1654         error = request_irq(self->io.irq, smsc_ircc_interrupt, 0,
1655                             self->netdev->name, self->netdev);
1656         if (error)
1657                 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d, err=%d\n",
1658                            __func__, self->io.irq, error);
1659
1660         return error;
1661 }
1662
1663 static void smsc_ircc_start_interrupts(struct smsc_ircc_cb *self)
1664 {
1665         unsigned long flags;
1666
1667         spin_lock_irqsave(&self->lock, flags);
1668
1669         self->io.speed = 0;
1670         smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1671
1672         spin_unlock_irqrestore(&self->lock, flags);
1673 }
1674
1675 static void smsc_ircc_stop_interrupts(struct smsc_ircc_cb *self)
1676 {
1677         int iobase = self->io.fir_base;
1678         unsigned long flags;
1679
1680         spin_lock_irqsave(&self->lock, flags);
1681
1682         register_bank(iobase, 0);
1683         outb(0, iobase + IRCC_IER);
1684         outb(IRCC_MASTER_RESET, iobase + IRCC_MASTER);
1685         outb(0x00, iobase + IRCC_MASTER);
1686
1687         spin_unlock_irqrestore(&self->lock, flags);
1688 }
1689
1690
1691 /*
1692  * Function smsc_ircc_net_open (dev)
1693  *
1694  *    Start the device
1695  *
1696  */
1697 static int smsc_ircc_net_open(struct net_device *dev)
1698 {
1699         struct smsc_ircc_cb *self;
1700         char hwname[16];
1701
1702         IRDA_DEBUG(1, "%s\n", __func__);
1703
1704         IRDA_ASSERT(dev != NULL, return -1;);
1705         self = netdev_priv(dev);
1706         IRDA_ASSERT(self != NULL, return 0;);
1707
1708         if (self->io.suspended) {
1709                 IRDA_DEBUG(0, "%s(), device is suspended\n", __func__);
1710                 return -EAGAIN;
1711         }
1712
1713         if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1714                         (void *) dev)) {
1715                 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1716                            __func__, self->io.irq);
1717                 return -EAGAIN;
1718         }
1719
1720         smsc_ircc_start_interrupts(self);
1721
1722         /* Give self a hardware name */
1723         /* It would be cool to offer the chip revision here - Jean II */
1724         sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1725
1726         /*
1727          * Open new IrLAP layer instance, now that everything should be
1728          * initialized properly
1729          */
1730         self->irlap = irlap_open(dev, &self->qos, hwname);
1731
1732         /*
1733          * Always allocate the DMA channel after the IRQ,
1734          * and clean up on failure.
1735          */
1736         if (request_dma(self->io.dma, dev->name)) {
1737                 smsc_ircc_net_close(dev);
1738
1739                 IRDA_WARNING("%s(), unable to allocate DMA=%d\n",
1740                              __func__, self->io.dma);
1741                 return -EAGAIN;
1742         }
1743
1744         netif_start_queue(dev);
1745
1746         return 0;
1747 }
1748
1749 /*
1750  * Function smsc_ircc_net_close (dev)
1751  *
1752  *    Stop the device
1753  *
1754  */
1755 static int smsc_ircc_net_close(struct net_device *dev)
1756 {
1757         struct smsc_ircc_cb *self;
1758
1759         IRDA_DEBUG(1, "%s\n", __func__);
1760
1761         IRDA_ASSERT(dev != NULL, return -1;);
1762         self = netdev_priv(dev);
1763         IRDA_ASSERT(self != NULL, return 0;);
1764
1765         /* Stop device */
1766         netif_stop_queue(dev);
1767
1768         /* Stop and remove instance of IrLAP */
1769         if (self->irlap)
1770                 irlap_close(self->irlap);
1771         self->irlap = NULL;
1772
1773         smsc_ircc_stop_interrupts(self);
1774
1775         /* if we are called from smsc_ircc_resume we don't have IRQ reserved */
1776         if (!self->io.suspended)
1777                 free_irq(self->io.irq, dev);
1778
1779         disable_dma(self->io.dma);
1780         free_dma(self->io.dma);
1781
1782         return 0;
1783 }
1784
1785 static int smsc_ircc_suspend(struct platform_device *dev, pm_message_t state)
1786 {
1787         struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1788
1789         if (!self->io.suspended) {
1790                 IRDA_DEBUG(1, "%s, Suspending\n", driver_name);
1791
1792                 rtnl_lock();
1793                 if (netif_running(self->netdev)) {
1794                         netif_device_detach(self->netdev);
1795                         smsc_ircc_stop_interrupts(self);
1796                         free_irq(self->io.irq, self->netdev);
1797                         disable_dma(self->io.dma);
1798                 }
1799                 self->io.suspended = 1;
1800                 rtnl_unlock();
1801         }
1802
1803         return 0;
1804 }
1805
1806 static int smsc_ircc_resume(struct platform_device *dev)
1807 {
1808         struct smsc_ircc_cb *self = platform_get_drvdata(dev);
1809
1810         if (self->io.suspended) {
1811                 IRDA_DEBUG(1, "%s, Waking up\n", driver_name);
1812
1813                 rtnl_lock();
1814                 smsc_ircc_init_chip(self);
1815                 if (netif_running(self->netdev)) {
1816                         if (smsc_ircc_request_irq(self)) {
1817                                 /*
1818                                  * Don't fail resume process, just kill this
1819                                  * network interface
1820                                  */
1821                                 unregister_netdevice(self->netdev);
1822                         } else {
1823                                 enable_dma(self->io.dma);
1824                                 smsc_ircc_start_interrupts(self);
1825                                 netif_device_attach(self->netdev);
1826                         }
1827                 }
1828                 self->io.suspended = 0;
1829                 rtnl_unlock();
1830         }
1831         return 0;
1832 }
1833
1834 /*
1835  * Function smsc_ircc_close (self)
1836  *
1837  *    Close driver instance
1838  *
1839  */
1840 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1841 {
1842         IRDA_DEBUG(1, "%s\n", __func__);
1843
1844         IRDA_ASSERT(self != NULL, return -1;);
1845
1846         platform_device_unregister(self->pldev);
1847
1848         /* Remove netdevice */
1849         unregister_netdev(self->netdev);
1850
1851         smsc_ircc_stop_interrupts(self);
1852
1853         /* Release the PORTS that this driver is using */
1854         IRDA_DEBUG(0, "%s(), releasing 0x%03x\n",  __func__,
1855                    self->io.fir_base);
1856
1857         release_region(self->io.fir_base, self->io.fir_ext);
1858
1859         IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __func__,
1860                    self->io.sir_base);
1861
1862         release_region(self->io.sir_base, self->io.sir_ext);
1863
1864         if (self->tx_buff.head)
1865                 dma_free_coherent(NULL, self->tx_buff.truesize,
1866                                   self->tx_buff.head, self->tx_buff_dma);
1867
1868         if (self->rx_buff.head)
1869                 dma_free_coherent(NULL, self->rx_buff.truesize,
1870                                   self->rx_buff.head, self->rx_buff_dma);
1871
1872         free_netdev(self->netdev);
1873
1874         return 0;
1875 }
1876
1877 static void __exit smsc_ircc_cleanup(void)
1878 {
1879         int i;
1880
1881         IRDA_DEBUG(1, "%s\n", __func__);
1882
1883         for (i = 0; i < 2; i++) {
1884                 if (dev_self[i])
1885                         smsc_ircc_close(dev_self[i]);
1886         }
1887
1888         if (pnp_driver_registered)
1889                 pnp_unregister_driver(&smsc_ircc_pnp_driver);
1890
1891         platform_driver_unregister(&smsc_ircc_driver);
1892 }
1893
1894 /*
1895  *      Start SIR operations
1896  *
1897  * This function *must* be called with spinlock held, because it may
1898  * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1899  */
1900 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1901 {
1902         struct net_device *dev;
1903         int fir_base, sir_base;
1904
1905         IRDA_DEBUG(3, "%s\n", __func__);
1906
1907         IRDA_ASSERT(self != NULL, return;);
1908         dev = self->netdev;
1909         IRDA_ASSERT(dev != NULL, return;);
1910
1911         fir_base = self->io.fir_base;
1912         sir_base = self->io.sir_base;
1913
1914         /* Reset everything */
1915         outb(IRCC_MASTER_RESET, fir_base + IRCC_MASTER);
1916
1917         #if SMSC_IRCC2_C_SIR_STOP
1918         /*smsc_ircc_sir_stop(self);*/
1919         #endif
1920
1921         register_bank(fir_base, 1);
1922         outb(((inb(fir_base + IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base + IRCC_SCE_CFGA);
1923
1924         /* Initialize UART */
1925         outb(UART_LCR_WLEN8, sir_base + UART_LCR);  /* Reset DLAB */
1926         outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base + UART_MCR);
1927
1928         /* Turn on interrups */
1929         outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base + UART_IER);
1930
1931         IRDA_DEBUG(3, "%s() - exit\n", __func__);
1932
1933         outb(0x00, fir_base + IRCC_MASTER);
1934 }
1935
1936 #if SMSC_IRCC2_C_SIR_STOP
1937 void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1938 {
1939         int iobase;
1940
1941         IRDA_DEBUG(3, "%s\n", __func__);
1942         iobase = self->io.sir_base;
1943
1944         /* Reset UART */
1945         outb(0, iobase + UART_MCR);
1946
1947         /* Turn off interrupts */
1948         outb(0, iobase + UART_IER);
1949 }
1950 #endif
1951
1952 /*
1953  * Function smsc_sir_write_wakeup (self)
1954  *
1955  *    Called by the SIR interrupt handler when there's room for more data.
1956  *    If we have more packets to send, we send them here.
1957  *
1958  */
1959 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1960 {
1961         int actual = 0;
1962         int iobase;
1963         int fcr;
1964
1965         IRDA_ASSERT(self != NULL, return;);
1966
1967         IRDA_DEBUG(4, "%s\n", __func__);
1968
1969         iobase = self->io.sir_base;
1970
1971         /* Finished with frame?  */
1972         if (self->tx_buff.len > 0)  {
1973                 /* Write data left in transmit buffer */
1974                 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1975                                       self->tx_buff.data, self->tx_buff.len);
1976                 self->tx_buff.data += actual;
1977                 self->tx_buff.len  -= actual;
1978         } else {
1979
1980         /*if (self->tx_buff.len ==0)  {*/
1981
1982                 /*
1983                  *  Now serial buffer is almost free & we can start
1984                  *  transmission of another packet. But first we must check
1985                  *  if we need to change the speed of the hardware
1986                  */
1987                 if (self->new_speed) {
1988                         IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1989                                    __func__, self->new_speed);
1990                         smsc_ircc_sir_wait_hw_transmitter_finish(self);
1991                         smsc_ircc_change_speed(self, self->new_speed);
1992                         self->new_speed = 0;
1993                 } else {
1994                         /* Tell network layer that we want more frames */
1995                         netif_wake_queue(self->netdev);
1996                 }
1997                 self->netdev->stats.tx_packets++;
1998
1999                 if (self->io.speed <= 115200) {
2000                         /*
2001                          * Reset Rx FIFO to make sure that all reflected transmit data
2002                          * is discarded. This is needed for half duplex operation
2003                          */
2004                         fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
2005                         fcr |= self->io.speed < 38400 ?
2006                                         UART_FCR_TRIGGER_1 : UART_FCR_TRIGGER_14;
2007
2008                         outb(fcr, iobase + UART_FCR);
2009
2010                         /* Turn on receive interrupts */
2011                         outb(UART_IER_RDI, iobase + UART_IER);
2012                 }
2013         }
2014 }
2015
2016 /*
2017  * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
2018  *
2019  *    Fill Tx FIFO with transmit data
2020  *
2021  */
2022 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
2023 {
2024         int actual = 0;
2025
2026         /* Tx FIFO should be empty! */
2027         if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) {
2028                 IRDA_WARNING("%s(), failed, fifo not empty!\n", __func__);
2029                 return 0;
2030         }
2031
2032         /* Fill FIFO with current frame */
2033         while (fifo_size-- > 0 && actual < len) {
2034                 /* Transmit next byte */
2035                 outb(buf[actual], iobase + UART_TX);
2036                 actual++;
2037         }
2038         return actual;
2039 }
2040
2041 /*
2042  * Function smsc_ircc_is_receiving (self)
2043  *
2044  *    Returns true is we are currently receiving data
2045  *
2046  */
2047 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
2048 {
2049         return (self->rx_buff.state != OUTSIDE_FRAME);
2050 }
2051
2052
2053 /*
2054  * Function smsc_ircc_probe_transceiver(self)
2055  *
2056  *    Tries to find the used Transceiver
2057  *
2058  */
2059 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
2060 {
2061         unsigned int    i;
2062
2063         IRDA_ASSERT(self != NULL, return;);
2064
2065         for (i = 0; smsc_transceivers[i].name != NULL; i++)
2066                 if (smsc_transceivers[i].probe(self->io.fir_base)) {
2067                         IRDA_MESSAGE(" %s transceiver found\n",
2068                                      smsc_transceivers[i].name);
2069                         self->transceiver= i + 1;
2070                         return;
2071                 }
2072
2073         IRDA_MESSAGE("No transceiver found. Defaulting to %s\n",
2074                      smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
2075
2076         self->transceiver = SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
2077 }
2078
2079
2080 /*
2081  * Function smsc_ircc_set_transceiver_for_speed(self, speed)
2082  *
2083  *    Set the transceiver according to the speed
2084  *
2085  */
2086 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
2087 {
2088         unsigned int trx;
2089
2090         trx = self->transceiver;
2091         if (trx > 0)
2092                 smsc_transceivers[trx - 1].set_for_speed(self->io.fir_base, speed);
2093 }
2094
2095 /*
2096  * Function smsc_ircc_wait_hw_transmitter_finish ()
2097  *
2098  *    Wait for the real end of HW transmission
2099  *
2100  * The UART is a strict FIFO, and we get called only when we have finished
2101  * pushing data to the FIFO, so the maximum amount of time we must wait
2102  * is only for the FIFO to drain out.
2103  *
2104  * We use a simple calibrated loop. We may need to adjust the loop
2105  * delay (udelay) to balance I/O traffic and latency. And we also need to
2106  * adjust the maximum timeout.
2107  * It would probably be better to wait for the proper interrupt,
2108  * but it doesn't seem to be available.
2109  *
2110  * We can't use jiffies or kernel timers because :
2111  * 1) We are called from the interrupt handler, which disable softirqs,
2112  * so jiffies won't be increased
2113  * 2) Jiffies granularity is usually very coarse (10ms), and we don't
2114  * want to wait that long to detect stuck hardware.
2115  * Jean II
2116  */
2117
2118 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
2119 {
2120         int iobase = self->io.sir_base;
2121         int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
2122
2123         /* Calibrated busy loop */
2124         while (count-- > 0 && !(inb(iobase + UART_LSR) & UART_LSR_TEMT))
2125                 udelay(1);
2126
2127         if (count == 0)
2128                 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __func__);
2129 }
2130
2131
2132 /* PROBING
2133  *
2134  * REVISIT we can be told about the device by PNP, and should use that info
2135  * instead of probing hardware and creating a platform_device ...
2136  */
2137
2138 static int __init smsc_ircc_look_for_chips(void)
2139 {
2140         struct smsc_chip_address *address;
2141         char *type;
2142         unsigned int cfg_base, found;
2143
2144         found = 0;
2145         address = possible_addresses;
2146
2147         while (address->cfg_base) {
2148                 cfg_base = address->cfg_base;
2149
2150                 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __func__, cfg_base, address->type);*/
2151
2152                 if (address->type & SMSCSIO_TYPE_FDC) {
2153                         type = "FDC";
2154                         if (address->type & SMSCSIO_TYPE_FLAT)
2155                                 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, type))
2156                                         found++;
2157
2158                         if (address->type & SMSCSIO_TYPE_PAGED)
2159                                 if (!smsc_superio_paged(fdc_chips_paged, cfg_base, type))
2160                                         found++;
2161                 }
2162                 if (address->type & SMSCSIO_TYPE_LPC) {
2163                         type = "LPC";
2164                         if (address->type & SMSCSIO_TYPE_FLAT)
2165                                 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, type))
2166                                         found++;
2167
2168                         if (address->type & SMSCSIO_TYPE_PAGED)
2169                                 if (!smsc_superio_paged(lpc_chips_paged, cfg_base, type))
2170                                         found++;
2171                 }
2172                 address++;
2173         }
2174         return found;
2175 }
2176
2177 /*
2178  * Function smsc_superio_flat (chip, base, type)
2179  *
2180  *    Try to get configuration of a smc SuperIO chip with flat register model
2181  *
2182  */
2183 static int __init smsc_superio_flat(const struct smsc_chip *chips, unsigned short cfgbase, char *type)
2184 {
2185         unsigned short firbase, sirbase;
2186         u8 mode, dma, irq;
2187         int ret = -ENODEV;
2188
2189         IRDA_DEBUG(1, "%s\n", __func__);
2190
2191         if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type) == NULL)
2192                 return ret;
2193
2194         outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2195         mode = inb(cfgbase + 1);
2196
2197         /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __func__, mode);*/
2198
2199         if (!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2200                 IRDA_WARNING("%s(): IrDA not enabled\n", __func__);
2201
2202         outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2203         sirbase = inb(cfgbase + 1) << 2;
2204
2205         /* FIR iobase */
2206         outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2207         firbase = inb(cfgbase + 1) << 3;
2208
2209         /* DMA */
2210         outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2211         dma = inb(cfgbase + 1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2212
2213         /* IRQ */
2214         outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2215         irq = inb(cfgbase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2216
2217         IRDA_MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __func__, firbase, sirbase, dma, irq, mode);
2218
2219         if (firbase && smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2220                 ret = 0;
2221
2222         /* Exit configuration */
2223         outb(SMSCSIO_CFGEXITKEY, cfgbase);
2224
2225         return ret;
2226 }
2227
2228 /*
2229  * Function smsc_superio_paged (chip, base, type)
2230  *
2231  *    Try  to get configuration of a smc SuperIO chip with paged register model
2232  *
2233  */
2234 static int __init smsc_superio_paged(const struct smsc_chip *chips, unsigned short cfg_base, char *type)
2235 {
2236         unsigned short fir_io, sir_io;
2237         int ret = -ENODEV;
2238
2239         IRDA_DEBUG(1, "%s\n", __func__);
2240
2241         if (smsc_ircc_probe(cfg_base, 0x20, chips, type) == NULL)
2242                 return ret;
2243
2244         /* Select logical device (UART2) */
2245         outb(0x07, cfg_base);
2246         outb(0x05, cfg_base + 1);
2247
2248         /* SIR iobase */
2249         outb(0x60, cfg_base);
2250         sir_io = inb(cfg_base + 1) << 8;
2251         outb(0x61, cfg_base);
2252         sir_io |= inb(cfg_base + 1);
2253
2254         /* Read FIR base */
2255         outb(0x62, cfg_base);
2256         fir_io = inb(cfg_base + 1) << 8;
2257         outb(0x63, cfg_base);
2258         fir_io |= inb(cfg_base + 1);
2259         outb(0x2b, cfg_base); /* ??? */
2260
2261         if (fir_io && smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2262                 ret = 0;
2263
2264         /* Exit configuration */
2265         outb(SMSCSIO_CFGEXITKEY, cfg_base);
2266
2267         return ret;
2268 }
2269
2270
2271 static int __init smsc_access(unsigned short cfg_base, unsigned char reg)
2272 {
2273         IRDA_DEBUG(1, "%s\n", __func__);
2274
2275         outb(reg, cfg_base);
2276         return inb(cfg_base) != reg ? -1 : 0;
2277 }
2278
2279 static const struct smsc_chip * __init smsc_ircc_probe(unsigned short cfg_base, u8 reg, const struct smsc_chip *chip, char *type)
2280 {
2281         u8 devid, xdevid, rev;
2282
2283         IRDA_DEBUG(1, "%s\n", __func__);
2284
2285         /* Leave configuration */
2286
2287         outb(SMSCSIO_CFGEXITKEY, cfg_base);
2288
2289         if (inb(cfg_base) == SMSCSIO_CFGEXITKEY)        /* not a smc superio chip */
2290                 return NULL;
2291
2292         outb(reg, cfg_base);
2293
2294         xdevid = inb(cfg_base + 1);
2295
2296         /* Enter configuration */
2297
2298         outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2299
2300         #if 0
2301         if (smsc_access(cfg_base,0x55)) /* send second key and check */
2302                 return NULL;
2303         #endif
2304
2305         /* probe device ID */
2306
2307         if (smsc_access(cfg_base, reg))
2308                 return NULL;
2309
2310         devid = inb(cfg_base + 1);
2311
2312         if (devid == 0 || devid == 0xff)        /* typical values for unused port */
2313                 return NULL;
2314
2315         /* probe revision ID */
2316
2317         if (smsc_access(cfg_base, reg + 1))
2318                 return NULL;
2319
2320         rev = inb(cfg_base + 1);
2321
2322         if (rev >= 128)                 /* i think this will make no sense */
2323                 return NULL;
2324
2325         if (devid == xdevid)            /* protection against false positives */
2326                 return NULL;
2327
2328         /* Check for expected device ID; are there others? */
2329
2330         while (chip->devid != devid) {
2331
2332                 chip++;
2333
2334                 if (chip->name == NULL)
2335                         return NULL;
2336         }
2337
2338         IRDA_MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",
2339                      devid, rev, cfg_base, type, chip->name);
2340
2341         if (chip->rev > rev) {
2342                 IRDA_MESSAGE("Revision higher than expected\n");
2343                 return NULL;
2344         }
2345
2346         if (chip->flags & NoIRDA)
2347                 IRDA_MESSAGE("chipset does not support IRDA\n");
2348
2349         return chip;
2350 }
2351
2352 static int __init smsc_superio_fdc(unsigned short cfg_base)
2353 {
2354         int ret = -1;
2355
2356         if (!request_region(cfg_base, 2, driver_name)) {
2357                 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2358                              __func__, cfg_base);
2359         } else {
2360                 if (!smsc_superio_flat(fdc_chips_flat, cfg_base, "FDC") ||
2361                     !smsc_superio_paged(fdc_chips_paged, cfg_base, "FDC"))
2362                         ret =  0;
2363
2364                 release_region(cfg_base, 2);
2365         }
2366
2367         return ret;
2368 }
2369
2370 static int __init smsc_superio_lpc(unsigned short cfg_base)
2371 {
2372         int ret = -1;
2373
2374         if (!request_region(cfg_base, 2, driver_name)) {
2375                 IRDA_WARNING("%s: can't get cfg_base of 0x%03x\n",
2376                              __func__, cfg_base);
2377         } else {
2378                 if (!smsc_superio_flat(lpc_chips_flat, cfg_base, "LPC") ||
2379                     !smsc_superio_paged(lpc_chips_paged, cfg_base, "LPC"))
2380                         ret = 0;
2381
2382                 release_region(cfg_base, 2);
2383         }
2384         return ret;
2385 }
2386
2387 /*
2388  * Look for some specific subsystem setups that need
2389  * pre-configuration not properly done by the BIOS (especially laptops)
2390  * This code is based in part on smcinit.c, tosh1800-smcinit.c
2391  * and tosh2450-smcinit.c. The table lists the device entries
2392  * for ISA bridges with an LPC (Low Pin Count) controller which
2393  * handles the communication with the SMSC device. After the LPC
2394  * controller is initialized through PCI, the SMSC device is initialized
2395  * through a dedicated port in the ISA port-mapped I/O area, this latter
2396  * area is used to configure the SMSC device with default
2397  * SIR and FIR I/O ports, DMA and IRQ. Different vendors have
2398  * used different sets of parameters and different control port
2399  * addresses making a subsystem device table necessary.
2400  */
2401 #ifdef CONFIG_PCI
2402 #define PCIID_VENDOR_INTEL 0x8086
2403 #define PCIID_VENDOR_ALI 0x10b9
2404 static struct smsc_ircc_subsystem_configuration subsystem_configurations[] __initdata = {
2405         /*
2406          * Subsystems needing entries:
2407          * 0x10b9:0x1533 0x103c:0x0850 HP nx9010 family
2408          * 0x10b9:0x1533 0x0e11:0x005a Compaq nc4000 family
2409          * 0x8086:0x24cc 0x0e11:0x002a HP nx9000 family
2410          */
2411         {
2412                 /* Guessed entry */
2413                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2414                 .device = 0x24cc,
2415                 .subvendor = 0x103c,
2416                 .subdevice = 0x08bc,
2417                 .sir_io = 0x02f8,
2418                 .fir_io = 0x0130,
2419                 .fir_irq = 0x05,
2420                 .fir_dma = 0x03,
2421                 .cfg_base = 0x004e,
2422                 .preconfigure = preconfigure_through_82801,
2423                 .name = "HP nx5000 family",
2424         },
2425         {
2426                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2427                 .device = 0x24cc,
2428                 .subvendor = 0x103c,
2429                 .subdevice = 0x088c,
2430                 /* Quite certain these are the same for nc8000 as for nc6000 */
2431                 .sir_io = 0x02f8,
2432                 .fir_io = 0x0130,
2433                 .fir_irq = 0x05,
2434                 .fir_dma = 0x03,
2435                 .cfg_base = 0x004e,
2436                 .preconfigure = preconfigure_through_82801,
2437                 .name = "HP nc8000 family",
2438         },
2439         {
2440                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2441                 .device = 0x24cc,
2442                 .subvendor = 0x103c,
2443                 .subdevice = 0x0890,
2444                 .sir_io = 0x02f8,
2445                 .fir_io = 0x0130,
2446                 .fir_irq = 0x05,
2447                 .fir_dma = 0x03,
2448                 .cfg_base = 0x004e,
2449                 .preconfigure = preconfigure_through_82801,
2450                 .name = "HP nc6000 family",
2451         },
2452         {
2453                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801DBM LPC bridge */
2454                 .device = 0x24cc,
2455                 .subvendor = 0x0e11,
2456                 .subdevice = 0x0860,
2457                 /* I assume these are the same for x1000 as for the others */
2458                 .sir_io = 0x02e8,
2459                 .fir_io = 0x02f8,
2460                 .fir_irq = 0x07,
2461                 .fir_dma = 0x03,
2462                 .cfg_base = 0x002e,
2463                 .preconfigure = preconfigure_through_82801,
2464                 .name = "Compaq x1000 family",
2465         },
2466         {
2467                 /* Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge */
2468                 .vendor = PCIID_VENDOR_INTEL,
2469                 .device = 0x24c0,
2470                 .subvendor = 0x1179,
2471                 .subdevice = 0xffff, /* 0xffff is "any" */
2472                 .sir_io = 0x03f8,
2473                 .fir_io = 0x0130,
2474                 .fir_irq = 0x07,
2475                 .fir_dma = 0x01,
2476                 .cfg_base = 0x002e,
2477                 .preconfigure = preconfigure_through_82801,
2478                 .name = "Toshiba laptop with Intel 82801DB/DBL LPC bridge",
2479         },
2480         {
2481                 .vendor = PCIID_VENDOR_INTEL, /* Intel 82801CAM ISA bridge */
2482                 .device = 0x248c,
2483                 .subvendor = 0x1179,
2484                 .subdevice = 0xffff, /* 0xffff is "any" */
2485                 .sir_io = 0x03f8,
2486                 .fir_io = 0x0130,
2487                 .fir_irq = 0x03,
2488                 .fir_dma = 0x03,
2489                 .cfg_base = 0x002e,
2490                 .preconfigure = preconfigure_through_82801,
2491                 .name = "Toshiba laptop with Intel 82801CAM ISA bridge",
2492         },
2493         {
2494                 /* 82801DBM (ICH4-M) LPC Interface Bridge */
2495                 .vendor = PCIID_VENDOR_INTEL,
2496                 .device = 0x24cc,
2497                 .subvendor = 0x1179,
2498                 .subdevice = 0xffff, /* 0xffff is "any" */
2499                 .sir_io = 0x03f8,
2500                 .fir_io = 0x0130,
2501                 .fir_irq = 0x03,
2502                 .fir_dma = 0x03,
2503                 .cfg_base = 0x002e,
2504                 .preconfigure = preconfigure_through_82801,
2505                 .name = "Toshiba laptop with Intel 8281DBM LPC bridge",
2506         },
2507         {
2508                 /* ALi M1533/M1535 PCI to ISA Bridge [Aladdin IV/V/V+] */
2509                 .vendor = PCIID_VENDOR_ALI,
2510                 .device = 0x1533,
2511                 .subvendor = 0x1179,
2512                 .subdevice = 0xffff, /* 0xffff is "any" */
2513                 .sir_io = 0x02e8,
2514                 .fir_io = 0x02f8,
2515                 .fir_irq = 0x07,
2516                 .fir_dma = 0x03,
2517                 .cfg_base = 0x002e,
2518                 .preconfigure = preconfigure_through_ali,
2519                 .name = "Toshiba laptop with ALi ISA bridge",
2520         },
2521         { } // Terminator
2522 };
2523
2524
2525 /*
2526  * This sets up the basic SMSC parameters
2527  * (FIR port, SIR port, FIR DMA, FIR IRQ)
2528  * through the chip configuration port.
2529  */
2530 static int __init preconfigure_smsc_chip(struct
2531                                          smsc_ircc_subsystem_configuration
2532                                          *conf)
2533 {
2534         unsigned short iobase = conf->cfg_base;
2535         unsigned char tmpbyte;
2536
2537         outb(LPC47N227_CFGACCESSKEY, iobase); // enter configuration state
2538         outb(SMSCSIOFLAT_DEVICEID_REG, iobase); // set for device ID
2539         tmpbyte = inb(iobase +1); // Read device ID
2540         IRDA_DEBUG(0,
2541                    "Detected Chip id: 0x%02x, setting up registers...\n",
2542                    tmpbyte);
2543
2544         /* Disable UART1 and set up SIR I/O port */
2545         outb(0x24, iobase);  // select CR24 - UART1 base addr
2546         outb(0x00, iobase + 1); // disable UART1
2547         outb(SMSCSIOFLAT_UART2BASEADDR_REG, iobase);  // select CR25 - UART2 base addr
2548         outb( (conf->sir_io >> 2), iobase + 1); // bits 2-9 of 0x3f8
2549         tmpbyte = inb(iobase + 1);
2550         if (tmpbyte != (conf->sir_io >> 2) ) {
2551                 IRDA_WARNING("ERROR: could not configure SIR ioport.\n");
2552                 IRDA_WARNING("Try to supply ircc_cfg argument.\n");
2553                 return -ENXIO;
2554         }
2555
2556         /* Set up FIR IRQ channel for UART2 */
2557         outb(SMSCSIOFLAT_UARTIRQSELECT_REG, iobase); // select CR28 - UART1,2 IRQ select
2558         tmpbyte = inb(iobase + 1);
2559         tmpbyte &= SMSCSIOFLAT_UART1IRQSELECT_MASK; // Do not touch the UART1 portion
2560         tmpbyte |= (conf->fir_irq & SMSCSIOFLAT_UART2IRQSELECT_MASK);
2561         outb(tmpbyte, iobase + 1);
2562         tmpbyte = inb(iobase + 1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2563         if (tmpbyte != conf->fir_irq) {
2564                 IRDA_WARNING("ERROR: could not configure FIR IRQ channel.\n");
2565                 return -ENXIO;
2566         }
2567
2568         /* Set up FIR I/O port */
2569         outb(SMSCSIOFLAT_FIRBASEADDR_REG, iobase);  // CR2B - SCE (FIR) base addr
2570         outb((conf->fir_io >> 3), iobase + 1);
2571         tmpbyte = inb(iobase + 1);
2572         if (tmpbyte != (conf->fir_io >> 3) ) {
2573                 IRDA_WARNING("ERROR: could not configure FIR I/O port.\n");
2574                 return -ENXIO;
2575         }
2576
2577         /* Set up FIR DMA channel */
2578         outb(SMSCSIOFLAT_FIRDMASELECT_REG, iobase);  // CR2C - SCE (FIR) DMA select
2579         outb((conf->fir_dma & LPC47N227_FIRDMASELECT_MASK), iobase + 1); // DMA
2580         tmpbyte = inb(iobase + 1) & LPC47N227_FIRDMASELECT_MASK;
2581         if (tmpbyte != (conf->fir_dma & LPC47N227_FIRDMASELECT_MASK)) {
2582                 IRDA_WARNING("ERROR: could not configure FIR DMA channel.\n");
2583                 return -ENXIO;
2584         }
2585
2586         outb(SMSCSIOFLAT_UARTMODE0C_REG, iobase);  // CR0C - UART mode
2587         tmpbyte = inb(iobase + 1);
2588         tmpbyte &= ~SMSCSIOFLAT_UART2MODE_MASK |
2589                 SMSCSIOFLAT_UART2MODE_VAL_IRDA;
2590         outb(tmpbyte, iobase + 1); // enable IrDA (HPSIR) mode, high speed
2591
2592         outb(LPC47N227_APMBOOTDRIVE_REG, iobase);  // CR07 - Auto Pwr Mgt/boot drive sel
2593         tmpbyte = inb(iobase + 1);
2594         outb(tmpbyte | LPC47N227_UART2AUTOPWRDOWN_MASK, iobase + 1); // enable UART2 autopower down
2595
2596         /* This one was not part of tosh1800 */
2597         outb(0x0a, iobase);  // CR0a - ecp fifo / ir mux
2598         tmpbyte = inb(iobase + 1);
2599         outb(tmpbyte | 0x40, iobase + 1); // send active device to ir port
2600
2601         outb(LPC47N227_UART12POWER_REG, iobase);  // CR02 - UART 1,2 power
2602         tmpbyte = inb(iobase + 1);
2603         outb(tmpbyte | LPC47N227_UART2POWERDOWN_MASK, iobase + 1); // UART2 power up mode, UART1 power down
2604
2605         outb(LPC47N227_FDCPOWERVALIDCONF_REG, iobase);  // CR00 - FDC Power/valid config cycle
2606         tmpbyte = inb(iobase + 1);
2607         outb(tmpbyte | LPC47N227_VALID_MASK, iobase + 1); // valid config cycle done
2608
2609         outb(LPC47N227_CFGEXITKEY, iobase);  // Exit configuration
2610
2611         return 0;
2612 }
2613
2614 /* 82801CAM generic registers */
2615 #define VID 0x00
2616 #define DID 0x02
2617 #define PIRQ_A_D_ROUT 0x60
2618 #define SIRQ_CNTL 0x64
2619 #define PIRQ_E_H_ROUT 0x68
2620 #define PCI_DMA_C 0x90
2621 /* LPC-specific registers */
2622 #define COM_DEC 0xe0
2623 #define GEN1_DEC 0xe4
2624 #define LPC_EN 0xe6
2625 #define GEN2_DEC 0xec
2626 /*
2627  * Sets up the I/O range using the 82801CAM ISA bridge, 82801DBM LPC bridge
2628  * or Intel 82801DB/DBL (ICH4/ICH4-L) LPC Interface Bridge.
2629  * They all work the same way!
2630  */
2631 static int __init preconfigure_through_82801(struct pci_dev *dev,
2632                                              struct
2633                                              smsc_ircc_subsystem_configuration
2634                                              *conf)
2635 {
2636         unsigned short tmpword;
2637         unsigned char tmpbyte;
2638
2639         IRDA_MESSAGE("Setting up Intel 82801 controller and SMSC device\n");
2640         /*
2641          * Select the range for the COMA COM port (SIR)
2642          * Register COM_DEC:
2643          * Bit 7: reserved
2644          * Bit 6-4, COMB decode range
2645          * Bit 3: reserved
2646          * Bit 2-0, COMA decode range
2647          *
2648          * Decode ranges:
2649          *   000 = 0x3f8-0x3ff (COM1)
2650          *   001 = 0x2f8-0x2ff (COM2)
2651          *   010 = 0x220-0x227
2652          *   011 = 0x228-0x22f
2653          *   100 = 0x238-0x23f
2654          *   101 = 0x2e8-0x2ef (COM4)
2655          *   110 = 0x338-0x33f
2656          *   111 = 0x3e8-0x3ef (COM3)
2657          */
2658         pci_read_config_byte(dev, COM_DEC, &tmpbyte);
2659         tmpbyte &= 0xf8; /* mask COMA bits */
2660         switch(conf->sir_io) {
2661         case 0x3f8:
2662                 tmpbyte |= 0x00;
2663                 break;
2664         case 0x2f8:
2665                 tmpbyte |= 0x01;
2666                 break;
2667         case 0x220:
2668                 tmpbyte |= 0x02;
2669                 break;
2670         case 0x228:
2671                 tmpbyte |= 0x03;
2672                 break;
2673         case 0x238:
2674                 tmpbyte |= 0x04;
2675                 break;
2676         case 0x2e8:
2677                 tmpbyte |= 0x05;
2678                 break;
2679         case 0x338:
2680                 tmpbyte |= 0x06;
2681                 break;
2682         case 0x3e8:
2683                 tmpbyte |= 0x07;
2684                 break;
2685         default:
2686                 tmpbyte |= 0x01; /* COM2 default */
2687         }
2688         IRDA_DEBUG(1, "COM_DEC (write): 0x%02x\n", tmpbyte);
2689         pci_write_config_byte(dev, COM_DEC, tmpbyte);
2690
2691         /* Enable Low Pin Count interface */
2692         pci_read_config_word(dev, LPC_EN, &tmpword);
2693         /* These seem to be set up at all times,
2694          * just make sure it is properly set.
2695          */
2696         switch(conf->cfg_base) {
2697         case 0x04e:
2698                 tmpword |= 0x2000;
2699                 break;
2700         case 0x02e:
2701                 tmpword |= 0x1000;
2702                 break;
2703         case 0x062:
2704                 tmpword |= 0x0800;
2705                 break;
2706         case 0x060:
2707                 tmpword |= 0x0400;
2708                 break;
2709         default:
2710                 IRDA_WARNING("Uncommon I/O base address: 0x%04x\n",
2711                              conf->cfg_base);
2712                 break;
2713         }
2714         tmpword &= 0xfffd; /* disable LPC COMB */
2715         tmpword |= 0x0001; /* set bit 0 : enable LPC COMA addr range (GEN2) */
2716         IRDA_DEBUG(1, "LPC_EN (write): 0x%04x\n", tmpword);
2717         pci_write_config_word(dev, LPC_EN, tmpword);
2718
2719         /*
2720          * Configure LPC DMA channel
2721          * PCI_DMA_C bits:
2722          * Bit 15-14: DMA channel 7 select
2723          * Bit 13-12: DMA channel 6 select
2724          * Bit 11-10: DMA channel 5 select
2725          * Bit 9-8:   Reserved
2726          * Bit 7-6:   DMA channel 3 select
2727          * Bit 5-4:   DMA channel 2 select
2728          * Bit 3-2:   DMA channel 1 select
2729          * Bit 1-0:   DMA channel 0 select
2730          *  00 = Reserved value
2731          *  01 = PC/PCI DMA
2732          *  10 = Reserved value
2733          *  11 = LPC I/F DMA
2734          */
2735         pci_read_config_word(dev, PCI_DMA_C, &tmpword);
2736         switch(conf->fir_dma) {
2737         case 0x07:
2738                 tmpword |= 0xc000;
2739                 break;
2740         case 0x06:
2741                 tmpword |= 0x3000;
2742                 break;
2743         case 0x05:
2744                 tmpword |= 0x0c00;
2745                 break;
2746         case 0x03:
2747                 tmpword |= 0x00c0;
2748                 break;
2749         case 0x02:
2750                 tmpword |= 0x0030;
2751                 break;
2752         case 0x01:
2753                 tmpword |= 0x000c;
2754                 break;
2755         case 0x00:
2756                 tmpword |= 0x0003;
2757                 break;
2758         default:
2759                 break; /* do not change settings */
2760         }
2761         IRDA_DEBUG(1, "PCI_DMA_C (write): 0x%04x\n", tmpword);
2762         pci_write_config_word(dev, PCI_DMA_C, tmpword);
2763
2764         /*
2765          * GEN2_DEC bits:
2766          * Bit 15-4: Generic I/O range
2767          * Bit 3-1: reserved (read as 0)
2768          * Bit 0: enable GEN2 range on LPC I/F
2769          */
2770         tmpword = conf->fir_io & 0xfff8;
2771         tmpword |= 0x0001;
2772         IRDA_DEBUG(1, "GEN2_DEC (write): 0x%04x\n", tmpword);
2773         pci_write_config_word(dev, GEN2_DEC, tmpword);
2774
2775         /* Pre-configure chip */
2776         return preconfigure_smsc_chip(conf);
2777 }
2778
2779 /*
2780  * Pre-configure a certain port on the ALi 1533 bridge.
2781  * This is based on reverse-engineering since ALi does not
2782  * provide any data sheet for the 1533 chip.
2783  */
2784 static void __init preconfigure_ali_port(struct pci_dev *dev,
2785                                          unsigned short port)
2786 {
2787         unsigned char reg;
2788         /* These bits obviously control the different ports */
2789         unsigned char mask;
2790         unsigned char tmpbyte;
2791
2792         switch(port) {
2793         case 0x0130:
2794         case 0x0178:
2795                 reg = 0xb0;
2796                 mask = 0x80;
2797                 break;
2798         case 0x03f8:
2799                 reg = 0xb4;
2800                 mask = 0x80;
2801                 break;
2802         case 0x02f8:
2803                 reg = 0xb4;
2804                 mask = 0x30;
2805                 break;
2806         case 0x02e8:
2807                 reg = 0xb4;
2808                 mask = 0x08;
2809                 break;
2810         default:
2811                 IRDA_ERROR("Failed to configure unsupported port on ALi 1533 bridge: 0x%04x\n", port);
2812                 return;
2813         }
2814
2815         pci_read_config_byte(dev, reg, &tmpbyte);
2816         /* Turn on the right bits */
2817         tmpbyte |= mask;
2818         pci_write_config_byte(dev, reg, tmpbyte);
2819         IRDA_MESSAGE("Activated ALi 1533 ISA bridge port 0x%04x.\n", port);
2820         return;
2821 }
2822
2823 static int __init preconfigure_through_ali(struct pci_dev *dev,
2824                                            struct
2825                                            smsc_ircc_subsystem_configuration
2826                                            *conf)
2827 {
2828         /* Configure the two ports on the ALi 1533 */
2829         preconfigure_ali_port(dev, conf->sir_io);
2830         preconfigure_ali_port(dev, conf->fir_io);
2831
2832         /* Pre-configure chip */
2833         return preconfigure_smsc_chip(conf);
2834 }
2835
2836 static int __init smsc_ircc_preconfigure_subsystems(unsigned short ircc_cfg,
2837                                                     unsigned short ircc_fir,
2838                                                     unsigned short ircc_sir,
2839                                                     unsigned char ircc_dma,
2840                                                     unsigned char ircc_irq)
2841 {
2842         struct pci_dev *dev = NULL;
2843         unsigned short ss_vendor = 0x0000;
2844         unsigned short ss_device = 0x0000;
2845         int ret = 0;
2846
2847         dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2848
2849         while (dev != NULL) {
2850                 struct smsc_ircc_subsystem_configuration *conf;
2851
2852                 /*
2853                  * Cache the subsystem vendor/device:
2854                  * some manufacturers fail to set this for all components,
2855                  * so we save it in case there is just 0x0000 0x0000 on the
2856                  * device we want to check.
2857                  */
2858                 if (dev->subsystem_vendor != 0x0000U) {
2859                         ss_vendor = dev->subsystem_vendor;
2860                         ss_device = dev->subsystem_device;
2861                 }
2862                 conf = subsystem_configurations;
2863                 for( ; conf->subvendor; conf++) {
2864                         if(conf->vendor == dev->vendor &&
2865                            conf->device == dev->device &&
2866                            conf->subvendor == ss_vendor &&
2867                            /* Sometimes these are cached values */
2868                            (conf->subdevice == ss_device ||
2869                             conf->subdevice == 0xffff)) {
2870                                 struct smsc_ircc_subsystem_configuration
2871                                         tmpconf;
2872
2873                                 memcpy(&tmpconf, conf,
2874                                        sizeof(struct smsc_ircc_subsystem_configuration));
2875
2876                                 /*
2877                                  * Override the default values with anything
2878                                  * passed in as parameter
2879                                  */
2880                                 if (ircc_cfg != 0)
2881                                         tmpconf.cfg_base = ircc_cfg;
2882                                 if (ircc_fir != 0)
2883                                         tmpconf.fir_io = ircc_fir;
2884                                 if (ircc_sir != 0)
2885                                         tmpconf.sir_io = ircc_sir;
2886                                 if (ircc_dma != DMA_INVAL)
2887                                         tmpconf.fir_dma = ircc_dma;
2888                                 if (ircc_irq != IRQ_INVAL)
2889                                         tmpconf.fir_irq = ircc_irq;
2890
2891                                 IRDA_MESSAGE("Detected unconfigured %s SMSC IrDA chip, pre-configuring device.\n", conf->name);
2892                                 if (conf->preconfigure)
2893                                         ret = conf->preconfigure(dev, &tmpconf);
2894                                 else
2895                                         ret = -ENODEV;
2896                         }
2897                 }
2898                 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
2899         }
2900
2901         return ret;
2902 }
2903 #endif // CONFIG_PCI
2904
2905 /************************************************
2906  *
2907  * Transceivers specific functions
2908  *
2909  ************************************************/
2910
2911
2912 /*
2913  * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2914  *
2915  *    Program transceiver through smsc-ircc ATC circuitry
2916  *
2917  */
2918
2919 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2920 {
2921         unsigned long jiffies_now, jiffies_timeout;
2922         u8 val;
2923
2924         jiffies_now = jiffies;
2925         jiffies_timeout = jiffies + SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2926
2927         /* ATC */
2928         register_bank(fir_base, 4);
2929         outb((inb(fir_base + IRCC_ATC) & IRCC_ATC_MASK) | IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE,
2930              fir_base + IRCC_ATC);
2931
2932         while ((val = (inb(fir_base + IRCC_ATC) & IRCC_ATC_nPROGREADY)) &&
2933                 !time_after(jiffies, jiffies_timeout))
2934                 /* empty */;
2935
2936         if (val)
2937                 IRDA_WARNING("%s(): ATC: 0x%02x\n", __func__,
2938                              inb(fir_base + IRCC_ATC));
2939 }
2940
2941 /*
2942  * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2943  *
2944  *    Probe transceiver smsc-ircc ATC circuitry
2945  *
2946  */
2947
2948 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2949 {
2950         return 0;
2951 }
2952
2953 /*
2954  * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2955  *
2956  *    Set transceiver
2957  *
2958  */
2959
2960 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2961 {
2962         u8 fast_mode;
2963
2964         switch (speed) {
2965         default:
2966         case 576000 :
2967                 fast_mode = 0;
2968                 break;
2969         case 1152000 :
2970         case 4000000 :
2971                 fast_mode = IRCC_LCR_A_FAST;
2972                 break;
2973         }
2974         register_bank(fir_base, 0);
2975         outb((inb(fir_base + IRCC_LCR_A) & 0xbf) | fast_mode, fir_base + IRCC_LCR_A);
2976 }
2977
2978 /*
2979  * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2980  *
2981  *    Probe transceiver
2982  *
2983  */
2984
2985 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2986 {
2987         return 0;
2988 }
2989
2990 /*
2991  * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2992  *
2993  *    Set transceiver
2994  *
2995  */
2996
2997 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2998 {
2999         u8 fast_mode;
3000
3001         switch (speed) {
3002         default:
3003         case 576000 :
3004                 fast_mode = 0;
3005                 break;
3006         case 1152000 :
3007         case 4000000 :
3008                 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
3009                 break;
3010
3011         }
3012         /* This causes an interrupt */
3013         register_bank(fir_base, 0);
3014         outb((inb(fir_base + IRCC_LCR_A) &  0xbf) | fast_mode, fir_base + IRCC_LCR_A);
3015 }
3016
3017 /*
3018  * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
3019  *
3020  *    Probe transceiver
3021  *
3022  */
3023
3024 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
3025 {
3026         return 0;
3027 }
3028
3029
3030 module_init(smsc_ircc_init);
3031 module_exit(smsc_ircc_cleanup);