2 * ipg.c: Device Driver for the IP1000 Gigabit Ethernet Adapter
4 * Copyright (C) 2003, 2007 IC Plus Corp
9 * Sundance Technology, Inc.
11 * craig_rich@sundanceti.com
16 * http://www.icplus.com.tw
17 * sorbica@icplus.com.tw
20 * http://www.icplus.com.tw
23 #include <linux/crc32.h>
24 #include <linux/ethtool.h>
25 #include <linux/mii.h>
26 #include <linux/mutex.h>
28 #include <asm/div64.h>
30 #define IPG_RX_RING_BYTES (sizeof(struct ipg_rx) * IPG_RFDLIST_LENGTH)
31 #define IPG_TX_RING_BYTES (sizeof(struct ipg_tx) * IPG_TFDLIST_LENGTH)
32 #define IPG_RESET_MASK \
33 (IPG_AC_GLOBAL_RESET | IPG_AC_RX_RESET | IPG_AC_TX_RESET | \
34 IPG_AC_DMA | IPG_AC_FIFO | IPG_AC_NETWORK | IPG_AC_HOST | \
37 #define ipg_w32(val32, reg) iowrite32((val32), ioaddr + (reg))
38 #define ipg_w16(val16, reg) iowrite16((val16), ioaddr + (reg))
39 #define ipg_w8(val8, reg) iowrite8((val8), ioaddr + (reg))
41 #define ipg_r32(reg) ioread32(ioaddr + (reg))
42 #define ipg_r16(reg) ioread16(ioaddr + (reg))
43 #define ipg_r8(reg) ioread8(ioaddr + (reg))
45 #define JUMBO_FRAME_4k_ONLY
51 #define DRV_NAME "ipg"
53 MODULE_AUTHOR("IC Plus Corp. 2003");
54 MODULE_DESCRIPTION("IC Plus IP1000 Gigabit Ethernet Adapter Linux Driver");
55 MODULE_LICENSE("GPL");
58 * Variable record -- index by leading revision/length
59 * Revision/Length(=N*4), Address1, Data1, Address2, Data2,...,AddressN,DataN
61 static unsigned short DefaultPhyParam[] = {
62 /* 11/12/03 IP1000A v1-3 rev=0x40 */
63 /*--------------------------------------------------------------------------
64 (0x4000|(15*4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 22, 0x85bd, 24, 0xfff2,
65 27, 0x0c10, 28, 0x0c10, 29, 0x2c10, 31, 0x0003, 23, 0x92f6,
66 31, 0x0000, 23, 0x003d, 30, 0x00de, 20, 0x20e7, 9, 0x0700,
67 --------------------------------------------------------------------------*/
68 /* 12/17/03 IP1000A v1-4 rev=0x40 */
69 (0x4000 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
71 30, 0x005e, 9, 0x0700,
72 /* 01/09/04 IP1000A v1-5 rev=0x41 */
73 (0x4100 | (07 * 4)), 31, 0x0001, 27, 0x01e0, 31, 0x0002, 27, 0xeb8e, 31,
75 30, 0x005e, 9, 0x0700,
79 static const char *ipg_brand_name[] = {
80 "IC PLUS IP1000 1000/100/10 based NIC",
81 "Sundance Technology ST2021 based NIC",
82 "Tamarack Microelectronics TC9020/9021 based NIC",
83 "Tamarack Microelectronics TC9020/9021 based NIC",
88 static struct pci_device_id ipg_pci_tbl[] __devinitdata = {
89 { PCI_VDEVICE(SUNDANCE, 0x1023), 0 },
90 { PCI_VDEVICE(SUNDANCE, 0x2021), 1 },
91 { PCI_VDEVICE(SUNDANCE, 0x1021), 2 },
92 { PCI_VDEVICE(DLINK, 0x9021), 3 },
93 { PCI_VDEVICE(DLINK, 0x4000), 4 },
94 { PCI_VDEVICE(DLINK, 0x4020), 5 },
98 MODULE_DEVICE_TABLE(pci, ipg_pci_tbl);
100 static inline void __iomem *ipg_ioaddr(struct net_device *dev)
102 struct ipg_nic_private *sp = netdev_priv(dev);
107 static void ipg_dump_rfdlist(struct net_device *dev)
109 struct ipg_nic_private *sp = netdev_priv(dev);
110 void __iomem *ioaddr = sp->ioaddr;
114 IPG_DEBUG_MSG("_dump_rfdlist\n");
116 printk(KERN_INFO "rx_current = %2.2x\n", sp->rx_current);
117 printk(KERN_INFO "rx_dirty = %2.2x\n", sp->rx_dirty);
118 printk(KERN_INFO "RFDList start address = %16.16lx\n",
119 (unsigned long) sp->rxd_map);
120 printk(KERN_INFO "RFDListPtr register = %8.8x%8.8x\n",
121 ipg_r32(IPG_RFDLISTPTR1), ipg_r32(IPG_RFDLISTPTR0));
123 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
124 offset = (u32) &sp->rxd[i].next_desc - (u32) sp->rxd;
125 printk(KERN_INFO "%2.2x %4.4x RFDNextPtr = %16.16lx\n", i,
126 offset, (unsigned long) sp->rxd[i].next_desc);
127 offset = (u32) &sp->rxd[i].rfs - (u32) sp->rxd;
128 printk(KERN_INFO "%2.2x %4.4x RFS = %16.16lx\n", i,
129 offset, (unsigned long) sp->rxd[i].rfs);
130 offset = (u32) &sp->rxd[i].frag_info - (u32) sp->rxd;
131 printk(KERN_INFO "%2.2x %4.4x frag_info = %16.16lx\n", i,
132 offset, (unsigned long) sp->rxd[i].frag_info);
136 static void ipg_dump_tfdlist(struct net_device *dev)
138 struct ipg_nic_private *sp = netdev_priv(dev);
139 void __iomem *ioaddr = sp->ioaddr;
143 IPG_DEBUG_MSG("_dump_tfdlist\n");
145 printk(KERN_INFO "tx_current = %2.2x\n", sp->tx_current);
146 printk(KERN_INFO "tx_dirty = %2.2x\n", sp->tx_dirty);
147 printk(KERN_INFO "TFDList start address = %16.16lx\n",
148 (unsigned long) sp->txd_map);
149 printk(KERN_INFO "TFDListPtr register = %8.8x%8.8x\n",
150 ipg_r32(IPG_TFDLISTPTR1), ipg_r32(IPG_TFDLISTPTR0));
152 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
153 offset = (u32) &sp->txd[i].next_desc - (u32) sp->txd;
154 printk(KERN_INFO "%2.2x %4.4x TFDNextPtr = %16.16lx\n", i,
155 offset, (unsigned long) sp->txd[i].next_desc);
157 offset = (u32) &sp->txd[i].tfc - (u32) sp->txd;
158 printk(KERN_INFO "%2.2x %4.4x TFC = %16.16lx\n", i,
159 offset, (unsigned long) sp->txd[i].tfc);
160 offset = (u32) &sp->txd[i].frag_info - (u32) sp->txd;
161 printk(KERN_INFO "%2.2x %4.4x frag_info = %16.16lx\n", i,
162 offset, (unsigned long) sp->txd[i].frag_info);
167 static void ipg_write_phy_ctl(void __iomem *ioaddr, u8 data)
169 ipg_w8(IPG_PC_RSVD_MASK & data, PHY_CTRL);
170 ndelay(IPG_PC_PHYCTRLWAIT_NS);
173 static void ipg_drive_phy_ctl_low_high(void __iomem *ioaddr, u8 data)
175 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | data);
176 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | data);
179 static void send_three_state(void __iomem *ioaddr, u8 phyctrlpolarity)
181 phyctrlpolarity |= (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR;
183 ipg_drive_phy_ctl_low_high(ioaddr, phyctrlpolarity);
186 static void send_end(void __iomem *ioaddr, u8 phyctrlpolarity)
188 ipg_w8((IPG_PC_MGMTCLK_LO | (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR |
189 phyctrlpolarity) & IPG_PC_RSVD_MASK, PHY_CTRL);
192 static u16 read_phy_bit(void __iomem *ioaddr, u8 phyctrlpolarity)
196 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | phyctrlpolarity);
198 bit_data = ((ipg_r8(PHY_CTRL) & IPG_PC_MGMTDATA) >> 1) & 1;
200 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | phyctrlpolarity);
206 * Read a register from the Physical Layer device located
207 * on the IPG NIC, using the IPG PHYCTRL register.
209 static int mdio_read(struct net_device *dev, int phy_id, int phy_reg)
211 void __iomem *ioaddr = ipg_ioaddr(dev);
213 * The GMII mangement frame structure for a read is as follows:
215 * |Preamble|st|op|phyad|regad|ta| data |idle|
216 * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z |
218 * <32 1s> = 32 consecutive logic 1 values
219 * A = bit of Physical Layer device address (MSB first)
220 * R = bit of register address (MSB first)
221 * z = High impedance state
222 * D = bit of read data (MSB first)
224 * Transmission order is 'Preamble' field first, bits transmitted
225 * left to right (first to last).
231 { GMII_PREAMBLE, 32 }, /* Preamble */
232 { GMII_ST, 2 }, /* ST */
233 { GMII_READ, 2 }, /* OP */
234 { phy_id, 5 }, /* PHYAD */
235 { phy_reg, 5 }, /* REGAD */
236 { 0x0000, 2 }, /* TA */
237 { 0x0000, 16 }, /* DATA */
238 { 0x0000, 1 } /* IDLE */
243 polarity = ipg_r8(PHY_CTRL);
244 polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
246 /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
247 for (j = 0; j < 5; j++) {
248 for (i = 0; i < p[j].len; i++) {
249 /* For each variable length field, the MSB must be
250 * transmitted first. Rotate through the field bits,
251 * starting with the MSB, and move each bit into the
252 * the 1st (2^1) bit position (this is the bit position
253 * corresponding to the MgmtData bit of the PhyCtrl
254 * register for the IPG).
258 * First write a '0' to bit 1 of the PhyCtrl
259 * register, then write a '1' to bit 1 of the
262 * To do this, right shift the MSB of ST by the value:
263 * [field length - 1 - #ST bits already written]
264 * then left shift this result by 1.
266 data = (p[j].field >> (p[j].len - 1 - i)) << 1;
267 data &= IPG_PC_MGMTDATA;
268 data |= polarity | IPG_PC_MGMTDIR;
270 ipg_drive_phy_ctl_low_high(ioaddr, data);
274 send_three_state(ioaddr, polarity);
276 read_phy_bit(ioaddr, polarity);
279 * For a read cycle, the bits for the next two fields (TA and
280 * DATA) are driven by the PHY (the IPG reads these bits).
282 for (i = 0; i < p[6].len; i++) {
284 (read_phy_bit(ioaddr, polarity) << (p[6].len - 1 - i));
287 send_three_state(ioaddr, polarity);
288 send_three_state(ioaddr, polarity);
289 send_three_state(ioaddr, polarity);
290 send_end(ioaddr, polarity);
292 /* Return the value of the DATA field. */
297 * Write to a register from the Physical Layer device located
298 * on the IPG NIC, using the IPG PHYCTRL register.
300 static void mdio_write(struct net_device *dev, int phy_id, int phy_reg, int val)
302 void __iomem *ioaddr = ipg_ioaddr(dev);
304 * The GMII mangement frame structure for a read is as follows:
306 * |Preamble|st|op|phyad|regad|ta| data |idle|
307 * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z |
309 * <32 1s> = 32 consecutive logic 1 values
310 * A = bit of Physical Layer device address (MSB first)
311 * R = bit of register address (MSB first)
312 * z = High impedance state
313 * D = bit of write data (MSB first)
315 * Transmission order is 'Preamble' field first, bits transmitted
316 * left to right (first to last).
322 { GMII_PREAMBLE, 32 }, /* Preamble */
323 { GMII_ST, 2 }, /* ST */
324 { GMII_WRITE, 2 }, /* OP */
325 { phy_id, 5 }, /* PHYAD */
326 { phy_reg, 5 }, /* REGAD */
327 { 0x0002, 2 }, /* TA */
328 { val & 0xffff, 16 }, /* DATA */
329 { 0x0000, 1 } /* IDLE */
334 polarity = ipg_r8(PHY_CTRL);
335 polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
337 /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
338 for (j = 0; j < 7; j++) {
339 for (i = 0; i < p[j].len; i++) {
340 /* For each variable length field, the MSB must be
341 * transmitted first. Rotate through the field bits,
342 * starting with the MSB, and move each bit into the
343 * the 1st (2^1) bit position (this is the bit position
344 * corresponding to the MgmtData bit of the PhyCtrl
345 * register for the IPG).
349 * First write a '0' to bit 1 of the PhyCtrl
350 * register, then write a '1' to bit 1 of the
353 * To do this, right shift the MSB of ST by the value:
354 * [field length - 1 - #ST bits already written]
355 * then left shift this result by 1.
357 data = (p[j].field >> (p[j].len - 1 - i)) << 1;
358 data &= IPG_PC_MGMTDATA;
359 data |= polarity | IPG_PC_MGMTDIR;
361 ipg_drive_phy_ctl_low_high(ioaddr, data);
365 /* The last cycle is a tri-state, so read from the PHY. */
366 for (j = 7; j < 8; j++) {
367 for (i = 0; i < p[j].len; i++) {
368 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | polarity);
370 p[j].field |= ((ipg_r8(PHY_CTRL) &
371 IPG_PC_MGMTDATA) >> 1) << (p[j].len - 1 - i);
373 ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | polarity);
378 static void ipg_set_led_mode(struct net_device *dev)
380 struct ipg_nic_private *sp = netdev_priv(dev);
381 void __iomem *ioaddr = sp->ioaddr;
384 mode = ipg_r32(ASIC_CTRL);
385 mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
387 if ((sp->led_mode & 0x03) > 1)
388 mode |= IPG_AC_LED_MODE_BIT_1; /* Write Asic Control Bit 29 */
390 if ((sp->led_mode & 0x01) == 1)
391 mode |= IPG_AC_LED_MODE; /* Write Asic Control Bit 14 */
393 if ((sp->led_mode & 0x08) == 8)
394 mode |= IPG_AC_LED_SPEED; /* Write Asic Control Bit 27 */
396 ipg_w32(mode, ASIC_CTRL);
399 static void ipg_set_phy_set(struct net_device *dev)
401 struct ipg_nic_private *sp = netdev_priv(dev);
402 void __iomem *ioaddr = sp->ioaddr;
405 physet = ipg_r8(PHY_SET);
406 physet &= ~(IPG_PS_MEM_LENB9B | IPG_PS_MEM_LEN9 | IPG_PS_NON_COMPDET);
407 physet |= ((sp->led_mode & 0x70) >> 4);
408 ipg_w8(physet, PHY_SET);
411 static int ipg_reset(struct net_device *dev, u32 resetflags)
413 /* Assert functional resets via the IPG AsicCtrl
414 * register as specified by the 'resetflags' input
417 void __iomem *ioaddr = ipg_ioaddr(dev);
418 unsigned int timeout_count = 0;
420 IPG_DEBUG_MSG("_reset\n");
422 ipg_w32(ipg_r32(ASIC_CTRL) | resetflags, ASIC_CTRL);
424 /* Delay added to account for problem with 10Mbps reset. */
425 mdelay(IPG_AC_RESETWAIT);
427 while (IPG_AC_RESET_BUSY & ipg_r32(ASIC_CTRL)) {
428 mdelay(IPG_AC_RESETWAIT);
429 if (++timeout_count > IPG_AC_RESET_TIMEOUT)
432 /* Set LED Mode in Asic Control */
433 ipg_set_led_mode(dev);
435 /* Set PHYSet Register Value */
436 ipg_set_phy_set(dev);
440 /* Find the GMII PHY address. */
441 static int ipg_find_phyaddr(struct net_device *dev)
443 unsigned int phyaddr, i;
445 for (i = 0; i < 32; i++) {
448 /* Search for the correct PHY address among 32 possible. */
449 phyaddr = (IPG_NIC_PHY_ADDRESS + i) % 32;
451 /* 10/22/03 Grace change verify from GMII_PHY_STATUS to
455 status = mdio_read(dev, phyaddr, MII_BMSR);
457 if ((status != 0xFFFF) && (status != 0))
465 * Configure IPG based on result of IEEE 802.3 PHY
468 static int ipg_config_autoneg(struct net_device *dev)
470 struct ipg_nic_private *sp = netdev_priv(dev);
471 void __iomem *ioaddr = sp->ioaddr;
472 unsigned int txflowcontrol;
473 unsigned int rxflowcontrol;
474 unsigned int fullduplex;
479 IPG_DEBUG_MSG("_config_autoneg\n");
481 asicctrl = ipg_r32(ASIC_CTRL);
482 phyctrl = ipg_r8(PHY_CTRL);
483 mac_ctrl_val = ipg_r32(MAC_CTRL);
485 /* Set flags for use in resolving auto-negotation, assuming
486 * non-1000Mbps, half duplex, no flow control.
492 /* To accomodate a problem in 10Mbps operation,
493 * set a global flag if PHY running in 10Mbps mode.
497 printk(KERN_INFO "%s: Link speed = ", dev->name);
499 /* Determine actual speed of operation. */
500 switch (phyctrl & IPG_PC_LINK_SPEED) {
501 case IPG_PC_LINK_SPEED_10MBPS:
503 printk(KERN_INFO "%s: 10Mbps operational mode enabled.\n",
507 case IPG_PC_LINK_SPEED_100MBPS:
508 printk("100Mbps.\n");
510 case IPG_PC_LINK_SPEED_1000MBPS:
511 printk("1000Mbps.\n");
514 printk("undefined!\n");
518 if (phyctrl & IPG_PC_DUPLEX_STATUS) {
524 /* Configure full duplex, and flow control. */
525 if (fullduplex == 1) {
526 /* Configure IPG for full duplex operation. */
527 printk(KERN_INFO "%s: setting full duplex, ", dev->name);
529 mac_ctrl_val |= IPG_MC_DUPLEX_SELECT_FD;
531 if (txflowcontrol == 1) {
532 printk("TX flow control");
533 mac_ctrl_val |= IPG_MC_TX_FLOW_CONTROL_ENABLE;
535 printk("no TX flow control");
536 mac_ctrl_val &= ~IPG_MC_TX_FLOW_CONTROL_ENABLE;
539 if (rxflowcontrol == 1) {
540 printk(", RX flow control.");
541 mac_ctrl_val |= IPG_MC_RX_FLOW_CONTROL_ENABLE;
543 printk(", no RX flow control.");
544 mac_ctrl_val &= ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
549 /* Configure IPG for half duplex operation. */
550 printk(KERN_INFO "%s: setting half duplex, "
551 "no TX flow control, no RX flow control.\n", dev->name);
553 mac_ctrl_val &= ~IPG_MC_DUPLEX_SELECT_FD &
554 ~IPG_MC_TX_FLOW_CONTROL_ENABLE &
555 ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
557 ipg_w32(mac_ctrl_val, MAC_CTRL);
561 /* Determine and configure multicast operation and set
562 * receive mode for IPG.
564 static void ipg_nic_set_multicast_list(struct net_device *dev)
566 void __iomem *ioaddr = ipg_ioaddr(dev);
567 struct dev_mc_list *mc_list_ptr;
568 unsigned int hashindex;
572 IPG_DEBUG_MSG("_nic_set_multicast_list\n");
574 receivemode = IPG_RM_RECEIVEUNICAST | IPG_RM_RECEIVEBROADCAST;
576 if (dev->flags & IFF_PROMISC) {
577 /* NIC to be configured in promiscuous mode. */
578 receivemode = IPG_RM_RECEIVEALLFRAMES;
579 } else if ((dev->flags & IFF_ALLMULTI) ||
580 ((dev->flags & IFF_MULTICAST) &&
581 (dev->mc_count > IPG_MULTICAST_HASHTABLE_SIZE))) {
582 /* NIC to be configured to receive all multicast
584 receivemode |= IPG_RM_RECEIVEMULTICAST;
585 } else if ((dev->flags & IFF_MULTICAST) && (dev->mc_count > 0)) {
586 /* NIC to be configured to receive selected
587 * multicast addresses. */
588 receivemode |= IPG_RM_RECEIVEMULTICASTHASH;
591 /* Calculate the bits to set for the 64 bit, IPG HASHTABLE.
592 * The IPG applies a cyclic-redundancy-check (the same CRC
593 * used to calculate the frame data FCS) to the destination
594 * address all incoming multicast frames whose destination
595 * address has the multicast bit set. The least significant
596 * 6 bits of the CRC result are used as an addressing index
597 * into the hash table. If the value of the bit addressed by
598 * this index is a 1, the frame is passed to the host system.
601 /* Clear hashtable. */
602 hashtable[0] = 0x00000000;
603 hashtable[1] = 0x00000000;
605 /* Cycle through all multicast addresses to filter. */
606 for (mc_list_ptr = dev->mc_list;
607 mc_list_ptr != NULL; mc_list_ptr = mc_list_ptr->next) {
608 /* Calculate CRC result for each multicast address. */
609 hashindex = crc32_le(0xffffffff, mc_list_ptr->dmi_addr,
612 /* Use only the least significant 6 bits. */
613 hashindex = hashindex & 0x3F;
615 /* Within "hashtable", set bit number "hashindex"
618 set_bit(hashindex, (void *)hashtable);
621 /* Write the value of the hashtable, to the 4, 16 bit
622 * HASHTABLE IPG registers.
624 ipg_w32(hashtable[0], HASHTABLE_0);
625 ipg_w32(hashtable[1], HASHTABLE_1);
627 ipg_w8(IPG_RM_RSVD_MASK & receivemode, RECEIVE_MODE);
629 IPG_DEBUG_MSG("ReceiveMode = %x\n", ipg_r8(RECEIVE_MODE));
632 static int ipg_io_config(struct net_device *dev)
634 void __iomem *ioaddr = ipg_ioaddr(dev);
638 IPG_DEBUG_MSG("_io_config\n");
640 origmacctrl = ipg_r32(MAC_CTRL);
642 restoremacctrl = origmacctrl | IPG_MC_STATISTICS_ENABLE;
644 /* Based on compilation option, determine if FCS is to be
645 * stripped on receive frames by IPG.
647 if (!IPG_STRIP_FCS_ON_RX)
648 restoremacctrl |= IPG_MC_RCV_FCS;
650 /* Determine if transmitter and/or receiver are
651 * enabled so we may restore MACCTRL correctly.
653 if (origmacctrl & IPG_MC_TX_ENABLED)
654 restoremacctrl |= IPG_MC_TX_ENABLE;
656 if (origmacctrl & IPG_MC_RX_ENABLED)
657 restoremacctrl |= IPG_MC_RX_ENABLE;
659 /* Transmitter and receiver must be disabled before setting
662 ipg_w32((origmacctrl & (IPG_MC_RX_DISABLE | IPG_MC_TX_DISABLE)) &
663 IPG_MC_RSVD_MASK, MAC_CTRL);
665 /* Now that transmitter and receiver are disabled, write
668 ipg_w32((origmacctrl & IPG_MC_IFS_96BIT) & IPG_MC_RSVD_MASK, MAC_CTRL);
670 /* Set RECEIVEMODE register. */
671 ipg_nic_set_multicast_list(dev);
673 ipg_w16(IPG_MAX_RXFRAME_SIZE, MAX_FRAME_SIZE);
675 ipg_w8(IPG_RXDMAPOLLPERIOD_VALUE, RX_DMA_POLL_PERIOD);
676 ipg_w8(IPG_RXDMAURGENTTHRESH_VALUE, RX_DMA_URGENT_THRESH);
677 ipg_w8(IPG_RXDMABURSTTHRESH_VALUE, RX_DMA_BURST_THRESH);
678 ipg_w8(IPG_TXDMAPOLLPERIOD_VALUE, TX_DMA_POLL_PERIOD);
679 ipg_w8(IPG_TXDMAURGENTTHRESH_VALUE, TX_DMA_URGENT_THRESH);
680 ipg_w8(IPG_TXDMABURSTTHRESH_VALUE, TX_DMA_BURST_THRESH);
681 ipg_w16((IPG_IE_HOST_ERROR | IPG_IE_TX_DMA_COMPLETE |
682 IPG_IE_TX_COMPLETE | IPG_IE_INT_REQUESTED |
683 IPG_IE_UPDATE_STATS | IPG_IE_LINK_EVENT |
684 IPG_IE_RX_DMA_COMPLETE | IPG_IE_RX_DMA_PRIORITY), INT_ENABLE);
685 ipg_w16(IPG_FLOWONTHRESH_VALUE, FLOW_ON_THRESH);
686 ipg_w16(IPG_FLOWOFFTHRESH_VALUE, FLOW_OFF_THRESH);
688 /* IPG multi-frag frame bug workaround.
689 * Per silicon revision B3 eratta.
691 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0200, DEBUG_CTRL);
693 /* IPG TX poll now bug workaround.
694 * Per silicon revision B3 eratta.
696 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0010, DEBUG_CTRL);
698 /* IPG RX poll now bug workaround.
699 * Per silicon revision B3 eratta.
701 ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0020, DEBUG_CTRL);
703 /* Now restore MACCTRL to original setting. */
704 ipg_w32(IPG_MC_RSVD_MASK & restoremacctrl, MAC_CTRL);
706 /* Disable unused RMON statistics. */
707 ipg_w32(IPG_RZ_ALL, RMON_STATISTICS_MASK);
709 /* Disable unused MIB statistics. */
710 ipg_w32(IPG_SM_MACCONTROLFRAMESXMTD | IPG_SM_MACCONTROLFRAMESRCVD |
711 IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK | IPG_SM_TXJUMBOFRAMES |
712 IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK | IPG_SM_RXJUMBOFRAMES |
713 IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK |
714 IPG_SM_UDPCHECKSUMERRORS | IPG_SM_TCPCHECKSUMERRORS |
715 IPG_SM_IPCHECKSUMERRORS, STATISTICS_MASK);
721 * Create a receive buffer within system memory and update
722 * NIC private structure appropriately.
724 static int ipg_get_rxbuff(struct net_device *dev, int entry)
726 struct ipg_nic_private *sp = netdev_priv(dev);
727 struct ipg_rx *rxfd = sp->rxd + entry;
731 IPG_DEBUG_MSG("_get_rxbuff\n");
733 skb = netdev_alloc_skb(dev, IPG_RXSUPPORT_SIZE + NET_IP_ALIGN);
735 sp->rx_buff[entry] = NULL;
739 /* Adjust the data start location within the buffer to
740 * align IP address field to a 16 byte boundary.
742 skb_reserve(skb, NET_IP_ALIGN);
744 /* Associate the receive buffer with the IPG NIC. */
747 /* Save the address of the sk_buff structure. */
748 sp->rx_buff[entry] = skb;
750 rxfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
751 sp->rx_buf_sz, PCI_DMA_FROMDEVICE));
753 /* Set the RFD fragment length. */
754 rxfragsize = IPG_RXFRAG_SIZE;
755 rxfd->frag_info |= cpu_to_le64((rxfragsize << 48) & IPG_RFI_FRAGLEN);
760 static int init_rfdlist(struct net_device *dev)
762 struct ipg_nic_private *sp = netdev_priv(dev);
763 void __iomem *ioaddr = sp->ioaddr;
766 IPG_DEBUG_MSG("_init_rfdlist\n");
768 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
769 struct ipg_rx *rxfd = sp->rxd + i;
771 if (sp->rx_buff[i]) {
772 pci_unmap_single(sp->pdev,
773 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
774 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
775 dev_kfree_skb_irq(sp->rx_buff[i]);
776 sp->rx_buff[i] = NULL;
779 /* Clear out the RFS field. */
780 rxfd->rfs = 0x0000000000000000;
782 if (ipg_get_rxbuff(dev, i) < 0) {
784 * A receive buffer was not ready, break the
787 IPG_DEBUG_MSG("Cannot allocate Rx buffer.\n");
789 /* Just in case we cannot allocate a single RFD.
793 printk(KERN_ERR "%s: No memory available"
794 " for RFD list.\n", dev->name);
799 rxfd->next_desc = cpu_to_le64(sp->rxd_map +
800 sizeof(struct ipg_rx)*(i + 1));
802 sp->rxd[i - 1].next_desc = cpu_to_le64(sp->rxd_map);
807 /* Write the location of the RFDList to the IPG. */
808 ipg_w32((u32) sp->rxd_map, RFD_LIST_PTR_0);
809 ipg_w32(0x00000000, RFD_LIST_PTR_1);
814 static void init_tfdlist(struct net_device *dev)
816 struct ipg_nic_private *sp = netdev_priv(dev);
817 void __iomem *ioaddr = sp->ioaddr;
820 IPG_DEBUG_MSG("_init_tfdlist\n");
822 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
823 struct ipg_tx *txfd = sp->txd + i;
825 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
827 if (sp->tx_buff[i]) {
828 dev_kfree_skb_irq(sp->tx_buff[i]);
829 sp->tx_buff[i] = NULL;
832 txfd->next_desc = cpu_to_le64(sp->txd_map +
833 sizeof(struct ipg_tx)*(i + 1));
835 sp->txd[i - 1].next_desc = cpu_to_le64(sp->txd_map);
840 /* Write the location of the TFDList to the IPG. */
841 IPG_DDEBUG_MSG("Starting TFDListPtr = %8.8x\n",
843 ipg_w32((u32) sp->txd_map, TFD_LIST_PTR_0);
844 ipg_w32(0x00000000, TFD_LIST_PTR_1);
846 sp->reset_current_tfd = 1;
850 * Free all transmit buffers which have already been transfered
851 * via DMA to the IPG.
853 static void ipg_nic_txfree(struct net_device *dev)
855 struct ipg_nic_private *sp = netdev_priv(dev);
856 unsigned int released, pending, dirty;
858 IPG_DEBUG_MSG("_nic_txfree\n");
860 pending = sp->tx_current - sp->tx_dirty;
861 dirty = sp->tx_dirty % IPG_TFDLIST_LENGTH;
863 for (released = 0; released < pending; released++) {
864 struct sk_buff *skb = sp->tx_buff[dirty];
865 struct ipg_tx *txfd = sp->txd + dirty;
867 IPG_DEBUG_MSG("TFC = %16.16lx\n", (unsigned long) txfd->tfc);
869 /* Look at each TFD's TFC field beginning
870 * at the last freed TFD up to the current TFD.
871 * If the TFDDone bit is set, free the associated
874 if (!(txfd->tfc & cpu_to_le64(IPG_TFC_TFDDONE)))
877 /* Free the transmit buffer. */
879 pci_unmap_single(sp->pdev,
880 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
881 skb->len, PCI_DMA_TODEVICE);
883 dev_kfree_skb_irq(skb);
885 sp->tx_buff[dirty] = NULL;
887 dirty = (dirty + 1) % IPG_TFDLIST_LENGTH;
890 sp->tx_dirty += released;
892 if (netif_queue_stopped(dev) &&
893 (sp->tx_current != (sp->tx_dirty + IPG_TFDLIST_LENGTH))) {
894 netif_wake_queue(dev);
898 static void ipg_tx_timeout(struct net_device *dev)
900 struct ipg_nic_private *sp = netdev_priv(dev);
901 void __iomem *ioaddr = sp->ioaddr;
903 ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA | IPG_AC_NETWORK |
906 spin_lock_irq(&sp->lock);
908 /* Re-configure after DMA reset. */
909 if (ipg_io_config(dev) < 0) {
910 printk(KERN_INFO "%s: Error during re-configuration.\n",
916 spin_unlock_irq(&sp->lock);
918 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) & IPG_MC_RSVD_MASK,
923 * For TxComplete interrupts, free all transmit
924 * buffers which have already been transfered via DMA
927 static void ipg_nic_txcleanup(struct net_device *dev)
929 struct ipg_nic_private *sp = netdev_priv(dev);
930 void __iomem *ioaddr = sp->ioaddr;
933 IPG_DEBUG_MSG("_nic_txcleanup\n");
935 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
936 /* Reading the TXSTATUS register clears the
937 * TX_COMPLETE interrupt.
939 u32 txstatusdword = ipg_r32(TX_STATUS);
941 IPG_DEBUG_MSG("TxStatus = %8.8x\n", txstatusdword);
943 /* Check for Transmit errors. Error bits only valid if
944 * TX_COMPLETE bit in the TXSTATUS register is a 1.
946 if (!(txstatusdword & IPG_TS_TX_COMPLETE))
949 /* If in 10Mbps mode, indicate transmit is ready. */
950 if (sp->tenmbpsmode) {
951 netif_wake_queue(dev);
954 /* Transmit error, increment stat counters. */
955 if (txstatusdword & IPG_TS_TX_ERROR) {
956 IPG_DEBUG_MSG("Transmit error.\n");
957 sp->stats.tx_errors++;
960 /* Late collision, re-enable transmitter. */
961 if (txstatusdword & IPG_TS_LATE_COLLISION) {
962 IPG_DEBUG_MSG("Late collision on transmit.\n");
963 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
964 IPG_MC_RSVD_MASK, MAC_CTRL);
967 /* Maximum collisions, re-enable transmitter. */
968 if (txstatusdword & IPG_TS_TX_MAX_COLL) {
969 IPG_DEBUG_MSG("Maximum collisions on transmit.\n");
970 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
971 IPG_MC_RSVD_MASK, MAC_CTRL);
974 /* Transmit underrun, reset and re-enable
977 if (txstatusdword & IPG_TS_TX_UNDERRUN) {
978 IPG_DEBUG_MSG("Transmitter underrun.\n");
979 sp->stats.tx_fifo_errors++;
980 ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA |
981 IPG_AC_NETWORK | IPG_AC_FIFO);
983 /* Re-configure after DMA reset. */
984 if (ipg_io_config(dev) < 0) {
986 "%s: Error during re-configuration.\n",
991 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
992 IPG_MC_RSVD_MASK, MAC_CTRL);
999 /* Provides statistical information about the IPG NIC. */
1000 static struct net_device_stats *ipg_nic_get_stats(struct net_device *dev)
1002 struct ipg_nic_private *sp = netdev_priv(dev);
1003 void __iomem *ioaddr = sp->ioaddr;
1007 IPG_DEBUG_MSG("_nic_get_stats\n");
1009 /* Check to see if the NIC has been initialized via nic_open,
1010 * before trying to read statistic registers.
1012 if (!test_bit(__LINK_STATE_START, &dev->state))
1015 sp->stats.rx_packets += ipg_r32(IPG_FRAMESRCVDOK);
1016 sp->stats.tx_packets += ipg_r32(IPG_FRAMESXMTDOK);
1017 sp->stats.rx_bytes += ipg_r32(IPG_OCTETRCVOK);
1018 sp->stats.tx_bytes += ipg_r32(IPG_OCTETXMTOK);
1019 temp1 = ipg_r16(IPG_FRAMESLOSTRXERRORS);
1020 sp->stats.rx_errors += temp1;
1021 sp->stats.rx_missed_errors += temp1;
1022 temp1 = ipg_r32(IPG_SINGLECOLFRAMES) + ipg_r32(IPG_MULTICOLFRAMES) +
1023 ipg_r32(IPG_LATECOLLISIONS);
1024 temp2 = ipg_r16(IPG_CARRIERSENSEERRORS);
1025 sp->stats.collisions += temp1;
1026 sp->stats.tx_dropped += ipg_r16(IPG_FRAMESABORTXSCOLLS);
1027 sp->stats.tx_errors += ipg_r16(IPG_FRAMESWEXDEFERRAL) +
1028 ipg_r32(IPG_FRAMESWDEFERREDXMT) + temp1 + temp2;
1029 sp->stats.multicast += ipg_r32(IPG_MCSTOCTETRCVDOK);
1031 /* detailed tx_errors */
1032 sp->stats.tx_carrier_errors += temp2;
1034 /* detailed rx_errors */
1035 sp->stats.rx_length_errors += ipg_r16(IPG_INRANGELENGTHERRORS) +
1036 ipg_r16(IPG_FRAMETOOLONGERRRORS);
1037 sp->stats.rx_crc_errors += ipg_r16(IPG_FRAMECHECKSEQERRORS);
1039 /* Unutilized IPG statistic registers. */
1040 ipg_r32(IPG_MCSTFRAMESRCVDOK);
1045 /* Restore used receive buffers. */
1046 static int ipg_nic_rxrestore(struct net_device *dev)
1048 struct ipg_nic_private *sp = netdev_priv(dev);
1049 const unsigned int curr = sp->rx_current;
1050 unsigned int dirty = sp->rx_dirty;
1052 IPG_DEBUG_MSG("_nic_rxrestore\n");
1054 for (dirty = sp->rx_dirty; curr - dirty > 0; dirty++) {
1055 unsigned int entry = dirty % IPG_RFDLIST_LENGTH;
1057 /* rx_copybreak may poke hole here and there. */
1058 if (sp->rx_buff[entry])
1061 /* Generate a new receive buffer to replace the
1062 * current buffer (which will be released by the
1065 if (ipg_get_rxbuff(dev, entry) < 0) {
1066 IPG_DEBUG_MSG("Cannot allocate new Rx buffer.\n");
1071 /* Reset the RFS field. */
1072 sp->rxd[entry].rfs = 0x0000000000000000;
1074 sp->rx_dirty = dirty;
1081 /* use jumboindex and jumbosize to control jumbo frame status
1082 * initial status is jumboindex=-1 and jumbosize=0
1083 * 1. jumboindex = -1 and jumbosize=0 : previous jumbo frame has been done.
1084 * 2. jumboindex != -1 and jumbosize != 0 : jumbo frame is not over size and receiving
1085 * 3. jumboindex = -1 and jumbosize != 0 : jumbo frame is over size, already dump
1086 * previous receiving and need to continue dumping the current one
1094 FRAME_NO_START_NO_END = 0,
1095 FRAME_WITH_START = 1,
1096 FRAME_WITH_END = 10,
1097 FRAME_WITH_START_WITH_END = 11
1100 inline void ipg_nic_rx_free_skb(struct net_device *dev)
1102 struct ipg_nic_private *sp = netdev_priv(dev);
1103 unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1105 if (sp->rx_buff[entry]) {
1106 struct ipg_rx *rxfd = sp->rxd + entry;
1108 pci_unmap_single(sp->pdev,
1109 le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1110 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1111 dev_kfree_skb_irq(sp->rx_buff[entry]);
1112 sp->rx_buff[entry] = NULL;
1116 inline int ipg_nic_rx_check_frame_type(struct net_device *dev)
1118 struct ipg_nic_private *sp = netdev_priv(dev);
1119 struct ipg_rx *rxfd = sp->rxd + (sp->rx_current % IPG_RFDLIST_LENGTH);
1120 int type = FRAME_NO_START_NO_END;
1122 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART)
1123 type += FRAME_WITH_START;
1124 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND)
1125 type += FRAME_WITH_END;
1129 inline int ipg_nic_rx_check_error(struct net_device *dev)
1131 struct ipg_nic_private *sp = netdev_priv(dev);
1132 unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1133 struct ipg_rx *rxfd = sp->rxd + entry;
1135 if (IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1136 (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1137 IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1138 IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR))) {
1139 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1140 (unsigned long) rxfd->rfs);
1142 /* Increment general receive error statistic. */
1143 sp->stats.rx_errors++;
1145 /* Increment detailed receive error statistics. */
1146 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1147 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1149 sp->stats.rx_fifo_errors++;
1152 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1153 IPG_DEBUG_MSG("RX runt occured.\n");
1154 sp->stats.rx_length_errors++;
1157 /* Do nothing for IPG_RFS_RXOVERSIZEDFRAME,
1158 * error count handled by a IPG statistic register.
1161 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1162 IPG_DEBUG_MSG("RX alignment error occured.\n");
1163 sp->stats.rx_frame_errors++;
1166 /* Do nothing for IPG_RFS_RXFCSERROR, error count
1167 * handled by a IPG statistic register.
1170 /* Free the memory associated with the RX
1171 * buffer since it is erroneous and we will
1172 * not pass it to higher layer processes.
1174 if (sp->rx_buff[entry]) {
1175 pci_unmap_single(sp->pdev,
1176 le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1177 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1179 dev_kfree_skb_irq(sp->rx_buff[entry]);
1180 sp->rx_buff[entry] = NULL;
1182 return ERROR_PACKET;
1184 return NORMAL_PACKET;
1187 static void ipg_nic_rx_with_start_and_end(struct net_device *dev,
1188 struct ipg_nic_private *sp,
1189 struct ipg_rx *rxfd, unsigned entry)
1191 struct ipg_jumbo *jumbo = &sp->jumbo;
1192 struct sk_buff *skb;
1195 if (jumbo->found_start) {
1196 dev_kfree_skb_irq(jumbo->skb);
1197 jumbo->found_start = 0;
1198 jumbo->current_size = 0;
1202 /* 1: found error, 0 no error */
1203 if (ipg_nic_rx_check_error(dev) != NORMAL_PACKET)
1206 skb = sp->rx_buff[entry];
1210 /* accept this frame and send to upper layer */
1211 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1212 if (framelen > IPG_RXFRAG_SIZE)
1213 framelen = IPG_RXFRAG_SIZE;
1215 skb_put(skb, framelen);
1216 skb->protocol = eth_type_trans(skb, dev);
1217 skb->ip_summed = CHECKSUM_NONE;
1219 dev->last_rx = jiffies;
1220 sp->rx_buff[entry] = NULL;
1223 static void ipg_nic_rx_with_start(struct net_device *dev,
1224 struct ipg_nic_private *sp,
1225 struct ipg_rx *rxfd, unsigned entry)
1227 struct ipg_jumbo *jumbo = &sp->jumbo;
1228 struct pci_dev *pdev = sp->pdev;
1229 struct sk_buff *skb;
1231 /* 1: found error, 0 no error */
1232 if (ipg_nic_rx_check_error(dev) != NORMAL_PACKET)
1235 /* accept this frame and send to upper layer */
1236 skb = sp->rx_buff[entry];
1240 if (jumbo->found_start)
1241 dev_kfree_skb_irq(jumbo->skb);
1243 pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1244 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1246 skb_put(skb, IPG_RXFRAG_SIZE);
1248 jumbo->found_start = 1;
1249 jumbo->current_size = IPG_RXFRAG_SIZE;
1252 sp->rx_buff[entry] = NULL;
1253 dev->last_rx = jiffies;
1256 static void ipg_nic_rx_with_end(struct net_device *dev,
1257 struct ipg_nic_private *sp,
1258 struct ipg_rx *rxfd, unsigned entry)
1260 struct ipg_jumbo *jumbo = &sp->jumbo;
1262 /* 1: found error, 0 no error */
1263 if (ipg_nic_rx_check_error(dev) == NORMAL_PACKET) {
1264 struct sk_buff *skb = sp->rx_buff[entry];
1269 if (jumbo->found_start) {
1270 int framelen, endframelen;
1272 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1274 endframelen = framelen - jumbo->current_size;
1276 if (framelen > IPG_RXFRAG_SIZE)
1277 framelen=IPG_RXFRAG_SIZE;
1279 if (framelen > IPG_RXSUPPORT_SIZE)
1280 dev_kfree_skb_irq(jumbo->skb);
1282 memcpy(skb_put(jumbo->skb, endframelen),
1283 skb->data, endframelen);
1285 jumbo->skb->protocol =
1286 eth_type_trans(jumbo->skb, dev);
1288 jumbo->skb->ip_summed = CHECKSUM_NONE;
1289 netif_rx(jumbo->skb);
1293 dev->last_rx = jiffies;
1294 jumbo->found_start = 0;
1295 jumbo->current_size = 0;
1298 ipg_nic_rx_free_skb(dev);
1300 dev_kfree_skb_irq(jumbo->skb);
1301 jumbo->found_start = 0;
1302 jumbo->current_size = 0;
1307 static void ipg_nic_rx_no_start_no_end(struct net_device *dev,
1308 struct ipg_nic_private *sp,
1309 struct ipg_rx *rxfd, unsigned entry)
1311 struct ipg_jumbo *jumbo = &sp->jumbo;
1313 /* 1: found error, 0 no error */
1314 if (ipg_nic_rx_check_error(dev) == NORMAL_PACKET) {
1315 struct sk_buff *skb = sp->rx_buff[entry];
1318 if (jumbo->found_start) {
1319 jumbo->current_size += IPG_RXFRAG_SIZE;
1320 if (jumbo->current_size <= IPG_RXSUPPORT_SIZE) {
1321 memcpy(skb_put(jumbo->skb,
1323 skb->data, IPG_RXFRAG_SIZE);
1326 dev->last_rx = jiffies;
1327 ipg_nic_rx_free_skb(dev);
1330 dev_kfree_skb_irq(jumbo->skb);
1331 jumbo->found_start = 0;
1332 jumbo->current_size = 0;
1337 static int ipg_nic_rx(struct net_device *dev)
1339 struct ipg_nic_private *sp = netdev_priv(dev);
1340 unsigned int curr = sp->rx_current;
1341 void __iomem *ioaddr = sp->ioaddr;
1344 IPG_DEBUG_MSG("_nic_rx\n");
1346 for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1347 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1348 struct ipg_rx *rxfd = sp->rxd + entry;
1350 if (!(rxfd->rfs & le64_to_cpu(IPG_RFS_RFDDONE)))
1353 switch (ipg_nic_rx_check_frame_type(dev)) {
1354 case FRAME_WITH_START_WITH_END:
1355 ipg_nic_rx_with_start_and_end(dev, sp, rxfd, entry);
1357 case FRAME_WITH_START:
1358 ipg_nic_rx_with_start(dev, sp, rxfd, entry);
1360 case FRAME_WITH_END:
1361 ipg_nic_rx_with_end(dev, sp, rxfd, entry);
1363 case FRAME_NO_START_NO_END:
1364 ipg_nic_rx_no_start_no_end(dev, sp, rxfd, entry);
1369 sp->rx_current = curr;
1371 if (i == IPG_MAXRFDPROCESS_COUNT) {
1372 /* There are more RFDs to process, however the
1373 * allocated amount of RFD processing time has
1374 * expired. Assert Interrupt Requested to make
1375 * sure we come back to process the remaining RFDs.
1377 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1380 ipg_nic_rxrestore(dev);
1386 static int ipg_nic_rx(struct net_device *dev)
1388 /* Transfer received Ethernet frames to higher network layers. */
1389 struct ipg_nic_private *sp = netdev_priv(dev);
1390 unsigned int curr = sp->rx_current;
1391 void __iomem *ioaddr = sp->ioaddr;
1392 struct ipg_rx *rxfd;
1395 IPG_DEBUG_MSG("_nic_rx\n");
1397 #define __RFS_MASK \
1398 cpu_to_le64(IPG_RFS_RFDDONE | IPG_RFS_FRAMESTART | IPG_RFS_FRAMEEND)
1400 for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1401 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1402 struct sk_buff *skb = sp->rx_buff[entry];
1403 unsigned int framelen;
1405 rxfd = sp->rxd + entry;
1407 if (((rxfd->rfs & __RFS_MASK) != __RFS_MASK) || !skb)
1410 /* Get received frame length. */
1411 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1413 /* Check for jumbo frame arrival with too small
1416 if (framelen > IPG_RXFRAG_SIZE) {
1418 ("RFS FrameLen > allocated fragment size.\n");
1420 framelen = IPG_RXFRAG_SIZE;
1423 if ((IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1424 (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1425 IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1426 IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR)))) {
1428 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1429 (unsigned long int) rxfd->rfs);
1431 /* Increment general receive error statistic. */
1432 sp->stats.rx_errors++;
1434 /* Increment detailed receive error statistics. */
1435 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1436 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1437 sp->stats.rx_fifo_errors++;
1440 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1441 IPG_DEBUG_MSG("RX runt occured.\n");
1442 sp->stats.rx_length_errors++;
1445 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXOVERSIZEDFRAME) ;
1446 /* Do nothing, error count handled by a IPG
1447 * statistic register.
1450 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1451 IPG_DEBUG_MSG("RX alignment error occured.\n");
1452 sp->stats.rx_frame_errors++;
1455 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFCSERROR) ;
1456 /* Do nothing, error count handled by a IPG
1457 * statistic register.
1460 /* Free the memory associated with the RX
1461 * buffer since it is erroneous and we will
1462 * not pass it to higher layer processes.
1465 __le64 info = rxfd->frag_info;
1467 pci_unmap_single(sp->pdev,
1468 le64_to_cpu(info) & ~IPG_RFI_FRAGLEN,
1469 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1471 dev_kfree_skb_irq(skb);
1475 /* Adjust the new buffer length to accomodate the size
1476 * of the received frame.
1478 skb_put(skb, framelen);
1480 /* Set the buffer's protocol field to Ethernet. */
1481 skb->protocol = eth_type_trans(skb, dev);
1483 /* The IPG encountered an error with (or
1484 * there were no) IP/TCP/UDP checksums.
1485 * This may or may not indicate an invalid
1486 * IP/TCP/UDP frame was received. Let the
1487 * upper layer decide.
1489 skb->ip_summed = CHECKSUM_NONE;
1491 /* Hand off frame for higher layer processing.
1492 * The function netif_rx() releases the sk_buff
1493 * when processing completes.
1497 /* Record frame receive time (jiffies = Linux
1498 * kernel current time stamp).
1500 dev->last_rx = jiffies;
1503 /* Assure RX buffer is not reused by IPG. */
1504 sp->rx_buff[entry] = NULL;
1508 * If there are more RFDs to proces and the allocated amount of RFD
1509 * processing time has expired, assert Interrupt Requested to make
1510 * sure we come back to process the remaining RFDs.
1512 if (i == IPG_MAXRFDPROCESS_COUNT)
1513 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1516 /* Check if the RFD list contained no receive frame data. */
1518 sp->EmptyRFDListCount++;
1520 while ((le64_to_cpu(rxfd->rfs) & IPG_RFS_RFDDONE) &&
1521 !((le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART) &&
1522 (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND))) {
1523 unsigned int entry = curr++ % IPG_RFDLIST_LENGTH;
1525 rxfd = sp->rxd + entry;
1527 IPG_DEBUG_MSG("Frame requires multiple RFDs.\n");
1529 /* An unexpected event, additional code needed to handle
1530 * properly. So for the time being, just disregard the
1534 /* Free the memory associated with the RX
1535 * buffer since it is erroneous and we will
1536 * not pass it to higher layer processes.
1538 if (sp->rx_buff[entry]) {
1539 pci_unmap_single(sp->pdev,
1540 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1541 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1542 dev_kfree_skb_irq(sp->rx_buff[entry]);
1545 /* Assure RX buffer is not reused by IPG. */
1546 sp->rx_buff[entry] = NULL;
1549 sp->rx_current = curr;
1551 /* Check to see if there are a minimum number of used
1552 * RFDs before restoring any (should improve performance.)
1554 if ((curr - sp->rx_dirty) >= IPG_MINUSEDRFDSTOFREE)
1555 ipg_nic_rxrestore(dev);
1561 static void ipg_reset_after_host_error(struct work_struct *work)
1563 struct ipg_nic_private *sp =
1564 container_of(work, struct ipg_nic_private, task.work);
1565 struct net_device *dev = sp->dev;
1567 IPG_DDEBUG_MSG("DMACtrl = %8.8x\n", ioread32(sp->ioaddr + IPG_DMACTRL));
1570 * Acknowledge HostError interrupt by resetting
1573 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1578 if (ipg_io_config(dev) < 0) {
1579 printk(KERN_INFO "%s: Cannot recover from PCI error.\n",
1581 schedule_delayed_work(&sp->task, HZ);
1585 static irqreturn_t ipg_interrupt_handler(int irq, void *dev_inst)
1587 struct net_device *dev = dev_inst;
1588 struct ipg_nic_private *sp = netdev_priv(dev);
1589 void __iomem *ioaddr = sp->ioaddr;
1590 unsigned int handled = 0;
1593 IPG_DEBUG_MSG("_interrupt_handler\n");
1596 ipg_nic_rxrestore(dev);
1598 spin_lock(&sp->lock);
1600 /* Get interrupt source information, and acknowledge
1601 * some (i.e. TxDMAComplete, RxDMAComplete, RxEarly,
1602 * IntRequested, MacControlFrame, LinkEvent) interrupts
1603 * if issued. Also, all IPG interrupts are disabled by
1604 * reading IntStatusAck.
1606 status = ipg_r16(INT_STATUS_ACK);
1608 IPG_DEBUG_MSG("IntStatusAck = %4.4x\n", status);
1610 /* Shared IRQ of remove event. */
1611 if (!(status & IPG_IS_RSVD_MASK))
1616 if (unlikely(!netif_running(dev)))
1619 /* If RFDListEnd interrupt, restore all used RFDs. */
1620 if (status & IPG_IS_RFD_LIST_END) {
1621 IPG_DEBUG_MSG("RFDListEnd Interrupt.\n");
1623 /* The RFD list end indicates an RFD was encountered
1624 * with a 0 NextPtr, or with an RFDDone bit set to 1
1625 * (indicating the RFD is not read for use by the
1626 * IPG.) Try to restore all RFDs.
1628 ipg_nic_rxrestore(dev);
1631 /* Increment the RFDlistendCount counter. */
1632 sp->RFDlistendCount++;
1636 /* If RFDListEnd, RxDMAPriority, RxDMAComplete, or
1637 * IntRequested interrupt, process received frames. */
1638 if ((status & IPG_IS_RX_DMA_PRIORITY) ||
1639 (status & IPG_IS_RFD_LIST_END) ||
1640 (status & IPG_IS_RX_DMA_COMPLETE) ||
1641 (status & IPG_IS_INT_REQUESTED)) {
1643 /* Increment the RFD list checked counter if interrupted
1644 * only to check the RFD list. */
1645 if (status & (~(IPG_IS_RX_DMA_PRIORITY | IPG_IS_RFD_LIST_END |
1646 IPG_IS_RX_DMA_COMPLETE | IPG_IS_INT_REQUESTED) &
1647 (IPG_IS_HOST_ERROR | IPG_IS_TX_DMA_COMPLETE |
1648 IPG_IS_LINK_EVENT | IPG_IS_TX_COMPLETE |
1649 IPG_IS_UPDATE_STATS)))
1650 sp->RFDListCheckedCount++;
1656 /* If TxDMAComplete interrupt, free used TFDs. */
1657 if (status & IPG_IS_TX_DMA_COMPLETE)
1658 ipg_nic_txfree(dev);
1660 /* TxComplete interrupts indicate one of numerous actions.
1661 * Determine what action to take based on TXSTATUS register.
1663 if (status & IPG_IS_TX_COMPLETE)
1664 ipg_nic_txcleanup(dev);
1666 /* If UpdateStats interrupt, update Linux Ethernet statistics */
1667 if (status & IPG_IS_UPDATE_STATS)
1668 ipg_nic_get_stats(dev);
1670 /* If HostError interrupt, reset IPG. */
1671 if (status & IPG_IS_HOST_ERROR) {
1672 IPG_DDEBUG_MSG("HostError Interrupt\n");
1674 schedule_delayed_work(&sp->task, 0);
1677 /* If LinkEvent interrupt, resolve autonegotiation. */
1678 if (status & IPG_IS_LINK_EVENT) {
1679 if (ipg_config_autoneg(dev) < 0)
1680 printk(KERN_INFO "%s: Auto-negotiation error.\n",
1684 /* If MACCtrlFrame interrupt, do nothing. */
1685 if (status & IPG_IS_MAC_CTRL_FRAME)
1686 IPG_DEBUG_MSG("MACCtrlFrame interrupt.\n");
1688 /* If RxComplete interrupt, do nothing. */
1689 if (status & IPG_IS_RX_COMPLETE)
1690 IPG_DEBUG_MSG("RxComplete interrupt.\n");
1692 /* If RxEarly interrupt, do nothing. */
1693 if (status & IPG_IS_RX_EARLY)
1694 IPG_DEBUG_MSG("RxEarly interrupt.\n");
1697 /* Re-enable IPG interrupts. */
1698 ipg_w16(IPG_IE_TX_DMA_COMPLETE | IPG_IE_RX_DMA_COMPLETE |
1699 IPG_IE_HOST_ERROR | IPG_IE_INT_REQUESTED | IPG_IE_TX_COMPLETE |
1700 IPG_IE_LINK_EVENT | IPG_IE_UPDATE_STATS, INT_ENABLE);
1702 spin_unlock(&sp->lock);
1704 return IRQ_RETVAL(handled);
1707 static void ipg_rx_clear(struct ipg_nic_private *sp)
1711 for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
1712 if (sp->rx_buff[i]) {
1713 struct ipg_rx *rxfd = sp->rxd + i;
1715 dev_kfree_skb_irq(sp->rx_buff[i]);
1716 sp->rx_buff[i] = NULL;
1717 pci_unmap_single(sp->pdev,
1718 le64_to_cpu(rxfd->frag_info) & ~IPG_RFI_FRAGLEN,
1719 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1724 static void ipg_tx_clear(struct ipg_nic_private *sp)
1728 for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
1729 if (sp->tx_buff[i]) {
1730 struct ipg_tx *txfd = sp->txd + i;
1732 pci_unmap_single(sp->pdev,
1733 le64_to_cpu(txfd->frag_info) & ~IPG_TFI_FRAGLEN,
1734 sp->tx_buff[i]->len, PCI_DMA_TODEVICE);
1736 dev_kfree_skb_irq(sp->tx_buff[i]);
1738 sp->tx_buff[i] = NULL;
1743 static int ipg_nic_open(struct net_device *dev)
1745 struct ipg_nic_private *sp = netdev_priv(dev);
1746 void __iomem *ioaddr = sp->ioaddr;
1747 struct pci_dev *pdev = sp->pdev;
1750 IPG_DEBUG_MSG("_nic_open\n");
1752 sp->rx_buf_sz = IPG_RXSUPPORT_SIZE;
1754 /* Check for interrupt line conflicts, and request interrupt
1757 * IMPORTANT: Disable IPG interrupts prior to registering
1760 ipg_w16(0x0000, INT_ENABLE);
1762 /* Register the interrupt line to be used by the IPG within
1765 rc = request_irq(pdev->irq, &ipg_interrupt_handler, IRQF_SHARED,
1768 printk(KERN_INFO "%s: Error when requesting interrupt.\n",
1773 dev->irq = pdev->irq;
1777 sp->rxd = dma_alloc_coherent(&pdev->dev, IPG_RX_RING_BYTES,
1778 &sp->rxd_map, GFP_KERNEL);
1780 goto err_free_irq_0;
1782 sp->txd = dma_alloc_coherent(&pdev->dev, IPG_TX_RING_BYTES,
1783 &sp->txd_map, GFP_KERNEL);
1787 rc = init_rfdlist(dev);
1789 printk(KERN_INFO "%s: Error during configuration.\n",
1796 rc = ipg_io_config(dev);
1798 printk(KERN_INFO "%s: Error during configuration.\n",
1800 goto err_release_tfdlist_3;
1803 /* Resolve autonegotiation. */
1804 if (ipg_config_autoneg(dev) < 0)
1805 printk(KERN_INFO "%s: Auto-negotiation error.\n", dev->name);
1808 /* initialize JUMBO Frame control variable */
1809 sp->jumbo.found_start = 0;
1810 sp->jumbo.current_size = 0;
1811 sp->jumbo.skb = NULL;
1812 dev->mtu = IPG_TXFRAG_SIZE;
1815 /* Enable transmit and receive operation of the IPG. */
1816 ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_RX_ENABLE | IPG_MC_TX_ENABLE) &
1817 IPG_MC_RSVD_MASK, MAC_CTRL);
1819 netif_start_queue(dev);
1823 err_release_tfdlist_3:
1827 dma_free_coherent(&pdev->dev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1829 dma_free_coherent(&pdev->dev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1831 free_irq(pdev->irq, dev);
1835 static int ipg_nic_stop(struct net_device *dev)
1837 struct ipg_nic_private *sp = netdev_priv(dev);
1838 void __iomem *ioaddr = sp->ioaddr;
1839 struct pci_dev *pdev = sp->pdev;
1841 IPG_DEBUG_MSG("_nic_stop\n");
1843 netif_stop_queue(dev);
1845 IPG_DDEBUG_MSG("RFDlistendCount = %i\n", sp->RFDlistendCount);
1846 IPG_DDEBUG_MSG("RFDListCheckedCount = %i\n", sp->rxdCheckedCount);
1847 IPG_DDEBUG_MSG("EmptyRFDListCount = %i\n", sp->EmptyRFDListCount);
1848 IPG_DUMPTFDLIST(dev);
1851 (void) ipg_r16(INT_STATUS_ACK);
1853 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1855 synchronize_irq(pdev->irq);
1856 } while (ipg_r16(INT_ENABLE) & IPG_IE_RSVD_MASK);
1862 pci_free_consistent(pdev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1863 pci_free_consistent(pdev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1865 free_irq(pdev->irq, dev);
1870 static int ipg_nic_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1872 struct ipg_nic_private *sp = netdev_priv(dev);
1873 void __iomem *ioaddr = sp->ioaddr;
1874 unsigned int entry = sp->tx_current % IPG_TFDLIST_LENGTH;
1875 unsigned long flags;
1876 struct ipg_tx *txfd;
1878 IPG_DDEBUG_MSG("_nic_hard_start_xmit\n");
1880 /* If in 10Mbps mode, stop the transmit queue so
1881 * no more transmit frames are accepted.
1883 if (sp->tenmbpsmode)
1884 netif_stop_queue(dev);
1886 if (sp->reset_current_tfd) {
1887 sp->reset_current_tfd = 0;
1891 txfd = sp->txd + entry;
1893 sp->tx_buff[entry] = skb;
1895 /* Clear all TFC fields, except TFDDONE. */
1896 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
1898 /* Specify the TFC field within the TFD. */
1899 txfd->tfc |= cpu_to_le64(IPG_TFC_WORDALIGNDISABLED |
1900 (IPG_TFC_FRAMEID & sp->tx_current) |
1901 (IPG_TFC_FRAGCOUNT & (1 << 24)));
1903 * 16--17 (WordAlign) <- 3 (disable),
1904 * 0--15 (FrameId) <- sp->tx_current,
1905 * 24--27 (FragCount) <- 1
1908 /* Request TxComplete interrupts at an interval defined
1909 * by the constant IPG_FRAMESBETWEENTXCOMPLETES.
1910 * Request TxComplete interrupt for every frame
1911 * if in 10Mbps mode to accomodate problem with 10Mbps
1914 if (sp->tenmbpsmode)
1915 txfd->tfc |= cpu_to_le64(IPG_TFC_TXINDICATE);
1916 txfd->tfc |= cpu_to_le64(IPG_TFC_TXDMAINDICATE);
1917 /* Based on compilation option, determine if FCS is to be
1918 * appended to transmit frame by IPG.
1920 if (!(IPG_APPEND_FCS_ON_TX))
1921 txfd->tfc |= cpu_to_le64(IPG_TFC_FCSAPPENDDISABLE);
1923 /* Based on compilation option, determine if IP, TCP and/or
1924 * UDP checksums are to be added to transmit frame by IPG.
1926 if (IPG_ADD_IPCHECKSUM_ON_TX)
1927 txfd->tfc |= cpu_to_le64(IPG_TFC_IPCHECKSUMENABLE);
1929 if (IPG_ADD_TCPCHECKSUM_ON_TX)
1930 txfd->tfc |= cpu_to_le64(IPG_TFC_TCPCHECKSUMENABLE);
1932 if (IPG_ADD_UDPCHECKSUM_ON_TX)
1933 txfd->tfc |= cpu_to_le64(IPG_TFC_UDPCHECKSUMENABLE);
1935 /* Based on compilation option, determine if VLAN tag info is to be
1936 * inserted into transmit frame by IPG.
1938 if (IPG_INSERT_MANUAL_VLAN_TAG) {
1939 txfd->tfc |= cpu_to_le64(IPG_TFC_VLANTAGINSERT |
1940 ((u64) IPG_MANUAL_VLAN_VID << 32) |
1941 ((u64) IPG_MANUAL_VLAN_CFI << 44) |
1942 ((u64) IPG_MANUAL_VLAN_USERPRIORITY << 45));
1945 /* The fragment start location within system memory is defined
1946 * by the sk_buff structure's data field. The physical address
1947 * of this location within the system's virtual memory space
1948 * is determined using the IPG_HOST2BUS_MAP function.
1950 txfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
1951 skb->len, PCI_DMA_TODEVICE));
1953 /* The length of the fragment within system memory is defined by
1954 * the sk_buff structure's len field.
1956 txfd->frag_info |= cpu_to_le64(IPG_TFI_FRAGLEN &
1957 ((u64) (skb->len & 0xffff) << 48));
1959 /* Clear the TFDDone bit last to indicate the TFD is ready
1960 * for transfer to the IPG.
1962 txfd->tfc &= cpu_to_le64(~IPG_TFC_TFDDONE);
1964 spin_lock_irqsave(&sp->lock, flags);
1970 ipg_w32(IPG_DC_TX_DMA_POLL_NOW, DMA_CTRL);
1972 if (sp->tx_current == (sp->tx_dirty + IPG_TFDLIST_LENGTH))
1973 netif_stop_queue(dev);
1975 spin_unlock_irqrestore(&sp->lock, flags);
1977 return NETDEV_TX_OK;
1980 static void ipg_set_phy_default_param(unsigned char rev,
1981 struct net_device *dev, int phy_address)
1983 unsigned short length;
1984 unsigned char revision;
1985 unsigned short *phy_param;
1986 unsigned short address, value;
1988 phy_param = &DefaultPhyParam[0];
1989 length = *phy_param & 0x00FF;
1990 revision = (unsigned char)((*phy_param) >> 8);
1992 while (length != 0) {
1993 if (rev == revision) {
1994 while (length > 1) {
1995 address = *phy_param;
1996 value = *(phy_param + 1);
1998 mdio_write(dev, phy_address, address, value);
2003 phy_param += length / 2;
2004 length = *phy_param & 0x00FF;
2005 revision = (unsigned char)((*phy_param) >> 8);
2011 static int read_eeprom(struct net_device *dev, int eep_addr)
2013 void __iomem *ioaddr = ipg_ioaddr(dev);
2018 value = IPG_EC_EEPROM_READOPCODE | (eep_addr & 0xff);
2019 ipg_w16(value, EEPROM_CTRL);
2021 for (i = 0; i < 1000; i++) {
2025 data = ipg_r16(EEPROM_CTRL);
2026 if (!(data & IPG_EC_EEPROM_BUSY)) {
2027 ret = ipg_r16(EEPROM_DATA);
2034 static void ipg_init_mii(struct net_device *dev)
2036 struct ipg_nic_private *sp = netdev_priv(dev);
2037 struct mii_if_info *mii_if = &sp->mii_if;
2041 mii_if->mdio_read = mdio_read;
2042 mii_if->mdio_write = mdio_write;
2043 mii_if->phy_id_mask = 0x1f;
2044 mii_if->reg_num_mask = 0x1f;
2046 mii_if->phy_id = phyaddr = ipg_find_phyaddr(dev);
2048 if (phyaddr != 0x1f) {
2049 u16 mii_phyctrl, mii_1000cr;
2052 mii_1000cr = mdio_read(dev, phyaddr, MII_CTRL1000);
2053 mii_1000cr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF |
2054 GMII_PHY_1000BASETCONTROL_PreferMaster;
2055 mdio_write(dev, phyaddr, MII_CTRL1000, mii_1000cr);
2057 mii_phyctrl = mdio_read(dev, phyaddr, MII_BMCR);
2059 /* Set default phyparam */
2060 pci_read_config_byte(sp->pdev, PCI_REVISION_ID, &revisionid);
2061 ipg_set_phy_default_param(revisionid, dev, phyaddr);
2064 mii_phyctrl |= BMCR_RESET | BMCR_ANRESTART;
2065 mdio_write(dev, phyaddr, MII_BMCR, mii_phyctrl);
2070 static int ipg_hw_init(struct net_device *dev)
2072 struct ipg_nic_private *sp = netdev_priv(dev);
2073 void __iomem *ioaddr = sp->ioaddr;
2077 /* Read/Write and Reset EEPROM Value */
2078 /* Read LED Mode Configuration from EEPROM */
2079 sp->led_mode = read_eeprom(dev, 6);
2081 /* Reset all functions within the IPG. Do not assert
2082 * RST_OUT as not compatible with some PHYs.
2084 rc = ipg_reset(dev, IPG_RESET_MASK);
2090 /* Read MAC Address from EEPROM */
2091 for (i = 0; i < 3; i++)
2092 sp->station_addr[i] = read_eeprom(dev, 16 + i);
2094 for (i = 0; i < 3; i++)
2095 ipg_w16(sp->station_addr[i], STATION_ADDRESS_0 + 2*i);
2097 /* Set station address in ethernet_device structure. */
2098 dev->dev_addr[0] = ipg_r16(STATION_ADDRESS_0) & 0x00ff;
2099 dev->dev_addr[1] = (ipg_r16(STATION_ADDRESS_0) & 0xff00) >> 8;
2100 dev->dev_addr[2] = ipg_r16(STATION_ADDRESS_1) & 0x00ff;
2101 dev->dev_addr[3] = (ipg_r16(STATION_ADDRESS_1) & 0xff00) >> 8;
2102 dev->dev_addr[4] = ipg_r16(STATION_ADDRESS_2) & 0x00ff;
2103 dev->dev_addr[5] = (ipg_r16(STATION_ADDRESS_2) & 0xff00) >> 8;
2108 static int ipg_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2110 struct ipg_nic_private *sp = netdev_priv(dev);
2113 mutex_lock(&sp->mii_mutex);
2114 rc = generic_mii_ioctl(&sp->mii_if, if_mii(ifr), cmd, NULL);
2115 mutex_unlock(&sp->mii_mutex);
2120 static int ipg_nic_change_mtu(struct net_device *dev, int new_mtu)
2122 /* Function to accomodate changes to Maximum Transfer Unit
2123 * (or MTU) of IPG NIC. Cannot use default function since
2124 * the default will not allow for MTU > 1500 bytes.
2127 IPG_DEBUG_MSG("_nic_change_mtu\n");
2129 /* Check that the new MTU value is between 68 (14 byte header, 46
2130 * byte payload, 4 byte FCS) and IPG_MAX_RXFRAME_SIZE, which
2131 * corresponds to the MAXFRAMESIZE register in the IPG.
2133 if ((new_mtu < 68) || (new_mtu > IPG_MAX_RXFRAME_SIZE))
2141 static int ipg_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2143 struct ipg_nic_private *sp = netdev_priv(dev);
2146 mutex_lock(&sp->mii_mutex);
2147 rc = mii_ethtool_gset(&sp->mii_if, cmd);
2148 mutex_unlock(&sp->mii_mutex);
2153 static int ipg_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2155 struct ipg_nic_private *sp = netdev_priv(dev);
2158 mutex_lock(&sp->mii_mutex);
2159 rc = mii_ethtool_sset(&sp->mii_if, cmd);
2160 mutex_unlock(&sp->mii_mutex);
2165 static int ipg_nway_reset(struct net_device *dev)
2167 struct ipg_nic_private *sp = netdev_priv(dev);
2170 mutex_lock(&sp->mii_mutex);
2171 rc = mii_nway_restart(&sp->mii_if);
2172 mutex_unlock(&sp->mii_mutex);
2177 static struct ethtool_ops ipg_ethtool_ops = {
2178 .get_settings = ipg_get_settings,
2179 .set_settings = ipg_set_settings,
2180 .nway_reset = ipg_nway_reset,
2183 static void __devexit ipg_remove(struct pci_dev *pdev)
2185 struct net_device *dev = pci_get_drvdata(pdev);
2186 struct ipg_nic_private *sp = netdev_priv(dev);
2188 IPG_DEBUG_MSG("_remove\n");
2190 /* Un-register Ethernet device. */
2191 unregister_netdev(dev);
2193 pci_iounmap(pdev, sp->ioaddr);
2195 pci_release_regions(pdev);
2198 pci_disable_device(pdev);
2199 pci_set_drvdata(pdev, NULL);
2202 static int __devinit ipg_probe(struct pci_dev *pdev,
2203 const struct pci_device_id *id)
2205 unsigned int i = id->driver_data;
2206 struct ipg_nic_private *sp;
2207 struct net_device *dev;
2208 void __iomem *ioaddr;
2211 rc = pci_enable_device(pdev);
2215 printk(KERN_INFO "%s: %s\n", pci_name(pdev), ipg_brand_name[i]);
2217 pci_set_master(pdev);
2219 rc = pci_set_dma_mask(pdev, DMA_40BIT_MASK);
2221 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2223 printk(KERN_ERR "%s: DMA config failed.\n",
2230 * Initialize net device.
2232 dev = alloc_etherdev(sizeof(struct ipg_nic_private));
2234 printk(KERN_ERR "%s: alloc_etherdev failed\n", pci_name(pdev));
2239 sp = netdev_priv(dev);
2240 spin_lock_init(&sp->lock);
2241 mutex_init(&sp->mii_mutex);
2243 /* Declare IPG NIC functions for Ethernet device methods.
2245 dev->open = &ipg_nic_open;
2246 dev->stop = &ipg_nic_stop;
2247 dev->hard_start_xmit = &ipg_nic_hard_start_xmit;
2248 dev->get_stats = &ipg_nic_get_stats;
2249 dev->set_multicast_list = &ipg_nic_set_multicast_list;
2250 dev->do_ioctl = ipg_ioctl;
2251 dev->tx_timeout = ipg_tx_timeout;
2252 dev->change_mtu = &ipg_nic_change_mtu;
2254 SET_NETDEV_DEV(dev, &pdev->dev);
2255 SET_ETHTOOL_OPS(dev, &ipg_ethtool_ops);
2257 rc = pci_request_regions(pdev, DRV_NAME);
2259 goto err_free_dev_1;
2261 ioaddr = pci_iomap(pdev, 1, pci_resource_len(pdev, 1));
2263 printk(KERN_ERR "%s cannot map MMIO\n", pci_name(pdev));
2265 goto err_release_regions_2;
2268 /* Save the pointer to the PCI device information. */
2269 sp->ioaddr = ioaddr;
2273 INIT_DELAYED_WORK(&sp->task, ipg_reset_after_host_error);
2275 pci_set_drvdata(pdev, dev);
2277 rc = ipg_hw_init(dev);
2281 rc = register_netdev(dev);
2285 printk(KERN_INFO "Ethernet device registered as: %s\n", dev->name);
2290 pci_iounmap(pdev, ioaddr);
2291 err_release_regions_2:
2292 pci_release_regions(pdev);
2296 pci_disable_device(pdev);
2300 static struct pci_driver ipg_pci_driver = {
2301 .name = IPG_DRIVER_NAME,
2302 .id_table = ipg_pci_tbl,
2304 .remove = __devexit_p(ipg_remove),
2307 static int __init ipg_init_module(void)
2309 return pci_register_driver(&ipg_pci_driver);
2312 static void __exit ipg_exit_module(void)
2314 pci_unregister_driver(&ipg_pci_driver);
2317 module_init(ipg_init_module);
2318 module_exit(ipg_exit_module);