drivers/net/ipg.c

   1 /*
   2  * ipg.c: Device Driver for the IP1000 Gigabit Ethernet Adapter
   3  *
   4  * Copyright (C) 2003, 2007  IC Plus Corp
   5  *
   6  * Original Author:
   7  *
   8  *   Craig Rich
   9  *   Sundance Technology, Inc.
  10  *   www.sundanceti.com
  11  *   craig_rich@sundanceti.com
  12  *
  13  * Current Maintainer:
  14  *
  15  *   Sorbica Shieh.
  16  *   http://www.icplus.com.tw
  17  *   sorbica@icplus.com.tw
  18  *
  19  *   Jesse Huang
  20  *   http://www.icplus.com.tw
  21  *   jesse@icplus.com.tw
  22  */
  23 #include <linux/crc32.h>
  24 #include <linux/ethtool.h>
  25 #include <linux/mii.h>
  26 #include <linux/mutex.h>
  27
  28 #define IPG_RX_RING_BYTES       (sizeof(struct ipg_rx) * IPG_RFDLIST_LENGTH)
  29 #define IPG_TX_RING_BYTES       (sizeof(struct ipg_tx) * IPG_TFDLIST_LENGTH)
  30 #define IPG_RESET_MASK \
  31         (IPG_AC_GLOBAL_RESET | IPG_AC_RX_RESET | IPG_AC_TX_RESET | \
  32          IPG_AC_DMA | IPG_AC_FIFO | IPG_AC_NETWORK | IPG_AC_HOST | \
  33          IPG_AC_AUTO_INIT)
  34
  35 #define ipg_w32(val32,reg)      iowrite32((val32), ioaddr + (reg))
  36 #define ipg_w16(val16,reg)      iowrite16((val16), ioaddr + (reg))
  37 #define ipg_w8(val8,reg)        iowrite8((val8), ioaddr + (reg))
  38
  39 #define ipg_r32(reg)            ioread32(ioaddr + (reg))
  40 #define ipg_r16(reg)            ioread16(ioaddr + (reg))
  41 #define ipg_r8(reg)             ioread8(ioaddr + (reg))
  42
  43 #define JUMBO_FRAME_4k_ONLY
  44 enum {
  45         netdev_io_size = 128
  46 };
  47
  48 #include "ipg.h"
  49 #define DRV_NAME        "ipg"
  50
  51 MODULE_AUTHOR("IC Plus Corp. 2003");
  52 MODULE_DESCRIPTION("IC Plus IP1000 Gigabit Ethernet Adapter Linux Driver "
  53                    DrvVer);
  54 MODULE_LICENSE("GPL");
  55
  56 static const char *ipg_brand_name[] = {
  57         "IC PLUS IP1000 1000/100/10 based NIC",
  58         "Sundance Technology ST2021 based NIC",
  59         "Tamarack Microelectronics TC9020/9021 based NIC",
  60         "Tamarack Microelectronics TC9020/9021 based NIC",
  61         "D-Link NIC",
  62         "D-Link NIC IP1000A"
  63 };
  64
  65 static struct pci_device_id ipg_pci_tbl[] __devinitdata = {
  66         { PCI_VDEVICE(SUNDANCE, 0x1023), 0 },
  67         { PCI_VDEVICE(SUNDANCE, 0x2021), 1 },
  68         { PCI_VDEVICE(SUNDANCE, 0x1021), 2 },
  69         { PCI_VDEVICE(DLINK,    0x9021), 3 },
  70         { PCI_VDEVICE(DLINK,    0x4000), 4 },
  71         { PCI_VDEVICE(DLINK,    0x4020), 5 },
  72         { 0, }
  73 };
  74
  75 MODULE_DEVICE_TABLE(pci, ipg_pci_tbl);
  76
  77 static inline void __iomem *ipg_ioaddr(struct net_device *dev)
  78 {
  79         struct ipg_nic_private *sp = netdev_priv(dev);
  80         return sp->ioaddr;
  81 }
  82
  83 #ifdef IPG_DEBUG
  84 static void ipg_dump_rfdlist(struct net_device *dev)
  85 {
  86         struct ipg_nic_private *sp = netdev_priv(dev);
  87         void __iomem *ioaddr = sp->ioaddr;
  88         unsigned int i;
  89         u32 offset;
  90
  91         IPG_DEBUG_MSG("_dump_rfdlist\n");
  92
  93         printk(KERN_INFO "rx_current = %2.2x\n", sp->rx_current);
  94         printk(KERN_INFO "rx_dirty   = %2.2x\n", sp->rx_dirty);
  95         printk(KERN_INFO "RFDList start address = %16.16lx\n",
  96                (unsigned long) sp->rxd_map);
  97         printk(KERN_INFO "RFDListPtr register   = %8.8x%8.8x\n",
  98                ipg_r32(IPG_RFDLISTPTR1), ipg_r32(IPG_RFDLISTPTR0));
  99
 100         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
 101                 offset = (u32) &sp->rxd[i].next_desc - (u32) sp->rxd;
 102                 printk(KERN_INFO "%2.2x %4.4x RFDNextPtr = %16.16lx\n", i,
 103                        offset, (unsigned long) sp->rxd[i].next_desc);
 104                 offset = (u32) &sp->rxd[i].rfs - (u32) sp->rxd;
 105                 printk(KERN_INFO "%2.2x %4.4x RFS        = %16.16lx\n", i,
 106                        offset, (unsigned long) sp->rxd[i].rfs);
 107                 offset = (u32) &sp->rxd[i].frag_info - (u32) sp->rxd;
 108                 printk(KERN_INFO "%2.2x %4.4x frag_info   = %16.16lx\n", i,
 109                        offset, (unsigned long) sp->rxd[i].frag_info);
 110         }
 111 }
 112
 113 static void ipg_dump_tfdlist(struct net_device *dev)
 114 {
 115         struct ipg_nic_private *sp = netdev_priv(dev);
 116         void __iomem *ioaddr = sp->ioaddr;
 117         unsigned int i;
 118         u32 offset;
 119
 120         IPG_DEBUG_MSG("_dump_tfdlist\n");
 121
 122         printk(KERN_INFO "tx_current         = %2.2x\n", sp->tx_current);
 123         printk(KERN_INFO "tx_dirty = %2.2x\n", sp->tx_dirty);
 124         printk(KERN_INFO "TFDList start address = %16.16lx\n",
 125                (unsigned long) sp->txd_map);
 126         printk(KERN_INFO "TFDListPtr register   = %8.8x%8.8x\n",
 127                ipg_r32(IPG_TFDLISTPTR1), ipg_r32(IPG_TFDLISTPTR0));
 128
 129         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
 130                 offset = (u32) &sp->txd[i].next_desc - (u32) sp->txd;
 131                 printk(KERN_INFO "%2.2x %4.4x TFDNextPtr = %16.16lx\n", i,
 132                        offset, (unsigned long) sp->txd[i].next_desc);
 133
 134                 offset = (u32) &sp->txd[i].tfc - (u32) sp->txd;
 135                 printk(KERN_INFO "%2.2x %4.4x TFC        = %16.16lx\n", i,
 136                        offset, (unsigned long) sp->txd[i].tfc);
 137                 offset = (u32) &sp->txd[i].frag_info - (u32) sp->txd;
 138                 printk(KERN_INFO "%2.2x %4.4x frag_info   = %16.16lx\n", i,
 139                        offset, (unsigned long) sp->txd[i].frag_info);
 140         }
 141 }
 142 #endif
 143
 144 static void ipg_write_phy_ctl(void __iomem *ioaddr, u8 data)
 145 {
 146         ipg_w8(IPG_PC_RSVD_MASK & data, PHY_CTRL);
 147         ndelay(IPG_PC_PHYCTRLWAIT_NS);
 148 }
 149
 150 static void ipg_drive_phy_ctl_low_high(void __iomem *ioaddr, u8 data)
 151 {
 152         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | data);
 153         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | data);
 154 }
 155
 156 static void send_three_state(void __iomem *ioaddr, u8 phyctrlpolarity)
 157 {
 158         phyctrlpolarity |= (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR;
 159
 160         ipg_drive_phy_ctl_low_high(ioaddr, phyctrlpolarity);
 161 }
 162
 163 static void send_end(void __iomem *ioaddr, u8 phyctrlpolarity)
 164 {
 165         ipg_w8((IPG_PC_MGMTCLK_LO | (IPG_PC_MGMTDATA & 0) | IPG_PC_MGMTDIR |
 166                 phyctrlpolarity) & IPG_PC_RSVD_MASK, PHY_CTRL);
 167 }
 168
 169 static u16 read_phy_bit(void __iomem * ioaddr, u8 phyctrlpolarity)
 170 {
 171         u16 bit_data;
 172
 173         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | phyctrlpolarity);
 174
 175         bit_data = ((ipg_r8(PHY_CTRL) & IPG_PC_MGMTDATA) >> 1) & 1;
 176
 177         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | phyctrlpolarity);
 178
 179         return bit_data;
 180 }
 181
 182 /*
 183  * Read a register from the Physical Layer device located
 184  * on the IPG NIC, using the IPG PHYCTRL register.
 185  */
 186 static int mdio_read(struct net_device * dev, int phy_id, int phy_reg)
 187 {
 188         void __iomem *ioaddr = ipg_ioaddr(dev);
 189         /*
 190          * The GMII mangement frame structure for a read is as follows:
 191          *
 192          * |Preamble|st|op|phyad|regad|ta|      data      |idle|
 193          * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z   |
 194          *
 195          * <32 1s> = 32 consecutive logic 1 values
 196          * A = bit of Physical Layer device address (MSB first)
 197          * R = bit of register address (MSB first)
 198          * z = High impedance state
 199          * D = bit of read data (MSB first)
 200          *
 201          * Transmission order is 'Preamble' field first, bits transmitted
 202          * left to right (first to last).
 203          */
 204         struct {
 205                 u32 field;
 206                 unsigned int len;
 207         } p[] = {
 208                 { GMII_PREAMBLE,        32 },   /* Preamble */
 209                 { GMII_ST,              2  },   /* ST */
 210                 { GMII_READ,            2  },   /* OP */
 211                 { phy_id,               5  },   /* PHYAD */
 212                 { phy_reg,              5  },   /* REGAD */
 213                 { 0x0000,               2  },   /* TA */
 214                 { 0x0000,               16 },   /* DATA */
 215                 { 0x0000,               1  }    /* IDLE */
 216         };
 217         unsigned int i, j;
 218         u8 polarity, data;
 219
 220         polarity  = ipg_r8(PHY_CTRL);
 221         polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
 222
 223         /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
 224         for (j = 0; j < 5; j++) {
 225                 for (i = 0; i < p[j].len; i++) {
 226                         /* For each variable length field, the MSB must be
 227                          * transmitted first. Rotate through the field bits,
 228                          * starting with the MSB, and move each bit into the
 229                          * the 1st (2^1) bit position (this is the bit position
 230                          * corresponding to the MgmtData bit of the PhyCtrl
 231                          * register for the IPG).
 232                          *
 233                          * Example: ST = 01;
 234                          *
 235                          *          First write a '0' to bit 1 of the PhyCtrl
 236                          *          register, then write a '1' to bit 1 of the
 237                          *          PhyCtrl register.
 238                          *
 239                          * To do this, right shift the MSB of ST by the value:
 240                          * [field length - 1 - #ST bits already written]
 241                          * then left shift this result by 1.
 242                          */
 243                         data  = (p[j].field >> (p[j].len - 1 - i)) << 1;
 244                         data &= IPG_PC_MGMTDATA;
 245                         data |= polarity | IPG_PC_MGMTDIR;
 246
 247                         ipg_drive_phy_ctl_low_high(ioaddr, data);
 248                 }
 249         }
 250
 251         send_three_state(ioaddr, polarity);
 252
 253         read_phy_bit(ioaddr, polarity);
 254
 255         /*
 256          * For a read cycle, the bits for the next two fields (TA and
 257          * DATA) are driven by the PHY (the IPG reads these bits).
 258          */
 259         for (i = 0; i < p[6].len; i++) {
 260                 p[6].field |=
 261                     (read_phy_bit(ioaddr, polarity) << (p[6].len - 1 - i));
 262         }
 263
 264         send_three_state(ioaddr, polarity);
 265         send_three_state(ioaddr, polarity);
 266         send_three_state(ioaddr, polarity);
 267         send_end(ioaddr, polarity);
 268
 269         /* Return the value of the DATA field. */
 270         return p[6].field;
 271 }
 272
 273 /*
 274  * Write to a register from the Physical Layer device located
 275  * on the IPG NIC, using the IPG PHYCTRL register.
 276  */
 277 static void mdio_write(struct net_device *dev, int phy_id, int phy_reg, int val)
 278 {
 279         void __iomem *ioaddr = ipg_ioaddr(dev);
 280         /*
 281          * The GMII mangement frame structure for a read is as follows:
 282          *
 283          * |Preamble|st|op|phyad|regad|ta|      data      |idle|
 284          * |< 32 1s>|01|10|AAAAA|RRRRR|z0|DDDDDDDDDDDDDDDD|z   |
 285          *
 286          * <32 1s> = 32 consecutive logic 1 values
 287          * A = bit of Physical Layer device address (MSB first)
 288          * R = bit of register address (MSB first)
 289          * z = High impedance state
 290          * D = bit of write data (MSB first)
 291          *
 292          * Transmission order is 'Preamble' field first, bits transmitted
 293          * left to right (first to last).
 294          */
 295         struct {
 296                 u32 field;
 297                 unsigned int len;
 298         } p[] = {
 299                 { GMII_PREAMBLE,        32 },   /* Preamble */
 300                 { GMII_ST,              2  },   /* ST */
 301                 { GMII_WRITE,           2  },   /* OP */
 302                 { phy_id,               5  },   /* PHYAD */
 303                 { phy_reg,              5  },   /* REGAD */
 304                 { 0x0002,               2  },   /* TA */
 305                 { val & 0xffff,         16 },   /* DATA */
 306                 { 0x0000,               1  }    /* IDLE */
 307         };
 308         unsigned int i, j;
 309         u8 polarity, data;
 310
 311         polarity  = ipg_r8(PHY_CTRL);
 312         polarity &= (IPG_PC_DUPLEX_POLARITY | IPG_PC_LINK_POLARITY);
 313
 314         /* Create the Preamble, ST, OP, PHYAD, and REGAD field. */
 315         for (j = 0; j < 7; j++) {
 316                 for (i = 0; i < p[j].len; i++) {
 317                         /* For each variable length field, the MSB must be
 318                          * transmitted first. Rotate through the field bits,
 319                          * starting with the MSB, and move each bit into the
 320                          * the 1st (2^1) bit position (this is the bit position
 321                          * corresponding to the MgmtData bit of the PhyCtrl
 322                          * register for the IPG).
 323                          *
 324                          * Example: ST = 01;
 325                          *
 326                          *          First write a '0' to bit 1 of the PhyCtrl
 327                          *          register, then write a '1' to bit 1 of the
 328                          *          PhyCtrl register.
 329                          *
 330                          * To do this, right shift the MSB of ST by the value:
 331                          * [field length - 1 - #ST bits already written]
 332                          * then left shift this result by 1.
 333                          */
 334                         data  = (p[j].field >> (p[j].len - 1 - i)) << 1;
 335                         data &= IPG_PC_MGMTDATA;
 336                         data |= polarity | IPG_PC_MGMTDIR;
 337
 338                         ipg_drive_phy_ctl_low_high(ioaddr, data);
 339                 }
 340         }
 341
 342         /* The last cycle is a tri-state, so read from the PHY. */
 343         for (j = 7; j < 8; j++) {
 344                 for (i = 0; i < p[j].len; i++) {
 345                         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_LO | polarity);
 346
 347                         p[j].field |= ((ipg_r8(PHY_CTRL) &
 348                                 IPG_PC_MGMTDATA) >> 1) << (p[j].len - 1 - i);
 349
 350                         ipg_write_phy_ctl(ioaddr, IPG_PC_MGMTCLK_HI | polarity);
 351                 }
 352         }
 353 }
 354
 355 /* Set LED_Mode JES20040127EEPROM */
 356 static void ipg_set_led_mode(struct net_device *dev)
 357 {
 358         struct ipg_nic_private *sp = netdev_priv(dev);
 359         void __iomem *ioaddr = sp->ioaddr;
 360         u32 mode;
 361
 362         mode = ipg_r32(ASIC_CTRL);
 363         mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
 364
 365         if ((sp->LED_Mode & 0x03) > 1)
 366                 mode |= IPG_AC_LED_MODE_BIT_1;  /* Write Asic Control Bit 29 */
 367
 368         if ((sp->LED_Mode & 0x01) == 1)
 369                 mode |= IPG_AC_LED_MODE;        /* Write Asic Control Bit 14 */
 370
 371         if ((sp->LED_Mode & 0x08) == 8)
 372                 mode |= IPG_AC_LED_SPEED;       /* Write Asic Control Bit 27 */
 373
 374         ipg_w32(mode, ASIC_CTRL);
 375 }
 376
 377 /* Set PHYSet JES20040127EEPROM */
 378 static void ipg_set_phy_set(struct net_device *dev)
 379 {
 380         struct ipg_nic_private *sp = netdev_priv(dev);
 381         void __iomem *ioaddr = sp->ioaddr;
 382         int physet;
 383
 384         physet = ipg_r8(PHY_SET);
 385         physet &= ~(IPG_PS_MEM_LENB9B | IPG_PS_MEM_LEN9 | IPG_PS_NON_COMPDET);
 386         physet |= ((sp->LED_Mode & 0x70) >> 4);
 387         ipg_w8(physet, PHY_SET);
 388 }
 389
 390 static int ipg_reset(struct net_device *dev, u32 resetflags)
 391 {
 392         /* Assert functional resets via the IPG AsicCtrl
 393          * register as specified by the 'resetflags' input
 394          * parameter.
 395          */
 396         void __iomem *ioaddr = ipg_ioaddr(dev); //JES20040127EEPROM:
 397         unsigned int timeout_count = 0;
 398
 399         IPG_DEBUG_MSG("_reset\n");
 400
 401         ipg_w32(ipg_r32(ASIC_CTRL) | resetflags, ASIC_CTRL);
 402
 403         /* Delay added to account for problem with 10Mbps reset. */
 404         mdelay(IPG_AC_RESETWAIT);
 405
 406         while (IPG_AC_RESET_BUSY & ipg_r32(ASIC_CTRL)) {
 407                 mdelay(IPG_AC_RESETWAIT);
 408                 if (++timeout_count > IPG_AC_RESET_TIMEOUT)
 409                         return -ETIME;
 410         }
 411         /* Set LED Mode in Asic Control JES20040127EEPROM */
 412         ipg_set_led_mode(dev);
 413
 414         /* Set PHYSet Register Value JES20040127EEPROM */
 415         ipg_set_phy_set(dev);
 416         return 0;
 417 }
 418
 419 /* Find the GMII PHY address. */
 420 static int ipg_find_phyaddr(struct net_device *dev)
 421 {
 422         unsigned int phyaddr, i;
 423
 424         for (i = 0; i < 32; i++) {
 425                 u32 status;
 426
 427                 /* Search for the correct PHY address among 32 possible. */
 428                 phyaddr = (IPG_NIC_PHY_ADDRESS + i) % 32;
 429
 430                 /* 10/22/03 Grace change verify from GMII_PHY_STATUS to
 431                    GMII_PHY_ID1
 432                  */
 433
 434                 status = mdio_read(dev, phyaddr, MII_BMSR);
 435
 436                 if ((status != 0xFFFF) && (status != 0))
 437                         return phyaddr;
 438         }
 439
 440         return 0x1f;
 441 }
 442
 443 /*
 444  * Configure IPG based on result of IEEE 802.3 PHY
 445  * auto-negotiation.
 446  */
 447 static int ipg_config_autoneg(struct net_device *dev)
 448 {
 449         struct ipg_nic_private *sp = netdev_priv(dev);
 450         void __iomem *ioaddr = sp->ioaddr;
 451         unsigned int txflowcontrol;
 452         unsigned int rxflowcontrol;
 453         unsigned int fullduplex;
 454         unsigned int gig;
 455         u32 mac_ctrl_val;
 456         u32 asicctrl;
 457         u8 phyctrl;
 458
 459         IPG_DEBUG_MSG("_config_autoneg\n");
 460
 461         asicctrl = ipg_r32(ASIC_CTRL);
 462         phyctrl = ipg_r8(PHY_CTRL);
 463         mac_ctrl_val = ipg_r32(MAC_CTRL);
 464
 465         /* Set flags for use in resolving auto-negotation, assuming
 466          * non-1000Mbps, half duplex, no flow control.
 467          */
 468         fullduplex = 0;
 469         txflowcontrol = 0;
 470         rxflowcontrol = 0;
 471         gig = 0;
 472
 473         /* To accomodate a problem in 10Mbps operation,
 474          * set a global flag if PHY running in 10Mbps mode.
 475          */
 476         sp->tenmbpsmode = 0;
 477
 478         printk(KERN_INFO "%s: Link speed = ", dev->name);
 479
 480         /* Determine actual speed of operation. */
 481         switch (phyctrl & IPG_PC_LINK_SPEED) {
 482         case IPG_PC_LINK_SPEED_10MBPS:
 483                 printk("10Mbps.\n");
 484                 printk(KERN_INFO "%s: 10Mbps operational mode enabled.\n",
 485                        dev->name);
 486                 sp->tenmbpsmode = 1;
 487                 break;
 488         case IPG_PC_LINK_SPEED_100MBPS:
 489                 printk("100Mbps.\n");
 490                 break;
 491         case IPG_PC_LINK_SPEED_1000MBPS:
 492                 printk("1000Mbps.\n");
 493                 gig = 1;
 494                 break;
 495         default:
 496                 printk("undefined!\n");
 497                 return 0;
 498         }
 499
 500         if (phyctrl & IPG_PC_DUPLEX_STATUS) {
 501                 fullduplex = 1;
 502                 txflowcontrol = 1;
 503                 rxflowcontrol = 1;
 504         }
 505
 506         /* Configure full duplex, and flow control. */
 507         if (fullduplex == 1) {
 508                 /* Configure IPG for full duplex operation. */
 509                 printk(KERN_INFO "%s: setting full duplex, ", dev->name);
 510
 511                 mac_ctrl_val |= IPG_MC_DUPLEX_SELECT_FD;
 512
 513                 if (txflowcontrol == 1) {
 514                         printk("TX flow control");
 515                         mac_ctrl_val |= IPG_MC_TX_FLOW_CONTROL_ENABLE;
 516                 } else {
 517                         printk("no TX flow control");
 518                         mac_ctrl_val &= ~IPG_MC_TX_FLOW_CONTROL_ENABLE;
 519                 }
 520
 521                 if (rxflowcontrol == 1) {
 522                         printk(", RX flow control.");
 523                         mac_ctrl_val |= IPG_MC_RX_FLOW_CONTROL_ENABLE;
 524                 } else {
 525                         printk(", no RX flow control.");
 526                         mac_ctrl_val &= ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
 527                 }
 528
 529                 printk("\n");
 530         } else {
 531                 /* Configure IPG for half duplex operation. */
 532                 printk(KERN_INFO "%s: setting half duplex, "
 533                        "no TX flow control, no RX flow control.\n", dev->name);
 534
 535                 mac_ctrl_val &= ~IPG_MC_DUPLEX_SELECT_FD &
 536                         ~IPG_MC_TX_FLOW_CONTROL_ENABLE &
 537                         ~IPG_MC_RX_FLOW_CONTROL_ENABLE;
 538         }
 539         ipg_w32(mac_ctrl_val, MAC_CTRL);
 540         return 0;
 541 }
 542
 543 /* Determine and configure multicast operation and set
 544  * receive mode for IPG.
 545  */
 546 static void ipg_nic_set_multicast_list(struct net_device *dev)
 547 {
 548         void __iomem *ioaddr = ipg_ioaddr(dev);
 549         struct dev_mc_list *mc_list_ptr;
 550         unsigned int hashindex;
 551         u32 hashtable[2];
 552         u8 receivemode;
 553
 554         IPG_DEBUG_MSG("_nic_set_multicast_list\n");
 555
 556         receivemode = IPG_RM_RECEIVEUNICAST | IPG_RM_RECEIVEBROADCAST;
 557
 558         if (dev->flags & IFF_PROMISC) {
 559                 /* NIC to be configured in promiscuous mode. */
 560                 receivemode = IPG_RM_RECEIVEALLFRAMES;
 561         } else if ((dev->flags & IFF_ALLMULTI) ||
 562                    (dev->flags & IFF_MULTICAST &
 563                     (dev->mc_count > IPG_MULTICAST_HASHTABLE_SIZE))) {
 564                 /* NIC to be configured to receive all multicast
 565                  * frames. */
 566                 receivemode |= IPG_RM_RECEIVEMULTICAST;
 567         } else if (dev->flags & IFF_MULTICAST & (dev->mc_count > 0)) {
 568                 /* NIC to be configured to receive selected
 569                  * multicast addresses. */
 570                 receivemode |= IPG_RM_RECEIVEMULTICASTHASH;
 571         }
 572
 573         /* Calculate the bits to set for the 64 bit, IPG HASHTABLE.
 574          * The IPG applies a cyclic-redundancy-check (the same CRC
 575          * used to calculate the frame data FCS) to the destination
 576          * address all incoming multicast frames whose destination
 577          * address has the multicast bit set. The least significant
 578          * 6 bits of the CRC result are used as an addressing index
 579          * into the hash table. If the value of the bit addressed by
 580          * this index is a 1, the frame is passed to the host system.
 581          */
 582
 583         /* Clear hashtable. */
 584         hashtable[0] = 0x00000000;
 585         hashtable[1] = 0x00000000;
 586
 587         /* Cycle through all multicast addresses to filter. */
 588         for (mc_list_ptr = dev->mc_list;
 589              mc_list_ptr != NULL; mc_list_ptr = mc_list_ptr->next) {
 590                 /* Calculate CRC result for each multicast address. */
 591                 hashindex = crc32_le(0xffffffff, mc_list_ptr->dmi_addr,
 592                                      ETH_ALEN);
 593
 594                 /* Use only the least significant 6 bits. */
 595                 hashindex = hashindex & 0x3F;
 596
 597                 /* Within "hashtable", set bit number "hashindex"
 598                  * to a logic 1.
 599                  */
 600                 set_bit(hashindex, (void *)hashtable);
 601         }
 602
 603         /* Write the value of the hashtable, to the 4, 16 bit
 604          * HASHTABLE IPG registers.
 605          */
 606         ipg_w32(hashtable[0], HASHTABLE_0);
 607         ipg_w32(hashtable[1], HASHTABLE_1);
 608
 609         ipg_w8(IPG_RM_RSVD_MASK & receivemode, RECEIVE_MODE);
 610
 611         IPG_DEBUG_MSG("ReceiveMode = %x\n", ipg_r8(RECEIVE_MODE));
 612 }
 613
 614 static int ipg_io_config(struct net_device *dev)
 615 {
 616         void __iomem *ioaddr = ipg_ioaddr(dev);
 617         u32 origmacctrl;
 618         u32 restoremacctrl;
 619
 620         IPG_DEBUG_MSG("_io_config\n");
 621
 622         origmacctrl = ipg_r32(MAC_CTRL);
 623
 624         restoremacctrl = origmacctrl | IPG_MC_STATISTICS_ENABLE;
 625
 626         /* Based on compilation option, determine if FCS is to be
 627          * stripped on receive frames by IPG.
 628          */
 629         if (!IPG_STRIP_FCS_ON_RX)
 630                 restoremacctrl |= IPG_MC_RCV_FCS;
 631
 632         /* Determine if transmitter and/or receiver are
 633          * enabled so we may restore MACCTRL correctly.
 634          */
 635         if (origmacctrl & IPG_MC_TX_ENABLED)
 636                 restoremacctrl |= IPG_MC_TX_ENABLE;
 637
 638         if (origmacctrl & IPG_MC_RX_ENABLED)
 639                 restoremacctrl |= IPG_MC_RX_ENABLE;
 640
 641         /* Transmitter and receiver must be disabled before setting
 642          * IFSSelect.
 643          */
 644         ipg_w32((origmacctrl & (IPG_MC_RX_DISABLE | IPG_MC_TX_DISABLE)) &
 645                 IPG_MC_RSVD_MASK, MAC_CTRL);
 646
 647         /* Now that transmitter and receiver are disabled, write
 648          * to IFSSelect.
 649          */
 650         ipg_w32((origmacctrl & IPG_MC_IFS_96BIT) & IPG_MC_RSVD_MASK, MAC_CTRL);
 651
 652         /* Set RECEIVEMODE register. */
 653         ipg_nic_set_multicast_list(dev);
 654
 655         ipg_w16(IPG_MAX_RXFRAME_SIZE, MAX_FRAME_SIZE);
 656
 657         ipg_w8(IPG_RXDMAPOLLPERIOD_VALUE,   RX_DMA_POLL_PERIOD);
 658         ipg_w8(IPG_RXDMAURGENTTHRESH_VALUE, RX_DMA_URGENT_THRESH);
 659         ipg_w8(IPG_RXDMABURSTTHRESH_VALUE,  RX_DMA_BURST_THRESH);
 660         ipg_w8(IPG_TXDMAPOLLPERIOD_VALUE,   TX_DMA_POLL_PERIOD);
 661         ipg_w8(IPG_TXDMAURGENTTHRESH_VALUE, TX_DMA_URGENT_THRESH);
 662         ipg_w8(IPG_TXDMABURSTTHRESH_VALUE,  TX_DMA_BURST_THRESH);
 663         ipg_w16((IPG_IE_HOST_ERROR | IPG_IE_TX_DMA_COMPLETE |
 664                  IPG_IE_TX_COMPLETE | IPG_IE_INT_REQUESTED |
 665                  IPG_IE_UPDATE_STATS | IPG_IE_LINK_EVENT |
 666                  IPG_IE_RX_DMA_COMPLETE | IPG_IE_RX_DMA_PRIORITY), INT_ENABLE);
 667         ipg_w16(IPG_FLOWONTHRESH_VALUE,  FLOW_ON_THRESH);
 668         ipg_w16(IPG_FLOWOFFTHRESH_VALUE, FLOW_OFF_THRESH);
 669
 670         /* IPG multi-frag frame bug workaround.
 671          * Per silicon revision B3 eratta.
 672          */
 673         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0200, DEBUG_CTRL);
 674
 675         /* IPG TX poll now bug workaround.
 676          * Per silicon revision B3 eratta.
 677          */
 678         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0010, DEBUG_CTRL);
 679
 680         /* IPG RX poll now bug workaround.
 681          * Per silicon revision B3 eratta.
 682          */
 683         ipg_w16(ipg_r16(DEBUG_CTRL) | 0x0020, DEBUG_CTRL);
 684
 685         /* Now restore MACCTRL to original setting. */
 686         ipg_w32(IPG_MC_RSVD_MASK & restoremacctrl, MAC_CTRL);
 687
 688         /* Disable unused RMON statistics. */
 689         ipg_w32(IPG_RZ_ALL, RMON_STATISTICS_MASK);
 690
 691         /* Disable unused MIB statistics. */
 692         ipg_w32(IPG_SM_MACCONTROLFRAMESXMTD | IPG_SM_MACCONTROLFRAMESRCVD |
 693                 IPG_SM_BCSTOCTETXMTOK_BCSTFRAMESXMTDOK | IPG_SM_TXJUMBOFRAMES |
 694                 IPG_SM_MCSTOCTETXMTOK_MCSTFRAMESXMTDOK | IPG_SM_RXJUMBOFRAMES |
 695                 IPG_SM_BCSTOCTETRCVDOK_BCSTFRAMESRCVDOK |
 696                 IPG_SM_UDPCHECKSUMERRORS | IPG_SM_TCPCHECKSUMERRORS |
 697                 IPG_SM_IPCHECKSUMERRORS, STATISTICS_MASK);
 698
 699         return 0;
 700 }
 701
 702 /*
 703  * Create a receive buffer within system memory and update
 704  * NIC private structure appropriately.
 705  */
 706 static int ipg_get_rxbuff(struct net_device *dev, int entry)
 707 {
 708         struct ipg_nic_private *sp = netdev_priv(dev);
 709         struct ipg_rx *rxfd = sp->rxd + entry;
 710         struct sk_buff *skb;
 711         u64 rxfragsize;
 712
 713         IPG_DEBUG_MSG("_get_rxbuff\n");
 714
 715         skb = netdev_alloc_skb(dev, IPG_RXSUPPORT_SIZE + NET_IP_ALIGN);
 716         if (!skb) {
 717                 sp->RxBuff[entry] = NULL;
 718                 return -ENOMEM;
 719         }
 720
 721         /* Adjust the data start location within the buffer to
 722          * align IP address field to a 16 byte boundary.
 723          */
 724         skb_reserve(skb, NET_IP_ALIGN);
 725
 726         /* Associate the receive buffer with the IPG NIC. */
 727         skb->dev = dev;
 728
 729         /* Save the address of the sk_buff structure. */
 730         sp->RxBuff[entry] = skb;
 731
 732         rxfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
 733                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE));
 734
 735         /* Set the RFD fragment length. */
 736         rxfragsize = IPG_RXFRAG_SIZE;
 737         rxfd->frag_info |= cpu_to_le64((rxfragsize << 48) & IPG_RFI_FRAGLEN);
 738
 739         return 0;
 740 }
 741
 742 static int init_rfdlist(struct net_device *dev)
 743 {
 744         struct ipg_nic_private *sp = netdev_priv(dev);
 745         void __iomem *ioaddr = sp->ioaddr;
 746         unsigned int i;
 747
 748         IPG_DEBUG_MSG("_init_rfdlist\n");
 749
 750         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
 751                 struct ipg_rx *rxfd = sp->rxd + i;
 752
 753                 if (sp->RxBuff[i]) {
 754                         pci_unmap_single(sp->pdev,
 755                                 le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
 756                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
 757                         IPG_DEV_KFREE_SKB(sp->RxBuff[i]);
 758                         sp->RxBuff[i] = NULL;
 759                 }
 760
 761                 /* Clear out the RFS field. */
 762                 rxfd->rfs = 0x0000000000000000;
 763
 764                 if (ipg_get_rxbuff(dev, i) < 0) {
 765                         /*
 766                          * A receive buffer was not ready, break the
 767                          * RFD list here.
 768                          */
 769                         IPG_DEBUG_MSG("Cannot allocate Rx buffer.\n");
 770
 771                         /* Just in case we cannot allocate a single RFD.
 772                          * Should not occur.
 773                          */
 774                         if (i == 0) {
 775                                 printk(KERN_ERR "%s: No memory available"
 776                                         " for RFD list.\n", dev->name);
 777                                 return -ENOMEM;
 778                         }
 779                 }
 780
 781                 rxfd->next_desc = cpu_to_le64(sp->rxd_map +
 782                         sizeof(struct ipg_rx)*(i + 1));
 783         }
 784         sp->rxd[i - 1].next_desc = cpu_to_le64(sp->rxd_map);
 785
 786         sp->rx_current = 0;
 787         sp->rx_dirty = 0;
 788
 789         /* Write the location of the RFDList to the IPG. */
 790         ipg_w32((u32) sp->rxd_map, RFD_LIST_PTR_0);
 791         ipg_w32(0x00000000, RFD_LIST_PTR_1);
 792
 793         return 0;
 794 }
 795
 796 static void init_tfdlist(struct net_device *dev)
 797 {
 798         struct ipg_nic_private *sp = netdev_priv(dev);
 799         void __iomem *ioaddr = sp->ioaddr;
 800         unsigned int i;
 801
 802         IPG_DEBUG_MSG("_init_tfdlist\n");
 803
 804         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
 805                 struct ipg_tx *txfd = sp->txd + i;
 806
 807                 txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
 808
 809                 if (sp->TxBuff[i]) {
 810                         IPG_DEV_KFREE_SKB(sp->TxBuff[i]);
 811                         sp->TxBuff[i] = NULL;
 812                 }
 813
 814                 txfd->next_desc = cpu_to_le64(sp->txd_map +
 815                         sizeof(struct ipg_tx)*(i + 1));
 816         }
 817         sp->txd[i - 1].next_desc = cpu_to_le64(sp->txd_map);
 818
 819         sp->tx_current = 0;
 820         sp->tx_dirty = 0;
 821
 822         /* Write the location of the TFDList to the IPG. */
 823         IPG_DDEBUG_MSG("Starting TFDListPtr = %8.8x\n",
 824                        (u32) sp->txd_map);
 825         ipg_w32((u32) sp->txd_map, TFD_LIST_PTR_0);
 826         ipg_w32(0x00000000, TFD_LIST_PTR_1);
 827
 828         sp->ResetCurrentTFD = 1;
 829 }
 830
 831 /*
 832  * Free all transmit buffers which have already been transfered
 833  * via DMA to the IPG.
 834  */
 835 static void ipg_nic_txfree(struct net_device *dev)
 836 {
 837         struct ipg_nic_private *sp = netdev_priv(dev);
 838         void __iomem *ioaddr = sp->ioaddr;
 839         const unsigned int curr = ipg_r32(TFD_LIST_PTR_0) -
 840                 (sp->txd_map / sizeof(struct ipg_tx)) - 1;
 841         unsigned int released, pending;
 842
 843         IPG_DEBUG_MSG("_nic_txfree\n");
 844
 845         pending = sp->tx_current - sp->tx_dirty;
 846
 847         for (released = 0; released < pending; released++) {
 848                 unsigned int dirty = sp->tx_dirty % IPG_TFDLIST_LENGTH;
 849                 struct sk_buff *skb = sp->TxBuff[dirty];
 850                 struct ipg_tx *txfd = sp->txd + dirty;
 851
 852                 IPG_DEBUG_MSG("TFC = %16.16lx\n", (unsigned long) txfd->tfc);
 853
 854                 /* Look at each TFD's TFC field beginning
 855                  * at the last freed TFD up to the current TFD.
 856                  * If the TFDDone bit is set, free the associated
 857                  * buffer.
 858                  */
 859                 if (dirty == curr)
 860                         break;
 861
 862                 /* Setup TFDDONE for compatible issue. */
 863                 txfd->tfc |= cpu_to_le64(IPG_TFC_TFDDONE);
 864
 865                 /* Free the transmit buffer. */
 866                 if (skb) {
 867                         pci_unmap_single(sp->pdev,
 868                                 le64_to_cpu(txfd->frag_info & ~IPG_TFI_FRAGLEN),
 869                                 skb->len, PCI_DMA_TODEVICE);
 870
 871                         IPG_DEV_KFREE_SKB(skb);
 872
 873                         sp->TxBuff[dirty] = NULL;
 874                 }
 875         }
 876
 877         sp->tx_dirty += released;
 878
 879         if (netif_queue_stopped(dev) &&
 880             (sp->tx_current != (sp->tx_dirty + IPG_TFDLIST_LENGTH))) {
 881                 netif_wake_queue(dev);
 882         }
 883 }
 884
 885 static void ipg_tx_timeout(struct net_device *dev)
 886 {
 887         struct ipg_nic_private *sp = netdev_priv(dev);
 888         void __iomem *ioaddr = sp->ioaddr;
 889
 890         ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA | IPG_AC_NETWORK |
 891                   IPG_AC_FIFO);
 892
 893         spin_lock_irq(&sp->lock);
 894
 895         /* Re-configure after DMA reset. */
 896         if (ipg_io_config(dev) < 0) {
 897                 printk(KERN_INFO "%s: Error during re-configuration.\n",
 898                        dev->name);
 899         }
 900
 901         init_tfdlist(dev);
 902
 903         spin_unlock_irq(&sp->lock);
 904
 905         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) & IPG_MC_RSVD_MASK,
 906                 MAC_CTRL);
 907 }
 908
 909 /*
 910  * For TxComplete interrupts, free all transmit
 911  * buffers which have already been transfered via DMA
 912  * to the IPG.
 913  */
 914 static void ipg_nic_txcleanup(struct net_device *dev)
 915 {
 916         struct ipg_nic_private *sp = netdev_priv(dev);
 917         void __iomem *ioaddr = sp->ioaddr;
 918         unsigned int i;
 919
 920         IPG_DEBUG_MSG("_nic_txcleanup\n");
 921
 922         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
 923                 /* Reading the TXSTATUS register clears the
 924                  * TX_COMPLETE interrupt.
 925                  */
 926                 u32 txstatusdword = ipg_r32(TX_STATUS);
 927
 928                 IPG_DEBUG_MSG("TxStatus = %8.8x\n", txstatusdword);
 929
 930                 /* Check for Transmit errors. Error bits only valid if
 931                  * TX_COMPLETE bit in the TXSTATUS register is a 1.
 932                  */
 933                 if (!(txstatusdword & IPG_TS_TX_COMPLETE))
 934                         break;
 935
 936                 /* If in 10Mbps mode, indicate transmit is ready. */
 937                 if (sp->tenmbpsmode) {
 938                         netif_wake_queue(dev);
 939                 }
 940
 941                 /* Transmit error, increment stat counters. */
 942                 if (txstatusdword & IPG_TS_TX_ERROR) {
 943                         IPG_DEBUG_MSG("Transmit error.\n");
 944                         sp->stats.tx_errors++;
 945                 }
 946
 947                 /* Late collision, re-enable transmitter. */
 948                 if (txstatusdword & IPG_TS_LATE_COLLISION) {
 949                         IPG_DEBUG_MSG("Late collision on transmit.\n");
 950                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
 951                                 IPG_MC_RSVD_MASK, MAC_CTRL);
 952                 }
 953
 954                 /* Maximum collisions, re-enable transmitter. */
 955                 if (txstatusdword & IPG_TS_TX_MAX_COLL) {
 956                         IPG_DEBUG_MSG("Maximum collisions on transmit.\n");
 957                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
 958                                 IPG_MC_RSVD_MASK, MAC_CTRL);
 959                 }
 960
 961                 /* Transmit underrun, reset and re-enable
 962                  * transmitter.
 963                  */
 964                 if (txstatusdword & IPG_TS_TX_UNDERRUN) {
 965                         IPG_DEBUG_MSG("Transmitter underrun.\n");
 966                         sp->stats.tx_fifo_errors++;
 967                         ipg_reset(dev, IPG_AC_TX_RESET | IPG_AC_DMA |
 968                                   IPG_AC_NETWORK | IPG_AC_FIFO);
 969
 970                         /* Re-configure after DMA reset. */
 971                         if (ipg_io_config(dev) < 0) {
 972                                 printk(KERN_INFO
 973                                        "%s: Error during re-configuration.\n",
 974                                        dev->name);
 975                         }
 976                         init_tfdlist(dev);
 977
 978                         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_TX_ENABLE) &
 979                                 IPG_MC_RSVD_MASK, MAC_CTRL);
 980                 }
 981         }
 982
 983         ipg_nic_txfree(dev);
 984 }
 985
 986 /* Provides statistical information about the IPG NIC. */
 987 struct net_device_stats *ipg_nic_get_stats(struct net_device *dev)
 988 {
 989         struct ipg_nic_private *sp = netdev_priv(dev);
 990         void __iomem *ioaddr = sp->ioaddr;
 991         u16 temp1;
 992         u16 temp2;
 993
 994         IPG_DEBUG_MSG("_nic_get_stats\n");
 995
 996         /* Check to see if the NIC has been initialized via nic_open,
 997          * before trying to read statistic registers.
 998          */
 999         if (!test_bit(__LINK_STATE_START, &dev->state))
1000                 return &sp->stats;
1001
1002         sp->stats.rx_packets += ipg_r32(IPG_FRAMESRCVDOK);
1003         sp->stats.tx_packets += ipg_r32(IPG_FRAMESXMTDOK);
1004         sp->stats.rx_bytes += ipg_r32(IPG_OCTETRCVOK);
1005         sp->stats.tx_bytes += ipg_r32(IPG_OCTETXMTOK);
1006         temp1 = ipg_r16(IPG_FRAMESLOSTRXERRORS);
1007         sp->stats.rx_errors += temp1;
1008         sp->stats.rx_missed_errors += temp1;
1009         temp1 = ipg_r32(IPG_SINGLECOLFRAMES) + ipg_r32(IPG_MULTICOLFRAMES) +
1010                 ipg_r32(IPG_LATECOLLISIONS);
1011         temp2 = ipg_r16(IPG_CARRIERSENSEERRORS);
1012         sp->stats.collisions += temp1;
1013         sp->stats.tx_dropped += ipg_r16(IPG_FRAMESABORTXSCOLLS);
1014         sp->stats.tx_errors += ipg_r16(IPG_FRAMESWEXDEFERRAL) +
1015                 ipg_r32(IPG_FRAMESWDEFERREDXMT) + temp1 + temp2;
1016         sp->stats.multicast += ipg_r32(IPG_MCSTOCTETRCVDOK);
1017
1018         /* detailed tx_errors */
1019         sp->stats.tx_carrier_errors += temp2;
1020
1021         /* detailed rx_errors */
1022         sp->stats.rx_length_errors += ipg_r16(IPG_INRANGELENGTHERRORS) +
1023                 ipg_r16(IPG_FRAMETOOLONGERRRORS);
1024         sp->stats.rx_crc_errors += ipg_r16(IPG_FRAMECHECKSEQERRORS);
1025
1026         /* Unutilized IPG statistic registers. */
1027         ipg_r32(IPG_MCSTFRAMESRCVDOK);
1028
1029         return &sp->stats;
1030 }
1031
1032 /* Restore used receive buffers. */
1033 static int ipg_nic_rxrestore(struct net_device *dev)
1034 {
1035         struct ipg_nic_private *sp = netdev_priv(dev);
1036         const unsigned int curr = sp->rx_current;
1037         unsigned int dirty = sp->rx_dirty;
1038
1039         IPG_DEBUG_MSG("_nic_rxrestore\n");
1040
1041         for (dirty = sp->rx_dirty; curr - dirty > 0; dirty++) {
1042                 unsigned int entry = dirty % IPG_RFDLIST_LENGTH;
1043
1044                 /* rx_copybreak may poke hole here and there. */
1045                 if (sp->RxBuff[entry])
1046                         continue;
1047
1048                 /* Generate a new receive buffer to replace the
1049                  * current buffer (which will be released by the
1050                  * Linux system).
1051                  */
1052                 if (ipg_get_rxbuff(dev, entry) < 0) {
1053                         IPG_DEBUG_MSG("Cannot allocate new Rx buffer.\n");
1054
1055                         break;
1056                 }
1057
1058                 /* Reset the RFS field. */
1059                 sp->rxd[entry].rfs = 0x0000000000000000;
1060         }
1061         sp->rx_dirty = dirty;
1062
1063         return 0;
1064 }
1065
1066 #ifdef JUMBO_FRAME
1067
1068 /* use jumboindex and jumbosize to control jumbo frame status
1069    initial status is jumboindex=-1 and jumbosize=0
1070    1. jumboindex = -1 and jumbosize=0 : previous jumbo frame has been done.
1071    2. jumboindex != -1 and jumbosize != 0 : jumbo frame is not over size and receiving
1072    3. jumboindex = -1 and jumbosize != 0 : jumbo frame is over size, already dump
1073                 previous receiving and need to continue dumping the current one
1074 */
1075 enum {
1076         NormalPacket,
1077         ErrorPacket
1078 };
1079
1080 enum {
1081         Frame_NoStart_NoEnd     = 0,
1082         Frame_WithStart         = 1,
1083         Frame_WithEnd           = 10,
1084         Frame_WithStart_WithEnd = 11
1085 };
1086
1087 inline void ipg_nic_rx_free_skb(struct net_device *dev)
1088 {
1089         struct ipg_nic_private *sp = netdev_priv(dev);
1090         unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1091
1092         if (sp->RxBuff[entry]) {
1093                 struct ipg_rx *rxfd = sp->rxd + entry;
1094
1095                 pci_unmap_single(sp->pdev,
1096                         le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1097                         sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1098                 IPG_DEV_KFREE_SKB(sp->RxBuff[entry]);
1099                 sp->RxBuff[entry] = NULL;
1100         }
1101 }
1102
1103 inline int ipg_nic_rx_check_frame_type(struct net_device *dev)
1104 {
1105         struct ipg_nic_private *sp = netdev_priv(dev);
1106         struct ipg_rx *rxfd = sp->rxd + (sp->rx_current % IPG_RFDLIST_LENGTH);
1107         int type = Frame_NoStart_NoEnd;
1108
1109         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMESTART)
1110                 type += Frame_WithStart;
1111         if (le64_to_cpu(rxfd->rfs) & IPG_RFS_FRAMEEND)
1112                 type += Frame_WithEnd;
1113         return type;
1114 }
1115
1116 inline int ipg_nic_rx_check_error(struct net_device *dev)
1117 {
1118         struct ipg_nic_private *sp = netdev_priv(dev);
1119         unsigned int entry = sp->rx_current % IPG_RFDLIST_LENGTH;
1120         struct ipg_rx *rxfd = sp->rxd + entry;
1121
1122         if (IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs) &
1123              (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1124               IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1125               IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR))) {
1126                 IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1127                               (unsigned long) rxfd->rfs);
1128
1129                 /* Increment general receive error statistic. */
1130                 sp->stats.rx_errors++;
1131
1132                 /* Increment detailed receive error statistics. */
1133                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFIFOOVERRUN) {
1134                         IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1135
1136                         sp->stats.rx_fifo_errors++;
1137                 }
1138
1139                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXRUNTFRAME) {
1140                         IPG_DEBUG_MSG("RX runt occured.\n");
1141                         sp->stats.rx_length_errors++;
1142                 }
1143
1144                 /* Do nothing for IPG_RFS_RXOVERSIZEDFRAME,
1145                  * error count handled by a IPG statistic register.
1146                  */
1147
1148                 if (le64_to_cpu(rxfd->rfs) & IPG_RFS_RXALIGNMENTERROR) {
1149                         IPG_DEBUG_MSG("RX alignment error occured.\n");
1150                         sp->stats.rx_frame_errors++;
1151                 }
1152
1153                 /* Do nothing for IPG_RFS_RXFCSERROR, error count
1154                  * handled by a IPG statistic register.
1155                  */
1156
1157                 /* Free the memory associated with the RX
1158                  * buffer since it is erroneous and we will
1159                  * not pass it to higher layer processes.
1160                  */
1161                 if (sp->RxBuff[entry]) {
1162                         pci_unmap_single(sp->pdev,
1163                                 le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1164                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1165
1166                         IPG_DEV_KFREE_SKB(sp->RxBuff[entry]);
1167                         sp->RxBuff[entry] = NULL;
1168                 }
1169                 return ErrorPacket;
1170         }
1171         return NormalPacket;
1172 }
1173
1174 static void ipg_nic_rx_with_start_and_end(struct net_device *dev,
1175                                           struct ipg_nic_private *sp,
1176                                           struct ipg_rx *rxfd, unsigned entry)
1177 {
1178         struct SJumbo *jumbo = &sp->Jumbo;
1179         struct sk_buff *skb;
1180         int framelen;
1181
1182         if (jumbo->FoundStart) {
1183                 IPG_DEV_KFREE_SKB(jumbo->skb);
1184                 jumbo->FoundStart = 0;
1185                 jumbo->CurrentSize = 0;
1186                 jumbo->skb = NULL;
1187         }
1188
1189         // 1: found error, 0 no error
1190         if (ipg_nic_rx_check_error(dev) != NormalPacket)
1191                 return;
1192
1193         skb = sp->RxBuff[entry];
1194         if (!skb)
1195                 return;
1196
1197         // accept this frame and send to upper layer
1198         framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1199         if (framelen > IPG_RXFRAG_SIZE)
1200                 framelen = IPG_RXFRAG_SIZE;
1201
1202         skb_put(skb, framelen);
1203         skb->protocol = eth_type_trans(skb, dev);
1204         skb->ip_summed = CHECKSUM_NONE;
1205         netif_rx(skb);
1206         dev->last_rx = jiffies;
1207         sp->RxBuff[entry] = NULL;
1208 }
1209
1210 static void ipg_nic_rx_with_start(struct net_device *dev,
1211                                   struct ipg_nic_private *sp,
1212                                   struct ipg_rx *rxfd, unsigned entry)
1213 {
1214         struct SJumbo *jumbo = &sp->Jumbo;
1215         struct pci_dev *pdev = sp->pdev;
1216         struct sk_buff *skb;
1217
1218         // 1: found error, 0 no error
1219         if (ipg_nic_rx_check_error(dev) != NormalPacket)
1220                 return;
1221
1222         // accept this frame and send to upper layer
1223         skb = sp->RxBuff[entry];
1224         if (!skb)
1225                 return;
1226
1227         if (jumbo->FoundStart)
1228                 IPG_DEV_KFREE_SKB(jumbo->skb);
1229
1230         pci_unmap_single(pdev, le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1231                          sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1232
1233         skb_put(skb, IPG_RXFRAG_SIZE);
1234
1235         jumbo->FoundStart = 1;
1236         jumbo->CurrentSize = IPG_RXFRAG_SIZE;
1237         jumbo->skb = skb;
1238
1239         sp->RxBuff[entry] = NULL;
1240         dev->last_rx = jiffies;
1241 }
1242
1243 static void ipg_nic_rx_with_end(struct net_device *dev,
1244                                 struct ipg_nic_private *sp,
1245                                 struct ipg_rx *rxfd, unsigned entry)
1246 {
1247         struct SJumbo *jumbo = &sp->Jumbo;
1248
1249         //1: found error, 0 no error
1250         if (ipg_nic_rx_check_error(dev) == NormalPacket) {
1251                 struct sk_buff *skb = sp->RxBuff[entry];
1252
1253                 if (!skb)
1254                         return;
1255
1256                 if (jumbo->FoundStart) {
1257                         int framelen, endframelen;
1258
1259                         framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1260
1261                         endframeLen = framelen - jumbo->CurrentSize;
1262                         /*
1263                         if (framelen > IPG_RXFRAG_SIZE)
1264                                 framelen=IPG_RXFRAG_SIZE;
1265                          */
1266                         if (framelen > IPG_RXSUPPORT_SIZE)
1267                                 IPG_DEV_KFREE_SKB(jumbo->skb);
1268                         else {
1269                                 memcpy(skb_put(jumbo->skb, endframeLen),
1270                                        skb->data, endframeLen);
1271
1272                                 jumbo->skb->protocol =
1273                                     eth_type_trans(jumbo->skb, dev);
1274
1275                                 jumbo->skb->ip_summed = CHECKSUM_NONE;
1276                                 netif_rx(jumbo->skb);
1277                         }
1278                 }
1279
1280                 dev->last_rx = jiffies;
1281                 jumbo->FoundStart = 0;
1282                 jumbo->CurrentSize = 0;
1283                 jumbo->skb = NULL;
1284
1285                 ipg_nic_rx_free_skb(dev);
1286         } else {
1287                 IPG_DEV_KFREE_SKB(jumbo->skb);
1288                 jumbo->FoundStart = 0;
1289                 jumbo->CurrentSize = 0;
1290                 jumbo->skb = NULL;
1291         }
1292 }
1293
1294 static void ipg_nic_rx_no_start_no_end(struct net_device *dev,
1295                                        struct ipg_nic_private *sp,
1296                                        struct ipg_rx *rxfd, unsigned entry)
1297 {
1298         struct SJumbo *jumbo = &sp->Jumbo;
1299
1300         //1: found error, 0 no error
1301         if (ipg_nic_rx_check_error(dev) == NormalPacket) {
1302                 struct sk_buff *skb = sp->RxBuff[entry];
1303
1304                 if (skb) {
1305                         if (jumbo->FoundStart) {
1306                                 jumbo->CurrentSize += IPG_RXFRAG_SIZE;
1307                                 if (jumbo->CurrentSize <= IPG_RXSUPPORT_SIZE) {
1308                                         memcpy(skb_put(jumbo->skb,
1309                                                        IPG_RXFRAG_SIZE),
1310                                                skb->data, IPG_RXFRAG_SIZE);
1311                                 }
1312                         }
1313                         dev->last_rx = jiffies;
1314                         ipg_nic_rx_free_skb(dev);
1315                 }
1316         } else {
1317                 IPG_DEV_KFREE_SKB(jumbo->skb);
1318                 jumbo->FoundStart = 0;
1319                 jumbo->CurrentSize = 0;
1320                 jumbo->skb = NULL;
1321         }
1322 }
1323
1324 static int ipg_nic_rx(struct net_device *dev)
1325 {
1326         struct ipg_nic_private *sp = netdev_priv(dev);
1327         unsigned int curr = sp->rx_current;
1328         void __iomem *ioaddr = sp->ioaddr;
1329         unsigned int i;
1330
1331         IPG_DEBUG_MSG("_nic_rx\n");
1332
1333         for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1334                 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1335                 struct ipg_rx *rxfd = sp->rxd + entry;
1336
1337                 if (!(rxfd->rfs & le64_to_cpu(IPG_RFS_RFDDONE)))
1338                         break;
1339
1340                 switch (ipg_nic_rx_check_frame_type(dev)) {
1341                 case Frame_WithStart_WithEnd:
1342                         ipg_nic_rx_with_start_and_end(dev, tp, rxfd, entry);
1343                         break;
1344                 case Frame_WithStart:
1345                         ipg_nic_rx_with_start(dev, tp, rxfd, entry);
1346                         break;
1347                 case Frame_WithEnd:
1348                         ipg_nic_rx_with_end(dev, tp, rxfd, entry);
1349                         break;
1350                 case Frame_NoStart_NoEnd:
1351                         ipg_nic_rx_no_start_no_end(dev, tp, rxfd, entry);
1352                         break;
1353                 }
1354         }
1355
1356         sp->rx_current = curr;
1357
1358         if (i == IPG_MAXRFDPROCESS_COUNT) {
1359                 /* There are more RFDs to process, however the
1360                  * allocated amount of RFD processing time has
1361                  * expired. Assert Interrupt Requested to make
1362                  * sure we come back to process the remaining RFDs.
1363                  */
1364                 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1365         }
1366
1367         ipg_nic_rxrestore(dev);
1368
1369         return 0;
1370 }
1371
1372 #else
1373 static int ipg_nic_rx(struct net_device *dev)
1374 {
1375         /* Transfer received Ethernet frames to higher network layers. */
1376         struct ipg_nic_private *sp = netdev_priv(dev);
1377         unsigned int curr = sp->rx_current;
1378         void __iomem *ioaddr = sp->ioaddr;
1379         struct ipg_rx *rxfd;
1380         unsigned int i;
1381
1382         IPG_DEBUG_MSG("_nic_rx\n");
1383
1384 #define __RFS_MASK \
1385         cpu_to_le64(IPG_RFS_RFDDONE | IPG_RFS_FRAMESTART | IPG_RFS_FRAMEEND)
1386
1387         for (i = 0; i < IPG_MAXRFDPROCESS_COUNT; i++, curr++) {
1388                 unsigned int entry = curr % IPG_RFDLIST_LENGTH;
1389                 struct sk_buff *skb = sp->RxBuff[entry];
1390                 unsigned int framelen;
1391
1392                 rxfd = sp->rxd + entry;
1393
1394                 if (((rxfd->rfs & __RFS_MASK) != __RFS_MASK) || !skb)
1395                         break;
1396
1397                 /* Get received frame length. */
1398                 framelen = le64_to_cpu(rxfd->rfs) & IPG_RFS_RXFRAMELEN;
1399
1400                 /* Check for jumbo frame arrival with too small
1401                  * RXFRAG_SIZE.
1402                  */
1403                 if (framelen > IPG_RXFRAG_SIZE) {
1404                         IPG_DEBUG_MSG
1405                             ("RFS FrameLen > allocated fragment size.\n");
1406
1407                         framelen = IPG_RXFRAG_SIZE;
1408                 }
1409
1410                 if ((IPG_DROP_ON_RX_ETH_ERRORS && (le64_to_cpu(rxfd->rfs &
1411                        (IPG_RFS_RXFIFOOVERRUN | IPG_RFS_RXRUNTFRAME |
1412                         IPG_RFS_RXALIGNMENTERROR | IPG_RFS_RXFCSERROR |
1413                         IPG_RFS_RXOVERSIZEDFRAME | IPG_RFS_RXLENGTHERROR))))) {
1414
1415                         IPG_DEBUG_MSG("Rx error, RFS = %16.16lx\n",
1416                                       (unsigned long int) rxfd->rfs);
1417
1418                         /* Increment general receive error statistic. */
1419                         sp->stats.rx_errors++;
1420
1421                         /* Increment detailed receive error statistics. */
1422                         if (le64_to_cpu(rxfd->rfs & IPG_RFS_RXFIFOOVERRUN)) {
1423                                 IPG_DEBUG_MSG("RX FIFO overrun occured.\n");
1424                                 sp->stats.rx_fifo_errors++;
1425                         }
1426
1427                         if (le64_to_cpu(rxfd->rfs & IPG_RFS_RXRUNTFRAME)) {
1428                                 IPG_DEBUG_MSG("RX runt occured.\n");
1429                                 sp->stats.rx_length_errors++;
1430                         }
1431
1432                         if (le64_to_cpu(rxfd->rfs & IPG_RFS_RXOVERSIZEDFRAME)) ;
1433                         /* Do nothing, error count handled by a IPG
1434                          * statistic register.
1435                          */
1436
1437                         if (le64_to_cpu(rxfd->rfs & IPG_RFS_RXALIGNMENTERROR)) {
1438                                 IPG_DEBUG_MSG("RX alignment error occured.\n");
1439                                 sp->stats.rx_frame_errors++;
1440                         }
1441
1442                         if (le64_to_cpu(rxfd->rfs & IPG_RFS_RXFCSERROR)) ;
1443                         /* Do nothing, error count handled by a IPG
1444                          * statistic register.
1445                          */
1446
1447                         /* Free the memory associated with the RX
1448                          * buffer since it is erroneous and we will
1449                          * not pass it to higher layer processes.
1450                          */
1451                         if (skb) {
1452                                 u64 info = rxfd->frag_info;
1453
1454                                 pci_unmap_single(sp->pdev,
1455                                         le64_to_cpu(info & ~IPG_RFI_FRAGLEN),
1456                                         sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1457
1458                                 IPG_DEV_KFREE_SKB(skb);
1459                         }
1460                 } else {
1461
1462                         /* Adjust the new buffer length to accomodate the size
1463                          * of the received frame.
1464                          */
1465                         skb_put(skb, framelen);
1466
1467                         /* Set the buffer's protocol field to Ethernet. */
1468                         skb->protocol = eth_type_trans(skb, dev);
1469
1470                         /* If the frame contains an IP/TCP/UDP frame,
1471                          * determine if upper layer must check IP/TCP/UDP
1472                          * checksums.
1473                          *
1474                          * NOTE: DO NOT RELY ON THE TCP/UDP CHECKSUM
1475                          *       VERIFICATION FOR SILICON REVISIONS B3
1476                          *       AND EARLIER!
1477                          *
1478                          if ((le64_to_cpu(rxfd->rfs &
1479                              (IPG_RFS_TCPDETECTED | IPG_RFS_UDPDETECTED |
1480                               IPG_RFS_IPDETECTED))) &&
1481                             !(le64_to_cpu(rxfd->rfs &
1482                               (IPG_RFS_TCPERROR | IPG_RFS_UDPERROR |
1483                                IPG_RFS_IPERROR)))) {
1484                                  * Indicate IP checksums were performed
1485                                  * by the IPG.
1486                                  *
1487                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1488                          } else
1489                          */
1490                          {
1491                                 /* The IPG encountered an error with (or
1492                                  * there were no) IP/TCP/UDP checksums.
1493                                  * This may or may not indicate an invalid
1494                                  * IP/TCP/UDP frame was received. Let the
1495                                  * upper layer decide.
1496                                  */
1497                                 skb->ip_summed = CHECKSUM_NONE;
1498                         }
1499
1500                         /* Hand off frame for higher layer processing.
1501                          * The function netif_rx() releases the sk_buff
1502                          * when processing completes.
1503                          */
1504                         netif_rx(skb);
1505
1506                         /* Record frame receive time (jiffies = Linux
1507                          * kernel current time stamp).
1508                          */
1509                         dev->last_rx = jiffies;
1510                 }
1511
1512                 /* Assure RX buffer is not reused by IPG. */
1513                 sp->RxBuff[entry] = NULL;
1514         }
1515
1516         /*
1517          * If there are more RFDs to proces and the allocated amount of RFD
1518          * processing time has expired, assert Interrupt Requested to make
1519          * sure we come back to process the remaining RFDs.
1520          */
1521         if (i == IPG_MAXRFDPROCESS_COUNT)
1522                 ipg_w32(ipg_r32(ASIC_CTRL) | IPG_AC_INT_REQUEST, ASIC_CTRL);
1523
1524 #ifdef IPG_DEBUG
1525         /* Check if the RFD list contained no receive frame data. */
1526         if (!i)
1527                 sp->EmptyRFDListCount++;
1528 #endif
1529         while ((le64_to_cpu(rxfd->rfs & IPG_RFS_RFDDONE)) &&
1530                !((le64_to_cpu(rxfd->rfs & IPG_RFS_FRAMESTART)) &&
1531                  (le64_to_cpu(rxfd->rfs & IPG_RFS_FRAMEEND)))) {
1532                 unsigned int entry = curr++ % IPG_RFDLIST_LENGTH;
1533
1534                 rxfd = sp->rxd + entry;
1535
1536                 IPG_DEBUG_MSG("Frame requires multiple RFDs.\n");
1537
1538                 /* An unexpected event, additional code needed to handle
1539                  * properly. So for the time being, just disregard the
1540                  * frame.
1541                  */
1542
1543                 /* Free the memory associated with the RX
1544                  * buffer since it is erroneous and we will
1545                  * not pass it to higher layer processes.
1546                  */
1547                 if (sp->RxBuff[entry]) {
1548                         pci_unmap_single(sp->pdev,
1549                                 le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1550                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1551                         IPG_DEV_KFREE_SKB(sp->RxBuff[entry]);
1552                 }
1553
1554                 /* Assure RX buffer is not reused by IPG. */
1555                 sp->RxBuff[entry] = NULL;
1556         }
1557
1558         sp->rx_current = curr;
1559
1560         /* Check to see if there are a minimum number of used
1561          * RFDs before restoring any (should improve performance.)
1562          */
1563         if ((curr - sp->rx_dirty) >= IPG_MINUSEDRFDSTOFREE)
1564                 ipg_nic_rxrestore(dev);
1565
1566         return 0;
1567 }
1568 #endif
1569
1570 static void ipg_reset_after_host_error(struct work_struct *work)
1571 {
1572         struct ipg_nic_private *sp =
1573                 container_of(work, struct ipg_nic_private, task.work);
1574         struct net_device *dev = sp->dev;
1575
1576         IPG_DDEBUG_MSG("DMACtrl = %8.8x\n", ioread32(sp->ioaddr + IPG_DMACTRL));
1577
1578         /*
1579          * Acknowledge HostError interrupt by resetting
1580          * IPG DMA and HOST.
1581          */
1582         ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1583
1584         init_rfdlist(dev);
1585         init_tfdlist(dev);
1586
1587         if (ipg_io_config(dev) < 0) {
1588                 printk(KERN_INFO "%s: Cannot recover from PCI error.\n",
1589                        dev->name);
1590                 schedule_delayed_work(&sp->task, HZ);
1591         }
1592 }
1593
1594 static irqreturn_t ipg_interrupt_handler(int irq, void *dev_inst)
1595 {
1596         struct net_device *dev = dev_inst;
1597         struct ipg_nic_private *sp = netdev_priv(dev);
1598         void __iomem *ioaddr = sp->ioaddr;
1599         unsigned int handled = 0;
1600         u16 status;
1601
1602         IPG_DEBUG_MSG("_interrupt_handler\n");
1603
1604 #ifdef JUMBO_FRAME
1605         ipg_nic_rxrestore(dev);
1606 #endif
1607         /* Get interrupt source information, and acknowledge
1608          * some (i.e. TxDMAComplete, RxDMAComplete, RxEarly,
1609          * IntRequested, MacControlFrame, LinkEvent) interrupts
1610          * if issued. Also, all IPG interrupts are disabled by
1611          * reading IntStatusAck.
1612          */
1613         status = ipg_r16(INT_STATUS_ACK);
1614
1615         IPG_DEBUG_MSG("IntStatusAck = %4.4x\n", status);
1616
1617         /* Shared IRQ of remove event. */
1618         if (!(status & IPG_IS_RSVD_MASK))
1619                 goto out_enable;
1620
1621         handled = 1;
1622
1623         if (unlikely(!netif_running(dev)))
1624                 goto out;
1625
1626         spin_lock(&sp->lock);
1627
1628         /* If RFDListEnd interrupt, restore all used RFDs. */
1629         if (status & IPG_IS_RFD_LIST_END) {
1630                 IPG_DEBUG_MSG("RFDListEnd Interrupt.\n");
1631
1632                 /* The RFD list end indicates an RFD was encountered
1633                  * with a 0 NextPtr, or with an RFDDone bit set to 1
1634                  * (indicating the RFD is not read for use by the
1635                  * IPG.) Try to restore all RFDs.
1636                  */
1637                 ipg_nic_rxrestore(dev);
1638
1639 #ifdef IPG_DEBUG
1640                 /* Increment the RFDlistendCount counter. */
1641                 sp->RFDlistendCount++;
1642 #endif
1643         }
1644
1645         /* If RFDListEnd, RxDMAPriority, RxDMAComplete, or
1646          * IntRequested interrupt, process received frames. */
1647         if ((status & IPG_IS_RX_DMA_PRIORITY) ||
1648             (status & IPG_IS_RFD_LIST_END) ||
1649             (status & IPG_IS_RX_DMA_COMPLETE) ||
1650             (status & IPG_IS_INT_REQUESTED)) {
1651 #ifdef IPG_DEBUG
1652                 /* Increment the RFD list checked counter if interrupted
1653                  * only to check the RFD list. */
1654                 if (status & (~(IPG_IS_RX_DMA_PRIORITY | IPG_IS_RFD_LIST_END |
1655                                 IPG_IS_RX_DMA_COMPLETE | IPG_IS_INT_REQUESTED) &
1656                                (IPG_IS_HOST_ERROR | IPG_IS_TX_DMA_COMPLETE |
1657                                 IPG_IS_LINK_EVENT | IPG_IS_TX_COMPLETE |
1658                                 IPG_IS_UPDATE_STATS)))
1659                         sp->RFDListCheckedCount++;
1660 #endif
1661
1662                 ipg_nic_rx(dev);
1663         }
1664
1665         /* If TxDMAComplete interrupt, free used TFDs. */
1666         if (status & IPG_IS_TX_DMA_COMPLETE)
1667                 ipg_nic_txfree(dev);
1668
1669         /* TxComplete interrupts indicate one of numerous actions.
1670          * Determine what action to take based on TXSTATUS register.
1671          */
1672         if (status & IPG_IS_TX_COMPLETE)
1673                 ipg_nic_txcleanup(dev);
1674
1675         /* If UpdateStats interrupt, update Linux Ethernet statistics */
1676         if (status & IPG_IS_UPDATE_STATS)
1677                 ipg_nic_get_stats(dev);
1678
1679         /* If HostError interrupt, reset IPG. */
1680         if (status & IPG_IS_HOST_ERROR) {
1681                 IPG_DDEBUG_MSG("HostError Interrupt\n");
1682
1683                 schedule_delayed_work(&sp->task, 0);
1684         }
1685
1686         /* If LinkEvent interrupt, resolve autonegotiation. */
1687         if (status & IPG_IS_LINK_EVENT) {
1688                 if (ipg_config_autoneg(dev) < 0)
1689                         printk(KERN_INFO "%s: Auto-negotiation error.\n",
1690                                dev->name);
1691         }
1692
1693         /* If MACCtrlFrame interrupt, do nothing. */
1694         if (status & IPG_IS_MAC_CTRL_FRAME)
1695                 IPG_DEBUG_MSG("MACCtrlFrame interrupt.\n");
1696
1697         /* If RxComplete interrupt, do nothing. */
1698         if (status & IPG_IS_RX_COMPLETE)
1699                 IPG_DEBUG_MSG("RxComplete interrupt.\n");
1700
1701         /* If RxEarly interrupt, do nothing. */
1702         if (status & IPG_IS_RX_EARLY)
1703                 IPG_DEBUG_MSG("RxEarly interrupt.\n");
1704
1705 out_enable:
1706         /* Re-enable IPG interrupts. */
1707         ipg_w16(IPG_IE_TX_DMA_COMPLETE | IPG_IE_RX_DMA_COMPLETE |
1708                 IPG_IE_HOST_ERROR | IPG_IE_INT_REQUESTED | IPG_IE_TX_COMPLETE |
1709                 IPG_IE_LINK_EVENT | IPG_IE_UPDATE_STATS, INT_ENABLE);
1710
1711         spin_unlock(&sp->lock);
1712 out:
1713         return IRQ_RETVAL(handled);
1714 }
1715
1716 static void ipg_rx_clear(struct ipg_nic_private *sp)
1717 {
1718         unsigned int i;
1719
1720         for (i = 0; i < IPG_RFDLIST_LENGTH; i++) {
1721                 if (sp->RxBuff[i]) {
1722                         struct ipg_rx *rxfd = sp->rxd + i;
1723
1724                         IPG_DEV_KFREE_SKB(sp->RxBuff[i]);
1725                         sp->RxBuff[i] = NULL;
1726                         pci_unmap_single(sp->pdev,
1727                                 le64_to_cpu(rxfd->frag_info & ~IPG_RFI_FRAGLEN),
1728                                 sp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1729                 }
1730         }
1731 }
1732
1733 static void ipg_tx_clear(struct ipg_nic_private *sp)
1734 {
1735         unsigned int i;
1736
1737         for (i = 0; i < IPG_TFDLIST_LENGTH; i++) {
1738                 if (sp->TxBuff[i]) {
1739                         struct ipg_tx *txfd = sp->txd + i;
1740
1741                         pci_unmap_single(sp->pdev,
1742                                 le64_to_cpu(txfd->frag_info & ~IPG_TFI_FRAGLEN),
1743                                 sp->TxBuff[i]->len, PCI_DMA_TODEVICE);
1744
1745                         IPG_DEV_KFREE_SKB(sp->TxBuff[i]);
1746
1747                         sp->TxBuff[i] = NULL;
1748                 }
1749         }
1750 }
1751
1752 static int ipg_nic_open(struct net_device *dev)
1753 {
1754         struct ipg_nic_private *sp = netdev_priv(dev);
1755         void __iomem *ioaddr = sp->ioaddr;
1756         struct pci_dev *pdev = sp->pdev;
1757         int rc;
1758
1759         IPG_DEBUG_MSG("_nic_open\n");
1760
1761         sp->rx_buf_sz = IPG_RXSUPPORT_SIZE;
1762
1763         /* Check for interrupt line conflicts, and request interrupt
1764          * line for IPG.
1765          *
1766          * IMPORTANT: Disable IPG interrupts prior to registering
1767          *            IRQ.
1768          */
1769         ipg_w16(0x0000, INT_ENABLE);
1770
1771         /* Register the interrupt line to be used by the IPG within
1772          * the Linux system.
1773          */
1774         rc = request_irq(pdev->irq, &ipg_interrupt_handler, IRQF_SHARED,
1775                          dev->name, dev);
1776         if (rc < 0) {
1777                 printk(KERN_INFO "%s: Error when requesting interrupt.\n",
1778                        dev->name);
1779                 goto out;
1780         }
1781
1782         dev->irq = pdev->irq;
1783
1784         rc = -ENOMEM;
1785
1786         sp->rxd = dma_alloc_coherent(&pdev->dev, IPG_RX_RING_BYTES,
1787                                      &sp->rxd_map, GFP_KERNEL);
1788         if (!sp->rxd)
1789                 goto err_free_irq_0;
1790
1791         sp->txd = dma_alloc_coherent(&pdev->dev, IPG_TX_RING_BYTES,
1792                                      &sp->txd_map, GFP_KERNEL);
1793         if (!sp->txd)
1794                 goto err_free_rx_1;
1795
1796         rc = init_rfdlist(dev);
1797         if (rc < 0) {
1798                 printk(KERN_INFO "%s: Error during configuration.\n",
1799                        dev->name);
1800                 goto err_free_tx_2;
1801         }
1802
1803         init_tfdlist(dev);
1804
1805         rc = ipg_io_config(dev);
1806         if (rc < 0) {
1807                 printk(KERN_INFO "%s: Error during configuration.\n",
1808                        dev->name);
1809                 goto err_release_tfdlist_3;
1810         }
1811
1812         /* Resolve autonegotiation. */
1813         if (ipg_config_autoneg(dev) < 0)
1814                 printk(KERN_INFO "%s: Auto-negotiation error.\n", dev->name);
1815
1816 #ifdef JUMBO_FRAME
1817         /* initialize JUMBO Frame control variable */
1818         sp->Jumbo.FoundStart = 0;
1819         sp->Jumbo.CurrentSize = 0;
1820         sp->Jumbo.skb = 0;
1821         dev->mtu = IPG_TXFRAG_SIZE;
1822 #endif
1823
1824         /* Enable transmit and receive operation of the IPG. */
1825         ipg_w32((ipg_r32(MAC_CTRL) | IPG_MC_RX_ENABLE | IPG_MC_TX_ENABLE) &
1826                  IPG_MC_RSVD_MASK, MAC_CTRL);
1827
1828         netif_start_queue(dev);
1829 out:
1830         return rc;
1831
1832 err_release_tfdlist_3:
1833         ipg_tx_clear(sp);
1834         ipg_rx_clear(sp);
1835 err_free_tx_2:
1836         dma_free_coherent(&pdev->dev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1837 err_free_rx_1:
1838         dma_free_coherent(&pdev->dev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1839 err_free_irq_0:
1840         free_irq(pdev->irq, dev);
1841         goto out;
1842 }
1843
1844 static int ipg_nic_stop(struct net_device *dev)
1845 {
1846         struct ipg_nic_private *sp = netdev_priv(dev);
1847         void __iomem *ioaddr = sp->ioaddr;
1848         struct pci_dev *pdev = sp->pdev;
1849
1850         IPG_DEBUG_MSG("_nic_stop\n");
1851
1852         netif_stop_queue(dev);
1853
1854         IPG_DDEBUG_MSG("RFDlistendCount = %i\n", sp->RFDlistendCount);
1855         IPG_DDEBUG_MSG("RFDListCheckedCount = %i\n", sp->rxdCheckedCount);
1856         IPG_DDEBUG_MSG("EmptyRFDListCount = %i\n", sp->EmptyRFDListCount);
1857         IPG_DUMPTFDLIST(dev);
1858
1859         do {
1860                 (void) ipg_r16(INT_STATUS_ACK);
1861
1862                 ipg_reset(dev, IPG_AC_GLOBAL_RESET | IPG_AC_HOST | IPG_AC_DMA);
1863
1864                 synchronize_irq(pdev->irq);
1865         } while (ipg_r16(INT_ENABLE) & IPG_IE_RSVD_MASK);
1866
1867         ipg_rx_clear(sp);
1868
1869         ipg_tx_clear(sp);
1870
1871         pci_free_consistent(pdev, IPG_RX_RING_BYTES, sp->rxd, sp->rxd_map);
1872         pci_free_consistent(pdev, IPG_TX_RING_BYTES, sp->txd, sp->txd_map);
1873
1874         free_irq(pdev->irq, dev);
1875
1876         return 0;
1877 }
1878
1879 static int ipg_nic_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
1880 {
1881         struct ipg_nic_private *sp = netdev_priv(dev);
1882         void __iomem *ioaddr = sp->ioaddr;
1883         unsigned int entry = sp->tx_current % IPG_TFDLIST_LENGTH;
1884         unsigned long flags;
1885         struct ipg_tx *txfd;
1886
1887         IPG_DDEBUG_MSG("_nic_hard_start_xmit\n");
1888
1889         /* If in 10Mbps mode, stop the transmit queue so
1890          * no more transmit frames are accepted.
1891          */
1892         if (sp->tenmbpsmode)
1893                 netif_stop_queue(dev);
1894
1895         if (sp->ResetCurrentTFD) {
1896                 sp->ResetCurrentTFD = 0;
1897                 entry = 0;
1898         }
1899
1900         txfd = sp->txd + entry;
1901
1902         sp->TxBuff[entry] = skb;
1903
1904         /* Clear all TFC fields, except TFDDONE. */
1905         txfd->tfc = cpu_to_le64(IPG_TFC_TFDDONE);
1906
1907         /* Specify the TFC field within the TFD. */
1908         txfd->tfc |= cpu_to_le64(IPG_TFC_WORDALIGNDISABLED |
1909                 (IPG_TFC_FRAMEID & cpu_to_le64(sp->tx_current)) |
1910                 (IPG_TFC_FRAGCOUNT & (1 << 24)));
1911
1912         /* Request TxComplete interrupts at an interval defined
1913          * by the constant IPG_FRAMESBETWEENTXCOMPLETES.
1914          * Request TxComplete interrupt for every frame
1915          * if in 10Mbps mode to accomodate problem with 10Mbps
1916          * processing.
1917          */
1918         if (sp->tenmbpsmode)
1919                 txfd->tfc |= cpu_to_le64(IPG_TFC_TXINDICATE);
1920         else if (!((sp->tx_current - sp->tx_dirty + 1) >
1921             IPG_FRAMESBETWEENTXDMACOMPLETES)) {
1922                 txfd->tfc |= cpu_to_le64(IPG_TFC_TXDMAINDICATE);
1923         }
1924         /* Based on compilation option, determine if FCS is to be
1925          * appended to transmit frame by IPG.
1926          */
1927         if (!(IPG_APPEND_FCS_ON_TX))
1928                 txfd->tfc |= cpu_to_le64(IPG_TFC_FCSAPPENDDISABLE);
1929
1930         /* Based on compilation option, determine if IP, TCP and/or
1931          * UDP checksums are to be added to transmit frame by IPG.
1932          */
1933         if (IPG_ADD_IPCHECKSUM_ON_TX)
1934                 txfd->tfc |= cpu_to_le64(IPG_TFC_IPCHECKSUMENABLE);
1935
1936         if (IPG_ADD_TCPCHECKSUM_ON_TX)
1937                 txfd->tfc |= cpu_to_le64(IPG_TFC_TCPCHECKSUMENABLE);
1938
1939         if (IPG_ADD_UDPCHECKSUM_ON_TX)
1940                 txfd->tfc |= cpu_to_le64(IPG_TFC_UDPCHECKSUMENABLE);
1941
1942         /* Based on compilation option, determine if VLAN tag info is to be
1943          * inserted into transmit frame by IPG.
1944          */
1945         if (IPG_INSERT_MANUAL_VLAN_TAG) {
1946                 txfd->tfc |= cpu_to_le64(IPG_TFC_VLANTAGINSERT |
1947                         ((u64) IPG_MANUAL_VLAN_VID << 32) |
1948                         ((u64) IPG_MANUAL_VLAN_CFI << 44) |
1949                         ((u64) IPG_MANUAL_VLAN_USERPRIORITY << 45));
1950         }
1951
1952         /* The fragment start location within system memory is defined
1953          * by the sk_buff structure's data field. The physical address
1954          * of this location within the system's virtual memory space
1955          * is determined using the IPG_HOST2BUS_MAP function.
1956          */
1957         txfd->frag_info = cpu_to_le64(pci_map_single(sp->pdev, skb->data,
1958                 skb->len, PCI_DMA_TODEVICE));
1959
1960         /* The length of the fragment within system memory is defined by
1961          * the sk_buff structure's len field.
1962          */
1963         txfd->frag_info |= cpu_to_le64(IPG_TFI_FRAGLEN &
1964                 ((u64) (skb->len & 0xffff) << 48));
1965
1966         /* Clear the TFDDone bit last to indicate the TFD is ready
1967          * for transfer to the IPG.
1968          */
1969         txfd->tfc &= cpu_to_le64(~IPG_TFC_TFDDONE);
1970
1971         spin_lock_irqsave(&sp->lock, flags);
1972
1973         sp->tx_current++;
1974
1975         mmiowb();
1976
1977         ipg_w32(IPG_DC_TX_DMA_POLL_NOW, DMA_CTRL);
1978
1979         if (sp->tx_current == (sp->tx_dirty + IPG_TFDLIST_LENGTH))
1980                 netif_wake_queue(dev);
1981
1982         spin_unlock_irqrestore(&sp->lock, flags);
1983
1984         return NETDEV_TX_OK;
1985 }
1986
1987 static void ipg_set_phy_default_param(unsigned char rev,
1988                                       struct net_device *dev, int phy_address)
1989 {
1990         unsigned short length;
1991         unsigned char revision;
1992         unsigned short *phy_param;
1993         unsigned short address, value;
1994
1995         phy_param = &DefaultPhyParam[0];
1996         length = *phy_param & 0x00FF;
1997         revision = (unsigned char)((*phy_param) >> 8);
1998         phy_param++;
1999         while (length != 0) {
2000                 if (rev == revision) {
2001                         while (length > 1) {
2002                                 address = *phy_param;
2003                                 value = *(phy_param + 1);
2004                                 phy_param += 2;
2005                                 mdio_write(dev, phy_address, address, value);
2006                                 length -= 4;
2007                         }
2008                         break;
2009                 } else {
2010                         phy_param += length / 2;
2011                         length = *phy_param & 0x00FF;
2012                         revision = (unsigned char)((*phy_param) >> 8);
2013                         phy_param++;
2014                 }
2015         }
2016 }
2017
2018 /* JES20040127EEPROM */
2019 static int read_eeprom(struct net_device *dev, int eep_addr)
2020 {
2021         void __iomem *ioaddr = ipg_ioaddr(dev);
2022         unsigned int i;
2023         int ret = 0;
2024         u16 value;
2025
2026         value = IPG_EC_EEPROM_READOPCODE | (eep_addr & 0xff);
2027         ipg_w16(value, EEPROM_CTRL);
2028
2029         for (i = 0; i < 1000; i++) {
2030                 u16 data;
2031
2032                 mdelay(10);
2033                 data = ipg_r16(EEPROM_CTRL);
2034                 if (!(data & IPG_EC_EEPROM_BUSY)) {
2035                         ret = ipg_r16(EEPROM_DATA);
2036                         break;
2037                 }
2038         }
2039         return ret;
2040 }
2041
2042 static void ipg_init_mii(struct net_device *dev)
2043 {
2044         struct ipg_nic_private *sp = netdev_priv(dev);
2045         struct mii_if_info *mii_if = &sp->mii_if;
2046         int phyaddr;
2047
2048         mii_if->dev          = dev;
2049         mii_if->mdio_read    = mdio_read;
2050         mii_if->mdio_write   = mdio_write;
2051         mii_if->phy_id_mask  = 0x1f;
2052         mii_if->reg_num_mask = 0x1f;
2053
2054         mii_if->phy_id = phyaddr = ipg_find_phyaddr(dev);
2055
2056         if (phyaddr != 0x1f) {
2057                 u16 mii_phyctrl, mii_1000cr;
2058                 u8 revisionid = 0;
2059
2060                 mii_1000cr  = mdio_read(dev, phyaddr, MII_CTRL1000);
2061                 mii_1000cr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF |
2062                         GMII_PHY_1000BASETCONTROL_PreferMaster;
2063                 mdio_write(dev, phyaddr, MII_CTRL1000, mii_1000cr);
2064
2065                 mii_phyctrl = mdio_read(dev, phyaddr, MII_BMCR);
2066
2067                 /* Set default phyparam */
2068                 pci_read_config_byte(sp->pdev, PCI_REVISION_ID, &revisionid);
2069                 ipg_set_phy_default_param(revisionid, dev, phyaddr);
2070
2071                 /* Reset PHY */
2072                 mii_phyctrl |= BMCR_RESET | BMCR_ANRESTART;
2073                 mdio_write(dev, phyaddr, MII_BMCR, mii_phyctrl);
2074
2075         }
2076 }
2077
2078 static int ipg_hw_init(struct net_device *dev)
2079 {
2080         struct ipg_nic_private *sp = netdev_priv(dev);
2081         void __iomem *ioaddr = sp->ioaddr;
2082         unsigned int i;
2083         int rc;
2084
2085         /* Read/Write and Reset EEPROM Value Jesse20040128EEPROM_VALUE */
2086         /* Read LED Mode Configuration from EEPROM */
2087         sp->LED_Mode = read_eeprom(dev, 6);
2088
2089         /* Reset all functions within the IPG. Do not assert
2090          * RST_OUT as not compatible with some PHYs.
2091          */
2092         rc = ipg_reset(dev, IPG_RESET_MASK);
2093         if (rc < 0)
2094                 goto out;
2095
2096         ipg_init_mii(dev);
2097
2098         /* Read MAC Address from EEPROM */
2099         for (i = 0; i < 3; i++)
2100                 sp->station_addr[i] = read_eeprom(dev, 16 + i);
2101
2102         for (i = 0; i < 3; i++)
2103                 ipg_w16(sp->station_addr[i], STATION_ADDRESS_0 + 2*i);
2104
2105         /* Set station address in ethernet_device structure. */
2106         dev->dev_addr[0] =  ipg_r16(STATION_ADDRESS_0) & 0x00ff;
2107         dev->dev_addr[1] = (ipg_r16(STATION_ADDRESS_0) & 0xff00) >> 8;
2108         dev->dev_addr[2] =  ipg_r16(STATION_ADDRESS_1) & 0x00ff;
2109         dev->dev_addr[3] = (ipg_r16(STATION_ADDRESS_1) & 0xff00) >> 8;
2110         dev->dev_addr[4] =  ipg_r16(STATION_ADDRESS_2) & 0x00ff;
2111         dev->dev_addr[5] = (ipg_r16(STATION_ADDRESS_2) & 0xff00) >> 8;
2112 out:
2113         return rc;
2114 }
2115
2116 static int ipg_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2117 {
2118         struct ipg_nic_private *sp = netdev_priv(dev);
2119         int rc;
2120
2121         mutex_lock(&sp->mii_mutex);
2122         rc = generic_mii_ioctl(&sp->mii_if, if_mii(ifr), cmd, NULL);
2123         mutex_unlock(&sp->mii_mutex);
2124
2125         return rc;
2126 }
2127
2128 static int ipg_nic_change_mtu(struct net_device *dev, int new_mtu)
2129 {
2130         /* Function to accomodate changes to Maximum Transfer Unit
2131          * (or MTU) of IPG NIC. Cannot use default function since
2132          * the default will not allow for MTU > 1500 bytes.
2133          */
2134
2135         IPG_DEBUG_MSG("_nic_change_mtu\n");
2136
2137         /* Check that the new MTU value is between 68 (14 byte header, 46
2138          * byte payload, 4 byte FCS) and IPG_MAX_RXFRAME_SIZE, which
2139          * corresponds to the MAXFRAMESIZE register in the IPG.
2140          */
2141         if ((new_mtu < 68) || (new_mtu > IPG_MAX_RXFRAME_SIZE))
2142                 return -EINVAL;
2143
2144         dev->mtu = new_mtu;
2145
2146         return 0;
2147 }
2148
2149 static int ipg_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2150 {
2151         struct ipg_nic_private *sp = netdev_priv(dev);
2152         int rc;
2153
2154         mutex_lock(&sp->mii_mutex);
2155         rc = mii_ethtool_gset(&sp->mii_if, cmd);
2156         mutex_unlock(&sp->mii_mutex);
2157
2158         return rc;
2159 }
2160
2161 static int ipg_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2162 {
2163         struct ipg_nic_private *sp = netdev_priv(dev);
2164         int rc;
2165
2166         mutex_lock(&sp->mii_mutex);
2167         rc = mii_ethtool_sset(&sp->mii_if, cmd);
2168         mutex_unlock(&sp->mii_mutex);
2169
2170         return rc;
2171 }
2172
2173 static int ipg_nway_reset(struct net_device *dev)
2174 {
2175         struct ipg_nic_private *sp = netdev_priv(dev);
2176         int rc;
2177
2178         mutex_lock(&sp->mii_mutex);
2179         rc = mii_nway_restart(&sp->mii_if);
2180         mutex_unlock(&sp->mii_mutex);
2181
2182         return rc;
2183 }
2184
2185 static struct ethtool_ops ipg_ethtool_ops = {
2186         .get_settings = ipg_get_settings,
2187         .set_settings = ipg_set_settings,
2188         .nway_reset   = ipg_nway_reset,
2189 };
2190
2191 static void ipg_remove(struct pci_dev *pdev)
2192 {
2193         struct net_device *dev = pci_get_drvdata(pdev);
2194         struct ipg_nic_private *sp = netdev_priv(dev);
2195
2196         IPG_DEBUG_MSG("_remove\n");
2197
2198         /* Un-register Ethernet device. */
2199         unregister_netdev(dev);
2200
2201         pci_iounmap(pdev, sp->ioaddr);
2202
2203         pci_release_regions(pdev);
2204
2205         free_netdev(dev);
2206         pci_disable_device(pdev);
2207         pci_set_drvdata(pdev, NULL);
2208 }
2209
2210 static int __devinit ipg_probe(struct pci_dev *pdev,
2211                                const struct pci_device_id *id)
2212 {
2213         unsigned int i = id->driver_data;
2214         struct ipg_nic_private *sp;
2215         struct net_device *dev;
2216         void __iomem *ioaddr;
2217         int rc;
2218
2219         rc = pci_enable_device(pdev);
2220         if (rc < 0)
2221                 goto out;
2222
2223         printk(KERN_INFO "%s: %s\n", pci_name(pdev), ipg_brand_name[i]);
2224
2225         pci_set_master(pdev);
2226
2227         rc = pci_set_dma_mask(pdev, DMA_40BIT_MASK);
2228         if (rc < 0) {
2229                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2230                 if (rc < 0) {
2231                         printk(KERN_ERR "%s: DMA config failed.\n",
2232                                pci_name(pdev));
2233                         goto err_disable_0;
2234                 }
2235         }
2236
2237         /*
2238          * Initialize net device.
2239          */
2240         dev = alloc_etherdev(sizeof(struct ipg_nic_private));
2241         if (!dev) {
2242                 printk(KERN_ERR "%s: alloc_etherdev failed\n", pci_name(pdev));
2243                 rc = -ENOMEM;
2244                 goto err_disable_0;
2245         }
2246
2247         sp = netdev_priv(dev);
2248         spin_lock_init(&sp->lock);
2249         mutex_init(&sp->mii_mutex);
2250
2251         /* Declare IPG NIC functions for Ethernet device methods.
2252          */
2253         dev->open = &ipg_nic_open;
2254         dev->stop = &ipg_nic_stop;
2255         dev->hard_start_xmit = &ipg_nic_hard_start_xmit;
2256         dev->get_stats = &ipg_nic_get_stats;
2257         dev->set_multicast_list = &ipg_nic_set_multicast_list;
2258         dev->do_ioctl = ipg_ioctl;
2259         dev->tx_timeout = ipg_tx_timeout;
2260         dev->change_mtu = &ipg_nic_change_mtu;
2261
2262         SET_NETDEV_DEV(dev, &pdev->dev);
2263         SET_ETHTOOL_OPS(dev, &ipg_ethtool_ops);
2264
2265         rc = pci_request_regions(pdev, DRV_NAME);
2266         if (rc)
2267                 goto err_free_dev_1;
2268
2269         ioaddr = pci_iomap(pdev, 1, pci_resource_len(pdev, 1));
2270         if (!ioaddr) {
2271                 printk(KERN_ERR "%s cannot map MMIO\n", pci_name(pdev));
2272                 rc = -EIO;
2273                 goto err_release_regions_2;
2274         }
2275
2276         /* Save the pointer to the PCI device information. */
2277         sp->ioaddr = ioaddr;
2278         sp->pdev = pdev;
2279         sp->dev = dev;
2280
2281         INIT_DELAYED_WORK(&sp->task, ipg_reset_after_host_error);
2282
2283         pci_set_drvdata(pdev, dev);
2284
2285         rc = ipg_hw_init(dev);
2286         if (rc < 0)
2287                 goto err_unmap_3;
2288
2289         rc = register_netdev(dev);
2290         if (rc < 0)
2291                 goto err_unmap_3;
2292
2293         printk(KERN_INFO "Ethernet device registered as: %s\n", dev->name);
2294 out:
2295         return rc;
2296
2297 err_unmap_3:
2298         pci_iounmap(pdev, ioaddr);
2299 err_release_regions_2:
2300         pci_release_regions(pdev);
2301 err_free_dev_1:
2302         free_netdev(dev);
2303 err_disable_0:
2304         pci_disable_device(pdev);
2305         goto out;
2306 }
2307
2308 static struct pci_driver ipg_pci_driver = {
2309         .name           = IPG_DRIVER_NAME,
2310         .id_table       = ipg_pci_tbl,
2311         .probe          = ipg_probe,
2312         .remove         = __devexit_p(ipg_remove),
2313 };
2314
2315 static int __init ipg_init_module(void)
2316 {
2317         return pci_register_driver(&ipg_pci_driver);
2318 }
2319
2320 static void __exit ipg_exit_module(void)
2321 {
2322         pci_unregister_driver(&ipg_pci_driver);
2323 }
2324
2325 module_init(ipg_init_module);
2326 module_exit(ipg_exit_module);