drivers/net/forcedeth.c

   1 /*
   2  * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
   3  *
   4  * Note: This driver is a cleanroom reimplementation based on reverse
   5  *      engineered documentation written by Carl-Daniel Hailfinger
   6  *      and Andrew de Quincey. It's neither supported nor endorsed
   7  *      by NVIDIA Corp. Use at your own risk.
   8  *
   9  * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
  10  * trademarks of NVIDIA Corporation in the United States and other
  11  * countries.
  12  *
  13  * Copyright (C) 2003,4 Manfred Spraul
  14  * Copyright (C) 2004 Andrew de Quincey (wol support)
  15  * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
  16  *              IRQ rate fixes, bigendian fixes, cleanups, verification)
  17  * Copyright (c) 2004 NVIDIA Corporation
  18  *
  19  * This program is free software; you can redistribute it and/or modify
  20  * it under the terms of the GNU General Public License as published by
  21  * the Free Software Foundation; either version 2 of the License, or
  22  * (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  32  *
  33  * Changelog:
  34  *      0.01: 05 Oct 2003: First release that compiles without warnings.
  35  *      0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
  36  *                         Check all PCI BARs for the register window.
  37  *                         udelay added to mii_rw.
  38  *      0.03: 06 Oct 2003: Initialize dev->irq.
  39  *      0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
  40  *      0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
  41  *      0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
  42  *                         irq mask updated
  43  *      0.07: 14 Oct 2003: Further irq mask updates.
  44  *      0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
  45  *                         added into irq handler, NULL check for drain_ring.
  46  *      0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
  47  *                         requested interrupt sources.
  48  *      0.10: 20 Oct 2003: First cleanup for release.
  49  *      0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
  50  *                         MAC Address init fix, set_multicast cleanup.
  51  *      0.12: 23 Oct 2003: Cleanups for release.
  52  *      0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
  53  *                         Set link speed correctly. start rx before starting
  54  *                         tx (nv_start_rx sets the link speed).
  55  *      0.14: 25 Oct 2003: Nic dependant irq mask.
  56  *      0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
  57  *                         open.
  58  *      0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
  59  *                         increased to 1628 bytes.
  60  *      0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
  61  *                         the tx length.
  62  *      0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
  63  *      0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
  64  *                         addresses, really stop rx if already running
  65  *                         in nv_start_rx, clean up a bit.
  66  *      0.20: 07 Dec 2003: alloc fixes
  67  *      0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
  68  *      0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
  69  *                         on close.
  70  *      0.23: 26 Jan 2004: various small cleanups
  71  *      0.24: 27 Feb 2004: make driver even less anonymous in backtraces
  72  *      0.25: 09 Mar 2004: wol support
  73  *      0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
  74  *      0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
  75  *                         added CK804/MCP04 device IDs, code fixes
  76  *                         for registers, link status and other minor fixes.
  77  *      0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
  78  *      0.29: 31 Aug 2004: Add backup timer for link change notification.
  79  *      0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
  80  *                         into nv_close, otherwise reenabling for wol can
  81  *                         cause DMA to kfree'd memory.
  82  *      0.31: 14 Nov 2004: ethtool support for getting/setting link
  83  *                         capabilities.
  84  *      0.32: 16 Apr 2005: RX_ERROR4 handling added.
  85  *      0.33: 16 May 2005: Support for MCP51 added.
  86  *      0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
  87  *      0.35: 26 Jun 2005: Support for MCP55 added.
  88  *      0.36: 28 Jun 2005: Add jumbo frame support.
  89  *      0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
  90  *      0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
  91  *                         per-packet flags.
  92  *      0.39: 18 Jul 2005: Add 64bit descriptor support.
  93  *      0.40: 19 Jul 2005: Add support for mac address change.
  94  *      0.41: 30 Jul 2005: Write back original MAC in nv_close instead
  95  *                         of nv_remove
  96  *
  97  * Known bugs:
  98  * We suspect that on some hardware no TX done interrupts are generated.
  99  * This means recovery from netif_stop_queue only happens if the hw timer
 100  * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
 101  * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
 102  * If your hardware reliably generates tx done interrupts, then you can remove
 103  * DEV_NEED_TIMERIRQ from the driver_data flags.
 104  * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
 105  * superfluous timer interrupts from the nic.
 106  */
 107 #define FORCEDETH_VERSION               "0.41"
 108 #define DRV_NAME                        "forcedeth"
 109
 110 #include <linux/module.h>
 111 #include <linux/types.h>
 112 #include <linux/pci.h>
 113 #include <linux/interrupt.h>
 114 #include <linux/netdevice.h>
 115 #include <linux/etherdevice.h>
 116 #include <linux/delay.h>
 117 #include <linux/spinlock.h>
 118 #include <linux/ethtool.h>
 119 #include <linux/timer.h>
 120 #include <linux/skbuff.h>
 121 #include <linux/mii.h>
 122 #include <linux/random.h>
 123 #include <linux/init.h>
 124 #include <linux/if_vlan.h>
 125
 126 #include <asm/irq.h>
 127 #include <asm/io.h>
 128 #include <asm/uaccess.h>
 129 #include <asm/system.h>
 130
 131 #if 0
 132 #define dprintk                 printk
 133 #else
 134 #define dprintk(x...)           do { } while (0)
 135 #endif
 136
 137
 138 /*
 139  * Hardware access:
 140  */
 141
 142 #define DEV_NEED_TIMERIRQ       0x0001  /* set the timer irq flag in the irq mask */
 143 #define DEV_NEED_LINKTIMER      0x0002  /* poll link settings. Relies on the timer irq */
 144 #define DEV_HAS_LARGEDESC       0x0004  /* device supports jumbo frames and needs packet format 2 */
 145 #define DEV_HAS_HIGH_DMA        0x0008  /* device supports 64bit dma */
 146
 147 enum {
 148         NvRegIrqStatus = 0x000,
 149 #define NVREG_IRQSTAT_MIIEVENT  0x040
 150 #define NVREG_IRQSTAT_MASK              0x1ff
 151         NvRegIrqMask = 0x004,
 152 #define NVREG_IRQ_RX_ERROR              0x0001
 153 #define NVREG_IRQ_RX                    0x0002
 154 #define NVREG_IRQ_RX_NOBUF              0x0004
 155 #define NVREG_IRQ_TX_ERR                0x0008
 156 #define NVREG_IRQ_TX_OK                 0x0010
 157 #define NVREG_IRQ_TIMER                 0x0020
 158 #define NVREG_IRQ_LINK                  0x0040
 159 #define NVREG_IRQ_TX_ERROR              0x0080
 160 #define NVREG_IRQ_TX1                   0x0100
 161 #define NVREG_IRQMASK_WANTED            0x00df
 162
 163 #define NVREG_IRQ_UNKNOWN       (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
 164                                         NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX_ERROR| \
 165                                         NVREG_IRQ_TX1))
 166
 167         NvRegUnknownSetupReg6 = 0x008,
 168 #define NVREG_UNKSETUP6_VAL             3
 169
 170 /*
 171  * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
 172  * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
 173  */
 174         NvRegPollingInterval = 0x00c,
 175 #define NVREG_POLL_DEFAULT      970
 176         NvRegMisc1 = 0x080,
 177 #define NVREG_MISC1_HD          0x02
 178 #define NVREG_MISC1_FORCE       0x3b0f3c
 179
 180         NvRegTransmitterControl = 0x084,
 181 #define NVREG_XMITCTL_START     0x01
 182         NvRegTransmitterStatus = 0x088,
 183 #define NVREG_XMITSTAT_BUSY     0x01
 184
 185         NvRegPacketFilterFlags = 0x8c,
 186 #define NVREG_PFF_ALWAYS        0x7F0008
 187 #define NVREG_PFF_PROMISC       0x80
 188 #define NVREG_PFF_MYADDR        0x20
 189
 190         NvRegOffloadConfig = 0x90,
 191 #define NVREG_OFFLOAD_HOMEPHY   0x601
 192 #define NVREG_OFFLOAD_NORMAL    RX_NIC_BUFSIZE
 193         NvRegReceiverControl = 0x094,
 194 #define NVREG_RCVCTL_START      0x01
 195         NvRegReceiverStatus = 0x98,
 196 #define NVREG_RCVSTAT_BUSY      0x01
 197
 198         NvRegRandomSeed = 0x9c,
 199 #define NVREG_RNDSEED_MASK      0x00ff
 200 #define NVREG_RNDSEED_FORCE     0x7f00
 201 #define NVREG_RNDSEED_FORCE2    0x2d00
 202 #define NVREG_RNDSEED_FORCE3    0x7400
 203
 204         NvRegUnknownSetupReg1 = 0xA0,
 205 #define NVREG_UNKSETUP1_VAL     0x16070f
 206         NvRegUnknownSetupReg2 = 0xA4,
 207 #define NVREG_UNKSETUP2_VAL     0x16
 208         NvRegMacAddrA = 0xA8,
 209         NvRegMacAddrB = 0xAC,
 210         NvRegMulticastAddrA = 0xB0,
 211 #define NVREG_MCASTADDRA_FORCE  0x01
 212         NvRegMulticastAddrB = 0xB4,
 213         NvRegMulticastMaskA = 0xB8,
 214         NvRegMulticastMaskB = 0xBC,
 215
 216         NvRegPhyInterface = 0xC0,
 217 #define PHY_RGMII               0x10000000
 218
 219         NvRegTxRingPhysAddr = 0x100,
 220         NvRegRxRingPhysAddr = 0x104,
 221         NvRegRingSizes = 0x108,
 222 #define NVREG_RINGSZ_TXSHIFT 0
 223 #define NVREG_RINGSZ_RXSHIFT 16
 224         NvRegUnknownTransmitterReg = 0x10c,
 225         NvRegLinkSpeed = 0x110,
 226 #define NVREG_LINKSPEED_FORCE 0x10000
 227 #define NVREG_LINKSPEED_10      1000
 228 #define NVREG_LINKSPEED_100     100
 229 #define NVREG_LINKSPEED_1000    50
 230 #define NVREG_LINKSPEED_MASK    (0xFFF)
 231         NvRegUnknownSetupReg5 = 0x130,
 232 #define NVREG_UNKSETUP5_BIT31   (1<<31)
 233         NvRegUnknownSetupReg3 = 0x13c,
 234 #define NVREG_UNKSETUP3_VAL1    0x200010
 235         NvRegTxRxControl = 0x144,
 236 #define NVREG_TXRXCTL_KICK      0x0001
 237 #define NVREG_TXRXCTL_BIT1      0x0002
 238 #define NVREG_TXRXCTL_BIT2      0x0004
 239 #define NVREG_TXRXCTL_IDLE      0x0008
 240 #define NVREG_TXRXCTL_RESET     0x0010
 241 #define NVREG_TXRXCTL_RXCHECK   0x0400
 242         NvRegMIIStatus = 0x180,
 243 #define NVREG_MIISTAT_ERROR             0x0001
 244 #define NVREG_MIISTAT_LINKCHANGE        0x0008
 245 #define NVREG_MIISTAT_MASK              0x000f
 246 #define NVREG_MIISTAT_MASK2             0x000f
 247         NvRegUnknownSetupReg4 = 0x184,
 248 #define NVREG_UNKSETUP4_VAL     8
 249
 250         NvRegAdapterControl = 0x188,
 251 #define NVREG_ADAPTCTL_START    0x02
 252 #define NVREG_ADAPTCTL_LINKUP   0x04
 253 #define NVREG_ADAPTCTL_PHYVALID 0x40000
 254 #define NVREG_ADAPTCTL_RUNNING  0x100000
 255 #define NVREG_ADAPTCTL_PHYSHIFT 24
 256         NvRegMIISpeed = 0x18c,
 257 #define NVREG_MIISPEED_BIT8     (1<<8)
 258 #define NVREG_MIIDELAY  5
 259         NvRegMIIControl = 0x190,
 260 #define NVREG_MIICTL_INUSE      0x08000
 261 #define NVREG_MIICTL_WRITE      0x00400
 262 #define NVREG_MIICTL_ADDRSHIFT  5
 263         NvRegMIIData = 0x194,
 264         NvRegWakeUpFlags = 0x200,
 265 #define NVREG_WAKEUPFLAGS_VAL           0x7770
 266 #define NVREG_WAKEUPFLAGS_BUSYSHIFT     24
 267 #define NVREG_WAKEUPFLAGS_ENABLESHIFT   16
 268 #define NVREG_WAKEUPFLAGS_D3SHIFT       12
 269 #define NVREG_WAKEUPFLAGS_D2SHIFT       8
 270 #define NVREG_WAKEUPFLAGS_D1SHIFT       4
 271 #define NVREG_WAKEUPFLAGS_D0SHIFT       0
 272 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT         0x01
 273 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT      0x02
 274 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE     0x04
 275 #define NVREG_WAKEUPFLAGS_ENABLE        0x1111
 276
 277         NvRegPatternCRC = 0x204,
 278         NvRegPatternMask = 0x208,
 279         NvRegPowerCap = 0x268,
 280 #define NVREG_POWERCAP_D3SUPP   (1<<30)
 281 #define NVREG_POWERCAP_D2SUPP   (1<<26)
 282 #define NVREG_POWERCAP_D1SUPP   (1<<25)
 283         NvRegPowerState = 0x26c,
 284 #define NVREG_POWERSTATE_POWEREDUP      0x8000
 285 #define NVREG_POWERSTATE_VALID          0x0100
 286 #define NVREG_POWERSTATE_MASK           0x0003
 287 #define NVREG_POWERSTATE_D0             0x0000
 288 #define NVREG_POWERSTATE_D1             0x0001
 289 #define NVREG_POWERSTATE_D2             0x0002
 290 #define NVREG_POWERSTATE_D3             0x0003
 291 };
 292
 293 /* Big endian: should work, but is untested */
 294 struct ring_desc {
 295         u32 PacketBuffer;
 296         u32 FlagLen;
 297 };
 298
 299 struct ring_desc_ex {
 300         u32 PacketBufferHigh;
 301         u32 PacketBufferLow;
 302         u32 Reserved;
 303         u32 FlagLen;
 304 };
 305
 306 typedef union _ring_type {
 307         struct ring_desc* orig;
 308         struct ring_desc_ex* ex;
 309 } ring_type;
 310
 311 #define FLAG_MASK_V1 0xffff0000
 312 #define FLAG_MASK_V2 0xffffc000
 313 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
 314 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
 315
 316 #define NV_TX_LASTPACKET        (1<<16)
 317 #define NV_TX_RETRYERROR        (1<<19)
 318 #define NV_TX_FORCED_INTERRUPT  (1<<24)
 319 #define NV_TX_DEFERRED          (1<<26)
 320 #define NV_TX_CARRIERLOST       (1<<27)
 321 #define NV_TX_LATECOLLISION     (1<<28)
 322 #define NV_TX_UNDERFLOW         (1<<29)
 323 #define NV_TX_ERROR             (1<<30)
 324 #define NV_TX_VALID             (1<<31)
 325
 326 #define NV_TX2_LASTPACKET       (1<<29)
 327 #define NV_TX2_RETRYERROR       (1<<18)
 328 #define NV_TX2_FORCED_INTERRUPT (1<<30)
 329 #define NV_TX2_DEFERRED         (1<<25)
 330 #define NV_TX2_CARRIERLOST      (1<<26)
 331 #define NV_TX2_LATECOLLISION    (1<<27)
 332 #define NV_TX2_UNDERFLOW        (1<<28)
 333 /* error and valid are the same for both */
 334 #define NV_TX2_ERROR            (1<<30)
 335 #define NV_TX2_VALID            (1<<31)
 336
 337 #define NV_RX_DESCRIPTORVALID   (1<<16)
 338 #define NV_RX_MISSEDFRAME       (1<<17)
 339 #define NV_RX_SUBSTRACT1        (1<<18)
 340 #define NV_RX_ERROR1            (1<<23)
 341 #define NV_RX_ERROR2            (1<<24)
 342 #define NV_RX_ERROR3            (1<<25)
 343 #define NV_RX_ERROR4            (1<<26)
 344 #define NV_RX_CRCERR            (1<<27)
 345 #define NV_RX_OVERFLOW          (1<<28)
 346 #define NV_RX_FRAMINGERR        (1<<29)
 347 #define NV_RX_ERROR             (1<<30)
 348 #define NV_RX_AVAIL             (1<<31)
 349
 350 #define NV_RX2_CHECKSUMMASK     (0x1C000000)
 351 #define NV_RX2_CHECKSUMOK1      (0x10000000)
 352 #define NV_RX2_CHECKSUMOK2      (0x14000000)
 353 #define NV_RX2_CHECKSUMOK3      (0x18000000)
 354 #define NV_RX2_DESCRIPTORVALID  (1<<29)
 355 #define NV_RX2_SUBSTRACT1       (1<<25)
 356 #define NV_RX2_ERROR1           (1<<18)
 357 #define NV_RX2_ERROR2           (1<<19)
 358 #define NV_RX2_ERROR3           (1<<20)
 359 #define NV_RX2_ERROR4           (1<<21)
 360 #define NV_RX2_CRCERR           (1<<22)
 361 #define NV_RX2_OVERFLOW         (1<<23)
 362 #define NV_RX2_FRAMINGERR       (1<<24)
 363 /* error and avail are the same for both */
 364 #define NV_RX2_ERROR            (1<<30)
 365 #define NV_RX2_AVAIL            (1<<31)
 366
 367 /* Miscelaneous hardware related defines: */
 368 #define NV_PCI_REGSZ            0x270
 369
 370 /* various timeout delays: all in usec */
 371 #define NV_TXRX_RESET_DELAY     4
 372 #define NV_TXSTOP_DELAY1        10
 373 #define NV_TXSTOP_DELAY1MAX     500000
 374 #define NV_TXSTOP_DELAY2        100
 375 #define NV_RXSTOP_DELAY1        10
 376 #define NV_RXSTOP_DELAY1MAX     500000
 377 #define NV_RXSTOP_DELAY2        100
 378 #define NV_SETUP5_DELAY         5
 379 #define NV_SETUP5_DELAYMAX      50000
 380 #define NV_POWERUP_DELAY        5
 381 #define NV_POWERUP_DELAYMAX     5000
 382 #define NV_MIIBUSY_DELAY        50
 383 #define NV_MIIPHY_DELAY 10
 384 #define NV_MIIPHY_DELAYMAX      10000
 385
 386 #define NV_WAKEUPPATTERNS       5
 387 #define NV_WAKEUPMASKENTRIES    4
 388
 389 /* General driver defaults */
 390 #define NV_WATCHDOG_TIMEO       (5*HZ)
 391
 392 #define RX_RING         128
 393 #define TX_RING         64
 394 /*
 395  * If your nic mysteriously hangs then try to reduce the limits
 396  * to 1/0: It might be required to set NV_TX_LASTPACKET in the
 397  * last valid ring entry. But this would be impossible to
 398  * implement - probably a disassembly error.
 399  */
 400 #define TX_LIMIT_STOP   63
 401 #define TX_LIMIT_START  62
 402
 403 /* rx/tx mac addr + type + vlan + align + slack*/
 404 #define NV_RX_HEADERS           (64)
 405 /* even more slack. */
 406 #define NV_RX_ALLOC_PAD         (64)
 407
 408 /* maximum mtu size */
 409 #define NV_PKTLIMIT_1   ETH_DATA_LEN    /* hard limit not known */
 410 #define NV_PKTLIMIT_2   9100    /* Actual limit according to NVidia: 9202 */
 411
 412 #define OOM_REFILL      (1+HZ/20)
 413 #define POLL_WAIT       (1+HZ/100)
 414 #define LINK_TIMEOUT    (3*HZ)
 415
 416 /*
 417  * desc_ver values:
 418  * This field has two purposes:
 419  * - Newer nics uses a different ring layout. The layout is selected by
 420  *   comparing np->desc_ver with DESC_VER_xy.
 421  * - It contains bits that are forced on when writing to NvRegTxRxControl.
 422  */
 423 #define DESC_VER_1      0x0
 424 #define DESC_VER_2      (0x02100|NVREG_TXRXCTL_RXCHECK)
 425 #define DESC_VER_3      (0x02200|NVREG_TXRXCTL_RXCHECK)
 426
 427 /* PHY defines */
 428 #define PHY_OUI_MARVELL 0x5043
 429 #define PHY_OUI_CICADA  0x03f1
 430 #define PHYID1_OUI_MASK 0x03ff
 431 #define PHYID1_OUI_SHFT 6
 432 #define PHYID2_OUI_MASK 0xfc00
 433 #define PHYID2_OUI_SHFT 10
 434 #define PHY_INIT1       0x0f000
 435 #define PHY_INIT2       0x0e00
 436 #define PHY_INIT3       0x01000
 437 #define PHY_INIT4       0x0200
 438 #define PHY_INIT5       0x0004
 439 #define PHY_INIT6       0x02000
 440 #define PHY_GIGABIT     0x0100
 441
 442 #define PHY_TIMEOUT     0x1
 443 #define PHY_ERROR       0x2
 444
 445 #define PHY_100 0x1
 446 #define PHY_1000        0x2
 447 #define PHY_HALF        0x100
 448
 449 /* FIXME: MII defines that should be added to <linux/mii.h> */
 450 #define MII_1000BT_CR   0x09
 451 #define MII_1000BT_SR   0x0a
 452 #define ADVERTISE_1000FULL      0x0200
 453 #define ADVERTISE_1000HALF      0x0100
 454 #define LPA_1000FULL    0x0800
 455 #define LPA_1000HALF    0x0400
 456
 457
 458 /*
 459  * SMP locking:
 460  * All hardware access under dev->priv->lock, except the performance
 461  * critical parts:
 462  * - rx is (pseudo-) lockless: it relies on the single-threading provided
 463  *      by the arch code for interrupts.
 464  * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
 465  *      needs dev->priv->lock :-(
 466  * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
 467  */
 468
 469 /* in dev: base, irq */
 470 struct fe_priv {
 471         spinlock_t lock;
 472
 473         /* General data:
 474          * Locking: spin_lock(&np->lock); */
 475         struct net_device_stats stats;
 476         int in_shutdown;
 477         u32 linkspeed;
 478         int duplex;
 479         int autoneg;
 480         int fixed_mode;
 481         int phyaddr;
 482         int wolenabled;
 483         unsigned int phy_oui;
 484         u16 gigabit;
 485
 486         /* General data: RO fields */
 487         dma_addr_t ring_addr;
 488         struct pci_dev *pci_dev;
 489         u32 orig_mac[2];
 490         u32 irqmask;
 491         u32 desc_ver;
 492
 493         void __iomem *base;
 494
 495         /* rx specific fields.
 496          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 497          */
 498         ring_type rx_ring;
 499         unsigned int cur_rx, refill_rx;
 500         struct sk_buff *rx_skbuff[RX_RING];
 501         dma_addr_t rx_dma[RX_RING];
 502         unsigned int rx_buf_sz;
 503         unsigned int pkt_limit;
 504         struct timer_list oom_kick;
 505         struct timer_list nic_poll;
 506
 507         /* media detection workaround.
 508          * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
 509          */
 510         int need_linktimer;
 511         unsigned long link_timeout;
 512         /*
 513          * tx specific fields.
 514          */
 515         ring_type tx_ring;
 516         unsigned int next_tx, nic_tx;
 517         struct sk_buff *tx_skbuff[TX_RING];
 518         dma_addr_t tx_dma[TX_RING];
 519         u32 tx_flags;
 520 };
 521
 522 /*
 523  * Maximum number of loops until we assume that a bit in the irq mask
 524  * is stuck. Overridable with module param.
 525  */
 526 static int max_interrupt_work = 5;
 527
 528 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
 529 {
 530         return netdev_priv(dev);
 531 }
 532
 533 static inline u8 __iomem *get_hwbase(struct net_device *dev)
 534 {
 535         return get_nvpriv(dev)->base;
 536 }
 537
 538 static inline void pci_push(u8 __iomem *base)
 539 {
 540         /* force out pending posted writes */
 541         readl(base);
 542 }
 543
 544 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
 545 {
 546         return le32_to_cpu(prd->FlagLen)
 547                 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
 548 }
 549
 550 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
 551 {
 552         return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
 553 }
 554
 555 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
 556                                 int delay, int delaymax, const char *msg)
 557 {
 558         u8 __iomem *base = get_hwbase(dev);
 559
 560         pci_push(base);
 561         do {
 562                 udelay(delay);
 563                 delaymax -= delay;
 564                 if (delaymax < 0) {
 565                         if (msg)
 566                                 printk(msg);
 567                         return 1;
 568                 }
 569         } while ((readl(base + offset) & mask) != target);
 570         return 0;
 571 }
 572
 573 #define MII_READ        (-1)
 574 /* mii_rw: read/write a register on the PHY.
 575  *
 576  * Caller must guarantee serialization
 577  */
 578 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
 579 {
 580         u8 __iomem *base = get_hwbase(dev);
 581         u32 reg;
 582         int retval;
 583
 584         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
 585
 586         reg = readl(base + NvRegMIIControl);
 587         if (reg & NVREG_MIICTL_INUSE) {
 588                 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
 589                 udelay(NV_MIIBUSY_DELAY);
 590         }
 591
 592         reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
 593         if (value != MII_READ) {
 594                 writel(value, base + NvRegMIIData);
 595                 reg |= NVREG_MIICTL_WRITE;
 596         }
 597         writel(reg, base + NvRegMIIControl);
 598
 599         if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
 600                         NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
 601                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
 602                                 dev->name, miireg, addr);
 603                 retval = -1;
 604         } else if (value != MII_READ) {
 605                 /* it was a write operation - fewer failures are detectable */
 606                 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
 607                                 dev->name, value, miireg, addr);
 608                 retval = 0;
 609         } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
 610                 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
 611                                 dev->name, miireg, addr);
 612                 retval = -1;
 613         } else {
 614                 retval = readl(base + NvRegMIIData);
 615                 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
 616                                 dev->name, miireg, addr, retval);
 617         }
 618
 619         return retval;
 620 }
 621
 622 static int phy_reset(struct net_device *dev)
 623 {
 624         struct fe_priv *np = get_nvpriv(dev);
 625         u32 miicontrol;
 626         unsigned int tries = 0;
 627
 628         miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 629         miicontrol |= BMCR_RESET;
 630         if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
 631                 return -1;
 632         }
 633
 634         /* wait for 500ms */
 635         msleep(500);
 636
 637         /* must wait till reset is deasserted */
 638         while (miicontrol & BMCR_RESET) {
 639                 msleep(10);
 640                 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 641                 /* FIXME: 100 tries seem excessive */
 642                 if (tries++ > 100)
 643                         return -1;
 644         }
 645         return 0;
 646 }
 647
 648 static int phy_init(struct net_device *dev)
 649 {
 650         struct fe_priv *np = get_nvpriv(dev);
 651         u8 __iomem *base = get_hwbase(dev);
 652         u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
 653
 654         /* set advertise register */
 655         reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
 656         reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
 657         if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
 658                 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
 659                 return PHY_ERROR;
 660         }
 661
 662         /* get phy interface type */
 663         phyinterface = readl(base + NvRegPhyInterface);
 664
 665         /* see if gigabit phy */
 666         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
 667         if (mii_status & PHY_GIGABIT) {
 668                 np->gigabit = PHY_GIGABIT;
 669                 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
 670                 mii_control_1000 &= ~ADVERTISE_1000HALF;
 671                 if (phyinterface & PHY_RGMII)
 672                         mii_control_1000 |= ADVERTISE_1000FULL;
 673                 else
 674                         mii_control_1000 &= ~ADVERTISE_1000FULL;
 675
 676                 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
 677                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 678                         return PHY_ERROR;
 679                 }
 680         }
 681         else
 682                 np->gigabit = 0;
 683
 684         /* reset the phy */
 685         if (phy_reset(dev)) {
 686                 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
 687                 return PHY_ERROR;
 688         }
 689
 690         /* phy vendor specific configuration */
 691         if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
 692                 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
 693                 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
 694                 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
 695                 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
 696                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 697                         return PHY_ERROR;
 698                 }
 699                 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
 700                 phy_reserved |= PHY_INIT5;
 701                 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
 702                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 703                         return PHY_ERROR;
 704                 }
 705         }
 706         if (np->phy_oui == PHY_OUI_CICADA) {
 707                 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
 708                 phy_reserved |= PHY_INIT6;
 709                 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
 710                         printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
 711                         return PHY_ERROR;
 712                 }
 713         }
 714
 715         /* restart auto negotiation */
 716         mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
 717         mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
 718         if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
 719                 return PHY_ERROR;
 720         }
 721
 722         return 0;
 723 }
 724
 725 static void nv_start_rx(struct net_device *dev)
 726 {
 727         struct fe_priv *np = get_nvpriv(dev);
 728         u8 __iomem *base = get_hwbase(dev);
 729
 730         dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
 731         /* Already running? Stop it. */
 732         if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
 733                 writel(0, base + NvRegReceiverControl);
 734                 pci_push(base);
 735         }
 736         writel(np->linkspeed, base + NvRegLinkSpeed);
 737         pci_push(base);
 738         writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
 739         dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
 740                                 dev->name, np->duplex, np->linkspeed);
 741         pci_push(base);
 742 }
 743
 744 static void nv_stop_rx(struct net_device *dev)
 745 {
 746         u8 __iomem *base = get_hwbase(dev);
 747
 748         dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
 749         writel(0, base + NvRegReceiverControl);
 750         reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
 751                         NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
 752                         KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
 753
 754         udelay(NV_RXSTOP_DELAY2);
 755         writel(0, base + NvRegLinkSpeed);
 756 }
 757
 758 static void nv_start_tx(struct net_device *dev)
 759 {
 760         u8 __iomem *base = get_hwbase(dev);
 761
 762         dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
 763         writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
 764         pci_push(base);
 765 }
 766
 767 static void nv_stop_tx(struct net_device *dev)
 768 {
 769         u8 __iomem *base = get_hwbase(dev);
 770
 771         dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
 772         writel(0, base + NvRegTransmitterControl);
 773         reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
 774                         NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
 775                         KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
 776
 777         udelay(NV_TXSTOP_DELAY2);
 778         writel(0, base + NvRegUnknownTransmitterReg);
 779 }
 780
 781 static void nv_txrx_reset(struct net_device *dev)
 782 {
 783         struct fe_priv *np = get_nvpriv(dev);
 784         u8 __iomem *base = get_hwbase(dev);
 785
 786         dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
 787         writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver, base + NvRegTxRxControl);
 788         pci_push(base);
 789         udelay(NV_TXRX_RESET_DELAY);
 790         writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl);
 791         pci_push(base);
 792 }
 793
 794 /*
 795  * nv_get_stats: dev->get_stats function
 796  * Get latest stats value from the nic.
 797  * Called with read_lock(&dev_base_lock) held for read -
 798  * only synchronized against unregister_netdevice.
 799  */
 800 static struct net_device_stats *nv_get_stats(struct net_device *dev)
 801 {
 802         struct fe_priv *np = get_nvpriv(dev);
 803
 804         /* It seems that the nic always generates interrupts and doesn't
 805          * accumulate errors internally. Thus the current values in np->stats
 806          * are already up to date.
 807          */
 808         return &np->stats;
 809 }
 810
 811 /*
 812  * nv_alloc_rx: fill rx ring entries.
 813  * Return 1 if the allocations for the skbs failed and the
 814  * rx engine is without Available descriptors
 815  */
 816 static int nv_alloc_rx(struct net_device *dev)
 817 {
 818         struct fe_priv *np = get_nvpriv(dev);
 819         unsigned int refill_rx = np->refill_rx;
 820         int nr;
 821
 822         while (np->cur_rx != refill_rx) {
 823                 struct sk_buff *skb;
 824
 825                 nr = refill_rx % RX_RING;
 826                 if (np->rx_skbuff[nr] == NULL) {
 827
 828                         skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
 829                         if (!skb)
 830                                 break;
 831
 832                         skb->dev = dev;
 833                         np->rx_skbuff[nr] = skb;
 834                 } else {
 835                         skb = np->rx_skbuff[nr];
 836                 }
 837                 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
 838                                                 PCI_DMA_FROMDEVICE);
 839                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
 840                         np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
 841                         wmb();
 842                         np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
 843                 } else {
 844                         np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
 845                         np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
 846                         wmb();
 847                         np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
 848                 }
 849                 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
 850                                         dev->name, refill_rx);
 851                 refill_rx++;
 852         }
 853         np->refill_rx = refill_rx;
 854         if (np->cur_rx - refill_rx == RX_RING)
 855                 return 1;
 856         return 0;
 857 }
 858
 859 static void nv_do_rx_refill(unsigned long data)
 860 {
 861         struct net_device *dev = (struct net_device *) data;
 862         struct fe_priv *np = get_nvpriv(dev);
 863
 864         disable_irq(dev->irq);
 865         if (nv_alloc_rx(dev)) {
 866                 spin_lock(&np->lock);
 867                 if (!np->in_shutdown)
 868                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
 869                 spin_unlock(&np->lock);
 870         }
 871         enable_irq(dev->irq);
 872 }
 873
 874 static void nv_init_rx(struct net_device *dev)
 875 {
 876         struct fe_priv *np = get_nvpriv(dev);
 877         int i;
 878
 879         np->cur_rx = RX_RING;
 880         np->refill_rx = 0;
 881         for (i = 0; i < RX_RING; i++)
 882                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 883                         np->rx_ring.orig[i].FlagLen = 0;
 884                 else
 885                         np->rx_ring.ex[i].FlagLen = 0;
 886 }
 887
 888 static void nv_init_tx(struct net_device *dev)
 889 {
 890         struct fe_priv *np = get_nvpriv(dev);
 891         int i;
 892
 893         np->next_tx = np->nic_tx = 0;
 894         for (i = 0; i < TX_RING; i++)
 895                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 896                         np->tx_ring.orig[i].FlagLen = 0;
 897                 else
 898                         np->tx_ring.ex[i].FlagLen = 0;
 899 }
 900
 901 static int nv_init_ring(struct net_device *dev)
 902 {
 903         nv_init_tx(dev);
 904         nv_init_rx(dev);
 905         return nv_alloc_rx(dev);
 906 }
 907
 908 static void nv_drain_tx(struct net_device *dev)
 909 {
 910         struct fe_priv *np = get_nvpriv(dev);
 911         int i;
 912         for (i = 0; i < TX_RING; i++) {
 913                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 914                         np->tx_ring.orig[i].FlagLen = 0;
 915                 else
 916                         np->tx_ring.ex[i].FlagLen = 0;
 917                 if (np->tx_skbuff[i]) {
 918                         pci_unmap_single(np->pci_dev, np->tx_dma[i],
 919                                                 np->tx_skbuff[i]->len,
 920                                                 PCI_DMA_TODEVICE);
 921                         dev_kfree_skb(np->tx_skbuff[i]);
 922                         np->tx_skbuff[i] = NULL;
 923                         np->stats.tx_dropped++;
 924                 }
 925         }
 926 }
 927
 928 static void nv_drain_rx(struct net_device *dev)
 929 {
 930         struct fe_priv *np = get_nvpriv(dev);
 931         int i;
 932         for (i = 0; i < RX_RING; i++) {
 933                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 934                         np->rx_ring.orig[i].FlagLen = 0;
 935                 else
 936                         np->rx_ring.ex[i].FlagLen = 0;
 937                 wmb();
 938                 if (np->rx_skbuff[i]) {
 939                         pci_unmap_single(np->pci_dev, np->rx_dma[i],
 940                                                 np->rx_skbuff[i]->len,
 941                                                 PCI_DMA_FROMDEVICE);
 942                         dev_kfree_skb(np->rx_skbuff[i]);
 943                         np->rx_skbuff[i] = NULL;
 944                 }
 945         }
 946 }
 947
 948 static void drain_ring(struct net_device *dev)
 949 {
 950         nv_drain_tx(dev);
 951         nv_drain_rx(dev);
 952 }
 953
 954 /*
 955  * nv_start_xmit: dev->hard_start_xmit function
 956  * Called with dev->xmit_lock held.
 957  */
 958 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
 959 {
 960         struct fe_priv *np = get_nvpriv(dev);
 961         int nr = np->next_tx % TX_RING;
 962
 963         np->tx_skbuff[nr] = skb;
 964         np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data,skb->len,
 965                                         PCI_DMA_TODEVICE);
 966
 967         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 968                 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
 969         else {
 970                 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
 971                 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
 972         }
 973
 974         spin_lock_irq(&np->lock);
 975         wmb();
 976         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
 977                 np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags );
 978         else
 979                 np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags );
 980         dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission.\n",
 981                                 dev->name, np->next_tx);
 982         {
 983                 int j;
 984                 for (j=0; j<64; j++) {
 985                         if ((j%16) == 0)
 986                                 dprintk("\n%03x:", j);
 987                         dprintk(" %02x", ((unsigned char*)skb->data)[j]);
 988                 }
 989                 dprintk("\n");
 990         }
 991
 992         np->next_tx++;
 993
 994         dev->trans_start = jiffies;
 995         if (np->next_tx - np->nic_tx >= TX_LIMIT_STOP)
 996                 netif_stop_queue(dev);
 997         spin_unlock_irq(&np->lock);
 998         writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
 999         pci_push(get_hwbase(dev));
1000         return 0;
1001 }
1002
1003 /*
1004  * nv_tx_done: check for completed packets, release the skbs.
1005  *
1006  * Caller must own np->lock.
1007  */
1008 static void nv_tx_done(struct net_device *dev)
1009 {
1010         struct fe_priv *np = get_nvpriv(dev);
1011         u32 Flags;
1012         int i;
1013
1014         while (np->nic_tx != np->next_tx) {
1015                 i = np->nic_tx % TX_RING;
1016
1017                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1018                         Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1019                 else
1020                         Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1021
1022                 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1023                                         dev->name, np->nic_tx, Flags);
1024                 if (Flags & NV_TX_VALID)
1025                         break;
1026                 if (np->desc_ver == DESC_VER_1) {
1027                         if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1028                                                         NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1029                                 if (Flags & NV_TX_UNDERFLOW)
1030                                         np->stats.tx_fifo_errors++;
1031                                 if (Flags & NV_TX_CARRIERLOST)
1032                                         np->stats.tx_carrier_errors++;
1033                                 np->stats.tx_errors++;
1034                         } else {
1035                                 np->stats.tx_packets++;
1036                                 np->stats.tx_bytes += np->tx_skbuff[i]->len;
1037                         }
1038                 } else {
1039                         if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1040                                                         NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1041                                 if (Flags & NV_TX2_UNDERFLOW)
1042                                         np->stats.tx_fifo_errors++;
1043                                 if (Flags & NV_TX2_CARRIERLOST)
1044                                         np->stats.tx_carrier_errors++;
1045                                 np->stats.tx_errors++;
1046                         } else {
1047                                 np->stats.tx_packets++;
1048                                 np->stats.tx_bytes += np->tx_skbuff[i]->len;
1049                         }
1050                 }
1051                 pci_unmap_single(np->pci_dev, np->tx_dma[i],
1052                                         np->tx_skbuff[i]->len,
1053                                         PCI_DMA_TODEVICE);
1054                 dev_kfree_skb_irq(np->tx_skbuff[i]);
1055                 np->tx_skbuff[i] = NULL;
1056                 np->nic_tx++;
1057         }
1058         if (np->next_tx - np->nic_tx < TX_LIMIT_START)
1059                 netif_wake_queue(dev);
1060 }
1061
1062 /*
1063  * nv_tx_timeout: dev->tx_timeout function
1064  * Called with dev->xmit_lock held.
1065  */
1066 static void nv_tx_timeout(struct net_device *dev)
1067 {
1068         struct fe_priv *np = get_nvpriv(dev);
1069         u8 __iomem *base = get_hwbase(dev);
1070
1071         printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name,
1072                         readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
1073
1074         {
1075                 int i;
1076
1077                 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1078                                 dev->name, (unsigned long)np->ring_addr,
1079                                 np->next_tx, np->nic_tx);
1080                 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1081                 for (i=0;i<0x400;i+= 32) {
1082                         printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1083                                         i,
1084                                         readl(base + i + 0), readl(base + i + 4),
1085                                         readl(base + i + 8), readl(base + i + 12),
1086                                         readl(base + i + 16), readl(base + i + 20),
1087                                         readl(base + i + 24), readl(base + i + 28));
1088                 }
1089                 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1090                 for (i=0;i<TX_RING;i+= 4) {
1091                         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1092                                 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1093                                        i,
1094                                        le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1095                                        le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1096                                        le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1097                                        le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1098                                        le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1099                                        le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1100                                        le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1101                                        le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1102                         } else {
1103                                 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1104                                        i,
1105                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1106                                        le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1107                                        le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1108                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1109                                        le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1110                                        le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1111                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1112                                        le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1113                                        le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1114                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1115                                        le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1116                                        le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1117                         }
1118                 }
1119         }
1120
1121         spin_lock_irq(&np->lock);
1122
1123         /* 1) stop tx engine */
1124         nv_stop_tx(dev);
1125
1126         /* 2) check that the packets were not sent already: */
1127         nv_tx_done(dev);
1128
1129         /* 3) if there are dead entries: clear everything */
1130         if (np->next_tx != np->nic_tx) {
1131                 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1132                 nv_drain_tx(dev);
1133                 np->next_tx = np->nic_tx = 0;
1134                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1135                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1136                 else
1137                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1138                 netif_wake_queue(dev);
1139         }
1140
1141         /* 4) restart tx engine */
1142         nv_start_tx(dev);
1143         spin_unlock_irq(&np->lock);
1144 }
1145
1146 /*
1147  * Called when the nic notices a mismatch between the actual data len on the
1148  * wire and the len indicated in the 802 header
1149  */
1150 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1151 {
1152         int hdrlen;     /* length of the 802 header */
1153         int protolen;   /* length as stored in the proto field */
1154
1155         /* 1) calculate len according to header */
1156         if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1157                 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1158                 hdrlen = VLAN_HLEN;
1159         } else {
1160                 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1161                 hdrlen = ETH_HLEN;
1162         }
1163         dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1164                                 dev->name, datalen, protolen, hdrlen);
1165         if (protolen > ETH_DATA_LEN)
1166                 return datalen; /* Value in proto field not a len, no checks possible */
1167
1168         protolen += hdrlen;
1169         /* consistency checks: */
1170         if (datalen > ETH_ZLEN) {
1171                 if (datalen >= protolen) {
1172                         /* more data on wire than in 802 header, trim of
1173                          * additional data.
1174                          */
1175                         dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1176                                         dev->name, protolen);
1177                         return protolen;
1178                 } else {
1179                         /* less data on wire than mentioned in header.
1180                          * Discard the packet.
1181                          */
1182                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1183                                         dev->name);
1184                         return -1;
1185                 }
1186         } else {
1187                 /* short packet. Accept only if 802 values are also short */
1188                 if (protolen > ETH_ZLEN) {
1189                         dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1190                                         dev->name);
1191                         return -1;
1192                 }
1193                 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1194                                 dev->name, datalen);
1195                 return datalen;
1196         }
1197 }
1198
1199 static void nv_rx_process(struct net_device *dev)
1200 {
1201         struct fe_priv *np = get_nvpriv(dev);
1202         u32 Flags;
1203
1204         for (;;) {
1205                 struct sk_buff *skb;
1206                 int len;
1207                 int i;
1208                 if (np->cur_rx - np->refill_rx >= RX_RING)
1209                         break;  /* we scanned the whole ring - do not continue */
1210
1211                 i = np->cur_rx % RX_RING;
1212                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1213                         Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1214                         len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1215                 } else {
1216                         Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1217                         len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1218                 }
1219
1220                 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1221                                         dev->name, np->cur_rx, Flags);
1222
1223                 if (Flags & NV_RX_AVAIL)
1224                         break;  /* still owned by hardware, */
1225
1226                 /*
1227                  * the packet is for us - immediately tear down the pci mapping.
1228                  * TODO: check if a prefetch of the first cacheline improves
1229                  * the performance.
1230                  */
1231                 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1232                                 np->rx_skbuff[i]->len,
1233                                 PCI_DMA_FROMDEVICE);
1234
1235                 {
1236                         int j;
1237                         dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1238                         for (j=0; j<64; j++) {
1239                                 if ((j%16) == 0)
1240                                         dprintk("\n%03x:", j);
1241                                 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1242                         }
1243                         dprintk("\n");
1244                 }
1245                 /* look at what we actually got: */
1246                 if (np->desc_ver == DESC_VER_1) {
1247                         if (!(Flags & NV_RX_DESCRIPTORVALID))
1248                                 goto next_pkt;
1249
1250                         if (Flags & NV_RX_MISSEDFRAME) {
1251                                 np->stats.rx_missed_errors++;
1252                                 np->stats.rx_errors++;
1253                                 goto next_pkt;
1254                         }
1255                         if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1256                                 np->stats.rx_errors++;
1257                                 goto next_pkt;
1258                         }
1259                         if (Flags & NV_RX_CRCERR) {
1260                                 np->stats.rx_crc_errors++;
1261                                 np->stats.rx_errors++;
1262                                 goto next_pkt;
1263                         }
1264                         if (Flags & NV_RX_OVERFLOW) {
1265                                 np->stats.rx_over_errors++;
1266                                 np->stats.rx_errors++;
1267                                 goto next_pkt;
1268                         }
1269                         if (Flags & NV_RX_ERROR4) {
1270                                 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1271                                 if (len < 0) {
1272                                         np->stats.rx_errors++;
1273                                         goto next_pkt;
1274                                 }
1275                         }
1276                         /* framing errors are soft errors. */
1277                         if (Flags & NV_RX_FRAMINGERR) {
1278                                 if (Flags & NV_RX_SUBSTRACT1) {
1279                                         len--;
1280                                 }
1281                         }
1282                 } else {
1283                         if (!(Flags & NV_RX2_DESCRIPTORVALID))
1284                                 goto next_pkt;
1285
1286                         if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1287                                 np->stats.rx_errors++;
1288                                 goto next_pkt;
1289                         }
1290                         if (Flags & NV_RX2_CRCERR) {
1291                                 np->stats.rx_crc_errors++;
1292                                 np->stats.rx_errors++;
1293                                 goto next_pkt;
1294                         }
1295                         if (Flags & NV_RX2_OVERFLOW) {
1296                                 np->stats.rx_over_errors++;
1297                                 np->stats.rx_errors++;
1298                                 goto next_pkt;
1299                         }
1300                         if (Flags & NV_RX2_ERROR4) {
1301                                 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1302                                 if (len < 0) {
1303                                         np->stats.rx_errors++;
1304                                         goto next_pkt;
1305                                 }
1306                         }
1307                         /* framing errors are soft errors */
1308                         if (Flags & NV_RX2_FRAMINGERR) {
1309                                 if (Flags & NV_RX2_SUBSTRACT1) {
1310                                         len--;
1311                                 }
1312                         }
1313                         Flags &= NV_RX2_CHECKSUMMASK;
1314                         if (Flags == NV_RX2_CHECKSUMOK1 ||
1315                                         Flags == NV_RX2_CHECKSUMOK2 ||
1316                                         Flags == NV_RX2_CHECKSUMOK3) {
1317                                 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1318                                 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1319                         } else {
1320                                 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1321                         }
1322                 }
1323                 /* got a valid packet - forward it to the network core */
1324                 skb = np->rx_skbuff[i];
1325                 np->rx_skbuff[i] = NULL;
1326
1327                 skb_put(skb, len);
1328                 skb->protocol = eth_type_trans(skb, dev);
1329                 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1330                                         dev->name, np->cur_rx, len, skb->protocol);
1331                 netif_rx(skb);
1332                 dev->last_rx = jiffies;
1333                 np->stats.rx_packets++;
1334                 np->stats.rx_bytes += len;
1335 next_pkt:
1336                 np->cur_rx++;
1337         }
1338 }
1339
1340 static void set_bufsize(struct net_device *dev)
1341 {
1342         struct fe_priv *np = netdev_priv(dev);
1343
1344         if (dev->mtu <= ETH_DATA_LEN)
1345                 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1346         else
1347                 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1348 }
1349
1350 /*
1351  * nv_change_mtu: dev->change_mtu function
1352  * Called with dev_base_lock held for read.
1353  */
1354 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1355 {
1356         struct fe_priv *np = get_nvpriv(dev);
1357         int old_mtu;
1358
1359         if (new_mtu < 64 || new_mtu > np->pkt_limit)
1360                 return -EINVAL;
1361
1362         old_mtu = dev->mtu;
1363         dev->mtu = new_mtu;
1364
1365         /* return early if the buffer sizes will not change */
1366         if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1367                 return 0;
1368         if (old_mtu == new_mtu)
1369                 return 0;
1370
1371         /* synchronized against open : rtnl_lock() held by caller */
1372         if (netif_running(dev)) {
1373                 u8 *base = get_hwbase(dev);
1374                 /*
1375                  * It seems that the nic preloads valid ring entries into an
1376                  * internal buffer. The procedure for flushing everything is
1377                  * guessed, there is probably a simpler approach.
1378                  * Changing the MTU is a rare event, it shouldn't matter.
1379                  */
1380                 disable_irq(dev->irq);
1381                 spin_lock_bh(&dev->xmit_lock);
1382                 spin_lock(&np->lock);
1383                 /* stop engines */
1384                 nv_stop_rx(dev);
1385                 nv_stop_tx(dev);
1386                 nv_txrx_reset(dev);
1387                 /* drain rx queue */
1388                 nv_drain_rx(dev);
1389                 nv_drain_tx(dev);
1390                 /* reinit driver view of the rx queue */
1391                 nv_init_rx(dev);
1392                 nv_init_tx(dev);
1393                 /* alloc new rx buffers */
1394                 set_bufsize(dev);
1395                 if (nv_alloc_rx(dev)) {
1396                         if (!np->in_shutdown)
1397                                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1398                 }
1399                 /* reinit nic view of the rx queue */
1400                 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1401                 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1402                 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1403                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1404                 else
1405                         writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1406                 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1407                         base + NvRegRingSizes);
1408                 pci_push(base);
1409                 writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
1410                 pci_push(base);
1411
1412                 /* restart rx engine */
1413                 nv_start_rx(dev);
1414                 nv_start_tx(dev);
1415                 spin_unlock(&np->lock);
1416                 spin_unlock_bh(&dev->xmit_lock);
1417                 enable_irq(dev->irq);
1418         }
1419         return 0;
1420 }
1421
1422 static void nv_copy_mac_to_hw(struct net_device *dev)
1423 {
1424         u8 *base = get_hwbase(dev);
1425         u32 mac[2];
1426
1427         mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1428                         (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1429         mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1430
1431         writel(mac[0], base + NvRegMacAddrA);
1432         writel(mac[1], base + NvRegMacAddrB);
1433 }
1434
1435 /*
1436  * nv_set_mac_address: dev->set_mac_address function
1437  * Called with rtnl_lock() held.
1438  */
1439 static int nv_set_mac_address(struct net_device *dev, void *addr)
1440 {
1441         struct fe_priv *np = get_nvpriv(dev);
1442         struct sockaddr *macaddr = (struct sockaddr*)addr;
1443
1444         if(!is_valid_ether_addr(macaddr->sa_data))
1445                 return -EADDRNOTAVAIL;
1446
1447         /* synchronized against open : rtnl_lock() held by caller */
1448         memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1449
1450         if (netif_running(dev)) {
1451                 spin_lock_bh(&dev->xmit_lock);
1452                 spin_lock_irq(&np->lock);
1453
1454                 /* stop rx engine */
1455                 nv_stop_rx(dev);
1456
1457                 /* set mac address */
1458                 nv_copy_mac_to_hw(dev);
1459
1460                 /* restart rx engine */
1461                 nv_start_rx(dev);
1462                 spin_unlock_irq(&np->lock);
1463                 spin_unlock_bh(&dev->xmit_lock);
1464         } else {
1465                 nv_copy_mac_to_hw(dev);
1466         }
1467         return 0;
1468 }
1469
1470 /*
1471  * nv_set_multicast: dev->set_multicast function
1472  * Called with dev->xmit_lock held.
1473  */
1474 static void nv_set_multicast(struct net_device *dev)
1475 {
1476         struct fe_priv *np = get_nvpriv(dev);
1477         u8 __iomem *base = get_hwbase(dev);
1478         u32 addr[2];
1479         u32 mask[2];
1480         u32 pff;
1481
1482         memset(addr, 0, sizeof(addr));
1483         memset(mask, 0, sizeof(mask));
1484
1485         if (dev->flags & IFF_PROMISC) {
1486                 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1487                 pff = NVREG_PFF_PROMISC;
1488         } else {
1489                 pff = NVREG_PFF_MYADDR;
1490
1491                 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1492                         u32 alwaysOff[2];
1493                         u32 alwaysOn[2];
1494
1495                         alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1496                         if (dev->flags & IFF_ALLMULTI) {
1497                                 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1498                         } else {
1499                                 struct dev_mc_list *walk;
1500
1501                                 walk = dev->mc_list;
1502                                 while (walk != NULL) {
1503                                         u32 a, b;
1504                                         a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1505                                         b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1506                                         alwaysOn[0] &= a;
1507                                         alwaysOff[0] &= ~a;
1508                                         alwaysOn[1] &= b;
1509                                         alwaysOff[1] &= ~b;
1510                                         walk = walk->next;
1511                                 }
1512                         }
1513                         addr[0] = alwaysOn[0];
1514                         addr[1] = alwaysOn[1];
1515                         mask[0] = alwaysOn[0] | alwaysOff[0];
1516                         mask[1] = alwaysOn[1] | alwaysOff[1];
1517                 }
1518         }
1519         addr[0] |= NVREG_MCASTADDRA_FORCE;
1520         pff |= NVREG_PFF_ALWAYS;
1521         spin_lock_irq(&np->lock);
1522         nv_stop_rx(dev);
1523         writel(addr[0], base + NvRegMulticastAddrA);
1524         writel(addr[1], base + NvRegMulticastAddrB);
1525         writel(mask[0], base + NvRegMulticastMaskA);
1526         writel(mask[1], base + NvRegMulticastMaskB);
1527         writel(pff, base + NvRegPacketFilterFlags);
1528         dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1529                 dev->name);
1530         nv_start_rx(dev);
1531         spin_unlock_irq(&np->lock);
1532 }
1533
1534 static int nv_update_linkspeed(struct net_device *dev)
1535 {
1536         struct fe_priv *np = get_nvpriv(dev);
1537         u8 __iomem *base = get_hwbase(dev);
1538         int adv, lpa;
1539         int newls = np->linkspeed;
1540         int newdup = np->duplex;
1541         int mii_status;
1542         int retval = 0;
1543         u32 control_1000, status_1000, phyreg;
1544
1545         /* BMSR_LSTATUS is latched, read it twice:
1546          * we want the current value.
1547          */
1548         mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1549         mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1550
1551         if (!(mii_status & BMSR_LSTATUS)) {
1552                 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1553                                 dev->name);
1554                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1555                 newdup = 0;
1556                 retval = 0;
1557                 goto set_speed;
1558         }
1559
1560         if (np->autoneg == 0) {
1561                 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1562                                 dev->name, np->fixed_mode);
1563                 if (np->fixed_mode & LPA_100FULL) {
1564                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1565                         newdup = 1;
1566                 } else if (np->fixed_mode & LPA_100HALF) {
1567                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1568                         newdup = 0;
1569                 } else if (np->fixed_mode & LPA_10FULL) {
1570                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1571                         newdup = 1;
1572                 } else {
1573                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1574                         newdup = 0;
1575                 }
1576                 retval = 1;
1577                 goto set_speed;
1578         }
1579         /* check auto negotiation is complete */
1580         if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1581                 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1582                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1583                 newdup = 0;
1584                 retval = 0;
1585                 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1586                 goto set_speed;
1587         }
1588
1589         retval = 1;
1590         if (np->gigabit == PHY_GIGABIT) {
1591                 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1592                 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1593
1594                 if ((control_1000 & ADVERTISE_1000FULL) &&
1595                         (status_1000 & LPA_1000FULL)) {
1596                         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1597                                 dev->name);
1598                         newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1599                         newdup = 1;
1600                         goto set_speed;
1601                 }
1602         }
1603
1604         adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1605         lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1606         dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1607                                 dev->name, adv, lpa);
1608
1609         /* FIXME: handle parallel detection properly */
1610         lpa = lpa & adv;
1611         if (lpa & LPA_100FULL) {
1612                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1613                 newdup = 1;
1614         } else if (lpa & LPA_100HALF) {
1615                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1616                 newdup = 0;
1617         } else if (lpa & LPA_10FULL) {
1618                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1619                 newdup = 1;
1620         } else if (lpa & LPA_10HALF) {
1621                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1622                 newdup = 0;
1623         } else {
1624                 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1625                 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1626                 newdup = 0;
1627         }
1628
1629 set_speed:
1630         if (np->duplex == newdup && np->linkspeed == newls)
1631                 return retval;
1632
1633         dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1634                         dev->name, np->linkspeed, np->duplex, newls, newdup);
1635
1636         np->duplex = newdup;
1637         np->linkspeed = newls;
1638
1639         if (np->gigabit == PHY_GIGABIT) {
1640                 phyreg = readl(base + NvRegRandomSeed);
1641                 phyreg &= ~(0x3FF00);
1642                 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1643                         phyreg |= NVREG_RNDSEED_FORCE3;
1644                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1645                         phyreg |= NVREG_RNDSEED_FORCE2;
1646                 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1647                         phyreg |= NVREG_RNDSEED_FORCE;
1648                 writel(phyreg, base + NvRegRandomSeed);
1649         }
1650
1651         phyreg = readl(base + NvRegPhyInterface);
1652         phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1653         if (np->duplex == 0)
1654                 phyreg |= PHY_HALF;
1655         if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
1656                 phyreg |= PHY_100;
1657         else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
1658                 phyreg |= PHY_1000;
1659         writel(phyreg, base + NvRegPhyInterface);
1660
1661         writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1662                 base + NvRegMisc1);
1663         pci_push(base);
1664         writel(np->linkspeed, base + NvRegLinkSpeed);
1665         pci_push(base);
1666
1667         return retval;
1668 }
1669
1670 static void nv_linkchange(struct net_device *dev)
1671 {
1672         if (nv_update_linkspeed(dev)) {
1673                 if (netif_carrier_ok(dev)) {
1674                         nv_stop_rx(dev);
1675                 } else {
1676                         netif_carrier_on(dev);
1677                         printk(KERN_INFO "%s: link up.\n", dev->name);
1678                 }
1679                 nv_start_rx(dev);
1680         } else {
1681                 if (netif_carrier_ok(dev)) {
1682                         netif_carrier_off(dev);
1683                         printk(KERN_INFO "%s: link down.\n", dev->name);
1684                         nv_stop_rx(dev);
1685                 }
1686         }
1687 }
1688
1689 static void nv_link_irq(struct net_device *dev)
1690 {
1691         u8 __iomem *base = get_hwbase(dev);
1692         u32 miistat;
1693
1694         miistat = readl(base + NvRegMIIStatus);
1695         writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1696         dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1697
1698         if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1699                 nv_linkchange(dev);
1700         dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1701 }
1702
1703 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1704 {
1705         struct net_device *dev = (struct net_device *) data;
1706         struct fe_priv *np = get_nvpriv(dev);
1707         u8 __iomem *base = get_hwbase(dev);
1708         u32 events;
1709         int i;
1710
1711         dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1712
1713         for (i=0; ; i++) {
1714                 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1715                 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1716                 pci_push(base);
1717                 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1718                 if (!(events & np->irqmask))
1719                         break;
1720
1721                 if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_ERROR|NVREG_IRQ_TX_ERR)) {
1722                         spin_lock(&np->lock);
1723                         nv_tx_done(dev);
1724                         spin_unlock(&np->lock);
1725                 }
1726
1727                 if (events & (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)) {
1728                         nv_rx_process(dev);
1729                         if (nv_alloc_rx(dev)) {
1730                                 spin_lock(&np->lock);
1731                                 if (!np->in_shutdown)
1732                                         mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1733                                 spin_unlock(&np->lock);
1734                         }
1735                 }
1736
1737                 if (events & NVREG_IRQ_LINK) {
1738                         spin_lock(&np->lock);
1739                         nv_link_irq(dev);
1740                         spin_unlock(&np->lock);
1741                 }
1742                 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1743                         spin_lock(&np->lock);
1744                         nv_linkchange(dev);
1745                         spin_unlock(&np->lock);
1746                         np->link_timeout = jiffies + LINK_TIMEOUT;
1747                 }
1748                 if (events & (NVREG_IRQ_TX_ERR)) {
1749                         dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1750                                                 dev->name, events);
1751                 }
1752                 if (events & (NVREG_IRQ_UNKNOWN)) {
1753                         printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1754                                                 dev->name, events);
1755                 }
1756                 if (i > max_interrupt_work) {
1757                         spin_lock(&np->lock);
1758                         /* disable interrupts on the nic */
1759                         writel(0, base + NvRegIrqMask);
1760                         pci_push(base);
1761
1762                         if (!np->in_shutdown)
1763                                 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1764                         printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1765                         spin_unlock(&np->lock);
1766                         break;
1767                 }
1768
1769         }
1770         dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1771
1772         return IRQ_RETVAL(i);
1773 }
1774
1775 static void nv_do_nic_poll(unsigned long data)
1776 {
1777         struct net_device *dev = (struct net_device *) data;
1778         struct fe_priv *np = get_nvpriv(dev);
1779         u8 __iomem *base = get_hwbase(dev);
1780
1781         disable_irq(dev->irq);
1782         /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1783         /*
1784          * reenable interrupts on the nic, we have to do this before calling
1785          * nv_nic_irq because that may decide to do otherwise
1786          */
1787         writel(np->irqmask, base + NvRegIrqMask);
1788         pci_push(base);
1789         nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1790         enable_irq(dev->irq);
1791 }
1792
1793 #ifdef CONFIG_NET_POLL_CONTROLLER
1794 static void nv_poll_controller(struct net_device *dev)
1795 {
1796         nv_do_nic_poll((unsigned long) dev);
1797 }
1798 #endif
1799
1800 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1801 {
1802         struct fe_priv *np = get_nvpriv(dev);
1803         strcpy(info->driver, "forcedeth");
1804         strcpy(info->version, FORCEDETH_VERSION);
1805         strcpy(info->bus_info, pci_name(np->pci_dev));
1806 }
1807
1808 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1809 {
1810         struct fe_priv *np = get_nvpriv(dev);
1811         wolinfo->supported = WAKE_MAGIC;
1812
1813         spin_lock_irq(&np->lock);
1814         if (np->wolenabled)
1815                 wolinfo->wolopts = WAKE_MAGIC;
1816         spin_unlock_irq(&np->lock);
1817 }
1818
1819 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1820 {
1821         struct fe_priv *np = get_nvpriv(dev);
1822         u8 __iomem *base = get_hwbase(dev);
1823
1824         spin_lock_irq(&np->lock);
1825         if (wolinfo->wolopts == 0) {
1826                 writel(0, base + NvRegWakeUpFlags);
1827                 np->wolenabled = 0;
1828         }
1829         if (wolinfo->wolopts & WAKE_MAGIC) {
1830                 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
1831                 np->wolenabled = 1;
1832         }
1833         spin_unlock_irq(&np->lock);
1834         return 0;
1835 }
1836
1837 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1838 {
1839         struct fe_priv *np = netdev_priv(dev);
1840         int adv;
1841
1842         spin_lock_irq(&np->lock);
1843         ecmd->port = PORT_MII;
1844         if (!netif_running(dev)) {
1845                 /* We do not track link speed / duplex setting if the
1846                  * interface is disabled. Force a link check */
1847                 nv_update_linkspeed(dev);
1848         }
1849         switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
1850                 case NVREG_LINKSPEED_10:
1851                         ecmd->speed = SPEED_10;
1852                         break;
1853                 case NVREG_LINKSPEED_100:
1854                         ecmd->speed = SPEED_100;
1855                         break;
1856                 case NVREG_LINKSPEED_1000:
1857                         ecmd->speed = SPEED_1000;
1858                         break;
1859         }
1860         ecmd->duplex = DUPLEX_HALF;
1861         if (np->duplex)
1862                 ecmd->duplex = DUPLEX_FULL;
1863
1864         ecmd->autoneg = np->autoneg;
1865
1866         ecmd->advertising = ADVERTISED_MII;
1867         if (np->autoneg) {
1868                 ecmd->advertising |= ADVERTISED_Autoneg;
1869                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1870         } else {
1871                 adv = np->fixed_mode;
1872         }
1873         if (adv & ADVERTISE_10HALF)
1874                 ecmd->advertising |= ADVERTISED_10baseT_Half;
1875         if (adv & ADVERTISE_10FULL)
1876                 ecmd->advertising |= ADVERTISED_10baseT_Full;
1877         if (adv & ADVERTISE_100HALF)
1878                 ecmd->advertising |= ADVERTISED_100baseT_Half;
1879         if (adv & ADVERTISE_100FULL)
1880                 ecmd->advertising |= ADVERTISED_100baseT_Full;
1881         if (np->autoneg && np->gigabit == PHY_GIGABIT) {
1882                 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1883                 if (adv & ADVERTISE_1000FULL)
1884                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
1885         }
1886
1887         ecmd->supported = (SUPPORTED_Autoneg |
1888                 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
1889                 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1890                 SUPPORTED_MII);
1891         if (np->gigabit == PHY_GIGABIT)
1892                 ecmd->supported |= SUPPORTED_1000baseT_Full;
1893
1894         ecmd->phy_address = np->phyaddr;
1895         ecmd->transceiver = XCVR_EXTERNAL;
1896
1897         /* ignore maxtxpkt, maxrxpkt for now */
1898         spin_unlock_irq(&np->lock);
1899         return 0;
1900 }
1901
1902 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1903 {
1904         struct fe_priv *np = netdev_priv(dev);
1905
1906         if (ecmd->port != PORT_MII)
1907                 return -EINVAL;
1908         if (ecmd->transceiver != XCVR_EXTERNAL)
1909                 return -EINVAL;
1910         if (ecmd->phy_address != np->phyaddr) {
1911                 /* TODO: support switching between multiple phys. Should be
1912                  * trivial, but not enabled due to lack of test hardware. */
1913                 return -EINVAL;
1914         }
1915         if (ecmd->autoneg == AUTONEG_ENABLE) {
1916                 u32 mask;
1917
1918                 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1919                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
1920                 if (np->gigabit == PHY_GIGABIT)
1921                         mask |= ADVERTISED_1000baseT_Full;
1922
1923                 if ((ecmd->advertising & mask) == 0)
1924                         return -EINVAL;
1925
1926         } else if (ecmd->autoneg == AUTONEG_DISABLE) {
1927                 /* Note: autonegotiation disable, speed 1000 intentionally
1928                  * forbidden - noone should need that. */
1929
1930                 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
1931                         return -EINVAL;
1932                 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
1933                         return -EINVAL;
1934         } else {
1935                 return -EINVAL;
1936         }
1937
1938         spin_lock_irq(&np->lock);
1939         if (ecmd->autoneg == AUTONEG_ENABLE) {
1940                 int adv, bmcr;
1941
1942                 np->autoneg = 1;
1943
1944                 /* advertise only what has been requested */
1945                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1946                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1947                 if (ecmd->advertising & ADVERTISED_10baseT_Half)
1948                         adv |= ADVERTISE_10HALF;
1949                 if (ecmd->advertising & ADVERTISED_10baseT_Full)
1950                         adv |= ADVERTISE_10FULL;
1951                 if (ecmd->advertising & ADVERTISED_100baseT_Half)
1952                         adv |= ADVERTISE_100HALF;
1953                 if (ecmd->advertising & ADVERTISED_100baseT_Full)
1954                         adv |= ADVERTISE_100FULL;
1955                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
1956
1957                 if (np->gigabit == PHY_GIGABIT) {
1958                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1959                         adv &= ~ADVERTISE_1000FULL;
1960                         if (ecmd->advertising & ADVERTISED_1000baseT_Full)
1961                                 adv |= ADVERTISE_1000FULL;
1962                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
1963                 }
1964
1965                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1966                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1967                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
1968
1969         } else {
1970                 int adv, bmcr;
1971
1972                 np->autoneg = 0;
1973
1974                 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1975                 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
1976                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
1977                         adv |= ADVERTISE_10HALF;
1978                 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
1979                         adv |= ADVERTISE_10FULL;
1980                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
1981                         adv |= ADVERTISE_100HALF;
1982                 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
1983                         adv |= ADVERTISE_100FULL;
1984                 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
1985                 np->fixed_mode = adv;
1986
1987                 if (np->gigabit == PHY_GIGABIT) {
1988                         adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1989                         adv &= ~ADVERTISE_1000FULL;
1990                         mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
1991                 }
1992
1993                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1994                 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX);
1995                 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL))
1996                         bmcr |= BMCR_FULLDPLX;
1997                 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL))
1998                         bmcr |= BMCR_SPEED100;
1999                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2000
2001                 if (netif_running(dev)) {
2002                         /* Wait a bit and then reconfigure the nic. */
2003                         udelay(10);
2004                         nv_linkchange(dev);
2005                 }
2006         }
2007         spin_unlock_irq(&np->lock);
2008
2009         return 0;
2010 }
2011
2012 #define FORCEDETH_REGS_VER      1
2013 #define FORCEDETH_REGS_SIZE     0x400 /* 256 32-bit registers */
2014
2015 static int nv_get_regs_len(struct net_device *dev)
2016 {
2017         return FORCEDETH_REGS_SIZE;
2018 }
2019
2020 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2021 {
2022         struct fe_priv *np = get_nvpriv(dev);
2023         u8 __iomem *base = get_hwbase(dev);
2024         u32 *rbuf = buf;
2025         int i;
2026
2027         regs->version = FORCEDETH_REGS_VER;
2028         spin_lock_irq(&np->lock);
2029         for (i=0;i<FORCEDETH_REGS_SIZE/sizeof(u32);i++)
2030                 rbuf[i] = readl(base + i*sizeof(u32));
2031         spin_unlock_irq(&np->lock);
2032 }
2033
2034 static int nv_nway_reset(struct net_device *dev)
2035 {
2036         struct fe_priv *np = get_nvpriv(dev);
2037         int ret;
2038
2039         spin_lock_irq(&np->lock);
2040         if (np->autoneg) {
2041                 int bmcr;
2042
2043                 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2044                 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2045                 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2046
2047                 ret = 0;
2048         } else {
2049                 ret = -EINVAL;
2050         }
2051         spin_unlock_irq(&np->lock);
2052
2053         return ret;
2054 }
2055
2056 static struct ethtool_ops ops = {
2057         .get_drvinfo = nv_get_drvinfo,
2058         .get_link = ethtool_op_get_link,
2059         .get_wol = nv_get_wol,
2060         .set_wol = nv_set_wol,
2061         .get_settings = nv_get_settings,
2062         .set_settings = nv_set_settings,
2063         .get_regs_len = nv_get_regs_len,
2064         .get_regs = nv_get_regs,
2065         .nway_reset = nv_nway_reset,
2066 };
2067
2068 static int nv_open(struct net_device *dev)
2069 {
2070         struct fe_priv *np = get_nvpriv(dev);
2071         u8 __iomem *base = get_hwbase(dev);
2072         int ret, oom, i;
2073
2074         dprintk(KERN_DEBUG "nv_open: begin\n");
2075
2076         /* 1) erase previous misconfiguration */
2077         /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
2078         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2079         writel(0, base + NvRegMulticastAddrB);
2080         writel(0, base + NvRegMulticastMaskA);
2081         writel(0, base + NvRegMulticastMaskB);
2082         writel(0, base + NvRegPacketFilterFlags);
2083
2084         writel(0, base + NvRegTransmitterControl);
2085         writel(0, base + NvRegReceiverControl);
2086
2087         writel(0, base + NvRegAdapterControl);
2088
2089         /* 2) initialize descriptor rings */
2090         set_bufsize(dev);
2091         oom = nv_init_ring(dev);
2092
2093         writel(0, base + NvRegLinkSpeed);
2094         writel(0, base + NvRegUnknownTransmitterReg);
2095         nv_txrx_reset(dev);
2096         writel(0, base + NvRegUnknownSetupReg6);
2097
2098         np->in_shutdown = 0;
2099
2100         /* 3) set mac address */
2101         nv_copy_mac_to_hw(dev);
2102
2103         /* 4) give hw rings */
2104         writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
2105         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2106                 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
2107         else
2108                 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
2109         writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
2110                 base + NvRegRingSizes);
2111
2112         /* 5) continue setup */
2113         writel(np->linkspeed, base + NvRegLinkSpeed);
2114         writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
2115         writel(np->desc_ver, base + NvRegTxRxControl);
2116         pci_push(base);
2117         writel(NVREG_TXRXCTL_BIT1|np->desc_ver, base + NvRegTxRxControl);
2118         reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
2119                         NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
2120                         KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
2121
2122         writel(0, base + NvRegUnknownSetupReg4);
2123         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2124         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2125
2126         /* 6) continue setup */
2127         writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
2128         writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
2129         writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
2130         writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2131
2132         writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
2133         get_random_bytes(&i, sizeof(i));
2134         writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
2135         writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
2136         writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
2137         writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
2138         writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
2139         writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
2140                         base + NvRegAdapterControl);
2141         writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
2142         writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
2143         writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
2144
2145         i = readl(base + NvRegPowerState);
2146         if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
2147                 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
2148
2149         pci_push(base);
2150         udelay(10);
2151         writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
2152
2153         writel(0, base + NvRegIrqMask);
2154         pci_push(base);
2155         writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2156         writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2157         pci_push(base);
2158
2159         ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
2160         if (ret)
2161                 goto out_drain;
2162
2163         /* ask for interrupts */
2164         writel(np->irqmask, base + NvRegIrqMask);
2165
2166         spin_lock_irq(&np->lock);
2167         writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2168         writel(0, base + NvRegMulticastAddrB);
2169         writel(0, base + NvRegMulticastMaskA);
2170         writel(0, base + NvRegMulticastMaskB);
2171         writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
2172         /* One manual link speed update: Interrupts are enabled, future link
2173          * speed changes cause interrupts and are handled by nv_link_irq().
2174          */
2175         {
2176                 u32 miistat;
2177                 miistat = readl(base + NvRegMIIStatus);
2178                 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2179                 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
2180         }
2181         ret = nv_update_linkspeed(dev);
2182         nv_start_rx(dev);
2183         nv_start_tx(dev);
2184         netif_start_queue(dev);
2185         if (ret) {
2186                 netif_carrier_on(dev);
2187         } else {
2188                 printk("%s: no link during initialization.\n", dev->name);
2189                 netif_carrier_off(dev);
2190         }
2191         if (oom)
2192                 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2193         spin_unlock_irq(&np->lock);
2194
2195         return 0;
2196 out_drain:
2197         drain_ring(dev);
2198         return ret;
2199 }
2200
2201 static int nv_close(struct net_device *dev)
2202 {
2203         struct fe_priv *np = get_nvpriv(dev);
2204         u8 __iomem *base;
2205
2206         spin_lock_irq(&np->lock);
2207         np->in_shutdown = 1;
2208         spin_unlock_irq(&np->lock);
2209         synchronize_irq(dev->irq);
2210
2211         del_timer_sync(&np->oom_kick);
2212         del_timer_sync(&np->nic_poll);
2213
2214         netif_stop_queue(dev);
2215         spin_lock_irq(&np->lock);
2216         nv_stop_tx(dev);
2217         nv_stop_rx(dev);
2218         nv_txrx_reset(dev);
2219
2220         /* disable interrupts on the nic or we will lock up */
2221         base = get_hwbase(dev);
2222         writel(0, base + NvRegIrqMask);
2223         pci_push(base);
2224         dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
2225
2226         spin_unlock_irq(&np->lock);
2227
2228         free_irq(dev->irq, dev);
2229
2230         drain_ring(dev);
2231
2232         if (np->wolenabled)
2233                 nv_start_rx(dev);
2234
2235         /* special op: write back the misordered MAC address - otherwise
2236          * the next nv_probe would see a wrong address.
2237          */
2238         writel(np->orig_mac[0], base + NvRegMacAddrA);
2239         writel(np->orig_mac[1], base + NvRegMacAddrB);
2240
2241         /* FIXME: power down nic */
2242
2243         return 0;
2244 }
2245
2246 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
2247 {
2248         struct net_device *dev;
2249         struct fe_priv *np;
2250         unsigned long addr;
2251         u8 __iomem *base;
2252         int err, i;
2253
2254         dev = alloc_etherdev(sizeof(struct fe_priv));
2255         err = -ENOMEM;
2256         if (!dev)
2257                 goto out;
2258
2259         np = get_nvpriv(dev);
2260         np->pci_dev = pci_dev;
2261         spin_lock_init(&np->lock);
2262         SET_MODULE_OWNER(dev);
2263         SET_NETDEV_DEV(dev, &pci_dev->dev);
2264
2265         init_timer(&np->oom_kick);
2266         np->oom_kick.data = (unsigned long) dev;
2267         np->oom_kick.function = &nv_do_rx_refill;       /* timer handler */
2268         init_timer(&np->nic_poll);
2269         np->nic_poll.data = (unsigned long) dev;
2270         np->nic_poll.function = &nv_do_nic_poll;        /* timer handler */
2271
2272         err = pci_enable_device(pci_dev);
2273         if (err) {
2274                 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
2275                                 err, pci_name(pci_dev));
2276                 goto out_free;
2277         }
2278
2279         pci_set_master(pci_dev);
2280
2281         err = pci_request_regions(pci_dev, DRV_NAME);
2282         if (err < 0)
2283                 goto out_disable;
2284
2285         err = -EINVAL;
2286         addr = 0;
2287         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2288                 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
2289                                 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
2290                                 pci_resource_len(pci_dev, i),
2291                                 pci_resource_flags(pci_dev, i));
2292                 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
2293                                 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
2294                         addr = pci_resource_start(pci_dev, i);
2295                         break;
2296                 }
2297         }
2298         if (i == DEVICE_COUNT_RESOURCE) {
2299                 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
2300                                         pci_name(pci_dev));
2301                 goto out_relreg;
2302         }
2303
2304         /* handle different descriptor versions */
2305         if (id->driver_data & DEV_HAS_HIGH_DMA) {
2306                 /* packet format 3: supports 40-bit addressing */
2307                 np->desc_ver = DESC_VER_3;
2308                 if (pci_set_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
2309                         printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
2310                                         pci_name(pci_dev));
2311                 }
2312         } else if (id->driver_data & DEV_HAS_LARGEDESC) {
2313                 /* packet format 2: supports jumbo frames */
2314                 np->desc_ver = DESC_VER_2;
2315         } else {
2316                 /* original packet format */
2317                 np->desc_ver = DESC_VER_1;
2318         }
2319
2320         np->pkt_limit = NV_PKTLIMIT_1;
2321         if (id->driver_data & DEV_HAS_LARGEDESC)
2322                 np->pkt_limit = NV_PKTLIMIT_2;
2323
2324         err = -ENOMEM;
2325         np->base = ioremap(addr, NV_PCI_REGSZ);
2326         if (!np->base)
2327                 goto out_relreg;
2328         dev->base_addr = (unsigned long)np->base;
2329
2330         dev->irq = pci_dev->irq;
2331
2332         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2333                 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
2334                                         sizeof(struct ring_desc) * (RX_RING + TX_RING),
2335                                         &np->ring_addr);
2336                 if (!np->rx_ring.orig)
2337                         goto out_unmap;
2338                 np->tx_ring.orig = &np->rx_ring.orig[RX_RING];
2339         } else {
2340                 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
2341                                         sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2342                                         &np->ring_addr);
2343                 if (!np->rx_ring.ex)
2344                         goto out_unmap;
2345                 np->tx_ring.ex = &np->rx_ring.ex[RX_RING];
2346         }
2347
2348         dev->open = nv_open;
2349         dev->stop = nv_close;
2350         dev->hard_start_xmit = nv_start_xmit;
2351         dev->get_stats = nv_get_stats;
2352         dev->change_mtu = nv_change_mtu;
2353         dev->set_mac_address = nv_set_mac_address;
2354         dev->set_multicast_list = nv_set_multicast;
2355 #ifdef CONFIG_NET_POLL_CONTROLLER
2356         dev->poll_controller = nv_poll_controller;
2357 #endif
2358         SET_ETHTOOL_OPS(dev, &ops);
2359         dev->tx_timeout = nv_tx_timeout;
2360         dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
2361
2362         pci_set_drvdata(pci_dev, dev);
2363
2364         /* read the mac address */
2365         base = get_hwbase(dev);
2366         np->orig_mac[0] = readl(base + NvRegMacAddrA);
2367         np->orig_mac[1] = readl(base + NvRegMacAddrB);
2368
2369         dev->dev_addr[0] = (np->orig_mac[1] >>  8) & 0xff;
2370         dev->dev_addr[1] = (np->orig_mac[1] >>  0) & 0xff;
2371         dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
2372         dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
2373         dev->dev_addr[4] = (np->orig_mac[0] >>  8) & 0xff;
2374         dev->dev_addr[5] = (np->orig_mac[0] >>  0) & 0xff;
2375
2376         if (!is_valid_ether_addr(dev->dev_addr)) {
2377                 /*
2378                  * Bad mac address. At least one bios sets the mac address
2379                  * to 01:23:45:67:89:ab
2380                  */
2381                 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2382                         pci_name(pci_dev),
2383                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2384                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2385                 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
2386                 dev->dev_addr[0] = 0x00;
2387                 dev->dev_addr[1] = 0x00;
2388                 dev->dev_addr[2] = 0x6c;
2389                 get_random_bytes(&dev->dev_addr[3], 3);
2390         }
2391
2392         dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
2393                         dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2394                         dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2395
2396         /* disable WOL */
2397         writel(0, base + NvRegWakeUpFlags);
2398         np->wolenabled = 0;
2399
2400         if (np->desc_ver == DESC_VER_1) {
2401                 np->tx_flags = NV_TX_LASTPACKET|NV_TX_VALID;
2402         } else {
2403                 np->tx_flags = NV_TX2_LASTPACKET|NV_TX2_VALID;
2404         }
2405         np->irqmask = NVREG_IRQMASK_WANTED;
2406         if (id->driver_data & DEV_NEED_TIMERIRQ)
2407                 np->irqmask |= NVREG_IRQ_TIMER;
2408         if (id->driver_data & DEV_NEED_LINKTIMER) {
2409                 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
2410                 np->need_linktimer = 1;
2411                 np->link_timeout = jiffies + LINK_TIMEOUT;
2412         } else {
2413                 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
2414                 np->need_linktimer = 0;
2415         }
2416
2417         /* find a suitable phy */
2418         for (i = 1; i < 32; i++) {
2419                 int id1, id2;
2420
2421                 spin_lock_irq(&np->lock);
2422                 id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ);
2423                 spin_unlock_irq(&np->lock);
2424                 if (id1 < 0 || id1 == 0xffff)
2425                         continue;
2426                 spin_lock_irq(&np->lock);
2427                 id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ);
2428                 spin_unlock_irq(&np->lock);
2429                 if (id2 < 0 || id2 == 0xffff)
2430                         continue;
2431
2432                 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
2433                 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
2434                 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
2435                                 pci_name(pci_dev), id1, id2, i);
2436                 np->phyaddr = i;
2437                 np->phy_oui = id1 | id2;
2438                 break;
2439         }
2440         if (i == 32) {
2441                 /* PHY in isolate mode? No phy attached and user wants to
2442                  * test loopback? Very odd, but can be correct.
2443                  */
2444                 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
2445                                 pci_name(pci_dev));
2446         }
2447
2448         if (i != 32) {
2449                 /* reset it */
2450                 phy_init(dev);
2451         }
2452
2453         /* set default link speed settings */
2454         np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2455         np->duplex = 0;
2456         np->autoneg = 1;
2457
2458         err = register_netdev(dev);
2459         if (err) {
2460                 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
2461                 goto out_freering;
2462         }
2463         printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2464                         dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
2465                         pci_name(pci_dev));
2466
2467         return 0;
2468
2469 out_freering:
2470         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2471                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2472                                     np->rx_ring.orig, np->ring_addr);
2473         else
2474                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2475                                     np->rx_ring.ex, np->ring_addr);
2476         pci_set_drvdata(pci_dev, NULL);
2477 out_unmap:
2478         iounmap(get_hwbase(dev));
2479 out_relreg:
2480         pci_release_regions(pci_dev);
2481 out_disable:
2482         pci_disable_device(pci_dev);
2483 out_free:
2484         free_netdev(dev);
2485 out:
2486         return err;
2487 }
2488
2489 static void __devexit nv_remove(struct pci_dev *pci_dev)
2490 {
2491         struct net_device *dev = pci_get_drvdata(pci_dev);
2492         struct fe_priv *np = get_nvpriv(dev);
2493
2494         unregister_netdev(dev);
2495
2496         /* free all structures */
2497         if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2498                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring.orig, np->ring_addr);
2499         else
2500                 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), np->rx_ring.ex, np->ring_addr);
2501         iounmap(get_hwbase(dev));
2502         pci_release_regions(pci_dev);
2503         pci_disable_device(pci_dev);
2504         free_netdev(dev);
2505         pci_set_drvdata(pci_dev, NULL);
2506 }
2507
2508 static struct pci_device_id pci_tbl[] = {
2509         {       /* nForce Ethernet Controller */
2510                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
2511                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2512         },
2513         {       /* nForce2 Ethernet Controller */
2514                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
2515                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2516         },
2517         {       /* nForce3 Ethernet Controller */
2518                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
2519                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2520         },
2521         {       /* nForce3 Ethernet Controller */
2522                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
2523                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2524         },
2525         {       /* nForce3 Ethernet Controller */
2526                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
2527                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2528         },
2529         {       /* nForce3 Ethernet Controller */
2530                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
2531                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2532         },
2533         {       /* nForce3 Ethernet Controller */
2534                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
2535                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
2536         },
2537         {       /* CK804 Ethernet Controller */
2538                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
2539                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2540         },
2541         {       /* CK804 Ethernet Controller */
2542                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
2543                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2544         },
2545         {       /* MCP04 Ethernet Controller */
2546                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
2547                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2548         },
2549         {       /* MCP04 Ethernet Controller */
2550                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
2551                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2552         },
2553         {       /* MCP51 Ethernet Controller */
2554                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
2555                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2556         },
2557         {       /* MCP51 Ethernet Controller */
2558                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
2559                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2560         },
2561         {       /* MCP55 Ethernet Controller */
2562                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
2563                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2564         },
2565         {       /* MCP55 Ethernet Controller */
2566                 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
2567                 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA,
2568         },
2569         {0,},
2570 };
2571
2572 static struct pci_driver driver = {
2573         .name = "forcedeth",
2574         .id_table = pci_tbl,
2575         .probe = nv_probe,
2576         .remove = __devexit_p(nv_remove),
2577 };
2578
2579
2580 static int __init init_nic(void)
2581 {
2582         printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2583         return pci_module_init(&driver);
2584 }
2585
2586 static void __exit exit_nic(void)
2587 {
2588         pci_unregister_driver(&driver);
2589 }
2590
2591 module_param(max_interrupt_work, int, 0);
2592 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2593
2594 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2595 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2596 MODULE_LICENSE("GPL");
2597
2598 MODULE_DEVICE_TABLE(pci, pci_tbl);
2599
2600 module_init(init_nic);
2601 module_exit(exit_nic);