2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003,4 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
78 * 0.29: 31 Aug 2004: Add backup timer for link change notification.
79 * 0.30: 25 Sep 2004: rx checksum support for nf 250 Gb. Add rx reset
80 * into nv_close, otherwise reenabling for wol can
81 * cause DMA to kfree'd memory.
82 * 0.31: 14 Nov 2004: ethtool support for getting/setting link
84 * 0.32: 16 Apr 2005: RX_ERROR4 handling added.
85 * 0.33: 16 May 2005: Support for MCP51 added.
86 * 0.34: 18 Jun 2005: Add DEV_NEED_LINKTIMER to all nForce nics.
87 * 0.35: 26 Jun 2005: Support for MCP55 added.
88 * 0.36: 28 Jun 2005: Add jumbo frame support.
89 * 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
90 * 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
92 * 0.39: 18 Jul 2005: Add 64bit descriptor support.
93 * 0.40: 19 Jul 2005: Add support for mac address change.
94 * 0.41: 30 Jul 2005: Write back original MAC in nv_close instead
96 * 0.42: 06 Aug 2005: Fix lack of link speed initialization
97 * in the second (and later) nv_open call
98 * 0.43: 10 Aug 2005: Add support for tx checksum.
99 * 0.44: 20 Aug 2005: Add support for scatter gather and segmentation.
100 * 0.45: 18 Sep 2005: Remove nv_stop/start_rx from every link check
101 * 0.46: 20 Oct 2005: Add irq optimization modes.
104 * We suspect that on some hardware no TX done interrupts are generated.
105 * This means recovery from netif_stop_queue only happens if the hw timer
106 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
107 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
108 * If your hardware reliably generates tx done interrupts, then you can remove
109 * DEV_NEED_TIMERIRQ from the driver_data flags.
110 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
111 * superfluous timer interrupts from the nic.
113 #define FORCEDETH_VERSION "0.46"
114 #define DRV_NAME "forcedeth"
116 #include <linux/module.h>
117 #include <linux/types.h>
118 #include <linux/pci.h>
119 #include <linux/interrupt.h>
120 #include <linux/netdevice.h>
121 #include <linux/etherdevice.h>
122 #include <linux/delay.h>
123 #include <linux/spinlock.h>
124 #include <linux/ethtool.h>
125 #include <linux/timer.h>
126 #include <linux/skbuff.h>
127 #include <linux/mii.h>
128 #include <linux/random.h>
129 #include <linux/init.h>
130 #include <linux/if_vlan.h>
134 #include <asm/uaccess.h>
135 #include <asm/system.h>
138 #define dprintk printk
140 #define dprintk(x...) do { } while (0)
148 #define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
149 #define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
150 #define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
151 #define DEV_HAS_HIGH_DMA 0x0008 /* device supports 64bit dma */
152 #define DEV_HAS_CHECKSUM 0x0010 /* device supports tx and rx checksum offloads */
155 NvRegIrqStatus = 0x000,
156 #define NVREG_IRQSTAT_MIIEVENT 0x040
157 #define NVREG_IRQSTAT_MASK 0x1ff
158 NvRegIrqMask = 0x004,
159 #define NVREG_IRQ_RX_ERROR 0x0001
160 #define NVREG_IRQ_RX 0x0002
161 #define NVREG_IRQ_RX_NOBUF 0x0004
162 #define NVREG_IRQ_TX_ERR 0x0008
163 #define NVREG_IRQ_TX_OK 0x0010
164 #define NVREG_IRQ_TIMER 0x0020
165 #define NVREG_IRQ_LINK 0x0040
166 #define NVREG_IRQ_TX_ERROR 0x0080
167 #define NVREG_IRQ_TX1 0x0100
168 #define NVREG_IRQMASK_THROUGHPUT 0x00df
169 #define NVREG_IRQMASK_CPU 0x0040
171 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
172 NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX_ERROR| \
175 NvRegUnknownSetupReg6 = 0x008,
176 #define NVREG_UNKSETUP6_VAL 3
179 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
180 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
182 NvRegPollingInterval = 0x00c,
183 #define NVREG_POLL_DEFAULT_THROUGHPUT 970
184 #define NVREG_POLL_DEFAULT_CPU 13
186 #define NVREG_MISC1_HD 0x02
187 #define NVREG_MISC1_FORCE 0x3b0f3c
189 NvRegTransmitterControl = 0x084,
190 #define NVREG_XMITCTL_START 0x01
191 NvRegTransmitterStatus = 0x088,
192 #define NVREG_XMITSTAT_BUSY 0x01
194 NvRegPacketFilterFlags = 0x8c,
195 #define NVREG_PFF_ALWAYS 0x7F0008
196 #define NVREG_PFF_PROMISC 0x80
197 #define NVREG_PFF_MYADDR 0x20
199 NvRegOffloadConfig = 0x90,
200 #define NVREG_OFFLOAD_HOMEPHY 0x601
201 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
202 NvRegReceiverControl = 0x094,
203 #define NVREG_RCVCTL_START 0x01
204 NvRegReceiverStatus = 0x98,
205 #define NVREG_RCVSTAT_BUSY 0x01
207 NvRegRandomSeed = 0x9c,
208 #define NVREG_RNDSEED_MASK 0x00ff
209 #define NVREG_RNDSEED_FORCE 0x7f00
210 #define NVREG_RNDSEED_FORCE2 0x2d00
211 #define NVREG_RNDSEED_FORCE3 0x7400
213 NvRegUnknownSetupReg1 = 0xA0,
214 #define NVREG_UNKSETUP1_VAL 0x16070f
215 NvRegUnknownSetupReg2 = 0xA4,
216 #define NVREG_UNKSETUP2_VAL 0x16
217 NvRegMacAddrA = 0xA8,
218 NvRegMacAddrB = 0xAC,
219 NvRegMulticastAddrA = 0xB0,
220 #define NVREG_MCASTADDRA_FORCE 0x01
221 NvRegMulticastAddrB = 0xB4,
222 NvRegMulticastMaskA = 0xB8,
223 NvRegMulticastMaskB = 0xBC,
225 NvRegPhyInterface = 0xC0,
226 #define PHY_RGMII 0x10000000
228 NvRegTxRingPhysAddr = 0x100,
229 NvRegRxRingPhysAddr = 0x104,
230 NvRegRingSizes = 0x108,
231 #define NVREG_RINGSZ_TXSHIFT 0
232 #define NVREG_RINGSZ_RXSHIFT 16
233 NvRegUnknownTransmitterReg = 0x10c,
234 NvRegLinkSpeed = 0x110,
235 #define NVREG_LINKSPEED_FORCE 0x10000
236 #define NVREG_LINKSPEED_10 1000
237 #define NVREG_LINKSPEED_100 100
238 #define NVREG_LINKSPEED_1000 50
239 #define NVREG_LINKSPEED_MASK (0xFFF)
240 NvRegUnknownSetupReg5 = 0x130,
241 #define NVREG_UNKSETUP5_BIT31 (1<<31)
242 NvRegUnknownSetupReg3 = 0x13c,
243 #define NVREG_UNKSETUP3_VAL1 0x200010
244 NvRegTxRxControl = 0x144,
245 #define NVREG_TXRXCTL_KICK 0x0001
246 #define NVREG_TXRXCTL_BIT1 0x0002
247 #define NVREG_TXRXCTL_BIT2 0x0004
248 #define NVREG_TXRXCTL_IDLE 0x0008
249 #define NVREG_TXRXCTL_RESET 0x0010
250 #define NVREG_TXRXCTL_RXCHECK 0x0400
251 #define NVREG_TXRXCTL_DESC_1 0
252 #define NVREG_TXRXCTL_DESC_2 0x02100
253 #define NVREG_TXRXCTL_DESC_3 0x02200
254 NvRegMIIStatus = 0x180,
255 #define NVREG_MIISTAT_ERROR 0x0001
256 #define NVREG_MIISTAT_LINKCHANGE 0x0008
257 #define NVREG_MIISTAT_MASK 0x000f
258 #define NVREG_MIISTAT_MASK2 0x000f
259 NvRegUnknownSetupReg4 = 0x184,
260 #define NVREG_UNKSETUP4_VAL 8
262 NvRegAdapterControl = 0x188,
263 #define NVREG_ADAPTCTL_START 0x02
264 #define NVREG_ADAPTCTL_LINKUP 0x04
265 #define NVREG_ADAPTCTL_PHYVALID 0x40000
266 #define NVREG_ADAPTCTL_RUNNING 0x100000
267 #define NVREG_ADAPTCTL_PHYSHIFT 24
268 NvRegMIISpeed = 0x18c,
269 #define NVREG_MIISPEED_BIT8 (1<<8)
270 #define NVREG_MIIDELAY 5
271 NvRegMIIControl = 0x190,
272 #define NVREG_MIICTL_INUSE 0x08000
273 #define NVREG_MIICTL_WRITE 0x00400
274 #define NVREG_MIICTL_ADDRSHIFT 5
275 NvRegMIIData = 0x194,
276 NvRegWakeUpFlags = 0x200,
277 #define NVREG_WAKEUPFLAGS_VAL 0x7770
278 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
279 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
280 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
281 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
282 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
283 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
284 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
285 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
286 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
287 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
289 NvRegPatternCRC = 0x204,
290 NvRegPatternMask = 0x208,
291 NvRegPowerCap = 0x268,
292 #define NVREG_POWERCAP_D3SUPP (1<<30)
293 #define NVREG_POWERCAP_D2SUPP (1<<26)
294 #define NVREG_POWERCAP_D1SUPP (1<<25)
295 NvRegPowerState = 0x26c,
296 #define NVREG_POWERSTATE_POWEREDUP 0x8000
297 #define NVREG_POWERSTATE_VALID 0x0100
298 #define NVREG_POWERSTATE_MASK 0x0003
299 #define NVREG_POWERSTATE_D0 0x0000
300 #define NVREG_POWERSTATE_D1 0x0001
301 #define NVREG_POWERSTATE_D2 0x0002
302 #define NVREG_POWERSTATE_D3 0x0003
305 /* Big endian: should work, but is untested */
311 struct ring_desc_ex {
312 u32 PacketBufferHigh;
318 typedef union _ring_type {
319 struct ring_desc* orig;
320 struct ring_desc_ex* ex;
323 #define FLAG_MASK_V1 0xffff0000
324 #define FLAG_MASK_V2 0xffffc000
325 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
326 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
328 #define NV_TX_LASTPACKET (1<<16)
329 #define NV_TX_RETRYERROR (1<<19)
330 #define NV_TX_FORCED_INTERRUPT (1<<24)
331 #define NV_TX_DEFERRED (1<<26)
332 #define NV_TX_CARRIERLOST (1<<27)
333 #define NV_TX_LATECOLLISION (1<<28)
334 #define NV_TX_UNDERFLOW (1<<29)
335 #define NV_TX_ERROR (1<<30)
336 #define NV_TX_VALID (1<<31)
338 #define NV_TX2_LASTPACKET (1<<29)
339 #define NV_TX2_RETRYERROR (1<<18)
340 #define NV_TX2_FORCED_INTERRUPT (1<<30)
341 #define NV_TX2_DEFERRED (1<<25)
342 #define NV_TX2_CARRIERLOST (1<<26)
343 #define NV_TX2_LATECOLLISION (1<<27)
344 #define NV_TX2_UNDERFLOW (1<<28)
345 /* error and valid are the same for both */
346 #define NV_TX2_ERROR (1<<30)
347 #define NV_TX2_VALID (1<<31)
348 #define NV_TX2_TSO (1<<28)
349 #define NV_TX2_TSO_SHIFT 14
350 #define NV_TX2_CHECKSUM_L3 (1<<27)
351 #define NV_TX2_CHECKSUM_L4 (1<<26)
353 #define NV_RX_DESCRIPTORVALID (1<<16)
354 #define NV_RX_MISSEDFRAME (1<<17)
355 #define NV_RX_SUBSTRACT1 (1<<18)
356 #define NV_RX_ERROR1 (1<<23)
357 #define NV_RX_ERROR2 (1<<24)
358 #define NV_RX_ERROR3 (1<<25)
359 #define NV_RX_ERROR4 (1<<26)
360 #define NV_RX_CRCERR (1<<27)
361 #define NV_RX_OVERFLOW (1<<28)
362 #define NV_RX_FRAMINGERR (1<<29)
363 #define NV_RX_ERROR (1<<30)
364 #define NV_RX_AVAIL (1<<31)
366 #define NV_RX2_CHECKSUMMASK (0x1C000000)
367 #define NV_RX2_CHECKSUMOK1 (0x10000000)
368 #define NV_RX2_CHECKSUMOK2 (0x14000000)
369 #define NV_RX2_CHECKSUMOK3 (0x18000000)
370 #define NV_RX2_DESCRIPTORVALID (1<<29)
371 #define NV_RX2_SUBSTRACT1 (1<<25)
372 #define NV_RX2_ERROR1 (1<<18)
373 #define NV_RX2_ERROR2 (1<<19)
374 #define NV_RX2_ERROR3 (1<<20)
375 #define NV_RX2_ERROR4 (1<<21)
376 #define NV_RX2_CRCERR (1<<22)
377 #define NV_RX2_OVERFLOW (1<<23)
378 #define NV_RX2_FRAMINGERR (1<<24)
379 /* error and avail are the same for both */
380 #define NV_RX2_ERROR (1<<30)
381 #define NV_RX2_AVAIL (1<<31)
383 /* Miscelaneous hardware related defines: */
384 #define NV_PCI_REGSZ 0x270
386 /* various timeout delays: all in usec */
387 #define NV_TXRX_RESET_DELAY 4
388 #define NV_TXSTOP_DELAY1 10
389 #define NV_TXSTOP_DELAY1MAX 500000
390 #define NV_TXSTOP_DELAY2 100
391 #define NV_RXSTOP_DELAY1 10
392 #define NV_RXSTOP_DELAY1MAX 500000
393 #define NV_RXSTOP_DELAY2 100
394 #define NV_SETUP5_DELAY 5
395 #define NV_SETUP5_DELAYMAX 50000
396 #define NV_POWERUP_DELAY 5
397 #define NV_POWERUP_DELAYMAX 5000
398 #define NV_MIIBUSY_DELAY 50
399 #define NV_MIIPHY_DELAY 10
400 #define NV_MIIPHY_DELAYMAX 10000
402 #define NV_WAKEUPPATTERNS 5
403 #define NV_WAKEUPMASKENTRIES 4
405 /* General driver defaults */
406 #define NV_WATCHDOG_TIMEO (5*HZ)
411 * If your nic mysteriously hangs then try to reduce the limits
412 * to 1/0: It might be required to set NV_TX_LASTPACKET in the
413 * last valid ring entry. But this would be impossible to
414 * implement - probably a disassembly error.
416 #define TX_LIMIT_STOP 63
417 #define TX_LIMIT_START 62
419 /* rx/tx mac addr + type + vlan + align + slack*/
420 #define NV_RX_HEADERS (64)
421 /* even more slack. */
422 #define NV_RX_ALLOC_PAD (64)
424 /* maximum mtu size */
425 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
426 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
428 #define OOM_REFILL (1+HZ/20)
429 #define POLL_WAIT (1+HZ/100)
430 #define LINK_TIMEOUT (3*HZ)
434 * The nic supports three different descriptor types:
435 * - DESC_VER_1: Original
436 * - DESC_VER_2: support for jumbo frames.
437 * - DESC_VER_3: 64-bit format.
444 #define PHY_OUI_MARVELL 0x5043
445 #define PHY_OUI_CICADA 0x03f1
446 #define PHYID1_OUI_MASK 0x03ff
447 #define PHYID1_OUI_SHFT 6
448 #define PHYID2_OUI_MASK 0xfc00
449 #define PHYID2_OUI_SHFT 10
450 #define PHY_INIT1 0x0f000
451 #define PHY_INIT2 0x0e00
452 #define PHY_INIT3 0x01000
453 #define PHY_INIT4 0x0200
454 #define PHY_INIT5 0x0004
455 #define PHY_INIT6 0x02000
456 #define PHY_GIGABIT 0x0100
458 #define PHY_TIMEOUT 0x1
459 #define PHY_ERROR 0x2
463 #define PHY_HALF 0x100
465 /* FIXME: MII defines that should be added to <linux/mii.h> */
466 #define MII_1000BT_CR 0x09
467 #define MII_1000BT_SR 0x0a
468 #define ADVERTISE_1000FULL 0x0200
469 #define ADVERTISE_1000HALF 0x0100
470 #define LPA_1000FULL 0x0800
471 #define LPA_1000HALF 0x0400
476 * All hardware access under dev->priv->lock, except the performance
478 * - rx is (pseudo-) lockless: it relies on the single-threading provided
479 * by the arch code for interrupts.
480 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
481 * needs dev->priv->lock :-(
482 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
485 /* in dev: base, irq */
490 * Locking: spin_lock(&np->lock); */
491 struct net_device_stats stats;
499 unsigned int phy_oui;
502 /* General data: RO fields */
503 dma_addr_t ring_addr;
504 struct pci_dev *pci_dev;
512 /* rx specific fields.
513 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
516 unsigned int cur_rx, refill_rx;
517 struct sk_buff *rx_skbuff[RX_RING];
518 dma_addr_t rx_dma[RX_RING];
519 unsigned int rx_buf_sz;
520 unsigned int pkt_limit;
521 struct timer_list oom_kick;
522 struct timer_list nic_poll;
524 /* media detection workaround.
525 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
528 unsigned long link_timeout;
530 * tx specific fields.
533 unsigned int next_tx, nic_tx;
534 struct sk_buff *tx_skbuff[TX_RING];
535 dma_addr_t tx_dma[TX_RING];
540 * Maximum number of loops until we assume that a bit in the irq mask
541 * is stuck. Overridable with module param.
543 static int max_interrupt_work = 5;
546 * Optimization can be either throuput mode or cpu mode
548 * Throughput Mode: Every tx and rx packet will generate an interrupt.
549 * CPU Mode: Interrupts are controlled by a timer.
551 #define NV_OPTIMIZATION_MODE_THROUGHPUT 0
552 #define NV_OPTIMIZATION_MODE_CPU 1
553 static int optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
556 * Poll interval for timer irq
558 * This interval determines how frequent an interrupt is generated.
559 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
560 * Min = 0, and Max = 65535
562 static int poll_interval = -1;
564 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
566 return netdev_priv(dev);
569 static inline u8 __iomem *get_hwbase(struct net_device *dev)
571 return ((struct fe_priv *)netdev_priv(dev))->base;
574 static inline void pci_push(u8 __iomem *base)
576 /* force out pending posted writes */
580 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
582 return le32_to_cpu(prd->FlagLen)
583 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
586 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
588 return le32_to_cpu(prd->FlagLen) & LEN_MASK_V2;
591 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
592 int delay, int delaymax, const char *msg)
594 u8 __iomem *base = get_hwbase(dev);
605 } while ((readl(base + offset) & mask) != target);
609 #define MII_READ (-1)
610 /* mii_rw: read/write a register on the PHY.
612 * Caller must guarantee serialization
614 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
616 u8 __iomem *base = get_hwbase(dev);
620 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
622 reg = readl(base + NvRegMIIControl);
623 if (reg & NVREG_MIICTL_INUSE) {
624 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
625 udelay(NV_MIIBUSY_DELAY);
628 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
629 if (value != MII_READ) {
630 writel(value, base + NvRegMIIData);
631 reg |= NVREG_MIICTL_WRITE;
633 writel(reg, base + NvRegMIIControl);
635 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
636 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
637 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
638 dev->name, miireg, addr);
640 } else if (value != MII_READ) {
641 /* it was a write operation - fewer failures are detectable */
642 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
643 dev->name, value, miireg, addr);
645 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
646 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
647 dev->name, miireg, addr);
650 retval = readl(base + NvRegMIIData);
651 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
652 dev->name, miireg, addr, retval);
658 static int phy_reset(struct net_device *dev)
660 struct fe_priv *np = netdev_priv(dev);
662 unsigned int tries = 0;
664 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
665 miicontrol |= BMCR_RESET;
666 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
673 /* must wait till reset is deasserted */
674 while (miicontrol & BMCR_RESET) {
676 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
677 /* FIXME: 100 tries seem excessive */
684 static int phy_init(struct net_device *dev)
686 struct fe_priv *np = get_nvpriv(dev);
687 u8 __iomem *base = get_hwbase(dev);
688 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
690 /* set advertise register */
691 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
692 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
693 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
694 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
698 /* get phy interface type */
699 phyinterface = readl(base + NvRegPhyInterface);
701 /* see if gigabit phy */
702 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
703 if (mii_status & PHY_GIGABIT) {
704 np->gigabit = PHY_GIGABIT;
705 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
706 mii_control_1000 &= ~ADVERTISE_1000HALF;
707 if (phyinterface & PHY_RGMII)
708 mii_control_1000 |= ADVERTISE_1000FULL;
710 mii_control_1000 &= ~ADVERTISE_1000FULL;
712 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
713 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
721 if (phy_reset(dev)) {
722 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
726 /* phy vendor specific configuration */
727 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
728 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
729 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
730 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
731 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
732 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
735 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
736 phy_reserved |= PHY_INIT5;
737 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
738 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
742 if (np->phy_oui == PHY_OUI_CICADA) {
743 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
744 phy_reserved |= PHY_INIT6;
745 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
746 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
751 /* restart auto negotiation */
752 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
753 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
754 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
761 static void nv_start_rx(struct net_device *dev)
763 struct fe_priv *np = netdev_priv(dev);
764 u8 __iomem *base = get_hwbase(dev);
766 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
767 /* Already running? Stop it. */
768 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
769 writel(0, base + NvRegReceiverControl);
772 writel(np->linkspeed, base + NvRegLinkSpeed);
774 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
775 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
776 dev->name, np->duplex, np->linkspeed);
780 static void nv_stop_rx(struct net_device *dev)
782 u8 __iomem *base = get_hwbase(dev);
784 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
785 writel(0, base + NvRegReceiverControl);
786 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
787 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
788 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
790 udelay(NV_RXSTOP_DELAY2);
791 writel(0, base + NvRegLinkSpeed);
794 static void nv_start_tx(struct net_device *dev)
796 u8 __iomem *base = get_hwbase(dev);
798 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
799 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
803 static void nv_stop_tx(struct net_device *dev)
805 u8 __iomem *base = get_hwbase(dev);
807 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
808 writel(0, base + NvRegTransmitterControl);
809 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
810 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
811 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
813 udelay(NV_TXSTOP_DELAY2);
814 writel(0, base + NvRegUnknownTransmitterReg);
817 static void nv_txrx_reset(struct net_device *dev)
819 struct fe_priv *np = netdev_priv(dev);
820 u8 __iomem *base = get_hwbase(dev);
822 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
823 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
825 udelay(NV_TXRX_RESET_DELAY);
826 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
831 * nv_get_stats: dev->get_stats function
832 * Get latest stats value from the nic.
833 * Called with read_lock(&dev_base_lock) held for read -
834 * only synchronized against unregister_netdevice.
836 static struct net_device_stats *nv_get_stats(struct net_device *dev)
838 struct fe_priv *np = netdev_priv(dev);
840 /* It seems that the nic always generates interrupts and doesn't
841 * accumulate errors internally. Thus the current values in np->stats
842 * are already up to date.
848 * nv_alloc_rx: fill rx ring entries.
849 * Return 1 if the allocations for the skbs failed and the
850 * rx engine is without Available descriptors
852 static int nv_alloc_rx(struct net_device *dev)
854 struct fe_priv *np = netdev_priv(dev);
855 unsigned int refill_rx = np->refill_rx;
858 while (np->cur_rx != refill_rx) {
861 nr = refill_rx % RX_RING;
862 if (np->rx_skbuff[nr] == NULL) {
864 skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
869 np->rx_skbuff[nr] = skb;
871 skb = np->rx_skbuff[nr];
873 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
875 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
876 np->rx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
878 np->rx_ring.orig[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
880 np->rx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->rx_dma[nr]) >> 32;
881 np->rx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->rx_dma[nr]) & 0x0FFFFFFFF;
883 np->rx_ring.ex[nr].FlagLen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
885 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
886 dev->name, refill_rx);
889 np->refill_rx = refill_rx;
890 if (np->cur_rx - refill_rx == RX_RING)
895 static void nv_do_rx_refill(unsigned long data)
897 struct net_device *dev = (struct net_device *) data;
898 struct fe_priv *np = netdev_priv(dev);
900 disable_irq(dev->irq);
901 if (nv_alloc_rx(dev)) {
902 spin_lock(&np->lock);
903 if (!np->in_shutdown)
904 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
905 spin_unlock(&np->lock);
907 enable_irq(dev->irq);
910 static void nv_init_rx(struct net_device *dev)
912 struct fe_priv *np = netdev_priv(dev);
915 np->cur_rx = RX_RING;
917 for (i = 0; i < RX_RING; i++)
918 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
919 np->rx_ring.orig[i].FlagLen = 0;
921 np->rx_ring.ex[i].FlagLen = 0;
924 static void nv_init_tx(struct net_device *dev)
926 struct fe_priv *np = netdev_priv(dev);
929 np->next_tx = np->nic_tx = 0;
930 for (i = 0; i < TX_RING; i++) {
931 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
932 np->tx_ring.orig[i].FlagLen = 0;
934 np->tx_ring.ex[i].FlagLen = 0;
935 np->tx_skbuff[i] = NULL;
939 static int nv_init_ring(struct net_device *dev)
943 return nv_alloc_rx(dev);
946 static void nv_release_txskb(struct net_device *dev, unsigned int skbnr)
948 struct fe_priv *np = netdev_priv(dev);
949 struct sk_buff *skb = np->tx_skbuff[skbnr];
950 unsigned int j, entry, fragments;
952 dprintk(KERN_INFO "%s: nv_release_txskb for skbnr %d, skb %p\n",
953 dev->name, skbnr, np->tx_skbuff[skbnr]);
956 if ((fragments = skb_shinfo(skb)->nr_frags) != 0) {
957 for (j = fragments; j >= 1; j--) {
958 skb_frag_t *frag = &skb_shinfo(skb)->frags[j-1];
959 pci_unmap_page(np->pci_dev, np->tx_dma[entry],
962 entry = (entry - 1) % TX_RING;
965 pci_unmap_single(np->pci_dev, np->tx_dma[entry],
966 skb->len - skb->data_len,
968 dev_kfree_skb_irq(skb);
969 np->tx_skbuff[skbnr] = NULL;
972 static void nv_drain_tx(struct net_device *dev)
974 struct fe_priv *np = netdev_priv(dev);
977 for (i = 0; i < TX_RING; i++) {
978 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
979 np->tx_ring.orig[i].FlagLen = 0;
981 np->tx_ring.ex[i].FlagLen = 0;
982 if (np->tx_skbuff[i]) {
983 nv_release_txskb(dev, i);
984 np->stats.tx_dropped++;
989 static void nv_drain_rx(struct net_device *dev)
991 struct fe_priv *np = netdev_priv(dev);
993 for (i = 0; i < RX_RING; i++) {
994 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
995 np->rx_ring.orig[i].FlagLen = 0;
997 np->rx_ring.ex[i].FlagLen = 0;
999 if (np->rx_skbuff[i]) {
1000 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1001 np->rx_skbuff[i]->len,
1002 PCI_DMA_FROMDEVICE);
1003 dev_kfree_skb(np->rx_skbuff[i]);
1004 np->rx_skbuff[i] = NULL;
1009 static void drain_ring(struct net_device *dev)
1016 * nv_start_xmit: dev->hard_start_xmit function
1017 * Called with dev->xmit_lock held.
1019 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
1021 struct fe_priv *np = netdev_priv(dev);
1022 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
1023 unsigned int fragments = skb_shinfo(skb)->nr_frags;
1024 unsigned int nr = (np->next_tx + fragments) % TX_RING;
1027 spin_lock_irq(&np->lock);
1029 if ((np->next_tx - np->nic_tx + fragments) > TX_LIMIT_STOP) {
1030 spin_unlock_irq(&np->lock);
1031 netif_stop_queue(dev);
1032 return NETDEV_TX_BUSY;
1035 np->tx_skbuff[nr] = skb;
1038 dprintk(KERN_DEBUG "%s: nv_start_xmit: buffer contains %d fragments\n", dev->name, fragments);
1039 /* setup descriptors in reverse order */
1040 for (i = fragments; i >= 1; i--) {
1041 skb_frag_t *frag = &skb_shinfo(skb)->frags[i-1];
1042 np->tx_dma[nr] = pci_map_page(np->pci_dev, frag->page, frag->page_offset, frag->size,
1045 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1046 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1047 np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (frag->size-1) | np->tx_flags | tx_flags_extra);
1049 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1050 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1051 np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (frag->size-1) | np->tx_flags | tx_flags_extra);
1054 nr = (nr - 1) % TX_RING;
1056 if (np->desc_ver == DESC_VER_1)
1057 tx_flags_extra &= ~NV_TX_LASTPACKET;
1059 tx_flags_extra &= ~NV_TX2_LASTPACKET;
1064 if (skb_shinfo(skb)->tso_size)
1065 tx_flags_extra |= NV_TX2_TSO | (skb_shinfo(skb)->tso_size << NV_TX2_TSO_SHIFT);
1068 tx_flags_extra |= (skb->ip_summed == CHECKSUM_HW ? (NV_TX2_CHECKSUM_L3|NV_TX2_CHECKSUM_L4) : 0);
1070 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len-skb->data_len,
1073 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1074 np->tx_ring.orig[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
1075 np->tx_ring.orig[nr].FlagLen = cpu_to_le32( (skb->len-skb->data_len-1) | np->tx_flags | tx_flags_extra);
1077 np->tx_ring.ex[nr].PacketBufferHigh = cpu_to_le64(np->tx_dma[nr]) >> 32;
1078 np->tx_ring.ex[nr].PacketBufferLow = cpu_to_le64(np->tx_dma[nr]) & 0x0FFFFFFFF;
1079 np->tx_ring.ex[nr].FlagLen = cpu_to_le32( (skb->len-skb->data_len-1) | np->tx_flags | tx_flags_extra);
1082 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission. tx_flags_extra: %x\n",
1083 dev->name, np->next_tx, tx_flags_extra);
1086 for (j=0; j<64; j++) {
1088 dprintk("\n%03x:", j);
1089 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
1094 np->next_tx += 1 + fragments;
1096 dev->trans_start = jiffies;
1097 spin_unlock_irq(&np->lock);
1098 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1099 pci_push(get_hwbase(dev));
1100 return NETDEV_TX_OK;
1104 * nv_tx_done: check for completed packets, release the skbs.
1106 * Caller must own np->lock.
1108 static void nv_tx_done(struct net_device *dev)
1110 struct fe_priv *np = netdev_priv(dev);
1113 struct sk_buff *skb;
1115 while (np->nic_tx != np->next_tx) {
1116 i = np->nic_tx % TX_RING;
1118 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1119 Flags = le32_to_cpu(np->tx_ring.orig[i].FlagLen);
1121 Flags = le32_to_cpu(np->tx_ring.ex[i].FlagLen);
1123 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
1124 dev->name, np->nic_tx, Flags);
1125 if (Flags & NV_TX_VALID)
1127 if (np->desc_ver == DESC_VER_1) {
1128 if (Flags & NV_TX_LASTPACKET) {
1129 skb = np->tx_skbuff[i];
1130 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1131 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1132 if (Flags & NV_TX_UNDERFLOW)
1133 np->stats.tx_fifo_errors++;
1134 if (Flags & NV_TX_CARRIERLOST)
1135 np->stats.tx_carrier_errors++;
1136 np->stats.tx_errors++;
1138 np->stats.tx_packets++;
1139 np->stats.tx_bytes += skb->len;
1141 nv_release_txskb(dev, i);
1144 if (Flags & NV_TX2_LASTPACKET) {
1145 skb = np->tx_skbuff[i];
1146 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1147 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1148 if (Flags & NV_TX2_UNDERFLOW)
1149 np->stats.tx_fifo_errors++;
1150 if (Flags & NV_TX2_CARRIERLOST)
1151 np->stats.tx_carrier_errors++;
1152 np->stats.tx_errors++;
1154 np->stats.tx_packets++;
1155 np->stats.tx_bytes += skb->len;
1157 nv_release_txskb(dev, i);
1162 if (np->next_tx - np->nic_tx < TX_LIMIT_START)
1163 netif_wake_queue(dev);
1167 * nv_tx_timeout: dev->tx_timeout function
1168 * Called with dev->xmit_lock held.
1170 static void nv_tx_timeout(struct net_device *dev)
1172 struct fe_priv *np = netdev_priv(dev);
1173 u8 __iomem *base = get_hwbase(dev);
1175 printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name,
1176 readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
1181 printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
1182 dev->name, (unsigned long)np->ring_addr,
1183 np->next_tx, np->nic_tx);
1184 printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
1185 for (i=0;i<0x400;i+= 32) {
1186 printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
1188 readl(base + i + 0), readl(base + i + 4),
1189 readl(base + i + 8), readl(base + i + 12),
1190 readl(base + i + 16), readl(base + i + 20),
1191 readl(base + i + 24), readl(base + i + 28));
1193 printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
1194 for (i=0;i<TX_RING;i+= 4) {
1195 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1196 printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
1198 le32_to_cpu(np->tx_ring.orig[i].PacketBuffer),
1199 le32_to_cpu(np->tx_ring.orig[i].FlagLen),
1200 le32_to_cpu(np->tx_ring.orig[i+1].PacketBuffer),
1201 le32_to_cpu(np->tx_ring.orig[i+1].FlagLen),
1202 le32_to_cpu(np->tx_ring.orig[i+2].PacketBuffer),
1203 le32_to_cpu(np->tx_ring.orig[i+2].FlagLen),
1204 le32_to_cpu(np->tx_ring.orig[i+3].PacketBuffer),
1205 le32_to_cpu(np->tx_ring.orig[i+3].FlagLen));
1207 printk(KERN_INFO "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
1209 le32_to_cpu(np->tx_ring.ex[i].PacketBufferHigh),
1210 le32_to_cpu(np->tx_ring.ex[i].PacketBufferLow),
1211 le32_to_cpu(np->tx_ring.ex[i].FlagLen),
1212 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferHigh),
1213 le32_to_cpu(np->tx_ring.ex[i+1].PacketBufferLow),
1214 le32_to_cpu(np->tx_ring.ex[i+1].FlagLen),
1215 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferHigh),
1216 le32_to_cpu(np->tx_ring.ex[i+2].PacketBufferLow),
1217 le32_to_cpu(np->tx_ring.ex[i+2].FlagLen),
1218 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferHigh),
1219 le32_to_cpu(np->tx_ring.ex[i+3].PacketBufferLow),
1220 le32_to_cpu(np->tx_ring.ex[i+3].FlagLen));
1225 spin_lock_irq(&np->lock);
1227 /* 1) stop tx engine */
1230 /* 2) check that the packets were not sent already: */
1233 /* 3) if there are dead entries: clear everything */
1234 if (np->next_tx != np->nic_tx) {
1235 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1237 np->next_tx = np->nic_tx = 0;
1238 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1239 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1241 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1242 netif_wake_queue(dev);
1245 /* 4) restart tx engine */
1247 spin_unlock_irq(&np->lock);
1251 * Called when the nic notices a mismatch between the actual data len on the
1252 * wire and the len indicated in the 802 header
1254 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
1256 int hdrlen; /* length of the 802 header */
1257 int protolen; /* length as stored in the proto field */
1259 /* 1) calculate len according to header */
1260 if ( ((struct vlan_ethhdr *)packet)->h_vlan_proto == __constant_htons(ETH_P_8021Q)) {
1261 protolen = ntohs( ((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto );
1264 protolen = ntohs( ((struct ethhdr *)packet)->h_proto);
1267 dprintk(KERN_DEBUG "%s: nv_getlen: datalen %d, protolen %d, hdrlen %d\n",
1268 dev->name, datalen, protolen, hdrlen);
1269 if (protolen > ETH_DATA_LEN)
1270 return datalen; /* Value in proto field not a len, no checks possible */
1273 /* consistency checks: */
1274 if (datalen > ETH_ZLEN) {
1275 if (datalen >= protolen) {
1276 /* more data on wire than in 802 header, trim of
1279 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1280 dev->name, protolen);
1283 /* less data on wire than mentioned in header.
1284 * Discard the packet.
1286 dprintk(KERN_DEBUG "%s: nv_getlen: discarding long packet.\n",
1291 /* short packet. Accept only if 802 values are also short */
1292 if (protolen > ETH_ZLEN) {
1293 dprintk(KERN_DEBUG "%s: nv_getlen: discarding short packet.\n",
1297 dprintk(KERN_DEBUG "%s: nv_getlen: accepting %d bytes.\n",
1298 dev->name, datalen);
1303 static void nv_rx_process(struct net_device *dev)
1305 struct fe_priv *np = netdev_priv(dev);
1309 struct sk_buff *skb;
1312 if (np->cur_rx - np->refill_rx >= RX_RING)
1313 break; /* we scanned the whole ring - do not continue */
1315 i = np->cur_rx % RX_RING;
1316 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
1317 Flags = le32_to_cpu(np->rx_ring.orig[i].FlagLen);
1318 len = nv_descr_getlength(&np->rx_ring.orig[i], np->desc_ver);
1320 Flags = le32_to_cpu(np->rx_ring.ex[i].FlagLen);
1321 len = nv_descr_getlength_ex(&np->rx_ring.ex[i], np->desc_ver);
1324 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1325 dev->name, np->cur_rx, Flags);
1327 if (Flags & NV_RX_AVAIL)
1328 break; /* still owned by hardware, */
1331 * the packet is for us - immediately tear down the pci mapping.
1332 * TODO: check if a prefetch of the first cacheline improves
1335 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1336 np->rx_skbuff[i]->len,
1337 PCI_DMA_FROMDEVICE);
1341 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1342 for (j=0; j<64; j++) {
1344 dprintk("\n%03x:", j);
1345 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1349 /* look at what we actually got: */
1350 if (np->desc_ver == DESC_VER_1) {
1351 if (!(Flags & NV_RX_DESCRIPTORVALID))
1354 if (Flags & NV_RX_ERROR) {
1355 if (Flags & NV_RX_MISSEDFRAME) {
1356 np->stats.rx_missed_errors++;
1357 np->stats.rx_errors++;
1360 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3)) {
1361 np->stats.rx_errors++;
1364 if (Flags & NV_RX_CRCERR) {
1365 np->stats.rx_crc_errors++;
1366 np->stats.rx_errors++;
1369 if (Flags & NV_RX_OVERFLOW) {
1370 np->stats.rx_over_errors++;
1371 np->stats.rx_errors++;
1374 if (Flags & NV_RX_ERROR4) {
1375 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1377 np->stats.rx_errors++;
1381 /* framing errors are soft errors. */
1382 if (Flags & NV_RX_FRAMINGERR) {
1383 if (Flags & NV_RX_SUBSTRACT1) {
1389 if (!(Flags & NV_RX2_DESCRIPTORVALID))
1392 if (Flags & NV_RX2_ERROR) {
1393 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3)) {
1394 np->stats.rx_errors++;
1397 if (Flags & NV_RX2_CRCERR) {
1398 np->stats.rx_crc_errors++;
1399 np->stats.rx_errors++;
1402 if (Flags & NV_RX2_OVERFLOW) {
1403 np->stats.rx_over_errors++;
1404 np->stats.rx_errors++;
1407 if (Flags & NV_RX2_ERROR4) {
1408 len = nv_getlen(dev, np->rx_skbuff[i]->data, len);
1410 np->stats.rx_errors++;
1414 /* framing errors are soft errors */
1415 if (Flags & NV_RX2_FRAMINGERR) {
1416 if (Flags & NV_RX2_SUBSTRACT1) {
1421 Flags &= NV_RX2_CHECKSUMMASK;
1422 if (Flags == NV_RX2_CHECKSUMOK1 ||
1423 Flags == NV_RX2_CHECKSUMOK2 ||
1424 Flags == NV_RX2_CHECKSUMOK3) {
1425 dprintk(KERN_DEBUG "%s: hw checksum hit!.\n", dev->name);
1426 np->rx_skbuff[i]->ip_summed = CHECKSUM_UNNECESSARY;
1428 dprintk(KERN_DEBUG "%s: hwchecksum miss!.\n", dev->name);
1431 /* got a valid packet - forward it to the network core */
1432 skb = np->rx_skbuff[i];
1433 np->rx_skbuff[i] = NULL;
1436 skb->protocol = eth_type_trans(skb, dev);
1437 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1438 dev->name, np->cur_rx, len, skb->protocol);
1440 dev->last_rx = jiffies;
1441 np->stats.rx_packets++;
1442 np->stats.rx_bytes += len;
1448 static void set_bufsize(struct net_device *dev)
1450 struct fe_priv *np = netdev_priv(dev);
1452 if (dev->mtu <= ETH_DATA_LEN)
1453 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
1455 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
1459 * nv_change_mtu: dev->change_mtu function
1460 * Called with dev_base_lock held for read.
1462 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1464 struct fe_priv *np = netdev_priv(dev);
1467 if (new_mtu < 64 || new_mtu > np->pkt_limit)
1473 /* return early if the buffer sizes will not change */
1474 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1476 if (old_mtu == new_mtu)
1479 /* synchronized against open : rtnl_lock() held by caller */
1480 if (netif_running(dev)) {
1481 u8 __iomem *base = get_hwbase(dev);
1483 * It seems that the nic preloads valid ring entries into an
1484 * internal buffer. The procedure for flushing everything is
1485 * guessed, there is probably a simpler approach.
1486 * Changing the MTU is a rare event, it shouldn't matter.
1488 disable_irq(dev->irq);
1489 spin_lock_bh(&dev->xmit_lock);
1490 spin_lock(&np->lock);
1495 /* drain rx queue */
1498 /* reinit driver view of the rx queue */
1501 /* alloc new rx buffers */
1503 if (nv_alloc_rx(dev)) {
1504 if (!np->in_shutdown)
1505 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1507 /* reinit nic view of the rx queue */
1508 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
1509 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1510 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
1511 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1513 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1514 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1515 base + NvRegRingSizes);
1517 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
1520 /* restart rx engine */
1523 spin_unlock(&np->lock);
1524 spin_unlock_bh(&dev->xmit_lock);
1525 enable_irq(dev->irq);
1530 static void nv_copy_mac_to_hw(struct net_device *dev)
1532 u8 __iomem *base = get_hwbase(dev);
1535 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1536 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1537 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1539 writel(mac[0], base + NvRegMacAddrA);
1540 writel(mac[1], base + NvRegMacAddrB);
1544 * nv_set_mac_address: dev->set_mac_address function
1545 * Called with rtnl_lock() held.
1547 static int nv_set_mac_address(struct net_device *dev, void *addr)
1549 struct fe_priv *np = netdev_priv(dev);
1550 struct sockaddr *macaddr = (struct sockaddr*)addr;
1552 if(!is_valid_ether_addr(macaddr->sa_data))
1553 return -EADDRNOTAVAIL;
1555 /* synchronized against open : rtnl_lock() held by caller */
1556 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
1558 if (netif_running(dev)) {
1559 spin_lock_bh(&dev->xmit_lock);
1560 spin_lock_irq(&np->lock);
1562 /* stop rx engine */
1565 /* set mac address */
1566 nv_copy_mac_to_hw(dev);
1568 /* restart rx engine */
1570 spin_unlock_irq(&np->lock);
1571 spin_unlock_bh(&dev->xmit_lock);
1573 nv_copy_mac_to_hw(dev);
1579 * nv_set_multicast: dev->set_multicast function
1580 * Called with dev->xmit_lock held.
1582 static void nv_set_multicast(struct net_device *dev)
1584 struct fe_priv *np = netdev_priv(dev);
1585 u8 __iomem *base = get_hwbase(dev);
1590 memset(addr, 0, sizeof(addr));
1591 memset(mask, 0, sizeof(mask));
1593 if (dev->flags & IFF_PROMISC) {
1594 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1595 pff = NVREG_PFF_PROMISC;
1597 pff = NVREG_PFF_MYADDR;
1599 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1603 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1604 if (dev->flags & IFF_ALLMULTI) {
1605 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1607 struct dev_mc_list *walk;
1609 walk = dev->mc_list;
1610 while (walk != NULL) {
1612 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1613 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1621 addr[0] = alwaysOn[0];
1622 addr[1] = alwaysOn[1];
1623 mask[0] = alwaysOn[0] | alwaysOff[0];
1624 mask[1] = alwaysOn[1] | alwaysOff[1];
1627 addr[0] |= NVREG_MCASTADDRA_FORCE;
1628 pff |= NVREG_PFF_ALWAYS;
1629 spin_lock_irq(&np->lock);
1631 writel(addr[0], base + NvRegMulticastAddrA);
1632 writel(addr[1], base + NvRegMulticastAddrB);
1633 writel(mask[0], base + NvRegMulticastMaskA);
1634 writel(mask[1], base + NvRegMulticastMaskB);
1635 writel(pff, base + NvRegPacketFilterFlags);
1636 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1639 spin_unlock_irq(&np->lock);
1643 * nv_update_linkspeed: Setup the MAC according to the link partner
1644 * @dev: Network device to be configured
1646 * The function queries the PHY and checks if there is a link partner.
1647 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
1648 * set to 10 MBit HD.
1650 * The function returns 0 if there is no link partner and 1 if there is
1651 * a good link partner.
1653 static int nv_update_linkspeed(struct net_device *dev)
1655 struct fe_priv *np = netdev_priv(dev);
1656 u8 __iomem *base = get_hwbase(dev);
1658 int newls = np->linkspeed;
1659 int newdup = np->duplex;
1662 u32 control_1000, status_1000, phyreg;
1664 /* BMSR_LSTATUS is latched, read it twice:
1665 * we want the current value.
1667 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1668 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1670 if (!(mii_status & BMSR_LSTATUS)) {
1671 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1673 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1679 if (np->autoneg == 0) {
1680 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: autoneg off, PHY set to 0x%04x.\n",
1681 dev->name, np->fixed_mode);
1682 if (np->fixed_mode & LPA_100FULL) {
1683 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1685 } else if (np->fixed_mode & LPA_100HALF) {
1686 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1688 } else if (np->fixed_mode & LPA_10FULL) {
1689 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1692 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1698 /* check auto negotiation is complete */
1699 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1700 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1701 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1704 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1709 if (np->gigabit == PHY_GIGABIT) {
1710 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1711 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1713 if ((control_1000 & ADVERTISE_1000FULL) &&
1714 (status_1000 & LPA_1000FULL)) {
1715 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1717 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1723 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1724 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1725 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1726 dev->name, adv, lpa);
1728 /* FIXME: handle parallel detection properly */
1730 if (lpa & LPA_100FULL) {
1731 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1733 } else if (lpa & LPA_100HALF) {
1734 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1736 } else if (lpa & LPA_10FULL) {
1737 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1739 } else if (lpa & LPA_10HALF) {
1740 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1743 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1744 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1749 if (np->duplex == newdup && np->linkspeed == newls)
1752 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1753 dev->name, np->linkspeed, np->duplex, newls, newdup);
1755 np->duplex = newdup;
1756 np->linkspeed = newls;
1758 if (np->gigabit == PHY_GIGABIT) {
1759 phyreg = readl(base + NvRegRandomSeed);
1760 phyreg &= ~(0x3FF00);
1761 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1762 phyreg |= NVREG_RNDSEED_FORCE3;
1763 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1764 phyreg |= NVREG_RNDSEED_FORCE2;
1765 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1766 phyreg |= NVREG_RNDSEED_FORCE;
1767 writel(phyreg, base + NvRegRandomSeed);
1770 phyreg = readl(base + NvRegPhyInterface);
1771 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1772 if (np->duplex == 0)
1774 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
1776 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
1778 writel(phyreg, base + NvRegPhyInterface);
1780 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1783 writel(np->linkspeed, base + NvRegLinkSpeed);
1789 static void nv_linkchange(struct net_device *dev)
1791 if (nv_update_linkspeed(dev)) {
1792 if (!netif_carrier_ok(dev)) {
1793 netif_carrier_on(dev);
1794 printk(KERN_INFO "%s: link up.\n", dev->name);
1798 if (netif_carrier_ok(dev)) {
1799 netif_carrier_off(dev);
1800 printk(KERN_INFO "%s: link down.\n", dev->name);
1806 static void nv_link_irq(struct net_device *dev)
1808 u8 __iomem *base = get_hwbase(dev);
1811 miistat = readl(base + NvRegMIIStatus);
1812 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1813 dprintk(KERN_INFO "%s: link change irq, status 0x%x.\n", dev->name, miistat);
1815 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
1817 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1820 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1822 struct net_device *dev = (struct net_device *) data;
1823 struct fe_priv *np = netdev_priv(dev);
1824 u8 __iomem *base = get_hwbase(dev);
1828 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1831 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1832 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1834 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1835 if (!(events & np->irqmask))
1838 spin_lock(&np->lock);
1840 spin_unlock(&np->lock);
1843 if (nv_alloc_rx(dev)) {
1844 spin_lock(&np->lock);
1845 if (!np->in_shutdown)
1846 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1847 spin_unlock(&np->lock);
1850 if (events & NVREG_IRQ_LINK) {
1851 spin_lock(&np->lock);
1853 spin_unlock(&np->lock);
1855 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
1856 spin_lock(&np->lock);
1858 spin_unlock(&np->lock);
1859 np->link_timeout = jiffies + LINK_TIMEOUT;
1861 if (events & (NVREG_IRQ_TX_ERR)) {
1862 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1865 if (events & (NVREG_IRQ_UNKNOWN)) {
1866 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1869 if (i > max_interrupt_work) {
1870 spin_lock(&np->lock);
1871 /* disable interrupts on the nic */
1872 writel(0, base + NvRegIrqMask);
1875 if (!np->in_shutdown)
1876 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1877 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1878 spin_unlock(&np->lock);
1883 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1885 return IRQ_RETVAL(i);
1888 static void nv_do_nic_poll(unsigned long data)
1890 struct net_device *dev = (struct net_device *) data;
1891 struct fe_priv *np = netdev_priv(dev);
1892 u8 __iomem *base = get_hwbase(dev);
1894 disable_irq(dev->irq);
1895 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1897 * reenable interrupts on the nic, we have to do this before calling
1898 * nv_nic_irq because that may decide to do otherwise
1900 writel(np->irqmask, base + NvRegIrqMask);
1902 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1903 enable_irq(dev->irq);
1906 #ifdef CONFIG_NET_POLL_CONTROLLER
1907 static void nv_poll_controller(struct net_device *dev)
1909 nv_do_nic_poll((unsigned long) dev);
1913 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1915 struct fe_priv *np = netdev_priv(dev);
1916 strcpy(info->driver, "forcedeth");
1917 strcpy(info->version, FORCEDETH_VERSION);
1918 strcpy(info->bus_info, pci_name(np->pci_dev));
1921 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1923 struct fe_priv *np = netdev_priv(dev);
1924 wolinfo->supported = WAKE_MAGIC;
1926 spin_lock_irq(&np->lock);
1928 wolinfo->wolopts = WAKE_MAGIC;
1929 spin_unlock_irq(&np->lock);
1932 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
1934 struct fe_priv *np = netdev_priv(dev);
1935 u8 __iomem *base = get_hwbase(dev);
1937 spin_lock_irq(&np->lock);
1938 if (wolinfo->wolopts == 0) {
1939 writel(0, base + NvRegWakeUpFlags);
1942 if (wolinfo->wolopts & WAKE_MAGIC) {
1943 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
1946 spin_unlock_irq(&np->lock);
1950 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1952 struct fe_priv *np = netdev_priv(dev);
1955 spin_lock_irq(&np->lock);
1956 ecmd->port = PORT_MII;
1957 if (!netif_running(dev)) {
1958 /* We do not track link speed / duplex setting if the
1959 * interface is disabled. Force a link check */
1960 nv_update_linkspeed(dev);
1962 switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) {
1963 case NVREG_LINKSPEED_10:
1964 ecmd->speed = SPEED_10;
1966 case NVREG_LINKSPEED_100:
1967 ecmd->speed = SPEED_100;
1969 case NVREG_LINKSPEED_1000:
1970 ecmd->speed = SPEED_1000;
1973 ecmd->duplex = DUPLEX_HALF;
1975 ecmd->duplex = DUPLEX_FULL;
1977 ecmd->autoneg = np->autoneg;
1979 ecmd->advertising = ADVERTISED_MII;
1981 ecmd->advertising |= ADVERTISED_Autoneg;
1982 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1984 adv = np->fixed_mode;
1986 if (adv & ADVERTISE_10HALF)
1987 ecmd->advertising |= ADVERTISED_10baseT_Half;
1988 if (adv & ADVERTISE_10FULL)
1989 ecmd->advertising |= ADVERTISED_10baseT_Full;
1990 if (adv & ADVERTISE_100HALF)
1991 ecmd->advertising |= ADVERTISED_100baseT_Half;
1992 if (adv & ADVERTISE_100FULL)
1993 ecmd->advertising |= ADVERTISED_100baseT_Full;
1994 if (np->autoneg && np->gigabit == PHY_GIGABIT) {
1995 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1996 if (adv & ADVERTISE_1000FULL)
1997 ecmd->advertising |= ADVERTISED_1000baseT_Full;
2000 ecmd->supported = (SUPPORTED_Autoneg |
2001 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2002 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2004 if (np->gigabit == PHY_GIGABIT)
2005 ecmd->supported |= SUPPORTED_1000baseT_Full;
2007 ecmd->phy_address = np->phyaddr;
2008 ecmd->transceiver = XCVR_EXTERNAL;
2010 /* ignore maxtxpkt, maxrxpkt for now */
2011 spin_unlock_irq(&np->lock);
2015 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2017 struct fe_priv *np = netdev_priv(dev);
2019 if (ecmd->port != PORT_MII)
2021 if (ecmd->transceiver != XCVR_EXTERNAL)
2023 if (ecmd->phy_address != np->phyaddr) {
2024 /* TODO: support switching between multiple phys. Should be
2025 * trivial, but not enabled due to lack of test hardware. */
2028 if (ecmd->autoneg == AUTONEG_ENABLE) {
2031 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2032 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
2033 if (np->gigabit == PHY_GIGABIT)
2034 mask |= ADVERTISED_1000baseT_Full;
2036 if ((ecmd->advertising & mask) == 0)
2039 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
2040 /* Note: autonegotiation disable, speed 1000 intentionally
2041 * forbidden - noone should need that. */
2043 if (ecmd->speed != SPEED_10 && ecmd->speed != SPEED_100)
2045 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
2051 spin_lock_irq(&np->lock);
2052 if (ecmd->autoneg == AUTONEG_ENABLE) {
2057 /* advertise only what has been requested */
2058 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2059 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2060 if (ecmd->advertising & ADVERTISED_10baseT_Half)
2061 adv |= ADVERTISE_10HALF;
2062 if (ecmd->advertising & ADVERTISED_10baseT_Full)
2063 adv |= ADVERTISE_10FULL;
2064 if (ecmd->advertising & ADVERTISED_100baseT_Half)
2065 adv |= ADVERTISE_100HALF;
2066 if (ecmd->advertising & ADVERTISED_100baseT_Full)
2067 adv |= ADVERTISE_100FULL;
2068 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2070 if (np->gigabit == PHY_GIGABIT) {
2071 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2072 adv &= ~ADVERTISE_1000FULL;
2073 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
2074 adv |= ADVERTISE_1000FULL;
2075 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
2078 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2079 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2080 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2087 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
2088 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
2089 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
2090 adv |= ADVERTISE_10HALF;
2091 if (ecmd->speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
2092 adv |= ADVERTISE_10FULL;
2093 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
2094 adv |= ADVERTISE_100HALF;
2095 if (ecmd->speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
2096 adv |= ADVERTISE_100FULL;
2097 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
2098 np->fixed_mode = adv;
2100 if (np->gigabit == PHY_GIGABIT) {
2101 adv = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
2102 adv &= ~ADVERTISE_1000FULL;
2103 mii_rw(dev, np->phyaddr, MII_1000BT_CR, adv);
2106 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2107 bmcr |= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_FULLDPLX);
2108 if (adv & (ADVERTISE_10FULL|ADVERTISE_100FULL))
2109 bmcr |= BMCR_FULLDPLX;
2110 if (adv & (ADVERTISE_100HALF|ADVERTISE_100FULL))
2111 bmcr |= BMCR_SPEED100;
2112 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2114 if (netif_running(dev)) {
2115 /* Wait a bit and then reconfigure the nic. */
2120 spin_unlock_irq(&np->lock);
2125 #define FORCEDETH_REGS_VER 1
2126 #define FORCEDETH_REGS_SIZE 0x400 /* 256 32-bit registers */
2128 static int nv_get_regs_len(struct net_device *dev)
2130 return FORCEDETH_REGS_SIZE;
2133 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
2135 struct fe_priv *np = netdev_priv(dev);
2136 u8 __iomem *base = get_hwbase(dev);
2140 regs->version = FORCEDETH_REGS_VER;
2141 spin_lock_irq(&np->lock);
2142 for (i=0;i<FORCEDETH_REGS_SIZE/sizeof(u32);i++)
2143 rbuf[i] = readl(base + i*sizeof(u32));
2144 spin_unlock_irq(&np->lock);
2147 static int nv_nway_reset(struct net_device *dev)
2149 struct fe_priv *np = netdev_priv(dev);
2152 spin_lock_irq(&np->lock);
2156 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
2157 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
2158 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
2164 spin_unlock_irq(&np->lock);
2169 static struct ethtool_ops ops = {
2170 .get_drvinfo = nv_get_drvinfo,
2171 .get_link = ethtool_op_get_link,
2172 .get_wol = nv_get_wol,
2173 .set_wol = nv_set_wol,
2174 .get_settings = nv_get_settings,
2175 .set_settings = nv_set_settings,
2176 .get_regs_len = nv_get_regs_len,
2177 .get_regs = nv_get_regs,
2178 .nway_reset = nv_nway_reset,
2179 .get_perm_addr = ethtool_op_get_perm_addr,
2182 static int nv_open(struct net_device *dev)
2184 struct fe_priv *np = netdev_priv(dev);
2185 u8 __iomem *base = get_hwbase(dev);
2188 dprintk(KERN_DEBUG "nv_open: begin\n");
2190 /* 1) erase previous misconfiguration */
2191 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
2192 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2193 writel(0, base + NvRegMulticastAddrB);
2194 writel(0, base + NvRegMulticastMaskA);
2195 writel(0, base + NvRegMulticastMaskB);
2196 writel(0, base + NvRegPacketFilterFlags);
2198 writel(0, base + NvRegTransmitterControl);
2199 writel(0, base + NvRegReceiverControl);
2201 writel(0, base + NvRegAdapterControl);
2203 /* 2) initialize descriptor rings */
2205 oom = nv_init_ring(dev);
2207 writel(0, base + NvRegLinkSpeed);
2208 writel(0, base + NvRegUnknownTransmitterReg);
2210 writel(0, base + NvRegUnknownSetupReg6);
2212 np->in_shutdown = 0;
2214 /* 3) set mac address */
2215 nv_copy_mac_to_hw(dev);
2217 /* 4) give hw rings */
2218 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
2219 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2220 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
2222 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
2223 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
2224 base + NvRegRingSizes);
2226 /* 5) continue setup */
2227 writel(np->linkspeed, base + NvRegLinkSpeed);
2228 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
2229 writel(np->txrxctl_bits, base + NvRegTxRxControl);
2231 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
2232 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
2233 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
2234 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
2236 writel(0, base + NvRegUnknownSetupReg4);
2237 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2238 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2240 /* 6) continue setup */
2241 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
2242 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
2243 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
2244 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2246 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
2247 get_random_bytes(&i, sizeof(i));
2248 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
2249 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
2250 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
2251 if (poll_interval == -1) {
2252 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
2253 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
2255 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
2258 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
2259 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
2260 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
2261 base + NvRegAdapterControl);
2262 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
2263 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
2264 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
2266 i = readl(base + NvRegPowerState);
2267 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
2268 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
2272 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
2274 writel(0, base + NvRegIrqMask);
2276 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
2277 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
2280 ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
2284 /* ask for interrupts */
2285 writel(np->irqmask, base + NvRegIrqMask);
2287 spin_lock_irq(&np->lock);
2288 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
2289 writel(0, base + NvRegMulticastAddrB);
2290 writel(0, base + NvRegMulticastMaskA);
2291 writel(0, base + NvRegMulticastMaskB);
2292 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
2293 /* One manual link speed update: Interrupts are enabled, future link
2294 * speed changes cause interrupts and are handled by nv_link_irq().
2298 miistat = readl(base + NvRegMIIStatus);
2299 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
2300 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
2302 /* set linkspeed to invalid value, thus force nv_update_linkspeed
2305 ret = nv_update_linkspeed(dev);
2308 netif_start_queue(dev);
2310 netif_carrier_on(dev);
2312 printk("%s: no link during initialization.\n", dev->name);
2313 netif_carrier_off(dev);
2316 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2317 spin_unlock_irq(&np->lock);
2325 static int nv_close(struct net_device *dev)
2327 struct fe_priv *np = netdev_priv(dev);
2330 spin_lock_irq(&np->lock);
2331 np->in_shutdown = 1;
2332 spin_unlock_irq(&np->lock);
2333 synchronize_irq(dev->irq);
2335 del_timer_sync(&np->oom_kick);
2336 del_timer_sync(&np->nic_poll);
2338 netif_stop_queue(dev);
2339 spin_lock_irq(&np->lock);
2344 /* disable interrupts on the nic or we will lock up */
2345 base = get_hwbase(dev);
2346 writel(0, base + NvRegIrqMask);
2348 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
2350 spin_unlock_irq(&np->lock);
2352 free_irq(dev->irq, dev);
2359 /* special op: write back the misordered MAC address - otherwise
2360 * the next nv_probe would see a wrong address.
2362 writel(np->orig_mac[0], base + NvRegMacAddrA);
2363 writel(np->orig_mac[1], base + NvRegMacAddrB);
2365 /* FIXME: power down nic */
2370 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
2372 struct net_device *dev;
2378 dev = alloc_etherdev(sizeof(struct fe_priv));
2383 np = netdev_priv(dev);
2384 np->pci_dev = pci_dev;
2385 spin_lock_init(&np->lock);
2386 SET_MODULE_OWNER(dev);
2387 SET_NETDEV_DEV(dev, &pci_dev->dev);
2389 init_timer(&np->oom_kick);
2390 np->oom_kick.data = (unsigned long) dev;
2391 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
2392 init_timer(&np->nic_poll);
2393 np->nic_poll.data = (unsigned long) dev;
2394 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
2396 err = pci_enable_device(pci_dev);
2398 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
2399 err, pci_name(pci_dev));
2403 pci_set_master(pci_dev);
2405 err = pci_request_regions(pci_dev, DRV_NAME);
2411 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2412 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
2413 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
2414 pci_resource_len(pci_dev, i),
2415 pci_resource_flags(pci_dev, i));
2416 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
2417 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
2418 addr = pci_resource_start(pci_dev, i);
2422 if (i == DEVICE_COUNT_RESOURCE) {
2423 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
2428 /* handle different descriptor versions */
2429 if (id->driver_data & DEV_HAS_HIGH_DMA) {
2430 /* packet format 3: supports 40-bit addressing */
2431 np->desc_ver = DESC_VER_3;
2432 if (pci_set_dma_mask(pci_dev, 0x0000007fffffffffULL)) {
2433 printk(KERN_INFO "forcedeth: 64-bit DMA failed, using 32-bit addressing for device %s.\n",
2436 dev->features |= NETIF_F_HIGHDMA;
2438 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
2439 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
2440 /* packet format 2: supports jumbo frames */
2441 np->desc_ver = DESC_VER_2;
2442 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
2444 /* original packet format */
2445 np->desc_ver = DESC_VER_1;
2446 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
2449 np->pkt_limit = NV_PKTLIMIT_1;
2450 if (id->driver_data & DEV_HAS_LARGEDESC)
2451 np->pkt_limit = NV_PKTLIMIT_2;
2453 if (id->driver_data & DEV_HAS_CHECKSUM) {
2454 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
2455 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG;
2457 dev->features |= NETIF_F_TSO;
2462 np->base = ioremap(addr, NV_PCI_REGSZ);
2465 dev->base_addr = (unsigned long)np->base;
2467 dev->irq = pci_dev->irq;
2469 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2) {
2470 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
2471 sizeof(struct ring_desc) * (RX_RING + TX_RING),
2473 if (!np->rx_ring.orig)
2475 np->tx_ring.orig = &np->rx_ring.orig[RX_RING];
2477 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
2478 sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2480 if (!np->rx_ring.ex)
2482 np->tx_ring.ex = &np->rx_ring.ex[RX_RING];
2485 dev->open = nv_open;
2486 dev->stop = nv_close;
2487 dev->hard_start_xmit = nv_start_xmit;
2488 dev->get_stats = nv_get_stats;
2489 dev->change_mtu = nv_change_mtu;
2490 dev->set_mac_address = nv_set_mac_address;
2491 dev->set_multicast_list = nv_set_multicast;
2492 #ifdef CONFIG_NET_POLL_CONTROLLER
2493 dev->poll_controller = nv_poll_controller;
2495 SET_ETHTOOL_OPS(dev, &ops);
2496 dev->tx_timeout = nv_tx_timeout;
2497 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
2499 pci_set_drvdata(pci_dev, dev);
2501 /* read the mac address */
2502 base = get_hwbase(dev);
2503 np->orig_mac[0] = readl(base + NvRegMacAddrA);
2504 np->orig_mac[1] = readl(base + NvRegMacAddrB);
2506 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
2507 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
2508 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
2509 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
2510 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
2511 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
2512 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2514 if (!is_valid_ether_addr(dev->perm_addr)) {
2516 * Bad mac address. At least one bios sets the mac address
2517 * to 01:23:45:67:89:ab
2519 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
2521 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2522 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2523 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
2524 dev->dev_addr[0] = 0x00;
2525 dev->dev_addr[1] = 0x00;
2526 dev->dev_addr[2] = 0x6c;
2527 get_random_bytes(&dev->dev_addr[3], 3);
2530 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
2531 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2532 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2535 writel(0, base + NvRegWakeUpFlags);
2538 if (np->desc_ver == DESC_VER_1) {
2539 np->tx_flags = NV_TX_VALID;
2541 np->tx_flags = NV_TX2_VALID;
2543 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
2544 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
2546 np->irqmask = NVREG_IRQMASK_CPU;
2548 if (id->driver_data & DEV_NEED_TIMERIRQ)
2549 np->irqmask |= NVREG_IRQ_TIMER;
2550 if (id->driver_data & DEV_NEED_LINKTIMER) {
2551 dprintk(KERN_INFO "%s: link timer on.\n", pci_name(pci_dev));
2552 np->need_linktimer = 1;
2553 np->link_timeout = jiffies + LINK_TIMEOUT;
2555 dprintk(KERN_INFO "%s: link timer off.\n", pci_name(pci_dev));
2556 np->need_linktimer = 0;
2559 /* find a suitable phy */
2560 for (i = 1; i < 32; i++) {
2563 spin_lock_irq(&np->lock);
2564 id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ);
2565 spin_unlock_irq(&np->lock);
2566 if (id1 < 0 || id1 == 0xffff)
2568 spin_lock_irq(&np->lock);
2569 id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ);
2570 spin_unlock_irq(&np->lock);
2571 if (id2 < 0 || id2 == 0xffff)
2574 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
2575 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
2576 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
2577 pci_name(pci_dev), id1, id2, i);
2579 np->phy_oui = id1 | id2;
2583 /* PHY in isolate mode? No phy attached and user wants to
2584 * test loopback? Very odd, but can be correct.
2586 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
2595 /* set default link speed settings */
2596 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
2600 err = register_netdev(dev);
2602 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
2605 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
2606 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
2612 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2613 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
2614 np->rx_ring.orig, np->ring_addr);
2616 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING),
2617 np->rx_ring.ex, np->ring_addr);
2618 pci_set_drvdata(pci_dev, NULL);
2620 iounmap(get_hwbase(dev));
2622 pci_release_regions(pci_dev);
2624 pci_disable_device(pci_dev);
2631 static void __devexit nv_remove(struct pci_dev *pci_dev)
2633 struct net_device *dev = pci_get_drvdata(pci_dev);
2634 struct fe_priv *np = netdev_priv(dev);
2636 unregister_netdev(dev);
2638 /* free all structures */
2639 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
2640 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring.orig, np->ring_addr);
2642 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (RX_RING + TX_RING), np->rx_ring.ex, np->ring_addr);
2643 iounmap(get_hwbase(dev));
2644 pci_release_regions(pci_dev);
2645 pci_disable_device(pci_dev);
2647 pci_set_drvdata(pci_dev, NULL);
2650 static struct pci_device_id pci_tbl[] = {
2651 { /* nForce Ethernet Controller */
2652 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
2653 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2655 { /* nForce2 Ethernet Controller */
2656 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
2657 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2659 { /* nForce3 Ethernet Controller */
2660 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
2661 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
2663 { /* nForce3 Ethernet Controller */
2664 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
2665 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2667 { /* nForce3 Ethernet Controller */
2668 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
2669 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2671 { /* nForce3 Ethernet Controller */
2672 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
2673 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2675 { /* nForce3 Ethernet Controller */
2676 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
2677 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
2679 { /* CK804 Ethernet Controller */
2680 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
2681 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2683 { /* CK804 Ethernet Controller */
2684 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
2685 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2687 { /* MCP04 Ethernet Controller */
2688 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
2689 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2691 { /* MCP04 Ethernet Controller */
2692 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
2693 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2695 { /* MCP51 Ethernet Controller */
2696 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
2697 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2699 { /* MCP51 Ethernet Controller */
2700 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
2701 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA,
2703 { /* MCP55 Ethernet Controller */
2704 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
2705 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2707 { /* MCP55 Ethernet Controller */
2708 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
2709 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA,
2714 static struct pci_driver driver = {
2715 .name = "forcedeth",
2716 .id_table = pci_tbl,
2718 .remove = __devexit_p(nv_remove),
2722 static int __init init_nic(void)
2724 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
2725 return pci_module_init(&driver);
2728 static void __exit exit_nic(void)
2730 pci_unregister_driver(&driver);
2733 module_param(max_interrupt_work, int, 0);
2734 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2735 module_param(optimization_mode, int, 0);
2736 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer.");
2737 module_param(poll_interval, int, 0);
2738 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
2740 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2741 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2742 MODULE_LICENSE("GPL");
2744 MODULE_DEVICE_TABLE(pci, pci_tbl);
2746 module_init(init_nic);
2747 module_exit(exit_nic);