drivers/net/e1000e/ich8lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 82562G-2 10/100 Network Connection
  31  * 82562GT 10/100 Network Connection
  32  * 82562GT-2 10/100 Network Connection
  33  * 82562V 10/100 Network Connection
  34  * 82562V-2 10/100 Network Connection
  35  * 82566DC-2 Gigabit Network Connection
  36  * 82566DC Gigabit Network Connection
  37  * 82566DM-2 Gigabit Network Connection
  38  * 82566DM Gigabit Network Connection
  39  * 82566MC Gigabit Network Connection
  40  * 82566MM Gigabit Network Connection
  41  * 82567LM Gigabit Network Connection
  42  * 82567LF Gigabit Network Connection
  43  * 82567LM-2 Gigabit Network Connection
  44  * 82567LF-2 Gigabit Network Connection
  45  * 82567V-2 Gigabit Network Connection
  46  * 82562GT-3 10/100 Network Connection
  47  */
  48
  49 #include <linux/netdevice.h>
  50 #include <linux/ethtool.h>
  51 #include <linux/delay.h>
  52 #include <linux/pci.h>
  53
  54 #include "e1000.h"
  55
  56 #define ICH_FLASH_GFPREG                0x0000
  57 #define ICH_FLASH_HSFSTS                0x0004
  58 #define ICH_FLASH_HSFCTL                0x0006
  59 #define ICH_FLASH_FADDR                 0x0008
  60 #define ICH_FLASH_FDATA0                0x0010
  61 #define ICH_FLASH_PR0                   0x0074
  62
  63 #define ICH_FLASH_READ_COMMAND_TIMEOUT  500
  64 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
  65 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
  66 #define ICH_FLASH_LINEAR_ADDR_MASK      0x00FFFFFF
  67 #define ICH_FLASH_CYCLE_REPEAT_COUNT    10
  68
  69 #define ICH_CYCLE_READ                  0
  70 #define ICH_CYCLE_WRITE                 2
  71 #define ICH_CYCLE_ERASE                 3
  72
  73 #define FLASH_GFPREG_BASE_MASK          0x1FFF
  74 #define FLASH_SECTOR_ADDR_SHIFT         12
  75
  76 #define ICH_FLASH_SEG_SIZE_256          256
  77 #define ICH_FLASH_SEG_SIZE_4K           4096
  78 #define ICH_FLASH_SEG_SIZE_8K           8192
  79 #define ICH_FLASH_SEG_SIZE_64K          65536
  80
  81
  82 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
  83
  84 #define E1000_ICH_MNG_IAMT_MODE         0x2
  85
  86 #define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
  87                                  (ID_LED_DEF1_OFF2 <<  8) | \
  88                                  (ID_LED_DEF1_ON2  <<  4) | \
  89                                  (ID_LED_DEF1_DEF2))
  90
  91 #define E1000_ICH_NVM_SIG_WORD          0x13
  92 #define E1000_ICH_NVM_SIG_MASK          0xC000
  93
  94 #define E1000_ICH8_LAN_INIT_TIMEOUT     1500
  95
  96 #define E1000_FEXTNVM_SW_CONFIG         1
  97 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
  98
  99 #define PCIE_ICH8_SNOOP_ALL             PCIE_NO_SNOOP_ALL
 100
 101 #define E1000_ICH_RAR_ENTRIES           7
 102
 103 #define PHY_PAGE_SHIFT 5
 104 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
 105                            ((reg) & MAX_PHY_REG_ADDRESS))
 106 #define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
 107 #define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
 108
 109 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS    0x0002
 110 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
 111 #define IGP3_VR_CTRL_MODE_SHUTDOWN      0x0200
 112
 113 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
 114 /* Offset 04h HSFSTS */
 115 union ich8_hws_flash_status {
 116         struct ich8_hsfsts {
 117                 u16 flcdone    :1; /* bit 0 Flash Cycle Done */
 118                 u16 flcerr     :1; /* bit 1 Flash Cycle Error */
 119                 u16 dael       :1; /* bit 2 Direct Access error Log */
 120                 u16 berasesz   :2; /* bit 4:3 Sector Erase Size */
 121                 u16 flcinprog  :1; /* bit 5 flash cycle in Progress */
 122                 u16 reserved1  :2; /* bit 13:6 Reserved */
 123                 u16 reserved2  :6; /* bit 13:6 Reserved */
 124                 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
 125                 u16 flockdn    :1; /* bit 15 Flash Config Lock-Down */
 126         } hsf_status;
 127         u16 regval;
 128 };
 129
 130 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
 131 /* Offset 06h FLCTL */
 132 union ich8_hws_flash_ctrl {
 133         struct ich8_hsflctl {
 134                 u16 flcgo      :1;   /* 0 Flash Cycle Go */
 135                 u16 flcycle    :2;   /* 2:1 Flash Cycle */
 136                 u16 reserved   :5;   /* 7:3 Reserved  */
 137                 u16 fldbcount  :2;   /* 9:8 Flash Data Byte Count */
 138                 u16 flockdn    :6;   /* 15:10 Reserved */
 139         } hsf_ctrl;
 140         u16 regval;
 141 };
 142
 143 /* ICH Flash Region Access Permissions */
 144 union ich8_hws_flash_regacc {
 145         struct ich8_flracc {
 146                 u32 grra      :8; /* 0:7 GbE region Read Access */
 147                 u32 grwa      :8; /* 8:15 GbE region Write Access */
 148                 u32 gmrag     :8; /* 23:16 GbE Master Read Access Grant */
 149                 u32 gmwag     :8; /* 31:24 GbE Master Write Access Grant */
 150         } hsf_flregacc;
 151         u16 regval;
 152 };
 153
 154 /* ICH Flash Protected Region */
 155 union ich8_flash_protected_range {
 156         struct ich8_pr {
 157                 u32 base:13;     /* 0:12 Protected Range Base */
 158                 u32 reserved1:2; /* 13:14 Reserved */
 159                 u32 rpe:1;       /* 15 Read Protection Enable */
 160                 u32 limit:13;    /* 16:28 Protected Range Limit */
 161                 u32 reserved2:2; /* 29:30 Reserved */
 162                 u32 wpe:1;       /* 31 Write Protection Enable */
 163         } range;
 164         u32 regval;
 165 };
 166
 167 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
 168 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
 169 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
 170 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw);
 171 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
 172 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
 173                                                 u32 offset, u8 byte);
 174 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
 175                                          u16 *data);
 176 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
 177                                          u8 size, u16 *data);
 178 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
 179 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
 180
 181 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
 182 {
 183         return readw(hw->flash_address + reg);
 184 }
 185
 186 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
 187 {
 188         return readl(hw->flash_address + reg);
 189 }
 190
 191 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
 192 {
 193         writew(val, hw->flash_address + reg);
 194 }
 195
 196 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
 197 {
 198         writel(val, hw->flash_address + reg);
 199 }
 200
 201 #define er16flash(reg)          __er16flash(hw, (reg))
 202 #define er32flash(reg)          __er32flash(hw, (reg))
 203 #define ew16flash(reg,val)      __ew16flash(hw, (reg), (val))
 204 #define ew32flash(reg,val)      __ew32flash(hw, (reg), (val))
 205
 206 /**
 207  *  e1000_init_phy_params_ich8lan - Initialize PHY function pointers
 208  *  @hw: pointer to the HW structure
 209  *
 210  *  Initialize family-specific PHY parameters and function pointers.
 211  **/
 212 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
 213 {
 214         struct e1000_phy_info *phy = &hw->phy;
 215         s32 ret_val;
 216         u16 i = 0;
 217
 218         phy->addr                       = 1;
 219         phy->reset_delay_us             = 100;
 220
 221         /*
 222          * We may need to do this twice - once for IGP and if that fails,
 223          * we'll set BM func pointers and try again
 224          */
 225         ret_val = e1000e_determine_phy_address(hw);
 226         if (ret_val) {
 227                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 228                 hw->phy.ops.read_phy_reg  = e1000e_read_phy_reg_bm;
 229                 ret_val = e1000e_determine_phy_address(hw);
 230                 if (ret_val)
 231                         return ret_val;
 232         }
 233
 234         phy->id = 0;
 235         while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
 236                (i++ < 100)) {
 237                 msleep(1);
 238                 ret_val = e1000e_get_phy_id(hw);
 239                 if (ret_val)
 240                         return ret_val;
 241         }
 242
 243         /* Verify phy id */
 244         switch (phy->id) {
 245         case IGP03E1000_E_PHY_ID:
 246                 phy->type = e1000_phy_igp_3;
 247                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 248                 break;
 249         case IFE_E_PHY_ID:
 250         case IFE_PLUS_E_PHY_ID:
 251         case IFE_C_E_PHY_ID:
 252                 phy->type = e1000_phy_ife;
 253                 phy->autoneg_mask = E1000_ALL_NOT_GIG;
 254                 break;
 255         case BME1000_E_PHY_ID:
 256                 phy->type = e1000_phy_bm;
 257                 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 258                 hw->phy.ops.read_phy_reg = e1000e_read_phy_reg_bm;
 259                 hw->phy.ops.write_phy_reg = e1000e_write_phy_reg_bm;
 260                 hw->phy.ops.commit_phy = e1000e_phy_sw_reset;
 261                 break;
 262         default:
 263                 return -E1000_ERR_PHY;
 264                 break;
 265         }
 266
 267         return 0;
 268 }
 269
 270 /**
 271  *  e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
 272  *  @hw: pointer to the HW structure
 273  *
 274  *  Initialize family-specific NVM parameters and function
 275  *  pointers.
 276  **/
 277 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
 278 {
 279         struct e1000_nvm_info *nvm = &hw->nvm;
 280         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 281         u32 gfpreg;
 282         u32 sector_base_addr;
 283         u32 sector_end_addr;
 284         u16 i;
 285
 286         /* Can't read flash registers if the register set isn't mapped. */
 287         if (!hw->flash_address) {
 288                 hw_dbg(hw, "ERROR: Flash registers not mapped\n");
 289                 return -E1000_ERR_CONFIG;
 290         }
 291
 292         nvm->type = e1000_nvm_flash_sw;
 293
 294         gfpreg = er32flash(ICH_FLASH_GFPREG);
 295
 296         /*
 297          * sector_X_addr is a "sector"-aligned address (4096 bytes)
 298          * Add 1 to sector_end_addr since this sector is included in
 299          * the overall size.
 300          */
 301         sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
 302         sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
 303
 304         /* flash_base_addr is byte-aligned */
 305         nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
 306
 307         /*
 308          * find total size of the NVM, then cut in half since the total
 309          * size represents two separate NVM banks.
 310          */
 311         nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
 312                                 << FLASH_SECTOR_ADDR_SHIFT;
 313         nvm->flash_bank_size /= 2;
 314         /* Adjust to word count */
 315         nvm->flash_bank_size /= sizeof(u16);
 316
 317         nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
 318
 319         /* Clear shadow ram */
 320         for (i = 0; i < nvm->word_size; i++) {
 321                 dev_spec->shadow_ram[i].modified = 0;
 322                 dev_spec->shadow_ram[i].value    = 0xFFFF;
 323         }
 324
 325         return 0;
 326 }
 327
 328 /**
 329  *  e1000_init_mac_params_ich8lan - Initialize MAC function pointers
 330  *  @hw: pointer to the HW structure
 331  *
 332  *  Initialize family-specific MAC parameters and function
 333  *  pointers.
 334  **/
 335 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
 336 {
 337         struct e1000_hw *hw = &adapter->hw;
 338         struct e1000_mac_info *mac = &hw->mac;
 339
 340         /* Set media type function pointer */
 341         hw->phy.media_type = e1000_media_type_copper;
 342
 343         /* Set mta register count */
 344         mac->mta_reg_count = 32;
 345         /* Set rar entry count */
 346         mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
 347         if (mac->type == e1000_ich8lan)
 348                 mac->rar_entry_count--;
 349         /* Set if manageability features are enabled. */
 350         mac->arc_subsystem_valid = 1;
 351
 352         /* Enable PCS Lock-loss workaround for ICH8 */
 353         if (mac->type == e1000_ich8lan)
 354                 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, 1);
 355
 356         return 0;
 357 }
 358
 359 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
 360 {
 361         struct e1000_hw *hw = &adapter->hw;
 362         s32 rc;
 363
 364         rc = e1000_init_mac_params_ich8lan(adapter);
 365         if (rc)
 366                 return rc;
 367
 368         rc = e1000_init_nvm_params_ich8lan(hw);
 369         if (rc)
 370                 return rc;
 371
 372         rc = e1000_init_phy_params_ich8lan(hw);
 373         if (rc)
 374                 return rc;
 375
 376         if ((adapter->hw.mac.type == e1000_ich8lan) &&
 377             (adapter->hw.phy.type == e1000_phy_igp_3))
 378                 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
 379
 380         return 0;
 381 }
 382
 383 static DEFINE_MUTEX(nvm_mutex);
 384 static pid_t nvm_owner = -1;
 385
 386 /**
 387  *  e1000_acquire_swflag_ich8lan - Acquire software control flag
 388  *  @hw: pointer to the HW structure
 389  *
 390  *  Acquires the software control flag for performing NVM and PHY
 391  *  operations.  This is a function pointer entry point only called by
 392  *  read/write routines for the PHY and NVM parts.
 393  **/
 394 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
 395 {
 396         u32 extcnf_ctrl;
 397         u32 timeout = PHY_CFG_TIMEOUT;
 398
 399         WARN_ON(preempt_count());
 400
 401         if (!mutex_trylock(&nvm_mutex)) {
 402                 WARN(1, KERN_ERR "e1000e mutex contention. Owned by pid %d\n",
 403                      nvm_owner);
 404                 mutex_lock(&nvm_mutex);
 405         }
 406         nvm_owner = current->pid;
 407
 408         while (timeout) {
 409                 extcnf_ctrl = er32(EXTCNF_CTRL);
 410                 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
 411                 ew32(EXTCNF_CTRL, extcnf_ctrl);
 412
 413                 extcnf_ctrl = er32(EXTCNF_CTRL);
 414                 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
 415                         break;
 416                 mdelay(1);
 417                 timeout--;
 418         }
 419
 420         if (!timeout) {
 421                 hw_dbg(hw, "FW or HW has locked the resource for too long.\n");
 422                 nvm_owner = -1;
 423                 mutex_unlock(&nvm_mutex);
 424                 return -E1000_ERR_CONFIG;
 425         }
 426
 427         return 0;
 428 }
 429
 430 /**
 431  *  e1000_release_swflag_ich8lan - Release software control flag
 432  *  @hw: pointer to the HW structure
 433  *
 434  *  Releases the software control flag for performing NVM and PHY operations.
 435  *  This is a function pointer entry point only called by read/write
 436  *  routines for the PHY and NVM parts.
 437  **/
 438 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
 439 {
 440         u32 extcnf_ctrl;
 441
 442         extcnf_ctrl = er32(EXTCNF_CTRL);
 443         extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
 444         ew32(EXTCNF_CTRL, extcnf_ctrl);
 445
 446         nvm_owner = -1;
 447         mutex_unlock(&nvm_mutex);
 448 }
 449
 450 /**
 451  *  e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
 452  *  @hw: pointer to the HW structure
 453  *
 454  *  Checks if firmware is blocking the reset of the PHY.
 455  *  This is a function pointer entry point only called by
 456  *  reset routines.
 457  **/
 458 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
 459 {
 460         u32 fwsm;
 461
 462         fwsm = er32(FWSM);
 463
 464         return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
 465 }
 466
 467 /**
 468  *  e1000_phy_force_speed_duplex_ich8lan - Force PHY speed & duplex
 469  *  @hw: pointer to the HW structure
 470  *
 471  *  Forces the speed and duplex settings of the PHY.
 472  *  This is a function pointer entry point only called by
 473  *  PHY setup routines.
 474  **/
 475 static s32 e1000_phy_force_speed_duplex_ich8lan(struct e1000_hw *hw)
 476 {
 477         struct e1000_phy_info *phy = &hw->phy;
 478         s32 ret_val;
 479         u16 data;
 480         bool link;
 481
 482         if (phy->type != e1000_phy_ife) {
 483                 ret_val = e1000e_phy_force_speed_duplex_igp(hw);
 484                 return ret_val;
 485         }
 486
 487         ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
 488         if (ret_val)
 489                 return ret_val;
 490
 491         e1000e_phy_force_speed_duplex_setup(hw, &data);
 492
 493         ret_val = e1e_wphy(hw, PHY_CONTROL, data);
 494         if (ret_val)
 495                 return ret_val;
 496
 497         /* Disable MDI-X support for 10/100 */
 498         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 499         if (ret_val)
 500                 return ret_val;
 501
 502         data &= ~IFE_PMC_AUTO_MDIX;
 503         data &= ~IFE_PMC_FORCE_MDIX;
 504
 505         ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
 506         if (ret_val)
 507                 return ret_val;
 508
 509         hw_dbg(hw, "IFE PMC: %X\n", data);
 510
 511         udelay(1);
 512
 513         if (phy->autoneg_wait_to_complete) {
 514                 hw_dbg(hw, "Waiting for forced speed/duplex link on IFE phy.\n");
 515
 516                 ret_val = e1000e_phy_has_link_generic(hw,
 517                                                      PHY_FORCE_LIMIT,
 518                                                      100000,
 519                                                      &link);
 520                 if (ret_val)
 521                         return ret_val;
 522
 523                 if (!link)
 524                         hw_dbg(hw, "Link taking longer than expected.\n");
 525
 526                 /* Try once more */
 527                 ret_val = e1000e_phy_has_link_generic(hw,
 528                                                      PHY_FORCE_LIMIT,
 529                                                      100000,
 530                                                      &link);
 531                 if (ret_val)
 532                         return ret_val;
 533         }
 534
 535         return 0;
 536 }
 537
 538 /**
 539  *  e1000_phy_hw_reset_ich8lan - Performs a PHY reset
 540  *  @hw: pointer to the HW structure
 541  *
 542  *  Resets the PHY
 543  *  This is a function pointer entry point called by drivers
 544  *  or other shared routines.
 545  **/
 546 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
 547 {
 548         struct e1000_phy_info *phy = &hw->phy;
 549         u32 i;
 550         u32 data, cnf_size, cnf_base_addr, sw_cfg_mask;
 551         s32 ret_val;
 552         u16 loop = E1000_ICH8_LAN_INIT_TIMEOUT;
 553         u16 word_addr, reg_data, reg_addr, phy_page = 0;
 554
 555         ret_val = e1000e_phy_hw_reset_generic(hw);
 556         if (ret_val)
 557                 return ret_val;
 558
 559         /*
 560          * Initialize the PHY from the NVM on ICH platforms.  This
 561          * is needed due to an issue where the NVM configuration is
 562          * not properly autoloaded after power transitions.
 563          * Therefore, after each PHY reset, we will load the
 564          * configuration data out of the NVM manually.
 565          */
 566         if (hw->mac.type == e1000_ich8lan && phy->type == e1000_phy_igp_3) {
 567                 struct e1000_adapter *adapter = hw->adapter;
 568
 569                 /* Check if SW needs configure the PHY */
 570                 if ((adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
 571                     (adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_M))
 572                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
 573                 else
 574                         sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
 575
 576                 data = er32(FEXTNVM);
 577                 if (!(data & sw_cfg_mask))
 578                         return 0;
 579
 580                 /* Wait for basic configuration completes before proceeding*/
 581                 do {
 582                         data = er32(STATUS);
 583                         data &= E1000_STATUS_LAN_INIT_DONE;
 584                         udelay(100);
 585                 } while ((!data) && --loop);
 586
 587                 /*
 588                  * If basic configuration is incomplete before the above loop
 589                  * count reaches 0, loading the configuration from NVM will
 590                  * leave the PHY in a bad state possibly resulting in no link.
 591                  */
 592                 if (loop == 0) {
 593                         hw_dbg(hw, "LAN_INIT_DONE not set, increase timeout\n");
 594                 }
 595
 596                 /* Clear the Init Done bit for the next init event */
 597                 data = er32(STATUS);
 598                 data &= ~E1000_STATUS_LAN_INIT_DONE;
 599                 ew32(STATUS, data);
 600
 601                 /*
 602                  * Make sure HW does not configure LCD from PHY
 603                  * extended configuration before SW configuration
 604                  */
 605                 data = er32(EXTCNF_CTRL);
 606                 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
 607                         return 0;
 608
 609                 cnf_size = er32(EXTCNF_SIZE);
 610                 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
 611                 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
 612                 if (!cnf_size)
 613                         return 0;
 614
 615                 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
 616                 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
 617
 618                 /* Configure LCD from extended configuration region. */
 619
 620                 /* cnf_base_addr is in DWORD */
 621                 word_addr = (u16)(cnf_base_addr << 1);
 622
 623                 for (i = 0; i < cnf_size; i++) {
 624                         ret_val = e1000_read_nvm(hw,
 625                                                 (word_addr + i * 2),
 626                                                 1,
 627                                                 &reg_data);
 628                         if (ret_val)
 629                                 return ret_val;
 630
 631                         ret_val = e1000_read_nvm(hw,
 632                                                 (word_addr + i * 2 + 1),
 633                                                 1,
 634                                                 &reg_addr);
 635                         if (ret_val)
 636                                 return ret_val;
 637
 638                         /* Save off the PHY page for future writes. */
 639                         if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
 640                                 phy_page = reg_data;
 641                                 continue;
 642                         }
 643
 644                         reg_addr |= phy_page;
 645
 646                         ret_val = e1e_wphy(hw, (u32)reg_addr, reg_data);
 647                         if (ret_val)
 648                                 return ret_val;
 649                 }
 650         }
 651
 652         return 0;
 653 }
 654
 655 /**
 656  *  e1000_get_phy_info_ife_ich8lan - Retrieves various IFE PHY states
 657  *  @hw: pointer to the HW structure
 658  *
 659  *  Populates "phy" structure with various feature states.
 660  *  This function is only called by other family-specific
 661  *  routines.
 662  **/
 663 static s32 e1000_get_phy_info_ife_ich8lan(struct e1000_hw *hw)
 664 {
 665         struct e1000_phy_info *phy = &hw->phy;
 666         s32 ret_val;
 667         u16 data;
 668         bool link;
 669
 670         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
 671         if (ret_val)
 672                 return ret_val;
 673
 674         if (!link) {
 675                 hw_dbg(hw, "Phy info is only valid if link is up\n");
 676                 return -E1000_ERR_CONFIG;
 677         }
 678
 679         ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
 680         if (ret_val)
 681                 return ret_val;
 682         phy->polarity_correction = (!(data & IFE_PSC_AUTO_POLARITY_DISABLE));
 683
 684         if (phy->polarity_correction) {
 685                 ret_val = e1000_check_polarity_ife_ich8lan(hw);
 686                 if (ret_val)
 687                         return ret_val;
 688         } else {
 689                 /* Polarity is forced */
 690                 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
 691                                       ? e1000_rev_polarity_reversed
 692                                       : e1000_rev_polarity_normal;
 693         }
 694
 695         ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
 696         if (ret_val)
 697                 return ret_val;
 698
 699         phy->is_mdix = (data & IFE_PMC_MDIX_STATUS);
 700
 701         /* The following parameters are undefined for 10/100 operation. */
 702         phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
 703         phy->local_rx = e1000_1000t_rx_status_undefined;
 704         phy->remote_rx = e1000_1000t_rx_status_undefined;
 705
 706         return 0;
 707 }
 708
 709 /**
 710  *  e1000_get_phy_info_ich8lan - Calls appropriate PHY type get_phy_info
 711  *  @hw: pointer to the HW structure
 712  *
 713  *  Wrapper for calling the get_phy_info routines for the appropriate phy type.
 714  *  This is a function pointer entry point called by drivers
 715  *  or other shared routines.
 716  **/
 717 static s32 e1000_get_phy_info_ich8lan(struct e1000_hw *hw)
 718 {
 719         switch (hw->phy.type) {
 720         case e1000_phy_ife:
 721                 return e1000_get_phy_info_ife_ich8lan(hw);
 722                 break;
 723         case e1000_phy_igp_3:
 724         case e1000_phy_bm:
 725                 return e1000e_get_phy_info_igp(hw);
 726                 break;
 727         default:
 728                 break;
 729         }
 730
 731         return -E1000_ERR_PHY_TYPE;
 732 }
 733
 734 /**
 735  *  e1000_check_polarity_ife_ich8lan - Check cable polarity for IFE PHY
 736  *  @hw: pointer to the HW structure
 737  *
 738  *  Polarity is determined on the polarity reversal feature being enabled.
 739  *  This function is only called by other family-specific
 740  *  routines.
 741  **/
 742 static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
 743 {
 744         struct e1000_phy_info *phy = &hw->phy;
 745         s32 ret_val;
 746         u16 phy_data, offset, mask;
 747
 748         /*
 749          * Polarity is determined based on the reversal feature being enabled.
 750          */
 751         if (phy->polarity_correction) {
 752                 offset  = IFE_PHY_EXTENDED_STATUS_CONTROL;
 753                 mask    = IFE_PESC_POLARITY_REVERSED;
 754         } else {
 755                 offset  = IFE_PHY_SPECIAL_CONTROL;
 756                 mask    = IFE_PSC_FORCE_POLARITY;
 757         }
 758
 759         ret_val = e1e_rphy(hw, offset, &phy_data);
 760
 761         if (!ret_val)
 762                 phy->cable_polarity = (phy_data & mask)
 763                                       ? e1000_rev_polarity_reversed
 764                                       : e1000_rev_polarity_normal;
 765
 766         return ret_val;
 767 }
 768
 769 /**
 770  *  e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
 771  *  @hw: pointer to the HW structure
 772  *  @active: TRUE to enable LPLU, FALSE to disable
 773  *
 774  *  Sets the LPLU D0 state according to the active flag.  When
 775  *  activating LPLU this function also disables smart speed
 776  *  and vice versa.  LPLU will not be activated unless the
 777  *  device autonegotiation advertisement meets standards of
 778  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 779  *  This is a function pointer entry point only called by
 780  *  PHY setup routines.
 781  **/
 782 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 783 {
 784         struct e1000_phy_info *phy = &hw->phy;
 785         u32 phy_ctrl;
 786         s32 ret_val = 0;
 787         u16 data;
 788
 789         if (phy->type == e1000_phy_ife)
 790                 return ret_val;
 791
 792         phy_ctrl = er32(PHY_CTRL);
 793
 794         if (active) {
 795                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
 796                 ew32(PHY_CTRL, phy_ctrl);
 797
 798                 /*
 799                  * Call gig speed drop workaround on LPLU before accessing
 800                  * any PHY registers
 801                  */
 802                 if ((hw->mac.type == e1000_ich8lan) &&
 803                     (hw->phy.type == e1000_phy_igp_3))
 804                         e1000e_gig_downshift_workaround_ich8lan(hw);
 805
 806                 /* When LPLU is enabled, we should disable SmartSpeed */
 807                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 808                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 809                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 810                 if (ret_val)
 811                         return ret_val;
 812         } else {
 813                 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
 814                 ew32(PHY_CTRL, phy_ctrl);
 815
 816                 /*
 817                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 818                  * during Dx states where the power conservation is most
 819                  * important.  During driver activity we should enable
 820                  * SmartSpeed, so performance is maintained.
 821                  */
 822                 if (phy->smart_speed == e1000_smart_speed_on) {
 823                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 824                                            &data);
 825                         if (ret_val)
 826                                 return ret_val;
 827
 828                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 829                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 830                                            data);
 831                         if (ret_val)
 832                                 return ret_val;
 833                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 834                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 835                                            &data);
 836                         if (ret_val)
 837                                 return ret_val;
 838
 839                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 840                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 841                                            data);
 842                         if (ret_val)
 843                                 return ret_val;
 844                 }
 845         }
 846
 847         return 0;
 848 }
 849
 850 /**
 851  *  e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
 852  *  @hw: pointer to the HW structure
 853  *  @active: TRUE to enable LPLU, FALSE to disable
 854  *
 855  *  Sets the LPLU D3 state according to the active flag.  When
 856  *  activating LPLU this function also disables smart speed
 857  *  and vice versa.  LPLU will not be activated unless the
 858  *  device autonegotiation advertisement meets standards of
 859  *  either 10 or 10/100 or 10/100/1000 at all duplexes.
 860  *  This is a function pointer entry point only called by
 861  *  PHY setup routines.
 862  **/
 863 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
 864 {
 865         struct e1000_phy_info *phy = &hw->phy;
 866         u32 phy_ctrl;
 867         s32 ret_val;
 868         u16 data;
 869
 870         phy_ctrl = er32(PHY_CTRL);
 871
 872         if (!active) {
 873                 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
 874                 ew32(PHY_CTRL, phy_ctrl);
 875                 /*
 876                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 877                  * during Dx states where the power conservation is most
 878                  * important.  During driver activity we should enable
 879                  * SmartSpeed, so performance is maintained.
 880                  */
 881                 if (phy->smart_speed == e1000_smart_speed_on) {
 882                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 883                                            &data);
 884                         if (ret_val)
 885                                 return ret_val;
 886
 887                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 888                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 889                                            data);
 890                         if (ret_val)
 891                                 return ret_val;
 892                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 893                         ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 894                                            &data);
 895                         if (ret_val)
 896                                 return ret_val;
 897
 898                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 899                         ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
 900                                            data);
 901                         if (ret_val)
 902                                 return ret_val;
 903                 }
 904         } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
 905                    (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
 906                    (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
 907                 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
 908                 ew32(PHY_CTRL, phy_ctrl);
 909
 910                 /*
 911                  * Call gig speed drop workaround on LPLU before accessing
 912                  * any PHY registers
 913                  */
 914                 if ((hw->mac.type == e1000_ich8lan) &&
 915                     (hw->phy.type == e1000_phy_igp_3))
 916                         e1000e_gig_downshift_workaround_ich8lan(hw);
 917
 918                 /* When LPLU is enabled, we should disable SmartSpeed */
 919                 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
 920                 if (ret_val)
 921                         return ret_val;
 922
 923                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 924                 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
 925         }
 926
 927         return 0;
 928 }
 929
 930 /**
 931  *  e1000_read_nvm_ich8lan - Read word(s) from the NVM
 932  *  @hw: pointer to the HW structure
 933  *  @offset: The offset (in bytes) of the word(s) to read.
 934  *  @words: Size of data to read in words
 935  *  @data: Pointer to the word(s) to read at offset.
 936  *
 937  *  Reads a word(s) from the NVM using the flash access registers.
 938  **/
 939 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
 940                                   u16 *data)
 941 {
 942         struct e1000_nvm_info *nvm = &hw->nvm;
 943         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
 944         u32 act_offset;
 945         s32 ret_val;
 946         u16 i, word;
 947
 948         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
 949             (words == 0)) {
 950                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
 951                 return -E1000_ERR_NVM;
 952         }
 953
 954         ret_val = e1000_acquire_swflag_ich8lan(hw);
 955         if (ret_val)
 956                 return ret_val;
 957
 958         /* Start with the bank offset, then add the relative offset. */
 959         act_offset = (er32(EECD) & E1000_EECD_SEC1VAL)
 960                      ? nvm->flash_bank_size
 961                      : 0;
 962         act_offset += offset;
 963
 964         for (i = 0; i < words; i++) {
 965                 if ((dev_spec->shadow_ram) &&
 966                     (dev_spec->shadow_ram[offset+i].modified)) {
 967                         data[i] = dev_spec->shadow_ram[offset+i].value;
 968                 } else {
 969                         ret_val = e1000_read_flash_word_ich8lan(hw,
 970                                                                 act_offset + i,
 971                                                                 &word);
 972                         if (ret_val)
 973                                 break;
 974                         data[i] = word;
 975                 }
 976         }
 977
 978         e1000_release_swflag_ich8lan(hw);
 979
 980         return ret_val;
 981 }
 982
 983 /**
 984  *  e1000_flash_cycle_init_ich8lan - Initialize flash
 985  *  @hw: pointer to the HW structure
 986  *
 987  *  This function does initial flash setup so that a new read/write/erase cycle
 988  *  can be started.
 989  **/
 990 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
 991 {
 992         union ich8_hws_flash_status hsfsts;
 993         s32 ret_val = -E1000_ERR_NVM;
 994         s32 i = 0;
 995
 996         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
 997
 998         /* Check if the flash descriptor is valid */
 999         if (hsfsts.hsf_status.fldesvalid == 0) {
1000                 hw_dbg(hw, "Flash descriptor invalid.  "
1001                          "SW Sequencing must be used.");
1002                 return -E1000_ERR_NVM;
1003         }
1004
1005         /* Clear FCERR and DAEL in hw status by writing 1 */
1006         hsfsts.hsf_status.flcerr = 1;
1007         hsfsts.hsf_status.dael = 1;
1008
1009         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1010
1011         /*
1012          * Either we should have a hardware SPI cycle in progress
1013          * bit to check against, in order to start a new cycle or
1014          * FDONE bit should be changed in the hardware so that it
1015          * is 1 after hardware reset, which can then be used as an
1016          * indication whether a cycle is in progress or has been
1017          * completed.
1018          */
1019
1020         if (hsfsts.hsf_status.flcinprog == 0) {
1021                 /*
1022                  * There is no cycle running at present,
1023                  * so we can start a cycle
1024                  * Begin by setting Flash Cycle Done.
1025                  */
1026                 hsfsts.hsf_status.flcdone = 1;
1027                 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1028                 ret_val = 0;
1029         } else {
1030                 /*
1031                  * otherwise poll for sometime so the current
1032                  * cycle has a chance to end before giving up.
1033                  */
1034                 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
1035                         hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
1036                         if (hsfsts.hsf_status.flcinprog == 0) {
1037                                 ret_val = 0;
1038                                 break;
1039                         }
1040                         udelay(1);
1041                 }
1042                 if (ret_val == 0) {
1043                         /*
1044                          * Successful in waiting for previous cycle to timeout,
1045                          * now set the Flash Cycle Done.
1046                          */
1047                         hsfsts.hsf_status.flcdone = 1;
1048                         ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1049                 } else {
1050                         hw_dbg(hw, "Flash controller busy, cannot get access");
1051                 }
1052         }
1053
1054         return ret_val;
1055 }
1056
1057 /**
1058  *  e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
1059  *  @hw: pointer to the HW structure
1060  *  @timeout: maximum time to wait for completion
1061  *
1062  *  This function starts a flash cycle and waits for its completion.
1063  **/
1064 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
1065 {
1066         union ich8_hws_flash_ctrl hsflctl;
1067         union ich8_hws_flash_status hsfsts;
1068         s32 ret_val = -E1000_ERR_NVM;
1069         u32 i = 0;
1070
1071         /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
1072         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1073         hsflctl.hsf_ctrl.flcgo = 1;
1074         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1075
1076         /* wait till FDONE bit is set to 1 */
1077         do {
1078                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1079                 if (hsfsts.hsf_status.flcdone == 1)
1080                         break;
1081                 udelay(1);
1082         } while (i++ < timeout);
1083
1084         if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
1085                 return 0;
1086
1087         return ret_val;
1088 }
1089
1090 /**
1091  *  e1000_read_flash_word_ich8lan - Read word from flash
1092  *  @hw: pointer to the HW structure
1093  *  @offset: offset to data location
1094  *  @data: pointer to the location for storing the data
1095  *
1096  *  Reads the flash word at offset into data.  Offset is converted
1097  *  to bytes before read.
1098  **/
1099 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
1100                                          u16 *data)
1101 {
1102         /* Must convert offset into bytes. */
1103         offset <<= 1;
1104
1105         return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
1106 }
1107
1108 /**
1109  *  e1000_read_flash_data_ich8lan - Read byte or word from NVM
1110  *  @hw: pointer to the HW structure
1111  *  @offset: The offset (in bytes) of the byte or word to read.
1112  *  @size: Size of data to read, 1=byte 2=word
1113  *  @data: Pointer to the word to store the value read.
1114  *
1115  *  Reads a byte or word from the NVM using the flash access registers.
1116  **/
1117 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1118                                          u8 size, u16 *data)
1119 {
1120         union ich8_hws_flash_status hsfsts;
1121         union ich8_hws_flash_ctrl hsflctl;
1122         u32 flash_linear_addr;
1123         u32 flash_data = 0;
1124         s32 ret_val = -E1000_ERR_NVM;
1125         u8 count = 0;
1126
1127         if (size < 1  || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
1128                 return -E1000_ERR_NVM;
1129
1130         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1131                             hw->nvm.flash_base_addr;
1132
1133         do {
1134                 udelay(1);
1135                 /* Steps */
1136                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1137                 if (ret_val != 0)
1138                         break;
1139
1140                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1141                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1142                 hsflctl.hsf_ctrl.fldbcount = size - 1;
1143                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
1144                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1145
1146                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1147
1148                 ret_val = e1000_flash_cycle_ich8lan(hw,
1149                                                 ICH_FLASH_READ_COMMAND_TIMEOUT);
1150
1151                 /*
1152                  * Check if FCERR is set to 1, if set to 1, clear it
1153                  * and try the whole sequence a few more times, else
1154                  * read in (shift in) the Flash Data0, the order is
1155                  * least significant byte first msb to lsb
1156                  */
1157                 if (ret_val == 0) {
1158                         flash_data = er32flash(ICH_FLASH_FDATA0);
1159                         if (size == 1) {
1160                                 *data = (u8)(flash_data & 0x000000FF);
1161                         } else if (size == 2) {
1162                                 *data = (u16)(flash_data & 0x0000FFFF);
1163                         }
1164                         break;
1165                 } else {
1166                         /*
1167                          * If we've gotten here, then things are probably
1168                          * completely hosed, but if the error condition is
1169                          * detected, it won't hurt to give it another try...
1170                          * ICH_FLASH_CYCLE_REPEAT_COUNT times.
1171                          */
1172                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1173                         if (hsfsts.hsf_status.flcerr == 1) {
1174                                 /* Repeat for some time before giving up. */
1175                                 continue;
1176                         } else if (hsfsts.hsf_status.flcdone == 0) {
1177                                 hw_dbg(hw, "Timeout error - flash cycle "
1178                                          "did not complete.");
1179                                 break;
1180                         }
1181                 }
1182         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1183
1184         return ret_val;
1185 }
1186
1187 /**
1188  *  e1000_write_nvm_ich8lan - Write word(s) to the NVM
1189  *  @hw: pointer to the HW structure
1190  *  @offset: The offset (in bytes) of the word(s) to write.
1191  *  @words: Size of data to write in words
1192  *  @data: Pointer to the word(s) to write at offset.
1193  *
1194  *  Writes a byte or word to the NVM using the flash access registers.
1195  **/
1196 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
1197                                    u16 *data)
1198 {
1199         struct e1000_nvm_info *nvm = &hw->nvm;
1200         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1201         s32 ret_val;
1202         u16 i;
1203
1204         if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
1205             (words == 0)) {
1206                 hw_dbg(hw, "nvm parameter(s) out of bounds\n");
1207                 return -E1000_ERR_NVM;
1208         }
1209
1210         ret_val = e1000_acquire_swflag_ich8lan(hw);
1211         if (ret_val)
1212                 return ret_val;
1213
1214         for (i = 0; i < words; i++) {
1215                 dev_spec->shadow_ram[offset+i].modified = 1;
1216                 dev_spec->shadow_ram[offset+i].value = data[i];
1217         }
1218
1219         e1000_release_swflag_ich8lan(hw);
1220
1221         return 0;
1222 }
1223
1224 /**
1225  *  e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
1226  *  @hw: pointer to the HW structure
1227  *
1228  *  The NVM checksum is updated by calling the generic update_nvm_checksum,
1229  *  which writes the checksum to the shadow ram.  The changes in the shadow
1230  *  ram are then committed to the EEPROM by processing each bank at a time
1231  *  checking for the modified bit and writing only the pending changes.
1232  *  After a successful commit, the shadow ram is cleared and is ready for
1233  *  future writes.
1234  **/
1235 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
1236 {
1237         struct e1000_nvm_info *nvm = &hw->nvm;
1238         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
1239         u32 i, act_offset, new_bank_offset, old_bank_offset;
1240         s32 ret_val;
1241         u16 data;
1242
1243         ret_val = e1000e_update_nvm_checksum_generic(hw);
1244         if (ret_val)
1245                 return ret_val;
1246
1247         if (nvm->type != e1000_nvm_flash_sw)
1248                 return ret_val;
1249
1250         ret_val = e1000_acquire_swflag_ich8lan(hw);
1251         if (ret_val)
1252                 return ret_val;
1253
1254         /*
1255          * We're writing to the opposite bank so if we're on bank 1,
1256          * write to bank 0 etc.  We also need to erase the segment that
1257          * is going to be written
1258          */
1259         if (!(er32(EECD) & E1000_EECD_SEC1VAL)) {
1260                 new_bank_offset = nvm->flash_bank_size;
1261                 old_bank_offset = 0;
1262                 e1000_erase_flash_bank_ich8lan(hw, 1);
1263         } else {
1264                 old_bank_offset = nvm->flash_bank_size;
1265                 new_bank_offset = 0;
1266                 e1000_erase_flash_bank_ich8lan(hw, 0);
1267         }
1268
1269         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1270                 /*
1271                  * Determine whether to write the value stored
1272                  * in the other NVM bank or a modified value stored
1273                  * in the shadow RAM
1274                  */
1275                 if (dev_spec->shadow_ram[i].modified) {
1276                         data = dev_spec->shadow_ram[i].value;
1277                 } else {
1278                         e1000_read_flash_word_ich8lan(hw,
1279                                                       i + old_bank_offset,
1280                                                       &data);
1281                 }
1282
1283                 /*
1284                  * If the word is 0x13, then make sure the signature bits
1285                  * (15:14) are 11b until the commit has completed.
1286                  * This will allow us to write 10b which indicates the
1287                  * signature is valid.  We want to do this after the write
1288                  * has completed so that we don't mark the segment valid
1289                  * while the write is still in progress
1290                  */
1291                 if (i == E1000_ICH_NVM_SIG_WORD)
1292                         data |= E1000_ICH_NVM_SIG_MASK;
1293
1294                 /* Convert offset to bytes. */
1295                 act_offset = (i + new_bank_offset) << 1;
1296
1297                 udelay(100);
1298                 /* Write the bytes to the new bank. */
1299                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1300                                                                act_offset,
1301                                                                (u8)data);
1302                 if (ret_val)
1303                         break;
1304
1305                 udelay(100);
1306                 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1307                                                           act_offset + 1,
1308                                                           (u8)(data >> 8));
1309                 if (ret_val)
1310                         break;
1311         }
1312
1313         /*
1314          * Don't bother writing the segment valid bits if sector
1315          * programming failed.
1316          */
1317         if (ret_val) {
1318                 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
1319                 hw_dbg(hw, "Flash commit failed.\n");
1320                 e1000_release_swflag_ich8lan(hw);
1321                 return ret_val;
1322         }
1323
1324         /*
1325          * Finally validate the new segment by setting bit 15:14
1326          * to 10b in word 0x13 , this can be done without an
1327          * erase as well since these bits are 11 to start with
1328          * and we need to change bit 14 to 0b
1329          */
1330         act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
1331         e1000_read_flash_word_ich8lan(hw, act_offset, &data);
1332         data &= 0xBFFF;
1333         ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
1334                                                        act_offset * 2 + 1,
1335                                                        (u8)(data >> 8));
1336         if (ret_val) {
1337                 e1000_release_swflag_ich8lan(hw);
1338                 return ret_val;
1339         }
1340
1341         /*
1342          * And invalidate the previously valid segment by setting
1343          * its signature word (0x13) high_byte to 0b. This can be
1344          * done without an erase because flash erase sets all bits
1345          * to 1's. We can write 1's to 0's without an erase
1346          */
1347         act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
1348         ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
1349         if (ret_val) {
1350                 e1000_release_swflag_ich8lan(hw);
1351                 return ret_val;
1352         }
1353
1354         /* Great!  Everything worked, we can now clear the cached entries. */
1355         for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
1356                 dev_spec->shadow_ram[i].modified = 0;
1357                 dev_spec->shadow_ram[i].value = 0xFFFF;
1358         }
1359
1360         e1000_release_swflag_ich8lan(hw);
1361
1362         /*
1363          * Reload the EEPROM, or else modifications will not appear
1364          * until after the next adapter reset.
1365          */
1366         e1000e_reload_nvm(hw);
1367         msleep(10);
1368
1369         return ret_val;
1370 }
1371
1372 /**
1373  *  e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
1374  *  @hw: pointer to the HW structure
1375  *
1376  *  Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
1377  *  If the bit is 0, that the EEPROM had been modified, but the checksum was not
1378  *  calculated, in which case we need to calculate the checksum and set bit 6.
1379  **/
1380 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
1381 {
1382         s32 ret_val;
1383         u16 data;
1384
1385         /*
1386          * Read 0x19 and check bit 6.  If this bit is 0, the checksum
1387          * needs to be fixed.  This bit is an indication that the NVM
1388          * was prepared by OEM software and did not calculate the
1389          * checksum...a likely scenario.
1390          */
1391         ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
1392         if (ret_val)
1393                 return ret_val;
1394
1395         if ((data & 0x40) == 0) {
1396                 data |= 0x40;
1397                 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
1398                 if (ret_val)
1399                         return ret_val;
1400                 ret_val = e1000e_update_nvm_checksum(hw);
1401                 if (ret_val)
1402                         return ret_val;
1403         }
1404
1405         return e1000e_validate_nvm_checksum_generic(hw);
1406 }
1407
1408 /**
1409  *  e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
1410  *  @hw: pointer to the HW structure
1411  *
1412  *  To prevent malicious write/erase of the NVM, set it to be read-only
1413  *  so that the hardware ignores all write/erase cycles of the NVM via
1414  *  the flash control registers.  The shadow-ram copy of the NVM will
1415  *  still be updated, however any updates to this copy will not stick
1416  *  across driver reloads.
1417  **/
1418 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
1419 {
1420         union ich8_flash_protected_range pr0;
1421         union ich8_hws_flash_status hsfsts;
1422         u32 gfpreg;
1423         s32 ret_val;
1424
1425         ret_val = e1000_acquire_swflag_ich8lan(hw);
1426         if (ret_val)
1427                 return;
1428
1429         gfpreg = er32flash(ICH_FLASH_GFPREG);
1430
1431         /* Write-protect GbE Sector of NVM */
1432         pr0.regval = er32flash(ICH_FLASH_PR0);
1433         pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
1434         pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
1435         pr0.range.wpe = true;
1436         ew32flash(ICH_FLASH_PR0, pr0.regval);
1437
1438         /*
1439          * Lock down a subset of GbE Flash Control Registers, e.g.
1440          * PR0 to prevent the write-protection from being lifted.
1441          * Once FLOCKDN is set, the registers protected by it cannot
1442          * be written until FLOCKDN is cleared by a hardware reset.
1443          */
1444         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1445         hsfsts.hsf_status.flockdn = true;
1446         ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
1447
1448         e1000_release_swflag_ich8lan(hw);
1449 }
1450
1451 /**
1452  *  e1000_write_flash_data_ich8lan - Writes bytes to the NVM
1453  *  @hw: pointer to the HW structure
1454  *  @offset: The offset (in bytes) of the byte/word to read.
1455  *  @size: Size of data to read, 1=byte 2=word
1456  *  @data: The byte(s) to write to the NVM.
1457  *
1458  *  Writes one/two bytes to the NVM using the flash access registers.
1459  **/
1460 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
1461                                           u8 size, u16 data)
1462 {
1463         union ich8_hws_flash_status hsfsts;
1464         union ich8_hws_flash_ctrl hsflctl;
1465         u32 flash_linear_addr;
1466         u32 flash_data = 0;
1467         s32 ret_val;
1468         u8 count = 0;
1469
1470         if (size < 1 || size > 2 || data > size * 0xff ||
1471             offset > ICH_FLASH_LINEAR_ADDR_MASK)
1472                 return -E1000_ERR_NVM;
1473
1474         flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
1475                             hw->nvm.flash_base_addr;
1476
1477         do {
1478                 udelay(1);
1479                 /* Steps */
1480                 ret_val = e1000_flash_cycle_init_ich8lan(hw);
1481                 if (ret_val)
1482                         break;
1483
1484                 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1485                 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
1486                 hsflctl.hsf_ctrl.fldbcount = size -1;
1487                 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
1488                 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1489
1490                 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1491
1492                 if (size == 1)
1493                         flash_data = (u32)data & 0x00FF;
1494                 else
1495                         flash_data = (u32)data;
1496
1497                 ew32flash(ICH_FLASH_FDATA0, flash_data);
1498
1499                 /*
1500                  * check if FCERR is set to 1 , if set to 1, clear it
1501                  * and try the whole sequence a few more times else done
1502                  */
1503                 ret_val = e1000_flash_cycle_ich8lan(hw,
1504                                                ICH_FLASH_WRITE_COMMAND_TIMEOUT);
1505                 if (!ret_val)
1506                         break;
1507
1508                 /*
1509                  * If we're here, then things are most likely
1510                  * completely hosed, but if the error condition
1511                  * is detected, it won't hurt to give it another
1512                  * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
1513                  */
1514                 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1515                 if (hsfsts.hsf_status.flcerr == 1)
1516                         /* Repeat for some time before giving up. */
1517                         continue;
1518                 if (hsfsts.hsf_status.flcdone == 0) {
1519                         hw_dbg(hw, "Timeout error - flash cycle "
1520                                  "did not complete.");
1521                         break;
1522                 }
1523         } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
1524
1525         return ret_val;
1526 }
1527
1528 /**
1529  *  e1000_write_flash_byte_ich8lan - Write a single byte to NVM
1530  *  @hw: pointer to the HW structure
1531  *  @offset: The index of the byte to read.
1532  *  @data: The byte to write to the NVM.
1533  *
1534  *  Writes a single byte to the NVM using the flash access registers.
1535  **/
1536 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
1537                                           u8 data)
1538 {
1539         u16 word = (u16)data;
1540
1541         return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
1542 }
1543
1544 /**
1545  *  e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
1546  *  @hw: pointer to the HW structure
1547  *  @offset: The offset of the byte to write.
1548  *  @byte: The byte to write to the NVM.
1549  *
1550  *  Writes a single byte to the NVM using the flash access registers.
1551  *  Goes through a retry algorithm before giving up.
1552  **/
1553 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
1554                                                 u32 offset, u8 byte)
1555 {
1556         s32 ret_val;
1557         u16 program_retries;
1558
1559         ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1560         if (!ret_val)
1561                 return ret_val;
1562
1563         for (program_retries = 0; program_retries < 100; program_retries++) {
1564                 hw_dbg(hw, "Retrying Byte %2.2X at offset %u\n", byte, offset);
1565                 udelay(100);
1566                 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
1567                 if (!ret_val)
1568                         break;
1569         }
1570         if (program_retries == 100)
1571                 return -E1000_ERR_NVM;
1572
1573         return 0;
1574 }
1575
1576 /**
1577  *  e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
1578  *  @hw: pointer to the HW structure
1579  *  @bank: 0 for first bank, 1 for second bank, etc.
1580  *
1581  *  Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
1582  *  bank N is 4096 * N + flash_reg_addr.
1583  **/
1584 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
1585 {
1586         struct e1000_nvm_info *nvm = &hw->nvm;
1587         union ich8_hws_flash_status hsfsts;
1588         union ich8_hws_flash_ctrl hsflctl;
1589         u32 flash_linear_addr;
1590         /* bank size is in 16bit words - adjust to bytes */
1591         u32 flash_bank_size = nvm->flash_bank_size * 2;
1592         s32 ret_val;
1593         s32 count = 0;
1594         s32 iteration;
1595         s32 sector_size;
1596         s32 j;
1597
1598         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1599
1600         /*
1601          * Determine HW Sector size: Read BERASE bits of hw flash status
1602          * register
1603          * 00: The Hw sector is 256 bytes, hence we need to erase 16
1604          *     consecutive sectors.  The start index for the nth Hw sector
1605          *     can be calculated as = bank * 4096 + n * 256
1606          * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
1607          *     The start index for the nth Hw sector can be calculated
1608          *     as = bank * 4096
1609          * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
1610          *     (ich9 only, otherwise error condition)
1611          * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
1612          */
1613         switch (hsfsts.hsf_status.berasesz) {
1614         case 0:
1615                 /* Hw sector size 256 */
1616                 sector_size = ICH_FLASH_SEG_SIZE_256;
1617                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
1618                 break;
1619         case 1:
1620                 sector_size = ICH_FLASH_SEG_SIZE_4K;
1621                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_4K;
1622                 break;
1623         case 2:
1624                 if (hw->mac.type == e1000_ich9lan) {
1625                         sector_size = ICH_FLASH_SEG_SIZE_8K;
1626                         iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_8K;
1627                 } else {
1628                         return -E1000_ERR_NVM;
1629                 }
1630                 break;
1631         case 3:
1632                 sector_size = ICH_FLASH_SEG_SIZE_64K;
1633                 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_64K;
1634                 break;
1635         default:
1636                 return -E1000_ERR_NVM;
1637         }
1638
1639         /* Start with the base address, then add the sector offset. */
1640         flash_linear_addr = hw->nvm.flash_base_addr;
1641         flash_linear_addr += (bank) ? (sector_size * iteration) : 0;
1642
1643         for (j = 0; j < iteration ; j++) {
1644                 do {
1645                         /* Steps */
1646                         ret_val = e1000_flash_cycle_init_ich8lan(hw);
1647                         if (ret_val)
1648                                 return ret_val;
1649
1650                         /*
1651                          * Write a value 11 (block Erase) in Flash
1652                          * Cycle field in hw flash control
1653                          */
1654                         hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
1655                         hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
1656                         ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
1657
1658                         /*
1659                          * Write the last 24 bits of an index within the
1660                          * block into Flash Linear address field in Flash
1661                          * Address.
1662                          */
1663                         flash_linear_addr += (j * sector_size);
1664                         ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
1665
1666                         ret_val = e1000_flash_cycle_ich8lan(hw,
1667                                                ICH_FLASH_ERASE_COMMAND_TIMEOUT);
1668                         if (ret_val == 0)
1669                                 break;
1670
1671                         /*
1672                          * Check if FCERR is set to 1.  If 1,
1673                          * clear it and try the whole sequence
1674                          * a few more times else Done
1675                          */
1676                         hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
1677                         if (hsfsts.hsf_status.flcerr == 1)
1678                                 /* repeat for some time before giving up */
1679                                 continue;
1680                         else if (hsfsts.hsf_status.flcdone == 0)
1681                                 return ret_val;
1682                 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
1683         }
1684
1685         return 0;
1686 }
1687
1688 /**
1689  *  e1000_valid_led_default_ich8lan - Set the default LED settings
1690  *  @hw: pointer to the HW structure
1691  *  @data: Pointer to the LED settings
1692  *
1693  *  Reads the LED default settings from the NVM to data.  If the NVM LED
1694  *  settings is all 0's or F's, set the LED default to a valid LED default
1695  *  setting.
1696  **/
1697 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
1698 {
1699         s32 ret_val;
1700
1701         ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1702         if (ret_val) {
1703                 hw_dbg(hw, "NVM Read Error\n");
1704                 return ret_val;
1705         }
1706
1707         if (*data == ID_LED_RESERVED_0000 ||
1708             *data == ID_LED_RESERVED_FFFF)
1709                 *data = ID_LED_DEFAULT_ICH8LAN;
1710
1711         return 0;
1712 }
1713
1714 /**
1715  *  e1000_get_bus_info_ich8lan - Get/Set the bus type and width
1716  *  @hw: pointer to the HW structure
1717  *
1718  *  ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
1719  *  register, so the the bus width is hard coded.
1720  **/
1721 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
1722 {
1723         struct e1000_bus_info *bus = &hw->bus;
1724         s32 ret_val;
1725
1726         ret_val = e1000e_get_bus_info_pcie(hw);
1727
1728         /*
1729          * ICH devices are "PCI Express"-ish.  They have
1730          * a configuration space, but do not contain
1731          * PCI Express Capability registers, so bus width
1732          * must be hardcoded.
1733          */
1734         if (bus->width == e1000_bus_width_unknown)
1735                 bus->width = e1000_bus_width_pcie_x1;
1736
1737         return ret_val;
1738 }
1739
1740 /**
1741  *  e1000_reset_hw_ich8lan - Reset the hardware
1742  *  @hw: pointer to the HW structure
1743  *
1744  *  Does a full reset of the hardware which includes a reset of the PHY and
1745  *  MAC.
1746  **/
1747 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
1748 {
1749         u32 ctrl, icr, kab;
1750         s32 ret_val;
1751
1752         /*
1753          * Prevent the PCI-E bus from sticking if there is no TLP connection
1754          * on the last TLP read/write transaction when MAC is reset.
1755          */
1756         ret_val = e1000e_disable_pcie_master(hw);
1757         if (ret_val) {
1758                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
1759         }
1760
1761         hw_dbg(hw, "Masking off all interrupts\n");
1762         ew32(IMC, 0xffffffff);
1763
1764         /*
1765          * Disable the Transmit and Receive units.  Then delay to allow
1766          * any pending transactions to complete before we hit the MAC
1767          * with the global reset.
1768          */
1769         ew32(RCTL, 0);
1770         ew32(TCTL, E1000_TCTL_PSP);
1771         e1e_flush();
1772
1773         msleep(10);
1774
1775         /* Workaround for ICH8 bit corruption issue in FIFO memory */
1776         if (hw->mac.type == e1000_ich8lan) {
1777                 /* Set Tx and Rx buffer allocation to 8k apiece. */
1778                 ew32(PBA, E1000_PBA_8K);
1779                 /* Set Packet Buffer Size to 16k. */
1780                 ew32(PBS, E1000_PBS_16K);
1781         }
1782
1783         ctrl = er32(CTRL);
1784
1785         if (!e1000_check_reset_block(hw)) {
1786                 /*
1787                  * PHY HW reset requires MAC CORE reset at the same
1788                  * time to make sure the interface between MAC and the
1789                  * external PHY is reset.
1790                  */
1791                 ctrl |= E1000_CTRL_PHY_RST;
1792         }
1793         ret_val = e1000_acquire_swflag_ich8lan(hw);
1794         hw_dbg(hw, "Issuing a global reset to ich8lan");
1795         ew32(CTRL, (ctrl | E1000_CTRL_RST));
1796         msleep(20);
1797
1798         /* release the swflag because it is not reset by hardware reset */
1799         e1000_release_swflag_ich8lan(hw);
1800
1801         ret_val = e1000e_get_auto_rd_done(hw);
1802         if (ret_val) {
1803                 /*
1804                  * When auto config read does not complete, do not
1805                  * return with an error. This can happen in situations
1806                  * where there is no eeprom and prevents getting link.
1807                  */
1808                 hw_dbg(hw, "Auto Read Done did not complete\n");
1809         }
1810
1811         ew32(IMC, 0xffffffff);
1812         icr = er32(ICR);
1813
1814         kab = er32(KABGTXD);
1815         kab |= E1000_KABGTXD_BGSQLBIAS;
1816         ew32(KABGTXD, kab);
1817
1818         return ret_val;
1819 }
1820
1821 /**
1822  *  e1000_init_hw_ich8lan - Initialize the hardware
1823  *  @hw: pointer to the HW structure
1824  *
1825  *  Prepares the hardware for transmit and receive by doing the following:
1826  *   - initialize hardware bits
1827  *   - initialize LED identification
1828  *   - setup receive address registers
1829  *   - setup flow control
1830  *   - setup transmit descriptors
1831  *   - clear statistics
1832  **/
1833 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
1834 {
1835         struct e1000_mac_info *mac = &hw->mac;
1836         u32 ctrl_ext, txdctl, snoop;
1837         s32 ret_val;
1838         u16 i;
1839
1840         e1000_initialize_hw_bits_ich8lan(hw);
1841
1842         /* Initialize identification LED */
1843         ret_val = e1000e_id_led_init(hw);
1844         if (ret_val) {
1845                 hw_dbg(hw, "Error initializing identification LED\n");
1846                 return ret_val;
1847         }
1848
1849         /* Setup the receive address. */
1850         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
1851
1852         /* Zero out the Multicast HASH table */
1853         hw_dbg(hw, "Zeroing the MTA\n");
1854         for (i = 0; i < mac->mta_reg_count; i++)
1855                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1856
1857         /* Setup link and flow control */
1858         ret_val = e1000_setup_link_ich8lan(hw);
1859
1860         /* Set the transmit descriptor write-back policy for both queues */
1861         txdctl = er32(TXDCTL(0));
1862         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1863                  E1000_TXDCTL_FULL_TX_DESC_WB;
1864         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1865                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1866         ew32(TXDCTL(0), txdctl);
1867         txdctl = er32(TXDCTL(1));
1868         txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
1869                  E1000_TXDCTL_FULL_TX_DESC_WB;
1870         txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
1871                  E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
1872         ew32(TXDCTL(1), txdctl);
1873
1874         /*
1875          * ICH8 has opposite polarity of no_snoop bits.
1876          * By default, we should use snoop behavior.
1877          */
1878         if (mac->type == e1000_ich8lan)
1879                 snoop = PCIE_ICH8_SNOOP_ALL;
1880         else
1881                 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
1882         e1000e_set_pcie_no_snoop(hw, snoop);
1883
1884         ctrl_ext = er32(CTRL_EXT);
1885         ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
1886         ew32(CTRL_EXT, ctrl_ext);
1887
1888         /*
1889          * Clear all of the statistics registers (clear on read).  It is
1890          * important that we do this after we have tried to establish link
1891          * because the symbol error count will increment wildly if there
1892          * is no link.
1893          */
1894         e1000_clear_hw_cntrs_ich8lan(hw);
1895
1896         return 0;
1897 }
1898 /**
1899  *  e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
1900  *  @hw: pointer to the HW structure
1901  *
1902  *  Sets/Clears required hardware bits necessary for correctly setting up the
1903  *  hardware for transmit and receive.
1904  **/
1905 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
1906 {
1907         u32 reg;
1908
1909         /* Extended Device Control */
1910         reg = er32(CTRL_EXT);
1911         reg |= (1 << 22);
1912         ew32(CTRL_EXT, reg);
1913
1914         /* Transmit Descriptor Control 0 */
1915         reg = er32(TXDCTL(0));
1916         reg |= (1 << 22);
1917         ew32(TXDCTL(0), reg);
1918
1919         /* Transmit Descriptor Control 1 */
1920         reg = er32(TXDCTL(1));
1921         reg |= (1 << 22);
1922         ew32(TXDCTL(1), reg);
1923
1924         /* Transmit Arbitration Control 0 */
1925         reg = er32(TARC(0));
1926         if (hw->mac.type == e1000_ich8lan)
1927                 reg |= (1 << 28) | (1 << 29);
1928         reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
1929         ew32(TARC(0), reg);
1930
1931         /* Transmit Arbitration Control 1 */
1932         reg = er32(TARC(1));
1933         if (er32(TCTL) & E1000_TCTL_MULR)
1934                 reg &= ~(1 << 28);
1935         else
1936                 reg |= (1 << 28);
1937         reg |= (1 << 24) | (1 << 26) | (1 << 30);
1938         ew32(TARC(1), reg);
1939
1940         /* Device Status */
1941         if (hw->mac.type == e1000_ich8lan) {
1942                 reg = er32(STATUS);
1943                 reg &= ~(1 << 31);
1944                 ew32(STATUS, reg);
1945         }
1946 }
1947
1948 /**
1949  *  e1000_setup_link_ich8lan - Setup flow control and link settings
1950  *  @hw: pointer to the HW structure
1951  *
1952  *  Determines which flow control settings to use, then configures flow
1953  *  control.  Calls the appropriate media-specific link configuration
1954  *  function.  Assuming the adapter has a valid link partner, a valid link
1955  *  should be established.  Assumes the hardware has previously been reset
1956  *  and the transmitter and receiver are not enabled.
1957  **/
1958 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
1959 {
1960         s32 ret_val;
1961
1962         if (e1000_check_reset_block(hw))
1963                 return 0;
1964
1965         /*
1966          * ICH parts do not have a word in the NVM to determine
1967          * the default flow control setting, so we explicitly
1968          * set it to full.
1969          */
1970         if (hw->fc.type == e1000_fc_default)
1971                 hw->fc.type = e1000_fc_full;
1972
1973         hw->fc.original_type = hw->fc.type;
1974
1975         hw_dbg(hw, "After fix-ups FlowControl is now = %x\n", hw->fc.type);
1976
1977         /* Continue to configure the copper link. */
1978         ret_val = e1000_setup_copper_link_ich8lan(hw);
1979         if (ret_val)
1980                 return ret_val;
1981
1982         ew32(FCTTV, hw->fc.pause_time);
1983
1984         return e1000e_set_fc_watermarks(hw);
1985 }
1986
1987 /**
1988  *  e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
1989  *  @hw: pointer to the HW structure
1990  *
1991  *  Configures the kumeran interface to the PHY to wait the appropriate time
1992  *  when polling the PHY, then call the generic setup_copper_link to finish
1993  *  configuring the copper link.
1994  **/
1995 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
1996 {
1997         u32 ctrl;
1998         s32 ret_val;
1999         u16 reg_data;
2000
2001         ctrl = er32(CTRL);
2002         ctrl |= E1000_CTRL_SLU;
2003         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2004         ew32(CTRL, ctrl);
2005
2006         /*
2007          * Set the mac to wait the maximum time between each iteration
2008          * and increase the max iterations when polling the phy;
2009          * this fixes erroneous timeouts at 10Mbps.
2010          */
2011         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2012         if (ret_val)
2013                 return ret_val;
2014         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2015         if (ret_val)
2016                 return ret_val;
2017         reg_data |= 0x3F;
2018         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2019         if (ret_val)
2020                 return ret_val;
2021
2022         if (hw->phy.type == e1000_phy_igp_3) {
2023                 ret_val = e1000e_copper_link_setup_igp(hw);
2024                 if (ret_val)
2025                         return ret_val;
2026         } else if (hw->phy.type == e1000_phy_bm) {
2027                 ret_val = e1000e_copper_link_setup_m88(hw);
2028                 if (ret_val)
2029                         return ret_val;
2030         }
2031
2032         if (hw->phy.type == e1000_phy_ife) {
2033                 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &reg_data);
2034                 if (ret_val)
2035                         return ret_val;
2036
2037                 reg_data &= ~IFE_PMC_AUTO_MDIX;
2038
2039                 switch (hw->phy.mdix) {
2040                 case 1:
2041                         reg_data &= ~IFE_PMC_FORCE_MDIX;
2042                         break;
2043                 case 2:
2044                         reg_data |= IFE_PMC_FORCE_MDIX;
2045                         break;
2046                 case 0:
2047                 default:
2048                         reg_data |= IFE_PMC_AUTO_MDIX;
2049                         break;
2050                 }
2051                 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
2052                 if (ret_val)
2053                         return ret_val;
2054         }
2055         return e1000e_setup_copper_link(hw);
2056 }
2057
2058 /**
2059  *  e1000_get_link_up_info_ich8lan - Get current link speed and duplex
2060  *  @hw: pointer to the HW structure
2061  *  @speed: pointer to store current link speed
2062  *  @duplex: pointer to store the current link duplex
2063  *
2064  *  Calls the generic get_speed_and_duplex to retrieve the current link
2065  *  information and then calls the Kumeran lock loss workaround for links at
2066  *  gigabit speeds.
2067  **/
2068 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
2069                                           u16 *duplex)
2070 {
2071         s32 ret_val;
2072
2073         ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
2074         if (ret_val)
2075                 return ret_val;
2076
2077         if ((hw->mac.type == e1000_ich8lan) &&
2078             (hw->phy.type == e1000_phy_igp_3) &&
2079             (*speed == SPEED_1000)) {
2080                 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
2081         }
2082
2083         return ret_val;
2084 }
2085
2086 /**
2087  *  e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
2088  *  @hw: pointer to the HW structure
2089  *
2090  *  Work-around for 82566 Kumeran PCS lock loss:
2091  *  On link status change (i.e. PCI reset, speed change) and link is up and
2092  *  speed is gigabit-
2093  *    0) if workaround is optionally disabled do nothing
2094  *    1) wait 1ms for Kumeran link to come up
2095  *    2) check Kumeran Diagnostic register PCS lock loss bit
2096  *    3) if not set the link is locked (all is good), otherwise...
2097  *    4) reset the PHY
2098  *    5) repeat up to 10 times
2099  *  Note: this is only called for IGP3 copper when speed is 1gb.
2100  **/
2101 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
2102 {
2103         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2104         u32 phy_ctrl;
2105         s32 ret_val;
2106         u16 i, data;
2107         bool link;
2108
2109         if (!dev_spec->kmrn_lock_loss_workaround_enabled)
2110                 return 0;
2111
2112         /*
2113          * Make sure link is up before proceeding.  If not just return.
2114          * Attempting this while link is negotiating fouled up link
2115          * stability
2116          */
2117         ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2118         if (!link)
2119                 return 0;
2120
2121         for (i = 0; i < 10; i++) {
2122                 /* read once to clear */
2123                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2124                 if (ret_val)
2125                         return ret_val;
2126                 /* and again to get new status */
2127                 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
2128                 if (ret_val)
2129                         return ret_val;
2130
2131                 /* check for PCS lock */
2132                 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
2133                         return 0;
2134
2135                 /* Issue PHY reset */
2136                 e1000_phy_hw_reset(hw);
2137                 mdelay(5);
2138         }
2139         /* Disable GigE link negotiation */
2140         phy_ctrl = er32(PHY_CTRL);
2141         phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
2142                      E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2143         ew32(PHY_CTRL, phy_ctrl);
2144
2145         /*
2146          * Call gig speed drop workaround on Gig disable before accessing
2147          * any PHY registers
2148          */
2149         e1000e_gig_downshift_workaround_ich8lan(hw);
2150
2151         /* unable to acquire PCS lock */
2152         return -E1000_ERR_PHY;
2153 }
2154
2155 /**
2156  *  e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
2157  *  @hw: pointer to the HW structure
2158  *  @state: boolean value used to set the current Kumeran workaround state
2159  *
2160  *  If ICH8, set the current Kumeran workaround state (enabled - TRUE
2161  *  /disabled - FALSE).
2162  **/
2163 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
2164                                                  bool state)
2165 {
2166         struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2167
2168         if (hw->mac.type != e1000_ich8lan) {
2169                 hw_dbg(hw, "Workaround applies to ICH8 only.\n");
2170                 return;
2171         }
2172
2173         dev_spec->kmrn_lock_loss_workaround_enabled = state;
2174 }
2175
2176 /**
2177  *  e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
2178  *  @hw: pointer to the HW structure
2179  *
2180  *  Workaround for 82566 power-down on D3 entry:
2181  *    1) disable gigabit link
2182  *    2) write VR power-down enable
2183  *    3) read it back
2184  *  Continue if successful, else issue LCD reset and repeat
2185  **/
2186 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
2187 {
2188         u32 reg;
2189         u16 data;
2190         u8  retry = 0;
2191
2192         if (hw->phy.type != e1000_phy_igp_3)
2193                 return;
2194
2195         /* Try the workaround twice (if needed) */
2196         do {
2197                 /* Disable link */
2198                 reg = er32(PHY_CTRL);
2199                 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
2200                         E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
2201                 ew32(PHY_CTRL, reg);
2202
2203                 /*
2204                  * Call gig speed drop workaround on Gig disable before
2205                  * accessing any PHY registers
2206                  */
2207                 if (hw->mac.type == e1000_ich8lan)
2208                         e1000e_gig_downshift_workaround_ich8lan(hw);
2209
2210                 /* Write VR power-down enable */
2211                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2212                 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2213                 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
2214
2215                 /* Read it back and test */
2216                 e1e_rphy(hw, IGP3_VR_CTRL, &data);
2217                 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
2218                 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
2219                         break;
2220
2221                 /* Issue PHY reset and repeat at most one more time */
2222                 reg = er32(CTRL);
2223                 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
2224                 retry++;
2225         } while (retry);
2226 }
2227
2228 /**
2229  *  e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
2230  *  @hw: pointer to the HW structure
2231  *
2232  *  Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
2233  *  LPLU, Gig disable, MDIC PHY reset):
2234  *    1) Set Kumeran Near-end loopback
2235  *    2) Clear Kumeran Near-end loopback
2236  *  Should only be called for ICH8[m] devices with IGP_3 Phy.
2237  **/
2238 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
2239 {
2240         s32 ret_val;
2241         u16 reg_data;
2242
2243         if ((hw->mac.type != e1000_ich8lan) ||
2244             (hw->phy.type != e1000_phy_igp_3))
2245                 return;
2246
2247         ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2248                                       &reg_data);
2249         if (ret_val)
2250                 return;
2251         reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
2252         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2253                                        reg_data);
2254         if (ret_val)
2255                 return;
2256         reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
2257         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
2258                                        reg_data);
2259 }
2260
2261 /**
2262  *  e1000e_disable_gig_wol_ich8lan - disable gig during WoL
2263  *  @hw: pointer to the HW structure
2264  *
2265  *  During S0 to Sx transition, it is possible the link remains at gig
2266  *  instead of negotiating to a lower speed.  Before going to Sx, set
2267  *  'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
2268  *  to a lower speed.
2269  *
2270  *  Should only be called for ICH9 devices.
2271  **/
2272 void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw)
2273 {
2274         u32 phy_ctrl;
2275
2276         if (hw->mac.type == e1000_ich9lan) {
2277                 phy_ctrl = er32(PHY_CTRL);
2278                 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU |
2279                             E1000_PHY_CTRL_GBE_DISABLE;
2280                 ew32(PHY_CTRL, phy_ctrl);
2281         }
2282
2283         return;
2284 }
2285
2286 /**
2287  *  e1000_cleanup_led_ich8lan - Restore the default LED operation
2288  *  @hw: pointer to the HW structure
2289  *
2290  *  Return the LED back to the default configuration.
2291  **/
2292 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
2293 {
2294         if (hw->phy.type == e1000_phy_ife)
2295                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
2296
2297         ew32(LEDCTL, hw->mac.ledctl_default);
2298         return 0;
2299 }
2300
2301 /**
2302  *  e1000_led_on_ich8lan - Turn LEDs on
2303  *  @hw: pointer to the HW structure
2304  *
2305  *  Turn on the LEDs.
2306  **/
2307 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
2308 {
2309         if (hw->phy.type == e1000_phy_ife)
2310                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2311                                 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
2312
2313         ew32(LEDCTL, hw->mac.ledctl_mode2);
2314         return 0;
2315 }
2316
2317 /**
2318  *  e1000_led_off_ich8lan - Turn LEDs off
2319  *  @hw: pointer to the HW structure
2320  *
2321  *  Turn off the LEDs.
2322  **/
2323 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
2324 {
2325         if (hw->phy.type == e1000_phy_ife)
2326                 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
2327                                (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_OFF));
2328
2329         ew32(LEDCTL, hw->mac.ledctl_mode1);
2330         return 0;
2331 }
2332
2333 /**
2334  *  e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
2335  *  @hw: pointer to the HW structure
2336  *
2337  *  Clears hardware counters specific to the silicon family and calls
2338  *  clear_hw_cntrs_generic to clear all general purpose counters.
2339  **/
2340 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
2341 {
2342         u32 temp;
2343
2344         e1000e_clear_hw_cntrs_base(hw);
2345
2346         temp = er32(ALGNERRC);
2347         temp = er32(RXERRC);
2348         temp = er32(TNCRS);
2349         temp = er32(CEXTERR);
2350         temp = er32(TSCTC);
2351         temp = er32(TSCTFC);
2352
2353         temp = er32(MGTPRC);
2354         temp = er32(MGTPDC);
2355         temp = er32(MGTPTC);
2356
2357         temp = er32(IAC);
2358         temp = er32(ICRXOC);
2359
2360 }
2361
2362 static struct e1000_mac_operations ich8_mac_ops = {
2363         .mng_mode_enab          = E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT,
2364         .check_for_link         = e1000e_check_for_copper_link,
2365         .cleanup_led            = e1000_cleanup_led_ich8lan,
2366         .clear_hw_cntrs         = e1000_clear_hw_cntrs_ich8lan,
2367         .get_bus_info           = e1000_get_bus_info_ich8lan,
2368         .get_link_up_info       = e1000_get_link_up_info_ich8lan,
2369         .led_on                 = e1000_led_on_ich8lan,
2370         .led_off                = e1000_led_off_ich8lan,
2371         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
2372         .reset_hw               = e1000_reset_hw_ich8lan,
2373         .init_hw                = e1000_init_hw_ich8lan,
2374         .setup_link             = e1000_setup_link_ich8lan,
2375         .setup_physical_interface= e1000_setup_copper_link_ich8lan,
2376 };
2377
2378 static struct e1000_phy_operations ich8_phy_ops = {
2379         .acquire_phy            = e1000_acquire_swflag_ich8lan,
2380         .check_reset_block      = e1000_check_reset_block_ich8lan,
2381         .commit_phy             = NULL,
2382         .force_speed_duplex     = e1000_phy_force_speed_duplex_ich8lan,
2383         .get_cfg_done           = e1000e_get_cfg_done,
2384         .get_cable_length       = e1000e_get_cable_length_igp_2,
2385         .get_phy_info           = e1000_get_phy_info_ich8lan,
2386         .read_phy_reg           = e1000e_read_phy_reg_igp,
2387         .release_phy            = e1000_release_swflag_ich8lan,
2388         .reset_phy              = e1000_phy_hw_reset_ich8lan,
2389         .set_d0_lplu_state      = e1000_set_d0_lplu_state_ich8lan,
2390         .set_d3_lplu_state      = e1000_set_d3_lplu_state_ich8lan,
2391         .write_phy_reg          = e1000e_write_phy_reg_igp,
2392 };
2393
2394 static struct e1000_nvm_operations ich8_nvm_ops = {
2395         .acquire_nvm            = e1000_acquire_swflag_ich8lan,
2396         .read_nvm               = e1000_read_nvm_ich8lan,
2397         .release_nvm            = e1000_release_swflag_ich8lan,
2398         .update_nvm             = e1000_update_nvm_checksum_ich8lan,
2399         .valid_led_default      = e1000_valid_led_default_ich8lan,
2400         .validate_nvm           = e1000_validate_nvm_checksum_ich8lan,
2401         .write_nvm              = e1000_write_nvm_ich8lan,
2402 };
2403
2404 struct e1000_info e1000_ich8_info = {
2405         .mac                    = e1000_ich8lan,
2406         .flags                  = FLAG_HAS_WOL
2407                                   | FLAG_IS_ICH
2408                                   | FLAG_RX_CSUM_ENABLED
2409                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2410                                   | FLAG_HAS_AMT
2411                                   | FLAG_HAS_FLASH
2412                                   | FLAG_APME_IN_WUC,
2413         .pba                    = 8,
2414         .get_variants           = e1000_get_variants_ich8lan,
2415         .mac_ops                = &ich8_mac_ops,
2416         .phy_ops                = &ich8_phy_ops,
2417         .nvm_ops                = &ich8_nvm_ops,
2418 };
2419
2420 struct e1000_info e1000_ich9_info = {
2421         .mac                    = e1000_ich9lan,
2422         .flags                  = FLAG_HAS_JUMBO_FRAMES
2423                                   | FLAG_IS_ICH
2424                                   | FLAG_HAS_WOL
2425                                   | FLAG_RX_CSUM_ENABLED
2426                                   | FLAG_HAS_CTRLEXT_ON_LOAD
2427                                   | FLAG_HAS_AMT
2428                                   | FLAG_HAS_ERT
2429                                   | FLAG_HAS_FLASH
2430                                   | FLAG_APME_IN_WUC,
2431         .pba                    = 10,
2432         .get_variants           = e1000_get_variants_ich8lan,
2433         .mac_ops                = &ich8_mac_ops,
2434         .phy_ops                = &ich8_phy_ops,
2435         .nvm_ops                = &ich8_nvm_ops,
2436 };
2437