drivers/net/e1000e/es2lan.c

   1 /*******************************************************************************
   2
   3   Intel PRO/1000 Linux driver
   4   Copyright(c) 1999 - 2008 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   Linux NICS <linux.nics@intel.com>
  24   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  25   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  26
  27 *******************************************************************************/
  28
  29 /*
  30  * 80003ES2LAN Gigabit Ethernet Controller (Copper)
  31  * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
  32  */
  33
  34 #include <linux/netdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/delay.h>
  37 #include <linux/pci.h>
  38
  39 #include "e1000.h"
  40
  41 #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
  42 #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
  43 #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
  44
  45 #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
  46 #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
  47 #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
  48
  49 #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
  50 #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
  51
  52 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
  53 #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
  54
  55 #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
  56 #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
  57
  58 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */
  59 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE   0x0002 /* 1=Reversal Disab. */
  60 #define GG82563_PSCR_CROSSOVER_MODE_MASK         0x0060
  61 #define GG82563_PSCR_CROSSOVER_MODE_MDI          0x0000 /* 00=Manual MDI */
  62 #define GG82563_PSCR_CROSSOVER_MODE_MDIX         0x0020 /* 01=Manual MDIX */
  63 #define GG82563_PSCR_CROSSOVER_MODE_AUTO         0x0060 /* 11=Auto crossover */
  64
  65 /* PHY Specific Control Register 2 (Page 0, Register 26) */
  66 #define GG82563_PSCR2_REVERSE_AUTO_NEG           0x2000
  67                                                 /* 1=Reverse Auto-Negotiation */
  68
  69 /* MAC Specific Control Register (Page 2, Register 21) */
  70 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
  71 #define GG82563_MSCR_TX_CLK_MASK                 0x0007
  72 #define GG82563_MSCR_TX_CLK_10MBPS_2_5           0x0004
  73 #define GG82563_MSCR_TX_CLK_100MBPS_25           0x0005
  74 #define GG82563_MSCR_TX_CLK_1000MBPS_25          0x0007
  75
  76 #define GG82563_MSCR_ASSERT_CRS_ON_TX            0x0010 /* 1=Assert */
  77
  78 /* DSP Distance Register (Page 5, Register 26) */
  79 #define GG82563_DSPD_CABLE_LENGTH                0x0007 /* 0 = <50M
  80                                                            1 = 50-80M
  81                                                            2 = 80-110M
  82                                                            3 = 110-140M
  83                                                            4 = >140M */
  84
  85 /* Kumeran Mode Control Register (Page 193, Register 16) */
  86 #define GG82563_KMCR_PASS_FALSE_CARRIER          0x0800
  87
  88 /* Power Management Control Register (Page 193, Register 20) */
  89 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE      0x0001
  90                                            /* 1=Enable SERDES Electrical Idle */
  91
  92 /* In-Band Control Register (Page 194, Register 18) */
  93 #define GG82563_ICR_DIS_PADDING                  0x0010 /* Disable Padding */
  94
  95 /*
  96  * A table for the GG82563 cable length where the range is defined
  97  * with a lower bound at "index" and the upper bound at
  98  * "index + 5".
  99  */
 100 static const u16 e1000_gg82563_cable_length_table[] =
 101          { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
 102
 103 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
 104 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 105 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
 106 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
 107 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
 108 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
 109 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
 110
 111 /**
 112  *  e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
 113  *  @hw: pointer to the HW structure
 114  *
 115  *  This is a function pointer entry point called by the api module.
 116  **/
 117 static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
 118 {
 119         struct e1000_phy_info *phy = &hw->phy;
 120         s32 ret_val;
 121
 122         if (hw->phy.media_type != e1000_media_type_copper) {
 123                 phy->type       = e1000_phy_none;
 124                 return 0;
 125         }
 126
 127         phy->addr               = 1;
 128         phy->autoneg_mask       = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 129         phy->reset_delay_us      = 100;
 130         phy->type               = e1000_phy_gg82563;
 131
 132         /* This can only be done after all function pointers are setup. */
 133         ret_val = e1000e_get_phy_id(hw);
 134
 135         /* Verify phy id */
 136         if (phy->id != GG82563_E_PHY_ID)
 137                 return -E1000_ERR_PHY;
 138
 139         return ret_val;
 140 }
 141
 142 /**
 143  *  e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
 144  *  @hw: pointer to the HW structure
 145  *
 146  *  This is a function pointer entry point called by the api module.
 147  **/
 148 static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
 149 {
 150         struct e1000_nvm_info *nvm = &hw->nvm;
 151         u32 eecd = er32(EECD);
 152         u16 size;
 153
 154         nvm->opcode_bits        = 8;
 155         nvm->delay_usec  = 1;
 156         switch (nvm->override) {
 157         case e1000_nvm_override_spi_large:
 158                 nvm->page_size    = 32;
 159                 nvm->address_bits = 16;
 160                 break;
 161         case e1000_nvm_override_spi_small:
 162                 nvm->page_size    = 8;
 163                 nvm->address_bits = 8;
 164                 break;
 165         default:
 166                 nvm->page_size    = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 167                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 168                 break;
 169         }
 170
 171         nvm->type = e1000_nvm_eeprom_spi;
 172
 173         size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 174                           E1000_EECD_SIZE_EX_SHIFT);
 175
 176         /*
 177          * Added to a constant, "size" becomes the left-shift value
 178          * for setting word_size.
 179          */
 180         size += NVM_WORD_SIZE_BASE_SHIFT;
 181         nvm->word_size  = 1 << size;
 182
 183         return 0;
 184 }
 185
 186 /**
 187  *  e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
 188  *  @hw: pointer to the HW structure
 189  *
 190  *  This is a function pointer entry point called by the api module.
 191  **/
 192 static s32 e1000_init_mac_params_80003es2lan(struct e1000_adapter *adapter)
 193 {
 194         struct e1000_hw *hw = &adapter->hw;
 195         struct e1000_mac_info *mac = &hw->mac;
 196         struct e1000_mac_operations *func = &mac->ops;
 197
 198         /* Set media type */
 199         switch (adapter->pdev->device) {
 200         case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
 201                 hw->phy.media_type = e1000_media_type_internal_serdes;
 202                 break;
 203         default:
 204                 hw->phy.media_type = e1000_media_type_copper;
 205                 break;
 206         }
 207
 208         /* Set mta register count */
 209         mac->mta_reg_count = 128;
 210         /* Set rar entry count */
 211         mac->rar_entry_count = E1000_RAR_ENTRIES;
 212         /* Set if manageability features are enabled. */
 213         mac->arc_subsystem_valid = (er32(FWSM) & E1000_FWSM_MODE_MASK) ? 1 : 0;
 214
 215         /* check for link */
 216         switch (hw->phy.media_type) {
 217         case e1000_media_type_copper:
 218                 func->setup_physical_interface = e1000_setup_copper_link_80003es2lan;
 219                 func->check_for_link = e1000e_check_for_copper_link;
 220                 break;
 221         case e1000_media_type_fiber:
 222                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
 223                 func->check_for_link = e1000e_check_for_fiber_link;
 224                 break;
 225         case e1000_media_type_internal_serdes:
 226                 func->setup_physical_interface = e1000e_setup_fiber_serdes_link;
 227                 func->check_for_link = e1000e_check_for_serdes_link;
 228                 break;
 229         default:
 230                 return -E1000_ERR_CONFIG;
 231                 break;
 232         }
 233
 234         return 0;
 235 }
 236
 237 static s32 e1000_get_invariants_80003es2lan(struct e1000_adapter *adapter)
 238 {
 239         struct e1000_hw *hw = &adapter->hw;
 240         s32 rc;
 241
 242         rc = e1000_init_mac_params_80003es2lan(adapter);
 243         if (rc)
 244                 return rc;
 245
 246         rc = e1000_init_nvm_params_80003es2lan(hw);
 247         if (rc)
 248                 return rc;
 249
 250         rc = e1000_init_phy_params_80003es2lan(hw);
 251         if (rc)
 252                 return rc;
 253
 254         return 0;
 255 }
 256
 257 /**
 258  *  e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
 259  *  @hw: pointer to the HW structure
 260  *
 261  *  A wrapper to acquire access rights to the correct PHY.  This is a
 262  *  function pointer entry point called by the api module.
 263  **/
 264 static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
 265 {
 266         u16 mask;
 267
 268         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 269
 270         return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
 271 }
 272
 273 /**
 274  *  e1000_release_phy_80003es2lan - Release rights to access PHY
 275  *  @hw: pointer to the HW structure
 276  *
 277  *  A wrapper to release access rights to the correct PHY.  This is a
 278  *  function pointer entry point called by the api module.
 279  **/
 280 static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
 281 {
 282         u16 mask;
 283
 284         mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
 285         e1000_release_swfw_sync_80003es2lan(hw, mask);
 286 }
 287
 288 /**
 289  *  e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
 290  *  @hw: pointer to the HW structure
 291  *
 292  *  Acquire the semaphore to access the EEPROM.  This is a function
 293  *  pointer entry point called by the api module.
 294  **/
 295 static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
 296 {
 297         s32 ret_val;
 298
 299         ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 300         if (ret_val)
 301                 return ret_val;
 302
 303         ret_val = e1000e_acquire_nvm(hw);
 304
 305         if (ret_val)
 306                 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 307
 308         return ret_val;
 309 }
 310
 311 /**
 312  *  e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
 313  *  @hw: pointer to the HW structure
 314  *
 315  *  Release the semaphore used to access the EEPROM.  This is a
 316  *  function pointer entry point called by the api module.
 317  **/
 318 static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
 319 {
 320         e1000e_release_nvm(hw);
 321         e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
 322 }
 323
 324 /**
 325  *  e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
 326  *  @hw: pointer to the HW structure
 327  *  @mask: specifies which semaphore to acquire
 328  *
 329  *  Acquire the SW/FW semaphore to access the PHY or NVM.  The mask
 330  *  will also specify which port we're acquiring the lock for.
 331  **/
 332 static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 333 {
 334         u32 swfw_sync;
 335         u32 swmask = mask;
 336         u32 fwmask = mask << 16;
 337         s32 i = 0;
 338         s32 timeout = 200;
 339
 340         while (i < timeout) {
 341                 if (e1000e_get_hw_semaphore(hw))
 342                         return -E1000_ERR_SWFW_SYNC;
 343
 344                 swfw_sync = er32(SW_FW_SYNC);
 345                 if (!(swfw_sync & (fwmask | swmask)))
 346                         break;
 347
 348                 /*
 349                  * Firmware currently using resource (fwmask)
 350                  * or other software thread using resource (swmask)
 351                  */
 352                 e1000e_put_hw_semaphore(hw);
 353                 mdelay(5);
 354                 i++;
 355         }
 356
 357         if (i == timeout) {
 358                 hw_dbg(hw,
 359                        "Driver can't access resource, SW_FW_SYNC timeout.\n");
 360                 return -E1000_ERR_SWFW_SYNC;
 361         }
 362
 363         swfw_sync |= swmask;
 364         ew32(SW_FW_SYNC, swfw_sync);
 365
 366         e1000e_put_hw_semaphore(hw);
 367
 368         return 0;
 369 }
 370
 371 /**
 372  *  e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
 373  *  @hw: pointer to the HW structure
 374  *  @mask: specifies which semaphore to acquire
 375  *
 376  *  Release the SW/FW semaphore used to access the PHY or NVM.  The mask
 377  *  will also specify which port we're releasing the lock for.
 378  **/
 379 static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
 380 {
 381         u32 swfw_sync;
 382
 383         while (e1000e_get_hw_semaphore(hw) != 0);
 384         /* Empty */
 385
 386         swfw_sync = er32(SW_FW_SYNC);
 387         swfw_sync &= ~mask;
 388         ew32(SW_FW_SYNC, swfw_sync);
 389
 390         e1000e_put_hw_semaphore(hw);
 391 }
 392
 393 /**
 394  *  e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
 395  *  @hw: pointer to the HW structure
 396  *  @offset: offset of the register to read
 397  *  @data: pointer to the data returned from the operation
 398  *
 399  *  Read the GG82563 PHY register.  This is a function pointer entry
 400  *  point called by the api module.
 401  **/
 402 static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 403                                                   u32 offset, u16 *data)
 404 {
 405         s32 ret_val;
 406         u32 page_select;
 407         u16 temp;
 408
 409         /* Select Configuration Page */
 410         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
 411                 page_select = GG82563_PHY_PAGE_SELECT;
 412         else
 413                 /*
 414                  * Use Alternative Page Select register to access
 415                  * registers 30 and 31
 416                  */
 417                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 418
 419         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 420         ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp);
 421         if (ret_val)
 422                 return ret_val;
 423
 424         /*
 425          * The "ready" bit in the MDIC register may be incorrectly set
 426          * before the device has completed the "Page Select" MDI
 427          * transaction.  So we wait 200us after each MDI command...
 428          */
 429         udelay(200);
 430
 431         /* ...and verify the command was successful. */
 432         ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp);
 433
 434         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
 435                 ret_val = -E1000_ERR_PHY;
 436                 return ret_val;
 437         }
 438
 439         udelay(200);
 440
 441         ret_val = e1000e_read_phy_reg_m88(hw,
 442                                          MAX_PHY_REG_ADDRESS & offset,
 443                                          data);
 444
 445         udelay(200);
 446
 447         return ret_val;
 448 }
 449
 450 /**
 451  *  e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
 452  *  @hw: pointer to the HW structure
 453  *  @offset: offset of the register to read
 454  *  @data: value to write to the register
 455  *
 456  *  Write to the GG82563 PHY register.  This is a function pointer entry
 457  *  point called by the api module.
 458  **/
 459 static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
 460                                                    u32 offset, u16 data)
 461 {
 462         s32 ret_val;
 463         u32 page_select;
 464         u16 temp;
 465
 466         /* Select Configuration Page */
 467         if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
 468                 page_select = GG82563_PHY_PAGE_SELECT;
 469         else
 470                 /*
 471                  * Use Alternative Page Select register to access
 472                  * registers 30 and 31
 473                  */
 474                 page_select = GG82563_PHY_PAGE_SELECT_ALT;
 475
 476         temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
 477         ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp);
 478         if (ret_val)
 479                 return ret_val;
 480
 481
 482         /*
 483          * The "ready" bit in the MDIC register may be incorrectly set
 484          * before the device has completed the "Page Select" MDI
 485          * transaction.  So we wait 200us after each MDI command...
 486          */
 487         udelay(200);
 488
 489         /* ...and verify the command was successful. */
 490         ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp);
 491
 492         if (((u16)offset >> GG82563_PAGE_SHIFT) != temp)
 493                 return -E1000_ERR_PHY;
 494
 495         udelay(200);
 496
 497         ret_val = e1000e_write_phy_reg_m88(hw,
 498                                           MAX_PHY_REG_ADDRESS & offset,
 499                                           data);
 500
 501         udelay(200);
 502
 503         return ret_val;
 504 }
 505
 506 /**
 507  *  e1000_write_nvm_80003es2lan - Write to ESB2 NVM
 508  *  @hw: pointer to the HW structure
 509  *  @offset: offset of the register to read
 510  *  @words: number of words to write
 511  *  @data: buffer of data to write to the NVM
 512  *
 513  *  Write "words" of data to the ESB2 NVM.  This is a function
 514  *  pointer entry point called by the api module.
 515  **/
 516 static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
 517                                        u16 words, u16 *data)
 518 {
 519         return e1000e_write_nvm_spi(hw, offset, words, data);
 520 }
 521
 522 /**
 523  *  e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
 524  *  @hw: pointer to the HW structure
 525  *
 526  *  Wait a specific amount of time for manageability processes to complete.
 527  *  This is a function pointer entry point called by the phy module.
 528  **/
 529 static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
 530 {
 531         s32 timeout = PHY_CFG_TIMEOUT;
 532         u32 mask = E1000_NVM_CFG_DONE_PORT_0;
 533
 534         if (hw->bus.func == 1)
 535                 mask = E1000_NVM_CFG_DONE_PORT_1;
 536
 537         while (timeout) {
 538                 if (er32(EEMNGCTL) & mask)
 539                         break;
 540                 msleep(1);
 541                 timeout--;
 542         }
 543         if (!timeout) {
 544                 hw_dbg(hw, "MNG configuration cycle has not completed.\n");
 545                 return -E1000_ERR_RESET;
 546         }
 547
 548         return 0;
 549 }
 550
 551 /**
 552  *  e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
 553  *  @hw: pointer to the HW structure
 554  *
 555  *  Force the speed and duplex settings onto the PHY.  This is a
 556  *  function pointer entry point called by the phy module.
 557  **/
 558 static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
 559 {
 560         s32 ret_val;
 561         u16 phy_data;
 562         bool link;
 563
 564         /*
 565          * Clear Auto-Crossover to force MDI manually.  M88E1000 requires MDI
 566          * forced whenever speed and duplex are forced.
 567          */
 568         ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
 569         if (ret_val)
 570                 return ret_val;
 571
 572         phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
 573         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
 574         if (ret_val)
 575                 return ret_val;
 576
 577         hw_dbg(hw, "GG82563 PSCR: %X\n", phy_data);
 578
 579         ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
 580         if (ret_val)
 581                 return ret_val;
 582
 583         e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
 584
 585         /* Reset the phy to commit changes. */
 586         phy_data |= MII_CR_RESET;
 587
 588         ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
 589         if (ret_val)
 590                 return ret_val;
 591
 592         udelay(1);
 593
 594         if (hw->phy.autoneg_wait_to_complete) {
 595                 hw_dbg(hw, "Waiting for forced speed/duplex link "
 596                          "on GG82563 phy.\n");
 597
 598                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 599                                                      100000, &link);
 600                 if (ret_val)
 601                         return ret_val;
 602
 603                 if (!link) {
 604                         /*
 605                          * We didn't get link.
 606                          * Reset the DSP and cross our fingers.
 607                          */
 608                         ret_val = e1000e_phy_reset_dsp(hw);
 609                         if (ret_val)
 610                                 return ret_val;
 611                 }
 612
 613                 /* Try once more */
 614                 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
 615                                                      100000, &link);
 616                 if (ret_val)
 617                         return ret_val;
 618         }
 619
 620         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
 621         if (ret_val)
 622                 return ret_val;
 623
 624         /*
 625          * Resetting the phy means we need to verify the TX_CLK corresponds
 626          * to the link speed.  10Mbps -> 2.5MHz, else 25MHz.
 627          */
 628         phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
 629         if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
 630                 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
 631         else
 632                 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
 633
 634         /*
 635          * In addition, we must re-enable CRS on Tx for both half and full
 636          * duplex.
 637          */
 638         phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 639         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
 640
 641         return ret_val;
 642 }
 643
 644 /**
 645  *  e1000_get_cable_length_80003es2lan - Set approximate cable length
 646  *  @hw: pointer to the HW structure
 647  *
 648  *  Find the approximate cable length as measured by the GG82563 PHY.
 649  *  This is a function pointer entry point called by the phy module.
 650  **/
 651 static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
 652 {
 653         struct e1000_phy_info *phy = &hw->phy;
 654         s32 ret_val;
 655         u16 phy_data;
 656         u16 index;
 657
 658         ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
 659         if (ret_val)
 660                 return ret_val;
 661
 662         index = phy_data & GG82563_DSPD_CABLE_LENGTH;
 663         phy->min_cable_length = e1000_gg82563_cable_length_table[index];
 664         phy->max_cable_length = e1000_gg82563_cable_length_table[index+5];
 665
 666         phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
 667
 668         return 0;
 669 }
 670
 671 /**
 672  *  e1000_get_link_up_info_80003es2lan - Report speed and duplex
 673  *  @hw: pointer to the HW structure
 674  *  @speed: pointer to speed buffer
 675  *  @duplex: pointer to duplex buffer
 676  *
 677  *  Retrieve the current speed and duplex configuration.
 678  *  This is a function pointer entry point called by the api module.
 679  **/
 680 static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
 681                                               u16 *duplex)
 682 {
 683         s32 ret_val;
 684
 685         if (hw->phy.media_type == e1000_media_type_copper) {
 686                 ret_val = e1000e_get_speed_and_duplex_copper(hw,
 687                                                                     speed,
 688                                                                     duplex);
 689                 if (ret_val)
 690                         return ret_val;
 691                 if (*speed == SPEED_1000)
 692                         ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
 693                 else
 694                         ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw,
 695                                                               *duplex);
 696         } else {
 697                 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
 698                                                                   speed,
 699                                                                   duplex);
 700         }
 701
 702         return ret_val;
 703 }
 704
 705 /**
 706  *  e1000_reset_hw_80003es2lan - Reset the ESB2 controller
 707  *  @hw: pointer to the HW structure
 708  *
 709  *  Perform a global reset to the ESB2 controller.
 710  *  This is a function pointer entry point called by the api module.
 711  **/
 712 static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
 713 {
 714         u32 ctrl;
 715         u32 icr;
 716         s32 ret_val;
 717
 718         /*
 719          * Prevent the PCI-E bus from sticking if there is no TLP connection
 720          * on the last TLP read/write transaction when MAC is reset.
 721          */
 722         ret_val = e1000e_disable_pcie_master(hw);
 723         if (ret_val)
 724                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 725
 726         hw_dbg(hw, "Masking off all interrupts\n");
 727         ew32(IMC, 0xffffffff);
 728
 729         ew32(RCTL, 0);
 730         ew32(TCTL, E1000_TCTL_PSP);
 731         e1e_flush();
 732
 733         msleep(10);
 734
 735         ctrl = er32(CTRL);
 736
 737         hw_dbg(hw, "Issuing a global reset to MAC\n");
 738         ew32(CTRL, ctrl | E1000_CTRL_RST);
 739
 740         ret_val = e1000e_get_auto_rd_done(hw);
 741         if (ret_val)
 742                 /* We don't want to continue accessing MAC registers. */
 743                 return ret_val;
 744
 745         /* Clear any pending interrupt events. */
 746         ew32(IMC, 0xffffffff);
 747         icr = er32(ICR);
 748
 749         return 0;
 750 }
 751
 752 /**
 753  *  e1000_init_hw_80003es2lan - Initialize the ESB2 controller
 754  *  @hw: pointer to the HW structure
 755  *
 756  *  Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
 757  *  This is a function pointer entry point called by the api module.
 758  **/
 759 static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
 760 {
 761         struct e1000_mac_info *mac = &hw->mac;
 762         u32 reg_data;
 763         s32 ret_val;
 764         u16 i;
 765
 766         e1000_initialize_hw_bits_80003es2lan(hw);
 767
 768         /* Initialize identification LED */
 769         ret_val = e1000e_id_led_init(hw);
 770         if (ret_val) {
 771                 hw_dbg(hw, "Error initializing identification LED\n");
 772                 return ret_val;
 773         }
 774
 775         /* Disabling VLAN filtering */
 776         hw_dbg(hw, "Initializing the IEEE VLAN\n");
 777         e1000e_clear_vfta(hw);
 778
 779         /* Setup the receive address. */
 780         e1000e_init_rx_addrs(hw, mac->rar_entry_count);
 781
 782         /* Zero out the Multicast HASH table */
 783         hw_dbg(hw, "Zeroing the MTA\n");
 784         for (i = 0; i < mac->mta_reg_count; i++)
 785                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 786
 787         /* Setup link and flow control */
 788         ret_val = e1000e_setup_link(hw);
 789
 790         /* Set the transmit descriptor write-back policy */
 791         reg_data = er32(TXDCTL);
 792         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 793                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 794         ew32(TXDCTL, reg_data);
 795
 796         /* ...for both queues. */
 797         reg_data = er32(TXDCTL1);
 798         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 799                    E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
 800         ew32(TXDCTL1, reg_data);
 801
 802         /* Enable retransmit on late collisions */
 803         reg_data = er32(TCTL);
 804         reg_data |= E1000_TCTL_RTLC;
 805         ew32(TCTL, reg_data);
 806
 807         /* Configure Gigabit Carry Extend Padding */
 808         reg_data = er32(TCTL_EXT);
 809         reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
 810         reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
 811         ew32(TCTL_EXT, reg_data);
 812
 813         /* Configure Transmit Inter-Packet Gap */
 814         reg_data = er32(TIPG);
 815         reg_data &= ~E1000_TIPG_IPGT_MASK;
 816         reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
 817         ew32(TIPG, reg_data);
 818
 819         reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
 820         reg_data &= ~0x00100000;
 821         E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
 822
 823         /*
 824          * Clear all of the statistics registers (clear on read).  It is
 825          * important that we do this after we have tried to establish link
 826          * because the symbol error count will increment wildly if there
 827          * is no link.
 828          */
 829         e1000_clear_hw_cntrs_80003es2lan(hw);
 830
 831         return ret_val;
 832 }
 833
 834 /**
 835  *  e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
 836  *  @hw: pointer to the HW structure
 837  *
 838  *  Initializes required hardware-dependent bits needed for normal operation.
 839  **/
 840 static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
 841 {
 842         u32 reg;
 843
 844         /* Transmit Descriptor Control 0 */
 845         reg = er32(TXDCTL);
 846         reg |= (1 << 22);
 847         ew32(TXDCTL, reg);
 848
 849         /* Transmit Descriptor Control 1 */
 850         reg = er32(TXDCTL1);
 851         reg |= (1 << 22);
 852         ew32(TXDCTL1, reg);
 853
 854         /* Transmit Arbitration Control 0 */
 855         reg = er32(TARC0);
 856         reg &= ~(0xF << 27); /* 30:27 */
 857         if (hw->phy.media_type != e1000_media_type_copper)
 858                 reg &= ~(1 << 20);
 859         ew32(TARC0, reg);
 860
 861         /* Transmit Arbitration Control 1 */
 862         reg = er32(TARC1);
 863         if (er32(TCTL) & E1000_TCTL_MULR)
 864                 reg &= ~(1 << 28);
 865         else
 866                 reg |= (1 << 28);
 867         ew32(TARC1, reg);
 868 }
 869
 870 /**
 871  *  e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
 872  *  @hw: pointer to the HW structure
 873  *
 874  *  Setup some GG82563 PHY registers for obtaining link
 875  **/
 876 static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
 877 {
 878         struct e1000_phy_info *phy = &hw->phy;
 879         s32 ret_val;
 880         u32 ctrl_ext;
 881         u16 data;
 882
 883         ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
 884                                      &data);
 885         if (ret_val)
 886                 return ret_val;
 887
 888         data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
 889         /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
 890         data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
 891
 892         ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL,
 893                                       data);
 894         if (ret_val)
 895                 return ret_val;
 896
 897         /*
 898          * Options:
 899          *   MDI/MDI-X = 0 (default)
 900          *   0 - Auto for all speeds
 901          *   1 - MDI mode
 902          *   2 - MDI-X mode
 903          *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
 904          */
 905         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
 906         if (ret_val)
 907                 return ret_val;
 908
 909         data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
 910
 911         switch (phy->mdix) {
 912         case 1:
 913                 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
 914                 break;
 915         case 2:
 916                 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
 917                 break;
 918         case 0:
 919         default:
 920                 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
 921                 break;
 922         }
 923
 924         /*
 925          * Options:
 926          *   disable_polarity_correction = 0 (default)
 927          *       Automatic Correction for Reversed Cable Polarity
 928          *   0 - Disabled
 929          *   1 - Enabled
 930          */
 931         data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 932         if (phy->disable_polarity_correction)
 933                 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
 934
 935         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
 936         if (ret_val)
 937                 return ret_val;
 938
 939         /* SW Reset the PHY so all changes take effect */
 940         ret_val = e1000e_commit_phy(hw);
 941         if (ret_val) {
 942                 hw_dbg(hw, "Error Resetting the PHY\n");
 943                 return ret_val;
 944         }
 945
 946         /* Bypass Rx and Tx FIFO's */
 947         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
 948                                         E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
 949                                         E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
 950         if (ret_val)
 951                 return ret_val;
 952
 953         ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
 954         if (ret_val)
 955                 return ret_val;
 956
 957         data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
 958         ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
 959         if (ret_val)
 960                 return ret_val;
 961
 962         ctrl_ext = er32(CTRL_EXT);
 963         ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
 964         ew32(CTRL_EXT, ctrl_ext);
 965
 966         ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
 967         if (ret_val)
 968                 return ret_val;
 969
 970         /*
 971          * Do not init these registers when the HW is in IAMT mode, since the
 972          * firmware will have already initialized them.  We only initialize
 973          * them if the HW is not in IAMT mode.
 974          */
 975         if (!e1000e_check_mng_mode(hw)) {
 976                 /* Enable Electrical Idle on the PHY */
 977                 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
 978                 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
 979                 if (ret_val)
 980                         return ret_val;
 981
 982                 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
 983                 if (ret_val)
 984                         return ret_val;
 985
 986                 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
 987                 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
 988                 if (ret_val)
 989                         return ret_val;
 990         }
 991
 992         /*
 993          * Workaround: Disable padding in Kumeran interface in the MAC
 994          * and in the PHY to avoid CRC errors.
 995          */
 996         ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
 997         if (ret_val)
 998                 return ret_val;
 999
1000         data |= GG82563_ICR_DIS_PADDING;
1001         ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1002         if (ret_val)
1003                 return ret_val;
1004
1005         return 0;
1006 }
1007
1008 /**
1009  *  e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1010  *  @hw: pointer to the HW structure
1011  *
1012  *  Essentially a wrapper for setting up all things "copper" related.
1013  *  This is a function pointer entry point called by the mac module.
1014  **/
1015 static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1016 {
1017         u32 ctrl;
1018         s32 ret_val;
1019         u16 reg_data;
1020
1021         ctrl = er32(CTRL);
1022         ctrl |= E1000_CTRL_SLU;
1023         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1024         ew32(CTRL, ctrl);
1025
1026         /*
1027          * Set the mac to wait the maximum time between each
1028          * iteration and increase the max iterations when
1029          * polling the phy; this fixes erroneous timeouts at 10Mbps.
1030          */
1031         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1032         if (ret_val)
1033                 return ret_val;
1034         ret_val = e1000e_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1035         if (ret_val)
1036                 return ret_val;
1037         reg_data |= 0x3F;
1038         ret_val = e1000e_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
1039         if (ret_val)
1040                 return ret_val;
1041         ret_val = e1000e_read_kmrn_reg(hw,
1042                                       E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1043                                       &reg_data);
1044         if (ret_val)
1045                 return ret_val;
1046         reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1047         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1048                                         reg_data);
1049         if (ret_val)
1050                 return ret_val;
1051
1052         ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1053         if (ret_val)
1054                 return ret_val;
1055
1056         ret_val = e1000e_setup_copper_link(hw);
1057
1058         return 0;
1059 }
1060
1061 /**
1062  *  e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1063  *  @hw: pointer to the HW structure
1064  *  @duplex: current duplex setting
1065  *
1066  *  Configure the KMRN interface by applying last minute quirks for
1067  *  10/100 operation.
1068  **/
1069 static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1070 {
1071         s32 ret_val;
1072         u32 tipg;
1073         u16 reg_data;
1074
1075         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1076         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1077                                         reg_data);
1078         if (ret_val)
1079                 return ret_val;
1080
1081         /* Configure Transmit Inter-Packet Gap */
1082         tipg = er32(TIPG);
1083         tipg &= ~E1000_TIPG_IPGT_MASK;
1084         tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1085         ew32(TIPG, tipg);
1086
1087         ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1088         if (ret_val)
1089                 return ret_val;
1090
1091         if (duplex == HALF_DUPLEX)
1092                 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1093         else
1094                 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1095
1096         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1097
1098         return 0;
1099 }
1100
1101 /**
1102  *  e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1103  *  @hw: pointer to the HW structure
1104  *
1105  *  Configure the KMRN interface by applying last minute quirks for
1106  *  gigabit operation.
1107  **/
1108 static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1109 {
1110         s32 ret_val;
1111         u16 reg_data;
1112         u32 tipg;
1113
1114         reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1115         ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1116                                         reg_data);
1117         if (ret_val)
1118                 return ret_val;
1119
1120         /* Configure Transmit Inter-Packet Gap */
1121         tipg = er32(TIPG);
1122         tipg &= ~E1000_TIPG_IPGT_MASK;
1123         tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1124         ew32(TIPG, tipg);
1125
1126         ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
1127         if (ret_val)
1128                 return ret_val;
1129
1130         reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1131         ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1132
1133         return ret_val;
1134 }
1135
1136 /**
1137  *  e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1138  *  @hw: pointer to the HW structure
1139  *
1140  *  Clears the hardware counters by reading the counter registers.
1141  **/
1142 static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1143 {
1144         u32 temp;
1145
1146         e1000e_clear_hw_cntrs_base(hw);
1147
1148         temp = er32(PRC64);
1149         temp = er32(PRC127);
1150         temp = er32(PRC255);
1151         temp = er32(PRC511);
1152         temp = er32(PRC1023);
1153         temp = er32(PRC1522);
1154         temp = er32(PTC64);
1155         temp = er32(PTC127);
1156         temp = er32(PTC255);
1157         temp = er32(PTC511);
1158         temp = er32(PTC1023);
1159         temp = er32(PTC1522);
1160
1161         temp = er32(ALGNERRC);
1162         temp = er32(RXERRC);
1163         temp = er32(TNCRS);
1164         temp = er32(CEXTERR);
1165         temp = er32(TSCTC);
1166         temp = er32(TSCTFC);
1167
1168         temp = er32(MGTPRC);
1169         temp = er32(MGTPDC);
1170         temp = er32(MGTPTC);
1171
1172         temp = er32(IAC);
1173         temp = er32(ICRXOC);
1174
1175         temp = er32(ICRXPTC);
1176         temp = er32(ICRXATC);
1177         temp = er32(ICTXPTC);
1178         temp = er32(ICTXATC);
1179         temp = er32(ICTXQEC);
1180         temp = er32(ICTXQMTC);
1181         temp = er32(ICRXDMTC);
1182 }
1183
1184 static struct e1000_mac_operations es2_mac_ops = {
1185         .mng_mode_enab          = E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT,
1186         /* check_for_link dependent on media type */
1187         .cleanup_led            = e1000e_cleanup_led_generic,
1188         .clear_hw_cntrs         = e1000_clear_hw_cntrs_80003es2lan,
1189         .get_bus_info           = e1000e_get_bus_info_pcie,
1190         .get_link_up_info       = e1000_get_link_up_info_80003es2lan,
1191         .led_on                 = e1000e_led_on_generic,
1192         .led_off                = e1000e_led_off_generic,
1193         .update_mc_addr_list    = e1000e_update_mc_addr_list_generic,
1194         .reset_hw               = e1000_reset_hw_80003es2lan,
1195         .init_hw                = e1000_init_hw_80003es2lan,
1196         .setup_link             = e1000e_setup_link,
1197         /* setup_physical_interface dependent on media type */
1198 };
1199
1200 static struct e1000_phy_operations es2_phy_ops = {
1201         .acquire_phy            = e1000_acquire_phy_80003es2lan,
1202         .check_reset_block      = e1000e_check_reset_block_generic,
1203         .commit_phy             = e1000e_phy_sw_reset,
1204         .force_speed_duplex     = e1000_phy_force_speed_duplex_80003es2lan,
1205         .get_cfg_done           = e1000_get_cfg_done_80003es2lan,
1206         .get_cable_length       = e1000_get_cable_length_80003es2lan,
1207         .get_phy_info           = e1000e_get_phy_info_m88,
1208         .read_phy_reg           = e1000_read_phy_reg_gg82563_80003es2lan,
1209         .release_phy            = e1000_release_phy_80003es2lan,
1210         .reset_phy              = e1000e_phy_hw_reset_generic,
1211         .set_d0_lplu_state      = NULL,
1212         .set_d3_lplu_state      = e1000e_set_d3_lplu_state,
1213         .write_phy_reg          = e1000_write_phy_reg_gg82563_80003es2lan,
1214 };
1215
1216 static struct e1000_nvm_operations es2_nvm_ops = {
1217         .acquire_nvm            = e1000_acquire_nvm_80003es2lan,
1218         .read_nvm               = e1000e_read_nvm_eerd,
1219         .release_nvm            = e1000_release_nvm_80003es2lan,
1220         .update_nvm             = e1000e_update_nvm_checksum_generic,
1221         .valid_led_default      = e1000e_valid_led_default,
1222         .validate_nvm           = e1000e_validate_nvm_checksum_generic,
1223         .write_nvm              = e1000_write_nvm_80003es2lan,
1224 };
1225
1226 struct e1000_info e1000_es2_info = {
1227         .mac                    = e1000_80003es2lan,
1228         .flags                  = FLAG_HAS_HW_VLAN_FILTER
1229                                   | FLAG_HAS_JUMBO_FRAMES
1230                                   | FLAG_HAS_STATS_PTC_PRC
1231                                   | FLAG_HAS_WOL
1232                                   | FLAG_APME_IN_CTRL3
1233                                   | FLAG_RX_CSUM_ENABLED
1234                                   | FLAG_HAS_CTRLEXT_ON_LOAD
1235                                   | FLAG_HAS_STATS_ICR_ICT
1236                                   | FLAG_RX_NEEDS_RESTART /* errata */
1237                                   | FLAG_TARC_SET_BIT_ZERO /* errata */
1238                                   | FLAG_APME_CHECK_PORT_B
1239                                   | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
1240                                   | FLAG_TIPG_MEDIUM_FOR_80003ESLAN,
1241         .pba                    = 38,
1242         .get_invariants         = e1000_get_invariants_80003es2lan,
1243         .mac_ops                = &es2_mac_ops,
1244         .phy_ops                = &es2_phy_ops,
1245         .nvm_ops                = &es2_nvm_ops,
1246 };
1247