1 /* $Date: 2006/04/28 19:20:06 $ $RCSfile: vsc7326.c,v $ $Revision: 1.19 $ */
3 /* Driver for Vitesse VSC7326 (Schaumburg) MAC */
7 #include "vsc7326_reg.h"
9 /* Update fast changing statistics every 15 seconds */
10 #define STATS_TICK_SECS 15
11 /* 30 minutes for full statistics update */
12 #define MAJOR_UPDATE_TICKS (1800 / STATS_TICK_SECS)
16 /* The egress WM value 0x01a01fff should be used only when the
17 * interface is down (MAC port disabled). This is a workaround
18 * for disabling the T2/MAC flow-control. When the interface is
19 * enabled, the WM value should be set to 0x014a03F0.
21 #define WM_DISABLE 0x01a01fff
22 #define WM_ENABLE 0x014a03F0
29 struct _cmac_instance {
34 #define INITBLOCK_SLEEP 0xffffffff
36 static void vsc_read(adapter_t *adapter, u32 addr, u32 *val)
41 spin_lock_bh(&adapter->mac_lock);
42 t1_tpi_read(adapter, (addr << 2) + 4, &vlo);
45 t1_tpi_read(adapter, (REG_LOCAL_STATUS << 2) + 4, &vlo);
46 t1_tpi_read(adapter, REG_LOCAL_STATUS << 2, &vhi);
47 status = (vhi << 16) | vlo;
49 } while (((status & 1) == 0) && (i < 50));
51 CH_ERR("Invalid tpi read from MAC, breaking loop.\n");
53 t1_tpi_read(adapter, (REG_LOCAL_DATA << 2) + 4, &vlo);
54 t1_tpi_read(adapter, REG_LOCAL_DATA << 2, &vhi);
56 *val = (vhi << 16) | vlo;
58 /* CH_ERR("rd: block: 0x%x sublock: 0x%x reg: 0x%x data: 0x%x\n",
59 ((addr&0xe000)>>13), ((addr&0x1e00)>>9),
60 ((addr&0x01fe)>>1), *val); */
61 spin_unlock_bh(&adapter->mac_lock);
64 static void vsc_write(adapter_t *adapter, u32 addr, u32 data)
66 spin_lock_bh(&adapter->mac_lock);
67 t1_tpi_write(adapter, (addr << 2) + 4, data & 0xFFFF);
68 t1_tpi_write(adapter, addr << 2, (data >> 16) & 0xFFFF);
69 /* CH_ERR("wr: block: 0x%x sublock: 0x%x reg: 0x%x data: 0x%x\n",
70 ((addr&0xe000)>>13), ((addr&0x1e00)>>9),
71 ((addr&0x01fe)>>1), data); */
72 spin_unlock_bh(&adapter->mac_lock);
75 /* Hard reset the MAC. This wipes out *all* configuration. */
76 static void vsc7326_full_reset(adapter_t* adapter)
81 t1_tpi_read(adapter, A_ELMER0_GPO, &val);
83 t1_tpi_write(adapter, A_ELMER0_GPO, val);
85 val |= 0x1; /* Enable mac MAC itself */
86 val |= 0x800; /* Turn off the red LED */
87 t1_tpi_write(adapter, A_ELMER0_GPO, val);
89 vsc_write(adapter, REG_SW_RESET, 0x80000001);
92 vsc_read(adapter, REG_SW_RESET, &result);
93 } while (result != 0x0);
96 static struct init_table vsc7326_reset[] = {
97 { REG_IFACE_MODE, 0x00000000 },
98 { REG_CRC_CFG, 0x00000020 },
99 { REG_PLL_CLK_SPEED, 0x00050c00 },
100 { REG_PLL_CLK_SPEED, 0x00050c00 },
101 { REG_MSCH, 0x00002f14 },
102 { REG_SPI4_MISC, 0x00040409 },
103 { REG_SPI4_DESKEW, 0x00080000 },
104 { REG_SPI4_ING_SETUP2, 0x08080004 },
105 { REG_SPI4_ING_SETUP0, 0x04111004 },
106 { REG_SPI4_EGR_SETUP0, 0x80001a04 },
107 { REG_SPI4_ING_SETUP1, 0x02010000 },
108 { REG_AGE_INC(0), 0x00000000 },
109 { REG_AGE_INC(1), 0x00000000 },
110 { REG_ING_CONTROL, 0x0a200011 },
111 { REG_EGR_CONTROL, 0xa0010091 },
114 static struct init_table vsc7326_portinit[4][22] = {
117 { REG_DBG(0), 0x000004f0 },
118 { REG_HDX(0), 0x00073101 },
119 { REG_TEST(0,0), 0x00000022 },
120 { REG_TEST(1,0), 0x00000022 },
121 { REG_TOP_BOTTOM(0,0), 0x003f0000 },
122 { REG_TOP_BOTTOM(1,0), 0x00120000 },
123 { REG_HIGH_LOW_WM(0,0), 0x07460757 },
124 { REG_HIGH_LOW_WM(1,0), WM_DISABLE },
125 { REG_CT_THRHLD(0,0), 0x00000000 },
126 { REG_CT_THRHLD(1,0), 0x00000000 },
127 { REG_BUCKE(0), 0x0002ffff },
128 { REG_BUCKI(0), 0x0002ffff },
129 { REG_TEST(0,0), 0x00000020 },
130 { REG_TEST(1,0), 0x00000020 },
132 { REG_MAX_LEN(0), 0x00002710 },
133 { REG_PORT_FAIL(0), 0x00000002 },
134 { REG_NORMALIZER(0), 0x00000a64 },
135 { REG_DENORM(0), 0x00000010 },
136 { REG_STICK_BIT(0), 0x03baa370 },
137 { REG_DEV_SETUP(0), 0x00000083 },
138 { REG_DEV_SETUP(0), 0x00000082 },
139 { REG_MODE_CFG(0), 0x0200259f },
143 { REG_DBG(1), 0x000004f0 },
144 { REG_HDX(1), 0x00073101 },
145 { REG_TEST(0,1), 0x00000022 },
146 { REG_TEST(1,1), 0x00000022 },
147 { REG_TOP_BOTTOM(0,1), 0x007e003f },
148 { REG_TOP_BOTTOM(1,1), 0x00240012 },
149 { REG_HIGH_LOW_WM(0,1), 0x07460757 },
150 { REG_HIGH_LOW_WM(1,1), WM_DISABLE },
151 { REG_CT_THRHLD(0,1), 0x00000000 },
152 { REG_CT_THRHLD(1,1), 0x00000000 },
153 { REG_BUCKE(1), 0x0002ffff },
154 { REG_BUCKI(1), 0x0002ffff },
155 { REG_TEST(0,1), 0x00000020 },
156 { REG_TEST(1,1), 0x00000020 },
158 { REG_MAX_LEN(1), 0x00002710 },
159 { REG_PORT_FAIL(1), 0x00000002 },
160 { REG_NORMALIZER(1), 0x00000a64 },
161 { REG_DENORM(1), 0x00000010 },
162 { REG_STICK_BIT(1), 0x03baa370 },
163 { REG_DEV_SETUP(1), 0x00000083 },
164 { REG_DEV_SETUP(1), 0x00000082 },
165 { REG_MODE_CFG(1), 0x0200259f },
169 { REG_DBG(2), 0x000004f0 },
170 { REG_HDX(2), 0x00073101 },
171 { REG_TEST(0,2), 0x00000022 },
172 { REG_TEST(1,2), 0x00000022 },
173 { REG_TOP_BOTTOM(0,2), 0x00bd007e },
174 { REG_TOP_BOTTOM(1,2), 0x00360024 },
175 { REG_HIGH_LOW_WM(0,2), 0x07460757 },
176 { REG_HIGH_LOW_WM(1,2), WM_DISABLE },
177 { REG_CT_THRHLD(0,2), 0x00000000 },
178 { REG_CT_THRHLD(1,2), 0x00000000 },
179 { REG_BUCKE(2), 0x0002ffff },
180 { REG_BUCKI(2), 0x0002ffff },
181 { REG_TEST(0,2), 0x00000020 },
182 { REG_TEST(1,2), 0x00000020 },
184 { REG_MAX_LEN(2), 0x00002710 },
185 { REG_PORT_FAIL(2), 0x00000002 },
186 { REG_NORMALIZER(2), 0x00000a64 },
187 { REG_DENORM(2), 0x00000010 },
188 { REG_STICK_BIT(2), 0x03baa370 },
189 { REG_DEV_SETUP(2), 0x00000083 },
190 { REG_DEV_SETUP(2), 0x00000082 },
191 { REG_MODE_CFG(2), 0x0200259f },
195 { REG_DBG(3), 0x000004f0 },
196 { REG_HDX(3), 0x00073101 },
197 { REG_TEST(0,3), 0x00000022 },
198 { REG_TEST(1,3), 0x00000022 },
199 { REG_TOP_BOTTOM(0,3), 0x00fc00bd },
200 { REG_TOP_BOTTOM(1,3), 0x00480036 },
201 { REG_HIGH_LOW_WM(0,3), 0x07460757 },
202 { REG_HIGH_LOW_WM(1,3), WM_DISABLE },
203 { REG_CT_THRHLD(0,3), 0x00000000 },
204 { REG_CT_THRHLD(1,3), 0x00000000 },
205 { REG_BUCKE(3), 0x0002ffff },
206 { REG_BUCKI(3), 0x0002ffff },
207 { REG_TEST(0,3), 0x00000020 },
208 { REG_TEST(1,3), 0x00000020 },
210 { REG_MAX_LEN(3), 0x00002710 },
211 { REG_PORT_FAIL(3), 0x00000002 },
212 { REG_NORMALIZER(3), 0x00000a64 },
213 { REG_DENORM(3), 0x00000010 },
214 { REG_STICK_BIT(3), 0x03baa370 },
215 { REG_DEV_SETUP(3), 0x00000083 },
216 { REG_DEV_SETUP(3), 0x00000082 },
217 { REG_MODE_CFG(3), 0x0200259f },
221 static void run_table(adapter_t *adapter, struct init_table *ib, int len)
225 for (i = 0; i < len; i++) {
226 if (ib[i].addr == INITBLOCK_SLEEP) {
227 udelay( ib[i].data );
228 CH_ERR("sleep %d us\n",ib[i].data);
230 vsc_write( adapter, ib[i].addr, ib[i].data );
235 static int bist_rd(adapter_t *adapter, int moduleid, int address)
240 if ((address != 0x0) &&
245 CH_ERR("No bist address: 0x%x\n", address);
247 data = ((0x00 << 24) | ((address & 0xff) << 16) | (0x00 << 8) |
248 ((moduleid & 0xff) << 0));
249 vsc_write(adapter, REG_RAM_BIST_CMD, data);
253 vsc_read(adapter, REG_RAM_BIST_RESULT, &result);
254 if ((result & (1 << 9)) != 0x0)
255 CH_ERR("Still in bist read: 0x%x\n", result);
256 else if ((result & (1 << 8)) != 0x0)
257 CH_ERR("bist read error: 0x%x\n", result);
259 return (result & 0xff);
262 static int bist_wr(adapter_t *adapter, int moduleid, int address, int value)
267 if ((address != 0x0) &&
272 CH_ERR("No bist address: 0x%x\n", address);
275 CH_ERR("Suspicious write out of range value: 0x%x\n", value);
277 data = ((0x01 << 24) | ((address & 0xff) << 16) | (value << 8) |
278 ((moduleid & 0xff) << 0));
279 vsc_write(adapter, REG_RAM_BIST_CMD, data);
283 vsc_read(adapter, REG_RAM_BIST_CMD, &result);
284 if ((result & (1 << 27)) != 0x0)
285 CH_ERR("Still in bist write: 0x%x\n", result);
286 else if ((result & (1 << 26)) != 0x0)
287 CH_ERR("bist write error: 0x%x\n", result);
292 static int run_bist(adapter_t *adapter, int moduleid)
295 (void) bist_wr(adapter,moduleid, 0x00, 0x02);
296 (void) bist_wr(adapter,moduleid, 0x01, 0x01);
301 static int check_bist(adapter_t *adapter, int moduleid)
306 result = bist_rd(adapter,moduleid, 0x02);
307 column = ((bist_rd(adapter,moduleid, 0x0e)<<8) +
308 (bist_rd(adapter,moduleid, 0x0d)));
309 if ((result & 3) != 0x3)
310 CH_ERR("Result: 0x%x BIST error in ram %d, column: 0x%04x\n",
311 result, moduleid, column);
315 static int enable_mem(adapter_t *adapter, int moduleid)
318 (void) bist_wr(adapter,moduleid, 0x00, 0x00);
322 static int run_bist_all(adapter_t *adapter)
327 vsc_write(adapter, REG_MEM_BIST, 0x5);
328 vsc_read(adapter, REG_MEM_BIST, &val);
330 for (port = 0; port < 12; port++)
331 vsc_write(adapter, REG_DEV_SETUP(port), 0x0);
334 vsc_write(adapter, REG_SPI4_MISC, 0x00040409);
337 (void) run_bist(adapter,13);
338 (void) run_bist(adapter,14);
339 (void) run_bist(adapter,20);
340 (void) run_bist(adapter,21);
342 (void) check_bist(adapter,13);
343 (void) check_bist(adapter,14);
344 (void) check_bist(adapter,20);
345 (void) check_bist(adapter,21);
347 (void) enable_mem(adapter,13);
348 (void) enable_mem(adapter,14);
349 (void) enable_mem(adapter,20);
350 (void) enable_mem(adapter,21);
352 vsc_write(adapter, REG_SPI4_MISC, 0x60040400);
354 for (port = 0; port < 12; port++)
355 vsc_write(adapter, REG_DEV_SETUP(port), 0x1);
358 vsc_write(adapter, REG_MEM_BIST, 0x0);
363 static int mac_intr_handler(struct cmac *mac)
368 static int mac_intr_enable(struct cmac *mac)
373 static int mac_intr_disable(struct cmac *mac)
378 static int mac_intr_clear(struct cmac *mac)
383 /* Expect MAC address to be in network byte order. */
384 static int mac_set_address(struct cmac* mac, u8 addr[6])
387 int port = mac->instance->index;
389 vsc_write(mac->adapter, REG_MAC_LOW_ADDR(port),
390 (addr[3] << 16) | (addr[4] << 8) | addr[5]);
391 vsc_write(mac->adapter, REG_MAC_HIGH_ADDR(port),
392 (addr[0] << 16) | (addr[1] << 8) | addr[2]);
394 vsc_read(mac->adapter, REG_ING_FFILT_UM_EN, &val);
396 vsc_write(mac->adapter, REG_ING_FFILT_UM_EN, val | (port << 28));
398 vsc_write(mac->adapter, REG_ING_FFILT_MASK0,
399 0xffff0000 | (addr[4] << 8) | addr[5]);
400 vsc_write(mac->adapter, REG_ING_FFILT_MASK1,
401 0xffff0000 | (addr[2] << 8) | addr[3]);
402 vsc_write(mac->adapter, REG_ING_FFILT_MASK2,
403 0xffff0000 | (addr[0] << 8) | addr[1]);
407 static int mac_get_address(struct cmac *mac, u8 addr[6])
409 u32 addr_lo, addr_hi;
410 int port = mac->instance->index;
412 vsc_read(mac->adapter, REG_MAC_LOW_ADDR(port), &addr_lo);
413 vsc_read(mac->adapter, REG_MAC_HIGH_ADDR(port), &addr_hi);
415 addr[0] = (u8) (addr_hi >> 16);
416 addr[1] = (u8) (addr_hi >> 8);
417 addr[2] = (u8) addr_hi;
418 addr[3] = (u8) (addr_lo >> 16);
419 addr[4] = (u8) (addr_lo >> 8);
420 addr[5] = (u8) addr_lo;
424 /* This is intended to reset a port, not the whole MAC */
425 static int mac_reset(struct cmac *mac)
427 int index = mac->instance->index;
429 run_table(mac->adapter, vsc7326_portinit[index],
430 ARRAY_SIZE(vsc7326_portinit[index]));
435 static int mac_set_rx_mode(struct cmac *mac, struct t1_rx_mode *rm)
438 int port = mac->instance->index;
440 vsc_read(mac->adapter, REG_ING_FFILT_UM_EN, &v);
443 if (t1_rx_mode_promisc(rm))
444 v &= ~(1 << (port + 16));
446 v |= 1 << (port + 16);
448 vsc_write(mac->adapter, REG_ING_FFILT_UM_EN, v);
452 static int mac_set_mtu(struct cmac *mac, int mtu)
454 int port = mac->instance->index;
459 /* max_len includes header and FCS */
460 vsc_write(mac->adapter, REG_MAX_LEN(port), mtu + 14 + 4);
464 static int mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
468 int enable, port = mac->instance->index;
470 if (speed >= 0 && speed != SPEED_10 && speed != SPEED_100 &&
473 if (duplex > 0 && duplex != DUPLEX_FULL)
477 vsc_read(mac->adapter, REG_MODE_CFG(port), &v);
478 enable = v & 3; /* save tx/rx enables */
480 v |= 4; /* full duplex */
481 if (speed == SPEED_1000)
484 vsc_write(mac->adapter, REG_MODE_CFG(port), v);
486 if (speed == SPEED_1000)
488 else if (speed == SPEED_100)
492 vsc_write(mac->adapter, REG_DEV_SETUP(port), v | 1); /* reset */
493 vsc_write(mac->adapter, REG_DEV_SETUP(port), v);
494 vsc_read(mac->adapter, REG_DBG(port), &v);
496 if (speed == SPEED_1000)
498 else if (speed == SPEED_100)
502 vsc_write(mac->adapter, REG_DBG(port), v);
504 vsc_write(mac->adapter, REG_TX_IFG(port),
505 speed == SPEED_1000 ? 5 : 0x11);
506 if (duplex == DUPLEX_HALF)
507 enable = 0x0; /* 100 or 10 */
508 else if (speed == SPEED_1000)
510 else /* SPEED_100 or 10 */
512 enable |= 0x9 << 10; /* IFG1 */
513 enable |= 0x6 << 6; /* IFG2 */
514 enable |= 0x1 << 4; /* VLAN */
515 enable |= 0x3; /* RX/TX EN */
516 vsc_write(mac->adapter, REG_MODE_CFG(port), enable);
520 vsc_read(mac->adapter, REG_PAUSE_CFG(port), &v);
522 v |= 0x20000; /* xon/xoff */
527 if (fc == (PAUSE_RX | PAUSE_TX))
529 vsc_write(mac->adapter, REG_PAUSE_CFG(port), v);
533 static int mac_enable(struct cmac *mac, int which)
536 int port = mac->instance->index;
538 /* Write the correct WM value when the port is enabled. */
539 vsc_write(mac->adapter, REG_HIGH_LOW_WM(1,port), WM_ENABLE);
541 vsc_read(mac->adapter, REG_MODE_CFG(port), &val);
542 if (which & MAC_DIRECTION_RX)
544 if (which & MAC_DIRECTION_TX)
546 vsc_write(mac->adapter, REG_MODE_CFG(port), val);
550 static int mac_disable(struct cmac *mac, int which)
553 int i, port = mac->instance->index;
555 /* Reset the port, this also writes the correct WM value */
558 vsc_read(mac->adapter, REG_MODE_CFG(port), &val);
559 if (which & MAC_DIRECTION_RX)
561 if (which & MAC_DIRECTION_TX)
563 vsc_write(mac->adapter, REG_MODE_CFG(port), val);
564 vsc_read(mac->adapter, REG_MODE_CFG(port), &val);
567 for (i = 0; i <= 0x3a; ++i)
568 vsc_write(mac->adapter, CRA(4, port, i), 0);
570 /* Clear sofware counters */
571 memset(&mac->stats, 0, sizeof(struct cmac_statistics));
576 static void rmon_update(struct cmac *mac, unsigned int addr, u64 *stat)
580 vsc_read(mac->adapter, addr, &v);
582 *stat = *stat - lo + v;
588 *stat += (1ULL << 32);
591 static void port_stats_update(struct cmac *mac)
593 int port = mac->instance->index;
596 rmon_update(mac, REG_RX_OK_BYTES(port), &mac->stats.RxOctetsOK);
597 rmon_update(mac, REG_RX_BAD_BYTES(port), &mac->stats.RxOctetsBad);
598 rmon_update(mac, REG_RX_UNICAST(port), &mac->stats.RxUnicastFramesOK);
599 rmon_update(mac, REG_RX_MULTICAST(port),
600 &mac->stats.RxMulticastFramesOK);
601 rmon_update(mac, REG_RX_BROADCAST(port),
602 &mac->stats.RxBroadcastFramesOK);
603 rmon_update(mac, REG_CRC(port), &mac->stats.RxFCSErrors);
604 rmon_update(mac, REG_RX_ALIGNMENT(port), &mac->stats.RxAlignErrors);
605 rmon_update(mac, REG_RX_OVERSIZE(port),
606 &mac->stats.RxFrameTooLongErrors);
607 rmon_update(mac, REG_RX_PAUSE(port), &mac->stats.RxPauseFrames);
608 rmon_update(mac, REG_RX_JABBERS(port), &mac->stats.RxJabberErrors);
609 rmon_update(mac, REG_RX_FRAGMENTS(port), &mac->stats.RxRuntErrors);
610 rmon_update(mac, REG_RX_UNDERSIZE(port), &mac->stats.RxRuntErrors);
611 rmon_update(mac, REG_RX_SYMBOL_CARRIER(port),
612 &mac->stats.RxSymbolErrors);
613 rmon_update(mac, REG_RX_SIZE_1519_TO_MAX(port),
614 &mac->stats.RxJumboFramesOK);
616 /* Tx stats (skip collision stats as we are full-duplex only) */
617 rmon_update(mac, REG_TX_OK_BYTES(port), &mac->stats.TxOctetsOK);
618 rmon_update(mac, REG_TX_UNICAST(port), &mac->stats.TxUnicastFramesOK);
619 rmon_update(mac, REG_TX_MULTICAST(port),
620 &mac->stats.TxMulticastFramesOK);
621 rmon_update(mac, REG_TX_BROADCAST(port),
622 &mac->stats.TxBroadcastFramesOK);
623 rmon_update(mac, REG_TX_PAUSE(port), &mac->stats.TxPauseFrames);
624 rmon_update(mac, REG_TX_UNDERRUN(port), &mac->stats.TxUnderrun);
625 rmon_update(mac, REG_TX_SIZE_1519_TO_MAX(port),
626 &mac->stats.TxJumboFramesOK);
630 * This function is called periodically to accumulate the current values of the
631 * RMON counters into the port statistics. Since the counters are only 32 bits
632 * some of them can overflow in less than a minute at GigE speeds, so this
633 * function should be called every 30 seconds or so.
635 * To cut down on reading costs we update only the octet counters at each tick
636 * and do a full update at major ticks, which can be every 30 minutes or more.
638 static const struct cmac_statistics *mac_update_statistics(struct cmac *mac,
641 if (flag == MAC_STATS_UPDATE_FULL ||
642 mac->instance->ticks >= MAJOR_UPDATE_TICKS) {
643 port_stats_update(mac);
644 mac->instance->ticks = 0;
646 int port = mac->instance->index;
648 rmon_update(mac, REG_RX_OK_BYTES(port),
649 &mac->stats.RxOctetsOK);
650 rmon_update(mac, REG_RX_BAD_BYTES(port),
651 &mac->stats.RxOctetsBad);
652 rmon_update(mac, REG_TX_OK_BYTES(port),
653 &mac->stats.TxOctetsOK);
654 mac->instance->ticks++;
659 static void mac_destroy(struct cmac *mac)
664 static struct cmac_ops vsc7326_ops = {
665 .destroy = mac_destroy,
667 .interrupt_handler = mac_intr_handler,
668 .interrupt_enable = mac_intr_enable,
669 .interrupt_disable = mac_intr_disable,
670 .interrupt_clear = mac_intr_clear,
671 .enable = mac_enable,
672 .disable = mac_disable,
673 .set_mtu = mac_set_mtu,
674 .set_rx_mode = mac_set_rx_mode,
675 .set_speed_duplex_fc = mac_set_speed_duplex_fc,
676 .statistics_update = mac_update_statistics,
677 .macaddress_get = mac_get_address,
678 .macaddress_set = mac_set_address,
681 static struct cmac *vsc7326_mac_create(adapter_t *adapter, int index)
687 mac = kzalloc(sizeof(*mac) + sizeof(cmac_instance), GFP_KERNEL);
691 mac->ops = &vsc7326_ops;
692 mac->instance = (cmac_instance *)(mac + 1);
693 mac->adapter = adapter;
695 mac->instance->index = index;
696 mac->instance->ticks = 0;
703 t1_tpi_read(adapter, (REG_LOCAL_STATUS << 2) + 4, &vlo);
705 t1_tpi_read(adapter, REG_LOCAL_STATUS << 2, &vhi);
707 val = (vhi << 16) | vlo;
708 } while ((++i < 10000) && (val == 0xffffffff));
713 static int vsc7326_mac_reset(adapter_t *adapter)
715 vsc7326_full_reset(adapter);
716 (void) run_bist_all(adapter);
717 run_table(adapter, vsc7326_reset, ARRAY_SIZE(vsc7326_reset));
721 struct gmac t1_vsc7326_ops = {
722 .stats_update_period = STATS_TICK_SECS,
723 .create = vsc7326_mac_create,
724 .reset = vsc7326_mac_reset,