1 /* Copyright 2008 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
17 #include <linux/kernel.h>
18 #include <linux/errno.h>
19 #include <linux/pci.h>
20 #include <linux/netdevice.h>
21 #include <linux/delay.h>
22 #include <linux/ethtool.h>
23 #include <linux/mutex.h>
24 #include <linux/version.h>
26 #include "bnx2x_reg.h"
27 #include "bnx2x_fw_defs.h"
28 #include "bnx2x_hsi.h"
29 #include "bnx2x_link.h"
32 /********************************************************/
33 #define SUPPORT_CL73 0 /* Currently no */
35 #define ETH_OVREHEAD (ETH_HLEN + 8)/* 8 for CRC + VLAN*/
36 #define ETH_MIN_PACKET_SIZE 60
37 #define ETH_MAX_PACKET_SIZE 1500
38 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
39 #define MDIO_ACCESS_TIMEOUT 1000
40 #define BMAC_CONTROL_RX_ENABLE 2
42 /***********************************************************/
43 /* Shortcut definitions */
44 /***********************************************************/
46 #define NIG_STATUS_XGXS0_LINK10G \
47 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
48 #define NIG_STATUS_XGXS0_LINK_STATUS \
49 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
50 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
51 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
52 #define NIG_STATUS_SERDES0_LINK_STATUS \
53 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
54 #define NIG_MASK_MI_INT \
55 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
56 #define NIG_MASK_XGXS0_LINK10G \
57 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
58 #define NIG_MASK_XGXS0_LINK_STATUS \
59 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
60 #define NIG_MASK_SERDES0_LINK_STATUS \
61 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
63 #define MDIO_AN_CL73_OR_37_COMPLETE \
64 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
65 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
67 #define XGXS_RESET_BITS \
68 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
69 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
70 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
71 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
72 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
74 #define SERDES_RESET_BITS \
75 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
76 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
77 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
78 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
80 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
81 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
82 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
83 #define AUTONEG_PARALLEL \
84 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
85 #define AUTONEG_SGMII_FIBER_AUTODET \
86 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
87 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
89 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
90 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
91 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
92 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
93 #define GP_STATUS_SPEED_MASK \
94 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
95 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
96 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
97 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
98 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
99 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
100 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
101 #define GP_STATUS_10G_HIG \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
103 #define GP_STATUS_10G_CX4 \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
105 #define GP_STATUS_12G_HIG \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
107 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
108 #define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
109 #define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
110 #define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
111 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
112 #define GP_STATUS_10G_KX4 \
113 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
115 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
116 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
117 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
118 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
119 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
120 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
121 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
122 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
123 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
124 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
125 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
126 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
127 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
128 #define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
129 #define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
130 #define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
131 #define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
132 #define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
133 #define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
134 #define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
135 #define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
136 #define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
137 #define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
139 #define PHY_XGXS_FLAG 0x1
140 #define PHY_SGMII_FLAG 0x2
141 #define PHY_SERDES_FLAG 0x4
143 /**********************************************************/
145 /**********************************************************/
146 #define CL45_WR_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
147 bnx2x_cl45_write(_bp, _port, 0, _phy_addr, \
148 DEFAULT_PHY_DEV_ADDR, \
149 (_bank + (_addr & 0xf)), \
152 #define CL45_RD_OVER_CL22(_bp, _port, _phy_addr, _bank, _addr, _val) \
153 bnx2x_cl45_read(_bp, _port, 0, _phy_addr, \
154 DEFAULT_PHY_DEV_ADDR, \
155 (_bank + (_addr & 0xf)), \
158 static void bnx2x_set_phy_mdio(struct link_params *params)
160 struct bnx2x *bp = params->bp;
161 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST +
162 params->port*0x18, 0);
163 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
164 DEFAULT_PHY_DEV_ADDR);
167 static u32 bnx2x_bits_en(struct bnx2x *bp, u32 reg, u32 bits)
169 u32 val = REG_RD(bp, reg);
172 REG_WR(bp, reg, val);
176 static u32 bnx2x_bits_dis(struct bnx2x *bp, u32 reg, u32 bits)
178 u32 val = REG_RD(bp, reg);
181 REG_WR(bp, reg, val);
185 static void bnx2x_emac_init(struct link_params *params,
186 struct link_vars *vars)
188 /* reset and unreset the emac core */
189 struct bnx2x *bp = params->bp;
190 u8 port = params->port;
191 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
195 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
196 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
198 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
199 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
201 /* init emac - use read-modify-write */
202 /* self clear reset */
203 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
204 EMAC_WR(EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
209 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
210 DP(NETIF_MSG_LINK, "EMAC reset reg is %u\n", val);
212 DP(NETIF_MSG_LINK, "EMAC timeout!\n");
216 }while (val & EMAC_MODE_RESET);
218 /* Set mac address */
219 val = ((params->mac_addr[0] << 8) |
220 params->mac_addr[1]);
221 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH, val);
223 val = ((params->mac_addr[2] << 24) |
224 (params->mac_addr[3] << 16) |
225 (params->mac_addr[4] << 8) |
226 params->mac_addr[5]);
227 EMAC_WR(EMAC_REG_EMAC_MAC_MATCH + 4, val);
230 static u8 bnx2x_emac_enable(struct link_params *params,
231 struct link_vars *vars, u8 lb)
233 struct bnx2x *bp = params->bp;
234 u8 port = params->port;
235 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
238 DP(NETIF_MSG_LINK, "enabling EMAC\n");
240 /* enable emac and not bmac */
241 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
244 if (CHIP_REV_IS_EMUL(bp)) {
245 /* Use lane 1 (of lanes 0-3) */
246 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
247 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
253 if (CHIP_REV_IS_FPGA(bp)) {
254 /* Use lane 1 (of lanes 0-3) */
255 DP(NETIF_MSG_LINK, "bnx2x_emac_enable: Setting FPGA\n");
257 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
258 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4,
262 if (vars->phy_flags & PHY_XGXS_FLAG) {
263 u32 ser_lane = ((params->lane_config &
264 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
265 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
267 DP(NETIF_MSG_LINK, "XGXS\n");
268 /* select the master lanes (out of 0-3) */
269 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 +
272 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
275 } else { /* SerDes */
276 DP(NETIF_MSG_LINK, "SerDes\n");
278 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL +
283 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1);
285 if (CHIP_REV_IS_SLOW(bp)) {
286 /* config GMII mode */
287 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
288 EMAC_WR(EMAC_REG_EMAC_MODE,
289 (val | EMAC_MODE_PORT_GMII));
291 /* pause enable/disable */
292 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_RX_MODE,
293 EMAC_RX_MODE_FLOW_EN);
294 if (vars->flow_ctrl & FLOW_CTRL_RX)
295 bnx2x_bits_en(bp, emac_base +
296 EMAC_REG_EMAC_RX_MODE,
297 EMAC_RX_MODE_FLOW_EN);
299 bnx2x_bits_dis(bp, emac_base + EMAC_REG_EMAC_TX_MODE,
300 (EMAC_TX_MODE_EXT_PAUSE_EN |
301 EMAC_TX_MODE_FLOW_EN));
302 if (vars->flow_ctrl & FLOW_CTRL_TX)
303 bnx2x_bits_en(bp, emac_base +
304 EMAC_REG_EMAC_TX_MODE,
305 (EMAC_TX_MODE_EXT_PAUSE_EN |
306 EMAC_TX_MODE_FLOW_EN));
309 /* KEEP_VLAN_TAG, promiscuous */
310 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_RX_MODE);
311 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
312 EMAC_WR(EMAC_REG_EMAC_RX_MODE, val);
315 val = REG_RD(bp, emac_base + EMAC_REG_EMAC_MODE);
320 EMAC_WR(EMAC_REG_EMAC_MODE, val);
322 /* enable emac for jumbo packets */
323 EMAC_WR(EMAC_REG_EMAC_RX_MTU_SIZE,
324 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
325 (ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD)));
328 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
330 /* disable the NIG in/out to the bmac */
331 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
332 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
333 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
335 /* enable the NIG in/out to the emac */
336 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
338 if (vars->flow_ctrl & FLOW_CTRL_TX)
341 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
342 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
344 if (CHIP_REV_IS_EMUL(bp)) {
345 /* take the BigMac out of reset */
347 GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
348 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
350 /* enable access for bmac registers */
351 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
354 vars->mac_type = MAC_TYPE_EMAC;
360 static u8 bnx2x_bmac_enable(struct link_params *params, struct link_vars *vars,
363 struct bnx2x *bp = params->bp;
364 u8 port = params->port;
365 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
366 NIG_REG_INGRESS_BMAC0_MEM;
370 DP(NETIF_MSG_LINK, "Enabling BigMAC\n");
371 /* reset and unreset the BigMac */
372 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
373 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
376 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
377 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
379 /* enable access for bmac registers */
380 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
385 REG_WR_DMAE(bp, bmac_addr +
386 BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
390 wb_data[0] = ((params->mac_addr[2] << 24) |
391 (params->mac_addr[3] << 16) |
392 (params->mac_addr[4] << 8) |
393 params->mac_addr[5]);
394 wb_data[1] = ((params->mac_addr[0] << 8) |
395 params->mac_addr[1]);
396 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR,
401 if (vars->flow_ctrl & FLOW_CTRL_TX)
405 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_CONTROL,
412 DP(NETIF_MSG_LINK, "enable bmac loopback\n");
416 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
421 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
423 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE,
426 /* rx control set to don't strip crc */
428 if (vars->flow_ctrl & FLOW_CTRL_RX)
432 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_CONTROL,
436 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
438 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE,
441 /* set cnt max size */
442 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD;
444 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE,
448 wb_data[0] = 0x1000200;
450 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
452 /* fix for emulation */
453 if (CHIP_REV_IS_EMUL(bp)) {
457 bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
461 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
462 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
463 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
465 if (vars->flow_ctrl & FLOW_CTRL_TX)
467 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
468 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
469 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
470 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
471 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
472 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
474 vars->mac_type = MAC_TYPE_BMAC;
478 static void bnx2x_phy_deassert(struct link_params *params, u8 phy_flags)
480 struct bnx2x *bp = params->bp;
483 if (phy_flags & PHY_XGXS_FLAG) {
484 DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:XGXS\n");
485 val = XGXS_RESET_BITS;
487 } else { /* SerDes */
488 DP(NETIF_MSG_LINK, "bnx2x_phy_deassert:SerDes\n");
489 val = SERDES_RESET_BITS;
492 val = val << (params->port*16);
494 /* reset and unreset the SerDes/XGXS */
495 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
498 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET,
500 bnx2x_set_phy_mdio(params);
503 void bnx2x_link_status_update(struct link_params *params,
504 struct link_vars *vars)
506 struct bnx2x *bp = params->bp;
508 u8 port = params->port;
510 if (params->switch_cfg == SWITCH_CFG_1G)
511 vars->phy_flags = PHY_SERDES_FLAG;
513 vars->phy_flags = PHY_XGXS_FLAG;
514 vars->link_status = REG_RD(bp, params->shmem_base +
515 offsetof(struct shmem_region,
516 port_mb[port].link_status));
518 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
521 DP(NETIF_MSG_LINK, "phy link up\n");
523 vars->phy_link_up = 1;
524 vars->duplex = DUPLEX_FULL;
525 switch (vars->link_status &
526 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
528 vars->duplex = DUPLEX_HALF;
531 vars->line_speed = SPEED_10;
535 vars->duplex = DUPLEX_HALF;
539 vars->line_speed = SPEED_100;
543 vars->duplex = DUPLEX_HALF;
546 vars->line_speed = SPEED_1000;
550 vars->duplex = DUPLEX_HALF;
553 vars->line_speed = SPEED_2500;
557 vars->line_speed = SPEED_10000;
561 vars->line_speed = SPEED_12000;
565 vars->line_speed = SPEED_12500;
569 vars->line_speed = SPEED_13000;
573 vars->line_speed = SPEED_15000;
577 vars->line_speed = SPEED_16000;
584 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
585 vars->flow_ctrl |= FLOW_CTRL_TX;
587 vars->flow_ctrl &= ~FLOW_CTRL_TX;
589 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
590 vars->flow_ctrl |= FLOW_CTRL_RX;
592 vars->flow_ctrl &= ~FLOW_CTRL_RX;
594 if (vars->phy_flags & PHY_XGXS_FLAG) {
595 if (vars->line_speed &&
596 ((vars->line_speed == SPEED_10) ||
597 (vars->line_speed == SPEED_100))) {
598 vars->phy_flags |= PHY_SGMII_FLAG;
600 vars->phy_flags &= ~PHY_SGMII_FLAG;
604 /* anything 10 and over uses the bmac */
605 link_10g = ((vars->line_speed == SPEED_10000) ||
606 (vars->line_speed == SPEED_12000) ||
607 (vars->line_speed == SPEED_12500) ||
608 (vars->line_speed == SPEED_13000) ||
609 (vars->line_speed == SPEED_15000) ||
610 (vars->line_speed == SPEED_16000));
612 vars->mac_type = MAC_TYPE_BMAC;
614 vars->mac_type = MAC_TYPE_EMAC;
616 } else { /* link down */
617 DP(NETIF_MSG_LINK, "phy link down\n");
619 vars->phy_link_up = 0;
621 vars->line_speed = 0;
622 vars->duplex = DUPLEX_FULL;
623 vars->flow_ctrl = FLOW_CTRL_NONE;
625 /* indicate no mac active */
626 vars->mac_type = MAC_TYPE_NONE;
629 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x\n",
630 vars->link_status, vars->phy_link_up);
631 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n",
632 vars->line_speed, vars->duplex, vars->flow_ctrl);
635 static void bnx2x_update_mng(struct link_params *params, u32 link_status)
637 struct bnx2x *bp = params->bp;
638 REG_WR(bp, params->shmem_base +
639 offsetof(struct shmem_region,
640 port_mb[params->port].link_status),
644 static void bnx2x_bmac_rx_disable(struct bnx2x *bp, u8 port)
646 u32 bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
647 NIG_REG_INGRESS_BMAC0_MEM;
649 u32 nig_bmac_enable = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
651 /* Only if the bmac is out of reset */
652 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
653 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
656 /* Clear Rx Enable bit in BMAC_CONTROL register */
657 REG_RD_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
659 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
660 REG_WR_DMAE(bp, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL,
667 static u8 bnx2x_pbf_update(struct link_params *params, u32 flow_ctrl,
670 struct bnx2x *bp = params->bp;
671 u8 port = params->port;
676 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
678 /* wait for init credit */
679 init_crd = REG_RD(bp, PBF_REG_P0_INIT_CRD + port*4);
680 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
681 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
683 while ((init_crd != crd) && count) {
686 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
689 crd = REG_RD(bp, PBF_REG_P0_CREDIT + port*8);
690 if (init_crd != crd) {
691 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n",
696 if (flow_ctrl & FLOW_CTRL_RX ||
697 line_speed == SPEED_10 ||
698 line_speed == SPEED_100 ||
699 line_speed == SPEED_1000 ||
700 line_speed == SPEED_2500) {
701 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
702 /* update threshold */
703 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0);
704 /* update init credit */
705 init_crd = 778; /* (800-18-4) */
708 u32 thresh = (ETH_MAX_JUMBO_PACKET_SIZE +
710 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
711 /* update threshold */
712 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh);
713 /* update init credit */
714 switch (line_speed) {
716 init_crd = thresh + 553 - 22;
720 init_crd = thresh + 664 - 22;
724 init_crd = thresh + 742 - 22;
728 init_crd = thresh + 778 - 22;
731 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
737 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd);
738 DP(NETIF_MSG_LINK, "PBF updated to speed %d credit %d\n",
739 line_speed, init_crd);
741 /* probe the credit changes */
742 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1);
744 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0);
747 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
751 static u32 bnx2x_get_emac_base(u32 ext_phy_type, u8 port)
754 switch (ext_phy_type) {
755 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
756 emac_base = GRCBASE_EMAC0;
758 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
759 emac_base = (port) ? GRCBASE_EMAC0: GRCBASE_EMAC1;
762 emac_base = (port) ? GRCBASE_EMAC1: GRCBASE_EMAC0;
769 u8 bnx2x_cl45_write(struct bnx2x *bp, u8 port, u32 ext_phy_type,
770 u8 phy_addr, u8 devad, u16 reg, u16 val)
774 u32 mdio_ctrl = bnx2x_get_emac_base(ext_phy_type, port);
776 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
777 * (a value of 49==0x31) and make sure that the AUTO poll is off
779 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
780 tmp = saved_mode & ~(EMAC_MDIO_MODE_AUTO_POLL |
781 EMAC_MDIO_MODE_CLOCK_CNT);
782 tmp |= (EMAC_MDIO_MODE_CLAUSE_45 |
783 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
784 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, tmp);
785 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
790 tmp = ((phy_addr << 21) | (devad << 16) | reg |
791 EMAC_MDIO_COMM_COMMAND_ADDRESS |
792 EMAC_MDIO_COMM_START_BUSY);
793 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
795 for (i = 0; i < 50; i++) {
798 tmp = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
799 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
804 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
805 DP(NETIF_MSG_LINK, "write phy register failed\n");
809 tmp = ((phy_addr << 21) | (devad << 16) | val |
810 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
811 EMAC_MDIO_COMM_START_BUSY);
812 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
814 for (i = 0; i < 50; i++) {
817 tmp = REG_RD(bp, mdio_ctrl +
818 EMAC_REG_EMAC_MDIO_COMM);
819 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
824 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
825 DP(NETIF_MSG_LINK, "write phy register failed\n");
830 /* Restore the saved mode */
831 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
836 u8 bnx2x_cl45_read(struct bnx2x *bp, u8 port, u32 ext_phy_type,
837 u8 phy_addr, u8 devad, u16 reg, u16 *ret_val)
843 u32 mdio_ctrl = bnx2x_get_emac_base(ext_phy_type, port);
844 /* set clause 45 mode, slow down the MDIO clock to 2.5MHz
845 * (a value of 49==0x31) and make sure that the AUTO poll is off
847 saved_mode = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
848 val = saved_mode & ((EMAC_MDIO_MODE_AUTO_POLL |
849 EMAC_MDIO_MODE_CLOCK_CNT));
850 val |= (EMAC_MDIO_MODE_CLAUSE_45 |
851 (49 << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT));
852 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, val);
853 REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
857 val = ((phy_addr << 21) | (devad << 16) | reg |
858 EMAC_MDIO_COMM_COMMAND_ADDRESS |
859 EMAC_MDIO_COMM_START_BUSY);
860 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
862 for (i = 0; i < 50; i++) {
865 val = REG_RD(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
866 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
871 if (val & EMAC_MDIO_COMM_START_BUSY) {
872 DP(NETIF_MSG_LINK, "read phy register failed\n");
879 val = ((phy_addr << 21) | (devad << 16) |
880 EMAC_MDIO_COMM_COMMAND_READ_45 |
881 EMAC_MDIO_COMM_START_BUSY);
882 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
884 for (i = 0; i < 50; i++) {
887 val = REG_RD(bp, mdio_ctrl +
888 EMAC_REG_EMAC_MDIO_COMM);
889 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
890 *ret_val = (u16)(val & EMAC_MDIO_COMM_DATA);
894 if (val & EMAC_MDIO_COMM_START_BUSY) {
895 DP(NETIF_MSG_LINK, "read phy register failed\n");
902 /* Restore the saved mode */
903 REG_WR(bp, mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, saved_mode);
908 static void bnx2x_set_aer_mmd(struct link_params *params,
909 struct link_vars *vars)
911 struct bnx2x *bp = params->bp;
915 ser_lane = ((params->lane_config &
916 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
917 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
919 offset = (vars->phy_flags & PHY_XGXS_FLAG) ?
920 (params->phy_addr + ser_lane) : 0;
922 CL45_WR_OVER_CL22(bp, params->port,
924 MDIO_REG_BANK_AER_BLOCK,
925 MDIO_AER_BLOCK_AER_REG, 0x3800 + offset);
928 static void bnx2x_set_master_ln(struct link_params *params)
930 struct bnx2x *bp = params->bp;
931 u16 new_master_ln, ser_lane;
932 ser_lane = ((params->lane_config &
933 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
934 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
936 /* set the master_ln for AN */
937 CL45_RD_OVER_CL22(bp, params->port,
939 MDIO_REG_BANK_XGXS_BLOCK2,
940 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
943 CL45_WR_OVER_CL22(bp, params->port,
945 MDIO_REG_BANK_XGXS_BLOCK2 ,
946 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
947 (new_master_ln | ser_lane));
950 static u8 bnx2x_reset_unicore(struct link_params *params)
952 struct bnx2x *bp = params->bp;
956 CL45_RD_OVER_CL22(bp, params->port,
958 MDIO_REG_BANK_COMBO_IEEE0,
959 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
961 /* reset the unicore */
962 CL45_WR_OVER_CL22(bp, params->port,
964 MDIO_REG_BANK_COMBO_IEEE0,
965 MDIO_COMBO_IEEE0_MII_CONTROL,
967 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
969 /* wait for the reset to self clear */
970 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) {
973 /* the reset erased the previous bank value */
974 CL45_RD_OVER_CL22(bp, params->port,
976 MDIO_REG_BANK_COMBO_IEEE0,
977 MDIO_COMBO_IEEE0_MII_CONTROL,
980 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
986 DP(NETIF_MSG_LINK, "BUG! XGXS is still in reset!\n");
991 static void bnx2x_set_swap_lanes(struct link_params *params)
993 struct bnx2x *bp = params->bp;
994 /* Each two bits represents a lane number:
995 No swap is 0123 => 0x1b no need to enable the swap */
996 u16 ser_lane, rx_lane_swap, tx_lane_swap;
998 ser_lane = ((params->lane_config &
999 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
1000 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
1001 rx_lane_swap = ((params->lane_config &
1002 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
1003 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
1004 tx_lane_swap = ((params->lane_config &
1005 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
1006 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
1008 if (rx_lane_swap != 0x1b) {
1009 CL45_WR_OVER_CL22(bp, params->port,
1011 MDIO_REG_BANK_XGXS_BLOCK2,
1012 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
1014 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
1015 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
1017 CL45_WR_OVER_CL22(bp, params->port,
1019 MDIO_REG_BANK_XGXS_BLOCK2,
1020 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
1023 if (tx_lane_swap != 0x1b) {
1024 CL45_WR_OVER_CL22(bp, params->port,
1026 MDIO_REG_BANK_XGXS_BLOCK2,
1027 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
1029 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
1031 CL45_WR_OVER_CL22(bp, params->port,
1033 MDIO_REG_BANK_XGXS_BLOCK2,
1034 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
1038 static void bnx2x_set_parallel_detection(struct link_params *params,
1041 struct bnx2x *bp = params->bp;
1044 CL45_RD_OVER_CL22(bp, params->port,
1046 MDIO_REG_BANK_SERDES_DIGITAL,
1047 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1051 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
1054 CL45_WR_OVER_CL22(bp, params->port,
1056 MDIO_REG_BANK_SERDES_DIGITAL,
1057 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
1060 if (phy_flags & PHY_XGXS_FLAG) {
1061 DP(NETIF_MSG_LINK, "XGXS\n");
1063 CL45_WR_OVER_CL22(bp, params->port,
1065 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1066 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
1067 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
1069 CL45_RD_OVER_CL22(bp, params->port,
1071 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1072 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1077 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
1079 CL45_WR_OVER_CL22(bp, params->port,
1081 MDIO_REG_BANK_10G_PARALLEL_DETECT,
1082 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
1085 /* Disable parallel detection of HiG */
1086 CL45_WR_OVER_CL22(bp, params->port,
1088 MDIO_REG_BANK_XGXS_BLOCK2,
1089 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
1090 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
1091 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
1095 static void bnx2x_set_autoneg(struct link_params *params,
1096 struct link_vars *vars)
1098 struct bnx2x *bp = params->bp;
1103 CL45_RD_OVER_CL22(bp, params->port,
1105 MDIO_REG_BANK_COMBO_IEEE0,
1106 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
1108 /* CL37 Autoneg Enabled */
1109 if (vars->line_speed == SPEED_AUTO_NEG)
1110 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
1111 else /* CL37 Autoneg Disabled */
1112 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1113 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
1115 CL45_WR_OVER_CL22(bp, params->port,
1117 MDIO_REG_BANK_COMBO_IEEE0,
1118 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1120 /* Enable/Disable Autodetection */
1122 CL45_RD_OVER_CL22(bp, params->port,
1124 MDIO_REG_BANK_SERDES_DIGITAL,
1125 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
1126 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN;
1127 if (vars->line_speed == SPEED_AUTO_NEG)
1128 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1130 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
1132 CL45_WR_OVER_CL22(bp, params->port,
1134 MDIO_REG_BANK_SERDES_DIGITAL,
1135 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
1137 /* Enable TetonII and BAM autoneg */
1138 CL45_RD_OVER_CL22(bp, params->port,
1140 MDIO_REG_BANK_BAM_NEXT_PAGE,
1141 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1143 if (vars->line_speed == SPEED_AUTO_NEG) {
1144 /* Enable BAM aneg Mode and TetonII aneg Mode */
1145 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1146 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1148 /* TetonII and BAM Autoneg Disabled */
1149 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
1150 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
1152 CL45_WR_OVER_CL22(bp, params->port,
1154 MDIO_REG_BANK_BAM_NEXT_PAGE,
1155 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
1158 /* Enable Clause 73 Aneg */
1159 if ((vars->line_speed == SPEED_AUTO_NEG) &&
1161 /* Enable BAM Station Manager */
1163 CL45_WR_OVER_CL22(bp, params->port,
1165 MDIO_REG_BANK_CL73_USERB0,
1166 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
1167 (MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
1168 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
1169 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN));
1171 /* Merge CL73 and CL37 aneg resolution */
1172 CL45_RD_OVER_CL22(bp, params->port,
1174 MDIO_REG_BANK_CL73_USERB0,
1175 MDIO_CL73_USERB0_CL73_BAM_CTRL3,
1178 CL45_WR_OVER_CL22(bp, params->port,
1180 MDIO_REG_BANK_CL73_USERB0,
1181 MDIO_CL73_USERB0_CL73_BAM_CTRL3,
1183 MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR));
1185 /* Set the CL73 AN speed */
1187 CL45_RD_OVER_CL22(bp, params->port,
1189 MDIO_REG_BANK_CL73_IEEEB1,
1190 MDIO_CL73_IEEEB1_AN_ADV2, ®_val);
1191 /* In the SerDes we support only the 1G.
1192 In the XGXS we support the 10G KX4
1193 but we currently do not support the KR */
1194 if (vars->phy_flags & PHY_XGXS_FLAG) {
1195 DP(NETIF_MSG_LINK, "XGXS\n");
1197 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
1199 DP(NETIF_MSG_LINK, "SerDes\n");
1201 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
1203 CL45_WR_OVER_CL22(bp, params->port,
1205 MDIO_REG_BANK_CL73_IEEEB1,
1206 MDIO_CL73_IEEEB1_AN_ADV2, reg_val);
1208 /* CL73 Autoneg Enabled */
1209 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
1211 /* CL73 Autoneg Disabled */
1214 CL45_WR_OVER_CL22(bp, params->port,
1216 MDIO_REG_BANK_CL73_IEEEB0,
1217 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
1220 /* program SerDes, forced speed */
1221 static void bnx2x_program_serdes(struct link_params *params,
1222 struct link_vars *vars)
1224 struct bnx2x *bp = params->bp;
1227 /* program duplex, disable autoneg */
1229 CL45_RD_OVER_CL22(bp, params->port,
1231 MDIO_REG_BANK_COMBO_IEEE0,
1232 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
1233 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
1234 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN);
1235 if (params->req_duplex == DUPLEX_FULL)
1236 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1237 CL45_WR_OVER_CL22(bp, params->port,
1239 MDIO_REG_BANK_COMBO_IEEE0,
1240 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
1243 - needed only if the speed is greater than 1G (2.5G or 10G) */
1244 CL45_RD_OVER_CL22(bp, params->port,
1246 MDIO_REG_BANK_SERDES_DIGITAL,
1247 MDIO_SERDES_DIGITAL_MISC1, ®_val);
1248 /* clearing the speed value before setting the right speed */
1249 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
1251 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
1252 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1254 if (!((vars->line_speed == SPEED_1000) ||
1255 (vars->line_speed == SPEED_100) ||
1256 (vars->line_speed == SPEED_10))) {
1258 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
1259 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
1260 if (vars->line_speed == SPEED_10000)
1262 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
1263 if (vars->line_speed == SPEED_13000)
1265 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G;
1268 CL45_WR_OVER_CL22(bp, params->port,
1270 MDIO_REG_BANK_SERDES_DIGITAL,
1271 MDIO_SERDES_DIGITAL_MISC1, reg_val);
1275 static void bnx2x_set_brcm_cl37_advertisment(struct link_params *params)
1277 struct bnx2x *bp = params->bp;
1280 /* configure the 48 bits for BAM AN */
1282 /* set extended capabilities */
1283 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
1284 val |= MDIO_OVER_1G_UP1_2_5G;
1285 if (params->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
1286 val |= MDIO_OVER_1G_UP1_10G;
1287 CL45_WR_OVER_CL22(bp, params->port,
1289 MDIO_REG_BANK_OVER_1G,
1290 MDIO_OVER_1G_UP1, val);
1292 CL45_WR_OVER_CL22(bp, params->port,
1294 MDIO_REG_BANK_OVER_1G,
1295 MDIO_OVER_1G_UP3, 0);
1298 static void bnx2x_calc_ieee_aneg_adv(struct link_params *params, u32 *ieee_fc)
1300 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
1301 /* resolve pause mode and advertisement
1302 * Please refer to Table 28B-3 of the 802.3ab-1999 spec */
1304 switch (params->req_flow_ctrl) {
1305 case FLOW_CTRL_AUTO:
1306 if (params->req_fc_auto_adv == FLOW_CTRL_BOTH) {
1308 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1311 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1316 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
1320 case FLOW_CTRL_BOTH:
1321 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
1324 case FLOW_CTRL_NONE:
1326 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
1331 static void bnx2x_set_ieee_aneg_advertisment(struct link_params *params,
1334 struct bnx2x *bp = params->bp;
1335 /* for AN, we are always publishing full duplex */
1337 CL45_WR_OVER_CL22(bp, params->port,
1339 MDIO_REG_BANK_COMBO_IEEE0,
1340 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, (u16)ieee_fc);
1343 static void bnx2x_restart_autoneg(struct link_params *params)
1345 struct bnx2x *bp = params->bp;
1346 DP(NETIF_MSG_LINK, "bnx2x_restart_autoneg\n");
1348 /* enable and restart clause 73 aneg */
1351 CL45_RD_OVER_CL22(bp, params->port,
1353 MDIO_REG_BANK_CL73_IEEEB0,
1354 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1356 CL45_WR_OVER_CL22(bp, params->port,
1358 MDIO_REG_BANK_CL73_IEEEB0,
1359 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
1361 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
1362 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
1365 /* Enable and restart BAM/CL37 aneg */
1368 CL45_RD_OVER_CL22(bp, params->port,
1370 MDIO_REG_BANK_COMBO_IEEE0,
1371 MDIO_COMBO_IEEE0_MII_CONTROL,
1374 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
1376 CL45_WR_OVER_CL22(bp, params->port,
1378 MDIO_REG_BANK_COMBO_IEEE0,
1379 MDIO_COMBO_IEEE0_MII_CONTROL,
1381 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1382 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
1386 static void bnx2x_initialize_sgmii_process(struct link_params *params,
1387 struct link_vars *vars)
1389 struct bnx2x *bp = params->bp;
1392 /* in SGMII mode, the unicore is always slave */
1394 CL45_RD_OVER_CL22(bp, params->port,
1396 MDIO_REG_BANK_SERDES_DIGITAL,
1397 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1399 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
1400 /* set sgmii mode (and not fiber) */
1401 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
1402 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
1403 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
1404 CL45_WR_OVER_CL22(bp, params->port,
1406 MDIO_REG_BANK_SERDES_DIGITAL,
1407 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
1410 /* if forced speed */
1411 if (!(vars->line_speed == SPEED_AUTO_NEG)) {
1412 /* set speed, disable autoneg */
1415 CL45_RD_OVER_CL22(bp, params->port,
1417 MDIO_REG_BANK_COMBO_IEEE0,
1418 MDIO_COMBO_IEEE0_MII_CONTROL,
1420 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
1421 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
1422 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
1424 switch (vars->line_speed) {
1427 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
1431 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
1434 /* there is nothing to set for 10M */
1437 /* invalid speed for SGMII */
1438 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n",
1443 /* setting the full duplex */
1444 if (params->req_duplex == DUPLEX_FULL)
1446 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
1447 CL45_WR_OVER_CL22(bp, params->port,
1449 MDIO_REG_BANK_COMBO_IEEE0,
1450 MDIO_COMBO_IEEE0_MII_CONTROL,
1453 } else { /* AN mode */
1454 /* enable and restart AN */
1455 bnx2x_restart_autoneg(params);
1464 static void bnx2x_pause_resolve(struct link_vars *vars, u32 pause_result)
1466 switch (pause_result) { /* ASYM P ASYM P */
1467 case 0xb: /* 1 0 1 1 */
1468 vars->flow_ctrl = FLOW_CTRL_TX;
1471 case 0xe: /* 1 1 1 0 */
1472 vars->flow_ctrl = FLOW_CTRL_RX;
1475 case 0x5: /* 0 1 0 1 */
1476 case 0x7: /* 0 1 1 1 */
1477 case 0xd: /* 1 1 0 1 */
1478 case 0xf: /* 1 1 1 1 */
1479 vars->flow_ctrl = FLOW_CTRL_BOTH;
1487 static u8 bnx2x_ext_phy_resove_fc(struct link_params *params,
1488 struct link_vars *vars)
1490 struct bnx2x *bp = params->bp;
1492 u16 ld_pause; /* local */
1493 u16 lp_pause; /* link partner */
1494 u16 an_complete; /* AN complete */
1498 u8 port = params->port;
1499 ext_phy_addr = ((params->ext_phy_config &
1500 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1501 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1503 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
1506 bnx2x_cl45_read(bp, port,
1510 MDIO_AN_REG_STATUS, &an_complete);
1511 bnx2x_cl45_read(bp, port,
1515 MDIO_AN_REG_STATUS, &an_complete);
1517 if (an_complete & MDIO_AN_REG_STATUS_AN_COMPLETE) {
1519 bnx2x_cl45_read(bp, port,
1523 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
1524 bnx2x_cl45_read(bp, port,
1528 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
1529 pause_result = (ld_pause &
1530 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
1531 pause_result |= (lp_pause &
1532 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
1533 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x \n",
1535 bnx2x_pause_resolve(vars, pause_result);
1536 if (vars->flow_ctrl == FLOW_CTRL_NONE &&
1537 ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
1538 bnx2x_cl45_read(bp, port,
1542 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
1544 bnx2x_cl45_read(bp, port,
1548 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
1549 pause_result = (ld_pause &
1550 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
1551 pause_result |= (lp_pause &
1552 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
1554 bnx2x_pause_resolve(vars, pause_result);
1555 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x \n",
1563 static void bnx2x_flow_ctrl_resolve(struct link_params *params,
1564 struct link_vars *vars,
1567 struct bnx2x *bp = params->bp;
1568 u16 ld_pause; /* local driver */
1569 u16 lp_pause; /* link partner */
1572 vars->flow_ctrl = FLOW_CTRL_NONE;
1574 /* resolve from gp_status in case of AN complete and not sgmii */
1575 if ((params->req_flow_ctrl == FLOW_CTRL_AUTO) &&
1576 (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) &&
1577 (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
1578 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1579 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)) {
1580 CL45_RD_OVER_CL22(bp, params->port,
1582 MDIO_REG_BANK_COMBO_IEEE0,
1583 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
1585 CL45_RD_OVER_CL22(bp, params->port,
1587 MDIO_REG_BANK_COMBO_IEEE0,
1588 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
1590 pause_result = (ld_pause &
1591 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
1592 pause_result |= (lp_pause &
1593 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
1594 DP(NETIF_MSG_LINK, "pause_result 0x%x\n", pause_result);
1595 bnx2x_pause_resolve(vars, pause_result);
1596 } else if ((params->req_flow_ctrl == FLOW_CTRL_AUTO) &&
1597 (bnx2x_ext_phy_resove_fc(params, vars))) {
1600 if (params->req_flow_ctrl == FLOW_CTRL_AUTO)
1601 vars->flow_ctrl = params->req_fc_auto_adv;
1603 vars->flow_ctrl = params->req_flow_ctrl;
1605 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl);
1609 static u8 bnx2x_link_settings_status(struct link_params *params,
1610 struct link_vars *vars,
1613 struct bnx2x *bp = params->bp;
1615 vars->link_status = 0;
1617 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
1618 DP(NETIF_MSG_LINK, "phy link up gp_status=0x%x\n",
1621 vars->phy_link_up = 1;
1622 vars->link_status |= LINK_STATUS_LINK_UP;
1624 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
1625 vars->duplex = DUPLEX_FULL;
1627 vars->duplex = DUPLEX_HALF;
1629 bnx2x_flow_ctrl_resolve(params, vars, gp_status);
1631 switch (gp_status & GP_STATUS_SPEED_MASK) {
1633 vars->line_speed = SPEED_10;
1634 if (vars->duplex == DUPLEX_FULL)
1635 vars->link_status |= LINK_10TFD;
1637 vars->link_status |= LINK_10THD;
1640 case GP_STATUS_100M:
1641 vars->line_speed = SPEED_100;
1642 if (vars->duplex == DUPLEX_FULL)
1643 vars->link_status |= LINK_100TXFD;
1645 vars->link_status |= LINK_100TXHD;
1649 case GP_STATUS_1G_KX:
1650 vars->line_speed = SPEED_1000;
1651 if (vars->duplex == DUPLEX_FULL)
1652 vars->link_status |= LINK_1000TFD;
1654 vars->link_status |= LINK_1000THD;
1657 case GP_STATUS_2_5G:
1658 vars->line_speed = SPEED_2500;
1659 if (vars->duplex == DUPLEX_FULL)
1660 vars->link_status |= LINK_2500TFD;
1662 vars->link_status |= LINK_2500THD;
1668 "link speed unsupported gp_status 0x%x\n",
1672 case GP_STATUS_10G_KX4:
1673 case GP_STATUS_10G_HIG:
1674 case GP_STATUS_10G_CX4:
1675 vars->line_speed = SPEED_10000;
1676 vars->link_status |= LINK_10GTFD;
1679 case GP_STATUS_12G_HIG:
1680 vars->line_speed = SPEED_12000;
1681 vars->link_status |= LINK_12GTFD;
1684 case GP_STATUS_12_5G:
1685 vars->line_speed = SPEED_12500;
1686 vars->link_status |= LINK_12_5GTFD;
1690 vars->line_speed = SPEED_13000;
1691 vars->link_status |= LINK_13GTFD;
1695 vars->line_speed = SPEED_15000;
1696 vars->link_status |= LINK_15GTFD;
1700 vars->line_speed = SPEED_16000;
1701 vars->link_status |= LINK_16GTFD;
1706 "link speed unsupported gp_status 0x%x\n",
1712 vars->link_status |= LINK_STATUS_SERDES_LINK;
1714 if ((params->req_line_speed == SPEED_AUTO_NEG) &&
1715 ((XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1716 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
1717 (XGXS_EXT_PHY_TYPE(params->ext_phy_config) ==
1718 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705))) {
1719 vars->autoneg = AUTO_NEG_ENABLED;
1721 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
1722 vars->autoneg |= AUTO_NEG_COMPLETE;
1723 vars->link_status |=
1724 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
1727 vars->autoneg |= AUTO_NEG_PARALLEL_DETECTION_USED;
1728 vars->link_status |=
1729 LINK_STATUS_PARALLEL_DETECTION_USED;
1732 if (vars->flow_ctrl & FLOW_CTRL_TX)
1733 vars->link_status |=
1734 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
1736 if (vars->flow_ctrl & FLOW_CTRL_RX)
1737 vars->link_status |=
1738 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
1740 } else { /* link_down */
1741 DP(NETIF_MSG_LINK, "phy link down\n");
1743 vars->phy_link_up = 0;
1745 vars->duplex = DUPLEX_FULL;
1746 vars->flow_ctrl = FLOW_CTRL_NONE;
1747 vars->autoneg = AUTO_NEG_DISABLED;
1748 vars->mac_type = MAC_TYPE_NONE;
1751 DP(NETIF_MSG_LINK, "gp_status 0x%x phy_link_up %x line_speed %x \n",
1752 gp_status, vars->phy_link_up, vars->line_speed);
1753 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x"
1756 vars->flow_ctrl, vars->autoneg);
1757 DP(NETIF_MSG_LINK, "link_status 0x%x\n", vars->link_status);
1762 static void bnx2x_set_sgmii_tx_driver(struct link_params *params)
1764 struct bnx2x *bp = params->bp;
1770 CL45_RD_OVER_CL22(bp, params->port,
1772 MDIO_REG_BANK_OVER_1G,
1773 MDIO_OVER_1G_LP_UP2, &lp_up2);
1775 CL45_RD_OVER_CL22(bp, params->port,
1778 MDIO_TX0_TX_DRIVER, &tx_driver);
1780 /* bits [10:7] at lp_up2, positioned at [15:12] */
1781 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
1782 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
1783 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
1785 if ((lp_up2 != 0) &&
1786 (lp_up2 != (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK))) {
1787 /* replace tx_driver bits [15:12] */
1788 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
1789 tx_driver |= lp_up2;
1790 CL45_WR_OVER_CL22(bp, params->port,
1793 MDIO_TX0_TX_DRIVER, tx_driver);
1797 static u8 bnx2x_emac_program(struct link_params *params,
1798 u32 line_speed, u32 duplex)
1800 struct bnx2x *bp = params->bp;
1801 u8 port = params->port;
1804 DP(NETIF_MSG_LINK, "setting link speed & duplex\n");
1805 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 +
1807 (EMAC_MODE_25G_MODE |
1808 EMAC_MODE_PORT_MII_10M |
1809 EMAC_MODE_HALF_DUPLEX));
1810 switch (line_speed) {
1812 mode |= EMAC_MODE_PORT_MII_10M;
1816 mode |= EMAC_MODE_PORT_MII;
1820 mode |= EMAC_MODE_PORT_GMII;
1824 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
1828 /* 10G not valid for EMAC */
1829 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", line_speed);
1833 if (duplex == DUPLEX_HALF)
1834 mode |= EMAC_MODE_HALF_DUPLEX;
1836 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
1839 bnx2x_set_led(bp, params->port, LED_MODE_OPER,
1840 line_speed, params->hw_led_mode, params->chip_id);
1844 /*****************************************************************************/
1845 /* External Phy section */
1846 /*****************************************************************************/
1847 static void bnx2x_hw_reset(struct bnx2x *bp)
1849 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1850 MISC_REGISTERS_GPIO_OUTPUT_LOW);
1852 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1853 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
1856 static void bnx2x_ext_phy_reset(struct link_params *params,
1857 struct link_vars *vars)
1859 struct bnx2x *bp = params->bp;
1861 u8 ext_phy_addr = ((params->ext_phy_config &
1862 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1863 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1864 DP(NETIF_MSG_LINK, "Port %x: bnx2x_ext_phy_reset\n", params->port);
1865 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
1866 /* The PHY reset is controled by GPIO 1
1867 * Give it 1ms of reset pulse
1869 if (vars->phy_flags & PHY_XGXS_FLAG) {
1871 switch (ext_phy_type) {
1872 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
1873 DP(NETIF_MSG_LINK, "XGXS Direct\n");
1876 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
1877 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
1878 DP(NETIF_MSG_LINK, "XGXS 8705/8706\n");
1880 /* Restore normal power mode*/
1881 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1882 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
1887 bnx2x_cl45_write(bp, params->port,
1891 MDIO_PMA_REG_CTRL, 0xa040);
1893 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
1894 /* Unset Low Power Mode and SW reset */
1895 /* Restore normal power mode*/
1896 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1897 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
1899 DP(NETIF_MSG_LINK, "XGXS 8072\n");
1900 bnx2x_cl45_write(bp, params->port,
1907 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
1910 emac_base = (params->port) ? GRCBASE_EMAC0 :
1913 /* Restore normal power mode*/
1914 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1915 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
1917 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
1918 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
1920 DP(NETIF_MSG_LINK, "XGXS 8073\n");
1921 bnx2x_cl45_write(bp,
1931 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
1932 DP(NETIF_MSG_LINK, "XGXS SFX7101\n");
1934 /* Restore normal power mode*/
1935 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
1936 MISC_REGISTERS_GPIO_OUTPUT_HIGH);
1943 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
1944 DP(NETIF_MSG_LINK, "XGXS PHY Failure detected\n");
1948 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
1949 params->ext_phy_config);
1953 } else { /* SerDes */
1954 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
1955 switch (ext_phy_type) {
1956 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
1957 DP(NETIF_MSG_LINK, "SerDes Direct\n");
1960 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
1961 DP(NETIF_MSG_LINK, "SerDes 5482\n");
1967 "BAD SerDes ext_phy_config 0x%x\n",
1968 params->ext_phy_config);
1974 static void bnx2x_bcm8072_external_rom_boot(struct link_params *params)
1976 struct bnx2x *bp = params->bp;
1977 u8 port = params->port;
1978 u8 ext_phy_addr = ((params->ext_phy_config &
1979 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
1980 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
1981 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
1982 u16 fw_ver1, fw_ver2;
1984 /* Need to wait 200ms after reset */
1986 /* Boot port from external ROM
1987 * Set ser_boot_ctl bit in the MISC_CTRL1 register
1989 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
1991 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
1993 /* Reset internal microprocessor */
1994 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
1996 MDIO_PMA_REG_GEN_CTRL,
1997 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
1998 /* set micro reset = 0 */
1999 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2001 MDIO_PMA_REG_GEN_CTRL,
2002 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2003 /* Reset internal microprocessor */
2004 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2006 MDIO_PMA_REG_GEN_CTRL,
2007 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2008 /* wait for 100ms for code download via SPI port */
2011 /* Clear ser_boot_ctl bit */
2012 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2014 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2018 /* Print the PHY FW version */
2019 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
2021 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
2022 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
2024 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
2025 DP(NETIF_MSG_LINK, "8072 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2);
2028 static u8 bnx2x_8073_is_snr_needed(struct link_params *params)
2030 /* This is only required for 8073A1, version 102 only */
2032 struct bnx2x *bp = params->bp;
2033 u8 ext_phy_addr = ((params->ext_phy_config &
2034 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2035 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2038 /* Read 8073 HW revision*/
2039 bnx2x_cl45_read(bp, params->port,
2040 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2046 /* No need to workaround in 8073 A1 */
2050 bnx2x_cl45_read(bp, params->port,
2051 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2054 MDIO_PMA_REG_ROM_VER2, &val);
2056 /* SNR should be applied only for version 0x102 */
2063 static u8 bnx2x_bcm8073_xaui_wa(struct link_params *params)
2065 struct bnx2x *bp = params->bp;
2066 u8 ext_phy_addr = ((params->ext_phy_config &
2067 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2068 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2069 u16 val, cnt, cnt1 ;
2071 bnx2x_cl45_read(bp, params->port,
2072 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2078 /* No need to workaround in 8073 A1 */
2081 /* XAUI workaround in 8073 A0: */
2083 /* After loading the boot ROM and restarting Autoneg,
2084 poll Dev1, Reg $C820: */
2086 for (cnt = 0; cnt < 1000; cnt++) {
2087 bnx2x_cl45_read(bp, params->port,
2088 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2092 /* If bit [14] = 0 or bit [13] = 0, continue on with
2093 system initialization (XAUI work-around not required,
2094 as these bits indicate 2.5G or 1G link up). */
2095 if (!(val & (1<<14)) || !(val & (1<<13))) {
2096 DP(NETIF_MSG_LINK, "XAUI work-around not required\n");
2098 } else if (!(val & (1<<15))) {
2099 DP(NETIF_MSG_LINK, "clc bit 15 went off\n");
2100 /* If bit 15 is 0, then poll Dev1, Reg $C841 until
2101 it's MSB (bit 15) goes to 1 (indicating that the
2102 XAUI workaround has completed),
2103 then continue on with system initialization.*/
2104 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
2105 bnx2x_cl45_read(bp, params->port,
2106 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2110 if (val & (1<<15)) {
2112 "XAUI workaround has completed\n");
2121 DP(NETIF_MSG_LINK, "Warning: XAUI work-around timeout !!!\n");
2126 static void bnx2x_bcm8073_external_rom_boot(struct link_params *params)
2128 struct bnx2x *bp = params->bp;
2129 u8 port = params->port;
2130 u8 ext_phy_addr = ((params->ext_phy_config &
2131 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2132 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2133 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2134 u16 fw_ver1, fw_ver2, val;
2135 /* Need to wait 100ms after reset */
2137 /* Boot port from external ROM */
2139 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2141 MDIO_PMA_REG_GEN_CTRL,
2144 /* ucode reboot and rst */
2145 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2147 MDIO_PMA_REG_GEN_CTRL,
2150 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2152 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
2154 /* Reset internal microprocessor */
2155 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2157 MDIO_PMA_REG_GEN_CTRL,
2158 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
2160 /* Release srst bit */
2161 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2163 MDIO_PMA_REG_GEN_CTRL,
2164 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
2166 /* wait for 100ms for code download via SPI port */
2169 /* Clear ser_boot_ctl bit */
2170 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2172 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
2174 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
2176 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
2177 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
2179 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
2180 DP(NETIF_MSG_LINK, "8073 FW version 0x%x:0x%x\n", fw_ver1, fw_ver2);
2182 /* Only set bit 10 = 1 (Tx power down) */
2183 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
2185 MDIO_PMA_REG_TX_POWER_DOWN, &val);
2187 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2189 MDIO_PMA_REG_TX_POWER_DOWN, (val | 1<<10));
2192 /* Release bit 10 (Release Tx power down) */
2193 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2195 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
2199 static void bnx2x_bcm8073_set_xaui_low_power_mode(struct link_params *params)
2201 struct bnx2x *bp = params->bp;
2202 u8 port = params->port;
2204 u8 ext_phy_addr = ((params->ext_phy_config &
2205 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2206 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2207 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2209 bnx2x_cl45_read(bp, params->port,
2210 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2216 /* Mustn't set low power mode in 8073 A0 */
2220 /* Disable PLL sequencer (use read-modify-write to clear bit 13) */
2221 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
2223 MDIO_XS_PLL_SEQUENCER, &val);
2225 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2226 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
2229 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2230 MDIO_XS_DEVAD, 0x805E, 0x1077);
2231 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2232 MDIO_XS_DEVAD, 0x805D, 0x0000);
2233 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2234 MDIO_XS_DEVAD, 0x805C, 0x030B);
2235 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2236 MDIO_XS_DEVAD, 0x805B, 0x1240);
2237 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2238 MDIO_XS_DEVAD, 0x805A, 0x2490);
2241 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2242 MDIO_XS_DEVAD, 0x80A7, 0x0C74);
2243 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2244 MDIO_XS_DEVAD, 0x80A6, 0x9041);
2245 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2246 MDIO_XS_DEVAD, 0x80A5, 0x4640);
2249 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2250 MDIO_XS_DEVAD, 0x80FE, 0x01C4);
2251 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2252 MDIO_XS_DEVAD, 0x80FD, 0x9249);
2253 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2254 MDIO_XS_DEVAD, 0x80FC, 0x2015);
2256 /* Enable PLL sequencer (use read-modify-write to set bit 13) */
2257 bnx2x_cl45_read(bp, port, ext_phy_type, ext_phy_addr,
2259 MDIO_XS_PLL_SEQUENCER, &val);
2261 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2262 MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
2264 static void bnx2x_bcm807x_force_10G(struct link_params *params)
2266 struct bnx2x *bp = params->bp;
2267 u8 port = params->port;
2268 u8 ext_phy_addr = ((params->ext_phy_config &
2269 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2270 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2271 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2273 /* Force KR or KX */
2274 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2278 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2280 MDIO_PMA_REG_10G_CTRL2,
2282 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2284 MDIO_PMA_REG_BCM_CTRL,
2286 bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
2292 static void bnx2x_ext_phy_set_pause(struct link_params *params,
2293 struct link_vars *vars)
2295 struct bnx2x *bp = params->bp;
2297 u8 ext_phy_addr = ((params->ext_phy_config &
2298 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2299 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2300 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2302 /* read modify write pause advertizing */
2303 bnx2x_cl45_read(bp, params->port,
2307 MDIO_AN_REG_ADV_PAUSE, &val);
2309 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
2311 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
2313 if ((vars->ieee_fc &
2314 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
2315 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
2316 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
2318 if ((vars->ieee_fc &
2319 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
2320 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
2322 MDIO_AN_REG_ADV_PAUSE_PAUSE;
2325 "Ext phy AN advertize 0x%x\n", val);
2326 bnx2x_cl45_write(bp, params->port,
2330 MDIO_AN_REG_ADV_PAUSE, val);
2334 static void bnx2x_init_internal_phy(struct link_params *params,
2335 struct link_vars *vars)
2337 struct bnx2x *bp = params->bp;
2338 u8 port = params->port;
2339 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
2342 rx_eq = ((params->serdes_config &
2343 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK) >>
2344 PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT);
2346 DP(NETIF_MSG_LINK, "setting rx eq to 0x%x\n", rx_eq);
2347 for (bank = MDIO_REG_BANK_RX0; bank <= MDIO_REG_BANK_RX_ALL;
2348 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0)) {
2349 CL45_WR_OVER_CL22(bp, port,
2352 MDIO_RX0_RX_EQ_BOOST,
2354 MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK) |
2355 MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL));
2358 /* forced speed requested? */
2359 if (vars->line_speed != SPEED_AUTO_NEG) {
2360 DP(NETIF_MSG_LINK, "not SGMII, no AN\n");
2362 /* disable autoneg */
2363 bnx2x_set_autoneg(params, vars);
2365 /* program speed and duplex */
2366 bnx2x_program_serdes(params, vars);
2368 } else { /* AN_mode */
2369 DP(NETIF_MSG_LINK, "not SGMII, AN\n");
2372 bnx2x_set_brcm_cl37_advertisment(params);
2374 /* program duplex & pause advertisement (for aneg) */
2375 bnx2x_set_ieee_aneg_advertisment(params,
2378 /* enable autoneg */
2379 bnx2x_set_autoneg(params, vars);
2381 /* enable and restart AN */
2382 bnx2x_restart_autoneg(params);
2385 } else { /* SGMII mode */
2386 DP(NETIF_MSG_LINK, "SGMII\n");
2388 bnx2x_initialize_sgmii_process(params, vars);
2392 static u8 bnx2x_ext_phy_init(struct link_params *params, struct link_vars *vars)
2394 struct bnx2x *bp = params->bp;
2401 if (vars->phy_flags & PHY_XGXS_FLAG) {
2402 ext_phy_addr = ((params->ext_phy_config &
2403 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2404 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2406 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2407 /* Make sure that the soft reset is off (expect for the 8072:
2408 * due to the lock, it will be done inside the specific
2411 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
2412 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
2413 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) &&
2414 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) &&
2415 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) {
2416 /* Wait for soft reset to get cleared upto 1 sec */
2417 for (cnt = 0; cnt < 1000; cnt++) {
2418 bnx2x_cl45_read(bp, params->port,
2422 MDIO_PMA_REG_CTRL, &ctrl);
2423 if (!(ctrl & (1<<15)))
2427 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n",
2431 switch (ext_phy_type) {
2432 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
2435 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
2436 DP(NETIF_MSG_LINK, "XGXS 8705\n");
2438 bnx2x_cl45_write(bp, params->port,
2442 MDIO_PMA_REG_MISC_CTRL,
2444 bnx2x_cl45_write(bp, params->port,
2448 MDIO_PMA_REG_PHY_IDENTIFIER,
2450 bnx2x_cl45_write(bp, params->port,
2454 MDIO_PMA_REG_CMU_PLL_BYPASS,
2456 bnx2x_cl45_write(bp, params->port,
2460 MDIO_WIS_REG_LASI_CNTL, 0x1);
2463 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
2464 DP(NETIF_MSG_LINK, "XGXS 8706\n");
2468 /* First enable LASI */
2469 bnx2x_cl45_write(bp, params->port,
2473 MDIO_PMA_REG_RX_ALARM_CTRL,
2475 bnx2x_cl45_write(bp, params->port,
2479 MDIO_PMA_REG_LASI_CTRL, 0x0004);
2481 if (params->req_line_speed == SPEED_10000) {
2482 DP(NETIF_MSG_LINK, "XGXS 8706 force 10Gbps\n");
2484 bnx2x_cl45_write(bp, params->port,
2488 MDIO_PMA_REG_DIGITAL_CTRL,
2491 /* Force 1Gbps using autoneg with 1G
2494 /* Allow CL37 through CL73 */
2495 DP(NETIF_MSG_LINK, "XGXS 8706 AutoNeg\n");
2496 bnx2x_cl45_write(bp, params->port,
2500 MDIO_AN_REG_CL37_CL73,
2503 /* Enable Full-Duplex advertisment on CL37 */
2504 bnx2x_cl45_write(bp, params->port,
2508 MDIO_AN_REG_CL37_FC_LP,
2510 /* Enable CL37 AN */
2511 bnx2x_cl45_write(bp, params->port,
2515 MDIO_AN_REG_CL37_AN,
2518 bnx2x_cl45_write(bp, params->port,
2522 MDIO_AN_REG_ADV, (1<<5));
2524 /* Enable clause 73 AN */
2525 bnx2x_cl45_write(bp, params->port,
2536 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
2537 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
2540 u16 rx_alarm_ctrl_val;
2543 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
2544 rx_alarm_ctrl_val = 0x400;
2545 lasi_ctrl_val = 0x0004;
2547 /* In 8073, port1 is directed through emac0 and
2548 * port0 is directed through emac1
2550 rx_alarm_ctrl_val = (1<<2);
2551 /*lasi_ctrl_val = 0x0005;*/
2552 lasi_ctrl_val = 0x0004;
2555 /* Wait for soft reset to get cleared upto 1 sec */
2556 for (cnt = 0; cnt < 1000; cnt++) {
2557 bnx2x_cl45_read(bp, params->port,
2563 if (!(ctrl & (1<<15)))
2568 "807x control reg 0x%x (after %d ms)\n",
2572 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072){
2573 bnx2x_bcm8072_external_rom_boot(params);
2575 bnx2x_bcm8073_external_rom_boot(params);
2576 /* In case of 8073 with long xaui lines,
2577 don't set the 8073 xaui low power*/
2578 bnx2x_bcm8073_set_xaui_low_power_mode(params);
2582 bnx2x_cl45_write(bp, params->port,
2586 MDIO_PMA_REG_RX_ALARM_CTRL,
2589 bnx2x_cl45_write(bp, params->port,
2593 MDIO_PMA_REG_LASI_CTRL,
2596 bnx2x_cl45_read(bp, params->port,
2600 MDIO_PMA_REG_RX_ALARM, &tmp1);
2602 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1):"
2605 /* If this is forced speed, set to KR or KX
2606 * (all other are not supported)
2608 if (!(params->req_line_speed == SPEED_AUTO_NEG)) {
2609 if (params->req_line_speed == SPEED_10000) {
2610 bnx2x_bcm807x_force_10G(params);
2612 "Forced speed 10G on 807X\n");
2614 } else if (params->req_line_speed ==
2617 /* Note that 2.5G works only
2618 when used with 1G advertisment */
2624 if (params->speed_cap_mask &
2625 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2628 if (params->speed_cap_mask &
2629 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
2631 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val);
2632 /*val = ((1<<5)|(1<<7));*/
2635 bnx2x_cl45_write(bp, params->port,
2639 MDIO_AN_REG_ADV, val);
2642 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
2643 /* Disable 2.5Ghz */
2644 bnx2x_cl45_read(bp, params->port,
2649 /* SUPPORT_SPEED_CAPABILITY
2650 (Due to the nature of the link order, its not
2651 possible to enable 2.5G within the autoneg
2653 if (params->speed_cap_mask &
2654 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
2656 if (params->req_line_speed == SPEED_2500) {
2658 /* Allow 2.5G for A1 and above */
2659 bnx2x_cl45_read(bp, params->port,
2660 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
2673 bnx2x_cl45_write(bp, params->port,
2679 /* Add support for CL37 (passive mode) I */
2680 bnx2x_cl45_write(bp, params->port,
2684 MDIO_AN_REG_CL37_FC_LD, 0x040c);
2685 /* Add support for CL37 (passive mode) II */
2686 bnx2x_cl45_write(bp, params->port,
2690 MDIO_AN_REG_CL37_FC_LD, 0x20);
2691 /* Add support for CL37 (passive mode) III */
2692 bnx2x_cl45_write(bp, params->port,
2696 MDIO_AN_REG_CL37_AN, 0x1000);
2697 /* Restart autoneg */
2701 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
2703 /* The SNR will improve about 2db by changing the
2704 BW and FEE main tap. Rest commands are executed
2706 /* Change FFE main cursor to 5 in EDC register */
2707 if (bnx2x_8073_is_snr_needed(params))
2708 bnx2x_cl45_write(bp, params->port,
2712 MDIO_PMA_REG_EDC_FFE_MAIN,
2715 /* Enable FEC (Forware Error Correction)
2716 Request in the AN */
2717 bnx2x_cl45_read(bp, params->port,
2721 MDIO_AN_REG_ADV2, &tmp1);
2725 bnx2x_cl45_write(bp, params->port,
2729 MDIO_AN_REG_ADV2, tmp1);
2732 bnx2x_ext_phy_set_pause(params, vars);
2734 bnx2x_cl45_write(bp, params->port,
2738 MDIO_AN_REG_CTRL, 0x1200);
2739 DP(NETIF_MSG_LINK, "807x Autoneg Restart: "
2740 "Advertise 1G=%x, 10G=%x\n",
2741 ((val & (1<<5)) > 0),
2742 ((val & (1<<7)) > 0));
2745 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
2747 "Setting the SFX7101 LASI indication\n");
2749 bnx2x_cl45_write(bp, params->port,
2753 MDIO_PMA_REG_LASI_CTRL, 0x1);
2755 "Setting the SFX7101 LED to blink on traffic\n");
2756 bnx2x_cl45_write(bp, params->port,
2760 MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
2762 bnx2x_ext_phy_set_pause(params, vars);
2763 /* Restart autoneg */
2764 bnx2x_cl45_read(bp, params->port,
2768 MDIO_AN_REG_CTRL, &val);
2770 bnx2x_cl45_write(bp, params->port,
2774 MDIO_AN_REG_CTRL, val);
2776 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
2778 "XGXS PHY Failure detected 0x%x\n",
2779 params->ext_phy_config);
2783 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
2784 params->ext_phy_config);
2789 } else { /* SerDes */
2791 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
2792 switch (ext_phy_type) {
2793 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
2794 DP(NETIF_MSG_LINK, "SerDes Direct\n");
2797 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
2798 DP(NETIF_MSG_LINK, "SerDes 5482\n");
2802 DP(NETIF_MSG_LINK, "BAD SerDes ext_phy_config 0x%x\n",
2803 params->ext_phy_config);
2811 static u8 bnx2x_ext_phy_is_link_up(struct link_params *params,
2812 struct link_vars *vars)
2814 struct bnx2x *bp = params->bp;
2818 u16 rx_sd, pcs_status;
2819 u8 ext_phy_link_up = 0;
2820 u8 port = params->port;
2821 if (vars->phy_flags & PHY_XGXS_FLAG) {
2822 ext_phy_addr = ((params->ext_phy_config &
2823 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
2824 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
2826 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
2827 switch (ext_phy_type) {
2828 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
2829 DP(NETIF_MSG_LINK, "XGXS Direct\n");
2830 ext_phy_link_up = 1;
2833 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
2834 DP(NETIF_MSG_LINK, "XGXS 8705\n");
2835 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2838 MDIO_WIS_REG_LASI_STATUS, &val1);
2839 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
2841 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2844 MDIO_WIS_REG_LASI_STATUS, &val1);
2845 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1);
2847 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2850 MDIO_PMA_REG_RX_SD, &rx_sd);
2851 DP(NETIF_MSG_LINK, "8705 rx_sd 0x%x\n", rx_sd);
2852 ext_phy_link_up = (rx_sd & 0x1);
2853 if (ext_phy_link_up)
2854 vars->line_speed = SPEED_10000;
2857 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
2858 DP(NETIF_MSG_LINK, "XGXS 8706\n");
2859 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2862 MDIO_PMA_REG_LASI_STATUS, &val1);
2863 DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1);
2865 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2868 MDIO_PMA_REG_LASI_STATUS, &val1);
2869 DP(NETIF_MSG_LINK, "8706 LASI status 0x%x\n", val1);
2871 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2874 MDIO_PMA_REG_RX_SD, &rx_sd);
2875 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2878 MDIO_PCS_REG_STATUS, &pcs_status);
2880 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2883 MDIO_AN_REG_LINK_STATUS, &val2);
2884 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2887 MDIO_AN_REG_LINK_STATUS, &val2);
2889 DP(NETIF_MSG_LINK, "8706 rx_sd 0x%x"
2890 " pcs_status 0x%x 1Gbps link_status 0x%x\n",
2891 rx_sd, pcs_status, val2);
2892 /* link is up if both bit 0 of pmd_rx_sd and
2893 * bit 0 of pcs_status are set, or if the autoneg bit
2896 ext_phy_link_up = ((rx_sd & pcs_status & 0x1) ||
2898 if (ext_phy_link_up) {
2900 vars->line_speed = SPEED_1000;
2902 vars->line_speed = SPEED_10000;
2905 /* clear LASI indication*/
2906 bnx2x_cl45_read(bp, params->port, ext_phy_type,
2909 MDIO_PMA_REG_RX_ALARM, &val2);
2912 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
2913 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
2916 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) {
2917 bnx2x_cl45_read(bp, params->port,
2921 MDIO_PCS_REG_LASI_STATUS, &val1);
2922 bnx2x_cl45_read(bp, params->port,
2926 MDIO_PCS_REG_LASI_STATUS, &val2);
2928 "870x LASI status 0x%x->0x%x\n",
2932 /* In 8073, port1 is directed through emac0 and
2933 * port0 is directed through emac1
2935 bnx2x_cl45_read(bp, params->port,
2939 MDIO_PMA_REG_LASI_STATUS, &val1);
2941 bnx2x_cl45_read(bp, params->port,
2945 MDIO_PMA_REG_LASI_STATUS, &val2);
2947 "8703 LASI status 0x%x->0x%x\n",
2951 /* clear the interrupt LASI status register */
2952 bnx2x_cl45_read(bp, params->port,
2956 MDIO_PCS_REG_STATUS, &val2);
2957 bnx2x_cl45_read(bp, params->port,
2961 MDIO_PCS_REG_STATUS, &val1);
2962 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n",
2964 /* Check the LASI */
2965 bnx2x_cl45_read(bp, params->port,
2969 MDIO_PMA_REG_RX_ALARM, &val2);
2970 bnx2x_cl45_read(bp, params->port,
2974 MDIO_PMA_REG_RX_ALARM,
2976 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x->0x%x\n",
2978 /* Check the link status */
2979 bnx2x_cl45_read(bp, params->port,
2983 MDIO_PCS_REG_STATUS, &val2);
2984 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2);
2986 bnx2x_cl45_read(bp, params->port,
2990 MDIO_PMA_REG_STATUS, &val2);
2991 bnx2x_cl45_read(bp, params->port,
2995 MDIO_PMA_REG_STATUS, &val1);
2996 ext_phy_link_up = ((val1 & 4) == 4);
2997 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1);
2999 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
3000 u16 an1000_status = 0;
3001 if (ext_phy_link_up &&
3003 (params->req_line_speed != SPEED_10000)
3005 if (bnx2x_bcm8073_xaui_wa(params)
3007 ext_phy_link_up = 0;
3010 bnx2x_cl45_read(bp, params->port,
3016 bnx2x_cl45_read(bp, params->port,
3023 /* Check the link status on 1.1.2 */
3024 bnx2x_cl45_read(bp, params->port,
3028 MDIO_PMA_REG_STATUS, &val2);
3029 bnx2x_cl45_read(bp, params->port,
3033 MDIO_PMA_REG_STATUS, &val1);
3034 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x,"
3035 "an_link_status=0x%x\n",
3036 val2, val1, an1000_status);
3038 ext_phy_link_up = (((val1 & 4) == 4) ||
3039 (an1000_status & (1<<1)));
3040 if (ext_phy_link_up &&
3041 bnx2x_8073_is_snr_needed(params)) {
3042 /* The SNR will improve about 2dbby
3043 changing the BW and FEE main tap.*/
3045 /* The 1st write to change FFE main
3046 tap is set before restart AN */
3047 /* Change PLL Bandwidth in EDC
3049 bnx2x_cl45_write(bp, port, ext_phy_type,
3052 MDIO_PMA_REG_PLL_BANDWIDTH,
3055 /* Change CDR Bandwidth in EDC
3057 bnx2x_cl45_write(bp, port, ext_phy_type,
3060 MDIO_PMA_REG_CDR_BANDWIDTH,
3067 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
3068 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3071 MDIO_PMA_REG_LASI_STATUS, &val2);
3072 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3075 MDIO_PMA_REG_LASI_STATUS, &val1);
3077 "10G-base-T LASI status 0x%x->0x%x\n",
3079 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3082 MDIO_PMA_REG_STATUS, &val2);
3083 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3086 MDIO_PMA_REG_STATUS, &val1);
3088 "10G-base-T PMA status 0x%x->0x%x\n",
3090 ext_phy_link_up = ((val1 & 4) == 4);
3092 * print the AN outcome of the SFX7101 PHY
3094 if (ext_phy_link_up) {
3095 bnx2x_cl45_read(bp, params->port,
3099 MDIO_AN_REG_MASTER_STATUS,
3101 vars->line_speed = SPEED_10000;
3103 "SFX7101 AN status 0x%x->Master=%x\n",
3110 DP(NETIF_MSG_LINK, "BAD XGXS ext_phy_config 0x%x\n",
3111 params->ext_phy_config);
3112 ext_phy_link_up = 0;
3116 } else { /* SerDes */
3117 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
3118 switch (ext_phy_type) {
3119 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
3120 DP(NETIF_MSG_LINK, "SerDes Direct\n");
3121 ext_phy_link_up = 1;
3124 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
3125 DP(NETIF_MSG_LINK, "SerDes 5482\n");
3126 ext_phy_link_up = 1;
3131 "BAD SerDes ext_phy_config 0x%x\n",
3132 params->ext_phy_config);
3133 ext_phy_link_up = 0;
3138 return ext_phy_link_up;
3141 static void bnx2x_link_int_enable(struct link_params *params)
3143 u8 port = params->port;
3146 struct bnx2x *bp = params->bp;
3147 /* setting the status to report on link up
3148 for either XGXS or SerDes */
3150 if (params->switch_cfg == SWITCH_CFG_10G) {
3151 mask = (NIG_MASK_XGXS0_LINK10G |
3152 NIG_MASK_XGXS0_LINK_STATUS);
3153 DP(NETIF_MSG_LINK, "enabled XGXS interrupt\n");
3154 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3155 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
3156 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
3158 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) {
3159 mask |= NIG_MASK_MI_INT;
3160 DP(NETIF_MSG_LINK, "enabled external phy int\n");
3163 } else { /* SerDes */
3164 mask = NIG_MASK_SERDES0_LINK_STATUS;
3165 DP(NETIF_MSG_LINK, "enabled SerDes interrupt\n");
3166 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
3167 if ((ext_phy_type !=
3168 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
3170 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN)) {
3171 mask |= NIG_MASK_MI_INT;
3172 DP(NETIF_MSG_LINK, "enabled external phy int\n");
3176 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3178 DP(NETIF_MSG_LINK, "port %x, is_xgxs=%x, int_status 0x%x\n", port,
3179 (params->switch_cfg == SWITCH_CFG_10G),
3180 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
3182 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
3183 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
3184 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
3185 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
3186 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
3187 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
3188 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
3195 static void bnx2x_link_int_ack(struct link_params *params,
3196 struct link_vars *vars, u16 is_10g)
3198 struct bnx2x *bp = params->bp;
3199 u8 port = params->port;
3201 /* first reset all status
3202 * we assume only one line will be change at a time */
3203 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3204 (NIG_STATUS_XGXS0_LINK10G |
3205 NIG_STATUS_XGXS0_LINK_STATUS |
3206 NIG_STATUS_SERDES0_LINK_STATUS));
3207 if (vars->phy_link_up) {
3209 /* Disable the 10G link interrupt
3210 * by writing 1 to the status register
3212 DP(NETIF_MSG_LINK, "10G XGXS phy link up\n");
3214 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3215 NIG_STATUS_XGXS0_LINK10G);
3217 } else if (params->switch_cfg == SWITCH_CFG_10G) {
3218 /* Disable the link interrupt
3219 * by writing 1 to the relevant lane
3220 * in the status register
3222 u32 ser_lane = ((params->lane_config &
3223 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
3224 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
3226 DP(NETIF_MSG_LINK, "1G XGXS phy link up\n");
3228 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3230 NIG_STATUS_XGXS0_LINK_STATUS_SIZE));
3232 } else { /* SerDes */
3233 DP(NETIF_MSG_LINK, "SerDes phy link up\n");
3234 /* Disable the link interrupt
3235 * by writing 1 to the status register
3238 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3239 NIG_STATUS_SERDES0_LINK_STATUS);
3242 } else { /* link_down */
3246 static u8 bnx2x_format_ver(u32 num, u8 *str, u16 len)
3249 u32 mask = 0xf0000000;
3253 /* Need more then 10chars for this format */
3260 digit = ((num & mask) >> shift);
3262 *str_ptr = digit + '0';
3264 *str_ptr = digit - 0xa + 'a';
3277 static void bnx2x_turn_on_ef(struct bnx2x *bp, u8 port, u8 ext_phy_addr,
3282 /* Enable EMAC0 in to enable MDIO */
3283 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
3284 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
3287 /* take ext phy out of reset */
3289 MISC_REGISTERS_GPIO_2,
3290 MISC_REGISTERS_GPIO_HIGH);
3293 MISC_REGISTERS_GPIO_1,
3294 MISC_REGISTERS_GPIO_HIGH);
3299 for (cnt = 0; cnt < 1000; cnt++) {
3301 bnx2x_cl45_read(bp, port,
3307 if (!(ctrl & (1<<15))) {
3308 DP(NETIF_MSG_LINK, "Reset completed\n\n");
3314 static void bnx2x_turn_off_sf(struct bnx2x *bp)
3316 /* put sf to reset */
3317 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1, MISC_REGISTERS_GPIO_LOW);
3319 MISC_REGISTERS_GPIO_2,
3320 MISC_REGISTERS_GPIO_LOW);
3323 u8 bnx2x_get_ext_phy_fw_version(struct link_params *params, u8 driver_loaded,
3324 u8 *version, u16 len)
3326 struct bnx2x *bp = params->bp;
3327 u32 ext_phy_type = 0;
3329 u8 ext_phy_addr = 0 ;
3333 if (version == NULL || params == NULL)
3336 /* reset the returned value to zero */
3337 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3338 ext_phy_addr = ((params->ext_phy_config &
3339 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3340 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3342 switch (ext_phy_type) {
3343 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
3348 /* Take ext phy out of reset */
3350 bnx2x_turn_on_ef(bp, params->port, ext_phy_addr,
3356 bnx2x_cl45_read(bp, params->port,
3360 MDIO_PMA_REG_7101_VER1, &val);
3361 version[2] = (val & 0xFF);
3362 version[3] = ((val & 0xFF00)>>8);
3364 bnx2x_cl45_read(bp, params->port,
3367 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2,
3369 version[0] = (val & 0xFF);
3370 version[1] = ((val & 0xFF00)>>8);
3374 bnx2x_turn_off_sf(bp);
3376 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3377 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
3379 /* Take ext phy out of reset */
3381 bnx2x_turn_on_ef(bp, params->port, ext_phy_addr,
3384 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3387 MDIO_PMA_REG_ROM_VER1, &val);
3389 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3392 MDIO_PMA_REG_ROM_VER2, &val);
3394 status = bnx2x_format_ver(ver_num, version, len);
3397 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3398 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
3400 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3403 MDIO_PMA_REG_ROM_VER1, &val);
3405 bnx2x_cl45_read(bp, params->port, ext_phy_type,
3408 MDIO_PMA_REG_ROM_VER2, &val);
3410 status = bnx2x_format_ver(ver_num, version, len);
3413 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
3416 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
3417 DP(NETIF_MSG_LINK, "bnx2x_get_ext_phy_fw_version:"
3418 " type is FAILURE!\n");
3428 static void bnx2x_set_xgxs_loopback(struct link_params *params,
3429 struct link_vars *vars,
3432 u8 port = params->port;
3433 struct bnx2x *bp = params->bp;
3438 DP(NETIF_MSG_LINK, "XGXS 10G loopback enable\n");
3440 /* change the uni_phy_addr in the nig */
3441 md_devad = REG_RD(bp, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
3444 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 0x5);
3446 bnx2x_cl45_write(bp, port, 0,
3449 (MDIO_REG_BANK_AER_BLOCK +
3450 (MDIO_AER_BLOCK_AER_REG & 0xf)),
3453 bnx2x_cl45_write(bp, port, 0,
3456 (MDIO_REG_BANK_CL73_IEEEB0 +
3457 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
3460 /* set aer mmd back */
3461 bnx2x_set_aer_mmd(params, vars);
3464 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
3470 DP(NETIF_MSG_LINK, "XGXS 1G loopback enable\n");
3472 CL45_RD_OVER_CL22(bp, port,
3474 MDIO_REG_BANK_COMBO_IEEE0,
3475 MDIO_COMBO_IEEE0_MII_CONTROL,
3478 CL45_WR_OVER_CL22(bp, port,
3480 MDIO_REG_BANK_COMBO_IEEE0,
3481 MDIO_COMBO_IEEE0_MII_CONTROL,
3483 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK));
3488 static void bnx2x_ext_phy_loopback(struct link_params *params)
3490 struct bnx2x *bp = params->bp;
3494 if (params->switch_cfg == SWITCH_CFG_10G) {
3495 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3496 /* CL37 Autoneg Enabled */
3497 ext_phy_addr = ((params->ext_phy_config &
3498 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
3499 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
3500 switch (ext_phy_type) {
3501 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
3502 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
3504 "ext_phy_loopback: We should not get here\n");
3506 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
3507 DP(NETIF_MSG_LINK, "ext_phy_loopback: 8705\n");
3509 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
3510 DP(NETIF_MSG_LINK, "ext_phy_loopback: 8706\n");
3512 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
3513 /* SFX7101_XGXS_TEST1 */
3514 bnx2x_cl45_write(bp, params->port, ext_phy_type,
3517 MDIO_XS_SFX7101_XGXS_TEST1,
3520 "ext_phy_loopback: set ext phy loopback\n");
3522 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3525 } /* switch external PHY type */
3528 ext_phy_type = SERDES_EXT_PHY_TYPE(params->ext_phy_config);
3529 ext_phy_addr = (params->ext_phy_config &
3530 PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK)
3531 >> PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT;
3537 *------------------------------------------------------------------------
3538 * bnx2x_override_led_value -
3540 * Override the led value of the requsted led
3542 *------------------------------------------------------------------------
3544 u8 bnx2x_override_led_value(struct bnx2x *bp, u8 port,
3545 u32 led_idx, u32 value)
3549 /* If port 0 then use EMAC0, else use EMAC1*/
3550 u32 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3553 "bnx2x_override_led_value() port %x led_idx %d value %d\n",
3554 port, led_idx, value);
3557 case 0: /* 10MB led */
3558 /* Read the current value of the LED register in
3560 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
3561 /* Set the OVERRIDE bit to 1 */
3562 reg_val |= EMAC_LED_OVERRIDE;
3563 /* If value is 1, set the 10M_OVERRIDE bit,
3564 otherwise reset it.*/
3565 reg_val = (value == 1) ? (reg_val | EMAC_LED_10MB_OVERRIDE) :
3566 (reg_val & ~EMAC_LED_10MB_OVERRIDE);
3567 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
3569 case 1: /*100MB led */
3570 /*Read the current value of the LED register in
3572 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
3573 /* Set the OVERRIDE bit to 1 */
3574 reg_val |= EMAC_LED_OVERRIDE;
3575 /* If value is 1, set the 100M_OVERRIDE bit,
3576 otherwise reset it.*/
3577 reg_val = (value == 1) ? (reg_val | EMAC_LED_100MB_OVERRIDE) :
3578 (reg_val & ~EMAC_LED_100MB_OVERRIDE);
3579 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
3581 case 2: /* 1000MB led */
3582 /* Read the current value of the LED register in the
3584 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
3585 /* Set the OVERRIDE bit to 1 */
3586 reg_val |= EMAC_LED_OVERRIDE;
3587 /* If value is 1, set the 1000M_OVERRIDE bit, otherwise
3589 reg_val = (value == 1) ? (reg_val | EMAC_LED_1000MB_OVERRIDE) :
3590 (reg_val & ~EMAC_LED_1000MB_OVERRIDE);
3591 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
3593 case 3: /* 2500MB led */
3594 /* Read the current value of the LED register in the
3596 reg_val = REG_RD(bp, emac_base + EMAC_REG_EMAC_LED);
3597 /* Set the OVERRIDE bit to 1 */
3598 reg_val |= EMAC_LED_OVERRIDE;
3599 /* If value is 1, set the 2500M_OVERRIDE bit, otherwise
3601 reg_val = (value == 1) ? (reg_val | EMAC_LED_2500MB_OVERRIDE) :
3602 (reg_val & ~EMAC_LED_2500MB_OVERRIDE);
3603 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
3605 case 4: /*10G led */
3607 REG_WR(bp, NIG_REG_LED_10G_P0,
3610 REG_WR(bp, NIG_REG_LED_10G_P1,
3614 case 5: /* TRAFFIC led */
3615 /* Find if the traffic control is via BMAC or EMAC */
3617 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC0_EN);
3619 reg_val = REG_RD(bp, NIG_REG_NIG_EMAC1_EN);
3621 /* Override the traffic led in the EMAC:*/
3623 /* Read the current value of the LED register in
3625 reg_val = REG_RD(bp, emac_base +
3627 /* Set the TRAFFIC_OVERRIDE bit to 1 */
3628 reg_val |= EMAC_LED_OVERRIDE;
3629 /* If value is 1, set the TRAFFIC bit, otherwise
3631 reg_val = (value == 1) ? (reg_val | EMAC_LED_TRAFFIC) :
3632 (reg_val & ~EMAC_LED_TRAFFIC);
3633 REG_WR(bp, emac_base + EMAC_REG_EMAC_LED, reg_val);
3634 } else { /* Override the traffic led in the BMAC: */
3635 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
3637 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + port*4,
3643 "bnx2x_override_led_value() unknown led index %d "
3644 "(should be 0-5)\n", led_idx);
3652 u8 bnx2x_set_led(struct bnx2x *bp, u8 port, u8 mode, u32 speed,
3653 u16 hw_led_mode, u32 chip_id)
3656 DP(NETIF_MSG_LINK, "bnx2x_set_led: port %x, mode %d\n", port, mode);
3657 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n",
3658 speed, hw_led_mode);
3661 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0);
3662 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
3663 SHARED_HW_CFG_LED_MAC1);
3667 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode);
3668 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 +
3670 /* Set blinking rate to ~15.9Hz */
3671 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
3672 LED_BLINK_RATE_VAL);
3673 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
3675 if (!CHIP_IS_E1H(bp) &&
3676 ((speed == SPEED_2500) ||
3677 (speed == SPEED_1000) ||
3678 (speed == SPEED_100) ||
3679 (speed == SPEED_10))) {
3680 /* On Everest 1 Ax chip versions for speeds less than
3681 10G LED scheme is different */
3682 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
3684 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
3686 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
3693 DP(NETIF_MSG_LINK, "bnx2x_set_led: Invalid led mode %d\n",
3701 u8 bnx2x_test_link(struct link_params *params, struct link_vars *vars)
3703 struct bnx2x *bp = params->bp;
3706 CL45_RD_OVER_CL22(bp, params->port,
3708 MDIO_REG_BANK_GP_STATUS,
3709 MDIO_GP_STATUS_TOP_AN_STATUS1,
3711 /* link is up only if both local phy and external phy are up */
3712 if ((gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) &&
3713 bnx2x_ext_phy_is_link_up(params, vars))
3719 static u8 bnx2x_link_initialize(struct link_params *params,
3720 struct link_vars *vars)
3722 struct bnx2x *bp = params->bp;
3723 u8 port = params->port;
3726 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
3727 /* Activate the external PHY */
3728 bnx2x_ext_phy_reset(params, vars);
3730 bnx2x_set_aer_mmd(params, vars);
3732 if (vars->phy_flags & PHY_XGXS_FLAG)
3733 bnx2x_set_master_ln(params);
3735 rc = bnx2x_reset_unicore(params);
3736 /* reset the SerDes and wait for reset bit return low */
3740 bnx2x_set_aer_mmd(params, vars);
3742 /* setting the masterLn_def again after the reset */
3743 if (vars->phy_flags & PHY_XGXS_FLAG) {
3744 bnx2x_set_master_ln(params);
3745 bnx2x_set_swap_lanes(params);
3748 if (vars->phy_flags & PHY_XGXS_FLAG) {
3749 if (params->req_line_speed &&
3750 ((params->req_line_speed == SPEED_100) ||
3751 (params->req_line_speed == SPEED_10))) {
3752 vars->phy_flags |= PHY_SGMII_FLAG;
3754 vars->phy_flags &= ~PHY_SGMII_FLAG;
3757 /* In case of external phy existance, the line speed would be the
3758 line speed linked up by the external phy. In case it is direct only,
3759 then the line_speed during initialization will be equal to the
3761 vars->line_speed = params->req_line_speed;
3763 bnx2x_calc_ieee_aneg_adv(params, &vars->ieee_fc);
3765 /* init ext phy and enable link state int */
3766 non_ext_phy = ((ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ||
3767 (params->loopback_mode == LOOPBACK_XGXS_10) ||
3768 (params->loopback_mode == LOOPBACK_EXT_PHY));
3771 (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705)) {
3772 if (params->req_line_speed == SPEED_AUTO_NEG)
3773 bnx2x_set_parallel_detection(params, vars->phy_flags);
3774 bnx2x_init_internal_phy(params, vars);
3778 rc |= bnx2x_ext_phy_init(params, vars);
3780 bnx2x_bits_dis(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
3781 (NIG_STATUS_XGXS0_LINK10G |
3782 NIG_STATUS_XGXS0_LINK_STATUS |
3783 NIG_STATUS_SERDES0_LINK_STATUS));
3790 u8 bnx2x_phy_init(struct link_params *params, struct link_vars *vars)
3792 struct bnx2x *bp = params->bp;
3795 DP(NETIF_MSG_LINK, "Phy Initialization started\n");
3796 DP(NETIF_MSG_LINK, "req_speed = %d, req_flowctrl=%d\n",
3797 params->req_line_speed, params->req_flow_ctrl);
3798 vars->link_status = 0;
3799 vars->phy_link_up = 0;
3801 vars->line_speed = 0;
3802 vars->duplex = DUPLEX_FULL;
3803 vars->flow_ctrl = FLOW_CTRL_NONE;
3804 vars->mac_type = MAC_TYPE_NONE;
3806 if (params->switch_cfg == SWITCH_CFG_1G)
3807 vars->phy_flags = PHY_SERDES_FLAG;
3809 vars->phy_flags = PHY_XGXS_FLAG;
3811 /* disable attentions */
3812 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
3813 (NIG_MASK_XGXS0_LINK_STATUS |
3814 NIG_MASK_XGXS0_LINK10G |
3815 NIG_MASK_SERDES0_LINK_STATUS |
3818 bnx2x_emac_init(params, vars);
3820 if (CHIP_REV_IS_FPGA(bp)) {
3822 vars->line_speed = SPEED_10000;
3823 vars->duplex = DUPLEX_FULL;
3824 vars->flow_ctrl = FLOW_CTRL_NONE;
3825 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
3826 /* enable on E1.5 FPGA */
3827 if (CHIP_IS_E1H(bp)) {
3829 (FLOW_CTRL_TX | FLOW_CTRL_RX);
3830 vars->link_status |=
3831 (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
3832 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
3835 bnx2x_emac_enable(params, vars, 0);
3836 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
3838 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
3839 + params->port*4, 0);
3841 /* update shared memory */
3842 bnx2x_update_mng(params, vars->link_status);
3847 if (CHIP_REV_IS_EMUL(bp)) {
3850 vars->line_speed = SPEED_10000;
3851 vars->duplex = DUPLEX_FULL;
3852 vars->flow_ctrl = FLOW_CTRL_NONE;
3853 vars->link_status = (LINK_STATUS_LINK_UP | LINK_10GTFD);
3855 bnx2x_bmac_enable(params, vars, 0);
3857 bnx2x_pbf_update(params, vars->flow_ctrl, vars->line_speed);
3859 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE
3860 + params->port*4, 0);
3862 /* update shared memory */
3863 bnx2x_update_mng(params, vars->link_status);
3868 if (params->loopback_mode == LOOPBACK_BMAC) {
3870 vars->line_speed = SPEED_10000;
3871 vars->duplex = DUPLEX_FULL;
3872 vars->flow_ctrl = FLOW_CTRL_NONE;
3873 vars->mac_type = MAC_TYPE_BMAC;
3875 vars->phy_flags = PHY_XGXS_FLAG;
3877 bnx2x_phy_deassert(params, vars->phy_flags);
3878 /* set bmac loopback */
3879 bnx2x_bmac_enable(params, vars, 1);
3881 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
3883 } else if (params->loopback_mode == LOOPBACK_EMAC) {
3885 vars->line_speed = SPEED_1000;
3886 vars->duplex = DUPLEX_FULL;
3887 vars->flow_ctrl = FLOW_CTRL_NONE;
3888 vars->mac_type = MAC_TYPE_EMAC;
3890 vars->phy_flags = PHY_XGXS_FLAG;
3892 bnx2x_phy_deassert(params, vars->phy_flags);
3893 /* set bmac loopback */
3894 bnx2x_emac_enable(params, vars, 1);
3895 bnx2x_emac_program(params, vars->line_speed,
3897 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
3899 } else if ((params->loopback_mode == LOOPBACK_XGXS_10) ||
3900 (params->loopback_mode == LOOPBACK_EXT_PHY)) {
3902 vars->line_speed = SPEED_10000;
3903 vars->duplex = DUPLEX_FULL;
3904 vars->flow_ctrl = FLOW_CTRL_NONE;
3906 vars->phy_flags = PHY_XGXS_FLAG;
3909 NIG_REG_XGXS0_CTRL_PHY_ADDR+
3911 params->phy_addr = (u8)val;
3913 bnx2x_phy_deassert(params, vars->phy_flags);
3914 bnx2x_link_initialize(params, vars);
3916 vars->mac_type = MAC_TYPE_BMAC;
3918 bnx2x_bmac_enable(params, vars, 0);
3920 if (params->loopback_mode == LOOPBACK_XGXS_10) {
3921 /* set 10G XGXS loopback */
3922 bnx2x_set_xgxs_loopback(params, vars, 1);
3924 /* set external phy loopback */
3925 bnx2x_ext_phy_loopback(params);
3927 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE +
3933 bnx2x_phy_deassert(params, vars->phy_flags);
3934 switch (params->switch_cfg) {
3936 vars->phy_flags |= PHY_SERDES_FLAG;
3937 if ((params->ext_phy_config &
3938 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK) ==
3939 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482) {
3945 NIG_REG_SERDES0_CTRL_PHY_ADDR+
3948 params->phy_addr = (u8)val;
3951 case SWITCH_CFG_10G:
3952 vars->phy_flags |= PHY_XGXS_FLAG;
3954 NIG_REG_XGXS0_CTRL_PHY_ADDR+
3956 params->phy_addr = (u8)val;
3960 DP(NETIF_MSG_LINK, "Invalid switch_cfg\n");
3965 bnx2x_link_initialize(params, vars);
3967 bnx2x_link_int_enable(params);
3972 u8 bnx2x_link_reset(struct link_params *params, struct link_vars *vars)
3975 struct bnx2x *bp = params->bp;
3976 u32 ext_phy_config = params->ext_phy_config;
3977 u16 hw_led_mode = params->hw_led_mode;
3978 u32 chip_id = params->chip_id;
3979 u8 port = params->port;
3980 u32 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
3981 /* disable attentions */
3983 vars->link_status = 0;
3984 bnx2x_update_mng(params, vars->link_status);
3985 bnx2x_bits_dis(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
3986 (NIG_MASK_XGXS0_LINK_STATUS |
3987 NIG_MASK_XGXS0_LINK10G |
3988 NIG_MASK_SERDES0_LINK_STATUS |
3991 /* activate nig drain */
3992 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
3994 /* disable nig egress interface */
3995 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
3996 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
3998 /* Stop BigMac rx */
3999 bnx2x_bmac_rx_disable(bp, port);
4002 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
4005 /* The PHY reset is controled by GPIO 1
4006 * Hold it as vars low
4008 /* clear link led */
4009 bnx2x_set_led(bp, port, LED_MODE_OFF, 0, hw_led_mode, chip_id);
4010 if (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
4011 if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072) &&
4012 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)) {
4015 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_1,
4016 MISC_REGISTERS_GPIO_OUTPUT_LOW);
4018 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4019 MISC_REGISTERS_GPIO_OUTPUT_LOW);
4021 DP(NETIF_MSG_LINK, "reset external PHY\n");
4022 } else if (ext_phy_type ==
4023 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073) {
4024 DP(NETIF_MSG_LINK, "Setting 8073 port %d into "
4027 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_2,
4028 MISC_REGISTERS_GPIO_OUTPUT_LOW);
4031 /* reset the SerDes/XGXS */
4032 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
4033 (0x1ff << (port*16)));
4036 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
4037 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
4039 /* disable nig ingress interface */
4040 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
4041 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
4042 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0);
4043 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
4048 static u8 bnx2x_update_link_down(struct link_params *params,
4049 struct link_vars *vars)
4051 struct bnx2x *bp = params->bp;
4052 u8 port = params->port;
4053 DP(NETIF_MSG_LINK, "Port %x: Link is down\n", port);
4054 bnx2x_set_led(bp, port, LED_MODE_OFF,
4055 0, params->hw_led_mode,
4058 /* indicate no mac active */
4059 vars->mac_type = MAC_TYPE_NONE;
4061 /* update shared memory */
4062 vars->link_status = 0;
4063 vars->line_speed = 0;
4064 bnx2x_update_mng(params, vars->link_status);
4066 /* activate nig drain */
4067 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
4070 bnx2x_bmac_rx_disable(bp, params->port);
4071 REG_WR(bp, GRCBASE_MISC +
4072 MISC_REGISTERS_RESET_REG_2_CLEAR,
4073 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
4077 static u8 bnx2x_update_link_up(struct link_params *params,
4078 struct link_vars *vars,
4079 u8 link_10g, u32 gp_status)
4081 struct bnx2x *bp = params->bp;
4082 u8 port = params->port;
4084 vars->link_status |= LINK_STATUS_LINK_UP;
4086 bnx2x_bmac_enable(params, vars, 0);
4087 bnx2x_set_led(bp, port, LED_MODE_OPER,
4088 SPEED_10000, params->hw_led_mode,
4092 bnx2x_emac_enable(params, vars, 0);
4093 rc = bnx2x_emac_program(params, vars->line_speed,
4097 if (gp_status & MDIO_AN_CL73_OR_37_COMPLETE) {
4098 if (!(vars->phy_flags &
4100 bnx2x_set_sgmii_tx_driver(params);
4105 rc |= bnx2x_pbf_update(params, vars->flow_ctrl,
4109 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
4111 /* update shared memory */
4112 bnx2x_update_mng(params, vars->link_status);
4115 /* This function should called upon link interrupt */
4116 /* In case vars->link_up, driver needs to
4119 3. Update the shared memory
4123 1. Update shared memory
4128 u8 bnx2x_link_update(struct link_params *params, struct link_vars *vars)
4130 struct bnx2x *bp = params->bp;
4131 u8 port = params->port;
4134 u8 ext_phy_link_up, rc = 0;
4137 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n",
4139 (vars->phy_flags & PHY_XGXS_FLAG),
4140 REG_RD(bp, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
4142 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
4143 REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
4144 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
4145 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
4147 DP(NETIF_MSG_LINK, " 10G %x, XGXS_LINK %x\n",
4148 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
4149 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
4151 ext_phy_type = XGXS_EXT_PHY_TYPE(params->ext_phy_config);
4153 /* Check external link change only for non-direct */
4154 ext_phy_link_up = bnx2x_ext_phy_is_link_up(params, vars);
4156 /* Read gp_status */
4157 CL45_RD_OVER_CL22(bp, port, params->phy_addr,
4158 MDIO_REG_BANK_GP_STATUS,
4159 MDIO_GP_STATUS_TOP_AN_STATUS1,
4162 rc = bnx2x_link_settings_status(params, vars, gp_status);
4166 /* anything 10 and over uses the bmac */
4167 link_10g = ((vars->line_speed == SPEED_10000) ||
4168 (vars->line_speed == SPEED_12000) ||
4169 (vars->line_speed == SPEED_12500) ||
4170 (vars->line_speed == SPEED_13000) ||
4171 (vars->line_speed == SPEED_15000) ||
4172 (vars->line_speed == SPEED_16000));
4174 bnx2x_link_int_ack(params, vars, link_10g);
4176 /* In case external phy link is up, and internal link is down
4177 ( not initialized yet probably after link initialization, it needs
4179 Note that after link down-up as result of cable plug,
4180 the xgxs link would probably become up again without the need to
4183 if ((ext_phy_type != PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT) &&
4184 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) &&
4185 (ext_phy_link_up && !vars->phy_link_up))
4186 bnx2x_init_internal_phy(params, vars);
4188 /* link is up only if both local phy and external phy are up */
4189 vars->link_up = (ext_phy_link_up && vars->phy_link_up);
4192 rc = bnx2x_update_link_up(params, vars, link_10g, gp_status);
4194 rc = bnx2x_update_link_down(params, vars);
4199 static void bnx2x_sfx7101_sp_sw_reset(struct bnx2x *bp, u8 port, u8 phy_addr)
4203 bnx2x_cl45_read(bp, port,
4204 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4207 MDIO_PMA_REG_7101_RESET, &val);
4209 for (cnt = 0; cnt < 10; cnt++) {
4211 /* Writes a self-clearing reset */
4212 bnx2x_cl45_write(bp, port,
4213 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4216 MDIO_PMA_REG_7101_RESET,
4218 /* Wait for clear */
4219 bnx2x_cl45_read(bp, port,
4220 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4223 MDIO_PMA_REG_7101_RESET, &val);
4225 if ((val & (1<<15)) == 0)
4229 #define RESERVED_SIZE 256
4230 /* max application is 160K bytes - data at end of RAM */
4231 #define MAX_APP_SIZE 160*1024 - RESERVED_SIZE
4233 /* Header is 14 bytes */
4234 #define HEADER_SIZE 14
4235 #define DATA_OFFSET HEADER_SIZE
4237 #define SPI_START_TRANSFER(bp, port, ext_phy_addr) \
4238 bnx2x_cl45_write(bp, port, PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, \
4241 MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 1)
4243 /* Programs an image to DSP's flash via the SPI port*/
4244 static u8 bnx2x_sfx7101_flash_download(struct bnx2x *bp, u8 port,
4246 char data[], u32 size)
4248 const u16 num_trans = size/4; /* 4 bytes can be sent at a time */
4249 /* Doesn't include last trans!*/
4250 const u16 last_trans_size = size%4; /* Num bytes on last trans */
4251 u16 trans_cnt, byte_cnt;
4254 u16 code_started = 0;
4255 u16 image_revision1, image_revision2;
4258 DP(NETIF_MSG_LINK, "bnx2x_sfx7101_flash_download file_size=%d\n", size);
4260 if ((size-HEADER_SIZE) > MAX_APP_SIZE) {
4261 /* This very often will be the case, because the image is built
4262 with 160Kbytes size whereas the total image size must actually
4263 be 160Kbytes-RESERVED_SIZE */
4264 DP(NETIF_MSG_LINK, "Warning, file size was %d bytes "
4265 "truncated to %d bytes\n", size, MAX_APP_SIZE);
4266 size = MAX_APP_SIZE+HEADER_SIZE;
4268 DP(NETIF_MSG_LINK, "File version is %c%c\n", data[0x14e], data[0x14f]);
4269 DP(NETIF_MSG_LINK, " %c%c\n", data[0x150], data[0x151]);
4270 /* Put the DSP in download mode by setting FLASH_CFG[2] to 1
4271 and issuing a reset.*/
4273 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
4274 MISC_REGISTERS_GPIO_HIGH);
4276 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
4279 for (cnt = 0; cnt < 100; cnt++)
4282 /* Make sure we can access the DSP
4283 And it's in the correct mode (waiting for download) */
4285 bnx2x_cl45_read(bp, port,
4286 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4289 MDIO_PCS_REG_7101_DSP_ACCESS, &tmp);
4291 if (tmp != 0x000A) {
4292 DP(NETIF_MSG_LINK, "DSP is not in waiting on download mode. "
4293 "Expected 0x000A, read 0x%04X\n", tmp);
4294 DP(NETIF_MSG_LINK, "Download failed\n");
4298 /* Mux the SPI interface away from the internal processor */
4299 bnx2x_cl45_write(bp, port,
4300 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4303 MDIO_PCS_REG_7101_SPI_MUX, 1);
4305 /* Reset the SPI port */
4306 bnx2x_cl45_write(bp, port,
4307 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4310 MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 0);
4311 bnx2x_cl45_write(bp, port,
4312 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4315 MDIO_PCS_REG_7101_SPI_CTRL_ADDR,
4316 (1<<MDIO_PCS_REG_7101_SPI_RESET_BIT));
4317 bnx2x_cl45_write(bp, port,
4318 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4321 MDIO_PCS_REG_7101_SPI_CTRL_ADDR, 0);
4323 /* Erase the flash */
4324 bnx2x_cl45_write(bp, port,
4325 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4328 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4329 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
4331 bnx2x_cl45_write(bp, port,
4332 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4335 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
4338 SPI_START_TRANSFER(bp, port, ext_phy_addr);
4339 bnx2x_cl45_write(bp, port,
4340 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4343 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4344 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD);
4346 bnx2x_cl45_write(bp, port,
4347 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4350 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
4352 SPI_START_TRANSFER(bp, port, ext_phy_addr);
4354 /* Wait 10 seconds, the maximum time for the erase to complete */
4355 DP(NETIF_MSG_LINK, "Erasing flash, this takes 10 seconds...\n");
4356 for (cnt = 0; cnt < 1000; cnt++)
4359 DP(NETIF_MSG_LINK, "Downloading flash, please wait...\n");
4361 for (trans_cnt = 0; trans_cnt < num_trans; trans_cnt++) {
4362 bnx2x_cl45_write(bp, port,
4363 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4366 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4367 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
4369 bnx2x_cl45_write(bp, port,
4370 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4373 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
4375 SPI_START_TRANSFER(bp, port, ext_phy_addr);
4377 bnx2x_cl45_write(bp, port,
4378 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4381 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4382 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD);
4384 /* Bits 23-16 of address */
4385 bnx2x_cl45_write(bp, port,
4386 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4389 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4391 /* Bits 15-8 of address */
4392 bnx2x_cl45_write(bp, port,
4393 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4396 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4399 /* Bits 7-0 of address */
4400 bnx2x_cl45_write(bp, port,
4401 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4404 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4408 while (byte_cnt < 4 && data_index < size) {
4409 bnx2x_cl45_write(bp, port,
4410 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4413 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4414 data[data_index++]);
4418 bnx2x_cl45_write(bp, port,
4419 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4422 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
4425 SPI_START_TRANSFER(bp, port, ext_phy_addr);
4426 msleep(5); /* Wait 5 ms minimum between transs */
4428 /* Let the user know something's going on.*/
4429 /* a pacifier ever 4K */
4430 if ((data_index % 1023) == 0)
4431 DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size);
4434 DP(NETIF_MSG_LINK, "\n");
4435 /* Transfer the last block if there is data remaining */
4436 if (last_trans_size) {
4437 bnx2x_cl45_write(bp, port,
4438 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4441 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4442 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD);
4444 bnx2x_cl45_write(bp, port,
4445 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4448 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
4451 SPI_START_TRANSFER(bp, port, ext_phy_addr);
4453 bnx2x_cl45_write(bp, port,
4454 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4457 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4458 MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD);
4460 /* Bits 23-16 of address */
4461 bnx2x_cl45_write(bp, port,
4462 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4465 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4467 /* Bits 15-8 of address */
4468 bnx2x_cl45_write(bp, port,
4469 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4472 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4475 /* Bits 7-0 of address */
4476 bnx2x_cl45_write(bp, port,
4477 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4480 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4484 while (byte_cnt < last_trans_size && data_index < size) {
4485 /* Bits 7-0 of address */
4486 bnx2x_cl45_write(bp, port,
4487 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4490 MDIO_PCS_REG_7101_SPI_FIFO_ADDR,
4491 data[data_index++]);
4495 bnx2x_cl45_write(bp, port,
4496 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4499 MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR,
4502 SPI_START_TRANSFER(bp, port, ext_phy_addr);
4505 /* DSP Remove Download Mode */
4506 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0, MISC_REGISTERS_GPIO_LOW);
4508 bnx2x_sfx7101_sp_sw_reset(bp, port, ext_phy_addr);
4510 /* wait 0.5 sec to allow it to run */
4511 for (cnt = 0; cnt < 100; cnt++)
4516 for (cnt = 0; cnt < 100; cnt++)
4519 /* Check that the code is started. In case the download
4520 checksum failed, the code won't be started. */
4521 bnx2x_cl45_read(bp, port,
4522 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4525 MDIO_PCS_REG_7101_DSP_ACCESS,
4528 code_started = (tmp & (1<<4));
4529 if (!code_started) {
4530 DP(NETIF_MSG_LINK, "Download failed. Please check file.\n");
4534 /* Verify that the file revision is now equal to the image
4535 revision within the DSP */
4536 bnx2x_cl45_read(bp, port,
4537 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4540 MDIO_PMA_REG_7101_VER1,
4543 bnx2x_cl45_read(bp, port,
4544 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
4547 MDIO_PMA_REG_7101_VER2,
4550 if (data[0x14e] != (image_revision2&0xFF) ||
4551 data[0x14f] != ((image_revision2&0xFF00)>>8) ||
4552 data[0x150] != (image_revision1&0xFF) ||
4553 data[0x151] != ((image_revision1&0xFF00)>>8)) {
4554 DP(NETIF_MSG_LINK, "Download failed.\n");
4557 DP(NETIF_MSG_LINK, "Download %d%%\n", data_index/size);
4561 u8 bnx2x_flash_download(struct bnx2x *bp, u8 port, u32 ext_phy_config,
4562 u8 driver_loaded, char data[], u32 size)
4567 ext_phy_addr = ((ext_phy_config &
4568 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
4569 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
4571 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
4573 switch (ext_phy_type) {
4574 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
4575 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
4576 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
4577 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
4579 "Flash download not supported for this ext phy\n");
4582 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
4583 /* Take ext phy out of reset */
4585 bnx2x_turn_on_ef(bp, port, ext_phy_addr, ext_phy_type);
4586 rc = bnx2x_sfx7101_flash_download(bp, port, ext_phy_addr,
4589 bnx2x_turn_off_sf(bp);
4591 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
4592 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
4593 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
4595 DP(NETIF_MSG_LINK, "Invalid ext phy type\n");