1 /* bnx2.c: Broadcom NX2 network driver.
3 * Copyright (c) 2004-2008 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Written by: Michael Chan (mchan@broadcom.com)
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/bitops.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #include <linux/if_vlan.h>
39 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/zlib.h>
50 #include <linux/log2.h>
56 #define FW_BUF_SIZE 0x10000
58 #define DRV_MODULE_NAME "bnx2"
59 #define PFX DRV_MODULE_NAME ": "
60 #define DRV_MODULE_VERSION "1.9.0"
61 #define DRV_MODULE_RELDATE "Dec 16, 2008"
63 #define RUN_AT(x) (jiffies + (x))
65 /* Time in jiffies before concluding the transmitter is hung. */
66 #define TX_TIMEOUT (5*HZ)
68 static char version[] __devinitdata =
69 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
71 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
72 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
73 MODULE_LICENSE("GPL");
74 MODULE_VERSION(DRV_MODULE_VERSION);
76 static int disable_msi = 0;
78 module_param(disable_msi, int, 0);
79 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
95 /* indexed by board_t, above */
98 } board_info[] __devinitdata = {
99 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
100 { "HP NC370T Multifunction Gigabit Server Adapter" },
101 { "HP NC370i Multifunction Gigabit Server Adapter" },
102 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
103 { "HP NC370F Multifunction Gigabit Server Adapter" },
104 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
105 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
106 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
107 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
108 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
109 { "Broadcom NetXtreme II BCM5716 1000Base-SX" },
112 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
113 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
114 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
115 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
116 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
117 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
119 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
121 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
122 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
123 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
129 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
131 { PCI_VENDOR_ID_BROADCOM, 0x163b,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
133 { PCI_VENDOR_ID_BROADCOM, 0x163c,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716S },
138 static struct flash_spec flash_table[] =
140 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
141 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
143 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
144 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
145 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
147 /* Expansion entry 0001 */
148 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
149 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
150 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
152 /* Saifun SA25F010 (non-buffered flash) */
153 /* strap, cfg1, & write1 need updates */
154 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
155 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
156 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
157 "Non-buffered flash (128kB)"},
158 /* Saifun SA25F020 (non-buffered flash) */
159 /* strap, cfg1, & write1 need updates */
160 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
161 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
162 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
163 "Non-buffered flash (256kB)"},
164 /* Expansion entry 0100 */
165 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
166 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
167 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
169 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
170 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
171 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
172 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
173 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
174 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
175 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
176 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
177 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
178 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
179 /* Saifun SA25F005 (non-buffered flash) */
180 /* strap, cfg1, & write1 need updates */
181 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
182 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
183 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
184 "Non-buffered flash (64kB)"},
186 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
187 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
188 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
190 /* Expansion entry 1001 */
191 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
192 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
193 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
195 /* Expansion entry 1010 */
196 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
197 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
198 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
200 /* ATMEL AT45DB011B (buffered flash) */
201 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
202 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
203 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
204 "Buffered flash (128kB)"},
205 /* Expansion entry 1100 */
206 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
207 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
208 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
210 /* Expansion entry 1101 */
211 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
212 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
213 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
215 /* Ateml Expansion entry 1110 */
216 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
217 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
218 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
219 "Entry 1110 (Atmel)"},
220 /* ATMEL AT45DB021B (buffered flash) */
221 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
222 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
223 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
224 "Buffered flash (256kB)"},
227 static struct flash_spec flash_5709 = {
228 .flags = BNX2_NV_BUFFERED,
229 .page_bits = BCM5709_FLASH_PAGE_BITS,
230 .page_size = BCM5709_FLASH_PAGE_SIZE,
231 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
232 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
233 .name = "5709 Buffered flash (256kB)",
236 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
238 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
244 /* The ring uses 256 indices for 255 entries, one of them
245 * needs to be skipped.
247 diff = txr->tx_prod - txr->tx_cons;
248 if (unlikely(diff >= TX_DESC_CNT)) {
250 if (diff == TX_DESC_CNT)
251 diff = MAX_TX_DESC_CNT;
253 return (bp->tx_ring_size - diff);
257 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
261 spin_lock_bh(&bp->indirect_lock);
262 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
263 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
264 spin_unlock_bh(&bp->indirect_lock);
269 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
271 spin_lock_bh(&bp->indirect_lock);
272 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
273 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
274 spin_unlock_bh(&bp->indirect_lock);
278 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
280 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
284 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
286 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
290 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
293 spin_lock_bh(&bp->indirect_lock);
294 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
297 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
298 REG_WR(bp, BNX2_CTX_CTX_CTRL,
299 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
300 for (i = 0; i < 5; i++) {
301 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
302 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
307 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
308 REG_WR(bp, BNX2_CTX_DATA, val);
310 spin_unlock_bh(&bp->indirect_lock);
314 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
319 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
320 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
321 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
323 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
324 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
329 val1 = (bp->phy_addr << 21) | (reg << 16) |
330 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
331 BNX2_EMAC_MDIO_COMM_START_BUSY;
332 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
334 for (i = 0; i < 50; i++) {
337 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
338 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
341 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
342 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
348 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
357 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
358 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
359 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
361 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
362 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
371 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
376 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
377 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
378 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
380 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
381 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
386 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
387 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
388 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
389 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
391 for (i = 0; i < 50; i++) {
394 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
395 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
401 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
406 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
407 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
408 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
410 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
411 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
420 bnx2_disable_int(struct bnx2 *bp)
423 struct bnx2_napi *bnapi;
425 for (i = 0; i < bp->irq_nvecs; i++) {
426 bnapi = &bp->bnx2_napi[i];
427 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
428 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
430 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
434 bnx2_enable_int(struct bnx2 *bp)
437 struct bnx2_napi *bnapi;
439 for (i = 0; i < bp->irq_nvecs; i++) {
440 bnapi = &bp->bnx2_napi[i];
442 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
443 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
444 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
445 bnapi->last_status_idx);
447 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
448 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
449 bnapi->last_status_idx);
451 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
455 bnx2_disable_int_sync(struct bnx2 *bp)
459 atomic_inc(&bp->intr_sem);
460 bnx2_disable_int(bp);
461 for (i = 0; i < bp->irq_nvecs; i++)
462 synchronize_irq(bp->irq_tbl[i].vector);
466 bnx2_napi_disable(struct bnx2 *bp)
470 for (i = 0; i < bp->irq_nvecs; i++)
471 napi_disable(&bp->bnx2_napi[i].napi);
475 bnx2_napi_enable(struct bnx2 *bp)
479 for (i = 0; i < bp->irq_nvecs; i++)
480 napi_enable(&bp->bnx2_napi[i].napi);
484 bnx2_netif_stop(struct bnx2 *bp)
486 bnx2_disable_int_sync(bp);
487 if (netif_running(bp->dev)) {
488 bnx2_napi_disable(bp);
489 netif_tx_disable(bp->dev);
490 bp->dev->trans_start = jiffies; /* prevent tx timeout */
495 bnx2_netif_start(struct bnx2 *bp)
497 if (atomic_dec_and_test(&bp->intr_sem)) {
498 if (netif_running(bp->dev)) {
499 netif_tx_wake_all_queues(bp->dev);
500 bnx2_napi_enable(bp);
507 bnx2_free_tx_mem(struct bnx2 *bp)
511 for (i = 0; i < bp->num_tx_rings; i++) {
512 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
513 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
515 if (txr->tx_desc_ring) {
516 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
518 txr->tx_desc_mapping);
519 txr->tx_desc_ring = NULL;
521 kfree(txr->tx_buf_ring);
522 txr->tx_buf_ring = NULL;
527 bnx2_free_rx_mem(struct bnx2 *bp)
531 for (i = 0; i < bp->num_rx_rings; i++) {
532 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
533 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
536 for (j = 0; j < bp->rx_max_ring; j++) {
537 if (rxr->rx_desc_ring[j])
538 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
539 rxr->rx_desc_ring[j],
540 rxr->rx_desc_mapping[j]);
541 rxr->rx_desc_ring[j] = NULL;
543 if (rxr->rx_buf_ring)
544 vfree(rxr->rx_buf_ring);
545 rxr->rx_buf_ring = NULL;
547 for (j = 0; j < bp->rx_max_pg_ring; j++) {
548 if (rxr->rx_pg_desc_ring[j])
549 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
550 rxr->rx_pg_desc_ring[j],
551 rxr->rx_pg_desc_mapping[j]);
552 rxr->rx_pg_desc_ring[j] = NULL;
555 vfree(rxr->rx_pg_ring);
556 rxr->rx_pg_ring = NULL;
561 bnx2_alloc_tx_mem(struct bnx2 *bp)
565 for (i = 0; i < bp->num_tx_rings; i++) {
566 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
567 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
569 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
570 if (txr->tx_buf_ring == NULL)
574 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
575 &txr->tx_desc_mapping);
576 if (txr->tx_desc_ring == NULL)
583 bnx2_alloc_rx_mem(struct bnx2 *bp)
587 for (i = 0; i < bp->num_rx_rings; i++) {
588 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
589 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
593 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
594 if (rxr->rx_buf_ring == NULL)
597 memset(rxr->rx_buf_ring, 0,
598 SW_RXBD_RING_SIZE * bp->rx_max_ring);
600 for (j = 0; j < bp->rx_max_ring; j++) {
601 rxr->rx_desc_ring[j] =
602 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
603 &rxr->rx_desc_mapping[j]);
604 if (rxr->rx_desc_ring[j] == NULL)
609 if (bp->rx_pg_ring_size) {
610 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
612 if (rxr->rx_pg_ring == NULL)
615 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
619 for (j = 0; j < bp->rx_max_pg_ring; j++) {
620 rxr->rx_pg_desc_ring[j] =
621 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
622 &rxr->rx_pg_desc_mapping[j]);
623 if (rxr->rx_pg_desc_ring[j] == NULL)
632 bnx2_free_mem(struct bnx2 *bp)
635 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
637 bnx2_free_tx_mem(bp);
638 bnx2_free_rx_mem(bp);
640 for (i = 0; i < bp->ctx_pages; i++) {
641 if (bp->ctx_blk[i]) {
642 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
644 bp->ctx_blk_mapping[i]);
645 bp->ctx_blk[i] = NULL;
648 if (bnapi->status_blk.msi) {
649 pci_free_consistent(bp->pdev, bp->status_stats_size,
650 bnapi->status_blk.msi,
651 bp->status_blk_mapping);
652 bnapi->status_blk.msi = NULL;
653 bp->stats_blk = NULL;
658 bnx2_alloc_mem(struct bnx2 *bp)
660 int i, status_blk_size, err;
661 struct bnx2_napi *bnapi;
664 /* Combine status and statistics blocks into one allocation. */
665 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
666 if (bp->flags & BNX2_FLAG_MSIX_CAP)
667 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
668 BNX2_SBLK_MSIX_ALIGN_SIZE);
669 bp->status_stats_size = status_blk_size +
670 sizeof(struct statistics_block);
672 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
673 &bp->status_blk_mapping);
674 if (status_blk == NULL)
677 memset(status_blk, 0, bp->status_stats_size);
679 bnapi = &bp->bnx2_napi[0];
680 bnapi->status_blk.msi = status_blk;
681 bnapi->hw_tx_cons_ptr =
682 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
683 bnapi->hw_rx_cons_ptr =
684 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
685 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
686 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
687 struct status_block_msix *sblk;
689 bnapi = &bp->bnx2_napi[i];
691 sblk = (void *) (status_blk +
692 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
693 bnapi->status_blk.msix = sblk;
694 bnapi->hw_tx_cons_ptr =
695 &sblk->status_tx_quick_consumer_index;
696 bnapi->hw_rx_cons_ptr =
697 &sblk->status_rx_quick_consumer_index;
698 bnapi->int_num = i << 24;
702 bp->stats_blk = status_blk + status_blk_size;
704 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
706 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
707 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
708 if (bp->ctx_pages == 0)
710 for (i = 0; i < bp->ctx_pages; i++) {
711 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
713 &bp->ctx_blk_mapping[i]);
714 if (bp->ctx_blk[i] == NULL)
719 err = bnx2_alloc_rx_mem(bp);
723 err = bnx2_alloc_tx_mem(bp);
735 bnx2_report_fw_link(struct bnx2 *bp)
737 u32 fw_link_status = 0;
739 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
745 switch (bp->line_speed) {
747 if (bp->duplex == DUPLEX_HALF)
748 fw_link_status = BNX2_LINK_STATUS_10HALF;
750 fw_link_status = BNX2_LINK_STATUS_10FULL;
753 if (bp->duplex == DUPLEX_HALF)
754 fw_link_status = BNX2_LINK_STATUS_100HALF;
756 fw_link_status = BNX2_LINK_STATUS_100FULL;
759 if (bp->duplex == DUPLEX_HALF)
760 fw_link_status = BNX2_LINK_STATUS_1000HALF;
762 fw_link_status = BNX2_LINK_STATUS_1000FULL;
765 if (bp->duplex == DUPLEX_HALF)
766 fw_link_status = BNX2_LINK_STATUS_2500HALF;
768 fw_link_status = BNX2_LINK_STATUS_2500FULL;
772 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
775 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
777 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
778 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
780 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
781 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
782 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
784 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
788 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
790 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
794 bnx2_xceiver_str(struct bnx2 *bp)
796 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
797 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
802 bnx2_report_link(struct bnx2 *bp)
805 netif_carrier_on(bp->dev);
806 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
807 bnx2_xceiver_str(bp));
809 printk("%d Mbps ", bp->line_speed);
811 if (bp->duplex == DUPLEX_FULL)
812 printk("full duplex");
814 printk("half duplex");
817 if (bp->flow_ctrl & FLOW_CTRL_RX) {
818 printk(", receive ");
819 if (bp->flow_ctrl & FLOW_CTRL_TX)
820 printk("& transmit ");
823 printk(", transmit ");
825 printk("flow control ON");
830 netif_carrier_off(bp->dev);
831 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
832 bnx2_xceiver_str(bp));
835 bnx2_report_fw_link(bp);
839 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
841 u32 local_adv, remote_adv;
844 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
845 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
847 if (bp->duplex == DUPLEX_FULL) {
848 bp->flow_ctrl = bp->req_flow_ctrl;
853 if (bp->duplex != DUPLEX_FULL) {
857 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
858 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
861 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
862 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
863 bp->flow_ctrl |= FLOW_CTRL_TX;
864 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
865 bp->flow_ctrl |= FLOW_CTRL_RX;
869 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
870 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
872 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
873 u32 new_local_adv = 0;
874 u32 new_remote_adv = 0;
876 if (local_adv & ADVERTISE_1000XPAUSE)
877 new_local_adv |= ADVERTISE_PAUSE_CAP;
878 if (local_adv & ADVERTISE_1000XPSE_ASYM)
879 new_local_adv |= ADVERTISE_PAUSE_ASYM;
880 if (remote_adv & ADVERTISE_1000XPAUSE)
881 new_remote_adv |= ADVERTISE_PAUSE_CAP;
882 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
883 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
885 local_adv = new_local_adv;
886 remote_adv = new_remote_adv;
889 /* See Table 28B-3 of 802.3ab-1999 spec. */
890 if (local_adv & ADVERTISE_PAUSE_CAP) {
891 if(local_adv & ADVERTISE_PAUSE_ASYM) {
892 if (remote_adv & ADVERTISE_PAUSE_CAP) {
893 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
895 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
896 bp->flow_ctrl = FLOW_CTRL_RX;
900 if (remote_adv & ADVERTISE_PAUSE_CAP) {
901 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
905 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
906 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
907 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
909 bp->flow_ctrl = FLOW_CTRL_TX;
915 bnx2_5709s_linkup(struct bnx2 *bp)
921 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
922 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
923 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
925 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
926 bp->line_speed = bp->req_line_speed;
927 bp->duplex = bp->req_duplex;
930 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
932 case MII_BNX2_GP_TOP_AN_SPEED_10:
933 bp->line_speed = SPEED_10;
935 case MII_BNX2_GP_TOP_AN_SPEED_100:
936 bp->line_speed = SPEED_100;
938 case MII_BNX2_GP_TOP_AN_SPEED_1G:
939 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
940 bp->line_speed = SPEED_1000;
942 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
943 bp->line_speed = SPEED_2500;
946 if (val & MII_BNX2_GP_TOP_AN_FD)
947 bp->duplex = DUPLEX_FULL;
949 bp->duplex = DUPLEX_HALF;
954 bnx2_5708s_linkup(struct bnx2 *bp)
959 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
960 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
961 case BCM5708S_1000X_STAT1_SPEED_10:
962 bp->line_speed = SPEED_10;
964 case BCM5708S_1000X_STAT1_SPEED_100:
965 bp->line_speed = SPEED_100;
967 case BCM5708S_1000X_STAT1_SPEED_1G:
968 bp->line_speed = SPEED_1000;
970 case BCM5708S_1000X_STAT1_SPEED_2G5:
971 bp->line_speed = SPEED_2500;
974 if (val & BCM5708S_1000X_STAT1_FD)
975 bp->duplex = DUPLEX_FULL;
977 bp->duplex = DUPLEX_HALF;
983 bnx2_5706s_linkup(struct bnx2 *bp)
985 u32 bmcr, local_adv, remote_adv, common;
988 bp->line_speed = SPEED_1000;
990 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
991 if (bmcr & BMCR_FULLDPLX) {
992 bp->duplex = DUPLEX_FULL;
995 bp->duplex = DUPLEX_HALF;
998 if (!(bmcr & BMCR_ANENABLE)) {
1002 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1003 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1005 common = local_adv & remote_adv;
1006 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1008 if (common & ADVERTISE_1000XFULL) {
1009 bp->duplex = DUPLEX_FULL;
1012 bp->duplex = DUPLEX_HALF;
1020 bnx2_copper_linkup(struct bnx2 *bp)
1024 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1025 if (bmcr & BMCR_ANENABLE) {
1026 u32 local_adv, remote_adv, common;
1028 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1029 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1031 common = local_adv & (remote_adv >> 2);
1032 if (common & ADVERTISE_1000FULL) {
1033 bp->line_speed = SPEED_1000;
1034 bp->duplex = DUPLEX_FULL;
1036 else if (common & ADVERTISE_1000HALF) {
1037 bp->line_speed = SPEED_1000;
1038 bp->duplex = DUPLEX_HALF;
1041 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1042 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1044 common = local_adv & remote_adv;
1045 if (common & ADVERTISE_100FULL) {
1046 bp->line_speed = SPEED_100;
1047 bp->duplex = DUPLEX_FULL;
1049 else if (common & ADVERTISE_100HALF) {
1050 bp->line_speed = SPEED_100;
1051 bp->duplex = DUPLEX_HALF;
1053 else if (common & ADVERTISE_10FULL) {
1054 bp->line_speed = SPEED_10;
1055 bp->duplex = DUPLEX_FULL;
1057 else if (common & ADVERTISE_10HALF) {
1058 bp->line_speed = SPEED_10;
1059 bp->duplex = DUPLEX_HALF;
1068 if (bmcr & BMCR_SPEED100) {
1069 bp->line_speed = SPEED_100;
1072 bp->line_speed = SPEED_10;
1074 if (bmcr & BMCR_FULLDPLX) {
1075 bp->duplex = DUPLEX_FULL;
1078 bp->duplex = DUPLEX_HALF;
1086 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1088 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1090 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1091 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1094 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1095 u32 lo_water, hi_water;
1097 if (bp->flow_ctrl & FLOW_CTRL_TX)
1098 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1100 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1101 if (lo_water >= bp->rx_ring_size)
1104 hi_water = bp->rx_ring_size / 4;
1106 if (hi_water <= lo_water)
1109 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1110 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1114 else if (hi_water == 0)
1116 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1118 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1122 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1127 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1130 bnx2_init_rx_context(bp, cid);
1135 bnx2_set_mac_link(struct bnx2 *bp)
1139 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1140 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1141 (bp->duplex == DUPLEX_HALF)) {
1142 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1145 /* Configure the EMAC mode register. */
1146 val = REG_RD(bp, BNX2_EMAC_MODE);
1148 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1149 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1150 BNX2_EMAC_MODE_25G_MODE);
1153 switch (bp->line_speed) {
1155 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1156 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1161 val |= BNX2_EMAC_MODE_PORT_MII;
1164 val |= BNX2_EMAC_MODE_25G_MODE;
1167 val |= BNX2_EMAC_MODE_PORT_GMII;
1172 val |= BNX2_EMAC_MODE_PORT_GMII;
1175 /* Set the MAC to operate in the appropriate duplex mode. */
1176 if (bp->duplex == DUPLEX_HALF)
1177 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1178 REG_WR(bp, BNX2_EMAC_MODE, val);
1180 /* Enable/disable rx PAUSE. */
1181 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1183 if (bp->flow_ctrl & FLOW_CTRL_RX)
1184 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1185 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1187 /* Enable/disable tx PAUSE. */
1188 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1189 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1191 if (bp->flow_ctrl & FLOW_CTRL_TX)
1192 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1193 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1195 /* Acknowledge the interrupt. */
1196 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1198 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1199 bnx2_init_all_rx_contexts(bp);
1203 bnx2_enable_bmsr1(struct bnx2 *bp)
1205 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1206 (CHIP_NUM(bp) == CHIP_NUM_5709))
1207 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1208 MII_BNX2_BLK_ADDR_GP_STATUS);
1212 bnx2_disable_bmsr1(struct bnx2 *bp)
1214 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1215 (CHIP_NUM(bp) == CHIP_NUM_5709))
1216 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1217 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1221 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1226 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1229 if (bp->autoneg & AUTONEG_SPEED)
1230 bp->advertising |= ADVERTISED_2500baseX_Full;
1232 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1233 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1235 bnx2_read_phy(bp, bp->mii_up1, &up1);
1236 if (!(up1 & BCM5708S_UP1_2G5)) {
1237 up1 |= BCM5708S_UP1_2G5;
1238 bnx2_write_phy(bp, bp->mii_up1, up1);
1242 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1243 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1244 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1250 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1255 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1258 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1259 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1261 bnx2_read_phy(bp, bp->mii_up1, &up1);
1262 if (up1 & BCM5708S_UP1_2G5) {
1263 up1 &= ~BCM5708S_UP1_2G5;
1264 bnx2_write_phy(bp, bp->mii_up1, up1);
1268 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1269 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1270 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1276 bnx2_enable_forced_2g5(struct bnx2 *bp)
1280 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1283 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1286 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1287 MII_BNX2_BLK_ADDR_SERDES_DIG);
1288 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1289 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1290 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1291 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1293 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1294 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1295 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1297 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1298 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1299 bmcr |= BCM5708S_BMCR_FORCE_2500;
1302 if (bp->autoneg & AUTONEG_SPEED) {
1303 bmcr &= ~BMCR_ANENABLE;
1304 if (bp->req_duplex == DUPLEX_FULL)
1305 bmcr |= BMCR_FULLDPLX;
1307 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1311 bnx2_disable_forced_2g5(struct bnx2 *bp)
1315 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1318 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1321 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1322 MII_BNX2_BLK_ADDR_SERDES_DIG);
1323 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1324 val &= ~MII_BNX2_SD_MISC1_FORCE;
1325 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1327 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1328 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1329 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1331 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1332 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1333 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1336 if (bp->autoneg & AUTONEG_SPEED)
1337 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1338 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1342 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1346 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1347 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1349 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1351 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1355 bnx2_set_link(struct bnx2 *bp)
1360 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1365 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1368 link_up = bp->link_up;
1370 bnx2_enable_bmsr1(bp);
1371 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1372 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1373 bnx2_disable_bmsr1(bp);
1375 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1376 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1379 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1380 bnx2_5706s_force_link_dn(bp, 0);
1381 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1383 val = REG_RD(bp, BNX2_EMAC_STATUS);
1385 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1386 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1387 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1389 if ((val & BNX2_EMAC_STATUS_LINK) &&
1390 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1391 bmsr |= BMSR_LSTATUS;
1393 bmsr &= ~BMSR_LSTATUS;
1396 if (bmsr & BMSR_LSTATUS) {
1399 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1400 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1401 bnx2_5706s_linkup(bp);
1402 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1403 bnx2_5708s_linkup(bp);
1404 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1405 bnx2_5709s_linkup(bp);
1408 bnx2_copper_linkup(bp);
1410 bnx2_resolve_flow_ctrl(bp);
1413 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1414 (bp->autoneg & AUTONEG_SPEED))
1415 bnx2_disable_forced_2g5(bp);
1417 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1420 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1421 bmcr |= BMCR_ANENABLE;
1422 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1424 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1429 if (bp->link_up != link_up) {
1430 bnx2_report_link(bp);
1433 bnx2_set_mac_link(bp);
1439 bnx2_reset_phy(struct bnx2 *bp)
1444 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1446 #define PHY_RESET_MAX_WAIT 100
1447 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1450 bnx2_read_phy(bp, bp->mii_bmcr, ®);
1451 if (!(reg & BMCR_RESET)) {
1456 if (i == PHY_RESET_MAX_WAIT) {
1463 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1467 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1468 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1470 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1471 adv = ADVERTISE_1000XPAUSE;
1474 adv = ADVERTISE_PAUSE_CAP;
1477 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1478 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1479 adv = ADVERTISE_1000XPSE_ASYM;
1482 adv = ADVERTISE_PAUSE_ASYM;
1485 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1486 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1487 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1490 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1496 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1499 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1500 __releases(&bp->phy_lock)
1501 __acquires(&bp->phy_lock)
1503 u32 speed_arg = 0, pause_adv;
1505 pause_adv = bnx2_phy_get_pause_adv(bp);
1507 if (bp->autoneg & AUTONEG_SPEED) {
1508 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1509 if (bp->advertising & ADVERTISED_10baseT_Half)
1510 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1511 if (bp->advertising & ADVERTISED_10baseT_Full)
1512 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1513 if (bp->advertising & ADVERTISED_100baseT_Half)
1514 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1515 if (bp->advertising & ADVERTISED_100baseT_Full)
1516 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1517 if (bp->advertising & ADVERTISED_1000baseT_Full)
1518 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1519 if (bp->advertising & ADVERTISED_2500baseX_Full)
1520 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1522 if (bp->req_line_speed == SPEED_2500)
1523 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1524 else if (bp->req_line_speed == SPEED_1000)
1525 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1526 else if (bp->req_line_speed == SPEED_100) {
1527 if (bp->req_duplex == DUPLEX_FULL)
1528 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1530 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1531 } else if (bp->req_line_speed == SPEED_10) {
1532 if (bp->req_duplex == DUPLEX_FULL)
1533 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1535 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1539 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1540 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1541 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1542 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1544 if (port == PORT_TP)
1545 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1546 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1548 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1550 spin_unlock_bh(&bp->phy_lock);
1551 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1552 spin_lock_bh(&bp->phy_lock);
1558 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1559 __releases(&bp->phy_lock)
1560 __acquires(&bp->phy_lock)
1565 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1566 return (bnx2_setup_remote_phy(bp, port));
1568 if (!(bp->autoneg & AUTONEG_SPEED)) {
1570 int force_link_down = 0;
1572 if (bp->req_line_speed == SPEED_2500) {
1573 if (!bnx2_test_and_enable_2g5(bp))
1574 force_link_down = 1;
1575 } else if (bp->req_line_speed == SPEED_1000) {
1576 if (bnx2_test_and_disable_2g5(bp))
1577 force_link_down = 1;
1579 bnx2_read_phy(bp, bp->mii_adv, &adv);
1580 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1582 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1583 new_bmcr = bmcr & ~BMCR_ANENABLE;
1584 new_bmcr |= BMCR_SPEED1000;
1586 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1587 if (bp->req_line_speed == SPEED_2500)
1588 bnx2_enable_forced_2g5(bp);
1589 else if (bp->req_line_speed == SPEED_1000) {
1590 bnx2_disable_forced_2g5(bp);
1591 new_bmcr &= ~0x2000;
1594 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1595 if (bp->req_line_speed == SPEED_2500)
1596 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1598 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1601 if (bp->req_duplex == DUPLEX_FULL) {
1602 adv |= ADVERTISE_1000XFULL;
1603 new_bmcr |= BMCR_FULLDPLX;
1606 adv |= ADVERTISE_1000XHALF;
1607 new_bmcr &= ~BMCR_FULLDPLX;
1609 if ((new_bmcr != bmcr) || (force_link_down)) {
1610 /* Force a link down visible on the other side */
1612 bnx2_write_phy(bp, bp->mii_adv, adv &
1613 ~(ADVERTISE_1000XFULL |
1614 ADVERTISE_1000XHALF));
1615 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1616 BMCR_ANRESTART | BMCR_ANENABLE);
1619 netif_carrier_off(bp->dev);
1620 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1621 bnx2_report_link(bp);
1623 bnx2_write_phy(bp, bp->mii_adv, adv);
1624 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1626 bnx2_resolve_flow_ctrl(bp);
1627 bnx2_set_mac_link(bp);
1632 bnx2_test_and_enable_2g5(bp);
1634 if (bp->advertising & ADVERTISED_1000baseT_Full)
1635 new_adv |= ADVERTISE_1000XFULL;
1637 new_adv |= bnx2_phy_get_pause_adv(bp);
1639 bnx2_read_phy(bp, bp->mii_adv, &adv);
1640 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1642 bp->serdes_an_pending = 0;
1643 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1644 /* Force a link down visible on the other side */
1646 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1647 spin_unlock_bh(&bp->phy_lock);
1649 spin_lock_bh(&bp->phy_lock);
1652 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1653 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1655 /* Speed up link-up time when the link partner
1656 * does not autonegotiate which is very common
1657 * in blade servers. Some blade servers use
1658 * IPMI for kerboard input and it's important
1659 * to minimize link disruptions. Autoneg. involves
1660 * exchanging base pages plus 3 next pages and
1661 * normally completes in about 120 msec.
1663 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
1664 bp->serdes_an_pending = 1;
1665 mod_timer(&bp->timer, jiffies + bp->current_interval);
1667 bnx2_resolve_flow_ctrl(bp);
1668 bnx2_set_mac_link(bp);
1674 #define ETHTOOL_ALL_FIBRE_SPEED \
1675 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1676 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1677 (ADVERTISED_1000baseT_Full)
1679 #define ETHTOOL_ALL_COPPER_SPEED \
1680 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1681 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1682 ADVERTISED_1000baseT_Full)
1684 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1685 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1687 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1690 bnx2_set_default_remote_link(struct bnx2 *bp)
1694 if (bp->phy_port == PORT_TP)
1695 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1697 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1699 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1700 bp->req_line_speed = 0;
1701 bp->autoneg |= AUTONEG_SPEED;
1702 bp->advertising = ADVERTISED_Autoneg;
1703 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1704 bp->advertising |= ADVERTISED_10baseT_Half;
1705 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1706 bp->advertising |= ADVERTISED_10baseT_Full;
1707 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1708 bp->advertising |= ADVERTISED_100baseT_Half;
1709 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1710 bp->advertising |= ADVERTISED_100baseT_Full;
1711 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1712 bp->advertising |= ADVERTISED_1000baseT_Full;
1713 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1714 bp->advertising |= ADVERTISED_2500baseX_Full;
1717 bp->advertising = 0;
1718 bp->req_duplex = DUPLEX_FULL;
1719 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1720 bp->req_line_speed = SPEED_10;
1721 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1722 bp->req_duplex = DUPLEX_HALF;
1724 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1725 bp->req_line_speed = SPEED_100;
1726 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1727 bp->req_duplex = DUPLEX_HALF;
1729 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1730 bp->req_line_speed = SPEED_1000;
1731 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1732 bp->req_line_speed = SPEED_2500;
1737 bnx2_set_default_link(struct bnx2 *bp)
1739 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1740 bnx2_set_default_remote_link(bp);
1744 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1745 bp->req_line_speed = 0;
1746 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1749 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1751 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1752 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1753 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1755 bp->req_line_speed = bp->line_speed = SPEED_1000;
1756 bp->req_duplex = DUPLEX_FULL;
1759 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1763 bnx2_send_heart_beat(struct bnx2 *bp)
1768 spin_lock(&bp->indirect_lock);
1769 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1770 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1771 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1772 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1773 spin_unlock(&bp->indirect_lock);
1777 bnx2_remote_phy_event(struct bnx2 *bp)
1780 u8 link_up = bp->link_up;
1783 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1785 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1786 bnx2_send_heart_beat(bp);
1788 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1790 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1796 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1797 bp->duplex = DUPLEX_FULL;
1799 case BNX2_LINK_STATUS_10HALF:
1800 bp->duplex = DUPLEX_HALF;
1801 case BNX2_LINK_STATUS_10FULL:
1802 bp->line_speed = SPEED_10;
1804 case BNX2_LINK_STATUS_100HALF:
1805 bp->duplex = DUPLEX_HALF;
1806 case BNX2_LINK_STATUS_100BASE_T4:
1807 case BNX2_LINK_STATUS_100FULL:
1808 bp->line_speed = SPEED_100;
1810 case BNX2_LINK_STATUS_1000HALF:
1811 bp->duplex = DUPLEX_HALF;
1812 case BNX2_LINK_STATUS_1000FULL:
1813 bp->line_speed = SPEED_1000;
1815 case BNX2_LINK_STATUS_2500HALF:
1816 bp->duplex = DUPLEX_HALF;
1817 case BNX2_LINK_STATUS_2500FULL:
1818 bp->line_speed = SPEED_2500;
1826 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1827 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1828 if (bp->duplex == DUPLEX_FULL)
1829 bp->flow_ctrl = bp->req_flow_ctrl;
1831 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1832 bp->flow_ctrl |= FLOW_CTRL_TX;
1833 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1834 bp->flow_ctrl |= FLOW_CTRL_RX;
1837 old_port = bp->phy_port;
1838 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1839 bp->phy_port = PORT_FIBRE;
1841 bp->phy_port = PORT_TP;
1843 if (old_port != bp->phy_port)
1844 bnx2_set_default_link(bp);
1847 if (bp->link_up != link_up)
1848 bnx2_report_link(bp);
1850 bnx2_set_mac_link(bp);
1854 bnx2_set_remote_link(struct bnx2 *bp)
1858 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
1860 case BNX2_FW_EVT_CODE_LINK_EVENT:
1861 bnx2_remote_phy_event(bp);
1863 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1865 bnx2_send_heart_beat(bp);
1872 bnx2_setup_copper_phy(struct bnx2 *bp)
1873 __releases(&bp->phy_lock)
1874 __acquires(&bp->phy_lock)
1879 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1881 if (bp->autoneg & AUTONEG_SPEED) {
1882 u32 adv_reg, adv1000_reg;
1883 u32 new_adv_reg = 0;
1884 u32 new_adv1000_reg = 0;
1886 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1887 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1888 ADVERTISE_PAUSE_ASYM);
1890 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1891 adv1000_reg &= PHY_ALL_1000_SPEED;
1893 if (bp->advertising & ADVERTISED_10baseT_Half)
1894 new_adv_reg |= ADVERTISE_10HALF;
1895 if (bp->advertising & ADVERTISED_10baseT_Full)
1896 new_adv_reg |= ADVERTISE_10FULL;
1897 if (bp->advertising & ADVERTISED_100baseT_Half)
1898 new_adv_reg |= ADVERTISE_100HALF;
1899 if (bp->advertising & ADVERTISED_100baseT_Full)
1900 new_adv_reg |= ADVERTISE_100FULL;
1901 if (bp->advertising & ADVERTISED_1000baseT_Full)
1902 new_adv1000_reg |= ADVERTISE_1000FULL;
1904 new_adv_reg |= ADVERTISE_CSMA;
1906 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1908 if ((adv1000_reg != new_adv1000_reg) ||
1909 (adv_reg != new_adv_reg) ||
1910 ((bmcr & BMCR_ANENABLE) == 0)) {
1912 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1913 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1914 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1917 else if (bp->link_up) {
1918 /* Flow ctrl may have changed from auto to forced */
1919 /* or vice-versa. */
1921 bnx2_resolve_flow_ctrl(bp);
1922 bnx2_set_mac_link(bp);
1928 if (bp->req_line_speed == SPEED_100) {
1929 new_bmcr |= BMCR_SPEED100;
1931 if (bp->req_duplex == DUPLEX_FULL) {
1932 new_bmcr |= BMCR_FULLDPLX;
1934 if (new_bmcr != bmcr) {
1937 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1938 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1940 if (bmsr & BMSR_LSTATUS) {
1941 /* Force link down */
1942 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1943 spin_unlock_bh(&bp->phy_lock);
1945 spin_lock_bh(&bp->phy_lock);
1947 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1948 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1951 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1953 /* Normally, the new speed is setup after the link has
1954 * gone down and up again. In some cases, link will not go
1955 * down so we need to set up the new speed here.
1957 if (bmsr & BMSR_LSTATUS) {
1958 bp->line_speed = bp->req_line_speed;
1959 bp->duplex = bp->req_duplex;
1960 bnx2_resolve_flow_ctrl(bp);
1961 bnx2_set_mac_link(bp);
1964 bnx2_resolve_flow_ctrl(bp);
1965 bnx2_set_mac_link(bp);
1971 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1972 __releases(&bp->phy_lock)
1973 __acquires(&bp->phy_lock)
1975 if (bp->loopback == MAC_LOOPBACK)
1978 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1979 return (bnx2_setup_serdes_phy(bp, port));
1982 return (bnx2_setup_copper_phy(bp));
1987 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
1991 bp->mii_bmcr = MII_BMCR + 0x10;
1992 bp->mii_bmsr = MII_BMSR + 0x10;
1993 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1994 bp->mii_adv = MII_ADVERTISE + 0x10;
1995 bp->mii_lpa = MII_LPA + 0x10;
1996 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1998 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1999 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
2001 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2005 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
2007 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
2008 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
2009 val |= MII_BNX2_SD_1000XCTL1_FIBER;
2010 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2012 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2013 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2014 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2015 val |= BCM5708S_UP1_2G5;
2017 val &= ~BCM5708S_UP1_2G5;
2018 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2020 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2021 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2022 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2023 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2025 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2027 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2028 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2029 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2031 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2037 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2044 bp->mii_up1 = BCM5708S_UP1;
2046 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2047 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2048 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2050 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2051 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2052 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2054 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2055 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2056 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2058 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2059 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2060 val |= BCM5708S_UP1_2G5;
2061 bnx2_write_phy(bp, BCM5708S_UP1, val);
2064 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2065 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2066 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2067 /* increase tx signal amplitude */
2068 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2069 BCM5708S_BLK_ADDR_TX_MISC);
2070 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2071 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2072 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2073 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2076 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2077 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2082 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2083 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2084 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2085 BCM5708S_BLK_ADDR_TX_MISC);
2086 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2087 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2088 BCM5708S_BLK_ADDR_DIG);
2095 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2100 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2102 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2103 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2105 if (bp->dev->mtu > 1500) {
2108 /* Set extended packet length bit */
2109 bnx2_write_phy(bp, 0x18, 0x7);
2110 bnx2_read_phy(bp, 0x18, &val);
2111 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2113 bnx2_write_phy(bp, 0x1c, 0x6c00);
2114 bnx2_read_phy(bp, 0x1c, &val);
2115 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2120 bnx2_write_phy(bp, 0x18, 0x7);
2121 bnx2_read_phy(bp, 0x18, &val);
2122 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2124 bnx2_write_phy(bp, 0x1c, 0x6c00);
2125 bnx2_read_phy(bp, 0x1c, &val);
2126 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2133 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2140 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2141 bnx2_write_phy(bp, 0x18, 0x0c00);
2142 bnx2_write_phy(bp, 0x17, 0x000a);
2143 bnx2_write_phy(bp, 0x15, 0x310b);
2144 bnx2_write_phy(bp, 0x17, 0x201f);
2145 bnx2_write_phy(bp, 0x15, 0x9506);
2146 bnx2_write_phy(bp, 0x17, 0x401f);
2147 bnx2_write_phy(bp, 0x15, 0x14e2);
2148 bnx2_write_phy(bp, 0x18, 0x0400);
2151 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2152 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2153 MII_BNX2_DSP_EXPAND_REG | 0x8);
2154 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2156 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2159 if (bp->dev->mtu > 1500) {
2160 /* Set extended packet length bit */
2161 bnx2_write_phy(bp, 0x18, 0x7);
2162 bnx2_read_phy(bp, 0x18, &val);
2163 bnx2_write_phy(bp, 0x18, val | 0x4000);
2165 bnx2_read_phy(bp, 0x10, &val);
2166 bnx2_write_phy(bp, 0x10, val | 0x1);
2169 bnx2_write_phy(bp, 0x18, 0x7);
2170 bnx2_read_phy(bp, 0x18, &val);
2171 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2173 bnx2_read_phy(bp, 0x10, &val);
2174 bnx2_write_phy(bp, 0x10, val & ~0x1);
2177 /* ethernet@wirespeed */
2178 bnx2_write_phy(bp, 0x18, 0x7007);
2179 bnx2_read_phy(bp, 0x18, &val);
2180 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2186 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2187 __releases(&bp->phy_lock)
2188 __acquires(&bp->phy_lock)
2193 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2194 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2196 bp->mii_bmcr = MII_BMCR;
2197 bp->mii_bmsr = MII_BMSR;
2198 bp->mii_bmsr1 = MII_BMSR;
2199 bp->mii_adv = MII_ADVERTISE;
2200 bp->mii_lpa = MII_LPA;
2202 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2204 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2207 bnx2_read_phy(bp, MII_PHYSID1, &val);
2208 bp->phy_id = val << 16;
2209 bnx2_read_phy(bp, MII_PHYSID2, &val);
2210 bp->phy_id |= val & 0xffff;
2212 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2213 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2214 rc = bnx2_init_5706s_phy(bp, reset_phy);
2215 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2216 rc = bnx2_init_5708s_phy(bp, reset_phy);
2217 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2218 rc = bnx2_init_5709s_phy(bp, reset_phy);
2221 rc = bnx2_init_copper_phy(bp, reset_phy);
2226 rc = bnx2_setup_phy(bp, bp->phy_port);
2232 bnx2_set_mac_loopback(struct bnx2 *bp)
2236 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2237 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2238 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2239 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2244 static int bnx2_test_link(struct bnx2 *);
2247 bnx2_set_phy_loopback(struct bnx2 *bp)
2252 spin_lock_bh(&bp->phy_lock);
2253 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2255 spin_unlock_bh(&bp->phy_lock);
2259 for (i = 0; i < 10; i++) {
2260 if (bnx2_test_link(bp) == 0)
2265 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2266 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2267 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2268 BNX2_EMAC_MODE_25G_MODE);
2270 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2271 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2277 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2283 msg_data |= bp->fw_wr_seq;
2285 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2290 /* wait for an acknowledgement. */
2291 for (i = 0; i < (BNX2_FW_ACK_TIME_OUT_MS / 10); i++) {
2294 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2296 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2299 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2302 /* If we timed out, inform the firmware that this is the case. */
2303 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2305 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2308 msg_data &= ~BNX2_DRV_MSG_CODE;
2309 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2311 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2316 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2323 bnx2_init_5709_context(struct bnx2 *bp)
2328 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2329 val |= (BCM_PAGE_BITS - 8) << 16;
2330 REG_WR(bp, BNX2_CTX_COMMAND, val);
2331 for (i = 0; i < 10; i++) {
2332 val = REG_RD(bp, BNX2_CTX_COMMAND);
2333 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2337 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2340 for (i = 0; i < bp->ctx_pages; i++) {
2344 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2348 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2349 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2350 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2351 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2352 (u64) bp->ctx_blk_mapping[i] >> 32);
2353 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2354 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2355 for (j = 0; j < 10; j++) {
2357 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2358 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2362 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2371 bnx2_init_context(struct bnx2 *bp)
2377 u32 vcid_addr, pcid_addr, offset;
2382 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2385 vcid_addr = GET_PCID_ADDR(vcid);
2387 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2392 pcid_addr = GET_PCID_ADDR(new_vcid);
2395 vcid_addr = GET_CID_ADDR(vcid);
2396 pcid_addr = vcid_addr;
2399 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2400 vcid_addr += (i << PHY_CTX_SHIFT);
2401 pcid_addr += (i << PHY_CTX_SHIFT);
2403 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2404 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2406 /* Zero out the context. */
2407 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2408 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2414 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2420 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2421 if (good_mbuf == NULL) {
2422 printk(KERN_ERR PFX "Failed to allocate memory in "
2423 "bnx2_alloc_bad_rbuf\n");
2427 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2428 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2432 /* Allocate a bunch of mbufs and save the good ones in an array. */
2433 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2434 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2435 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2436 BNX2_RBUF_COMMAND_ALLOC_REQ);
2438 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2440 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2442 /* The addresses with Bit 9 set are bad memory blocks. */
2443 if (!(val & (1 << 9))) {
2444 good_mbuf[good_mbuf_cnt] = (u16) val;
2448 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2451 /* Free the good ones back to the mbuf pool thus discarding
2452 * all the bad ones. */
2453 while (good_mbuf_cnt) {
2456 val = good_mbuf[good_mbuf_cnt];
2457 val = (val << 9) | val | 1;
2459 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2466 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2470 val = (mac_addr[0] << 8) | mac_addr[1];
2472 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2474 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2475 (mac_addr[4] << 8) | mac_addr[5];
2477 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2481 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2484 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2485 struct rx_bd *rxbd =
2486 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2487 struct page *page = alloc_page(GFP_ATOMIC);
2491 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2492 PCI_DMA_FROMDEVICE);
2493 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2499 pci_unmap_addr_set(rx_pg, mapping, mapping);
2500 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2501 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2506 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2508 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2509 struct page *page = rx_pg->page;
2514 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2515 PCI_DMA_FROMDEVICE);
2522 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2524 struct sk_buff *skb;
2525 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2527 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2528 unsigned long align;
2530 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2535 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2536 skb_reserve(skb, BNX2_RX_ALIGN - align);
2538 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2539 PCI_DMA_FROMDEVICE);
2540 if (pci_dma_mapping_error(bp->pdev, mapping)) {
2546 pci_unmap_addr_set(rx_buf, mapping, mapping);
2548 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2549 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2551 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2557 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2559 struct status_block *sblk = bnapi->status_blk.msi;
2560 u32 new_link_state, old_link_state;
2563 new_link_state = sblk->status_attn_bits & event;
2564 old_link_state = sblk->status_attn_bits_ack & event;
2565 if (new_link_state != old_link_state) {
2567 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2569 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2577 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2579 spin_lock(&bp->phy_lock);
2581 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2583 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2584 bnx2_set_remote_link(bp);
2586 spin_unlock(&bp->phy_lock);
2591 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2595 /* Tell compiler that status block fields can change. */
2597 cons = *bnapi->hw_tx_cons_ptr;
2598 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2604 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2606 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2607 u16 hw_cons, sw_cons, sw_ring_cons;
2608 int tx_pkt = 0, index;
2609 struct netdev_queue *txq;
2611 index = (bnapi - bp->bnx2_napi);
2612 txq = netdev_get_tx_queue(bp->dev, index);
2614 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2615 sw_cons = txr->tx_cons;
2617 while (sw_cons != hw_cons) {
2618 struct sw_tx_bd *tx_buf;
2619 struct sk_buff *skb;
2622 sw_ring_cons = TX_RING_IDX(sw_cons);
2624 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2627 /* partial BD completions possible with TSO packets */
2628 if (skb_is_gso(skb)) {
2629 u16 last_idx, last_ring_idx;
2631 last_idx = sw_cons +
2632 skb_shinfo(skb)->nr_frags + 1;
2633 last_ring_idx = sw_ring_cons +
2634 skb_shinfo(skb)->nr_frags + 1;
2635 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2638 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2643 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
2646 last = skb_shinfo(skb)->nr_frags;
2648 for (i = 0; i < last; i++) {
2649 sw_cons = NEXT_TX_BD(sw_cons);
2652 sw_cons = NEXT_TX_BD(sw_cons);
2656 if (tx_pkt == budget)
2659 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2662 txr->hw_tx_cons = hw_cons;
2663 txr->tx_cons = sw_cons;
2665 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2666 * before checking for netif_tx_queue_stopped(). Without the
2667 * memory barrier, there is a small possibility that bnx2_start_xmit()
2668 * will miss it and cause the queue to be stopped forever.
2672 if (unlikely(netif_tx_queue_stopped(txq)) &&
2673 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2674 __netif_tx_lock(txq, smp_processor_id());
2675 if ((netif_tx_queue_stopped(txq)) &&
2676 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2677 netif_tx_wake_queue(txq);
2678 __netif_tx_unlock(txq);
2685 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2686 struct sk_buff *skb, int count)
2688 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2689 struct rx_bd *cons_bd, *prod_bd;
2692 u16 cons = rxr->rx_pg_cons;
2694 cons_rx_pg = &rxr->rx_pg_ring[cons];
2696 /* The caller was unable to allocate a new page to replace the
2697 * last one in the frags array, so we need to recycle that page
2698 * and then free the skb.
2702 struct skb_shared_info *shinfo;
2704 shinfo = skb_shinfo(skb);
2706 page = shinfo->frags[shinfo->nr_frags].page;
2707 shinfo->frags[shinfo->nr_frags].page = NULL;
2709 cons_rx_pg->page = page;
2713 hw_prod = rxr->rx_pg_prod;
2715 for (i = 0; i < count; i++) {
2716 prod = RX_PG_RING_IDX(hw_prod);
2718 prod_rx_pg = &rxr->rx_pg_ring[prod];
2719 cons_rx_pg = &rxr->rx_pg_ring[cons];
2720 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2721 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2724 prod_rx_pg->page = cons_rx_pg->page;
2725 cons_rx_pg->page = NULL;
2726 pci_unmap_addr_set(prod_rx_pg, mapping,
2727 pci_unmap_addr(cons_rx_pg, mapping));
2729 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2730 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2733 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2734 hw_prod = NEXT_RX_BD(hw_prod);
2736 rxr->rx_pg_prod = hw_prod;
2737 rxr->rx_pg_cons = cons;
2741 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2742 struct sk_buff *skb, u16 cons, u16 prod)
2744 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2745 struct rx_bd *cons_bd, *prod_bd;
2747 cons_rx_buf = &rxr->rx_buf_ring[cons];
2748 prod_rx_buf = &rxr->rx_buf_ring[prod];
2750 pci_dma_sync_single_for_device(bp->pdev,
2751 pci_unmap_addr(cons_rx_buf, mapping),
2752 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2754 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2756 prod_rx_buf->skb = skb;
2761 pci_unmap_addr_set(prod_rx_buf, mapping,
2762 pci_unmap_addr(cons_rx_buf, mapping));
2764 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2765 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2766 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2767 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2771 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2772 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2776 u16 prod = ring_idx & 0xffff;
2778 err = bnx2_alloc_rx_skb(bp, rxr, prod);
2779 if (unlikely(err)) {
2780 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2782 unsigned int raw_len = len + 4;
2783 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2785 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2790 skb_reserve(skb, BNX2_RX_OFFSET);
2791 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2792 PCI_DMA_FROMDEVICE);
2798 unsigned int i, frag_len, frag_size, pages;
2799 struct sw_pg *rx_pg;
2800 u16 pg_cons = rxr->rx_pg_cons;
2801 u16 pg_prod = rxr->rx_pg_prod;
2803 frag_size = len + 4 - hdr_len;
2804 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2805 skb_put(skb, hdr_len);
2807 for (i = 0; i < pages; i++) {
2808 dma_addr_t mapping_old;
2810 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2811 if (unlikely(frag_len <= 4)) {
2812 unsigned int tail = 4 - frag_len;
2814 rxr->rx_pg_cons = pg_cons;
2815 rxr->rx_pg_prod = pg_prod;
2816 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
2823 &skb_shinfo(skb)->frags[i - 1];
2825 skb->data_len -= tail;
2826 skb->truesize -= tail;
2830 rx_pg = &rxr->rx_pg_ring[pg_cons];
2832 /* Don't unmap yet. If we're unable to allocate a new
2833 * page, we need to recycle the page and the DMA addr.
2835 mapping_old = pci_unmap_addr(rx_pg, mapping);
2839 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2842 err = bnx2_alloc_rx_page(bp, rxr,
2843 RX_PG_RING_IDX(pg_prod));
2844 if (unlikely(err)) {
2845 rxr->rx_pg_cons = pg_cons;
2846 rxr->rx_pg_prod = pg_prod;
2847 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
2852 pci_unmap_page(bp->pdev, mapping_old,
2853 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2855 frag_size -= frag_len;
2856 skb->data_len += frag_len;
2857 skb->truesize += frag_len;
2858 skb->len += frag_len;
2860 pg_prod = NEXT_RX_BD(pg_prod);
2861 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2863 rxr->rx_pg_prod = pg_prod;
2864 rxr->rx_pg_cons = pg_cons;
2870 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2874 /* Tell compiler that status block fields can change. */
2876 cons = *bnapi->hw_rx_cons_ptr;
2877 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2883 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2885 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
2886 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2887 struct l2_fhdr *rx_hdr;
2888 int rx_pkt = 0, pg_ring_used = 0;
2890 hw_cons = bnx2_get_hw_rx_cons(bnapi);
2891 sw_cons = rxr->rx_cons;
2892 sw_prod = rxr->rx_prod;
2894 /* Memory barrier necessary as speculative reads of the rx
2895 * buffer can be ahead of the index in the status block
2898 while (sw_cons != hw_cons) {
2899 unsigned int len, hdr_len;
2901 struct sw_bd *rx_buf;
2902 struct sk_buff *skb;
2903 dma_addr_t dma_addr;
2905 int hw_vlan __maybe_unused = 0;
2907 sw_ring_cons = RX_RING_IDX(sw_cons);
2908 sw_ring_prod = RX_RING_IDX(sw_prod);
2910 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
2915 dma_addr = pci_unmap_addr(rx_buf, mapping);
2917 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2918 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2919 PCI_DMA_FROMDEVICE);
2921 rx_hdr = (struct l2_fhdr *) skb->data;
2922 len = rx_hdr->l2_fhdr_pkt_len;
2924 if ((status = rx_hdr->l2_fhdr_status) &
2925 (L2_FHDR_ERRORS_BAD_CRC |
2926 L2_FHDR_ERRORS_PHY_DECODE |
2927 L2_FHDR_ERRORS_ALIGNMENT |
2928 L2_FHDR_ERRORS_TOO_SHORT |
2929 L2_FHDR_ERRORS_GIANT_FRAME)) {
2931 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2936 if (status & L2_FHDR_STATUS_SPLIT) {
2937 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2939 } else if (len > bp->rx_jumbo_thresh) {
2940 hdr_len = bp->rx_jumbo_thresh;
2946 if (len <= bp->rx_copy_thresh) {
2947 struct sk_buff *new_skb;
2949 new_skb = netdev_alloc_skb(bp->dev, len + 6);
2950 if (new_skb == NULL) {
2951 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2957 skb_copy_from_linear_data_offset(skb,
2959 new_skb->data, len + 6);
2960 skb_reserve(new_skb, 6);
2961 skb_put(new_skb, len);
2963 bnx2_reuse_rx_skb(bp, rxr, skb,
2964 sw_ring_cons, sw_ring_prod);
2967 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
2968 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2971 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
2972 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
2973 vtag = rx_hdr->l2_fhdr_vlan_tag;
2980 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
2983 memmove(ve, skb->data + 4, ETH_ALEN * 2);
2984 ve->h_vlan_proto = htons(ETH_P_8021Q);
2985 ve->h_vlan_TCI = htons(vtag);
2990 skb->protocol = eth_type_trans(skb, bp->dev);
2992 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2993 (ntohs(skb->protocol) != 0x8100)) {
3000 skb->ip_summed = CHECKSUM_NONE;
3002 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
3003 L2_FHDR_STATUS_UDP_DATAGRAM))) {
3005 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
3006 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
3007 skb->ip_summed = CHECKSUM_UNNECESSARY;
3010 skb_record_rx_queue(skb, bnapi - &bp->bnx2_napi[0]);
3014 vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
3017 netif_receive_skb(skb);
3022 sw_cons = NEXT_RX_BD(sw_cons);
3023 sw_prod = NEXT_RX_BD(sw_prod);
3025 if ((rx_pkt == budget))
3028 /* Refresh hw_cons to see if there is new work */
3029 if (sw_cons == hw_cons) {
3030 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3034 rxr->rx_cons = sw_cons;
3035 rxr->rx_prod = sw_prod;
3038 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3040 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3042 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3050 /* MSI ISR - The only difference between this and the INTx ISR
3051 * is that the MSI interrupt is always serviced.
3054 bnx2_msi(int irq, void *dev_instance)
3056 struct bnx2_napi *bnapi = dev_instance;
3057 struct bnx2 *bp = bnapi->bp;
3059 prefetch(bnapi->status_blk.msi);
3060 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3061 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3062 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3064 /* Return here if interrupt is disabled. */
3065 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3068 napi_schedule(&bnapi->napi);
3074 bnx2_msi_1shot(int irq, void *dev_instance)
3076 struct bnx2_napi *bnapi = dev_instance;
3077 struct bnx2 *bp = bnapi->bp;
3079 prefetch(bnapi->status_blk.msi);
3081 /* Return here if interrupt is disabled. */
3082 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3085 napi_schedule(&bnapi->napi);
3091 bnx2_interrupt(int irq, void *dev_instance)
3093 struct bnx2_napi *bnapi = dev_instance;
3094 struct bnx2 *bp = bnapi->bp;
3095 struct status_block *sblk = bnapi->status_blk.msi;
3097 /* When using INTx, it is possible for the interrupt to arrive
3098 * at the CPU before the status block posted prior to the
3099 * interrupt. Reading a register will flush the status block.
3100 * When using MSI, the MSI message will always complete after
3101 * the status block write.
3103 if ((sblk->status_idx == bnapi->last_status_idx) &&
3104 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3105 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3108 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3109 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3110 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3112 /* Read back to deassert IRQ immediately to avoid too many
3113 * spurious interrupts.
3115 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3117 /* Return here if interrupt is shared and is disabled. */
3118 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3121 if (napi_schedule_prep(&bnapi->napi)) {
3122 bnapi->last_status_idx = sblk->status_idx;
3123 __napi_schedule(&bnapi->napi);
3130 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3132 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3133 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3135 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3136 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3141 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3142 STATUS_ATTN_BITS_TIMER_ABORT)
3145 bnx2_has_work(struct bnx2_napi *bnapi)
3147 struct status_block *sblk = bnapi->status_blk.msi;
3149 if (bnx2_has_fast_work(bnapi))
3152 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3153 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3160 bnx2_chk_missed_msi(struct bnx2 *bp)
3162 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
3165 if (bnx2_has_work(bnapi)) {
3166 msi_ctrl = REG_RD(bp, BNX2_PCICFG_MSI_CONTROL);
3167 if (!(msi_ctrl & BNX2_PCICFG_MSI_CONTROL_ENABLE))
3170 if (bnapi->last_status_idx == bp->idle_chk_status_idx) {
3171 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl &
3172 ~BNX2_PCICFG_MSI_CONTROL_ENABLE);
3173 REG_WR(bp, BNX2_PCICFG_MSI_CONTROL, msi_ctrl);
3174 bnx2_msi(bp->irq_tbl[0].vector, bnapi);
3178 bp->idle_chk_status_idx = bnapi->last_status_idx;
3181 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3183 struct status_block *sblk = bnapi->status_blk.msi;
3184 u32 status_attn_bits = sblk->status_attn_bits;
3185 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3187 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3188 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3190 bnx2_phy_int(bp, bnapi);
3192 /* This is needed to take care of transient status
3193 * during link changes.
3195 REG_WR(bp, BNX2_HC_COMMAND,
3196 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3197 REG_RD(bp, BNX2_HC_COMMAND);
3201 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3202 int work_done, int budget)
3204 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3205 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3207 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3208 bnx2_tx_int(bp, bnapi, 0);
3210 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3211 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3216 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3218 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3219 struct bnx2 *bp = bnapi->bp;
3221 struct status_block_msix *sblk = bnapi->status_blk.msix;
3224 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3225 if (unlikely(work_done >= budget))
3228 bnapi->last_status_idx = sblk->status_idx;
3229 /* status idx must be read before checking for more work. */
3231 if (likely(!bnx2_has_fast_work(bnapi))) {
3233 napi_complete(napi);
3234 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3235 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3236 bnapi->last_status_idx);
3243 static int bnx2_poll(struct napi_struct *napi, int budget)
3245 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3246 struct bnx2 *bp = bnapi->bp;
3248 struct status_block *sblk = bnapi->status_blk.msi;
3251 bnx2_poll_link(bp, bnapi);
3253 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3255 /* bnapi->last_status_idx is used below to tell the hw how
3256 * much work has been processed, so we must read it before
3257 * checking for more work.
3259 bnapi->last_status_idx = sblk->status_idx;
3261 if (unlikely(work_done >= budget))
3265 if (likely(!bnx2_has_work(bnapi))) {
3266 napi_complete(napi);
3267 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3268 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3269 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3270 bnapi->last_status_idx);
3273 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3274 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3275 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3276 bnapi->last_status_idx);
3278 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3279 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3280 bnapi->last_status_idx);
3288 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3289 * from set_multicast.
3292 bnx2_set_rx_mode(struct net_device *dev)
3294 struct bnx2 *bp = netdev_priv(dev);
3295 u32 rx_mode, sort_mode;
3296 struct dev_addr_list *uc_ptr;
3299 if (!netif_running(dev))
3302 spin_lock_bh(&bp->phy_lock);
3304 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3305 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3306 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3308 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3309 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3311 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3312 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3314 if (dev->flags & IFF_PROMISC) {
3315 /* Promiscuous mode. */
3316 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3317 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3318 BNX2_RPM_SORT_USER0_PROM_VLAN;
3320 else if (dev->flags & IFF_ALLMULTI) {
3321 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3322 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3325 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3328 /* Accept one or more multicast(s). */
3329 struct dev_mc_list *mclist;
3330 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3335 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3337 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3338 i++, mclist = mclist->next) {
3340 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3342 regidx = (bit & 0xe0) >> 5;
3344 mc_filter[regidx] |= (1 << bit);
3347 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3348 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3352 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3356 if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
3357 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3358 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3359 BNX2_RPM_SORT_USER0_PROM_VLAN;
3360 } else if (!(dev->flags & IFF_PROMISC)) {
3361 uc_ptr = dev->uc_list;
3363 /* Add all entries into to the match filter list */
3364 for (i = 0; i < dev->uc_count; i++) {
3365 bnx2_set_mac_addr(bp, uc_ptr->da_addr,
3366 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3368 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3369 uc_ptr = uc_ptr->next;
3374 if (rx_mode != bp->rx_mode) {
3375 bp->rx_mode = rx_mode;
3376 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3379 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3380 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3381 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3383 spin_unlock_bh(&bp->phy_lock);
3387 load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
3393 if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
3394 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
3395 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
3396 val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
3397 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
3400 for (i = 0; i < rv2p_code_len; i += 8) {
3401 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
3403 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
3406 if (rv2p_proc == RV2P_PROC1) {
3407 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3408 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3411 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3412 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3416 /* Reset the processor, un-stall is done later. */
3417 if (rv2p_proc == RV2P_PROC1) {
3418 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3421 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3426 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
3433 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3434 val |= cpu_reg->mode_value_halt;
3435 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3436 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3438 /* Load the Text area. */
3439 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3443 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3448 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3449 bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
3453 /* Load the Data area. */
3454 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3458 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3459 bnx2_reg_wr_ind(bp, offset, fw->data[j]);
3463 /* Load the SBSS area. */
3464 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
3468 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3469 bnx2_reg_wr_ind(bp, offset, 0);
3473 /* Load the BSS area. */
3474 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
3478 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3479 bnx2_reg_wr_ind(bp, offset, 0);
3483 /* Load the Read-Only area. */
3484 offset = cpu_reg->spad_base +
3485 (fw->rodata_addr - cpu_reg->mips_view_base);
3489 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3490 bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
3494 /* Clear the pre-fetch instruction. */
3495 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3496 bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
3498 /* Start the CPU. */
3499 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3500 val &= ~cpu_reg->mode_value_halt;
3501 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3502 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3508 bnx2_init_cpus(struct bnx2 *bp)
3514 /* Initialize the RV2P processor. */
3515 text = vmalloc(FW_BUF_SIZE);
3518 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3519 rv2p = bnx2_xi_rv2p_proc1;
3520 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3522 rv2p = bnx2_rv2p_proc1;
3523 rv2p_len = sizeof(bnx2_rv2p_proc1);
3525 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3529 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
3531 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3532 rv2p = bnx2_xi_rv2p_proc2;
3533 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3535 rv2p = bnx2_rv2p_proc2;
3536 rv2p_len = sizeof(bnx2_rv2p_proc2);
3538 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3542 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
3544 /* Initialize the RX Processor. */
3545 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3546 fw = &bnx2_rxp_fw_09;
3548 fw = &bnx2_rxp_fw_06;
3551 rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
3555 /* Initialize the TX Processor. */
3556 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3557 fw = &bnx2_txp_fw_09;
3559 fw = &bnx2_txp_fw_06;
3562 rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
3566 /* Initialize the TX Patch-up Processor. */
3567 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3568 fw = &bnx2_tpat_fw_09;
3570 fw = &bnx2_tpat_fw_06;
3573 rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
3577 /* Initialize the Completion Processor. */
3578 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3579 fw = &bnx2_com_fw_09;
3581 fw = &bnx2_com_fw_06;
3584 rc = load_cpu_fw(bp, &cpu_reg_com, fw);
3588 /* Initialize the Command Processor. */
3589 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3590 fw = &bnx2_cp_fw_09;
3592 fw = &bnx2_cp_fw_06;
3595 rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
3603 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3607 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3613 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3614 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3615 PCI_PM_CTRL_PME_STATUS);
3617 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3618 /* delay required during transition out of D3hot */
3621 val = REG_RD(bp, BNX2_EMAC_MODE);
3622 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3623 val &= ~BNX2_EMAC_MODE_MPKT;
3624 REG_WR(bp, BNX2_EMAC_MODE, val);
3626 val = REG_RD(bp, BNX2_RPM_CONFIG);
3627 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3628 REG_WR(bp, BNX2_RPM_CONFIG, val);
3639 autoneg = bp->autoneg;
3640 advertising = bp->advertising;
3642 if (bp->phy_port == PORT_TP) {
3643 bp->autoneg = AUTONEG_SPEED;
3644 bp->advertising = ADVERTISED_10baseT_Half |
3645 ADVERTISED_10baseT_Full |
3646 ADVERTISED_100baseT_Half |
3647 ADVERTISED_100baseT_Full |
3651 spin_lock_bh(&bp->phy_lock);
3652 bnx2_setup_phy(bp, bp->phy_port);
3653 spin_unlock_bh(&bp->phy_lock);
3655 bp->autoneg = autoneg;
3656 bp->advertising = advertising;
3658 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3660 val = REG_RD(bp, BNX2_EMAC_MODE);
3662 /* Enable port mode. */
3663 val &= ~BNX2_EMAC_MODE_PORT;
3664 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3665 BNX2_EMAC_MODE_ACPI_RCVD |
3666 BNX2_EMAC_MODE_MPKT;
3667 if (bp->phy_port == PORT_TP)
3668 val |= BNX2_EMAC_MODE_PORT_MII;
3670 val |= BNX2_EMAC_MODE_PORT_GMII;
3671 if (bp->line_speed == SPEED_2500)
3672 val |= BNX2_EMAC_MODE_25G_MODE;
3675 REG_WR(bp, BNX2_EMAC_MODE, val);
3677 /* receive all multicast */
3678 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3679 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3682 REG_WR(bp, BNX2_EMAC_RX_MODE,
3683 BNX2_EMAC_RX_MODE_SORT_MODE);
3685 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3686 BNX2_RPM_SORT_USER0_MC_EN;
3687 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3688 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3689 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3690 BNX2_RPM_SORT_USER0_ENA);
3692 /* Need to enable EMAC and RPM for WOL. */
3693 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3694 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3695 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3696 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3698 val = REG_RD(bp, BNX2_RPM_CONFIG);
3699 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3700 REG_WR(bp, BNX2_RPM_CONFIG, val);
3702 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3705 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3708 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3709 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3712 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3713 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3714 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3723 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3725 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3728 /* No more memory access after this point until
3729 * device is brought back to D0.
3741 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3746 /* Request access to the flash interface. */
3747 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3748 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3749 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3750 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3756 if (j >= NVRAM_TIMEOUT_COUNT)
3763 bnx2_release_nvram_lock(struct bnx2 *bp)
3768 /* Relinquish nvram interface. */
3769 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3771 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3772 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3773 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3779 if (j >= NVRAM_TIMEOUT_COUNT)
3787 bnx2_enable_nvram_write(struct bnx2 *bp)
3791 val = REG_RD(bp, BNX2_MISC_CFG);
3792 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3794 if (bp->flash_info->flags & BNX2_NV_WREN) {
3797 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3798 REG_WR(bp, BNX2_NVM_COMMAND,
3799 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3801 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3804 val = REG_RD(bp, BNX2_NVM_COMMAND);
3805 if (val & BNX2_NVM_COMMAND_DONE)
3809 if (j >= NVRAM_TIMEOUT_COUNT)
3816 bnx2_disable_nvram_write(struct bnx2 *bp)
3820 val = REG_RD(bp, BNX2_MISC_CFG);
3821 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3826 bnx2_enable_nvram_access(struct bnx2 *bp)
3830 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3831 /* Enable both bits, even on read. */
3832 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3833 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3837 bnx2_disable_nvram_access(struct bnx2 *bp)
3841 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3842 /* Disable both bits, even after read. */
3843 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3844 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3845 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3849 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3854 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3855 /* Buffered flash, no erase needed */
3858 /* Build an erase command */
3859 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3860 BNX2_NVM_COMMAND_DOIT;
3862 /* Need to clear DONE bit separately. */
3863 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3865 /* Address of the NVRAM to read from. */
3866 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3868 /* Issue an erase command. */
3869 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3871 /* Wait for completion. */
3872 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3877 val = REG_RD(bp, BNX2_NVM_COMMAND);
3878 if (val & BNX2_NVM_COMMAND_DONE)
3882 if (j >= NVRAM_TIMEOUT_COUNT)
3889 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3894 /* Build the command word. */
3895 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3897 /* Calculate an offset of a buffered flash, not needed for 5709. */
3898 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3899 offset = ((offset / bp->flash_info->page_size) <<
3900 bp->flash_info->page_bits) +
3901 (offset % bp->flash_info->page_size);
3904 /* Need to clear DONE bit separately. */
3905 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3907 /* Address of the NVRAM to read from. */
3908 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3910 /* Issue a read command. */
3911 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3913 /* Wait for completion. */
3914 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3919 val = REG_RD(bp, BNX2_NVM_COMMAND);
3920 if (val & BNX2_NVM_COMMAND_DONE) {
3921 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3922 memcpy(ret_val, &v, 4);
3926 if (j >= NVRAM_TIMEOUT_COUNT)
3934 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3940 /* Build the command word. */
3941 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3943 /* Calculate an offset of a buffered flash, not needed for 5709. */
3944 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3945 offset = ((offset / bp->flash_info->page_size) <<
3946 bp->flash_info->page_bits) +
3947 (offset % bp->flash_info->page_size);
3950 /* Need to clear DONE bit separately. */
3951 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3953 memcpy(&val32, val, 4);
3955 /* Write the data. */
3956 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
3958 /* Address of the NVRAM to write to. */
3959 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3961 /* Issue the write command. */
3962 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3964 /* Wait for completion. */
3965 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3968 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3971 if (j >= NVRAM_TIMEOUT_COUNT)
3978 bnx2_init_nvram(struct bnx2 *bp)
3981 int j, entry_count, rc = 0;
3982 struct flash_spec *flash;
3984 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3985 bp->flash_info = &flash_5709;
3986 goto get_flash_size;
3989 /* Determine the selected interface. */
3990 val = REG_RD(bp, BNX2_NVM_CFG1);
3992 entry_count = ARRAY_SIZE(flash_table);
3994 if (val & 0x40000000) {
3996 /* Flash interface has been reconfigured */
3997 for (j = 0, flash = &flash_table[0]; j < entry_count;
3999 if ((val & FLASH_BACKUP_STRAP_MASK) ==
4000 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
4001 bp->flash_info = flash;
4008 /* Not yet been reconfigured */
4010 if (val & (1 << 23))
4011 mask = FLASH_BACKUP_STRAP_MASK;
4013 mask = FLASH_STRAP_MASK;
4015 for (j = 0, flash = &flash_table[0]; j < entry_count;
4018 if ((val & mask) == (flash->strapping & mask)) {
4019 bp->flash_info = flash;
4021 /* Request access to the flash interface. */
4022 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4025 /* Enable access to flash interface */
4026 bnx2_enable_nvram_access(bp);
4028 /* Reconfigure the flash interface */
4029 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
4030 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
4031 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
4032 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
4034 /* Disable access to flash interface */
4035 bnx2_disable_nvram_access(bp);
4036 bnx2_release_nvram_lock(bp);
4041 } /* if (val & 0x40000000) */
4043 if (j == entry_count) {
4044 bp->flash_info = NULL;
4045 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
4050 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4051 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4053 bp->flash_size = val;
4055 bp->flash_size = bp->flash_info->total_size;
4061 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4065 u32 cmd_flags, offset32, len32, extra;
4070 /* Request access to the flash interface. */
4071 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4074 /* Enable access to flash interface */
4075 bnx2_enable_nvram_access(bp);
4088 pre_len = 4 - (offset & 3);
4090 if (pre_len >= len32) {
4092 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4093 BNX2_NVM_COMMAND_LAST;
4096 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4099 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4104 memcpy(ret_buf, buf + (offset & 3), pre_len);
4111 extra = 4 - (len32 & 3);
4112 len32 = (len32 + 4) & ~3;
4119 cmd_flags = BNX2_NVM_COMMAND_LAST;
4121 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4122 BNX2_NVM_COMMAND_LAST;
4124 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4126 memcpy(ret_buf, buf, 4 - extra);
4128 else if (len32 > 0) {
4131 /* Read the first word. */
4135 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4137 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4139 /* Advance to the next dword. */
4144 while (len32 > 4 && rc == 0) {
4145 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4147 /* Advance to the next dword. */
4156 cmd_flags = BNX2_NVM_COMMAND_LAST;
4157 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4159 memcpy(ret_buf, buf, 4 - extra);
4162 /* Disable access to flash interface */
4163 bnx2_disable_nvram_access(bp);
4165 bnx2_release_nvram_lock(bp);
4171 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4174 u32 written, offset32, len32;
4175 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4177 int align_start, align_end;
4182 align_start = align_end = 0;
4184 if ((align_start = (offset32 & 3))) {
4186 len32 += align_start;
4189 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4194 align_end = 4 - (len32 & 3);
4196 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4200 if (align_start || align_end) {
4201 align_buf = kmalloc(len32, GFP_KERNEL);
4202 if (align_buf == NULL)
4205 memcpy(align_buf, start, 4);
4208 memcpy(align_buf + len32 - 4, end, 4);
4210 memcpy(align_buf + align_start, data_buf, buf_size);
4214 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4215 flash_buffer = kmalloc(264, GFP_KERNEL);
4216 if (flash_buffer == NULL) {
4218 goto nvram_write_end;
4223 while ((written < len32) && (rc == 0)) {
4224 u32 page_start, page_end, data_start, data_end;
4225 u32 addr, cmd_flags;
4228 /* Find the page_start addr */
4229 page_start = offset32 + written;
4230 page_start -= (page_start % bp->flash_info->page_size);
4231 /* Find the page_end addr */
4232 page_end = page_start + bp->flash_info->page_size;
4233 /* Find the data_start addr */
4234 data_start = (written == 0) ? offset32 : page_start;
4235 /* Find the data_end addr */
4236 data_end = (page_end > offset32 + len32) ?
4237 (offset32 + len32) : page_end;
4239 /* Request access to the flash interface. */
4240 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4241 goto nvram_write_end;
4243 /* Enable access to flash interface */
4244 bnx2_enable_nvram_access(bp);
4246 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4247 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4250 /* Read the whole page into the buffer
4251 * (non-buffer flash only) */
4252 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4253 if (j == (bp->flash_info->page_size - 4)) {
4254 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4256 rc = bnx2_nvram_read_dword(bp,
4262 goto nvram_write_end;
4268 /* Enable writes to flash interface (unlock write-protect) */
4269 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4270 goto nvram_write_end;
4272 /* Loop to write back the buffer data from page_start to
4275 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4276 /* Erase the page */
4277 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4278 goto nvram_write_end;
4280 /* Re-enable the write again for the actual write */
4281 bnx2_enable_nvram_write(bp);
4283 for (addr = page_start; addr < data_start;
4284 addr += 4, i += 4) {
4286 rc = bnx2_nvram_write_dword(bp, addr,
4287 &flash_buffer[i], cmd_flags);
4290 goto nvram_write_end;
4296 /* Loop to write the new data from data_start to data_end */
4297 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4298 if ((addr == page_end - 4) ||
4299 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4300 (addr == data_end - 4))) {
4302 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4304 rc = bnx2_nvram_write_dword(bp, addr, buf,
4308 goto nvram_write_end;
4314 /* Loop to write back the buffer data from data_end
4316 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4317 for (addr = data_end; addr < page_end;
4318 addr += 4, i += 4) {
4320 if (addr == page_end-4) {
4321 cmd_flags = BNX2_NVM_COMMAND_LAST;
4323 rc = bnx2_nvram_write_dword(bp, addr,
4324 &flash_buffer[i], cmd_flags);
4327 goto nvram_write_end;
4333 /* Disable writes to flash interface (lock write-protect) */
4334 bnx2_disable_nvram_write(bp);
4336 /* Disable access to flash interface */
4337 bnx2_disable_nvram_access(bp);
4338 bnx2_release_nvram_lock(bp);
4340 /* Increment written */
4341 written += data_end - data_start;
4345 kfree(flash_buffer);
4351 bnx2_init_fw_cap(struct bnx2 *bp)
4355 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4356 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4358 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4359 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4361 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4362 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4365 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4366 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4367 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4370 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4371 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4374 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4376 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4377 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4378 bp->phy_port = PORT_FIBRE;
4380 bp->phy_port = PORT_TP;
4382 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4383 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4386 if (netif_running(bp->dev) && sig)
4387 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4391 bnx2_setup_msix_tbl(struct bnx2 *bp)
4393 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4395 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4396 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4400 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4406 /* Wait for the current PCI transaction to complete before
4407 * issuing a reset. */
4408 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4409 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4410 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4411 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4412 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4413 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4416 /* Wait for the firmware to tell us it is ok to issue a reset. */
4417 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4419 /* Deposit a driver reset signature so the firmware knows that
4420 * this is a soft reset. */
4421 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4422 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4424 /* Do a dummy read to force the chip to complete all current transaction
4425 * before we issue a reset. */
4426 val = REG_RD(bp, BNX2_MISC_ID);
4428 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4429 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4430 REG_RD(bp, BNX2_MISC_COMMAND);
4433 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4434 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4436 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4439 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4440 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4441 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4444 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4446 /* Reading back any register after chip reset will hang the
4447 * bus on 5706 A0 and A1. The msleep below provides plenty
4448 * of margin for write posting.
4450 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4451 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4454 /* Reset takes approximate 30 usec */
4455 for (i = 0; i < 10; i++) {
4456 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4457 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4458 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4463 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4464 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4465 printk(KERN_ERR PFX "Chip reset did not complete\n");
4470 /* Make sure byte swapping is properly configured. */
4471 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4472 if (val != 0x01020304) {
4473 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4477 /* Wait for the firmware to finish its initialization. */
4478 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4482 spin_lock_bh(&bp->phy_lock);
4483 old_port = bp->phy_port;
4484 bnx2_init_fw_cap(bp);
4485 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4486 old_port != bp->phy_port)
4487 bnx2_set_default_remote_link(bp);
4488 spin_unlock_bh(&bp->phy_lock);
4490 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4491 /* Adjust the voltage regular to two steps lower. The default
4492 * of this register is 0x0000000e. */
4493 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4495 /* Remove bad rbuf memory from the free pool. */
4496 rc = bnx2_alloc_bad_rbuf(bp);
4499 if (bp->flags & BNX2_FLAG_USING_MSIX)
4500 bnx2_setup_msix_tbl(bp);
4506 bnx2_init_chip(struct bnx2 *bp)
4511 /* Make sure the interrupt is not active. */
4512 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4514 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4515 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4517 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4519 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4520 DMA_READ_CHANS << 12 |
4521 DMA_WRITE_CHANS << 16;
4523 val |= (0x2 << 20) | (1 << 11);
4525 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4528 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4529 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4530 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4532 REG_WR(bp, BNX2_DMA_CONFIG, val);
4534 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4535 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4536 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4537 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4540 if (bp->flags & BNX2_FLAG_PCIX) {
4543 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4545 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4546 val16 & ~PCI_X_CMD_ERO);
4549 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4550 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4551 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4552 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4554 /* Initialize context mapping and zero out the quick contexts. The
4555 * context block must have already been enabled. */
4556 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4557 rc = bnx2_init_5709_context(bp);
4561 bnx2_init_context(bp);
4563 if ((rc = bnx2_init_cpus(bp)) != 0)
4566 bnx2_init_nvram(bp);
4568 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4570 val = REG_RD(bp, BNX2_MQ_CONFIG);
4571 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4572 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4573 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4574 val |= BNX2_MQ_CONFIG_HALT_DIS;
4576 REG_WR(bp, BNX2_MQ_CONFIG, val);
4578 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4579 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4580 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4582 val = (BCM_PAGE_BITS - 8) << 24;
4583 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4585 /* Configure page size. */
4586 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4587 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4588 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4589 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4591 val = bp->mac_addr[0] +
4592 (bp->mac_addr[1] << 8) +
4593 (bp->mac_addr[2] << 16) +
4595 (bp->mac_addr[4] << 8) +
4596 (bp->mac_addr[5] << 16);
4597 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4599 /* Program the MTU. Also include 4 bytes for CRC32. */
4601 val = mtu + ETH_HLEN + ETH_FCS_LEN;
4602 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4603 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4604 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4609 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG, BNX2_RBUF_CONFIG_VAL(mtu));
4610 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG2, BNX2_RBUF_CONFIG2_VAL(mtu));
4611 bnx2_reg_wr_ind(bp, BNX2_RBUF_CONFIG3, BNX2_RBUF_CONFIG3_VAL(mtu));
4613 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4614 bp->bnx2_napi[i].last_status_idx = 0;
4616 bp->idle_chk_status_idx = 0xffff;
4618 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4620 /* Set up how to generate a link change interrupt. */
4621 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4623 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4624 (u64) bp->status_blk_mapping & 0xffffffff);
4625 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4627 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4628 (u64) bp->stats_blk_mapping & 0xffffffff);
4629 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4630 (u64) bp->stats_blk_mapping >> 32);
4632 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4633 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4635 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4636 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4638 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4639 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4641 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4643 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4645 REG_WR(bp, BNX2_HC_COM_TICKS,
4646 (bp->com_ticks_int << 16) | bp->com_ticks);
4648 REG_WR(bp, BNX2_HC_CMD_TICKS,
4649 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4651 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4652 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4654 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4655 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4657 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4658 val = BNX2_HC_CONFIG_COLLECT_STATS;
4660 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4661 BNX2_HC_CONFIG_COLLECT_STATS;
4664 if (bp->irq_nvecs > 1) {
4665 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4666 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4668 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4671 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4672 val |= BNX2_HC_CONFIG_ONE_SHOT;
4674 REG_WR(bp, BNX2_HC_CONFIG, val);
4676 for (i = 1; i < bp->irq_nvecs; i++) {
4677 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4678 BNX2_HC_SB_CONFIG_1;
4681 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4682 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4683 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4685 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4686 (bp->tx_quick_cons_trip_int << 16) |
4687 bp->tx_quick_cons_trip);
4689 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4690 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4692 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4693 (bp->rx_quick_cons_trip_int << 16) |
4694 bp->rx_quick_cons_trip);
4696 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4697 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4700 /* Clear internal stats counters. */
4701 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4703 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4705 /* Initialize the receive filter. */
4706 bnx2_set_rx_mode(bp->dev);
4708 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4709 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4710 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4711 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4713 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4716 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4717 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4721 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4727 bnx2_clear_ring_states(struct bnx2 *bp)
4729 struct bnx2_napi *bnapi;
4730 struct bnx2_tx_ring_info *txr;
4731 struct bnx2_rx_ring_info *rxr;
4734 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4735 bnapi = &bp->bnx2_napi[i];
4736 txr = &bnapi->tx_ring;
4737 rxr = &bnapi->rx_ring;
4740 txr->hw_tx_cons = 0;
4741 rxr->rx_prod_bseq = 0;
4744 rxr->rx_pg_prod = 0;
4745 rxr->rx_pg_cons = 0;
4750 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
4752 u32 val, offset0, offset1, offset2, offset3;
4753 u32 cid_addr = GET_CID_ADDR(cid);
4755 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4756 offset0 = BNX2_L2CTX_TYPE_XI;
4757 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4758 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4759 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4761 offset0 = BNX2_L2CTX_TYPE;
4762 offset1 = BNX2_L2CTX_CMD_TYPE;
4763 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4764 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4766 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4767 bnx2_ctx_wr(bp, cid_addr, offset0, val);
4769 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4770 bnx2_ctx_wr(bp, cid_addr, offset1, val);
4772 val = (u64) txr->tx_desc_mapping >> 32;
4773 bnx2_ctx_wr(bp, cid_addr, offset2, val);
4775 val = (u64) txr->tx_desc_mapping & 0xffffffff;
4776 bnx2_ctx_wr(bp, cid_addr, offset3, val);
4780 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
4784 struct bnx2_napi *bnapi;
4785 struct bnx2_tx_ring_info *txr;
4787 bnapi = &bp->bnx2_napi[ring_num];
4788 txr = &bnapi->tx_ring;
4793 cid = TX_TSS_CID + ring_num - 1;
4795 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4797 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
4799 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
4800 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
4803 txr->tx_prod_bseq = 0;
4805 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4806 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4808 bnx2_init_tx_context(bp, cid, txr);
4812 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4818 for (i = 0; i < num_rings; i++) {
4821 rxbd = &rx_ring[i][0];
4822 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4823 rxbd->rx_bd_len = buf_size;
4824 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4826 if (i == (num_rings - 1))
4830 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4831 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4836 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
4839 u16 prod, ring_prod;
4840 u32 cid, rx_cid_addr, val;
4841 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
4842 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
4847 cid = RX_RSS_CID + ring_num - 1;
4849 rx_cid_addr = GET_CID_ADDR(cid);
4851 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
4852 bp->rx_buf_use_size, bp->rx_max_ring);
4854 bnx2_init_rx_context(bp, cid);
4856 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4857 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4858 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4861 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4862 if (bp->rx_pg_ring_size) {
4863 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
4864 rxr->rx_pg_desc_mapping,
4865 PAGE_SIZE, bp->rx_max_pg_ring);
4866 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4867 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4868 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4869 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
4871 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
4872 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4874 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
4875 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4877 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4878 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4881 val = (u64) rxr->rx_desc_mapping[0] >> 32;
4882 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4884 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
4885 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4887 ring_prod = prod = rxr->rx_pg_prod;
4888 for (i = 0; i < bp->rx_pg_ring_size; i++) {
4889 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
4891 prod = NEXT_RX_BD(prod);
4892 ring_prod = RX_PG_RING_IDX(prod);
4894 rxr->rx_pg_prod = prod;
4896 ring_prod = prod = rxr->rx_prod;
4897 for (i = 0; i < bp->rx_ring_size; i++) {
4898 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
4900 prod = NEXT_RX_BD(prod);
4901 ring_prod = RX_RING_IDX(prod);
4903 rxr->rx_prod = prod;
4905 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
4906 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
4907 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
4909 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
4910 REG_WR16(bp, rxr->rx_bidx_addr, prod);
4912 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
4916 bnx2_init_all_rings(struct bnx2 *bp)
4921 bnx2_clear_ring_states(bp);
4923 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
4924 for (i = 0; i < bp->num_tx_rings; i++)
4925 bnx2_init_tx_ring(bp, i);
4927 if (bp->num_tx_rings > 1)
4928 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
4931 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
4932 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
4934 for (i = 0; i < bp->num_rx_rings; i++)
4935 bnx2_init_rx_ring(bp, i);
4937 if (bp->num_rx_rings > 1) {
4939 u8 *tbl = (u8 *) &tbl_32;
4941 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
4942 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
4944 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
4945 tbl[i % 4] = i % (bp->num_rx_rings - 1);
4948 BNX2_RXP_SCRATCH_RSS_TBL + i,
4949 cpu_to_be32(tbl_32));
4952 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
4953 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
4955 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
4960 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
4962 u32 max, num_rings = 1;
4964 while (ring_size > MAX_RX_DESC_CNT) {
4965 ring_size -= MAX_RX_DESC_CNT;
4968 /* round to next power of 2 */
4970 while ((max & num_rings) == 0)
4973 if (num_rings != max)
4980 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4982 u32 rx_size, rx_space, jumbo_size;
4984 /* 8 for CRC and VLAN */
4985 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
4987 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4988 sizeof(struct skb_shared_info);
4990 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
4991 bp->rx_pg_ring_size = 0;
4992 bp->rx_max_pg_ring = 0;
4993 bp->rx_max_pg_ring_idx = 0;
4994 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
4995 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4997 jumbo_size = size * pages;
4998 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4999 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
5001 bp->rx_pg_ring_size = jumbo_size;
5002 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
5004 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
5005 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
5006 bp->rx_copy_thresh = 0;
5009 bp->rx_buf_use_size = rx_size;
5011 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
5012 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
5013 bp->rx_ring_size = size;
5014 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
5015 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
5019 bnx2_free_tx_skbs(struct bnx2 *bp)
5023 for (i = 0; i < bp->num_tx_rings; i++) {
5024 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5025 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5028 if (txr->tx_buf_ring == NULL)
5031 for (j = 0; j < TX_DESC_CNT; ) {
5032 struct sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
5033 struct sk_buff *skb = tx_buf->skb;
5040 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5044 j += skb_shinfo(skb)->nr_frags + 1;
5051 bnx2_free_rx_skbs(struct bnx2 *bp)
5055 for (i = 0; i < bp->num_rx_rings; i++) {
5056 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5057 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5060 if (rxr->rx_buf_ring == NULL)
5063 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5064 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5065 struct sk_buff *skb = rx_buf->skb;
5070 pci_unmap_single(bp->pdev,
5071 pci_unmap_addr(rx_buf, mapping),
5072 bp->rx_buf_use_size,
5073 PCI_DMA_FROMDEVICE);
5079 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5080 bnx2_free_rx_page(bp, rxr, j);
5085 bnx2_free_skbs(struct bnx2 *bp)
5087 bnx2_free_tx_skbs(bp);
5088 bnx2_free_rx_skbs(bp);
5092 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5096 rc = bnx2_reset_chip(bp, reset_code);
5101 if ((rc = bnx2_init_chip(bp)) != 0)
5104 bnx2_init_all_rings(bp);
5109 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5113 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5116 spin_lock_bh(&bp->phy_lock);
5117 bnx2_init_phy(bp, reset_phy);
5119 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5120 bnx2_remote_phy_event(bp);
5121 spin_unlock_bh(&bp->phy_lock);
5126 bnx2_shutdown_chip(struct bnx2 *bp)
5130 if (bp->flags & BNX2_FLAG_NO_WOL)
5131 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5133 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5135 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5137 return bnx2_reset_chip(bp, reset_code);
5141 bnx2_test_registers(struct bnx2 *bp)
5145 static const struct {
5148 #define BNX2_FL_NOT_5709 1
5152 { 0x006c, 0, 0x00000000, 0x0000003f },
5153 { 0x0090, 0, 0xffffffff, 0x00000000 },
5154 { 0x0094, 0, 0x00000000, 0x00000000 },
5156 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5157 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5158 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5159 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5160 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5161 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5162 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5163 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5164 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5166 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5167 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5168 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5169 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5170 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5171 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5173 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5174 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5175 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
5177 { 0x1000, 0, 0x00000000, 0x00000001 },
5178 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5180 { 0x1408, 0, 0x01c00800, 0x00000000 },
5181 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5182 { 0x14a8, 0, 0x00000000, 0x000001ff },
5183 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5184 { 0x14b0, 0, 0x00000002, 0x00000001 },
5185 { 0x14b8, 0, 0x00000000, 0x00000000 },
5186 { 0x14c0, 0, 0x00000000, 0x00000009 },
5187 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5188 { 0x14cc, 0, 0x00000000, 0x00000001 },
5189 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5191 { 0x1800, 0, 0x00000000, 0x00000001 },
5192 { 0x1804, 0, 0x00000000, 0x00000003 },
5194 { 0x2800, 0, 0x00000000, 0x00000001 },
5195 { 0x2804, 0, 0x00000000, 0x00003f01 },
5196 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5197 { 0x2810, 0, 0xffff0000, 0x00000000 },
5198 { 0x2814, 0, 0xffff0000, 0x00000000 },
5199 { 0x2818, 0, 0xffff0000, 0x00000000 },
5200 { 0x281c, 0, 0xffff0000, 0x00000000 },
5201 { 0x2834, 0, 0xffffffff, 0x00000000 },
5202 { 0x2840, 0, 0x00000000, 0xffffffff },
5203 { 0x2844, 0, 0x00000000, 0xffffffff },
5204 { 0x2848, 0, 0xffffffff, 0x00000000 },
5205 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5207 { 0x2c00, 0, 0x00000000, 0x00000011 },
5208 { 0x2c04, 0, 0x00000000, 0x00030007 },
5210 { 0x3c00, 0, 0x00000000, 0x00000001 },
5211 { 0x3c04, 0, 0x00000000, 0x00070000 },
5212 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5213 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5214 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5215 { 0x3c14, 0, 0x00000000, 0xffffffff },
5216 { 0x3c18, 0, 0x00000000, 0xffffffff },
5217 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5218 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5220 { 0x5004, 0, 0x00000000, 0x0000007f },
5221 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5223 { 0x5c00, 0, 0x00000000, 0x00000001 },
5224 { 0x5c04, 0, 0x00000000, 0x0003000f },
5225 { 0x5c08, 0, 0x00000003, 0x00000000 },
5226 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5227 { 0x5c10, 0, 0x00000000, 0xffffffff },
5228 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5229 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5230 { 0x5c88, 0, 0x00000000, 0x00077373 },
5231 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5233 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5234 { 0x680c, 0, 0xffffffff, 0x00000000 },
5235 { 0x6810, 0, 0xffffffff, 0x00000000 },
5236 { 0x6814, 0, 0xffffffff, 0x00000000 },
5237 { 0x6818, 0, 0xffffffff, 0x00000000 },
5238 { 0x681c, 0, 0xffffffff, 0x00000000 },
5239 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5240 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5241 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5242 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5243 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5244 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5245 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5246 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5247 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5248 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5249 { 0x684c, 0, 0xffffffff, 0x00000000 },
5250 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5251 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5252 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5253 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5254 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5255 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5257 { 0xffff, 0, 0x00000000, 0x00000000 },
5262 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5265 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5266 u32 offset, rw_mask, ro_mask, save_val, val;
5267 u16 flags = reg_tbl[i].flags;
5269 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5272 offset = (u32) reg_tbl[i].offset;
5273 rw_mask = reg_tbl[i].rw_mask;
5274 ro_mask = reg_tbl[i].ro_mask;
5276 save_val = readl(bp->regview + offset);
5278 writel(0, bp->regview + offset);
5280 val = readl(bp->regview + offset);
5281 if ((val & rw_mask) != 0) {
5285 if ((val & ro_mask) != (save_val & ro_mask)) {
5289 writel(0xffffffff, bp->regview + offset);
5291 val = readl(bp->regview + offset);
5292 if ((val & rw_mask) != rw_mask) {
5296 if ((val & ro_mask) != (save_val & ro_mask)) {
5300 writel(save_val, bp->regview + offset);
5304 writel(save_val, bp->regview + offset);
5312 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5314 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5315 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5318 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5321 for (offset = 0; offset < size; offset += 4) {
5323 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5325 if (bnx2_reg_rd_ind(bp, start + offset) !=
5335 bnx2_test_memory(struct bnx2 *bp)
5339 static struct mem_entry {
5342 } mem_tbl_5706[] = {
5343 { 0x60000, 0x4000 },
5344 { 0xa0000, 0x3000 },
5345 { 0xe0000, 0x4000 },
5346 { 0x120000, 0x4000 },
5347 { 0x1a0000, 0x4000 },
5348 { 0x160000, 0x4000 },
5352 { 0x60000, 0x4000 },
5353 { 0xa0000, 0x3000 },
5354 { 0xe0000, 0x4000 },
5355 { 0x120000, 0x4000 },
5356 { 0x1a0000, 0x4000 },
5359 struct mem_entry *mem_tbl;
5361 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5362 mem_tbl = mem_tbl_5709;
5364 mem_tbl = mem_tbl_5706;
5366 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5367 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5368 mem_tbl[i].len)) != 0) {
5376 #define BNX2_MAC_LOOPBACK 0
5377 #define BNX2_PHY_LOOPBACK 1
5380 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5382 unsigned int pkt_size, num_pkts, i;
5383 struct sk_buff *skb, *rx_skb;
5384 unsigned char *packet;
5385 u16 rx_start_idx, rx_idx;
5388 struct sw_bd *rx_buf;
5389 struct l2_fhdr *rx_hdr;
5391 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5392 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5393 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5397 txr = &tx_napi->tx_ring;
5398 rxr = &bnapi->rx_ring;
5399 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5400 bp->loopback = MAC_LOOPBACK;
5401 bnx2_set_mac_loopback(bp);
5403 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5404 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5407 bp->loopback = PHY_LOOPBACK;
5408 bnx2_set_phy_loopback(bp);
5413 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5414 skb = netdev_alloc_skb(bp->dev, pkt_size);
5417 packet = skb_put(skb, pkt_size);
5418 memcpy(packet, bp->dev->dev_addr, 6);
5419 memset(packet + 6, 0x0, 8);
5420 for (i = 14; i < pkt_size; i++)
5421 packet[i] = (unsigned char) (i & 0xff);
5423 if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
5427 map = skb_shinfo(skb)->dma_maps[0];
5429 REG_WR(bp, BNX2_HC_COMMAND,
5430 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5432 REG_RD(bp, BNX2_HC_COMMAND);
5435 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5439 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5441 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5442 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5443 txbd->tx_bd_mss_nbytes = pkt_size;
5444 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5447 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5448 txr->tx_prod_bseq += pkt_size;
5450 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5451 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5455 REG_WR(bp, BNX2_HC_COMMAND,
5456 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5458 REG_RD(bp, BNX2_HC_COMMAND);
5462 skb_dma_unmap(&bp->pdev->dev, skb, DMA_TO_DEVICE);
5465 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5466 goto loopback_test_done;
5468 rx_idx = bnx2_get_hw_rx_cons(bnapi);
5469 if (rx_idx != rx_start_idx + num_pkts) {
5470 goto loopback_test_done;
5473 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5474 rx_skb = rx_buf->skb;
5476 rx_hdr = (struct l2_fhdr *) rx_skb->data;
5477 skb_reserve(rx_skb, BNX2_RX_OFFSET);
5479 pci_dma_sync_single_for_cpu(bp->pdev,
5480 pci_unmap_addr(rx_buf, mapping),
5481 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5483 if (rx_hdr->l2_fhdr_status &
5484 (L2_FHDR_ERRORS_BAD_CRC |
5485 L2_FHDR_ERRORS_PHY_DECODE |
5486 L2_FHDR_ERRORS_ALIGNMENT |
5487 L2_FHDR_ERRORS_TOO_SHORT |
5488 L2_FHDR_ERRORS_GIANT_FRAME)) {
5490 goto loopback_test_done;
5493 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5494 goto loopback_test_done;
5497 for (i = 14; i < pkt_size; i++) {
5498 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5499 goto loopback_test_done;
5510 #define BNX2_MAC_LOOPBACK_FAILED 1
5511 #define BNX2_PHY_LOOPBACK_FAILED 2
5512 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5513 BNX2_PHY_LOOPBACK_FAILED)
5516 bnx2_test_loopback(struct bnx2 *bp)
5520 if (!netif_running(bp->dev))
5521 return BNX2_LOOPBACK_FAILED;
5523 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5524 spin_lock_bh(&bp->phy_lock);
5525 bnx2_init_phy(bp, 1);
5526 spin_unlock_bh(&bp->phy_lock);
5527 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5528 rc |= BNX2_MAC_LOOPBACK_FAILED;
5529 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5530 rc |= BNX2_PHY_LOOPBACK_FAILED;
5534 #define NVRAM_SIZE 0x200
5535 #define CRC32_RESIDUAL 0xdebb20e3
5538 bnx2_test_nvram(struct bnx2 *bp)
5540 __be32 buf[NVRAM_SIZE / 4];
5541 u8 *data = (u8 *) buf;
5545 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5546 goto test_nvram_done;
5548 magic = be32_to_cpu(buf[0]);
5549 if (magic != 0x669955aa) {
5551 goto test_nvram_done;
5554 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5555 goto test_nvram_done;
5557 csum = ether_crc_le(0x100, data);
5558 if (csum != CRC32_RESIDUAL) {
5560 goto test_nvram_done;
5563 csum = ether_crc_le(0x100, data + 0x100);
5564 if (csum != CRC32_RESIDUAL) {
5573 bnx2_test_link(struct bnx2 *bp)
5577 if (!netif_running(bp->dev))
5580 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5585 spin_lock_bh(&bp->phy_lock);
5586 bnx2_enable_bmsr1(bp);
5587 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5588 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5589 bnx2_disable_bmsr1(bp);
5590 spin_unlock_bh(&bp->phy_lock);
5592 if (bmsr & BMSR_LSTATUS) {
5599 bnx2_test_intr(struct bnx2 *bp)
5604 if (!netif_running(bp->dev))
5607 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5609 /* This register is not touched during run-time. */
5610 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5611 REG_RD(bp, BNX2_HC_COMMAND);
5613 for (i = 0; i < 10; i++) {
5614 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5620 msleep_interruptible(10);
5628 /* Determining link for parallel detection. */
5630 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5632 u32 mode_ctl, an_dbg, exp;
5634 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5637 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5638 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5640 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5643 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5644 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5645 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5647 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5650 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5651 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5652 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5654 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5661 bnx2_5706_serdes_timer(struct bnx2 *bp)
5665 spin_lock(&bp->phy_lock);
5666 if (bp->serdes_an_pending) {
5667 bp->serdes_an_pending--;
5669 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5672 bp->current_interval = BNX2_TIMER_INTERVAL;
5674 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5676 if (bmcr & BMCR_ANENABLE) {
5677 if (bnx2_5706_serdes_has_link(bp)) {
5678 bmcr &= ~BMCR_ANENABLE;
5679 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5680 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5681 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5685 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5686 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5689 bnx2_write_phy(bp, 0x17, 0x0f01);
5690 bnx2_read_phy(bp, 0x15, &phy2);
5694 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5695 bmcr |= BMCR_ANENABLE;
5696 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5698 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5701 bp->current_interval = BNX2_TIMER_INTERVAL;
5706 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5707 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5708 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5710 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5711 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5712 bnx2_5706s_force_link_dn(bp, 1);
5713 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5716 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5719 spin_unlock(&bp->phy_lock);
5723 bnx2_5708_serdes_timer(struct bnx2 *bp)
5725 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5728 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5729 bp->serdes_an_pending = 0;
5733 spin_lock(&bp->phy_lock);
5734 if (bp->serdes_an_pending)
5735 bp->serdes_an_pending--;
5736 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5739 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5740 if (bmcr & BMCR_ANENABLE) {
5741 bnx2_enable_forced_2g5(bp);
5742 bp->current_interval = BNX2_SERDES_FORCED_TIMEOUT;
5744 bnx2_disable_forced_2g5(bp);
5745 bp->serdes_an_pending = 2;
5746 bp->current_interval = BNX2_TIMER_INTERVAL;
5750 bp->current_interval = BNX2_TIMER_INTERVAL;
5752 spin_unlock(&bp->phy_lock);
5756 bnx2_timer(unsigned long data)
5758 struct bnx2 *bp = (struct bnx2 *) data;
5760 if (!netif_running(bp->dev))
5763 if (atomic_read(&bp->intr_sem) != 0)
5764 goto bnx2_restart_timer;
5766 if ((bp->flags & (BNX2_FLAG_USING_MSI | BNX2_FLAG_ONE_SHOT_MSI)) ==
5767 BNX2_FLAG_USING_MSI)
5768 bnx2_chk_missed_msi(bp);
5770 bnx2_send_heart_beat(bp);
5772 bp->stats_blk->stat_FwRxDrop =
5773 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
5775 /* workaround occasional corrupted counters */
5776 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5777 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5778 BNX2_HC_COMMAND_STATS_NOW);
5780 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5781 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5782 bnx2_5706_serdes_timer(bp);
5784 bnx2_5708_serdes_timer(bp);
5788 mod_timer(&bp->timer, jiffies + bp->current_interval);
5792 bnx2_request_irq(struct bnx2 *bp)
5794 unsigned long flags;
5795 struct bnx2_irq *irq;
5798 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
5801 flags = IRQF_SHARED;
5803 for (i = 0; i < bp->irq_nvecs; i++) {
5804 irq = &bp->irq_tbl[i];
5805 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5815 bnx2_free_irq(struct bnx2 *bp)
5817 struct bnx2_irq *irq;
5820 for (i = 0; i < bp->irq_nvecs; i++) {
5821 irq = &bp->irq_tbl[i];
5823 free_irq(irq->vector, &bp->bnx2_napi[i]);
5826 if (bp->flags & BNX2_FLAG_USING_MSI)
5827 pci_disable_msi(bp->pdev);
5828 else if (bp->flags & BNX2_FLAG_USING_MSIX)
5829 pci_disable_msix(bp->pdev);
5831 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
5835 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
5838 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5839 struct net_device *dev = bp->dev;
5840 const int len = sizeof(bp->irq_tbl[0].name);
5842 bnx2_setup_msix_tbl(bp);
5843 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5844 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5845 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
5847 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5848 msix_ent[i].entry = i;
5849 msix_ent[i].vector = 0;
5851 snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i);
5852 bp->irq_tbl[i].handler = bnx2_msi_1shot;
5855 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5859 bp->irq_nvecs = msix_vecs;
5860 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
5861 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5862 bp->irq_tbl[i].vector = msix_ent[i].vector;
5866 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5868 int cpus = num_online_cpus();
5869 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5871 bp->irq_tbl[0].handler = bnx2_interrupt;
5872 strcpy(bp->irq_tbl[0].name, bp->dev->name);
5874 bp->irq_tbl[0].vector = bp->pdev->irq;
5876 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
5877 bnx2_enable_msix(bp, msix_vecs);
5879 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5880 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
5881 if (pci_enable_msi(bp->pdev) == 0) {
5882 bp->flags |= BNX2_FLAG_USING_MSI;
5883 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5884 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
5885 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5887 bp->irq_tbl[0].handler = bnx2_msi;
5889 bp->irq_tbl[0].vector = bp->pdev->irq;
5893 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
5894 bp->dev->real_num_tx_queues = bp->num_tx_rings;
5896 bp->num_rx_rings = bp->irq_nvecs;
5899 /* Called with rtnl_lock */
5901 bnx2_open(struct net_device *dev)
5903 struct bnx2 *bp = netdev_priv(dev);
5906 netif_carrier_off(dev);
5908 bnx2_set_power_state(bp, PCI_D0);
5909 bnx2_disable_int(bp);
5911 bnx2_setup_int_mode(bp, disable_msi);
5912 bnx2_napi_enable(bp);
5913 rc = bnx2_alloc_mem(bp);
5917 rc = bnx2_request_irq(bp);
5921 rc = bnx2_init_nic(bp, 1);
5925 mod_timer(&bp->timer, jiffies + bp->current_interval);
5927 atomic_set(&bp->intr_sem, 0);
5929 bnx2_enable_int(bp);
5931 if (bp->flags & BNX2_FLAG_USING_MSI) {
5932 /* Test MSI to make sure it is working
5933 * If MSI test fails, go back to INTx mode
5935 if (bnx2_test_intr(bp) != 0) {
5936 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5937 " using MSI, switching to INTx mode. Please"
5938 " report this failure to the PCI maintainer"
5939 " and include system chipset information.\n",
5942 bnx2_disable_int(bp);
5945 bnx2_setup_int_mode(bp, 1);
5947 rc = bnx2_init_nic(bp, 0);
5950 rc = bnx2_request_irq(bp);
5953 del_timer_sync(&bp->timer);
5956 bnx2_enable_int(bp);
5959 if (bp->flags & BNX2_FLAG_USING_MSI)
5960 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5961 else if (bp->flags & BNX2_FLAG_USING_MSIX)
5962 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
5964 netif_tx_start_all_queues(dev);
5969 bnx2_napi_disable(bp);
5977 bnx2_reset_task(struct work_struct *work)
5979 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5981 if (!netif_running(bp->dev))
5984 bnx2_netif_stop(bp);
5986 bnx2_init_nic(bp, 1);
5988 atomic_set(&bp->intr_sem, 1);
5989 bnx2_netif_start(bp);
5993 bnx2_tx_timeout(struct net_device *dev)
5995 struct bnx2 *bp = netdev_priv(dev);
5997 /* This allows the netif to be shutdown gracefully before resetting */
5998 schedule_work(&bp->reset_task);
6002 /* Called with rtnl_lock */
6004 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
6006 struct bnx2 *bp = netdev_priv(dev);
6008 bnx2_netif_stop(bp);
6011 bnx2_set_rx_mode(dev);
6012 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
6013 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
6015 bnx2_netif_start(bp);
6019 /* Called with netif_tx_lock.
6020 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
6021 * netif_wake_queue().
6024 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
6026 struct bnx2 *bp = netdev_priv(dev);
6029 struct sw_tx_bd *tx_buf;
6030 u32 len, vlan_tag_flags, last_frag, mss;
6031 u16 prod, ring_prod;
6033 struct bnx2_napi *bnapi;
6034 struct bnx2_tx_ring_info *txr;
6035 struct netdev_queue *txq;
6036 struct skb_shared_info *sp;
6038 /* Determine which tx ring we will be placed on */
6039 i = skb_get_queue_mapping(skb);
6040 bnapi = &bp->bnx2_napi[i];
6041 txr = &bnapi->tx_ring;
6042 txq = netdev_get_tx_queue(dev, i);
6044 if (unlikely(bnx2_tx_avail(bp, txr) <
6045 (skb_shinfo(skb)->nr_frags + 1))) {
6046 netif_tx_stop_queue(txq);
6047 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
6050 return NETDEV_TX_BUSY;
6052 len = skb_headlen(skb);
6053 prod = txr->tx_prod;
6054 ring_prod = TX_RING_IDX(prod);
6057 if (skb->ip_summed == CHECKSUM_PARTIAL) {
6058 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6062 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6064 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6067 if ((mss = skb_shinfo(skb)->gso_size)) {
6071 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6073 tcp_opt_len = tcp_optlen(skb);
6075 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6076 u32 tcp_off = skb_transport_offset(skb) -
6077 sizeof(struct ipv6hdr) - ETH_HLEN;
6079 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6080 TX_BD_FLAGS_SW_FLAGS;
6081 if (likely(tcp_off == 0))
6082 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6085 vlan_tag_flags |= ((tcp_off & 0x3) <<
6086 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6087 ((tcp_off & 0x10) <<
6088 TX_BD_FLAGS_TCP6_OFF4_SHL);
6089 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6093 if (tcp_opt_len || (iph->ihl > 5)) {
6094 vlan_tag_flags |= ((iph->ihl - 5) +
6095 (tcp_opt_len >> 2)) << 8;
6101 if (skb_dma_map(&bp->pdev->dev, skb, DMA_TO_DEVICE)) {
6103 return NETDEV_TX_OK;
6106 sp = skb_shinfo(skb);
6107 mapping = sp->dma_maps[0];
6109 tx_buf = &txr->tx_buf_ring[ring_prod];
6112 txbd = &txr->tx_desc_ring[ring_prod];
6114 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6115 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6116 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6117 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6119 last_frag = skb_shinfo(skb)->nr_frags;
6121 for (i = 0; i < last_frag; i++) {
6122 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6124 prod = NEXT_TX_BD(prod);
6125 ring_prod = TX_RING_IDX(prod);
6126 txbd = &txr->tx_desc_ring[ring_prod];
6129 mapping = sp->dma_maps[i + 1];
6131 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6132 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6133 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6134 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6137 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6139 prod = NEXT_TX_BD(prod);
6140 txr->tx_prod_bseq += skb->len;
6142 REG_WR16(bp, txr->tx_bidx_addr, prod);
6143 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6147 txr->tx_prod = prod;
6148 dev->trans_start = jiffies;
6150 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6151 netif_tx_stop_queue(txq);
6152 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6153 netif_tx_wake_queue(txq);
6156 return NETDEV_TX_OK;
6159 /* Called with rtnl_lock */
6161 bnx2_close(struct net_device *dev)
6163 struct bnx2 *bp = netdev_priv(dev);
6165 cancel_work_sync(&bp->reset_task);
6167 bnx2_disable_int_sync(bp);
6168 bnx2_napi_disable(bp);
6169 del_timer_sync(&bp->timer);
6170 bnx2_shutdown_chip(bp);
6175 netif_carrier_off(bp->dev);
6176 bnx2_set_power_state(bp, PCI_D3hot);
6180 #define GET_NET_STATS64(ctr) \
6181 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
6182 (unsigned long) (ctr##_lo)
6184 #define GET_NET_STATS32(ctr) \
6187 #if (BITS_PER_LONG == 64)
6188 #define GET_NET_STATS GET_NET_STATS64
6190 #define GET_NET_STATS GET_NET_STATS32
6193 static struct net_device_stats *
6194 bnx2_get_stats(struct net_device *dev)
6196 struct bnx2 *bp = netdev_priv(dev);
6197 struct statistics_block *stats_blk = bp->stats_blk;
6198 struct net_device_stats *net_stats = &dev->stats;
6200 if (bp->stats_blk == NULL) {
6203 net_stats->rx_packets =
6204 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6205 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6206 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6208 net_stats->tx_packets =
6209 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6210 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6211 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6213 net_stats->rx_bytes =
6214 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6216 net_stats->tx_bytes =
6217 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6219 net_stats->multicast =
6220 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6222 net_stats->collisions =
6223 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6225 net_stats->rx_length_errors =
6226 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6227 stats_blk->stat_EtherStatsOverrsizePkts);
6229 net_stats->rx_over_errors =
6230 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
6232 net_stats->rx_frame_errors =
6233 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6235 net_stats->rx_crc_errors =
6236 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6238 net_stats->rx_errors = net_stats->rx_length_errors +
6239 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6240 net_stats->rx_crc_errors;
6242 net_stats->tx_aborted_errors =
6243 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6244 stats_blk->stat_Dot3StatsLateCollisions);
6246 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6247 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6248 net_stats->tx_carrier_errors = 0;
6250 net_stats->tx_carrier_errors =
6252 stats_blk->stat_Dot3StatsCarrierSenseErrors;
6255 net_stats->tx_errors =
6257 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6259 net_stats->tx_aborted_errors +
6260 net_stats->tx_carrier_errors;
6262 net_stats->rx_missed_errors =
6263 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6264 stats_blk->stat_FwRxDrop);
6269 /* All ethtool functions called with rtnl_lock */
6272 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6274 struct bnx2 *bp = netdev_priv(dev);
6275 int support_serdes = 0, support_copper = 0;
6277 cmd->supported = SUPPORTED_Autoneg;
6278 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6281 } else if (bp->phy_port == PORT_FIBRE)
6286 if (support_serdes) {
6287 cmd->supported |= SUPPORTED_1000baseT_Full |
6289 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6290 cmd->supported |= SUPPORTED_2500baseX_Full;
6293 if (support_copper) {
6294 cmd->supported |= SUPPORTED_10baseT_Half |
6295 SUPPORTED_10baseT_Full |
6296 SUPPORTED_100baseT_Half |
6297 SUPPORTED_100baseT_Full |
6298 SUPPORTED_1000baseT_Full |
6303 spin_lock_bh(&bp->phy_lock);
6304 cmd->port = bp->phy_port;
6305 cmd->advertising = bp->advertising;
6307 if (bp->autoneg & AUTONEG_SPEED) {
6308 cmd->autoneg = AUTONEG_ENABLE;
6311 cmd->autoneg = AUTONEG_DISABLE;
6314 if (netif_carrier_ok(dev)) {
6315 cmd->speed = bp->line_speed;
6316 cmd->duplex = bp->duplex;
6322 spin_unlock_bh(&bp->phy_lock);
6324 cmd->transceiver = XCVR_INTERNAL;
6325 cmd->phy_address = bp->phy_addr;
6331 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6333 struct bnx2 *bp = netdev_priv(dev);
6334 u8 autoneg = bp->autoneg;
6335 u8 req_duplex = bp->req_duplex;
6336 u16 req_line_speed = bp->req_line_speed;
6337 u32 advertising = bp->advertising;
6340 spin_lock_bh(&bp->phy_lock);
6342 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6343 goto err_out_unlock;
6345 if (cmd->port != bp->phy_port &&
6346 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6347 goto err_out_unlock;
6349 /* If device is down, we can store the settings only if the user
6350 * is setting the currently active port.
6352 if (!netif_running(dev) && cmd->port != bp->phy_port)
6353 goto err_out_unlock;
6355 if (cmd->autoneg == AUTONEG_ENABLE) {
6356 autoneg |= AUTONEG_SPEED;
6358 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6360 /* allow advertising 1 speed */
6361 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6362 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6363 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6364 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6366 if (cmd->port == PORT_FIBRE)
6367 goto err_out_unlock;
6369 advertising = cmd->advertising;
6371 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6372 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6373 (cmd->port == PORT_TP))
6374 goto err_out_unlock;
6375 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6376 advertising = cmd->advertising;
6377 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6378 goto err_out_unlock;
6380 if (cmd->port == PORT_FIBRE)
6381 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6383 advertising = ETHTOOL_ALL_COPPER_SPEED;
6385 advertising |= ADVERTISED_Autoneg;
6388 if (cmd->port == PORT_FIBRE) {
6389 if ((cmd->speed != SPEED_1000 &&
6390 cmd->speed != SPEED_2500) ||
6391 (cmd->duplex != DUPLEX_FULL))
6392 goto err_out_unlock;
6394 if (cmd->speed == SPEED_2500 &&
6395 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6396 goto err_out_unlock;
6398 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6399 goto err_out_unlock;
6401 autoneg &= ~AUTONEG_SPEED;
6402 req_line_speed = cmd->speed;
6403 req_duplex = cmd->duplex;
6407 bp->autoneg = autoneg;
6408 bp->advertising = advertising;
6409 bp->req_line_speed = req_line_speed;
6410 bp->req_duplex = req_duplex;
6413 /* If device is down, the new settings will be picked up when it is
6416 if (netif_running(dev))
6417 err = bnx2_setup_phy(bp, cmd->port);
6420 spin_unlock_bh(&bp->phy_lock);
6426 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6428 struct bnx2 *bp = netdev_priv(dev);
6430 strcpy(info->driver, DRV_MODULE_NAME);
6431 strcpy(info->version, DRV_MODULE_VERSION);
6432 strcpy(info->bus_info, pci_name(bp->pdev));
6433 strcpy(info->fw_version, bp->fw_version);
6436 #define BNX2_REGDUMP_LEN (32 * 1024)
6439 bnx2_get_regs_len(struct net_device *dev)
6441 return BNX2_REGDUMP_LEN;
6445 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6447 u32 *p = _p, i, offset;
6449 struct bnx2 *bp = netdev_priv(dev);
6450 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6451 0x0800, 0x0880, 0x0c00, 0x0c10,
6452 0x0c30, 0x0d08, 0x1000, 0x101c,
6453 0x1040, 0x1048, 0x1080, 0x10a4,
6454 0x1400, 0x1490, 0x1498, 0x14f0,
6455 0x1500, 0x155c, 0x1580, 0x15dc,
6456 0x1600, 0x1658, 0x1680, 0x16d8,
6457 0x1800, 0x1820, 0x1840, 0x1854,
6458 0x1880, 0x1894, 0x1900, 0x1984,
6459 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6460 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6461 0x2000, 0x2030, 0x23c0, 0x2400,
6462 0x2800, 0x2820, 0x2830, 0x2850,
6463 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6464 0x3c00, 0x3c94, 0x4000, 0x4010,
6465 0x4080, 0x4090, 0x43c0, 0x4458,
6466 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6467 0x4fc0, 0x5010, 0x53c0, 0x5444,
6468 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6469 0x5fc0, 0x6000, 0x6400, 0x6428,
6470 0x6800, 0x6848, 0x684c, 0x6860,
6471 0x6888, 0x6910, 0x8000 };
6475 memset(p, 0, BNX2_REGDUMP_LEN);
6477 if (!netif_running(bp->dev))
6481 offset = reg_boundaries[0];
6483 while (offset < BNX2_REGDUMP_LEN) {
6484 *p++ = REG_RD(bp, offset);
6486 if (offset == reg_boundaries[i + 1]) {
6487 offset = reg_boundaries[i + 2];
6488 p = (u32 *) (orig_p + offset);
6495 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6497 struct bnx2 *bp = netdev_priv(dev);
6499 if (bp->flags & BNX2_FLAG_NO_WOL) {
6504 wol->supported = WAKE_MAGIC;
6506 wol->wolopts = WAKE_MAGIC;
6510 memset(&wol->sopass, 0, sizeof(wol->sopass));
6514 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6516 struct bnx2 *bp = netdev_priv(dev);
6518 if (wol->wolopts & ~WAKE_MAGIC)
6521 if (wol->wolopts & WAKE_MAGIC) {
6522 if (bp->flags & BNX2_FLAG_NO_WOL)
6534 bnx2_nway_reset(struct net_device *dev)
6536 struct bnx2 *bp = netdev_priv(dev);
6539 if (!netif_running(dev))
6542 if (!(bp->autoneg & AUTONEG_SPEED)) {
6546 spin_lock_bh(&bp->phy_lock);
6548 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6551 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6552 spin_unlock_bh(&bp->phy_lock);
6556 /* Force a link down visible on the other side */
6557 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6558 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6559 spin_unlock_bh(&bp->phy_lock);
6563 spin_lock_bh(&bp->phy_lock);
6565 bp->current_interval = BNX2_SERDES_AN_TIMEOUT;
6566 bp->serdes_an_pending = 1;
6567 mod_timer(&bp->timer, jiffies + bp->current_interval);
6570 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6571 bmcr &= ~BMCR_LOOPBACK;
6572 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6574 spin_unlock_bh(&bp->phy_lock);
6580 bnx2_get_eeprom_len(struct net_device *dev)
6582 struct bnx2 *bp = netdev_priv(dev);
6584 if (bp->flash_info == NULL)
6587 return (int) bp->flash_size;
6591 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6594 struct bnx2 *bp = netdev_priv(dev);
6597 if (!netif_running(dev))
6600 /* parameters already validated in ethtool_get_eeprom */
6602 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6608 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6611 struct bnx2 *bp = netdev_priv(dev);
6614 if (!netif_running(dev))
6617 /* parameters already validated in ethtool_set_eeprom */
6619 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6625 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6627 struct bnx2 *bp = netdev_priv(dev);
6629 memset(coal, 0, sizeof(struct ethtool_coalesce));
6631 coal->rx_coalesce_usecs = bp->rx_ticks;
6632 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6633 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6634 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6636 coal->tx_coalesce_usecs = bp->tx_ticks;
6637 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6638 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6639 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6641 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6647 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6649 struct bnx2 *bp = netdev_priv(dev);
6651 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6652 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6654 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6655 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6657 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6658 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6660 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6661 if (bp->rx_quick_cons_trip_int > 0xff)
6662 bp->rx_quick_cons_trip_int = 0xff;
6664 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6665 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6667 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6668 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6670 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6671 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6673 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6674 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6677 bp->stats_ticks = coal->stats_block_coalesce_usecs;
6678 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6679 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6680 bp->stats_ticks = USEC_PER_SEC;
6682 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6683 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6684 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6686 if (netif_running(bp->dev)) {
6687 bnx2_netif_stop(bp);
6688 bnx2_init_nic(bp, 0);
6689 bnx2_netif_start(bp);
6696 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6698 struct bnx2 *bp = netdev_priv(dev);
6700 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6701 ering->rx_mini_max_pending = 0;
6702 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6704 ering->rx_pending = bp->rx_ring_size;
6705 ering->rx_mini_pending = 0;
6706 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6708 ering->tx_max_pending = MAX_TX_DESC_CNT;
6709 ering->tx_pending = bp->tx_ring_size;
6713 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6715 if (netif_running(bp->dev)) {
6716 bnx2_netif_stop(bp);
6717 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6722 bnx2_set_rx_ring_size(bp, rx);
6723 bp->tx_ring_size = tx;
6725 if (netif_running(bp->dev)) {
6728 rc = bnx2_alloc_mem(bp);
6731 bnx2_init_nic(bp, 0);
6732 bnx2_netif_start(bp);
6738 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6740 struct bnx2 *bp = netdev_priv(dev);
6743 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6744 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6745 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6749 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6754 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6756 struct bnx2 *bp = netdev_priv(dev);
6758 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6759 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6760 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6764 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6766 struct bnx2 *bp = netdev_priv(dev);
6768 bp->req_flow_ctrl = 0;
6769 if (epause->rx_pause)
6770 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6771 if (epause->tx_pause)
6772 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6774 if (epause->autoneg) {
6775 bp->autoneg |= AUTONEG_FLOW_CTRL;
6778 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6781 if (netif_running(dev)) {
6782 spin_lock_bh(&bp->phy_lock);
6783 bnx2_setup_phy(bp, bp->phy_port);
6784 spin_unlock_bh(&bp->phy_lock);
6791 bnx2_get_rx_csum(struct net_device *dev)
6793 struct bnx2 *bp = netdev_priv(dev);
6799 bnx2_set_rx_csum(struct net_device *dev, u32 data)
6801 struct bnx2 *bp = netdev_priv(dev);
6808 bnx2_set_tso(struct net_device *dev, u32 data)
6810 struct bnx2 *bp = netdev_priv(dev);
6813 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6814 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6815 dev->features |= NETIF_F_TSO6;
6817 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6822 #define BNX2_NUM_STATS 46
6825 char string[ETH_GSTRING_LEN];
6826 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6828 { "rx_error_bytes" },
6830 { "tx_error_bytes" },
6831 { "rx_ucast_packets" },
6832 { "rx_mcast_packets" },
6833 { "rx_bcast_packets" },
6834 { "tx_ucast_packets" },
6835 { "tx_mcast_packets" },
6836 { "tx_bcast_packets" },
6837 { "tx_mac_errors" },
6838 { "tx_carrier_errors" },
6839 { "rx_crc_errors" },
6840 { "rx_align_errors" },
6841 { "tx_single_collisions" },
6842 { "tx_multi_collisions" },
6844 { "tx_excess_collisions" },
6845 { "tx_late_collisions" },
6846 { "tx_total_collisions" },
6849 { "rx_undersize_packets" },
6850 { "rx_oversize_packets" },
6851 { "rx_64_byte_packets" },
6852 { "rx_65_to_127_byte_packets" },
6853 { "rx_128_to_255_byte_packets" },
6854 { "rx_256_to_511_byte_packets" },
6855 { "rx_512_to_1023_byte_packets" },
6856 { "rx_1024_to_1522_byte_packets" },
6857 { "rx_1523_to_9022_byte_packets" },
6858 { "tx_64_byte_packets" },
6859 { "tx_65_to_127_byte_packets" },
6860 { "tx_128_to_255_byte_packets" },
6861 { "tx_256_to_511_byte_packets" },
6862 { "tx_512_to_1023_byte_packets" },
6863 { "tx_1024_to_1522_byte_packets" },
6864 { "tx_1523_to_9022_byte_packets" },
6865 { "rx_xon_frames" },
6866 { "rx_xoff_frames" },
6867 { "tx_xon_frames" },
6868 { "tx_xoff_frames" },
6869 { "rx_mac_ctrl_frames" },
6870 { "rx_filtered_packets" },
6872 { "rx_fw_discards" },
6875 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6877 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
6878 STATS_OFFSET32(stat_IfHCInOctets_hi),
6879 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6880 STATS_OFFSET32(stat_IfHCOutOctets_hi),
6881 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6882 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6883 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6884 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6885 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6886 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6887 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6888 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6889 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6890 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6891 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6892 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6893 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6894 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6895 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6896 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6897 STATS_OFFSET32(stat_EtherStatsCollisions),
6898 STATS_OFFSET32(stat_EtherStatsFragments),
6899 STATS_OFFSET32(stat_EtherStatsJabbers),
6900 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6901 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6902 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6903 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6904 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6905 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6906 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6907 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6908 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6909 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6910 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6911 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6912 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6913 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6914 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6915 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6916 STATS_OFFSET32(stat_XonPauseFramesReceived),
6917 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6918 STATS_OFFSET32(stat_OutXonSent),
6919 STATS_OFFSET32(stat_OutXoffSent),
6920 STATS_OFFSET32(stat_MacControlFramesReceived),
6921 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6922 STATS_OFFSET32(stat_IfInMBUFDiscards),
6923 STATS_OFFSET32(stat_FwRxDrop),
6926 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6927 * skipped because of errata.
6929 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6930 8,0,8,8,8,8,8,8,8,8,
6931 4,0,4,4,4,4,4,4,4,4,
6932 4,4,4,4,4,4,4,4,4,4,
6933 4,4,4,4,4,4,4,4,4,4,
6937 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6938 8,0,8,8,8,8,8,8,8,8,
6939 4,4,4,4,4,4,4,4,4,4,
6940 4,4,4,4,4,4,4,4,4,4,
6941 4,4,4,4,4,4,4,4,4,4,
6945 #define BNX2_NUM_TESTS 6
6948 char string[ETH_GSTRING_LEN];
6949 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6950 { "register_test (offline)" },
6951 { "memory_test (offline)" },
6952 { "loopback_test (offline)" },
6953 { "nvram_test (online)" },
6954 { "interrupt_test (online)" },
6955 { "link_test (online)" },
6959 bnx2_get_sset_count(struct net_device *dev, int sset)
6963 return BNX2_NUM_TESTS;
6965 return BNX2_NUM_STATS;
6972 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6974 struct bnx2 *bp = netdev_priv(dev);
6976 bnx2_set_power_state(bp, PCI_D0);
6978 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6979 if (etest->flags & ETH_TEST_FL_OFFLINE) {
6982 bnx2_netif_stop(bp);
6983 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6986 if (bnx2_test_registers(bp) != 0) {
6988 etest->flags |= ETH_TEST_FL_FAILED;
6990 if (bnx2_test_memory(bp) != 0) {
6992 etest->flags |= ETH_TEST_FL_FAILED;
6994 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6995 etest->flags |= ETH_TEST_FL_FAILED;
6997 if (!netif_running(bp->dev))
6998 bnx2_shutdown_chip(bp);
7000 bnx2_init_nic(bp, 1);
7001 bnx2_netif_start(bp);
7004 /* wait for link up */
7005 for (i = 0; i < 7; i++) {
7008 msleep_interruptible(1000);
7012 if (bnx2_test_nvram(bp) != 0) {
7014 etest->flags |= ETH_TEST_FL_FAILED;
7016 if (bnx2_test_intr(bp) != 0) {
7018 etest->flags |= ETH_TEST_FL_FAILED;
7021 if (bnx2_test_link(bp) != 0) {
7023 etest->flags |= ETH_TEST_FL_FAILED;
7026 if (!netif_running(bp->dev))
7027 bnx2_set_power_state(bp, PCI_D3hot);
7031 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
7033 switch (stringset) {
7035 memcpy(buf, bnx2_stats_str_arr,
7036 sizeof(bnx2_stats_str_arr));
7039 memcpy(buf, bnx2_tests_str_arr,
7040 sizeof(bnx2_tests_str_arr));
7046 bnx2_get_ethtool_stats(struct net_device *dev,
7047 struct ethtool_stats *stats, u64 *buf)
7049 struct bnx2 *bp = netdev_priv(dev);
7051 u32 *hw_stats = (u32 *) bp->stats_blk;
7052 u8 *stats_len_arr = NULL;
7054 if (hw_stats == NULL) {
7055 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
7059 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
7060 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
7061 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
7062 (CHIP_ID(bp) == CHIP_ID_5708_A0))
7063 stats_len_arr = bnx2_5706_stats_len_arr;
7065 stats_len_arr = bnx2_5708_stats_len_arr;
7067 for (i = 0; i < BNX2_NUM_STATS; i++) {
7068 if (stats_len_arr[i] == 0) {
7069 /* skip this counter */
7073 if (stats_len_arr[i] == 4) {
7074 /* 4-byte counter */
7076 *(hw_stats + bnx2_stats_offset_arr[i]);
7079 /* 8-byte counter */
7080 buf[i] = (((u64) *(hw_stats +
7081 bnx2_stats_offset_arr[i])) << 32) +
7082 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7087 bnx2_phys_id(struct net_device *dev, u32 data)
7089 struct bnx2 *bp = netdev_priv(dev);
7093 bnx2_set_power_state(bp, PCI_D0);
7098 save = REG_RD(bp, BNX2_MISC_CFG);
7099 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7101 for (i = 0; i < (data * 2); i++) {
7103 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7106 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7107 BNX2_EMAC_LED_1000MB_OVERRIDE |
7108 BNX2_EMAC_LED_100MB_OVERRIDE |
7109 BNX2_EMAC_LED_10MB_OVERRIDE |
7110 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7111 BNX2_EMAC_LED_TRAFFIC);
7113 msleep_interruptible(500);
7114 if (signal_pending(current))
7117 REG_WR(bp, BNX2_EMAC_LED, 0);
7118 REG_WR(bp, BNX2_MISC_CFG, save);
7120 if (!netif_running(dev))
7121 bnx2_set_power_state(bp, PCI_D3hot);
7127 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7129 struct bnx2 *bp = netdev_priv(dev);
7131 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7132 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7134 return (ethtool_op_set_tx_csum(dev, data));
7137 static const struct ethtool_ops bnx2_ethtool_ops = {
7138 .get_settings = bnx2_get_settings,
7139 .set_settings = bnx2_set_settings,
7140 .get_drvinfo = bnx2_get_drvinfo,
7141 .get_regs_len = bnx2_get_regs_len,
7142 .get_regs = bnx2_get_regs,
7143 .get_wol = bnx2_get_wol,
7144 .set_wol = bnx2_set_wol,
7145 .nway_reset = bnx2_nway_reset,
7146 .get_link = ethtool_op_get_link,
7147 .get_eeprom_len = bnx2_get_eeprom_len,
7148 .get_eeprom = bnx2_get_eeprom,
7149 .set_eeprom = bnx2_set_eeprom,
7150 .get_coalesce = bnx2_get_coalesce,
7151 .set_coalesce = bnx2_set_coalesce,
7152 .get_ringparam = bnx2_get_ringparam,
7153 .set_ringparam = bnx2_set_ringparam,
7154 .get_pauseparam = bnx2_get_pauseparam,
7155 .set_pauseparam = bnx2_set_pauseparam,
7156 .get_rx_csum = bnx2_get_rx_csum,
7157 .set_rx_csum = bnx2_set_rx_csum,
7158 .set_tx_csum = bnx2_set_tx_csum,
7159 .set_sg = ethtool_op_set_sg,
7160 .set_tso = bnx2_set_tso,
7161 .self_test = bnx2_self_test,
7162 .get_strings = bnx2_get_strings,
7163 .phys_id = bnx2_phys_id,
7164 .get_ethtool_stats = bnx2_get_ethtool_stats,
7165 .get_sset_count = bnx2_get_sset_count,
7168 /* Called with rtnl_lock */
7170 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7172 struct mii_ioctl_data *data = if_mii(ifr);
7173 struct bnx2 *bp = netdev_priv(dev);
7178 data->phy_id = bp->phy_addr;
7184 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7187 if (!netif_running(dev))
7190 spin_lock_bh(&bp->phy_lock);
7191 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7192 spin_unlock_bh(&bp->phy_lock);
7194 data->val_out = mii_regval;
7200 if (!capable(CAP_NET_ADMIN))
7203 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7206 if (!netif_running(dev))
7209 spin_lock_bh(&bp->phy_lock);
7210 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7211 spin_unlock_bh(&bp->phy_lock);
7222 /* Called with rtnl_lock */
7224 bnx2_change_mac_addr(struct net_device *dev, void *p)
7226 struct sockaddr *addr = p;
7227 struct bnx2 *bp = netdev_priv(dev);
7229 if (!is_valid_ether_addr(addr->sa_data))
7232 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7233 if (netif_running(dev))
7234 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7239 /* Called with rtnl_lock */
7241 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7243 struct bnx2 *bp = netdev_priv(dev);
7245 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7246 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7250 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7253 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7255 poll_bnx2(struct net_device *dev)
7257 struct bnx2 *bp = netdev_priv(dev);
7260 for (i = 0; i < bp->irq_nvecs; i++) {
7261 disable_irq(bp->irq_tbl[i].vector);
7262 bnx2_interrupt(bp->irq_tbl[i].vector, &bp->bnx2_napi[i]);
7263 enable_irq(bp->irq_tbl[i].vector);
7268 static void __devinit
7269 bnx2_get_5709_media(struct bnx2 *bp)
7271 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7272 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7275 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7277 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7278 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7282 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7283 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7285 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7287 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7292 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7300 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7306 static void __devinit
7307 bnx2_get_pci_speed(struct bnx2 *bp)
7311 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7312 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7315 bp->flags |= BNX2_FLAG_PCIX;
7317 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7319 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7321 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7322 bp->bus_speed_mhz = 133;
7325 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7326 bp->bus_speed_mhz = 100;
7329 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7330 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7331 bp->bus_speed_mhz = 66;
7334 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7335 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7336 bp->bus_speed_mhz = 50;
7339 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7340 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7341 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7342 bp->bus_speed_mhz = 33;
7347 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7348 bp->bus_speed_mhz = 66;
7350 bp->bus_speed_mhz = 33;
7353 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7354 bp->flags |= BNX2_FLAG_PCI_32BIT;
7358 static int __devinit
7359 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7362 unsigned long mem_len;
7365 u64 dma_mask, persist_dma_mask;
7367 SET_NETDEV_DEV(dev, &pdev->dev);
7368 bp = netdev_priv(dev);
7373 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7374 rc = pci_enable_device(pdev);
7376 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7380 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7382 "Cannot find PCI device base address, aborting.\n");
7384 goto err_out_disable;
7387 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7389 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7390 goto err_out_disable;
7393 pci_set_master(pdev);
7394 pci_save_state(pdev);
7396 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7397 if (bp->pm_cap == 0) {
7399 "Cannot find power management capability, aborting.\n");
7401 goto err_out_release;
7407 spin_lock_init(&bp->phy_lock);
7408 spin_lock_init(&bp->indirect_lock);
7409 INIT_WORK(&bp->reset_task, bnx2_reset_task);
7411 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7412 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS);
7413 dev->mem_end = dev->mem_start + mem_len;
7414 dev->irq = pdev->irq;
7416 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7419 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7421 goto err_out_release;
7424 /* Configure byte swap and enable write to the reg_window registers.
7425 * Rely on CPU to do target byte swapping on big endian systems
7426 * The chip's target access swapping will not swap all accesses
7428 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7429 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7430 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7432 bnx2_set_power_state(bp, PCI_D0);
7434 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7436 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7437 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7439 "Cannot find PCIE capability, aborting.\n");
7443 bp->flags |= BNX2_FLAG_PCIE;
7444 if (CHIP_REV(bp) == CHIP_REV_Ax)
7445 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7447 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7448 if (bp->pcix_cap == 0) {
7450 "Cannot find PCIX capability, aborting.\n");
7456 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7457 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7458 bp->flags |= BNX2_FLAG_MSIX_CAP;
7461 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7462 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7463 bp->flags |= BNX2_FLAG_MSI_CAP;
7466 /* 5708 cannot support DMA addresses > 40-bit. */
7467 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7468 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7470 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7472 /* Configure DMA attributes. */
7473 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7474 dev->features |= NETIF_F_HIGHDMA;
7475 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7478 "pci_set_consistent_dma_mask failed, aborting.\n");
7481 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7482 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7486 if (!(bp->flags & BNX2_FLAG_PCIE))
7487 bnx2_get_pci_speed(bp);
7489 /* 5706A0 may falsely detect SERR and PERR. */
7490 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7491 reg = REG_RD(bp, PCI_COMMAND);
7492 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7493 REG_WR(bp, PCI_COMMAND, reg);
7495 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7496 !(bp->flags & BNX2_FLAG_PCIX)) {
7499 "5706 A1 can only be used in a PCIX bus, aborting.\n");
7503 bnx2_init_nvram(bp);
7505 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7507 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7508 BNX2_SHM_HDR_SIGNATURE_SIG) {
7509 u32 off = PCI_FUNC(pdev->devfn) << 2;
7511 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7513 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7515 /* Get the permanent MAC address. First we need to make sure the
7516 * firmware is actually running.
7518 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7520 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7521 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7522 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7527 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7528 for (i = 0, j = 0; i < 3; i++) {
7531 num = (u8) (reg >> (24 - (i * 8)));
7532 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7533 if (num >= k || !skip0 || k == 1) {
7534 bp->fw_version[j++] = (num / k) + '0';
7539 bp->fw_version[j++] = '.';
7541 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7542 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7545 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7546 bp->flags |= BNX2_FLAG_ASF_ENABLE;
7548 for (i = 0; i < 30; i++) {
7549 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7550 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7555 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7556 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7557 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7558 reg != BNX2_CONDITION_MFW_RUN_NONE) {
7559 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7561 bp->fw_version[j++] = ' ';
7562 for (i = 0; i < 3; i++) {
7563 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7565 memcpy(&bp->fw_version[j], ®, 4);
7570 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7571 bp->mac_addr[0] = (u8) (reg >> 8);
7572 bp->mac_addr[1] = (u8) reg;
7574 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7575 bp->mac_addr[2] = (u8) (reg >> 24);
7576 bp->mac_addr[3] = (u8) (reg >> 16);
7577 bp->mac_addr[4] = (u8) (reg >> 8);
7578 bp->mac_addr[5] = (u8) reg;
7580 bp->tx_ring_size = MAX_TX_DESC_CNT;
7581 bnx2_set_rx_ring_size(bp, 255);
7585 bp->tx_quick_cons_trip_int = 20;
7586 bp->tx_quick_cons_trip = 20;
7587 bp->tx_ticks_int = 80;
7590 bp->rx_quick_cons_trip_int = 6;
7591 bp->rx_quick_cons_trip = 6;
7592 bp->rx_ticks_int = 18;
7595 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7597 bp->current_interval = BNX2_TIMER_INTERVAL;
7601 /* Disable WOL support if we are running on a SERDES chip. */
7602 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7603 bnx2_get_5709_media(bp);
7604 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7605 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7607 bp->phy_port = PORT_TP;
7608 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7609 bp->phy_port = PORT_FIBRE;
7610 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7611 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7612 bp->flags |= BNX2_FLAG_NO_WOL;
7615 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7616 /* Don't do parallel detect on this board because of
7617 * some board problems. The link will not go down
7618 * if we do parallel detect.
7620 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7621 pdev->subsystem_device == 0x310c)
7622 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7625 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7626 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7628 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7629 CHIP_NUM(bp) == CHIP_NUM_5708)
7630 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7631 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7632 (CHIP_REV(bp) == CHIP_REV_Ax ||
7633 CHIP_REV(bp) == CHIP_REV_Bx))
7634 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7636 bnx2_init_fw_cap(bp);
7638 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7639 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7640 (CHIP_ID(bp) == CHIP_ID_5708_B1) ||
7641 !(REG_RD(bp, BNX2_PCI_CONFIG_3) & BNX2_PCI_CONFIG_3_VAUX_PRESET)) {
7642 bp->flags |= BNX2_FLAG_NO_WOL;
7646 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7647 bp->tx_quick_cons_trip_int =
7648 bp->tx_quick_cons_trip;
7649 bp->tx_ticks_int = bp->tx_ticks;
7650 bp->rx_quick_cons_trip_int =
7651 bp->rx_quick_cons_trip;
7652 bp->rx_ticks_int = bp->rx_ticks;
7653 bp->comp_prod_trip_int = bp->comp_prod_trip;
7654 bp->com_ticks_int = bp->com_ticks;
7655 bp->cmd_ticks_int = bp->cmd_ticks;
7658 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7660 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7661 * with byte enables disabled on the unused 32-bit word. This is legal
7662 * but causes problems on the AMD 8132 which will eventually stop
7663 * responding after a while.
7665 * AMD believes this incompatibility is unique to the 5706, and
7666 * prefers to locally disable MSI rather than globally disabling it.
7668 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7669 struct pci_dev *amd_8132 = NULL;
7671 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7672 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7675 if (amd_8132->revision >= 0x10 &&
7676 amd_8132->revision <= 0x13) {
7678 pci_dev_put(amd_8132);
7684 bnx2_set_default_link(bp);
7685 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7687 init_timer(&bp->timer);
7688 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
7689 bp->timer.data = (unsigned long) bp;
7690 bp->timer.function = bnx2_timer;
7696 iounmap(bp->regview);
7701 pci_release_regions(pdev);
7704 pci_disable_device(pdev);
7705 pci_set_drvdata(pdev, NULL);
7711 static char * __devinit
7712 bnx2_bus_string(struct bnx2 *bp, char *str)
7716 if (bp->flags & BNX2_FLAG_PCIE) {
7717 s += sprintf(s, "PCI Express");
7719 s += sprintf(s, "PCI");
7720 if (bp->flags & BNX2_FLAG_PCIX)
7721 s += sprintf(s, "-X");
7722 if (bp->flags & BNX2_FLAG_PCI_32BIT)
7723 s += sprintf(s, " 32-bit");
7725 s += sprintf(s, " 64-bit");
7726 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7731 static void __devinit
7732 bnx2_init_napi(struct bnx2 *bp)
7736 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7737 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
7738 int (*poll)(struct napi_struct *, int);
7743 poll = bnx2_poll_msix;
7745 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
7750 static const struct net_device_ops bnx2_netdev_ops = {
7751 .ndo_open = bnx2_open,
7752 .ndo_start_xmit = bnx2_start_xmit,
7753 .ndo_stop = bnx2_close,
7754 .ndo_get_stats = bnx2_get_stats,
7755 .ndo_set_rx_mode = bnx2_set_rx_mode,
7756 .ndo_do_ioctl = bnx2_ioctl,
7757 .ndo_validate_addr = eth_validate_addr,
7758 .ndo_set_mac_address = bnx2_change_mac_addr,
7759 .ndo_change_mtu = bnx2_change_mtu,
7760 .ndo_tx_timeout = bnx2_tx_timeout,
7762 .ndo_vlan_rx_register = bnx2_vlan_rx_register,
7764 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7765 .ndo_poll_controller = poll_bnx2,
7769 static int __devinit
7770 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7772 static int version_printed = 0;
7773 struct net_device *dev = NULL;
7778 if (version_printed++ == 0)
7779 printk(KERN_INFO "%s", version);
7781 /* dev zeroed in init_etherdev */
7782 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
7787 rc = bnx2_init_board(pdev, dev);
7793 dev->netdev_ops = &bnx2_netdev_ops;
7794 dev->watchdog_timeo = TX_TIMEOUT;
7795 dev->ethtool_ops = &bnx2_ethtool_ops;
7797 bp = netdev_priv(dev);
7800 pci_set_drvdata(pdev, dev);
7802 memcpy(dev->dev_addr, bp->mac_addr, 6);
7803 memcpy(dev->perm_addr, bp->mac_addr, 6);
7805 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
7806 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7807 dev->features |= NETIF_F_IPV6_CSUM;
7810 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7812 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7813 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7814 dev->features |= NETIF_F_TSO6;
7816 if ((rc = register_netdev(dev))) {
7817 dev_err(&pdev->dev, "Cannot register net device\n");
7819 iounmap(bp->regview);
7820 pci_release_regions(pdev);
7821 pci_disable_device(pdev);
7822 pci_set_drvdata(pdev, NULL);
7827 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
7828 "IRQ %d, node addr %pM\n",
7830 board_info[ent->driver_data].name,
7831 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7832 ((CHIP_ID(bp) & 0x0ff0) >> 4),
7833 bnx2_bus_string(bp, str),
7835 bp->pdev->irq, dev->dev_addr);
7840 static void __devexit
7841 bnx2_remove_one(struct pci_dev *pdev)
7843 struct net_device *dev = pci_get_drvdata(pdev);
7844 struct bnx2 *bp = netdev_priv(dev);
7846 flush_scheduled_work();
7848 unregister_netdev(dev);
7851 iounmap(bp->regview);
7854 pci_release_regions(pdev);
7855 pci_disable_device(pdev);
7856 pci_set_drvdata(pdev, NULL);
7860 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
7862 struct net_device *dev = pci_get_drvdata(pdev);
7863 struct bnx2 *bp = netdev_priv(dev);
7865 /* PCI register 4 needs to be saved whether netif_running() or not.
7866 * MSI address and data need to be saved if using MSI and
7869 pci_save_state(pdev);
7870 if (!netif_running(dev))
7873 flush_scheduled_work();
7874 bnx2_netif_stop(bp);
7875 netif_device_detach(dev);
7876 del_timer_sync(&bp->timer);
7877 bnx2_shutdown_chip(bp);
7879 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
7884 bnx2_resume(struct pci_dev *pdev)
7886 struct net_device *dev = pci_get_drvdata(pdev);
7887 struct bnx2 *bp = netdev_priv(dev);
7889 pci_restore_state(pdev);
7890 if (!netif_running(dev))
7893 bnx2_set_power_state(bp, PCI_D0);
7894 netif_device_attach(dev);
7895 bnx2_init_nic(bp, 1);
7896 bnx2_netif_start(bp);
7901 * bnx2_io_error_detected - called when PCI error is detected
7902 * @pdev: Pointer to PCI device
7903 * @state: The current pci connection state
7905 * This function is called after a PCI bus error affecting
7906 * this device has been detected.
7908 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7909 pci_channel_state_t state)
7911 struct net_device *dev = pci_get_drvdata(pdev);
7912 struct bnx2 *bp = netdev_priv(dev);
7915 netif_device_detach(dev);
7917 if (netif_running(dev)) {
7918 bnx2_netif_stop(bp);
7919 del_timer_sync(&bp->timer);
7920 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7923 pci_disable_device(pdev);
7926 /* Request a slot slot reset. */
7927 return PCI_ERS_RESULT_NEED_RESET;
7931 * bnx2_io_slot_reset - called after the pci bus has been reset.
7932 * @pdev: Pointer to PCI device
7934 * Restart the card from scratch, as if from a cold-boot.
7936 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
7938 struct net_device *dev = pci_get_drvdata(pdev);
7939 struct bnx2 *bp = netdev_priv(dev);
7942 if (pci_enable_device(pdev)) {
7944 "Cannot re-enable PCI device after reset.\n");
7946 return PCI_ERS_RESULT_DISCONNECT;
7948 pci_set_master(pdev);
7949 pci_restore_state(pdev);
7951 if (netif_running(dev)) {
7952 bnx2_set_power_state(bp, PCI_D0);
7953 bnx2_init_nic(bp, 1);
7957 return PCI_ERS_RESULT_RECOVERED;
7961 * bnx2_io_resume - called when traffic can start flowing again.
7962 * @pdev: Pointer to PCI device
7964 * This callback is called when the error recovery driver tells us that
7965 * its OK to resume normal operation.
7967 static void bnx2_io_resume(struct pci_dev *pdev)
7969 struct net_device *dev = pci_get_drvdata(pdev);
7970 struct bnx2 *bp = netdev_priv(dev);
7973 if (netif_running(dev))
7974 bnx2_netif_start(bp);
7976 netif_device_attach(dev);
7980 static struct pci_error_handlers bnx2_err_handler = {
7981 .error_detected = bnx2_io_error_detected,
7982 .slot_reset = bnx2_io_slot_reset,
7983 .resume = bnx2_io_resume,
7986 static struct pci_driver bnx2_pci_driver = {
7987 .name = DRV_MODULE_NAME,
7988 .id_table = bnx2_pci_tbl,
7989 .probe = bnx2_init_one,
7990 .remove = __devexit_p(bnx2_remove_one),
7991 .suspend = bnx2_suspend,
7992 .resume = bnx2_resume,
7993 .err_handler = &bnx2_err_handler,
7996 static int __init bnx2_init(void)
7998 return pci_register_driver(&bnx2_pci_driver);
8001 static void __exit bnx2_cleanup(void)
8003 pci_unregister_driver(&bnx2_pci_driver);
8006 module_init(bnx2_init);
8007 module_exit(bnx2_cleanup);