1 /* bnx2.c: Broadcom NX2 network driver.
3 * Copyright (c) 2004-2008 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Written by: Michael Chan (mchan@broadcom.com)
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/bitops.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #include <linux/if_vlan.h>
39 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/zlib.h>
50 #include <linux/log2.h>
56 #define FW_BUF_SIZE 0x10000
58 #define DRV_MODULE_NAME "bnx2"
59 #define PFX DRV_MODULE_NAME ": "
60 #define DRV_MODULE_VERSION "1.8.0"
61 #define DRV_MODULE_RELDATE "Aug 14, 2008"
63 #define RUN_AT(x) (jiffies + (x))
65 /* Time in jiffies before concluding the transmitter is hung. */
66 #define TX_TIMEOUT (5*HZ)
68 static char version[] __devinitdata =
69 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
71 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
72 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708/5709/5716 Driver");
73 MODULE_LICENSE("GPL");
74 MODULE_VERSION(DRV_MODULE_VERSION);
76 static int disable_msi = 0;
78 module_param(disable_msi, int, 0);
79 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
94 /* indexed by board_t, above */
97 } board_info[] __devinitdata = {
98 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
99 { "HP NC370T Multifunction Gigabit Server Adapter" },
100 { "HP NC370i Multifunction Gigabit Server Adapter" },
101 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
102 { "HP NC370F Multifunction Gigabit Server Adapter" },
103 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
104 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
105 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
106 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
107 { "Broadcom NetXtreme II BCM5716 1000Base-T" },
110 static DEFINE_PCI_DEVICE_TABLE(bnx2_pci_tbl) = {
111 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
112 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
113 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
114 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
115 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
117 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
119 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
120 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
121 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
123 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
125 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
127 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
129 { PCI_VENDOR_ID_BROADCOM, 0x163b,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5716 },
134 static struct flash_spec flash_table[] =
136 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
137 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
139 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
140 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
141 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
143 /* Expansion entry 0001 */
144 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
145 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
146 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
148 /* Saifun SA25F010 (non-buffered flash) */
149 /* strap, cfg1, & write1 need updates */
150 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
151 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
152 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
153 "Non-buffered flash (128kB)"},
154 /* Saifun SA25F020 (non-buffered flash) */
155 /* strap, cfg1, & write1 need updates */
156 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
158 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
159 "Non-buffered flash (256kB)"},
160 /* Expansion entry 0100 */
161 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
162 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
163 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
165 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
166 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
167 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
168 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
169 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
170 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
171 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
172 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
173 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
174 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
175 /* Saifun SA25F005 (non-buffered flash) */
176 /* strap, cfg1, & write1 need updates */
177 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
178 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
179 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
180 "Non-buffered flash (64kB)"},
182 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
183 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
184 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
186 /* Expansion entry 1001 */
187 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
191 /* Expansion entry 1010 */
192 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
193 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
194 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
196 /* ATMEL AT45DB011B (buffered flash) */
197 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
198 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
199 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
200 "Buffered flash (128kB)"},
201 /* Expansion entry 1100 */
202 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
206 /* Expansion entry 1101 */
207 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
208 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
209 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
211 /* Ateml Expansion entry 1110 */
212 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
214 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
215 "Entry 1110 (Atmel)"},
216 /* ATMEL AT45DB021B (buffered flash) */
217 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
218 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
219 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
220 "Buffered flash (256kB)"},
223 static struct flash_spec flash_5709 = {
224 .flags = BNX2_NV_BUFFERED,
225 .page_bits = BCM5709_FLASH_PAGE_BITS,
226 .page_size = BCM5709_FLASH_PAGE_SIZE,
227 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
228 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
229 .name = "5709 Buffered flash (256kB)",
232 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
234 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_tx_ring_info *txr)
240 /* The ring uses 256 indices for 255 entries, one of them
241 * needs to be skipped.
243 diff = txr->tx_prod - txr->tx_cons;
244 if (unlikely(diff >= TX_DESC_CNT)) {
246 if (diff == TX_DESC_CNT)
247 diff = MAX_TX_DESC_CNT;
249 return (bp->tx_ring_size - diff);
253 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
257 spin_lock_bh(&bp->indirect_lock);
258 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
259 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
260 spin_unlock_bh(&bp->indirect_lock);
265 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
267 spin_lock_bh(&bp->indirect_lock);
268 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
269 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
270 spin_unlock_bh(&bp->indirect_lock);
274 bnx2_shmem_wr(struct bnx2 *bp, u32 offset, u32 val)
276 bnx2_reg_wr_ind(bp, bp->shmem_base + offset, val);
280 bnx2_shmem_rd(struct bnx2 *bp, u32 offset)
282 return (bnx2_reg_rd_ind(bp, bp->shmem_base + offset));
286 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
289 spin_lock_bh(&bp->indirect_lock);
290 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
293 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
294 REG_WR(bp, BNX2_CTX_CTX_CTRL,
295 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
296 for (i = 0; i < 5; i++) {
297 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
298 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
303 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
304 REG_WR(bp, BNX2_CTX_DATA, val);
306 spin_unlock_bh(&bp->indirect_lock);
310 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
315 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
316 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
317 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
319 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
320 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
325 val1 = (bp->phy_addr << 21) | (reg << 16) |
326 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
327 BNX2_EMAC_MDIO_COMM_START_BUSY;
328 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
330 for (i = 0; i < 50; i++) {
333 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
334 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
337 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
338 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
344 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
353 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
354 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
355 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
357 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
358 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
367 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
372 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
373 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
374 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
376 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
377 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
382 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
383 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
384 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
385 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
387 for (i = 0; i < 50; i++) {
390 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
391 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
397 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
402 if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) {
403 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
404 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
406 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
407 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
416 bnx2_disable_int(struct bnx2 *bp)
419 struct bnx2_napi *bnapi;
421 for (i = 0; i < bp->irq_nvecs; i++) {
422 bnapi = &bp->bnx2_napi[i];
423 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
424 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
426 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
430 bnx2_enable_int(struct bnx2 *bp)
433 struct bnx2_napi *bnapi;
435 for (i = 0; i < bp->irq_nvecs; i++) {
436 bnapi = &bp->bnx2_napi[i];
438 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
439 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
440 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
441 bnapi->last_status_idx);
443 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
444 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
445 bnapi->last_status_idx);
447 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
451 bnx2_disable_int_sync(struct bnx2 *bp)
455 atomic_inc(&bp->intr_sem);
456 bnx2_disable_int(bp);
457 for (i = 0; i < bp->irq_nvecs; i++)
458 synchronize_irq(bp->irq_tbl[i].vector);
462 bnx2_napi_disable(struct bnx2 *bp)
466 for (i = 0; i < bp->irq_nvecs; i++)
467 napi_disable(&bp->bnx2_napi[i].napi);
471 bnx2_napi_enable(struct bnx2 *bp)
475 for (i = 0; i < bp->irq_nvecs; i++)
476 napi_enable(&bp->bnx2_napi[i].napi);
480 bnx2_netif_stop(struct bnx2 *bp)
482 bnx2_disable_int_sync(bp);
483 if (netif_running(bp->dev)) {
484 bnx2_napi_disable(bp);
485 netif_tx_disable(bp->dev);
486 bp->dev->trans_start = jiffies; /* prevent tx timeout */
491 bnx2_netif_start(struct bnx2 *bp)
493 if (atomic_dec_and_test(&bp->intr_sem)) {
494 if (netif_running(bp->dev)) {
495 netif_tx_wake_all_queues(bp->dev);
496 bnx2_napi_enable(bp);
503 bnx2_free_tx_mem(struct bnx2 *bp)
507 for (i = 0; i < bp->num_tx_rings; i++) {
508 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
509 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
511 if (txr->tx_desc_ring) {
512 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
514 txr->tx_desc_mapping);
515 txr->tx_desc_ring = NULL;
517 kfree(txr->tx_buf_ring);
518 txr->tx_buf_ring = NULL;
523 bnx2_free_rx_mem(struct bnx2 *bp)
527 for (i = 0; i < bp->num_rx_rings; i++) {
528 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
529 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
532 for (j = 0; j < bp->rx_max_ring; j++) {
533 if (rxr->rx_desc_ring[j])
534 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
535 rxr->rx_desc_ring[j],
536 rxr->rx_desc_mapping[j]);
537 rxr->rx_desc_ring[j] = NULL;
539 if (rxr->rx_buf_ring)
540 vfree(rxr->rx_buf_ring);
541 rxr->rx_buf_ring = NULL;
543 for (j = 0; j < bp->rx_max_pg_ring; j++) {
544 if (rxr->rx_pg_desc_ring[j])
545 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
546 rxr->rx_pg_desc_ring[i],
547 rxr->rx_pg_desc_mapping[i]);
548 rxr->rx_pg_desc_ring[i] = NULL;
551 vfree(rxr->rx_pg_ring);
552 rxr->rx_pg_ring = NULL;
557 bnx2_alloc_tx_mem(struct bnx2 *bp)
561 for (i = 0; i < bp->num_tx_rings; i++) {
562 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
563 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
565 txr->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
566 if (txr->tx_buf_ring == NULL)
570 pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
571 &txr->tx_desc_mapping);
572 if (txr->tx_desc_ring == NULL)
579 bnx2_alloc_rx_mem(struct bnx2 *bp)
583 for (i = 0; i < bp->num_rx_rings; i++) {
584 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
585 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
589 vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
590 if (rxr->rx_buf_ring == NULL)
593 memset(rxr->rx_buf_ring, 0,
594 SW_RXBD_RING_SIZE * bp->rx_max_ring);
596 for (j = 0; j < bp->rx_max_ring; j++) {
597 rxr->rx_desc_ring[j] =
598 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
599 &rxr->rx_desc_mapping[j]);
600 if (rxr->rx_desc_ring[j] == NULL)
605 if (bp->rx_pg_ring_size) {
606 rxr->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
608 if (rxr->rx_pg_ring == NULL)
611 memset(rxr->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
615 for (j = 0; j < bp->rx_max_pg_ring; j++) {
616 rxr->rx_pg_desc_ring[j] =
617 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
618 &rxr->rx_pg_desc_mapping[j]);
619 if (rxr->rx_pg_desc_ring[j] == NULL)
628 bnx2_free_mem(struct bnx2 *bp)
631 struct bnx2_napi *bnapi = &bp->bnx2_napi[0];
633 bnx2_free_tx_mem(bp);
634 bnx2_free_rx_mem(bp);
636 for (i = 0; i < bp->ctx_pages; i++) {
637 if (bp->ctx_blk[i]) {
638 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
640 bp->ctx_blk_mapping[i]);
641 bp->ctx_blk[i] = NULL;
644 if (bnapi->status_blk.msi) {
645 pci_free_consistent(bp->pdev, bp->status_stats_size,
646 bnapi->status_blk.msi,
647 bp->status_blk_mapping);
648 bnapi->status_blk.msi = NULL;
649 bp->stats_blk = NULL;
654 bnx2_alloc_mem(struct bnx2 *bp)
656 int i, status_blk_size, err;
657 struct bnx2_napi *bnapi;
660 /* Combine status and statistics blocks into one allocation. */
661 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
662 if (bp->flags & BNX2_FLAG_MSIX_CAP)
663 status_blk_size = L1_CACHE_ALIGN(BNX2_MAX_MSIX_HW_VEC *
664 BNX2_SBLK_MSIX_ALIGN_SIZE);
665 bp->status_stats_size = status_blk_size +
666 sizeof(struct statistics_block);
668 status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
669 &bp->status_blk_mapping);
670 if (status_blk == NULL)
673 memset(status_blk, 0, bp->status_stats_size);
675 bnapi = &bp->bnx2_napi[0];
676 bnapi->status_blk.msi = status_blk;
677 bnapi->hw_tx_cons_ptr =
678 &bnapi->status_blk.msi->status_tx_quick_consumer_index0;
679 bnapi->hw_rx_cons_ptr =
680 &bnapi->status_blk.msi->status_rx_quick_consumer_index0;
681 if (bp->flags & BNX2_FLAG_MSIX_CAP) {
682 for (i = 1; i < BNX2_MAX_MSIX_VEC; i++) {
683 struct status_block_msix *sblk;
685 bnapi = &bp->bnx2_napi[i];
687 sblk = (void *) (status_blk +
688 BNX2_SBLK_MSIX_ALIGN_SIZE * i);
689 bnapi->status_blk.msix = sblk;
690 bnapi->hw_tx_cons_ptr =
691 &sblk->status_tx_quick_consumer_index;
692 bnapi->hw_rx_cons_ptr =
693 &sblk->status_rx_quick_consumer_index;
694 bnapi->int_num = i << 24;
698 bp->stats_blk = status_blk + status_blk_size;
700 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
702 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
703 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
704 if (bp->ctx_pages == 0)
706 for (i = 0; i < bp->ctx_pages; i++) {
707 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
709 &bp->ctx_blk_mapping[i]);
710 if (bp->ctx_blk[i] == NULL)
715 err = bnx2_alloc_rx_mem(bp);
719 err = bnx2_alloc_tx_mem(bp);
731 bnx2_report_fw_link(struct bnx2 *bp)
733 u32 fw_link_status = 0;
735 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
741 switch (bp->line_speed) {
743 if (bp->duplex == DUPLEX_HALF)
744 fw_link_status = BNX2_LINK_STATUS_10HALF;
746 fw_link_status = BNX2_LINK_STATUS_10FULL;
749 if (bp->duplex == DUPLEX_HALF)
750 fw_link_status = BNX2_LINK_STATUS_100HALF;
752 fw_link_status = BNX2_LINK_STATUS_100FULL;
755 if (bp->duplex == DUPLEX_HALF)
756 fw_link_status = BNX2_LINK_STATUS_1000HALF;
758 fw_link_status = BNX2_LINK_STATUS_1000FULL;
761 if (bp->duplex == DUPLEX_HALF)
762 fw_link_status = BNX2_LINK_STATUS_2500HALF;
764 fw_link_status = BNX2_LINK_STATUS_2500FULL;
768 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
771 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
773 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
774 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
776 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
777 bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)
778 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
780 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
784 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
786 bnx2_shmem_wr(bp, BNX2_LINK_STATUS, fw_link_status);
790 bnx2_xceiver_str(struct bnx2 *bp)
792 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
793 ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" :
798 bnx2_report_link(struct bnx2 *bp)
801 netif_carrier_on(bp->dev);
802 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
803 bnx2_xceiver_str(bp));
805 printk("%d Mbps ", bp->line_speed);
807 if (bp->duplex == DUPLEX_FULL)
808 printk("full duplex");
810 printk("half duplex");
813 if (bp->flow_ctrl & FLOW_CTRL_RX) {
814 printk(", receive ");
815 if (bp->flow_ctrl & FLOW_CTRL_TX)
816 printk("& transmit ");
819 printk(", transmit ");
821 printk("flow control ON");
826 netif_carrier_off(bp->dev);
827 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
828 bnx2_xceiver_str(bp));
831 bnx2_report_fw_link(bp);
835 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
837 u32 local_adv, remote_adv;
840 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
841 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
843 if (bp->duplex == DUPLEX_FULL) {
844 bp->flow_ctrl = bp->req_flow_ctrl;
849 if (bp->duplex != DUPLEX_FULL) {
853 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
854 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
857 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
858 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
859 bp->flow_ctrl |= FLOW_CTRL_TX;
860 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
861 bp->flow_ctrl |= FLOW_CTRL_RX;
865 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
866 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
868 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
869 u32 new_local_adv = 0;
870 u32 new_remote_adv = 0;
872 if (local_adv & ADVERTISE_1000XPAUSE)
873 new_local_adv |= ADVERTISE_PAUSE_CAP;
874 if (local_adv & ADVERTISE_1000XPSE_ASYM)
875 new_local_adv |= ADVERTISE_PAUSE_ASYM;
876 if (remote_adv & ADVERTISE_1000XPAUSE)
877 new_remote_adv |= ADVERTISE_PAUSE_CAP;
878 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
879 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
881 local_adv = new_local_adv;
882 remote_adv = new_remote_adv;
885 /* See Table 28B-3 of 802.3ab-1999 spec. */
886 if (local_adv & ADVERTISE_PAUSE_CAP) {
887 if(local_adv & ADVERTISE_PAUSE_ASYM) {
888 if (remote_adv & ADVERTISE_PAUSE_CAP) {
889 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
891 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
892 bp->flow_ctrl = FLOW_CTRL_RX;
896 if (remote_adv & ADVERTISE_PAUSE_CAP) {
897 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
901 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
902 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
903 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
905 bp->flow_ctrl = FLOW_CTRL_TX;
911 bnx2_5709s_linkup(struct bnx2 *bp)
917 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
918 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
919 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
921 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
922 bp->line_speed = bp->req_line_speed;
923 bp->duplex = bp->req_duplex;
926 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
928 case MII_BNX2_GP_TOP_AN_SPEED_10:
929 bp->line_speed = SPEED_10;
931 case MII_BNX2_GP_TOP_AN_SPEED_100:
932 bp->line_speed = SPEED_100;
934 case MII_BNX2_GP_TOP_AN_SPEED_1G:
935 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
936 bp->line_speed = SPEED_1000;
938 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
939 bp->line_speed = SPEED_2500;
942 if (val & MII_BNX2_GP_TOP_AN_FD)
943 bp->duplex = DUPLEX_FULL;
945 bp->duplex = DUPLEX_HALF;
950 bnx2_5708s_linkup(struct bnx2 *bp)
955 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
956 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
957 case BCM5708S_1000X_STAT1_SPEED_10:
958 bp->line_speed = SPEED_10;
960 case BCM5708S_1000X_STAT1_SPEED_100:
961 bp->line_speed = SPEED_100;
963 case BCM5708S_1000X_STAT1_SPEED_1G:
964 bp->line_speed = SPEED_1000;
966 case BCM5708S_1000X_STAT1_SPEED_2G5:
967 bp->line_speed = SPEED_2500;
970 if (val & BCM5708S_1000X_STAT1_FD)
971 bp->duplex = DUPLEX_FULL;
973 bp->duplex = DUPLEX_HALF;
979 bnx2_5706s_linkup(struct bnx2 *bp)
981 u32 bmcr, local_adv, remote_adv, common;
984 bp->line_speed = SPEED_1000;
986 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
987 if (bmcr & BMCR_FULLDPLX) {
988 bp->duplex = DUPLEX_FULL;
991 bp->duplex = DUPLEX_HALF;
994 if (!(bmcr & BMCR_ANENABLE)) {
998 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
999 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1001 common = local_adv & remote_adv;
1002 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
1004 if (common & ADVERTISE_1000XFULL) {
1005 bp->duplex = DUPLEX_FULL;
1008 bp->duplex = DUPLEX_HALF;
1016 bnx2_copper_linkup(struct bnx2 *bp)
1020 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1021 if (bmcr & BMCR_ANENABLE) {
1022 u32 local_adv, remote_adv, common;
1024 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
1025 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
1027 common = local_adv & (remote_adv >> 2);
1028 if (common & ADVERTISE_1000FULL) {
1029 bp->line_speed = SPEED_1000;
1030 bp->duplex = DUPLEX_FULL;
1032 else if (common & ADVERTISE_1000HALF) {
1033 bp->line_speed = SPEED_1000;
1034 bp->duplex = DUPLEX_HALF;
1037 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
1038 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
1040 common = local_adv & remote_adv;
1041 if (common & ADVERTISE_100FULL) {
1042 bp->line_speed = SPEED_100;
1043 bp->duplex = DUPLEX_FULL;
1045 else if (common & ADVERTISE_100HALF) {
1046 bp->line_speed = SPEED_100;
1047 bp->duplex = DUPLEX_HALF;
1049 else if (common & ADVERTISE_10FULL) {
1050 bp->line_speed = SPEED_10;
1051 bp->duplex = DUPLEX_FULL;
1053 else if (common & ADVERTISE_10HALF) {
1054 bp->line_speed = SPEED_10;
1055 bp->duplex = DUPLEX_HALF;
1064 if (bmcr & BMCR_SPEED100) {
1065 bp->line_speed = SPEED_100;
1068 bp->line_speed = SPEED_10;
1070 if (bmcr & BMCR_FULLDPLX) {
1071 bp->duplex = DUPLEX_FULL;
1074 bp->duplex = DUPLEX_HALF;
1082 bnx2_init_rx_context(struct bnx2 *bp, u32 cid)
1084 u32 val, rx_cid_addr = GET_CID_ADDR(cid);
1086 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
1087 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
1090 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1091 u32 lo_water, hi_water;
1093 if (bp->flow_ctrl & FLOW_CTRL_TX)
1094 lo_water = BNX2_L2CTX_LO_WATER_MARK_DEFAULT;
1096 lo_water = BNX2_L2CTX_LO_WATER_MARK_DIS;
1097 if (lo_water >= bp->rx_ring_size)
1100 hi_water = bp->rx_ring_size / 4;
1102 if (hi_water <= lo_water)
1105 hi_water /= BNX2_L2CTX_HI_WATER_MARK_SCALE;
1106 lo_water /= BNX2_L2CTX_LO_WATER_MARK_SCALE;
1110 else if (hi_water == 0)
1112 val |= lo_water | (hi_water << BNX2_L2CTX_HI_WATER_MARK_SHIFT);
1114 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
1118 bnx2_init_all_rx_contexts(struct bnx2 *bp)
1123 for (i = 0, cid = RX_CID; i < bp->num_rx_rings; i++, cid++) {
1126 bnx2_init_rx_context(bp, cid);
1131 bnx2_set_mac_link(struct bnx2 *bp)
1135 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
1136 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
1137 (bp->duplex == DUPLEX_HALF)) {
1138 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
1141 /* Configure the EMAC mode register. */
1142 val = REG_RD(bp, BNX2_EMAC_MODE);
1144 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1145 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1146 BNX2_EMAC_MODE_25G_MODE);
1149 switch (bp->line_speed) {
1151 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
1152 val |= BNX2_EMAC_MODE_PORT_MII_10M;
1157 val |= BNX2_EMAC_MODE_PORT_MII;
1160 val |= BNX2_EMAC_MODE_25G_MODE;
1163 val |= BNX2_EMAC_MODE_PORT_GMII;
1168 val |= BNX2_EMAC_MODE_PORT_GMII;
1171 /* Set the MAC to operate in the appropriate duplex mode. */
1172 if (bp->duplex == DUPLEX_HALF)
1173 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
1174 REG_WR(bp, BNX2_EMAC_MODE, val);
1176 /* Enable/disable rx PAUSE. */
1177 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
1179 if (bp->flow_ctrl & FLOW_CTRL_RX)
1180 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1181 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1183 /* Enable/disable tx PAUSE. */
1184 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1185 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1187 if (bp->flow_ctrl & FLOW_CTRL_TX)
1188 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1189 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1191 /* Acknowledge the interrupt. */
1192 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1194 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1195 bnx2_init_all_rx_contexts(bp);
1199 bnx2_enable_bmsr1(struct bnx2 *bp)
1201 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1202 (CHIP_NUM(bp) == CHIP_NUM_5709))
1203 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1204 MII_BNX2_BLK_ADDR_GP_STATUS);
1208 bnx2_disable_bmsr1(struct bnx2 *bp)
1210 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1211 (CHIP_NUM(bp) == CHIP_NUM_5709))
1212 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1213 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1217 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1222 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1225 if (bp->autoneg & AUTONEG_SPEED)
1226 bp->advertising |= ADVERTISED_2500baseX_Full;
1228 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1229 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1231 bnx2_read_phy(bp, bp->mii_up1, &up1);
1232 if (!(up1 & BCM5708S_UP1_2G5)) {
1233 up1 |= BCM5708S_UP1_2G5;
1234 bnx2_write_phy(bp, bp->mii_up1, up1);
1238 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1239 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1240 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1246 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1251 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1254 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1255 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1257 bnx2_read_phy(bp, bp->mii_up1, &up1);
1258 if (up1 & BCM5708S_UP1_2G5) {
1259 up1 &= ~BCM5708S_UP1_2G5;
1260 bnx2_write_phy(bp, bp->mii_up1, up1);
1264 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1265 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1266 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1272 bnx2_enable_forced_2g5(struct bnx2 *bp)
1276 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1279 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1282 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1283 MII_BNX2_BLK_ADDR_SERDES_DIG);
1284 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1285 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1286 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1287 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1289 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1290 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1291 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1293 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1294 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1295 bmcr |= BCM5708S_BMCR_FORCE_2500;
1298 if (bp->autoneg & AUTONEG_SPEED) {
1299 bmcr &= ~BMCR_ANENABLE;
1300 if (bp->req_duplex == DUPLEX_FULL)
1301 bmcr |= BMCR_FULLDPLX;
1303 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1307 bnx2_disable_forced_2g5(struct bnx2 *bp)
1311 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
1314 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1317 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1318 MII_BNX2_BLK_ADDR_SERDES_DIG);
1319 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1320 val &= ~MII_BNX2_SD_MISC1_FORCE;
1321 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1323 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1324 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1325 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1327 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1328 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1329 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1332 if (bp->autoneg & AUTONEG_SPEED)
1333 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1334 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1338 bnx2_5706s_force_link_dn(struct bnx2 *bp, int start)
1342 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_SERDES_CTL);
1343 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1345 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val & 0xff0f);
1347 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val | 0xc0);
1351 bnx2_set_link(struct bnx2 *bp)
1356 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1361 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1364 link_up = bp->link_up;
1366 bnx2_enable_bmsr1(bp);
1367 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1368 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1369 bnx2_disable_bmsr1(bp);
1371 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1372 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1375 if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) {
1376 bnx2_5706s_force_link_dn(bp, 0);
1377 bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN;
1379 val = REG_RD(bp, BNX2_EMAC_STATUS);
1381 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
1382 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1383 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
1385 if ((val & BNX2_EMAC_STATUS_LINK) &&
1386 !(an_dbg & MISC_SHDW_AN_DBG_NOSYNC))
1387 bmsr |= BMSR_LSTATUS;
1389 bmsr &= ~BMSR_LSTATUS;
1392 if (bmsr & BMSR_LSTATUS) {
1395 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1396 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1397 bnx2_5706s_linkup(bp);
1398 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1399 bnx2_5708s_linkup(bp);
1400 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1401 bnx2_5709s_linkup(bp);
1404 bnx2_copper_linkup(bp);
1406 bnx2_resolve_flow_ctrl(bp);
1409 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
1410 (bp->autoneg & AUTONEG_SPEED))
1411 bnx2_disable_forced_2g5(bp);
1413 if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) {
1416 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1417 bmcr |= BMCR_ANENABLE;
1418 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1420 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
1425 if (bp->link_up != link_up) {
1426 bnx2_report_link(bp);
1429 bnx2_set_mac_link(bp);
1435 bnx2_reset_phy(struct bnx2 *bp)
1440 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1442 #define PHY_RESET_MAX_WAIT 100
1443 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1446 bnx2_read_phy(bp, bp->mii_bmcr, ®);
1447 if (!(reg & BMCR_RESET)) {
1452 if (i == PHY_RESET_MAX_WAIT) {
1459 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1463 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1464 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1466 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1467 adv = ADVERTISE_1000XPAUSE;
1470 adv = ADVERTISE_PAUSE_CAP;
1473 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1474 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1475 adv = ADVERTISE_1000XPSE_ASYM;
1478 adv = ADVERTISE_PAUSE_ASYM;
1481 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1482 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1483 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1486 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1492 static int bnx2_fw_sync(struct bnx2 *, u32, int, int);
1495 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1497 u32 speed_arg = 0, pause_adv;
1499 pause_adv = bnx2_phy_get_pause_adv(bp);
1501 if (bp->autoneg & AUTONEG_SPEED) {
1502 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1503 if (bp->advertising & ADVERTISED_10baseT_Half)
1504 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1505 if (bp->advertising & ADVERTISED_10baseT_Full)
1506 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1507 if (bp->advertising & ADVERTISED_100baseT_Half)
1508 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1509 if (bp->advertising & ADVERTISED_100baseT_Full)
1510 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1511 if (bp->advertising & ADVERTISED_1000baseT_Full)
1512 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1513 if (bp->advertising & ADVERTISED_2500baseX_Full)
1514 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1516 if (bp->req_line_speed == SPEED_2500)
1517 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1518 else if (bp->req_line_speed == SPEED_1000)
1519 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1520 else if (bp->req_line_speed == SPEED_100) {
1521 if (bp->req_duplex == DUPLEX_FULL)
1522 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1524 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1525 } else if (bp->req_line_speed == SPEED_10) {
1526 if (bp->req_duplex == DUPLEX_FULL)
1527 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1529 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1533 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1534 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1535 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_PAUSE_ASYM))
1536 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1538 if (port == PORT_TP)
1539 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1540 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1542 bnx2_shmem_wr(bp, BNX2_DRV_MB_ARG0, speed_arg);
1544 spin_unlock_bh(&bp->phy_lock);
1545 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 1, 0);
1546 spin_lock_bh(&bp->phy_lock);
1552 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1557 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
1558 return (bnx2_setup_remote_phy(bp, port));
1560 if (!(bp->autoneg & AUTONEG_SPEED)) {
1562 int force_link_down = 0;
1564 if (bp->req_line_speed == SPEED_2500) {
1565 if (!bnx2_test_and_enable_2g5(bp))
1566 force_link_down = 1;
1567 } else if (bp->req_line_speed == SPEED_1000) {
1568 if (bnx2_test_and_disable_2g5(bp))
1569 force_link_down = 1;
1571 bnx2_read_phy(bp, bp->mii_adv, &adv);
1572 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1574 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1575 new_bmcr = bmcr & ~BMCR_ANENABLE;
1576 new_bmcr |= BMCR_SPEED1000;
1578 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1579 if (bp->req_line_speed == SPEED_2500)
1580 bnx2_enable_forced_2g5(bp);
1581 else if (bp->req_line_speed == SPEED_1000) {
1582 bnx2_disable_forced_2g5(bp);
1583 new_bmcr &= ~0x2000;
1586 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1587 if (bp->req_line_speed == SPEED_2500)
1588 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1590 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1593 if (bp->req_duplex == DUPLEX_FULL) {
1594 adv |= ADVERTISE_1000XFULL;
1595 new_bmcr |= BMCR_FULLDPLX;
1598 adv |= ADVERTISE_1000XHALF;
1599 new_bmcr &= ~BMCR_FULLDPLX;
1601 if ((new_bmcr != bmcr) || (force_link_down)) {
1602 /* Force a link down visible on the other side */
1604 bnx2_write_phy(bp, bp->mii_adv, adv &
1605 ~(ADVERTISE_1000XFULL |
1606 ADVERTISE_1000XHALF));
1607 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1608 BMCR_ANRESTART | BMCR_ANENABLE);
1611 netif_carrier_off(bp->dev);
1612 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1613 bnx2_report_link(bp);
1615 bnx2_write_phy(bp, bp->mii_adv, adv);
1616 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1618 bnx2_resolve_flow_ctrl(bp);
1619 bnx2_set_mac_link(bp);
1624 bnx2_test_and_enable_2g5(bp);
1626 if (bp->advertising & ADVERTISED_1000baseT_Full)
1627 new_adv |= ADVERTISE_1000XFULL;
1629 new_adv |= bnx2_phy_get_pause_adv(bp);
1631 bnx2_read_phy(bp, bp->mii_adv, &adv);
1632 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1634 bp->serdes_an_pending = 0;
1635 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1636 /* Force a link down visible on the other side */
1638 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1639 spin_unlock_bh(&bp->phy_lock);
1641 spin_lock_bh(&bp->phy_lock);
1644 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1645 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1647 /* Speed up link-up time when the link partner
1648 * does not autonegotiate which is very common
1649 * in blade servers. Some blade servers use
1650 * IPMI for kerboard input and it's important
1651 * to minimize link disruptions. Autoneg. involves
1652 * exchanging base pages plus 3 next pages and
1653 * normally completes in about 120 msec.
1655 bp->current_interval = SERDES_AN_TIMEOUT;
1656 bp->serdes_an_pending = 1;
1657 mod_timer(&bp->timer, jiffies + bp->current_interval);
1659 bnx2_resolve_flow_ctrl(bp);
1660 bnx2_set_mac_link(bp);
1666 #define ETHTOOL_ALL_FIBRE_SPEED \
1667 (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \
1668 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1669 (ADVERTISED_1000baseT_Full)
1671 #define ETHTOOL_ALL_COPPER_SPEED \
1672 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1673 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1674 ADVERTISED_1000baseT_Full)
1676 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1677 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1679 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1682 bnx2_set_default_remote_link(struct bnx2 *bp)
1686 if (bp->phy_port == PORT_TP)
1687 link = bnx2_shmem_rd(bp, BNX2_RPHY_COPPER_LINK);
1689 link = bnx2_shmem_rd(bp, BNX2_RPHY_SERDES_LINK);
1691 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1692 bp->req_line_speed = 0;
1693 bp->autoneg |= AUTONEG_SPEED;
1694 bp->advertising = ADVERTISED_Autoneg;
1695 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1696 bp->advertising |= ADVERTISED_10baseT_Half;
1697 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1698 bp->advertising |= ADVERTISED_10baseT_Full;
1699 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1700 bp->advertising |= ADVERTISED_100baseT_Half;
1701 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1702 bp->advertising |= ADVERTISED_100baseT_Full;
1703 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1704 bp->advertising |= ADVERTISED_1000baseT_Full;
1705 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1706 bp->advertising |= ADVERTISED_2500baseX_Full;
1709 bp->advertising = 0;
1710 bp->req_duplex = DUPLEX_FULL;
1711 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1712 bp->req_line_speed = SPEED_10;
1713 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1714 bp->req_duplex = DUPLEX_HALF;
1716 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1717 bp->req_line_speed = SPEED_100;
1718 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1719 bp->req_duplex = DUPLEX_HALF;
1721 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1722 bp->req_line_speed = SPEED_1000;
1723 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1724 bp->req_line_speed = SPEED_2500;
1729 bnx2_set_default_link(struct bnx2 *bp)
1731 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
1732 bnx2_set_default_remote_link(bp);
1736 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1737 bp->req_line_speed = 0;
1738 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1741 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1743 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG);
1744 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1745 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1747 bp->req_line_speed = bp->line_speed = SPEED_1000;
1748 bp->req_duplex = DUPLEX_FULL;
1751 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1755 bnx2_send_heart_beat(struct bnx2 *bp)
1760 spin_lock(&bp->indirect_lock);
1761 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1762 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1763 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1764 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1765 spin_unlock(&bp->indirect_lock);
1769 bnx2_remote_phy_event(struct bnx2 *bp)
1772 u8 link_up = bp->link_up;
1775 msg = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
1777 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1778 bnx2_send_heart_beat(bp);
1780 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1782 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1788 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1789 bp->duplex = DUPLEX_FULL;
1791 case BNX2_LINK_STATUS_10HALF:
1792 bp->duplex = DUPLEX_HALF;
1793 case BNX2_LINK_STATUS_10FULL:
1794 bp->line_speed = SPEED_10;
1796 case BNX2_LINK_STATUS_100HALF:
1797 bp->duplex = DUPLEX_HALF;
1798 case BNX2_LINK_STATUS_100BASE_T4:
1799 case BNX2_LINK_STATUS_100FULL:
1800 bp->line_speed = SPEED_100;
1802 case BNX2_LINK_STATUS_1000HALF:
1803 bp->duplex = DUPLEX_HALF;
1804 case BNX2_LINK_STATUS_1000FULL:
1805 bp->line_speed = SPEED_1000;
1807 case BNX2_LINK_STATUS_2500HALF:
1808 bp->duplex = DUPLEX_HALF;
1809 case BNX2_LINK_STATUS_2500FULL:
1810 bp->line_speed = SPEED_2500;
1818 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1819 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1820 if (bp->duplex == DUPLEX_FULL)
1821 bp->flow_ctrl = bp->req_flow_ctrl;
1823 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1824 bp->flow_ctrl |= FLOW_CTRL_TX;
1825 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1826 bp->flow_ctrl |= FLOW_CTRL_RX;
1829 old_port = bp->phy_port;
1830 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1831 bp->phy_port = PORT_FIBRE;
1833 bp->phy_port = PORT_TP;
1835 if (old_port != bp->phy_port)
1836 bnx2_set_default_link(bp);
1839 if (bp->link_up != link_up)
1840 bnx2_report_link(bp);
1842 bnx2_set_mac_link(bp);
1846 bnx2_set_remote_link(struct bnx2 *bp)
1850 evt_code = bnx2_shmem_rd(bp, BNX2_FW_EVT_CODE_MB);
1852 case BNX2_FW_EVT_CODE_LINK_EVENT:
1853 bnx2_remote_phy_event(bp);
1855 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1857 bnx2_send_heart_beat(bp);
1864 bnx2_setup_copper_phy(struct bnx2 *bp)
1869 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1871 if (bp->autoneg & AUTONEG_SPEED) {
1872 u32 adv_reg, adv1000_reg;
1873 u32 new_adv_reg = 0;
1874 u32 new_adv1000_reg = 0;
1876 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1877 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1878 ADVERTISE_PAUSE_ASYM);
1880 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1881 adv1000_reg &= PHY_ALL_1000_SPEED;
1883 if (bp->advertising & ADVERTISED_10baseT_Half)
1884 new_adv_reg |= ADVERTISE_10HALF;
1885 if (bp->advertising & ADVERTISED_10baseT_Full)
1886 new_adv_reg |= ADVERTISE_10FULL;
1887 if (bp->advertising & ADVERTISED_100baseT_Half)
1888 new_adv_reg |= ADVERTISE_100HALF;
1889 if (bp->advertising & ADVERTISED_100baseT_Full)
1890 new_adv_reg |= ADVERTISE_100FULL;
1891 if (bp->advertising & ADVERTISED_1000baseT_Full)
1892 new_adv1000_reg |= ADVERTISE_1000FULL;
1894 new_adv_reg |= ADVERTISE_CSMA;
1896 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1898 if ((adv1000_reg != new_adv1000_reg) ||
1899 (adv_reg != new_adv_reg) ||
1900 ((bmcr & BMCR_ANENABLE) == 0)) {
1902 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1903 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1904 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1907 else if (bp->link_up) {
1908 /* Flow ctrl may have changed from auto to forced */
1909 /* or vice-versa. */
1911 bnx2_resolve_flow_ctrl(bp);
1912 bnx2_set_mac_link(bp);
1918 if (bp->req_line_speed == SPEED_100) {
1919 new_bmcr |= BMCR_SPEED100;
1921 if (bp->req_duplex == DUPLEX_FULL) {
1922 new_bmcr |= BMCR_FULLDPLX;
1924 if (new_bmcr != bmcr) {
1927 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1928 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1930 if (bmsr & BMSR_LSTATUS) {
1931 /* Force link down */
1932 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1933 spin_unlock_bh(&bp->phy_lock);
1935 spin_lock_bh(&bp->phy_lock);
1937 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1938 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1941 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1943 /* Normally, the new speed is setup after the link has
1944 * gone down and up again. In some cases, link will not go
1945 * down so we need to set up the new speed here.
1947 if (bmsr & BMSR_LSTATUS) {
1948 bp->line_speed = bp->req_line_speed;
1949 bp->duplex = bp->req_duplex;
1950 bnx2_resolve_flow_ctrl(bp);
1951 bnx2_set_mac_link(bp);
1954 bnx2_resolve_flow_ctrl(bp);
1955 bnx2_set_mac_link(bp);
1961 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1963 if (bp->loopback == MAC_LOOPBACK)
1966 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
1967 return (bnx2_setup_serdes_phy(bp, port));
1970 return (bnx2_setup_copper_phy(bp));
1975 bnx2_init_5709s_phy(struct bnx2 *bp, int reset_phy)
1979 bp->mii_bmcr = MII_BMCR + 0x10;
1980 bp->mii_bmsr = MII_BMSR + 0x10;
1981 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1982 bp->mii_adv = MII_ADVERTISE + 0x10;
1983 bp->mii_lpa = MII_LPA + 0x10;
1984 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1986 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1987 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1989 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1993 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1995 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1996 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1997 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1998 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
2000 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
2001 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
2002 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
2003 val |= BCM5708S_UP1_2G5;
2005 val &= ~BCM5708S_UP1_2G5;
2006 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
2008 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
2009 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
2010 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
2011 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
2013 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
2015 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
2016 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
2017 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
2019 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
2025 bnx2_init_5708s_phy(struct bnx2 *bp, int reset_phy)
2032 bp->mii_up1 = BCM5708S_UP1;
2034 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
2035 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
2036 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2038 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
2039 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
2040 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
2042 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
2043 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
2044 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
2046 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) {
2047 bnx2_read_phy(bp, BCM5708S_UP1, &val);
2048 val |= BCM5708S_UP1_2G5;
2049 bnx2_write_phy(bp, BCM5708S_UP1, val);
2052 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
2053 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
2054 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
2055 /* increase tx signal amplitude */
2056 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2057 BCM5708S_BLK_ADDR_TX_MISC);
2058 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
2059 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
2060 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
2061 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
2064 val = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_CONFIG) &
2065 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
2070 is_backplane = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
2071 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
2072 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2073 BCM5708S_BLK_ADDR_TX_MISC);
2074 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
2075 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
2076 BCM5708S_BLK_ADDR_DIG);
2083 bnx2_init_5706s_phy(struct bnx2 *bp, int reset_phy)
2088 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
2090 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2091 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
2093 if (bp->dev->mtu > 1500) {
2096 /* Set extended packet length bit */
2097 bnx2_write_phy(bp, 0x18, 0x7);
2098 bnx2_read_phy(bp, 0x18, &val);
2099 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
2101 bnx2_write_phy(bp, 0x1c, 0x6c00);
2102 bnx2_read_phy(bp, 0x1c, &val);
2103 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
2108 bnx2_write_phy(bp, 0x18, 0x7);
2109 bnx2_read_phy(bp, 0x18, &val);
2110 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2112 bnx2_write_phy(bp, 0x1c, 0x6c00);
2113 bnx2_read_phy(bp, 0x1c, &val);
2114 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
2121 bnx2_init_copper_phy(struct bnx2 *bp, int reset_phy)
2128 if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) {
2129 bnx2_write_phy(bp, 0x18, 0x0c00);
2130 bnx2_write_phy(bp, 0x17, 0x000a);
2131 bnx2_write_phy(bp, 0x15, 0x310b);
2132 bnx2_write_phy(bp, 0x17, 0x201f);
2133 bnx2_write_phy(bp, 0x15, 0x9506);
2134 bnx2_write_phy(bp, 0x17, 0x401f);
2135 bnx2_write_phy(bp, 0x15, 0x14e2);
2136 bnx2_write_phy(bp, 0x18, 0x0400);
2139 if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) {
2140 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
2141 MII_BNX2_DSP_EXPAND_REG | 0x8);
2142 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
2144 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
2147 if (bp->dev->mtu > 1500) {
2148 /* Set extended packet length bit */
2149 bnx2_write_phy(bp, 0x18, 0x7);
2150 bnx2_read_phy(bp, 0x18, &val);
2151 bnx2_write_phy(bp, 0x18, val | 0x4000);
2153 bnx2_read_phy(bp, 0x10, &val);
2154 bnx2_write_phy(bp, 0x10, val | 0x1);
2157 bnx2_write_phy(bp, 0x18, 0x7);
2158 bnx2_read_phy(bp, 0x18, &val);
2159 bnx2_write_phy(bp, 0x18, val & ~0x4007);
2161 bnx2_read_phy(bp, 0x10, &val);
2162 bnx2_write_phy(bp, 0x10, val & ~0x1);
2165 /* ethernet@wirespeed */
2166 bnx2_write_phy(bp, 0x18, 0x7007);
2167 bnx2_read_phy(bp, 0x18, &val);
2168 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
2174 bnx2_init_phy(struct bnx2 *bp, int reset_phy)
2179 bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK;
2180 bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY;
2182 bp->mii_bmcr = MII_BMCR;
2183 bp->mii_bmsr = MII_BMSR;
2184 bp->mii_bmsr1 = MII_BMSR;
2185 bp->mii_adv = MII_ADVERTISE;
2186 bp->mii_lpa = MII_LPA;
2188 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2190 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
2193 bnx2_read_phy(bp, MII_PHYSID1, &val);
2194 bp->phy_id = val << 16;
2195 bnx2_read_phy(bp, MII_PHYSID2, &val);
2196 bp->phy_id |= val & 0xffff;
2198 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
2199 if (CHIP_NUM(bp) == CHIP_NUM_5706)
2200 rc = bnx2_init_5706s_phy(bp, reset_phy);
2201 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
2202 rc = bnx2_init_5708s_phy(bp, reset_phy);
2203 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
2204 rc = bnx2_init_5709s_phy(bp, reset_phy);
2207 rc = bnx2_init_copper_phy(bp, reset_phy);
2212 rc = bnx2_setup_phy(bp, bp->phy_port);
2218 bnx2_set_mac_loopback(struct bnx2 *bp)
2222 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2223 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2224 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2225 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2230 static int bnx2_test_link(struct bnx2 *);
2233 bnx2_set_phy_loopback(struct bnx2 *bp)
2238 spin_lock_bh(&bp->phy_lock);
2239 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2241 spin_unlock_bh(&bp->phy_lock);
2245 for (i = 0; i < 10; i++) {
2246 if (bnx2_test_link(bp) == 0)
2251 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2252 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2253 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2254 BNX2_EMAC_MODE_25G_MODE);
2256 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2257 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2263 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int ack, int silent)
2269 msg_data |= bp->fw_wr_seq;
2271 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2276 /* wait for an acknowledgement. */
2277 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2280 val = bnx2_shmem_rd(bp, BNX2_FW_MB);
2282 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2285 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2288 /* If we timed out, inform the firmware that this is the case. */
2289 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2291 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2294 msg_data &= ~BNX2_DRV_MSG_CODE;
2295 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2297 bnx2_shmem_wr(bp, BNX2_DRV_MB, msg_data);
2302 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2309 bnx2_init_5709_context(struct bnx2 *bp)
2314 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2315 val |= (BCM_PAGE_BITS - 8) << 16;
2316 REG_WR(bp, BNX2_CTX_COMMAND, val);
2317 for (i = 0; i < 10; i++) {
2318 val = REG_RD(bp, BNX2_CTX_COMMAND);
2319 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2323 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2326 for (i = 0; i < bp->ctx_pages; i++) {
2330 memset(bp->ctx_blk[i], 0, BCM_PAGE_SIZE);
2334 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2335 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2336 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2337 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2338 (u64) bp->ctx_blk_mapping[i] >> 32);
2339 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2340 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2341 for (j = 0; j < 10; j++) {
2343 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2344 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2348 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2357 bnx2_init_context(struct bnx2 *bp)
2363 u32 vcid_addr, pcid_addr, offset;
2368 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2371 vcid_addr = GET_PCID_ADDR(vcid);
2373 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2378 pcid_addr = GET_PCID_ADDR(new_vcid);
2381 vcid_addr = GET_CID_ADDR(vcid);
2382 pcid_addr = vcid_addr;
2385 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2386 vcid_addr += (i << PHY_CTX_SHIFT);
2387 pcid_addr += (i << PHY_CTX_SHIFT);
2389 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2390 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2392 /* Zero out the context. */
2393 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2394 bnx2_ctx_wr(bp, vcid_addr, offset, 0);
2400 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2406 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2407 if (good_mbuf == NULL) {
2408 printk(KERN_ERR PFX "Failed to allocate memory in "
2409 "bnx2_alloc_bad_rbuf\n");
2413 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2414 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2418 /* Allocate a bunch of mbufs and save the good ones in an array. */
2419 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2420 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2421 bnx2_reg_wr_ind(bp, BNX2_RBUF_COMMAND,
2422 BNX2_RBUF_COMMAND_ALLOC_REQ);
2424 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_FW_BUF_ALLOC);
2426 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2428 /* The addresses with Bit 9 set are bad memory blocks. */
2429 if (!(val & (1 << 9))) {
2430 good_mbuf[good_mbuf_cnt] = (u16) val;
2434 val = bnx2_reg_rd_ind(bp, BNX2_RBUF_STATUS1);
2437 /* Free the good ones back to the mbuf pool thus discarding
2438 * all the bad ones. */
2439 while (good_mbuf_cnt) {
2442 val = good_mbuf[good_mbuf_cnt];
2443 val = (val << 9) | val | 1;
2445 bnx2_reg_wr_ind(bp, BNX2_RBUF_FW_BUF_FREE, val);
2452 bnx2_set_mac_addr(struct bnx2 *bp, u8 *mac_addr, u32 pos)
2456 val = (mac_addr[0] << 8) | mac_addr[1];
2458 REG_WR(bp, BNX2_EMAC_MAC_MATCH0 + (pos * 8), val);
2460 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2461 (mac_addr[4] << 8) | mac_addr[5];
2463 REG_WR(bp, BNX2_EMAC_MAC_MATCH1 + (pos * 8), val);
2467 bnx2_alloc_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2470 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2471 struct rx_bd *rxbd =
2472 &rxr->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2473 struct page *page = alloc_page(GFP_ATOMIC);
2477 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2478 PCI_DMA_FROMDEVICE);
2480 pci_unmap_addr_set(rx_pg, mapping, mapping);
2481 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2482 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2487 bnx2_free_rx_page(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2489 struct sw_pg *rx_pg = &rxr->rx_pg_ring[index];
2490 struct page *page = rx_pg->page;
2495 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2496 PCI_DMA_FROMDEVICE);
2503 bnx2_alloc_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, u16 index)
2505 struct sk_buff *skb;
2506 struct sw_bd *rx_buf = &rxr->rx_buf_ring[index];
2508 struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2509 unsigned long align;
2511 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2516 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2517 skb_reserve(skb, BNX2_RX_ALIGN - align);
2519 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2520 PCI_DMA_FROMDEVICE);
2523 pci_unmap_addr_set(rx_buf, mapping, mapping);
2525 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2526 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2528 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2534 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2536 struct status_block *sblk = bnapi->status_blk.msi;
2537 u32 new_link_state, old_link_state;
2540 new_link_state = sblk->status_attn_bits & event;
2541 old_link_state = sblk->status_attn_bits_ack & event;
2542 if (new_link_state != old_link_state) {
2544 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2546 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2554 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2556 spin_lock(&bp->phy_lock);
2558 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE))
2560 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2561 bnx2_set_remote_link(bp);
2563 spin_unlock(&bp->phy_lock);
2568 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2572 /* Tell compiler that status block fields can change. */
2574 cons = *bnapi->hw_tx_cons_ptr;
2575 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2581 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2583 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
2584 u16 hw_cons, sw_cons, sw_ring_cons;
2585 int tx_pkt = 0, index;
2586 struct netdev_queue *txq;
2588 index = (bnapi - bp->bnx2_napi);
2589 txq = netdev_get_tx_queue(bp->dev, index);
2591 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2592 sw_cons = txr->tx_cons;
2594 while (sw_cons != hw_cons) {
2595 struct sw_bd *tx_buf;
2596 struct sk_buff *skb;
2599 sw_ring_cons = TX_RING_IDX(sw_cons);
2601 tx_buf = &txr->tx_buf_ring[sw_ring_cons];
2604 /* partial BD completions possible with TSO packets */
2605 if (skb_is_gso(skb)) {
2606 u16 last_idx, last_ring_idx;
2608 last_idx = sw_cons +
2609 skb_shinfo(skb)->nr_frags + 1;
2610 last_ring_idx = sw_ring_cons +
2611 skb_shinfo(skb)->nr_frags + 1;
2612 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2615 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2620 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2621 skb_headlen(skb), PCI_DMA_TODEVICE);
2624 last = skb_shinfo(skb)->nr_frags;
2626 for (i = 0; i < last; i++) {
2627 sw_cons = NEXT_TX_BD(sw_cons);
2629 pci_unmap_page(bp->pdev,
2631 &txr->tx_buf_ring[TX_RING_IDX(sw_cons)],
2633 skb_shinfo(skb)->frags[i].size,
2637 sw_cons = NEXT_TX_BD(sw_cons);
2641 if (tx_pkt == budget)
2644 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2647 txr->hw_tx_cons = hw_cons;
2648 txr->tx_cons = sw_cons;
2650 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2651 * before checking for netif_tx_queue_stopped(). Without the
2652 * memory barrier, there is a small possibility that bnx2_start_xmit()
2653 * will miss it and cause the queue to be stopped forever.
2657 if (unlikely(netif_tx_queue_stopped(txq)) &&
2658 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
2659 __netif_tx_lock(txq, smp_processor_id());
2660 if ((netif_tx_queue_stopped(txq)) &&
2661 (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh))
2662 netif_tx_wake_queue(txq);
2663 __netif_tx_unlock(txq);
2670 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2671 struct sk_buff *skb, int count)
2673 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2674 struct rx_bd *cons_bd, *prod_bd;
2677 u16 hw_prod = rxr->rx_pg_prod, prod;
2678 u16 cons = rxr->rx_pg_cons;
2680 for (i = 0; i < count; i++) {
2681 prod = RX_PG_RING_IDX(hw_prod);
2683 prod_rx_pg = &rxr->rx_pg_ring[prod];
2684 cons_rx_pg = &rxr->rx_pg_ring[cons];
2685 cons_bd = &rxr->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2686 prod_bd = &rxr->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2688 if (i == 0 && skb) {
2690 struct skb_shared_info *shinfo;
2692 shinfo = skb_shinfo(skb);
2694 page = shinfo->frags[shinfo->nr_frags].page;
2695 shinfo->frags[shinfo->nr_frags].page = NULL;
2696 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2697 PCI_DMA_FROMDEVICE);
2698 cons_rx_pg->page = page;
2699 pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
2703 prod_rx_pg->page = cons_rx_pg->page;
2704 cons_rx_pg->page = NULL;
2705 pci_unmap_addr_set(prod_rx_pg, mapping,
2706 pci_unmap_addr(cons_rx_pg, mapping));
2708 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2709 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2712 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2713 hw_prod = NEXT_RX_BD(hw_prod);
2715 rxr->rx_pg_prod = hw_prod;
2716 rxr->rx_pg_cons = cons;
2720 bnx2_reuse_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr,
2721 struct sk_buff *skb, u16 cons, u16 prod)
2723 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2724 struct rx_bd *cons_bd, *prod_bd;
2726 cons_rx_buf = &rxr->rx_buf_ring[cons];
2727 prod_rx_buf = &rxr->rx_buf_ring[prod];
2729 pci_dma_sync_single_for_device(bp->pdev,
2730 pci_unmap_addr(cons_rx_buf, mapping),
2731 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2733 rxr->rx_prod_bseq += bp->rx_buf_use_size;
2735 prod_rx_buf->skb = skb;
2740 pci_unmap_addr_set(prod_rx_buf, mapping,
2741 pci_unmap_addr(cons_rx_buf, mapping));
2743 cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2744 prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2745 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2746 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2750 bnx2_rx_skb(struct bnx2 *bp, struct bnx2_rx_ring_info *rxr, struct sk_buff *skb,
2751 unsigned int len, unsigned int hdr_len, dma_addr_t dma_addr,
2755 u16 prod = ring_idx & 0xffff;
2757 err = bnx2_alloc_rx_skb(bp, rxr, prod);
2758 if (unlikely(err)) {
2759 bnx2_reuse_rx_skb(bp, rxr, skb, (u16) (ring_idx >> 16), prod);
2761 unsigned int raw_len = len + 4;
2762 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2764 bnx2_reuse_rx_skb_pages(bp, rxr, NULL, pages);
2769 skb_reserve(skb, BNX2_RX_OFFSET);
2770 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2771 PCI_DMA_FROMDEVICE);
2777 unsigned int i, frag_len, frag_size, pages;
2778 struct sw_pg *rx_pg;
2779 u16 pg_cons = rxr->rx_pg_cons;
2780 u16 pg_prod = rxr->rx_pg_prod;
2782 frag_size = len + 4 - hdr_len;
2783 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2784 skb_put(skb, hdr_len);
2786 for (i = 0; i < pages; i++) {
2787 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2788 if (unlikely(frag_len <= 4)) {
2789 unsigned int tail = 4 - frag_len;
2791 rxr->rx_pg_cons = pg_cons;
2792 rxr->rx_pg_prod = pg_prod;
2793 bnx2_reuse_rx_skb_pages(bp, rxr, NULL,
2800 &skb_shinfo(skb)->frags[i - 1];
2802 skb->data_len -= tail;
2803 skb->truesize -= tail;
2807 rx_pg = &rxr->rx_pg_ring[pg_cons];
2809 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2810 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2815 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2818 err = bnx2_alloc_rx_page(bp, rxr,
2819 RX_PG_RING_IDX(pg_prod));
2820 if (unlikely(err)) {
2821 rxr->rx_pg_cons = pg_cons;
2822 rxr->rx_pg_prod = pg_prod;
2823 bnx2_reuse_rx_skb_pages(bp, rxr, skb,
2828 frag_size -= frag_len;
2829 skb->data_len += frag_len;
2830 skb->truesize += frag_len;
2831 skb->len += frag_len;
2833 pg_prod = NEXT_RX_BD(pg_prod);
2834 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2836 rxr->rx_pg_prod = pg_prod;
2837 rxr->rx_pg_cons = pg_cons;
2843 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2847 /* Tell compiler that status block fields can change. */
2849 cons = *bnapi->hw_rx_cons_ptr;
2850 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2856 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2858 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
2859 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2860 struct l2_fhdr *rx_hdr;
2861 int rx_pkt = 0, pg_ring_used = 0;
2863 hw_cons = bnx2_get_hw_rx_cons(bnapi);
2864 sw_cons = rxr->rx_cons;
2865 sw_prod = rxr->rx_prod;
2867 /* Memory barrier necessary as speculative reads of the rx
2868 * buffer can be ahead of the index in the status block
2871 while (sw_cons != hw_cons) {
2872 unsigned int len, hdr_len;
2874 struct sw_bd *rx_buf;
2875 struct sk_buff *skb;
2876 dma_addr_t dma_addr;
2878 int hw_vlan __maybe_unused = 0;
2880 sw_ring_cons = RX_RING_IDX(sw_cons);
2881 sw_ring_prod = RX_RING_IDX(sw_prod);
2883 rx_buf = &rxr->rx_buf_ring[sw_ring_cons];
2888 dma_addr = pci_unmap_addr(rx_buf, mapping);
2890 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2891 BNX2_RX_OFFSET + BNX2_RX_COPY_THRESH,
2892 PCI_DMA_FROMDEVICE);
2894 rx_hdr = (struct l2_fhdr *) skb->data;
2895 len = rx_hdr->l2_fhdr_pkt_len;
2897 if ((status = rx_hdr->l2_fhdr_status) &
2898 (L2_FHDR_ERRORS_BAD_CRC |
2899 L2_FHDR_ERRORS_PHY_DECODE |
2900 L2_FHDR_ERRORS_ALIGNMENT |
2901 L2_FHDR_ERRORS_TOO_SHORT |
2902 L2_FHDR_ERRORS_GIANT_FRAME)) {
2904 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2909 if (status & L2_FHDR_STATUS_SPLIT) {
2910 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2912 } else if (len > bp->rx_jumbo_thresh) {
2913 hdr_len = bp->rx_jumbo_thresh;
2919 if (len <= bp->rx_copy_thresh) {
2920 struct sk_buff *new_skb;
2922 new_skb = netdev_alloc_skb(bp->dev, len + 6);
2923 if (new_skb == NULL) {
2924 bnx2_reuse_rx_skb(bp, rxr, skb, sw_ring_cons,
2930 skb_copy_from_linear_data_offset(skb,
2932 new_skb->data, len + 6);
2933 skb_reserve(new_skb, 6);
2934 skb_put(new_skb, len);
2936 bnx2_reuse_rx_skb(bp, rxr, skb,
2937 sw_ring_cons, sw_ring_prod);
2940 } else if (unlikely(bnx2_rx_skb(bp, rxr, skb, len, hdr_len,
2941 dma_addr, (sw_ring_cons << 16) | sw_ring_prod)))
2944 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
2945 !(bp->rx_mode & BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
2946 vtag = rx_hdr->l2_fhdr_vlan_tag;
2953 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
2956 memmove(ve, skb->data + 4, ETH_ALEN * 2);
2957 ve->h_vlan_proto = htons(ETH_P_8021Q);
2958 ve->h_vlan_TCI = htons(vtag);
2963 skb->protocol = eth_type_trans(skb, bp->dev);
2965 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2966 (ntohs(skb->protocol) != 0x8100)) {
2973 skb->ip_summed = CHECKSUM_NONE;
2975 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2976 L2_FHDR_STATUS_UDP_DATAGRAM))) {
2978 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2979 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2980 skb->ip_summed = CHECKSUM_UNNECESSARY;
2985 vlan_hwaccel_receive_skb(skb, bp->vlgrp, vtag);
2988 netif_receive_skb(skb);
2990 bp->dev->last_rx = jiffies;
2994 sw_cons = NEXT_RX_BD(sw_cons);
2995 sw_prod = NEXT_RX_BD(sw_prod);
2997 if ((rx_pkt == budget))
3000 /* Refresh hw_cons to see if there is new work */
3001 if (sw_cons == hw_cons) {
3002 hw_cons = bnx2_get_hw_rx_cons(bnapi);
3006 rxr->rx_cons = sw_cons;
3007 rxr->rx_prod = sw_prod;
3010 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
3012 REG_WR16(bp, rxr->rx_bidx_addr, sw_prod);
3014 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
3022 /* MSI ISR - The only difference between this and the INTx ISR
3023 * is that the MSI interrupt is always serviced.
3026 bnx2_msi(int irq, void *dev_instance)
3028 struct bnx2_napi *bnapi = dev_instance;
3029 struct bnx2 *bp = bnapi->bp;
3030 struct net_device *dev = bp->dev;
3032 prefetch(bnapi->status_blk.msi);
3033 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3034 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3035 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3037 /* Return here if interrupt is disabled. */
3038 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3041 netif_rx_schedule(dev, &bnapi->napi);
3047 bnx2_msi_1shot(int irq, void *dev_instance)
3049 struct bnx2_napi *bnapi = dev_instance;
3050 struct bnx2 *bp = bnapi->bp;
3051 struct net_device *dev = bp->dev;
3053 prefetch(bnapi->status_blk.msi);
3055 /* Return here if interrupt is disabled. */
3056 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3059 netif_rx_schedule(dev, &bnapi->napi);
3065 bnx2_interrupt(int irq, void *dev_instance)
3067 struct bnx2_napi *bnapi = dev_instance;
3068 struct bnx2 *bp = bnapi->bp;
3069 struct net_device *dev = bp->dev;
3070 struct status_block *sblk = bnapi->status_blk.msi;
3072 /* When using INTx, it is possible for the interrupt to arrive
3073 * at the CPU before the status block posted prior to the
3074 * interrupt. Reading a register will flush the status block.
3075 * When using MSI, the MSI message will always complete after
3076 * the status block write.
3078 if ((sblk->status_idx == bnapi->last_status_idx) &&
3079 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
3080 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
3083 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3084 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
3085 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3087 /* Read back to deassert IRQ immediately to avoid too many
3088 * spurious interrupts.
3090 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
3092 /* Return here if interrupt is shared and is disabled. */
3093 if (unlikely(atomic_read(&bp->intr_sem) != 0))
3096 if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
3097 bnapi->last_status_idx = sblk->status_idx;
3098 __netif_rx_schedule(dev, &bnapi->napi);
3105 bnx2_has_fast_work(struct bnx2_napi *bnapi)
3107 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3108 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3110 if ((bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons) ||
3111 (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons))
3116 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
3117 STATUS_ATTN_BITS_TIMER_ABORT)
3120 bnx2_has_work(struct bnx2_napi *bnapi)
3122 struct status_block *sblk = bnapi->status_blk.msi;
3124 if (bnx2_has_fast_work(bnapi))
3127 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
3128 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
3134 static void bnx2_poll_link(struct bnx2 *bp, struct bnx2_napi *bnapi)
3136 struct status_block *sblk = bnapi->status_blk.msi;
3137 u32 status_attn_bits = sblk->status_attn_bits;
3138 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
3140 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
3141 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
3143 bnx2_phy_int(bp, bnapi);
3145 /* This is needed to take care of transient status
3146 * during link changes.
3148 REG_WR(bp, BNX2_HC_COMMAND,
3149 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3150 REG_RD(bp, BNX2_HC_COMMAND);
3154 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
3155 int work_done, int budget)
3157 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
3158 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
3160 if (bnx2_get_hw_tx_cons(bnapi) != txr->hw_tx_cons)
3161 bnx2_tx_int(bp, bnapi, 0);
3163 if (bnx2_get_hw_rx_cons(bnapi) != rxr->rx_cons)
3164 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
3169 static int bnx2_poll_msix(struct napi_struct *napi, int budget)
3171 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3172 struct bnx2 *bp = bnapi->bp;
3174 struct status_block_msix *sblk = bnapi->status_blk.msix;
3177 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3178 if (unlikely(work_done >= budget))
3181 bnapi->last_status_idx = sblk->status_idx;
3182 /* status idx must be read before checking for more work. */
3184 if (likely(!bnx2_has_fast_work(bnapi))) {
3186 netif_rx_complete(bp->dev, napi);
3187 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, bnapi->int_num |
3188 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3189 bnapi->last_status_idx);
3196 static int bnx2_poll(struct napi_struct *napi, int budget)
3198 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
3199 struct bnx2 *bp = bnapi->bp;
3201 struct status_block *sblk = bnapi->status_blk.msi;
3204 bnx2_poll_link(bp, bnapi);
3206 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
3208 if (unlikely(work_done >= budget))
3211 /* bnapi->last_status_idx is used below to tell the hw how
3212 * much work has been processed, so we must read it before
3213 * checking for more work.
3215 bnapi->last_status_idx = sblk->status_idx;
3217 if (likely(!bnx2_has_work(bnapi))) {
3218 netif_rx_complete(bp->dev, napi);
3219 if (likely(bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)) {
3220 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3221 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3222 bnapi->last_status_idx);
3225 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3226 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3227 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
3228 bnapi->last_status_idx);
3230 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
3231 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
3232 bnapi->last_status_idx);
3240 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
3241 * from set_multicast.
3244 bnx2_set_rx_mode(struct net_device *dev)
3246 struct bnx2 *bp = netdev_priv(dev);
3247 u32 rx_mode, sort_mode;
3248 struct dev_addr_list *uc_ptr;
3251 spin_lock_bh(&bp->phy_lock);
3253 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
3254 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
3255 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
3257 if (!bp->vlgrp && (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN))
3258 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3260 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
3261 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
3263 if (dev->flags & IFF_PROMISC) {
3264 /* Promiscuous mode. */
3265 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3266 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3267 BNX2_RPM_SORT_USER0_PROM_VLAN;
3269 else if (dev->flags & IFF_ALLMULTI) {
3270 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3271 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3274 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
3277 /* Accept one or more multicast(s). */
3278 struct dev_mc_list *mclist;
3279 u32 mc_filter[NUM_MC_HASH_REGISTERS];
3284 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
3286 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3287 i++, mclist = mclist->next) {
3289 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
3291 regidx = (bit & 0xe0) >> 5;
3293 mc_filter[regidx] |= (1 << bit);
3296 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3297 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3301 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
3305 if (dev->uc_count > BNX2_MAX_UNICAST_ADDRESSES) {
3306 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
3307 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
3308 BNX2_RPM_SORT_USER0_PROM_VLAN;
3309 } else if (!(dev->flags & IFF_PROMISC)) {
3310 uc_ptr = dev->uc_list;
3312 /* Add all entries into to the match filter list */
3313 for (i = 0; i < dev->uc_count; i++) {
3314 bnx2_set_mac_addr(bp, uc_ptr->da_addr,
3315 i + BNX2_START_UNICAST_ADDRESS_INDEX);
3317 (i + BNX2_START_UNICAST_ADDRESS_INDEX));
3318 uc_ptr = uc_ptr->next;
3323 if (rx_mode != bp->rx_mode) {
3324 bp->rx_mode = rx_mode;
3325 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
3328 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3329 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3330 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3332 spin_unlock_bh(&bp->phy_lock);
3336 load_rv2p_fw(struct bnx2 *bp, __le32 *rv2p_code, u32 rv2p_code_len,
3342 if (rv2p_proc == RV2P_PROC2 && CHIP_NUM(bp) == CHIP_NUM_5709) {
3343 val = le32_to_cpu(rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC]);
3344 val &= ~XI_RV2P_PROC2_BD_PAGE_SIZE_MSK;
3345 val |= XI_RV2P_PROC2_BD_PAGE_SIZE;
3346 rv2p_code[XI_RV2P_PROC2_MAX_BD_PAGE_LOC] = cpu_to_le32(val);
3349 for (i = 0; i < rv2p_code_len; i += 8) {
3350 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, le32_to_cpu(*rv2p_code));
3352 REG_WR(bp, BNX2_RV2P_INSTR_LOW, le32_to_cpu(*rv2p_code));
3355 if (rv2p_proc == RV2P_PROC1) {
3356 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3357 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3360 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3361 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3365 /* Reset the processor, un-stall is done later. */
3366 if (rv2p_proc == RV2P_PROC1) {
3367 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3370 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3375 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, struct fw_info *fw)
3382 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3383 val |= cpu_reg->mode_value_halt;
3384 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3385 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3387 /* Load the Text area. */
3388 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3392 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3397 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3398 bnx2_reg_wr_ind(bp, offset, le32_to_cpu(fw->text[j]));
3402 /* Load the Data area. */
3403 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3407 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3408 bnx2_reg_wr_ind(bp, offset, fw->data[j]);
3412 /* Load the SBSS area. */
3413 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
3417 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3418 bnx2_reg_wr_ind(bp, offset, 0);
3422 /* Load the BSS area. */
3423 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
3427 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3428 bnx2_reg_wr_ind(bp, offset, 0);
3432 /* Load the Read-Only area. */
3433 offset = cpu_reg->spad_base +
3434 (fw->rodata_addr - cpu_reg->mips_view_base);
3438 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3439 bnx2_reg_wr_ind(bp, offset, fw->rodata[j]);
3443 /* Clear the pre-fetch instruction. */
3444 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0);
3445 bnx2_reg_wr_ind(bp, cpu_reg->pc, fw->start_addr);
3447 /* Start the CPU. */
3448 val = bnx2_reg_rd_ind(bp, cpu_reg->mode);
3449 val &= ~cpu_reg->mode_value_halt;
3450 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear);
3451 bnx2_reg_wr_ind(bp, cpu_reg->mode, val);
3457 bnx2_init_cpus(struct bnx2 *bp)
3463 /* Initialize the RV2P processor. */
3464 text = vmalloc(FW_BUF_SIZE);
3467 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3468 rv2p = bnx2_xi_rv2p_proc1;
3469 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3471 rv2p = bnx2_rv2p_proc1;
3472 rv2p_len = sizeof(bnx2_rv2p_proc1);
3474 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3478 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
3480 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3481 rv2p = bnx2_xi_rv2p_proc2;
3482 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3484 rv2p = bnx2_rv2p_proc2;
3485 rv2p_len = sizeof(bnx2_rv2p_proc2);
3487 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3491 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
3493 /* Initialize the RX Processor. */
3494 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3495 fw = &bnx2_rxp_fw_09;
3497 fw = &bnx2_rxp_fw_06;
3500 rc = load_cpu_fw(bp, &cpu_reg_rxp, fw);
3504 /* Initialize the TX Processor. */
3505 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3506 fw = &bnx2_txp_fw_09;
3508 fw = &bnx2_txp_fw_06;
3511 rc = load_cpu_fw(bp, &cpu_reg_txp, fw);
3515 /* Initialize the TX Patch-up Processor. */
3516 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3517 fw = &bnx2_tpat_fw_09;
3519 fw = &bnx2_tpat_fw_06;
3522 rc = load_cpu_fw(bp, &cpu_reg_tpat, fw);
3526 /* Initialize the Completion Processor. */
3527 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3528 fw = &bnx2_com_fw_09;
3530 fw = &bnx2_com_fw_06;
3533 rc = load_cpu_fw(bp, &cpu_reg_com, fw);
3537 /* Initialize the Command Processor. */
3538 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3539 fw = &bnx2_cp_fw_09;
3541 fw = &bnx2_cp_fw_06;
3544 rc = load_cpu_fw(bp, &cpu_reg_cp, fw);
3552 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3556 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3562 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3563 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3564 PCI_PM_CTRL_PME_STATUS);
3566 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3567 /* delay required during transition out of D3hot */
3570 val = REG_RD(bp, BNX2_EMAC_MODE);
3571 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3572 val &= ~BNX2_EMAC_MODE_MPKT;
3573 REG_WR(bp, BNX2_EMAC_MODE, val);
3575 val = REG_RD(bp, BNX2_RPM_CONFIG);
3576 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3577 REG_WR(bp, BNX2_RPM_CONFIG, val);
3588 autoneg = bp->autoneg;
3589 advertising = bp->advertising;
3591 if (bp->phy_port == PORT_TP) {
3592 bp->autoneg = AUTONEG_SPEED;
3593 bp->advertising = ADVERTISED_10baseT_Half |
3594 ADVERTISED_10baseT_Full |
3595 ADVERTISED_100baseT_Half |
3596 ADVERTISED_100baseT_Full |
3600 spin_lock_bh(&bp->phy_lock);
3601 bnx2_setup_phy(bp, bp->phy_port);
3602 spin_unlock_bh(&bp->phy_lock);
3604 bp->autoneg = autoneg;
3605 bp->advertising = advertising;
3607 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
3609 val = REG_RD(bp, BNX2_EMAC_MODE);
3611 /* Enable port mode. */
3612 val &= ~BNX2_EMAC_MODE_PORT;
3613 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3614 BNX2_EMAC_MODE_ACPI_RCVD |
3615 BNX2_EMAC_MODE_MPKT;
3616 if (bp->phy_port == PORT_TP)
3617 val |= BNX2_EMAC_MODE_PORT_MII;
3619 val |= BNX2_EMAC_MODE_PORT_GMII;
3620 if (bp->line_speed == SPEED_2500)
3621 val |= BNX2_EMAC_MODE_25G_MODE;
3624 REG_WR(bp, BNX2_EMAC_MODE, val);
3626 /* receive all multicast */
3627 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3628 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3631 REG_WR(bp, BNX2_EMAC_RX_MODE,
3632 BNX2_EMAC_RX_MODE_SORT_MODE);
3634 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3635 BNX2_RPM_SORT_USER0_MC_EN;
3636 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3637 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3638 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3639 BNX2_RPM_SORT_USER0_ENA);
3641 /* Need to enable EMAC and RPM for WOL. */
3642 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3643 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3644 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3645 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3647 val = REG_RD(bp, BNX2_RPM_CONFIG);
3648 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3649 REG_WR(bp, BNX2_RPM_CONFIG, val);
3651 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3654 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3657 if (!(bp->flags & BNX2_FLAG_NO_WOL))
3658 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg,
3661 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3662 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3663 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3672 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3674 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3677 /* No more memory access after this point until
3678 * device is brought back to D0.
3690 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3695 /* Request access to the flash interface. */
3696 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3697 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3698 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3699 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3705 if (j >= NVRAM_TIMEOUT_COUNT)
3712 bnx2_release_nvram_lock(struct bnx2 *bp)
3717 /* Relinquish nvram interface. */
3718 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3720 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3721 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3722 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3728 if (j >= NVRAM_TIMEOUT_COUNT)
3736 bnx2_enable_nvram_write(struct bnx2 *bp)
3740 val = REG_RD(bp, BNX2_MISC_CFG);
3741 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3743 if (bp->flash_info->flags & BNX2_NV_WREN) {
3746 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3747 REG_WR(bp, BNX2_NVM_COMMAND,
3748 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3750 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3753 val = REG_RD(bp, BNX2_NVM_COMMAND);
3754 if (val & BNX2_NVM_COMMAND_DONE)
3758 if (j >= NVRAM_TIMEOUT_COUNT)
3765 bnx2_disable_nvram_write(struct bnx2 *bp)
3769 val = REG_RD(bp, BNX2_MISC_CFG);
3770 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3775 bnx2_enable_nvram_access(struct bnx2 *bp)
3779 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3780 /* Enable both bits, even on read. */
3781 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3782 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3786 bnx2_disable_nvram_access(struct bnx2 *bp)
3790 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3791 /* Disable both bits, even after read. */
3792 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3793 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3794 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3798 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3803 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3804 /* Buffered flash, no erase needed */
3807 /* Build an erase command */
3808 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3809 BNX2_NVM_COMMAND_DOIT;
3811 /* Need to clear DONE bit separately. */
3812 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3814 /* Address of the NVRAM to read from. */
3815 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3817 /* Issue an erase command. */
3818 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3820 /* Wait for completion. */
3821 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3826 val = REG_RD(bp, BNX2_NVM_COMMAND);
3827 if (val & BNX2_NVM_COMMAND_DONE)
3831 if (j >= NVRAM_TIMEOUT_COUNT)
3838 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3843 /* Build the command word. */
3844 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3846 /* Calculate an offset of a buffered flash, not needed for 5709. */
3847 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3848 offset = ((offset / bp->flash_info->page_size) <<
3849 bp->flash_info->page_bits) +
3850 (offset % bp->flash_info->page_size);
3853 /* Need to clear DONE bit separately. */
3854 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3856 /* Address of the NVRAM to read from. */
3857 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3859 /* Issue a read command. */
3860 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3862 /* Wait for completion. */
3863 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3868 val = REG_RD(bp, BNX2_NVM_COMMAND);
3869 if (val & BNX2_NVM_COMMAND_DONE) {
3870 __be32 v = cpu_to_be32(REG_RD(bp, BNX2_NVM_READ));
3871 memcpy(ret_val, &v, 4);
3875 if (j >= NVRAM_TIMEOUT_COUNT)
3883 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3889 /* Build the command word. */
3890 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3892 /* Calculate an offset of a buffered flash, not needed for 5709. */
3893 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3894 offset = ((offset / bp->flash_info->page_size) <<
3895 bp->flash_info->page_bits) +
3896 (offset % bp->flash_info->page_size);
3899 /* Need to clear DONE bit separately. */
3900 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3902 memcpy(&val32, val, 4);
3904 /* Write the data. */
3905 REG_WR(bp, BNX2_NVM_WRITE, be32_to_cpu(val32));
3907 /* Address of the NVRAM to write to. */
3908 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3910 /* Issue the write command. */
3911 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3913 /* Wait for completion. */
3914 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3917 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3920 if (j >= NVRAM_TIMEOUT_COUNT)
3927 bnx2_init_nvram(struct bnx2 *bp)
3930 int j, entry_count, rc = 0;
3931 struct flash_spec *flash;
3933 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3934 bp->flash_info = &flash_5709;
3935 goto get_flash_size;
3938 /* Determine the selected interface. */
3939 val = REG_RD(bp, BNX2_NVM_CFG1);
3941 entry_count = ARRAY_SIZE(flash_table);
3943 if (val & 0x40000000) {
3945 /* Flash interface has been reconfigured */
3946 for (j = 0, flash = &flash_table[0]; j < entry_count;
3948 if ((val & FLASH_BACKUP_STRAP_MASK) ==
3949 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3950 bp->flash_info = flash;
3957 /* Not yet been reconfigured */
3959 if (val & (1 << 23))
3960 mask = FLASH_BACKUP_STRAP_MASK;
3962 mask = FLASH_STRAP_MASK;
3964 for (j = 0, flash = &flash_table[0]; j < entry_count;
3967 if ((val & mask) == (flash->strapping & mask)) {
3968 bp->flash_info = flash;
3970 /* Request access to the flash interface. */
3971 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3974 /* Enable access to flash interface */
3975 bnx2_enable_nvram_access(bp);
3977 /* Reconfigure the flash interface */
3978 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3979 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3980 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3981 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3983 /* Disable access to flash interface */
3984 bnx2_disable_nvram_access(bp);
3985 bnx2_release_nvram_lock(bp);
3990 } /* if (val & 0x40000000) */
3992 if (j == entry_count) {
3993 bp->flash_info = NULL;
3994 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
3999 val = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG2);
4000 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
4002 bp->flash_size = val;
4004 bp->flash_size = bp->flash_info->total_size;
4010 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
4014 u32 cmd_flags, offset32, len32, extra;
4019 /* Request access to the flash interface. */
4020 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4023 /* Enable access to flash interface */
4024 bnx2_enable_nvram_access(bp);
4037 pre_len = 4 - (offset & 3);
4039 if (pre_len >= len32) {
4041 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4042 BNX2_NVM_COMMAND_LAST;
4045 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4048 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4053 memcpy(ret_buf, buf + (offset & 3), pre_len);
4060 extra = 4 - (len32 & 3);
4061 len32 = (len32 + 4) & ~3;
4068 cmd_flags = BNX2_NVM_COMMAND_LAST;
4070 cmd_flags = BNX2_NVM_COMMAND_FIRST |
4071 BNX2_NVM_COMMAND_LAST;
4073 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4075 memcpy(ret_buf, buf, 4 - extra);
4077 else if (len32 > 0) {
4080 /* Read the first word. */
4084 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4086 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
4088 /* Advance to the next dword. */
4093 while (len32 > 4 && rc == 0) {
4094 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
4096 /* Advance to the next dword. */
4105 cmd_flags = BNX2_NVM_COMMAND_LAST;
4106 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
4108 memcpy(ret_buf, buf, 4 - extra);
4111 /* Disable access to flash interface */
4112 bnx2_disable_nvram_access(bp);
4114 bnx2_release_nvram_lock(bp);
4120 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
4123 u32 written, offset32, len32;
4124 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
4126 int align_start, align_end;
4131 align_start = align_end = 0;
4133 if ((align_start = (offset32 & 3))) {
4135 len32 += align_start;
4138 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
4143 align_end = 4 - (len32 & 3);
4145 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
4149 if (align_start || align_end) {
4150 align_buf = kmalloc(len32, GFP_KERNEL);
4151 if (align_buf == NULL)
4154 memcpy(align_buf, start, 4);
4157 memcpy(align_buf + len32 - 4, end, 4);
4159 memcpy(align_buf + align_start, data_buf, buf_size);
4163 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4164 flash_buffer = kmalloc(264, GFP_KERNEL);
4165 if (flash_buffer == NULL) {
4167 goto nvram_write_end;
4172 while ((written < len32) && (rc == 0)) {
4173 u32 page_start, page_end, data_start, data_end;
4174 u32 addr, cmd_flags;
4177 /* Find the page_start addr */
4178 page_start = offset32 + written;
4179 page_start -= (page_start % bp->flash_info->page_size);
4180 /* Find the page_end addr */
4181 page_end = page_start + bp->flash_info->page_size;
4182 /* Find the data_start addr */
4183 data_start = (written == 0) ? offset32 : page_start;
4184 /* Find the data_end addr */
4185 data_end = (page_end > offset32 + len32) ?
4186 (offset32 + len32) : page_end;
4188 /* Request access to the flash interface. */
4189 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
4190 goto nvram_write_end;
4192 /* Enable access to flash interface */
4193 bnx2_enable_nvram_access(bp);
4195 cmd_flags = BNX2_NVM_COMMAND_FIRST;
4196 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4199 /* Read the whole page into the buffer
4200 * (non-buffer flash only) */
4201 for (j = 0; j < bp->flash_info->page_size; j += 4) {
4202 if (j == (bp->flash_info->page_size - 4)) {
4203 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4205 rc = bnx2_nvram_read_dword(bp,
4211 goto nvram_write_end;
4217 /* Enable writes to flash interface (unlock write-protect) */
4218 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
4219 goto nvram_write_end;
4221 /* Loop to write back the buffer data from page_start to
4224 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4225 /* Erase the page */
4226 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
4227 goto nvram_write_end;
4229 /* Re-enable the write again for the actual write */
4230 bnx2_enable_nvram_write(bp);
4232 for (addr = page_start; addr < data_start;
4233 addr += 4, i += 4) {
4235 rc = bnx2_nvram_write_dword(bp, addr,
4236 &flash_buffer[i], cmd_flags);
4239 goto nvram_write_end;
4245 /* Loop to write the new data from data_start to data_end */
4246 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
4247 if ((addr == page_end - 4) ||
4248 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
4249 (addr == data_end - 4))) {
4251 cmd_flags |= BNX2_NVM_COMMAND_LAST;
4253 rc = bnx2_nvram_write_dword(bp, addr, buf,
4257 goto nvram_write_end;
4263 /* Loop to write back the buffer data from data_end
4265 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
4266 for (addr = data_end; addr < page_end;
4267 addr += 4, i += 4) {
4269 if (addr == page_end-4) {
4270 cmd_flags = BNX2_NVM_COMMAND_LAST;
4272 rc = bnx2_nvram_write_dword(bp, addr,
4273 &flash_buffer[i], cmd_flags);
4276 goto nvram_write_end;
4282 /* Disable writes to flash interface (lock write-protect) */
4283 bnx2_disable_nvram_write(bp);
4285 /* Disable access to flash interface */
4286 bnx2_disable_nvram_access(bp);
4287 bnx2_release_nvram_lock(bp);
4289 /* Increment written */
4290 written += data_end - data_start;
4294 kfree(flash_buffer);
4300 bnx2_init_fw_cap(struct bnx2 *bp)
4304 bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4305 bp->flags &= ~BNX2_FLAG_CAN_KEEP_VLAN;
4307 if (!(bp->flags & BNX2_FLAG_ASF_ENABLE))
4308 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4310 val = bnx2_shmem_rd(bp, BNX2_FW_CAP_MB);
4311 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4314 if ((val & BNX2_FW_CAP_CAN_KEEP_VLAN) == BNX2_FW_CAP_CAN_KEEP_VLAN) {
4315 bp->flags |= BNX2_FLAG_CAN_KEEP_VLAN;
4316 sig |= BNX2_DRV_ACK_CAP_SIGNATURE | BNX2_FW_CAP_CAN_KEEP_VLAN;
4319 if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) &&
4320 (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE)) {
4323 bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP;
4325 link = bnx2_shmem_rd(bp, BNX2_LINK_STATUS);
4326 if (link & BNX2_LINK_STATUS_SERDES_LINK)
4327 bp->phy_port = PORT_FIBRE;
4329 bp->phy_port = PORT_TP;
4331 sig |= BNX2_DRV_ACK_CAP_SIGNATURE |
4332 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4335 if (netif_running(bp->dev) && sig)
4336 bnx2_shmem_wr(bp, BNX2_DRV_ACK_CAP_MB, sig);
4340 bnx2_setup_msix_tbl(struct bnx2 *bp)
4342 REG_WR(bp, BNX2_PCI_GRC_WINDOW_ADDR, BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN);
4344 REG_WR(bp, BNX2_PCI_GRC_WINDOW2_ADDR, BNX2_MSIX_TABLE_ADDR);
4345 REG_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
4349 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4355 /* Wait for the current PCI transaction to complete before
4356 * issuing a reset. */
4357 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4358 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4359 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4360 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4361 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4362 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4365 /* Wait for the firmware to tell us it is ok to issue a reset. */
4366 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
4368 /* Deposit a driver reset signature so the firmware knows that
4369 * this is a soft reset. */
4370 bnx2_shmem_wr(bp, BNX2_DRV_RESET_SIGNATURE,
4371 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4373 /* Do a dummy read to force the chip to complete all current transaction
4374 * before we issue a reset. */
4375 val = REG_RD(bp, BNX2_MISC_ID);
4377 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4378 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4379 REG_RD(bp, BNX2_MISC_COMMAND);
4382 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4383 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4385 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4388 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4389 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4390 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4393 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4395 /* Reading back any register after chip reset will hang the
4396 * bus on 5706 A0 and A1. The msleep below provides plenty
4397 * of margin for write posting.
4399 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4400 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4403 /* Reset takes approximate 30 usec */
4404 for (i = 0; i < 10; i++) {
4405 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4406 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4407 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4412 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4413 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4414 printk(KERN_ERR PFX "Chip reset did not complete\n");
4419 /* Make sure byte swapping is properly configured. */
4420 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4421 if (val != 0x01020304) {
4422 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4426 /* Wait for the firmware to finish its initialization. */
4427 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 1, 0);
4431 spin_lock_bh(&bp->phy_lock);
4432 old_port = bp->phy_port;
4433 bnx2_init_fw_cap(bp);
4434 if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) &&
4435 old_port != bp->phy_port)
4436 bnx2_set_default_remote_link(bp);
4437 spin_unlock_bh(&bp->phy_lock);
4439 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4440 /* Adjust the voltage regular to two steps lower. The default
4441 * of this register is 0x0000000e. */
4442 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4444 /* Remove bad rbuf memory from the free pool. */
4445 rc = bnx2_alloc_bad_rbuf(bp);
4448 if (bp->flags & BNX2_FLAG_USING_MSIX)
4449 bnx2_setup_msix_tbl(bp);
4455 bnx2_init_chip(struct bnx2 *bp)
4460 /* Make sure the interrupt is not active. */
4461 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4463 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4464 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4466 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4468 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4469 DMA_READ_CHANS << 12 |
4470 DMA_WRITE_CHANS << 16;
4472 val |= (0x2 << 20) | (1 << 11);
4474 if ((bp->flags & BNX2_FLAG_PCIX) && (bp->bus_speed_mhz == 133))
4477 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4478 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & BNX2_FLAG_PCIX))
4479 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4481 REG_WR(bp, BNX2_DMA_CONFIG, val);
4483 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4484 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4485 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4486 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4489 if (bp->flags & BNX2_FLAG_PCIX) {
4492 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4494 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4495 val16 & ~PCI_X_CMD_ERO);
4498 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4499 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4500 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4501 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4503 /* Initialize context mapping and zero out the quick contexts. The
4504 * context block must have already been enabled. */
4505 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4506 rc = bnx2_init_5709_context(bp);
4510 bnx2_init_context(bp);
4512 if ((rc = bnx2_init_cpus(bp)) != 0)
4515 bnx2_init_nvram(bp);
4517 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
4519 val = REG_RD(bp, BNX2_MQ_CONFIG);
4520 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4521 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4522 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4523 val |= BNX2_MQ_CONFIG_HALT_DIS;
4525 REG_WR(bp, BNX2_MQ_CONFIG, val);
4527 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4528 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4529 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4531 val = (BCM_PAGE_BITS - 8) << 24;
4532 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4534 /* Configure page size. */
4535 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4536 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4537 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4538 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4540 val = bp->mac_addr[0] +
4541 (bp->mac_addr[1] << 8) +
4542 (bp->mac_addr[2] << 16) +
4544 (bp->mac_addr[4] << 8) +
4545 (bp->mac_addr[5] << 16);
4546 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4548 /* Program the MTU. Also include 4 bytes for CRC32. */
4549 val = bp->dev->mtu + ETH_HLEN + 4;
4550 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4551 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4552 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4554 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
4555 bp->bnx2_napi[i].last_status_idx = 0;
4557 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4559 /* Set up how to generate a link change interrupt. */
4560 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4562 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4563 (u64) bp->status_blk_mapping & 0xffffffff);
4564 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4566 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4567 (u64) bp->stats_blk_mapping & 0xffffffff);
4568 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4569 (u64) bp->stats_blk_mapping >> 32);
4571 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4572 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4574 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4575 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4577 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4578 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4580 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4582 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4584 REG_WR(bp, BNX2_HC_COM_TICKS,
4585 (bp->com_ticks_int << 16) | bp->com_ticks);
4587 REG_WR(bp, BNX2_HC_CMD_TICKS,
4588 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4590 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4591 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4593 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4594 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4596 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4597 val = BNX2_HC_CONFIG_COLLECT_STATS;
4599 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4600 BNX2_HC_CONFIG_COLLECT_STATS;
4603 if (bp->irq_nvecs > 1) {
4604 REG_WR(bp, BNX2_HC_MSIX_BIT_VECTOR,
4605 BNX2_HC_MSIX_BIT_VECTOR_VAL);
4607 val |= BNX2_HC_CONFIG_SB_ADDR_INC_128B;
4610 if (bp->flags & BNX2_FLAG_ONE_SHOT_MSI)
4611 val |= BNX2_HC_CONFIG_ONE_SHOT;
4613 REG_WR(bp, BNX2_HC_CONFIG, val);
4615 for (i = 1; i < bp->irq_nvecs; i++) {
4616 u32 base = ((i - 1) * BNX2_HC_SB_CONFIG_SIZE) +
4617 BNX2_HC_SB_CONFIG_1;
4620 BNX2_HC_SB_CONFIG_1_TX_TMR_MODE |
4621 BNX2_HC_SB_CONFIG_1_RX_TMR_MODE |
4622 BNX2_HC_SB_CONFIG_1_ONE_SHOT);
4624 REG_WR(bp, base + BNX2_HC_TX_QUICK_CONS_TRIP_OFF,
4625 (bp->tx_quick_cons_trip_int << 16) |
4626 bp->tx_quick_cons_trip);
4628 REG_WR(bp, base + BNX2_HC_TX_TICKS_OFF,
4629 (bp->tx_ticks_int << 16) | bp->tx_ticks);
4631 REG_WR(bp, base + BNX2_HC_RX_QUICK_CONS_TRIP_OFF,
4632 (bp->rx_quick_cons_trip_int << 16) |
4633 bp->rx_quick_cons_trip);
4635 REG_WR(bp, base + BNX2_HC_RX_TICKS_OFF,
4636 (bp->rx_ticks_int << 16) | bp->rx_ticks);
4639 /* Clear internal stats counters. */
4640 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4642 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4644 /* Initialize the receive filter. */
4645 bnx2_set_rx_mode(bp->dev);
4647 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4648 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4649 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4650 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4652 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4655 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4656 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4660 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4666 bnx2_clear_ring_states(struct bnx2 *bp)
4668 struct bnx2_napi *bnapi;
4669 struct bnx2_tx_ring_info *txr;
4670 struct bnx2_rx_ring_info *rxr;
4673 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
4674 bnapi = &bp->bnx2_napi[i];
4675 txr = &bnapi->tx_ring;
4676 rxr = &bnapi->rx_ring;
4679 txr->hw_tx_cons = 0;
4680 rxr->rx_prod_bseq = 0;
4683 rxr->rx_pg_prod = 0;
4684 rxr->rx_pg_cons = 0;
4689 bnx2_init_tx_context(struct bnx2 *bp, u32 cid, struct bnx2_tx_ring_info *txr)
4691 u32 val, offset0, offset1, offset2, offset3;
4692 u32 cid_addr = GET_CID_ADDR(cid);
4694 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4695 offset0 = BNX2_L2CTX_TYPE_XI;
4696 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4697 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4698 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4700 offset0 = BNX2_L2CTX_TYPE;
4701 offset1 = BNX2_L2CTX_CMD_TYPE;
4702 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4703 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4705 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4706 bnx2_ctx_wr(bp, cid_addr, offset0, val);
4708 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4709 bnx2_ctx_wr(bp, cid_addr, offset1, val);
4711 val = (u64) txr->tx_desc_mapping >> 32;
4712 bnx2_ctx_wr(bp, cid_addr, offset2, val);
4714 val = (u64) txr->tx_desc_mapping & 0xffffffff;
4715 bnx2_ctx_wr(bp, cid_addr, offset3, val);
4719 bnx2_init_tx_ring(struct bnx2 *bp, int ring_num)
4723 struct bnx2_napi *bnapi;
4724 struct bnx2_tx_ring_info *txr;
4726 bnapi = &bp->bnx2_napi[ring_num];
4727 txr = &bnapi->tx_ring;
4732 cid = TX_TSS_CID + ring_num - 1;
4734 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4736 txbd = &txr->tx_desc_ring[MAX_TX_DESC_CNT];
4738 txbd->tx_bd_haddr_hi = (u64) txr->tx_desc_mapping >> 32;
4739 txbd->tx_bd_haddr_lo = (u64) txr->tx_desc_mapping & 0xffffffff;
4742 txr->tx_prod_bseq = 0;
4744 txr->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4745 txr->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4747 bnx2_init_tx_context(bp, cid, txr);
4751 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4757 for (i = 0; i < num_rings; i++) {
4760 rxbd = &rx_ring[i][0];
4761 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4762 rxbd->rx_bd_len = buf_size;
4763 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4765 if (i == (num_rings - 1))
4769 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4770 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4775 bnx2_init_rx_ring(struct bnx2 *bp, int ring_num)
4778 u16 prod, ring_prod;
4779 u32 cid, rx_cid_addr, val;
4780 struct bnx2_napi *bnapi = &bp->bnx2_napi[ring_num];
4781 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
4786 cid = RX_RSS_CID + ring_num - 1;
4788 rx_cid_addr = GET_CID_ADDR(cid);
4790 bnx2_init_rxbd_rings(rxr->rx_desc_ring, rxr->rx_desc_mapping,
4791 bp->rx_buf_use_size, bp->rx_max_ring);
4793 bnx2_init_rx_context(bp, cid);
4795 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4796 val = REG_RD(bp, BNX2_MQ_MAP_L2_5);
4797 REG_WR(bp, BNX2_MQ_MAP_L2_5, val | BNX2_MQ_MAP_L2_5_ARM);
4800 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4801 if (bp->rx_pg_ring_size) {
4802 bnx2_init_rxbd_rings(rxr->rx_pg_desc_ring,
4803 rxr->rx_pg_desc_mapping,
4804 PAGE_SIZE, bp->rx_max_pg_ring);
4805 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4806 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4807 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4808 BNX2_L2CTX_RBDC_JUMBO_KEY - ring_num);
4810 val = (u64) rxr->rx_pg_desc_mapping[0] >> 32;
4811 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4813 val = (u64) rxr->rx_pg_desc_mapping[0] & 0xffffffff;
4814 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4816 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4817 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4820 val = (u64) rxr->rx_desc_mapping[0] >> 32;
4821 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4823 val = (u64) rxr->rx_desc_mapping[0] & 0xffffffff;
4824 bnx2_ctx_wr(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4826 ring_prod = prod = rxr->rx_pg_prod;
4827 for (i = 0; i < bp->rx_pg_ring_size; i++) {
4828 if (bnx2_alloc_rx_page(bp, rxr, ring_prod) < 0)
4830 prod = NEXT_RX_BD(prod);
4831 ring_prod = RX_PG_RING_IDX(prod);
4833 rxr->rx_pg_prod = prod;
4835 ring_prod = prod = rxr->rx_prod;
4836 for (i = 0; i < bp->rx_ring_size; i++) {
4837 if (bnx2_alloc_rx_skb(bp, rxr, ring_prod) < 0)
4839 prod = NEXT_RX_BD(prod);
4840 ring_prod = RX_RING_IDX(prod);
4842 rxr->rx_prod = prod;
4844 rxr->rx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BDIDX;
4845 rxr->rx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_BSEQ;
4846 rxr->rx_pg_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_HOST_PG_BDIDX;
4848 REG_WR16(bp, rxr->rx_pg_bidx_addr, rxr->rx_pg_prod);
4849 REG_WR16(bp, rxr->rx_bidx_addr, prod);
4851 REG_WR(bp, rxr->rx_bseq_addr, rxr->rx_prod_bseq);
4855 bnx2_init_all_rings(struct bnx2 *bp)
4860 bnx2_clear_ring_states(bp);
4862 REG_WR(bp, BNX2_TSCH_TSS_CFG, 0);
4863 for (i = 0; i < bp->num_tx_rings; i++)
4864 bnx2_init_tx_ring(bp, i);
4866 if (bp->num_tx_rings > 1)
4867 REG_WR(bp, BNX2_TSCH_TSS_CFG, ((bp->num_tx_rings - 1) << 24) |
4870 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, 0);
4871 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ, 0);
4873 for (i = 0; i < bp->num_rx_rings; i++)
4874 bnx2_init_rx_ring(bp, i);
4876 if (bp->num_rx_rings > 1) {
4878 u8 *tbl = (u8 *) &tbl_32;
4880 bnx2_reg_wr_ind(bp, BNX2_RXP_SCRATCH_RSS_TBL_SZ,
4881 BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES);
4883 for (i = 0; i < BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES; i++) {
4884 tbl[i % 4] = i % (bp->num_rx_rings - 1);
4887 BNX2_RXP_SCRATCH_RSS_TBL + i,
4888 cpu_to_be32(tbl_32));
4891 val = BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI |
4892 BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI;
4894 REG_WR(bp, BNX2_RLUP_RSS_CONFIG, val);
4899 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
4901 u32 max, num_rings = 1;
4903 while (ring_size > MAX_RX_DESC_CNT) {
4904 ring_size -= MAX_RX_DESC_CNT;
4907 /* round to next power of 2 */
4909 while ((max & num_rings) == 0)
4912 if (num_rings != max)
4919 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4921 u32 rx_size, rx_space, jumbo_size;
4923 /* 8 for CRC and VLAN */
4924 rx_size = bp->dev->mtu + ETH_HLEN + BNX2_RX_OFFSET + 8;
4926 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4927 sizeof(struct skb_shared_info);
4929 bp->rx_copy_thresh = BNX2_RX_COPY_THRESH;
4930 bp->rx_pg_ring_size = 0;
4931 bp->rx_max_pg_ring = 0;
4932 bp->rx_max_pg_ring_idx = 0;
4933 if ((rx_space > PAGE_SIZE) && !(bp->flags & BNX2_FLAG_JUMBO_BROKEN)) {
4934 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4936 jumbo_size = size * pages;
4937 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4938 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4940 bp->rx_pg_ring_size = jumbo_size;
4941 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4943 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4944 rx_size = BNX2_RX_COPY_THRESH + BNX2_RX_OFFSET;
4945 bp->rx_copy_thresh = 0;
4948 bp->rx_buf_use_size = rx_size;
4950 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4951 bp->rx_jumbo_thresh = rx_size - BNX2_RX_OFFSET;
4952 bp->rx_ring_size = size;
4953 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
4954 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4958 bnx2_free_tx_skbs(struct bnx2 *bp)
4962 for (i = 0; i < bp->num_tx_rings; i++) {
4963 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
4964 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
4967 if (txr->tx_buf_ring == NULL)
4970 for (j = 0; j < TX_DESC_CNT; ) {
4971 struct sw_bd *tx_buf = &txr->tx_buf_ring[j];
4972 struct sk_buff *skb = tx_buf->skb;
4980 pci_unmap_single(bp->pdev,
4981 pci_unmap_addr(tx_buf, mapping),
4982 skb_headlen(skb), PCI_DMA_TODEVICE);
4986 last = skb_shinfo(skb)->nr_frags;
4987 for (k = 0; k < last; k++) {
4988 tx_buf = &txr->tx_buf_ring[j + k + 1];
4989 pci_unmap_page(bp->pdev,
4990 pci_unmap_addr(tx_buf, mapping),
4991 skb_shinfo(skb)->frags[j].size,
5001 bnx2_free_rx_skbs(struct bnx2 *bp)
5005 for (i = 0; i < bp->num_rx_rings; i++) {
5006 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
5007 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5010 if (rxr->rx_buf_ring == NULL)
5013 for (j = 0; j < bp->rx_max_ring_idx; j++) {
5014 struct sw_bd *rx_buf = &rxr->rx_buf_ring[j];
5015 struct sk_buff *skb = rx_buf->skb;
5020 pci_unmap_single(bp->pdev,
5021 pci_unmap_addr(rx_buf, mapping),
5022 bp->rx_buf_use_size,
5023 PCI_DMA_FROMDEVICE);
5029 for (j = 0; j < bp->rx_max_pg_ring_idx; j++)
5030 bnx2_free_rx_page(bp, rxr, j);
5035 bnx2_free_skbs(struct bnx2 *bp)
5037 bnx2_free_tx_skbs(bp);
5038 bnx2_free_rx_skbs(bp);
5042 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
5046 rc = bnx2_reset_chip(bp, reset_code);
5051 if ((rc = bnx2_init_chip(bp)) != 0)
5054 bnx2_init_all_rings(bp);
5059 bnx2_init_nic(struct bnx2 *bp, int reset_phy)
5063 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
5066 spin_lock_bh(&bp->phy_lock);
5067 bnx2_init_phy(bp, reset_phy);
5069 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5070 bnx2_remote_phy_event(bp);
5071 spin_unlock_bh(&bp->phy_lock);
5076 bnx2_shutdown_chip(struct bnx2 *bp)
5080 if (bp->flags & BNX2_FLAG_NO_WOL)
5081 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5083 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5085 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5087 return bnx2_reset_chip(bp, reset_code);
5091 bnx2_test_registers(struct bnx2 *bp)
5095 static const struct {
5098 #define BNX2_FL_NOT_5709 1
5102 { 0x006c, 0, 0x00000000, 0x0000003f },
5103 { 0x0090, 0, 0xffffffff, 0x00000000 },
5104 { 0x0094, 0, 0x00000000, 0x00000000 },
5106 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
5107 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5108 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5109 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
5110 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
5111 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5112 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
5113 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5114 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5116 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5117 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
5118 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5119 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5120 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5121 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
5123 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
5124 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
5125 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
5127 { 0x1000, 0, 0x00000000, 0x00000001 },
5128 { 0x1004, BNX2_FL_NOT_5709, 0x00000000, 0x000f0001 },
5130 { 0x1408, 0, 0x01c00800, 0x00000000 },
5131 { 0x149c, 0, 0x8000ffff, 0x00000000 },
5132 { 0x14a8, 0, 0x00000000, 0x000001ff },
5133 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
5134 { 0x14b0, 0, 0x00000002, 0x00000001 },
5135 { 0x14b8, 0, 0x00000000, 0x00000000 },
5136 { 0x14c0, 0, 0x00000000, 0x00000009 },
5137 { 0x14c4, 0, 0x00003fff, 0x00000000 },
5138 { 0x14cc, 0, 0x00000000, 0x00000001 },
5139 { 0x14d0, 0, 0xffffffff, 0x00000000 },
5141 { 0x1800, 0, 0x00000000, 0x00000001 },
5142 { 0x1804, 0, 0x00000000, 0x00000003 },
5144 { 0x2800, 0, 0x00000000, 0x00000001 },
5145 { 0x2804, 0, 0x00000000, 0x00003f01 },
5146 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
5147 { 0x2810, 0, 0xffff0000, 0x00000000 },
5148 { 0x2814, 0, 0xffff0000, 0x00000000 },
5149 { 0x2818, 0, 0xffff0000, 0x00000000 },
5150 { 0x281c, 0, 0xffff0000, 0x00000000 },
5151 { 0x2834, 0, 0xffffffff, 0x00000000 },
5152 { 0x2840, 0, 0x00000000, 0xffffffff },
5153 { 0x2844, 0, 0x00000000, 0xffffffff },
5154 { 0x2848, 0, 0xffffffff, 0x00000000 },
5155 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
5157 { 0x2c00, 0, 0x00000000, 0x00000011 },
5158 { 0x2c04, 0, 0x00000000, 0x00030007 },
5160 { 0x3c00, 0, 0x00000000, 0x00000001 },
5161 { 0x3c04, 0, 0x00000000, 0x00070000 },
5162 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
5163 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
5164 { 0x3c10, 0, 0xffffffff, 0x00000000 },
5165 { 0x3c14, 0, 0x00000000, 0xffffffff },
5166 { 0x3c18, 0, 0x00000000, 0xffffffff },
5167 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
5168 { 0x3c20, 0, 0xffffff00, 0x00000000 },
5170 { 0x5004, 0, 0x00000000, 0x0000007f },
5171 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
5173 { 0x5c00, 0, 0x00000000, 0x00000001 },
5174 { 0x5c04, 0, 0x00000000, 0x0003000f },
5175 { 0x5c08, 0, 0x00000003, 0x00000000 },
5176 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
5177 { 0x5c10, 0, 0x00000000, 0xffffffff },
5178 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
5179 { 0x5c84, 0, 0x00000000, 0x0000f333 },
5180 { 0x5c88, 0, 0x00000000, 0x00077373 },
5181 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
5183 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
5184 { 0x680c, 0, 0xffffffff, 0x00000000 },
5185 { 0x6810, 0, 0xffffffff, 0x00000000 },
5186 { 0x6814, 0, 0xffffffff, 0x00000000 },
5187 { 0x6818, 0, 0xffffffff, 0x00000000 },
5188 { 0x681c, 0, 0xffffffff, 0x00000000 },
5189 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
5190 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
5191 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
5192 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
5193 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
5194 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
5195 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
5196 { 0x683c, 0, 0x0000ffff, 0x00000000 },
5197 { 0x6840, 0, 0x00000ff0, 0x00000000 },
5198 { 0x6844, 0, 0x00ffff00, 0x00000000 },
5199 { 0x684c, 0, 0xffffffff, 0x00000000 },
5200 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
5201 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
5202 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
5203 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
5204 { 0x6908, 0, 0x00000000, 0x0001ff0f },
5205 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
5207 { 0xffff, 0, 0x00000000, 0x00000000 },
5212 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5215 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
5216 u32 offset, rw_mask, ro_mask, save_val, val;
5217 u16 flags = reg_tbl[i].flags;
5219 if (is_5709 && (flags & BNX2_FL_NOT_5709))
5222 offset = (u32) reg_tbl[i].offset;
5223 rw_mask = reg_tbl[i].rw_mask;
5224 ro_mask = reg_tbl[i].ro_mask;
5226 save_val = readl(bp->regview + offset);
5228 writel(0, bp->regview + offset);
5230 val = readl(bp->regview + offset);
5231 if ((val & rw_mask) != 0) {
5235 if ((val & ro_mask) != (save_val & ro_mask)) {
5239 writel(0xffffffff, bp->regview + offset);
5241 val = readl(bp->regview + offset);
5242 if ((val & rw_mask) != rw_mask) {
5246 if ((val & ro_mask) != (save_val & ro_mask)) {
5250 writel(save_val, bp->regview + offset);
5254 writel(save_val, bp->regview + offset);
5262 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
5264 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
5265 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
5268 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
5271 for (offset = 0; offset < size; offset += 4) {
5273 bnx2_reg_wr_ind(bp, start + offset, test_pattern[i]);
5275 if (bnx2_reg_rd_ind(bp, start + offset) !=
5285 bnx2_test_memory(struct bnx2 *bp)
5289 static struct mem_entry {
5292 } mem_tbl_5706[] = {
5293 { 0x60000, 0x4000 },
5294 { 0xa0000, 0x3000 },
5295 { 0xe0000, 0x4000 },
5296 { 0x120000, 0x4000 },
5297 { 0x1a0000, 0x4000 },
5298 { 0x160000, 0x4000 },
5302 { 0x60000, 0x4000 },
5303 { 0xa0000, 0x3000 },
5304 { 0xe0000, 0x4000 },
5305 { 0x120000, 0x4000 },
5306 { 0x1a0000, 0x4000 },
5309 struct mem_entry *mem_tbl;
5311 if (CHIP_NUM(bp) == CHIP_NUM_5709)
5312 mem_tbl = mem_tbl_5709;
5314 mem_tbl = mem_tbl_5706;
5316 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
5317 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
5318 mem_tbl[i].len)) != 0) {
5326 #define BNX2_MAC_LOOPBACK 0
5327 #define BNX2_PHY_LOOPBACK 1
5330 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
5332 unsigned int pkt_size, num_pkts, i;
5333 struct sk_buff *skb, *rx_skb;
5334 unsigned char *packet;
5335 u16 rx_start_idx, rx_idx;
5338 struct sw_bd *rx_buf;
5339 struct l2_fhdr *rx_hdr;
5341 struct bnx2_napi *bnapi = &bp->bnx2_napi[0], *tx_napi;
5342 struct bnx2_tx_ring_info *txr = &bnapi->tx_ring;
5343 struct bnx2_rx_ring_info *rxr = &bnapi->rx_ring;
5347 txr = &tx_napi->tx_ring;
5348 rxr = &bnapi->rx_ring;
5349 if (loopback_mode == BNX2_MAC_LOOPBACK) {
5350 bp->loopback = MAC_LOOPBACK;
5351 bnx2_set_mac_loopback(bp);
5353 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
5354 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5357 bp->loopback = PHY_LOOPBACK;
5358 bnx2_set_phy_loopback(bp);
5363 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
5364 skb = netdev_alloc_skb(bp->dev, pkt_size);
5367 packet = skb_put(skb, pkt_size);
5368 memcpy(packet, bp->dev->dev_addr, 6);
5369 memset(packet + 6, 0x0, 8);
5370 for (i = 14; i < pkt_size; i++)
5371 packet[i] = (unsigned char) (i & 0xff);
5373 map = pci_map_single(bp->pdev, skb->data, pkt_size,
5376 REG_WR(bp, BNX2_HC_COMMAND,
5377 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5379 REG_RD(bp, BNX2_HC_COMMAND);
5382 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
5386 txbd = &txr->tx_desc_ring[TX_RING_IDX(txr->tx_prod)];
5388 txbd->tx_bd_haddr_hi = (u64) map >> 32;
5389 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
5390 txbd->tx_bd_mss_nbytes = pkt_size;
5391 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
5394 txr->tx_prod = NEXT_TX_BD(txr->tx_prod);
5395 txr->tx_prod_bseq += pkt_size;
5397 REG_WR16(bp, txr->tx_bidx_addr, txr->tx_prod);
5398 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
5402 REG_WR(bp, BNX2_HC_COMMAND,
5403 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
5405 REG_RD(bp, BNX2_HC_COMMAND);
5409 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
5412 if (bnx2_get_hw_tx_cons(tx_napi) != txr->tx_prod)
5413 goto loopback_test_done;
5415 rx_idx = bnx2_get_hw_rx_cons(bnapi);
5416 if (rx_idx != rx_start_idx + num_pkts) {
5417 goto loopback_test_done;
5420 rx_buf = &rxr->rx_buf_ring[rx_start_idx];
5421 rx_skb = rx_buf->skb;
5423 rx_hdr = (struct l2_fhdr *) rx_skb->data;
5424 skb_reserve(rx_skb, BNX2_RX_OFFSET);
5426 pci_dma_sync_single_for_cpu(bp->pdev,
5427 pci_unmap_addr(rx_buf, mapping),
5428 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
5430 if (rx_hdr->l2_fhdr_status &
5431 (L2_FHDR_ERRORS_BAD_CRC |
5432 L2_FHDR_ERRORS_PHY_DECODE |
5433 L2_FHDR_ERRORS_ALIGNMENT |
5434 L2_FHDR_ERRORS_TOO_SHORT |
5435 L2_FHDR_ERRORS_GIANT_FRAME)) {
5437 goto loopback_test_done;
5440 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5441 goto loopback_test_done;
5444 for (i = 14; i < pkt_size; i++) {
5445 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5446 goto loopback_test_done;
5457 #define BNX2_MAC_LOOPBACK_FAILED 1
5458 #define BNX2_PHY_LOOPBACK_FAILED 2
5459 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5460 BNX2_PHY_LOOPBACK_FAILED)
5463 bnx2_test_loopback(struct bnx2 *bp)
5467 if (!netif_running(bp->dev))
5468 return BNX2_LOOPBACK_FAILED;
5470 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5471 spin_lock_bh(&bp->phy_lock);
5472 bnx2_init_phy(bp, 1);
5473 spin_unlock_bh(&bp->phy_lock);
5474 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5475 rc |= BNX2_MAC_LOOPBACK_FAILED;
5476 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5477 rc |= BNX2_PHY_LOOPBACK_FAILED;
5481 #define NVRAM_SIZE 0x200
5482 #define CRC32_RESIDUAL 0xdebb20e3
5485 bnx2_test_nvram(struct bnx2 *bp)
5487 __be32 buf[NVRAM_SIZE / 4];
5488 u8 *data = (u8 *) buf;
5492 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5493 goto test_nvram_done;
5495 magic = be32_to_cpu(buf[0]);
5496 if (magic != 0x669955aa) {
5498 goto test_nvram_done;
5501 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5502 goto test_nvram_done;
5504 csum = ether_crc_le(0x100, data);
5505 if (csum != CRC32_RESIDUAL) {
5507 goto test_nvram_done;
5510 csum = ether_crc_le(0x100, data + 0x100);
5511 if (csum != CRC32_RESIDUAL) {
5520 bnx2_test_link(struct bnx2 *bp)
5524 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
5529 spin_lock_bh(&bp->phy_lock);
5530 bnx2_enable_bmsr1(bp);
5531 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5532 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5533 bnx2_disable_bmsr1(bp);
5534 spin_unlock_bh(&bp->phy_lock);
5536 if (bmsr & BMSR_LSTATUS) {
5543 bnx2_test_intr(struct bnx2 *bp)
5548 if (!netif_running(bp->dev))
5551 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5553 /* This register is not touched during run-time. */
5554 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5555 REG_RD(bp, BNX2_HC_COMMAND);
5557 for (i = 0; i < 10; i++) {
5558 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5564 msleep_interruptible(10);
5572 /* Determining link for parallel detection. */
5574 bnx2_5706_serdes_has_link(struct bnx2 *bp)
5576 u32 mode_ctl, an_dbg, exp;
5578 if (bp->phy_flags & BNX2_PHY_FLAG_NO_PARALLEL)
5581 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_MODE_CTL);
5582 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &mode_ctl);
5584 if (!(mode_ctl & MISC_SHDW_MODE_CTL_SIG_DET))
5587 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5588 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5589 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &an_dbg);
5591 if (an_dbg & (MISC_SHDW_AN_DBG_NOSYNC | MISC_SHDW_AN_DBG_RUDI_INVALID))
5594 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, MII_EXPAND_REG1);
5595 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5596 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &exp);
5598 if (exp & MII_EXPAND_REG1_RUDI_C) /* receiving CONFIG */
5605 bnx2_5706_serdes_timer(struct bnx2 *bp)
5609 spin_lock(&bp->phy_lock);
5610 if (bp->serdes_an_pending) {
5611 bp->serdes_an_pending--;
5613 } else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5616 bp->current_interval = BNX2_TIMER_INTERVAL;
5618 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5620 if (bmcr & BMCR_ANENABLE) {
5621 if (bnx2_5706_serdes_has_link(bp)) {
5622 bmcr &= ~BMCR_ANENABLE;
5623 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5624 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5625 bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT;
5629 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5630 (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) {
5633 bnx2_write_phy(bp, 0x17, 0x0f01);
5634 bnx2_read_phy(bp, 0x15, &phy2);
5638 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5639 bmcr |= BMCR_ANENABLE;
5640 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5642 bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT;
5645 bp->current_interval = BNX2_TIMER_INTERVAL;
5650 bnx2_write_phy(bp, MII_BNX2_MISC_SHADOW, MISC_SHDW_AN_DBG);
5651 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5652 bnx2_read_phy(bp, MII_BNX2_MISC_SHADOW, &val);
5654 if (bp->link_up && (val & MISC_SHDW_AN_DBG_NOSYNC)) {
5655 if (!(bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN)) {
5656 bnx2_5706s_force_link_dn(bp, 1);
5657 bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN;
5660 } else if (!bp->link_up && !(val & MISC_SHDW_AN_DBG_NOSYNC))
5663 spin_unlock(&bp->phy_lock);
5667 bnx2_5708_serdes_timer(struct bnx2 *bp)
5669 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
5672 if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) {
5673 bp->serdes_an_pending = 0;
5677 spin_lock(&bp->phy_lock);
5678 if (bp->serdes_an_pending)
5679 bp->serdes_an_pending--;
5680 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5683 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5684 if (bmcr & BMCR_ANENABLE) {
5685 bnx2_enable_forced_2g5(bp);
5686 bp->current_interval = SERDES_FORCED_TIMEOUT;
5688 bnx2_disable_forced_2g5(bp);
5689 bp->serdes_an_pending = 2;
5690 bp->current_interval = BNX2_TIMER_INTERVAL;
5694 bp->current_interval = BNX2_TIMER_INTERVAL;
5696 spin_unlock(&bp->phy_lock);
5700 bnx2_timer(unsigned long data)
5702 struct bnx2 *bp = (struct bnx2 *) data;
5704 if (!netif_running(bp->dev))
5707 if (atomic_read(&bp->intr_sem) != 0)
5708 goto bnx2_restart_timer;
5710 bnx2_send_heart_beat(bp);
5712 bp->stats_blk->stat_FwRxDrop =
5713 bnx2_reg_rd_ind(bp, BNX2_FW_RX_DROP_COUNT);
5715 /* workaround occasional corrupted counters */
5716 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5717 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5718 BNX2_HC_COMMAND_STATS_NOW);
5720 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
5721 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5722 bnx2_5706_serdes_timer(bp);
5724 bnx2_5708_serdes_timer(bp);
5728 mod_timer(&bp->timer, jiffies + bp->current_interval);
5732 bnx2_request_irq(struct bnx2 *bp)
5734 unsigned long flags;
5735 struct bnx2_irq *irq;
5738 if (bp->flags & BNX2_FLAG_USING_MSI_OR_MSIX)
5741 flags = IRQF_SHARED;
5743 for (i = 0; i < bp->irq_nvecs; i++) {
5744 irq = &bp->irq_tbl[i];
5745 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
5755 bnx2_free_irq(struct bnx2 *bp)
5757 struct bnx2_irq *irq;
5760 for (i = 0; i < bp->irq_nvecs; i++) {
5761 irq = &bp->irq_tbl[i];
5763 free_irq(irq->vector, &bp->bnx2_napi[i]);
5766 if (bp->flags & BNX2_FLAG_USING_MSI)
5767 pci_disable_msi(bp->pdev);
5768 else if (bp->flags & BNX2_FLAG_USING_MSIX)
5769 pci_disable_msix(bp->pdev);
5771 bp->flags &= ~(BNX2_FLAG_USING_MSI_OR_MSIX | BNX2_FLAG_ONE_SHOT_MSI);
5775 bnx2_enable_msix(struct bnx2 *bp, int msix_vecs)
5778 struct msix_entry msix_ent[BNX2_MAX_MSIX_VEC];
5780 bnx2_setup_msix_tbl(bp);
5781 REG_WR(bp, BNX2_PCI_MSIX_CONTROL, BNX2_MAX_MSIX_HW_VEC - 1);
5782 REG_WR(bp, BNX2_PCI_MSIX_TBL_OFF_BIR, BNX2_PCI_GRC_WINDOW2_BASE);
5783 REG_WR(bp, BNX2_PCI_MSIX_PBA_OFF_BIT, BNX2_PCI_GRC_WINDOW3_BASE);
5785 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
5786 msix_ent[i].entry = i;
5787 msix_ent[i].vector = 0;
5789 strcpy(bp->irq_tbl[i].name, bp->dev->name);
5790 bp->irq_tbl[i].handler = bnx2_msi_1shot;
5793 rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC);
5797 bp->irq_nvecs = msix_vecs;
5798 bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI;
5799 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++)
5800 bp->irq_tbl[i].vector = msix_ent[i].vector;
5804 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5806 int cpus = num_online_cpus();
5807 int msix_vecs = min(cpus + 1, RX_MAX_RINGS);
5809 bp->irq_tbl[0].handler = bnx2_interrupt;
5810 strcpy(bp->irq_tbl[0].name, bp->dev->name);
5812 bp->irq_tbl[0].vector = bp->pdev->irq;
5814 if ((bp->flags & BNX2_FLAG_MSIX_CAP) && !dis_msi && cpus > 1)
5815 bnx2_enable_msix(bp, msix_vecs);
5817 if ((bp->flags & BNX2_FLAG_MSI_CAP) && !dis_msi &&
5818 !(bp->flags & BNX2_FLAG_USING_MSIX)) {
5819 if (pci_enable_msi(bp->pdev) == 0) {
5820 bp->flags |= BNX2_FLAG_USING_MSI;
5821 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5822 bp->flags |= BNX2_FLAG_ONE_SHOT_MSI;
5823 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5825 bp->irq_tbl[0].handler = bnx2_msi;
5827 bp->irq_tbl[0].vector = bp->pdev->irq;
5831 bp->num_tx_rings = rounddown_pow_of_two(bp->irq_nvecs);
5832 bp->dev->real_num_tx_queues = bp->num_tx_rings;
5834 bp->num_rx_rings = bp->irq_nvecs;
5837 /* Called with rtnl_lock */
5839 bnx2_open(struct net_device *dev)
5841 struct bnx2 *bp = netdev_priv(dev);
5844 netif_carrier_off(dev);
5846 bnx2_set_power_state(bp, PCI_D0);
5847 bnx2_disable_int(bp);
5849 bnx2_setup_int_mode(bp, disable_msi);
5850 bnx2_napi_enable(bp);
5851 rc = bnx2_alloc_mem(bp);
5855 rc = bnx2_request_irq(bp);
5859 rc = bnx2_init_nic(bp, 1);
5863 mod_timer(&bp->timer, jiffies + bp->current_interval);
5865 atomic_set(&bp->intr_sem, 0);
5867 bnx2_enable_int(bp);
5869 if (bp->flags & BNX2_FLAG_USING_MSI) {
5870 /* Test MSI to make sure it is working
5871 * If MSI test fails, go back to INTx mode
5873 if (bnx2_test_intr(bp) != 0) {
5874 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5875 " using MSI, switching to INTx mode. Please"
5876 " report this failure to the PCI maintainer"
5877 " and include system chipset information.\n",
5880 bnx2_disable_int(bp);
5883 bnx2_setup_int_mode(bp, 1);
5885 rc = bnx2_init_nic(bp, 0);
5888 rc = bnx2_request_irq(bp);
5891 del_timer_sync(&bp->timer);
5894 bnx2_enable_int(bp);
5897 if (bp->flags & BNX2_FLAG_USING_MSI)
5898 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5899 else if (bp->flags & BNX2_FLAG_USING_MSIX)
5900 printk(KERN_INFO PFX "%s: using MSIX\n", dev->name);
5902 netif_tx_start_all_queues(dev);
5907 bnx2_napi_disable(bp);
5915 bnx2_reset_task(struct work_struct *work)
5917 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5919 if (!netif_running(bp->dev))
5922 bnx2_netif_stop(bp);
5924 bnx2_init_nic(bp, 1);
5926 atomic_set(&bp->intr_sem, 1);
5927 bnx2_netif_start(bp);
5931 bnx2_tx_timeout(struct net_device *dev)
5933 struct bnx2 *bp = netdev_priv(dev);
5935 /* This allows the netif to be shutdown gracefully before resetting */
5936 schedule_work(&bp->reset_task);
5940 /* Called with rtnl_lock */
5942 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5944 struct bnx2 *bp = netdev_priv(dev);
5946 bnx2_netif_stop(bp);
5949 bnx2_set_rx_mode(dev);
5950 if (bp->flags & BNX2_FLAG_CAN_KEEP_VLAN)
5951 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE, 0, 1);
5953 bnx2_netif_start(bp);
5957 /* Called with netif_tx_lock.
5958 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5959 * netif_wake_queue().
5962 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5964 struct bnx2 *bp = netdev_priv(dev);
5967 struct sw_bd *tx_buf;
5968 u32 len, vlan_tag_flags, last_frag, mss;
5969 u16 prod, ring_prod;
5971 struct bnx2_napi *bnapi;
5972 struct bnx2_tx_ring_info *txr;
5973 struct netdev_queue *txq;
5975 /* Determine which tx ring we will be placed on */
5976 i = skb_get_queue_mapping(skb);
5977 bnapi = &bp->bnx2_napi[i];
5978 txr = &bnapi->tx_ring;
5979 txq = netdev_get_tx_queue(dev, i);
5981 if (unlikely(bnx2_tx_avail(bp, txr) <
5982 (skb_shinfo(skb)->nr_frags + 1))) {
5983 netif_tx_stop_queue(txq);
5984 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5987 return NETDEV_TX_BUSY;
5989 len = skb_headlen(skb);
5990 prod = txr->tx_prod;
5991 ring_prod = TX_RING_IDX(prod);
5994 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5995 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5999 if (bp->vlgrp && vlan_tx_tag_present(skb)) {
6001 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
6004 if ((mss = skb_shinfo(skb)->gso_size)) {
6005 u32 tcp_opt_len, ip_tcp_len;
6008 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
6010 tcp_opt_len = tcp_optlen(skb);
6012 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
6013 u32 tcp_off = skb_transport_offset(skb) -
6014 sizeof(struct ipv6hdr) - ETH_HLEN;
6016 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
6017 TX_BD_FLAGS_SW_FLAGS;
6018 if (likely(tcp_off == 0))
6019 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
6022 vlan_tag_flags |= ((tcp_off & 0x3) <<
6023 TX_BD_FLAGS_TCP6_OFF0_SHL) |
6024 ((tcp_off & 0x10) <<
6025 TX_BD_FLAGS_TCP6_OFF4_SHL);
6026 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
6029 if (skb_header_cloned(skb) &&
6030 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
6032 return NETDEV_TX_OK;
6035 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
6039 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
6040 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6044 if (tcp_opt_len || (iph->ihl > 5)) {
6045 vlan_tag_flags |= ((iph->ihl - 5) +
6046 (tcp_opt_len >> 2)) << 8;
6052 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6054 tx_buf = &txr->tx_buf_ring[ring_prod];
6056 pci_unmap_addr_set(tx_buf, mapping, mapping);
6058 txbd = &txr->tx_desc_ring[ring_prod];
6060 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6061 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6062 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6063 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
6065 last_frag = skb_shinfo(skb)->nr_frags;
6067 for (i = 0; i < last_frag; i++) {
6068 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6070 prod = NEXT_TX_BD(prod);
6071 ring_prod = TX_RING_IDX(prod);
6072 txbd = &txr->tx_desc_ring[ring_prod];
6075 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
6076 len, PCI_DMA_TODEVICE);
6077 pci_unmap_addr_set(&txr->tx_buf_ring[ring_prod],
6080 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
6081 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
6082 txbd->tx_bd_mss_nbytes = len | (mss << 16);
6083 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
6086 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
6088 prod = NEXT_TX_BD(prod);
6089 txr->tx_prod_bseq += skb->len;
6091 REG_WR16(bp, txr->tx_bidx_addr, prod);
6092 REG_WR(bp, txr->tx_bseq_addr, txr->tx_prod_bseq);
6096 txr->tx_prod = prod;
6097 dev->trans_start = jiffies;
6099 if (unlikely(bnx2_tx_avail(bp, txr) <= MAX_SKB_FRAGS)) {
6100 netif_tx_stop_queue(txq);
6101 if (bnx2_tx_avail(bp, txr) > bp->tx_wake_thresh)
6102 netif_tx_wake_queue(txq);
6105 return NETDEV_TX_OK;
6108 /* Called with rtnl_lock */
6110 bnx2_close(struct net_device *dev)
6112 struct bnx2 *bp = netdev_priv(dev);
6114 cancel_work_sync(&bp->reset_task);
6116 bnx2_disable_int_sync(bp);
6117 bnx2_napi_disable(bp);
6118 del_timer_sync(&bp->timer);
6119 bnx2_shutdown_chip(bp);
6124 netif_carrier_off(bp->dev);
6125 bnx2_set_power_state(bp, PCI_D3hot);
6129 #define GET_NET_STATS64(ctr) \
6130 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
6131 (unsigned long) (ctr##_lo)
6133 #define GET_NET_STATS32(ctr) \
6136 #if (BITS_PER_LONG == 64)
6137 #define GET_NET_STATS GET_NET_STATS64
6139 #define GET_NET_STATS GET_NET_STATS32
6142 static struct net_device_stats *
6143 bnx2_get_stats(struct net_device *dev)
6145 struct bnx2 *bp = netdev_priv(dev);
6146 struct statistics_block *stats_blk = bp->stats_blk;
6147 struct net_device_stats *net_stats = &bp->net_stats;
6149 if (bp->stats_blk == NULL) {
6152 net_stats->rx_packets =
6153 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
6154 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
6155 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
6157 net_stats->tx_packets =
6158 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
6159 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
6160 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
6162 net_stats->rx_bytes =
6163 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
6165 net_stats->tx_bytes =
6166 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
6168 net_stats->multicast =
6169 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
6171 net_stats->collisions =
6172 (unsigned long) stats_blk->stat_EtherStatsCollisions;
6174 net_stats->rx_length_errors =
6175 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
6176 stats_blk->stat_EtherStatsOverrsizePkts);
6178 net_stats->rx_over_errors =
6179 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
6181 net_stats->rx_frame_errors =
6182 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
6184 net_stats->rx_crc_errors =
6185 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
6187 net_stats->rx_errors = net_stats->rx_length_errors +
6188 net_stats->rx_over_errors + net_stats->rx_frame_errors +
6189 net_stats->rx_crc_errors;
6191 net_stats->tx_aborted_errors =
6192 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
6193 stats_blk->stat_Dot3StatsLateCollisions);
6195 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
6196 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6197 net_stats->tx_carrier_errors = 0;
6199 net_stats->tx_carrier_errors =
6201 stats_blk->stat_Dot3StatsCarrierSenseErrors;
6204 net_stats->tx_errors =
6206 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
6208 net_stats->tx_aborted_errors +
6209 net_stats->tx_carrier_errors;
6211 net_stats->rx_missed_errors =
6212 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
6213 stats_blk->stat_FwRxDrop);
6218 /* All ethtool functions called with rtnl_lock */
6221 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6223 struct bnx2 *bp = netdev_priv(dev);
6224 int support_serdes = 0, support_copper = 0;
6226 cmd->supported = SUPPORTED_Autoneg;
6227 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6230 } else if (bp->phy_port == PORT_FIBRE)
6235 if (support_serdes) {
6236 cmd->supported |= SUPPORTED_1000baseT_Full |
6238 if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)
6239 cmd->supported |= SUPPORTED_2500baseX_Full;
6242 if (support_copper) {
6243 cmd->supported |= SUPPORTED_10baseT_Half |
6244 SUPPORTED_10baseT_Full |
6245 SUPPORTED_100baseT_Half |
6246 SUPPORTED_100baseT_Full |
6247 SUPPORTED_1000baseT_Full |
6252 spin_lock_bh(&bp->phy_lock);
6253 cmd->port = bp->phy_port;
6254 cmd->advertising = bp->advertising;
6256 if (bp->autoneg & AUTONEG_SPEED) {
6257 cmd->autoneg = AUTONEG_ENABLE;
6260 cmd->autoneg = AUTONEG_DISABLE;
6263 if (netif_carrier_ok(dev)) {
6264 cmd->speed = bp->line_speed;
6265 cmd->duplex = bp->duplex;
6271 spin_unlock_bh(&bp->phy_lock);
6273 cmd->transceiver = XCVR_INTERNAL;
6274 cmd->phy_address = bp->phy_addr;
6280 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
6282 struct bnx2 *bp = netdev_priv(dev);
6283 u8 autoneg = bp->autoneg;
6284 u8 req_duplex = bp->req_duplex;
6285 u16 req_line_speed = bp->req_line_speed;
6286 u32 advertising = bp->advertising;
6289 spin_lock_bh(&bp->phy_lock);
6291 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
6292 goto err_out_unlock;
6294 if (cmd->port != bp->phy_port &&
6295 !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP))
6296 goto err_out_unlock;
6298 /* If device is down, we can store the settings only if the user
6299 * is setting the currently active port.
6301 if (!netif_running(dev) && cmd->port != bp->phy_port)
6302 goto err_out_unlock;
6304 if (cmd->autoneg == AUTONEG_ENABLE) {
6305 autoneg |= AUTONEG_SPEED;
6307 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
6309 /* allow advertising 1 speed */
6310 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
6311 (cmd->advertising == ADVERTISED_10baseT_Full) ||
6312 (cmd->advertising == ADVERTISED_100baseT_Half) ||
6313 (cmd->advertising == ADVERTISED_100baseT_Full)) {
6315 if (cmd->port == PORT_FIBRE)
6316 goto err_out_unlock;
6318 advertising = cmd->advertising;
6320 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
6321 if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ||
6322 (cmd->port == PORT_TP))
6323 goto err_out_unlock;
6324 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
6325 advertising = cmd->advertising;
6326 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
6327 goto err_out_unlock;
6329 if (cmd->port == PORT_FIBRE)
6330 advertising = ETHTOOL_ALL_FIBRE_SPEED;
6332 advertising = ETHTOOL_ALL_COPPER_SPEED;
6334 advertising |= ADVERTISED_Autoneg;
6337 if (cmd->port == PORT_FIBRE) {
6338 if ((cmd->speed != SPEED_1000 &&
6339 cmd->speed != SPEED_2500) ||
6340 (cmd->duplex != DUPLEX_FULL))
6341 goto err_out_unlock;
6343 if (cmd->speed == SPEED_2500 &&
6344 !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE))
6345 goto err_out_unlock;
6347 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
6348 goto err_out_unlock;
6350 autoneg &= ~AUTONEG_SPEED;
6351 req_line_speed = cmd->speed;
6352 req_duplex = cmd->duplex;
6356 bp->autoneg = autoneg;
6357 bp->advertising = advertising;
6358 bp->req_line_speed = req_line_speed;
6359 bp->req_duplex = req_duplex;
6362 /* If device is down, the new settings will be picked up when it is
6365 if (netif_running(dev))
6366 err = bnx2_setup_phy(bp, cmd->port);
6369 spin_unlock_bh(&bp->phy_lock);
6375 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
6377 struct bnx2 *bp = netdev_priv(dev);
6379 strcpy(info->driver, DRV_MODULE_NAME);
6380 strcpy(info->version, DRV_MODULE_VERSION);
6381 strcpy(info->bus_info, pci_name(bp->pdev));
6382 strcpy(info->fw_version, bp->fw_version);
6385 #define BNX2_REGDUMP_LEN (32 * 1024)
6388 bnx2_get_regs_len(struct net_device *dev)
6390 return BNX2_REGDUMP_LEN;
6394 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
6396 u32 *p = _p, i, offset;
6398 struct bnx2 *bp = netdev_priv(dev);
6399 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
6400 0x0800, 0x0880, 0x0c00, 0x0c10,
6401 0x0c30, 0x0d08, 0x1000, 0x101c,
6402 0x1040, 0x1048, 0x1080, 0x10a4,
6403 0x1400, 0x1490, 0x1498, 0x14f0,
6404 0x1500, 0x155c, 0x1580, 0x15dc,
6405 0x1600, 0x1658, 0x1680, 0x16d8,
6406 0x1800, 0x1820, 0x1840, 0x1854,
6407 0x1880, 0x1894, 0x1900, 0x1984,
6408 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
6409 0x1c80, 0x1c94, 0x1d00, 0x1d84,
6410 0x2000, 0x2030, 0x23c0, 0x2400,
6411 0x2800, 0x2820, 0x2830, 0x2850,
6412 0x2b40, 0x2c10, 0x2fc0, 0x3058,
6413 0x3c00, 0x3c94, 0x4000, 0x4010,
6414 0x4080, 0x4090, 0x43c0, 0x4458,
6415 0x4c00, 0x4c18, 0x4c40, 0x4c54,
6416 0x4fc0, 0x5010, 0x53c0, 0x5444,
6417 0x5c00, 0x5c18, 0x5c80, 0x5c90,
6418 0x5fc0, 0x6000, 0x6400, 0x6428,
6419 0x6800, 0x6848, 0x684c, 0x6860,
6420 0x6888, 0x6910, 0x8000 };
6424 memset(p, 0, BNX2_REGDUMP_LEN);
6426 if (!netif_running(bp->dev))
6430 offset = reg_boundaries[0];
6432 while (offset < BNX2_REGDUMP_LEN) {
6433 *p++ = REG_RD(bp, offset);
6435 if (offset == reg_boundaries[i + 1]) {
6436 offset = reg_boundaries[i + 2];
6437 p = (u32 *) (orig_p + offset);
6444 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6446 struct bnx2 *bp = netdev_priv(dev);
6448 if (bp->flags & BNX2_FLAG_NO_WOL) {
6453 wol->supported = WAKE_MAGIC;
6455 wol->wolopts = WAKE_MAGIC;
6459 memset(&wol->sopass, 0, sizeof(wol->sopass));
6463 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
6465 struct bnx2 *bp = netdev_priv(dev);
6467 if (wol->wolopts & ~WAKE_MAGIC)
6470 if (wol->wolopts & WAKE_MAGIC) {
6471 if (bp->flags & BNX2_FLAG_NO_WOL)
6483 bnx2_nway_reset(struct net_device *dev)
6485 struct bnx2 *bp = netdev_priv(dev);
6488 if (!(bp->autoneg & AUTONEG_SPEED)) {
6492 spin_lock_bh(&bp->phy_lock);
6494 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) {
6497 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
6498 spin_unlock_bh(&bp->phy_lock);
6502 /* Force a link down visible on the other side */
6503 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
6504 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
6505 spin_unlock_bh(&bp->phy_lock);
6509 spin_lock_bh(&bp->phy_lock);
6511 bp->current_interval = SERDES_AN_TIMEOUT;
6512 bp->serdes_an_pending = 1;
6513 mod_timer(&bp->timer, jiffies + bp->current_interval);
6516 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
6517 bmcr &= ~BMCR_LOOPBACK;
6518 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
6520 spin_unlock_bh(&bp->phy_lock);
6526 bnx2_get_eeprom_len(struct net_device *dev)
6528 struct bnx2 *bp = netdev_priv(dev);
6530 if (bp->flash_info == NULL)
6533 return (int) bp->flash_size;
6537 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6540 struct bnx2 *bp = netdev_priv(dev);
6543 /* parameters already validated in ethtool_get_eeprom */
6545 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6551 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6554 struct bnx2 *bp = netdev_priv(dev);
6557 /* parameters already validated in ethtool_set_eeprom */
6559 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6565 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6567 struct bnx2 *bp = netdev_priv(dev);
6569 memset(coal, 0, sizeof(struct ethtool_coalesce));
6571 coal->rx_coalesce_usecs = bp->rx_ticks;
6572 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6573 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6574 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6576 coal->tx_coalesce_usecs = bp->tx_ticks;
6577 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6578 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6579 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6581 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6587 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6589 struct bnx2 *bp = netdev_priv(dev);
6591 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6592 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6594 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6595 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6597 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6598 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6600 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6601 if (bp->rx_quick_cons_trip_int > 0xff)
6602 bp->rx_quick_cons_trip_int = 0xff;
6604 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6605 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6607 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6608 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6610 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6611 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6613 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6614 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6617 bp->stats_ticks = coal->stats_block_coalesce_usecs;
6618 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6619 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6620 bp->stats_ticks = USEC_PER_SEC;
6622 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6623 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6624 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6626 if (netif_running(bp->dev)) {
6627 bnx2_netif_stop(bp);
6628 bnx2_init_nic(bp, 0);
6629 bnx2_netif_start(bp);
6636 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6638 struct bnx2 *bp = netdev_priv(dev);
6640 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6641 ering->rx_mini_max_pending = 0;
6642 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6644 ering->rx_pending = bp->rx_ring_size;
6645 ering->rx_mini_pending = 0;
6646 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6648 ering->tx_max_pending = MAX_TX_DESC_CNT;
6649 ering->tx_pending = bp->tx_ring_size;
6653 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6655 if (netif_running(bp->dev)) {
6656 bnx2_netif_stop(bp);
6657 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6662 bnx2_set_rx_ring_size(bp, rx);
6663 bp->tx_ring_size = tx;
6665 if (netif_running(bp->dev)) {
6668 rc = bnx2_alloc_mem(bp);
6671 bnx2_init_nic(bp, 0);
6672 bnx2_netif_start(bp);
6678 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6680 struct bnx2 *bp = netdev_priv(dev);
6683 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6684 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6685 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6689 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6694 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6696 struct bnx2 *bp = netdev_priv(dev);
6698 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6699 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6700 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6704 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6706 struct bnx2 *bp = netdev_priv(dev);
6708 bp->req_flow_ctrl = 0;
6709 if (epause->rx_pause)
6710 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6711 if (epause->tx_pause)
6712 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6714 if (epause->autoneg) {
6715 bp->autoneg |= AUTONEG_FLOW_CTRL;
6718 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6721 spin_lock_bh(&bp->phy_lock);
6723 bnx2_setup_phy(bp, bp->phy_port);
6725 spin_unlock_bh(&bp->phy_lock);
6731 bnx2_get_rx_csum(struct net_device *dev)
6733 struct bnx2 *bp = netdev_priv(dev);
6739 bnx2_set_rx_csum(struct net_device *dev, u32 data)
6741 struct bnx2 *bp = netdev_priv(dev);
6748 bnx2_set_tso(struct net_device *dev, u32 data)
6750 struct bnx2 *bp = netdev_priv(dev);
6753 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6754 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6755 dev->features |= NETIF_F_TSO6;
6757 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6762 #define BNX2_NUM_STATS 46
6765 char string[ETH_GSTRING_LEN];
6766 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6768 { "rx_error_bytes" },
6770 { "tx_error_bytes" },
6771 { "rx_ucast_packets" },
6772 { "rx_mcast_packets" },
6773 { "rx_bcast_packets" },
6774 { "tx_ucast_packets" },
6775 { "tx_mcast_packets" },
6776 { "tx_bcast_packets" },
6777 { "tx_mac_errors" },
6778 { "tx_carrier_errors" },
6779 { "rx_crc_errors" },
6780 { "rx_align_errors" },
6781 { "tx_single_collisions" },
6782 { "tx_multi_collisions" },
6784 { "tx_excess_collisions" },
6785 { "tx_late_collisions" },
6786 { "tx_total_collisions" },
6789 { "rx_undersize_packets" },
6790 { "rx_oversize_packets" },
6791 { "rx_64_byte_packets" },
6792 { "rx_65_to_127_byte_packets" },
6793 { "rx_128_to_255_byte_packets" },
6794 { "rx_256_to_511_byte_packets" },
6795 { "rx_512_to_1023_byte_packets" },
6796 { "rx_1024_to_1522_byte_packets" },
6797 { "rx_1523_to_9022_byte_packets" },
6798 { "tx_64_byte_packets" },
6799 { "tx_65_to_127_byte_packets" },
6800 { "tx_128_to_255_byte_packets" },
6801 { "tx_256_to_511_byte_packets" },
6802 { "tx_512_to_1023_byte_packets" },
6803 { "tx_1024_to_1522_byte_packets" },
6804 { "tx_1523_to_9022_byte_packets" },
6805 { "rx_xon_frames" },
6806 { "rx_xoff_frames" },
6807 { "tx_xon_frames" },
6808 { "tx_xoff_frames" },
6809 { "rx_mac_ctrl_frames" },
6810 { "rx_filtered_packets" },
6812 { "rx_fw_discards" },
6815 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6817 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
6818 STATS_OFFSET32(stat_IfHCInOctets_hi),
6819 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6820 STATS_OFFSET32(stat_IfHCOutOctets_hi),
6821 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6822 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6823 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6824 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6825 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6826 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6827 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6828 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6829 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6830 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6831 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6832 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6833 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6834 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6835 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6836 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6837 STATS_OFFSET32(stat_EtherStatsCollisions),
6838 STATS_OFFSET32(stat_EtherStatsFragments),
6839 STATS_OFFSET32(stat_EtherStatsJabbers),
6840 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6841 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6842 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6843 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6844 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6845 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6846 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6847 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6848 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6849 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6850 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6851 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6852 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6853 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6854 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6855 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6856 STATS_OFFSET32(stat_XonPauseFramesReceived),
6857 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6858 STATS_OFFSET32(stat_OutXonSent),
6859 STATS_OFFSET32(stat_OutXoffSent),
6860 STATS_OFFSET32(stat_MacControlFramesReceived),
6861 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6862 STATS_OFFSET32(stat_IfInMBUFDiscards),
6863 STATS_OFFSET32(stat_FwRxDrop),
6866 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6867 * skipped because of errata.
6869 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6870 8,0,8,8,8,8,8,8,8,8,
6871 4,0,4,4,4,4,4,4,4,4,
6872 4,4,4,4,4,4,4,4,4,4,
6873 4,4,4,4,4,4,4,4,4,4,
6877 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6878 8,0,8,8,8,8,8,8,8,8,
6879 4,4,4,4,4,4,4,4,4,4,
6880 4,4,4,4,4,4,4,4,4,4,
6881 4,4,4,4,4,4,4,4,4,4,
6885 #define BNX2_NUM_TESTS 6
6888 char string[ETH_GSTRING_LEN];
6889 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6890 { "register_test (offline)" },
6891 { "memory_test (offline)" },
6892 { "loopback_test (offline)" },
6893 { "nvram_test (online)" },
6894 { "interrupt_test (online)" },
6895 { "link_test (online)" },
6899 bnx2_get_sset_count(struct net_device *dev, int sset)
6903 return BNX2_NUM_TESTS;
6905 return BNX2_NUM_STATS;
6912 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6914 struct bnx2 *bp = netdev_priv(dev);
6916 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6917 if (etest->flags & ETH_TEST_FL_OFFLINE) {
6920 bnx2_netif_stop(bp);
6921 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6924 if (bnx2_test_registers(bp) != 0) {
6926 etest->flags |= ETH_TEST_FL_FAILED;
6928 if (bnx2_test_memory(bp) != 0) {
6930 etest->flags |= ETH_TEST_FL_FAILED;
6932 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6933 etest->flags |= ETH_TEST_FL_FAILED;
6935 if (!netif_running(bp->dev)) {
6936 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6939 bnx2_init_nic(bp, 1);
6940 bnx2_netif_start(bp);
6943 /* wait for link up */
6944 for (i = 0; i < 7; i++) {
6947 msleep_interruptible(1000);
6951 if (bnx2_test_nvram(bp) != 0) {
6953 etest->flags |= ETH_TEST_FL_FAILED;
6955 if (bnx2_test_intr(bp) != 0) {
6957 etest->flags |= ETH_TEST_FL_FAILED;
6960 if (bnx2_test_link(bp) != 0) {
6962 etest->flags |= ETH_TEST_FL_FAILED;
6968 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6970 switch (stringset) {
6972 memcpy(buf, bnx2_stats_str_arr,
6973 sizeof(bnx2_stats_str_arr));
6976 memcpy(buf, bnx2_tests_str_arr,
6977 sizeof(bnx2_tests_str_arr));
6983 bnx2_get_ethtool_stats(struct net_device *dev,
6984 struct ethtool_stats *stats, u64 *buf)
6986 struct bnx2 *bp = netdev_priv(dev);
6988 u32 *hw_stats = (u32 *) bp->stats_blk;
6989 u8 *stats_len_arr = NULL;
6991 if (hw_stats == NULL) {
6992 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6996 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6997 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6998 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6999 (CHIP_ID(bp) == CHIP_ID_5708_A0))
7000 stats_len_arr = bnx2_5706_stats_len_arr;
7002 stats_len_arr = bnx2_5708_stats_len_arr;
7004 for (i = 0; i < BNX2_NUM_STATS; i++) {
7005 if (stats_len_arr[i] == 0) {
7006 /* skip this counter */
7010 if (stats_len_arr[i] == 4) {
7011 /* 4-byte counter */
7013 *(hw_stats + bnx2_stats_offset_arr[i]);
7016 /* 8-byte counter */
7017 buf[i] = (((u64) *(hw_stats +
7018 bnx2_stats_offset_arr[i])) << 32) +
7019 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
7024 bnx2_phys_id(struct net_device *dev, u32 data)
7026 struct bnx2 *bp = netdev_priv(dev);
7033 save = REG_RD(bp, BNX2_MISC_CFG);
7034 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
7036 for (i = 0; i < (data * 2); i++) {
7038 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
7041 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
7042 BNX2_EMAC_LED_1000MB_OVERRIDE |
7043 BNX2_EMAC_LED_100MB_OVERRIDE |
7044 BNX2_EMAC_LED_10MB_OVERRIDE |
7045 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
7046 BNX2_EMAC_LED_TRAFFIC);
7048 msleep_interruptible(500);
7049 if (signal_pending(current))
7052 REG_WR(bp, BNX2_EMAC_LED, 0);
7053 REG_WR(bp, BNX2_MISC_CFG, save);
7058 bnx2_set_tx_csum(struct net_device *dev, u32 data)
7060 struct bnx2 *bp = netdev_priv(dev);
7062 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7063 return (ethtool_op_set_tx_ipv6_csum(dev, data));
7065 return (ethtool_op_set_tx_csum(dev, data));
7068 static const struct ethtool_ops bnx2_ethtool_ops = {
7069 .get_settings = bnx2_get_settings,
7070 .set_settings = bnx2_set_settings,
7071 .get_drvinfo = bnx2_get_drvinfo,
7072 .get_regs_len = bnx2_get_regs_len,
7073 .get_regs = bnx2_get_regs,
7074 .get_wol = bnx2_get_wol,
7075 .set_wol = bnx2_set_wol,
7076 .nway_reset = bnx2_nway_reset,
7077 .get_link = ethtool_op_get_link,
7078 .get_eeprom_len = bnx2_get_eeprom_len,
7079 .get_eeprom = bnx2_get_eeprom,
7080 .set_eeprom = bnx2_set_eeprom,
7081 .get_coalesce = bnx2_get_coalesce,
7082 .set_coalesce = bnx2_set_coalesce,
7083 .get_ringparam = bnx2_get_ringparam,
7084 .set_ringparam = bnx2_set_ringparam,
7085 .get_pauseparam = bnx2_get_pauseparam,
7086 .set_pauseparam = bnx2_set_pauseparam,
7087 .get_rx_csum = bnx2_get_rx_csum,
7088 .set_rx_csum = bnx2_set_rx_csum,
7089 .set_tx_csum = bnx2_set_tx_csum,
7090 .set_sg = ethtool_op_set_sg,
7091 .set_tso = bnx2_set_tso,
7092 .self_test = bnx2_self_test,
7093 .get_strings = bnx2_get_strings,
7094 .phys_id = bnx2_phys_id,
7095 .get_ethtool_stats = bnx2_get_ethtool_stats,
7096 .get_sset_count = bnx2_get_sset_count,
7099 /* Called with rtnl_lock */
7101 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7103 struct mii_ioctl_data *data = if_mii(ifr);
7104 struct bnx2 *bp = netdev_priv(dev);
7109 data->phy_id = bp->phy_addr;
7115 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7118 if (!netif_running(dev))
7121 spin_lock_bh(&bp->phy_lock);
7122 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
7123 spin_unlock_bh(&bp->phy_lock);
7125 data->val_out = mii_regval;
7131 if (!capable(CAP_NET_ADMIN))
7134 if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)
7137 if (!netif_running(dev))
7140 spin_lock_bh(&bp->phy_lock);
7141 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
7142 spin_unlock_bh(&bp->phy_lock);
7153 /* Called with rtnl_lock */
7155 bnx2_change_mac_addr(struct net_device *dev, void *p)
7157 struct sockaddr *addr = p;
7158 struct bnx2 *bp = netdev_priv(dev);
7160 if (!is_valid_ether_addr(addr->sa_data))
7163 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7164 if (netif_running(dev))
7165 bnx2_set_mac_addr(bp, bp->dev->dev_addr, 0);
7170 /* Called with rtnl_lock */
7172 bnx2_change_mtu(struct net_device *dev, int new_mtu)
7174 struct bnx2 *bp = netdev_priv(dev);
7176 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
7177 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
7181 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
7184 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7186 poll_bnx2(struct net_device *dev)
7188 struct bnx2 *bp = netdev_priv(dev);
7190 disable_irq(bp->pdev->irq);
7191 bnx2_interrupt(bp->pdev->irq, dev);
7192 enable_irq(bp->pdev->irq);
7196 static void __devinit
7197 bnx2_get_5709_media(struct bnx2 *bp)
7199 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
7200 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
7203 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
7205 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
7206 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7210 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
7211 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
7213 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
7215 if (PCI_FUNC(bp->pdev->devfn) == 0) {
7220 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7228 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7234 static void __devinit
7235 bnx2_get_pci_speed(struct bnx2 *bp)
7239 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
7240 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
7243 bp->flags |= BNX2_FLAG_PCIX;
7245 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
7247 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
7249 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
7250 bp->bus_speed_mhz = 133;
7253 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
7254 bp->bus_speed_mhz = 100;
7257 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
7258 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
7259 bp->bus_speed_mhz = 66;
7262 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
7263 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
7264 bp->bus_speed_mhz = 50;
7267 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
7268 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
7269 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
7270 bp->bus_speed_mhz = 33;
7275 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
7276 bp->bus_speed_mhz = 66;
7278 bp->bus_speed_mhz = 33;
7281 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
7282 bp->flags |= BNX2_FLAG_PCI_32BIT;
7286 static int __devinit
7287 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
7290 unsigned long mem_len;
7293 u64 dma_mask, persist_dma_mask;
7295 SET_NETDEV_DEV(dev, &pdev->dev);
7296 bp = netdev_priv(dev);
7301 /* enable device (incl. PCI PM wakeup), and bus-mastering */
7302 rc = pci_enable_device(pdev);
7304 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
7308 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
7310 "Cannot find PCI device base address, aborting.\n");
7312 goto err_out_disable;
7315 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
7317 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
7318 goto err_out_disable;
7321 pci_set_master(pdev);
7322 pci_save_state(pdev);
7324 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
7325 if (bp->pm_cap == 0) {
7327 "Cannot find power management capability, aborting.\n");
7329 goto err_out_release;
7335 spin_lock_init(&bp->phy_lock);
7336 spin_lock_init(&bp->indirect_lock);
7337 INIT_WORK(&bp->reset_task, bnx2_reset_task);
7339 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
7340 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + TX_MAX_TSS_RINGS);
7341 dev->mem_end = dev->mem_start + mem_len;
7342 dev->irq = pdev->irq;
7344 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
7347 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
7349 goto err_out_release;
7352 /* Configure byte swap and enable write to the reg_window registers.
7353 * Rely on CPU to do target byte swapping on big endian systems
7354 * The chip's target access swapping will not swap all accesses
7356 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
7357 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
7358 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
7360 bnx2_set_power_state(bp, PCI_D0);
7362 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
7364 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
7365 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
7367 "Cannot find PCIE capability, aborting.\n");
7371 bp->flags |= BNX2_FLAG_PCIE;
7372 if (CHIP_REV(bp) == CHIP_REV_Ax)
7373 bp->flags |= BNX2_FLAG_JUMBO_BROKEN;
7375 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
7376 if (bp->pcix_cap == 0) {
7378 "Cannot find PCIX capability, aborting.\n");
7384 if (CHIP_NUM(bp) == CHIP_NUM_5709 && CHIP_REV(bp) != CHIP_REV_Ax) {
7385 if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
7386 bp->flags |= BNX2_FLAG_MSIX_CAP;
7389 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
7390 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
7391 bp->flags |= BNX2_FLAG_MSI_CAP;
7394 /* 5708 cannot support DMA addresses > 40-bit. */
7395 if (CHIP_NUM(bp) == CHIP_NUM_5708)
7396 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
7398 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
7400 /* Configure DMA attributes. */
7401 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
7402 dev->features |= NETIF_F_HIGHDMA;
7403 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
7406 "pci_set_consistent_dma_mask failed, aborting.\n");
7409 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
7410 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
7414 if (!(bp->flags & BNX2_FLAG_PCIE))
7415 bnx2_get_pci_speed(bp);
7417 /* 5706A0 may falsely detect SERR and PERR. */
7418 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7419 reg = REG_RD(bp, PCI_COMMAND);
7420 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
7421 REG_WR(bp, PCI_COMMAND, reg);
7423 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
7424 !(bp->flags & BNX2_FLAG_PCIX)) {
7427 "5706 A1 can only be used in a PCIX bus, aborting.\n");
7431 bnx2_init_nvram(bp);
7433 reg = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_SIGNATURE);
7435 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
7436 BNX2_SHM_HDR_SIGNATURE_SIG) {
7437 u32 off = PCI_FUNC(pdev->devfn) << 2;
7439 bp->shmem_base = bnx2_reg_rd_ind(bp, BNX2_SHM_HDR_ADDR_0 + off);
7441 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
7443 /* Get the permanent MAC address. First we need to make sure the
7444 * firmware is actually running.
7446 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_SIGNATURE);
7448 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
7449 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
7450 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
7455 reg = bnx2_shmem_rd(bp, BNX2_DEV_INFO_BC_REV);
7456 for (i = 0, j = 0; i < 3; i++) {
7459 num = (u8) (reg >> (24 - (i * 8)));
7460 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
7461 if (num >= k || !skip0 || k == 1) {
7462 bp->fw_version[j++] = (num / k) + '0';
7467 bp->fw_version[j++] = '.';
7469 reg = bnx2_shmem_rd(bp, BNX2_PORT_FEATURE);
7470 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
7473 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
7474 bp->flags |= BNX2_FLAG_ASF_ENABLE;
7476 for (i = 0; i < 30; i++) {
7477 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7478 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
7483 reg = bnx2_shmem_rd(bp, BNX2_BC_STATE_CONDITION);
7484 reg &= BNX2_CONDITION_MFW_RUN_MASK;
7485 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
7486 reg != BNX2_CONDITION_MFW_RUN_NONE) {
7487 u32 addr = bnx2_shmem_rd(bp, BNX2_MFW_VER_PTR);
7489 bp->fw_version[j++] = ' ';
7490 for (i = 0; i < 3; i++) {
7491 reg = bnx2_reg_rd_ind(bp, addr + i * 4);
7493 memcpy(&bp->fw_version[j], ®, 4);
7498 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_UPPER);
7499 bp->mac_addr[0] = (u8) (reg >> 8);
7500 bp->mac_addr[1] = (u8) reg;
7502 reg = bnx2_shmem_rd(bp, BNX2_PORT_HW_CFG_MAC_LOWER);
7503 bp->mac_addr[2] = (u8) (reg >> 24);
7504 bp->mac_addr[3] = (u8) (reg >> 16);
7505 bp->mac_addr[4] = (u8) (reg >> 8);
7506 bp->mac_addr[5] = (u8) reg;
7508 bp->tx_ring_size = MAX_TX_DESC_CNT;
7509 bnx2_set_rx_ring_size(bp, 255);
7513 bp->tx_quick_cons_trip_int = 20;
7514 bp->tx_quick_cons_trip = 20;
7515 bp->tx_ticks_int = 80;
7518 bp->rx_quick_cons_trip_int = 6;
7519 bp->rx_quick_cons_trip = 6;
7520 bp->rx_ticks_int = 18;
7523 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
7525 bp->current_interval = BNX2_TIMER_INTERVAL;
7529 /* Disable WOL support if we are running on a SERDES chip. */
7530 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7531 bnx2_get_5709_media(bp);
7532 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
7533 bp->phy_flags |= BNX2_PHY_FLAG_SERDES;
7535 bp->phy_port = PORT_TP;
7536 if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) {
7537 bp->phy_port = PORT_FIBRE;
7538 reg = bnx2_shmem_rd(bp, BNX2_SHARED_HW_CFG_CONFIG);
7539 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7540 bp->flags |= BNX2_FLAG_NO_WOL;
7543 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
7544 /* Don't do parallel detect on this board because of
7545 * some board problems. The link will not go down
7546 * if we do parallel detect.
7548 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
7549 pdev->subsystem_device == 0x310c)
7550 bp->phy_flags |= BNX2_PHY_FLAG_NO_PARALLEL;
7553 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7554 bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE;
7556 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7557 CHIP_NUM(bp) == CHIP_NUM_5708)
7558 bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX;
7559 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7560 (CHIP_REV(bp) == CHIP_REV_Ax ||
7561 CHIP_REV(bp) == CHIP_REV_Bx))
7562 bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC;
7564 bnx2_init_fw_cap(bp);
7566 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7567 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7568 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
7569 bp->flags |= BNX2_FLAG_NO_WOL;
7573 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7574 bp->tx_quick_cons_trip_int =
7575 bp->tx_quick_cons_trip;
7576 bp->tx_ticks_int = bp->tx_ticks;
7577 bp->rx_quick_cons_trip_int =
7578 bp->rx_quick_cons_trip;
7579 bp->rx_ticks_int = bp->rx_ticks;
7580 bp->comp_prod_trip_int = bp->comp_prod_trip;
7581 bp->com_ticks_int = bp->com_ticks;
7582 bp->cmd_ticks_int = bp->cmd_ticks;
7585 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7587 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7588 * with byte enables disabled on the unused 32-bit word. This is legal
7589 * but causes problems on the AMD 8132 which will eventually stop
7590 * responding after a while.
7592 * AMD believes this incompatibility is unique to the 5706, and
7593 * prefers to locally disable MSI rather than globally disabling it.
7595 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7596 struct pci_dev *amd_8132 = NULL;
7598 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7599 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7602 if (amd_8132->revision >= 0x10 &&
7603 amd_8132->revision <= 0x13) {
7605 pci_dev_put(amd_8132);
7611 bnx2_set_default_link(bp);
7612 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7614 init_timer(&bp->timer);
7615 bp->timer.expires = RUN_AT(BNX2_TIMER_INTERVAL);
7616 bp->timer.data = (unsigned long) bp;
7617 bp->timer.function = bnx2_timer;
7623 iounmap(bp->regview);
7628 pci_release_regions(pdev);
7631 pci_disable_device(pdev);
7632 pci_set_drvdata(pdev, NULL);
7638 static char * __devinit
7639 bnx2_bus_string(struct bnx2 *bp, char *str)
7643 if (bp->flags & BNX2_FLAG_PCIE) {
7644 s += sprintf(s, "PCI Express");
7646 s += sprintf(s, "PCI");
7647 if (bp->flags & BNX2_FLAG_PCIX)
7648 s += sprintf(s, "-X");
7649 if (bp->flags & BNX2_FLAG_PCI_32BIT)
7650 s += sprintf(s, " 32-bit");
7652 s += sprintf(s, " 64-bit");
7653 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7658 static void __devinit
7659 bnx2_init_napi(struct bnx2 *bp)
7663 for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) {
7664 struct bnx2_napi *bnapi = &bp->bnx2_napi[i];
7665 int (*poll)(struct napi_struct *, int);
7670 poll = bnx2_poll_msix;
7672 netif_napi_add(bp->dev, &bp->bnx2_napi[i].napi, poll, 64);
7677 static int __devinit
7678 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7680 static int version_printed = 0;
7681 struct net_device *dev = NULL;
7685 DECLARE_MAC_BUF(mac);
7687 if (version_printed++ == 0)
7688 printk(KERN_INFO "%s", version);
7690 /* dev zeroed in init_etherdev */
7691 dev = alloc_etherdev_mq(sizeof(*bp), TX_MAX_RINGS);
7696 rc = bnx2_init_board(pdev, dev);
7702 dev->open = bnx2_open;
7703 dev->hard_start_xmit = bnx2_start_xmit;
7704 dev->stop = bnx2_close;
7705 dev->get_stats = bnx2_get_stats;
7706 dev->set_rx_mode = bnx2_set_rx_mode;
7707 dev->do_ioctl = bnx2_ioctl;
7708 dev->set_mac_address = bnx2_change_mac_addr;
7709 dev->change_mtu = bnx2_change_mtu;
7710 dev->tx_timeout = bnx2_tx_timeout;
7711 dev->watchdog_timeo = TX_TIMEOUT;
7713 dev->vlan_rx_register = bnx2_vlan_rx_register;
7715 dev->ethtool_ops = &bnx2_ethtool_ops;
7717 bp = netdev_priv(dev);
7720 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7721 dev->poll_controller = poll_bnx2;
7724 pci_set_drvdata(pdev, dev);
7726 memcpy(dev->dev_addr, bp->mac_addr, 6);
7727 memcpy(dev->perm_addr, bp->mac_addr, 6);
7729 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
7730 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7731 dev->features |= NETIF_F_IPV6_CSUM;
7734 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7736 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7737 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7738 dev->features |= NETIF_F_TSO6;
7740 if ((rc = register_netdev(dev))) {
7741 dev_err(&pdev->dev, "Cannot register net device\n");
7743 iounmap(bp->regview);
7744 pci_release_regions(pdev);
7745 pci_disable_device(pdev);
7746 pci_set_drvdata(pdev, NULL);
7751 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
7752 "IRQ %d, node addr %s\n",
7754 board_info[ent->driver_data].name,
7755 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7756 ((CHIP_ID(bp) & 0x0ff0) >> 4),
7757 bnx2_bus_string(bp, str),
7759 bp->pdev->irq, print_mac(mac, dev->dev_addr));
7764 static void __devexit
7765 bnx2_remove_one(struct pci_dev *pdev)
7767 struct net_device *dev = pci_get_drvdata(pdev);
7768 struct bnx2 *bp = netdev_priv(dev);
7770 flush_scheduled_work();
7772 unregister_netdev(dev);
7775 iounmap(bp->regview);
7778 pci_release_regions(pdev);
7779 pci_disable_device(pdev);
7780 pci_set_drvdata(pdev, NULL);
7784 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
7786 struct net_device *dev = pci_get_drvdata(pdev);
7787 struct bnx2 *bp = netdev_priv(dev);
7789 /* PCI register 4 needs to be saved whether netif_running() or not.
7790 * MSI address and data need to be saved if using MSI and
7793 pci_save_state(pdev);
7794 if (!netif_running(dev))
7797 flush_scheduled_work();
7798 bnx2_netif_stop(bp);
7799 netif_device_detach(dev);
7800 del_timer_sync(&bp->timer);
7801 bnx2_shutdown_chip(bp);
7803 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
7808 bnx2_resume(struct pci_dev *pdev)
7810 struct net_device *dev = pci_get_drvdata(pdev);
7811 struct bnx2 *bp = netdev_priv(dev);
7813 pci_restore_state(pdev);
7814 if (!netif_running(dev))
7817 bnx2_set_power_state(bp, PCI_D0);
7818 netif_device_attach(dev);
7819 bnx2_init_nic(bp, 1);
7820 bnx2_netif_start(bp);
7825 * bnx2_io_error_detected - called when PCI error is detected
7826 * @pdev: Pointer to PCI device
7827 * @state: The current pci connection state
7829 * This function is called after a PCI bus error affecting
7830 * this device has been detected.
7832 static pci_ers_result_t bnx2_io_error_detected(struct pci_dev *pdev,
7833 pci_channel_state_t state)
7835 struct net_device *dev = pci_get_drvdata(pdev);
7836 struct bnx2 *bp = netdev_priv(dev);
7839 netif_device_detach(dev);
7841 if (netif_running(dev)) {
7842 bnx2_netif_stop(bp);
7843 del_timer_sync(&bp->timer);
7844 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
7847 pci_disable_device(pdev);
7850 /* Request a slot slot reset. */
7851 return PCI_ERS_RESULT_NEED_RESET;
7855 * bnx2_io_slot_reset - called after the pci bus has been reset.
7856 * @pdev: Pointer to PCI device
7858 * Restart the card from scratch, as if from a cold-boot.
7860 static pci_ers_result_t bnx2_io_slot_reset(struct pci_dev *pdev)
7862 struct net_device *dev = pci_get_drvdata(pdev);
7863 struct bnx2 *bp = netdev_priv(dev);
7866 if (pci_enable_device(pdev)) {
7868 "Cannot re-enable PCI device after reset.\n");
7870 return PCI_ERS_RESULT_DISCONNECT;
7872 pci_set_master(pdev);
7873 pci_restore_state(pdev);
7875 if (netif_running(dev)) {
7876 bnx2_set_power_state(bp, PCI_D0);
7877 bnx2_init_nic(bp, 1);
7881 return PCI_ERS_RESULT_RECOVERED;
7885 * bnx2_io_resume - called when traffic can start flowing again.
7886 * @pdev: Pointer to PCI device
7888 * This callback is called when the error recovery driver tells us that
7889 * its OK to resume normal operation.
7891 static void bnx2_io_resume(struct pci_dev *pdev)
7893 struct net_device *dev = pci_get_drvdata(pdev);
7894 struct bnx2 *bp = netdev_priv(dev);
7897 if (netif_running(dev))
7898 bnx2_netif_start(bp);
7900 netif_device_attach(dev);
7904 static struct pci_error_handlers bnx2_err_handler = {
7905 .error_detected = bnx2_io_error_detected,
7906 .slot_reset = bnx2_io_slot_reset,
7907 .resume = bnx2_io_resume,
7910 static struct pci_driver bnx2_pci_driver = {
7911 .name = DRV_MODULE_NAME,
7912 .id_table = bnx2_pci_tbl,
7913 .probe = bnx2_init_one,
7914 .remove = __devexit_p(bnx2_remove_one),
7915 .suspend = bnx2_suspend,
7916 .resume = bnx2_resume,
7917 .err_handler = &bnx2_err_handler,
7920 static int __init bnx2_init(void)
7922 return pci_register_driver(&bnx2_pci_driver);
7925 static void __exit bnx2_cleanup(void)
7927 pci_unregister_driver(&bnx2_pci_driver);
7930 module_init(bnx2_init);
7931 module_exit(bnx2_cleanup);