1 /* bnx2.c: Broadcom NX2 network driver.
3 * Copyright (c) 2004-2007 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Written by: Michael Chan (mchan@broadcom.com)
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/timer.h>
18 #include <linux/errno.h>
19 #include <linux/ioport.h>
20 #include <linux/slab.h>
21 #include <linux/vmalloc.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/bitops.h>
32 #include <linux/delay.h>
33 #include <asm/byteorder.h>
35 #include <linux/time.h>
36 #include <linux/ethtool.h>
37 #include <linux/mii.h>
38 #ifdef NETIF_F_HW_VLAN_TX
39 #include <linux/if_vlan.h>
44 #include <net/checksum.h>
45 #include <linux/workqueue.h>
46 #include <linux/crc32.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/zlib.h>
55 #define FW_BUF_SIZE 0x10000
57 #define DRV_MODULE_NAME "bnx2"
58 #define PFX DRV_MODULE_NAME ": "
59 #define DRV_MODULE_VERSION "1.7.0"
60 #define DRV_MODULE_RELDATE "December 11, 2007"
62 #define RUN_AT(x) (jiffies + (x))
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT (5*HZ)
67 static const char version[] __devinitdata =
68 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
70 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
71 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
72 MODULE_LICENSE("GPL");
73 MODULE_VERSION(DRV_MODULE_VERSION);
75 static int disable_msi = 0;
77 module_param(disable_msi, int, 0);
78 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
92 /* indexed by board_t, above */
95 } board_info[] __devinitdata = {
96 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
97 { "HP NC370T Multifunction Gigabit Server Adapter" },
98 { "HP NC370i Multifunction Gigabit Server Adapter" },
99 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
100 { "HP NC370F Multifunction Gigabit Server Adapter" },
101 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
102 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
103 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
104 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
107 static struct pci_device_id bnx2_pci_tbl[] = {
108 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
109 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
110 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
111 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
112 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
114 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
116 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
117 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
118 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
120 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
122 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
124 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
129 static struct flash_spec flash_table[] =
131 #define BUFFERED_FLAGS (BNX2_NV_BUFFERED | BNX2_NV_TRANSLATE)
132 #define NONBUFFERED_FLAGS (BNX2_NV_WREN)
134 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
135 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
136 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
138 /* Expansion entry 0001 */
139 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
140 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
141 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
143 /* Saifun SA25F010 (non-buffered flash) */
144 /* strap, cfg1, & write1 need updates */
145 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
146 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
147 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
148 "Non-buffered flash (128kB)"},
149 /* Saifun SA25F020 (non-buffered flash) */
150 /* strap, cfg1, & write1 need updates */
151 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
152 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
153 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
154 "Non-buffered flash (256kB)"},
155 /* Expansion entry 0100 */
156 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
158 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
160 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
161 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
162 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
163 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
164 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
165 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
166 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
167 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
168 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
169 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
170 /* Saifun SA25F005 (non-buffered flash) */
171 /* strap, cfg1, & write1 need updates */
172 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
173 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
174 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
175 "Non-buffered flash (64kB)"},
177 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
178 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
179 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
181 /* Expansion entry 1001 */
182 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
183 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
184 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
186 /* Expansion entry 1010 */
187 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
188 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
189 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
191 /* ATMEL AT45DB011B (buffered flash) */
192 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
193 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
194 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
195 "Buffered flash (128kB)"},
196 /* Expansion entry 1100 */
197 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
198 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
199 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
201 /* Expansion entry 1101 */
202 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
203 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
204 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
206 /* Ateml Expansion entry 1110 */
207 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
208 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
209 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
210 "Entry 1110 (Atmel)"},
211 /* ATMEL AT45DB021B (buffered flash) */
212 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
213 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
214 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
215 "Buffered flash (256kB)"},
218 static struct flash_spec flash_5709 = {
219 .flags = BNX2_NV_BUFFERED,
220 .page_bits = BCM5709_FLASH_PAGE_BITS,
221 .page_size = BCM5709_FLASH_PAGE_SIZE,
222 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
223 .total_size = BUFFERED_FLASH_TOTAL_SIZE*2,
224 .name = "5709 Buffered flash (256kB)",
227 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
229 static inline u32 bnx2_tx_avail(struct bnx2 *bp, struct bnx2_napi *bnapi)
235 /* The ring uses 256 indices for 255 entries, one of them
236 * needs to be skipped.
238 diff = bp->tx_prod - bnapi->tx_cons;
239 if (unlikely(diff >= TX_DESC_CNT)) {
241 if (diff == TX_DESC_CNT)
242 diff = MAX_TX_DESC_CNT;
244 return (bp->tx_ring_size - diff);
248 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
252 spin_lock_bh(&bp->indirect_lock);
253 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
254 val = REG_RD(bp, BNX2_PCICFG_REG_WINDOW);
255 spin_unlock_bh(&bp->indirect_lock);
260 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
262 spin_lock_bh(&bp->indirect_lock);
263 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
264 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
265 spin_unlock_bh(&bp->indirect_lock);
269 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
272 spin_lock_bh(&bp->indirect_lock);
273 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
276 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
277 REG_WR(bp, BNX2_CTX_CTX_CTRL,
278 offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
279 for (i = 0; i < 5; i++) {
281 val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
282 if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
287 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
288 REG_WR(bp, BNX2_CTX_DATA, val);
290 spin_unlock_bh(&bp->indirect_lock);
294 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
299 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
300 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
301 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
303 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
304 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
309 val1 = (bp->phy_addr << 21) | (reg << 16) |
310 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
311 BNX2_EMAC_MDIO_COMM_START_BUSY;
312 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
314 for (i = 0; i < 50; i++) {
317 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
318 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
321 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
322 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
328 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
337 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
338 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
339 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
341 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
342 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
351 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
356 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
357 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
358 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
360 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
361 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
366 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
367 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
368 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
369 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
371 for (i = 0; i < 50; i++) {
374 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
375 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
381 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
386 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
387 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
388 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
390 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
391 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
400 bnx2_disable_int(struct bnx2 *bp)
402 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
403 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
404 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
408 bnx2_enable_int(struct bnx2 *bp)
410 struct bnx2_napi *bnapi = &bp->bnx2_napi;
412 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
413 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
414 BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bnapi->last_status_idx);
416 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
417 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bnapi->last_status_idx);
419 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
423 bnx2_disable_int_sync(struct bnx2 *bp)
425 atomic_inc(&bp->intr_sem);
426 bnx2_disable_int(bp);
427 synchronize_irq(bp->pdev->irq);
431 bnx2_napi_disable(struct bnx2 *bp)
433 napi_disable(&bp->bnx2_napi.napi);
437 bnx2_napi_enable(struct bnx2 *bp)
439 napi_enable(&bp->bnx2_napi.napi);
443 bnx2_netif_stop(struct bnx2 *bp)
445 bnx2_disable_int_sync(bp);
446 if (netif_running(bp->dev)) {
447 bnx2_napi_disable(bp);
448 netif_tx_disable(bp->dev);
449 bp->dev->trans_start = jiffies; /* prevent tx timeout */
454 bnx2_netif_start(struct bnx2 *bp)
456 if (atomic_dec_and_test(&bp->intr_sem)) {
457 if (netif_running(bp->dev)) {
458 netif_wake_queue(bp->dev);
459 bnx2_napi_enable(bp);
466 bnx2_free_mem(struct bnx2 *bp)
470 for (i = 0; i < bp->ctx_pages; i++) {
471 if (bp->ctx_blk[i]) {
472 pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
474 bp->ctx_blk_mapping[i]);
475 bp->ctx_blk[i] = NULL;
478 if (bp->status_blk) {
479 pci_free_consistent(bp->pdev, bp->status_stats_size,
480 bp->status_blk, bp->status_blk_mapping);
481 bp->status_blk = NULL;
482 bp->stats_blk = NULL;
484 if (bp->tx_desc_ring) {
485 pci_free_consistent(bp->pdev, TXBD_RING_SIZE,
486 bp->tx_desc_ring, bp->tx_desc_mapping);
487 bp->tx_desc_ring = NULL;
489 kfree(bp->tx_buf_ring);
490 bp->tx_buf_ring = NULL;
491 for (i = 0; i < bp->rx_max_ring; i++) {
492 if (bp->rx_desc_ring[i])
493 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
495 bp->rx_desc_mapping[i]);
496 bp->rx_desc_ring[i] = NULL;
498 vfree(bp->rx_buf_ring);
499 bp->rx_buf_ring = NULL;
500 for (i = 0; i < bp->rx_max_pg_ring; i++) {
501 if (bp->rx_pg_desc_ring[i])
502 pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
503 bp->rx_pg_desc_ring[i],
504 bp->rx_pg_desc_mapping[i]);
505 bp->rx_pg_desc_ring[i] = NULL;
508 vfree(bp->rx_pg_ring);
509 bp->rx_pg_ring = NULL;
513 bnx2_alloc_mem(struct bnx2 *bp)
515 int i, status_blk_size;
517 bp->tx_buf_ring = kzalloc(SW_TXBD_RING_SIZE, GFP_KERNEL);
518 if (bp->tx_buf_ring == NULL)
521 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev, TXBD_RING_SIZE,
522 &bp->tx_desc_mapping);
523 if (bp->tx_desc_ring == NULL)
526 bp->rx_buf_ring = vmalloc(SW_RXBD_RING_SIZE * bp->rx_max_ring);
527 if (bp->rx_buf_ring == NULL)
530 memset(bp->rx_buf_ring, 0, SW_RXBD_RING_SIZE * bp->rx_max_ring);
532 for (i = 0; i < bp->rx_max_ring; i++) {
533 bp->rx_desc_ring[i] =
534 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
535 &bp->rx_desc_mapping[i]);
536 if (bp->rx_desc_ring[i] == NULL)
541 if (bp->rx_pg_ring_size) {
542 bp->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
544 if (bp->rx_pg_ring == NULL)
547 memset(bp->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
551 for (i = 0; i < bp->rx_max_pg_ring; i++) {
552 bp->rx_pg_desc_ring[i] =
553 pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
554 &bp->rx_pg_desc_mapping[i]);
555 if (bp->rx_pg_desc_ring[i] == NULL)
560 /* Combine status and statistics blocks into one allocation. */
561 status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
562 bp->status_stats_size = status_blk_size +
563 sizeof(struct statistics_block);
565 bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
566 &bp->status_blk_mapping);
567 if (bp->status_blk == NULL)
570 memset(bp->status_blk, 0, bp->status_stats_size);
572 bp->bnx2_napi.status_blk = bp->status_blk;
574 bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
577 bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
579 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
580 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
581 if (bp->ctx_pages == 0)
583 for (i = 0; i < bp->ctx_pages; i++) {
584 bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
586 &bp->ctx_blk_mapping[i]);
587 if (bp->ctx_blk[i] == NULL)
599 bnx2_report_fw_link(struct bnx2 *bp)
601 u32 fw_link_status = 0;
603 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
609 switch (bp->line_speed) {
611 if (bp->duplex == DUPLEX_HALF)
612 fw_link_status = BNX2_LINK_STATUS_10HALF;
614 fw_link_status = BNX2_LINK_STATUS_10FULL;
617 if (bp->duplex == DUPLEX_HALF)
618 fw_link_status = BNX2_LINK_STATUS_100HALF;
620 fw_link_status = BNX2_LINK_STATUS_100FULL;
623 if (bp->duplex == DUPLEX_HALF)
624 fw_link_status = BNX2_LINK_STATUS_1000HALF;
626 fw_link_status = BNX2_LINK_STATUS_1000FULL;
629 if (bp->duplex == DUPLEX_HALF)
630 fw_link_status = BNX2_LINK_STATUS_2500HALF;
632 fw_link_status = BNX2_LINK_STATUS_2500FULL;
636 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
639 fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
641 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
642 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
644 if (!(bmsr & BMSR_ANEGCOMPLETE) ||
645 bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
646 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
648 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
652 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
654 REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
658 bnx2_xceiver_str(struct bnx2 *bp)
660 return ((bp->phy_port == PORT_FIBRE) ? "SerDes" :
661 ((bp->phy_flags & PHY_SERDES_FLAG) ? "Remote Copper" :
666 bnx2_report_link(struct bnx2 *bp)
669 netif_carrier_on(bp->dev);
670 printk(KERN_INFO PFX "%s NIC %s Link is Up, ", bp->dev->name,
671 bnx2_xceiver_str(bp));
673 printk("%d Mbps ", bp->line_speed);
675 if (bp->duplex == DUPLEX_FULL)
676 printk("full duplex");
678 printk("half duplex");
681 if (bp->flow_ctrl & FLOW_CTRL_RX) {
682 printk(", receive ");
683 if (bp->flow_ctrl & FLOW_CTRL_TX)
684 printk("& transmit ");
687 printk(", transmit ");
689 printk("flow control ON");
694 netif_carrier_off(bp->dev);
695 printk(KERN_ERR PFX "%s NIC %s Link is Down\n", bp->dev->name,
696 bnx2_xceiver_str(bp));
699 bnx2_report_fw_link(bp);
703 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
705 u32 local_adv, remote_adv;
708 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
709 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
711 if (bp->duplex == DUPLEX_FULL) {
712 bp->flow_ctrl = bp->req_flow_ctrl;
717 if (bp->duplex != DUPLEX_FULL) {
721 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
722 (CHIP_NUM(bp) == CHIP_NUM_5708)) {
725 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
726 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
727 bp->flow_ctrl |= FLOW_CTRL_TX;
728 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
729 bp->flow_ctrl |= FLOW_CTRL_RX;
733 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
734 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
736 if (bp->phy_flags & PHY_SERDES_FLAG) {
737 u32 new_local_adv = 0;
738 u32 new_remote_adv = 0;
740 if (local_adv & ADVERTISE_1000XPAUSE)
741 new_local_adv |= ADVERTISE_PAUSE_CAP;
742 if (local_adv & ADVERTISE_1000XPSE_ASYM)
743 new_local_adv |= ADVERTISE_PAUSE_ASYM;
744 if (remote_adv & ADVERTISE_1000XPAUSE)
745 new_remote_adv |= ADVERTISE_PAUSE_CAP;
746 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
747 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
749 local_adv = new_local_adv;
750 remote_adv = new_remote_adv;
753 /* See Table 28B-3 of 802.3ab-1999 spec. */
754 if (local_adv & ADVERTISE_PAUSE_CAP) {
755 if(local_adv & ADVERTISE_PAUSE_ASYM) {
756 if (remote_adv & ADVERTISE_PAUSE_CAP) {
757 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
759 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
760 bp->flow_ctrl = FLOW_CTRL_RX;
764 if (remote_adv & ADVERTISE_PAUSE_CAP) {
765 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
769 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
770 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
771 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
773 bp->flow_ctrl = FLOW_CTRL_TX;
779 bnx2_5709s_linkup(struct bnx2 *bp)
785 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
786 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
787 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
789 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
790 bp->line_speed = bp->req_line_speed;
791 bp->duplex = bp->req_duplex;
794 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
796 case MII_BNX2_GP_TOP_AN_SPEED_10:
797 bp->line_speed = SPEED_10;
799 case MII_BNX2_GP_TOP_AN_SPEED_100:
800 bp->line_speed = SPEED_100;
802 case MII_BNX2_GP_TOP_AN_SPEED_1G:
803 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
804 bp->line_speed = SPEED_1000;
806 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
807 bp->line_speed = SPEED_2500;
810 if (val & MII_BNX2_GP_TOP_AN_FD)
811 bp->duplex = DUPLEX_FULL;
813 bp->duplex = DUPLEX_HALF;
818 bnx2_5708s_linkup(struct bnx2 *bp)
823 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
824 switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
825 case BCM5708S_1000X_STAT1_SPEED_10:
826 bp->line_speed = SPEED_10;
828 case BCM5708S_1000X_STAT1_SPEED_100:
829 bp->line_speed = SPEED_100;
831 case BCM5708S_1000X_STAT1_SPEED_1G:
832 bp->line_speed = SPEED_1000;
834 case BCM5708S_1000X_STAT1_SPEED_2G5:
835 bp->line_speed = SPEED_2500;
838 if (val & BCM5708S_1000X_STAT1_FD)
839 bp->duplex = DUPLEX_FULL;
841 bp->duplex = DUPLEX_HALF;
847 bnx2_5706s_linkup(struct bnx2 *bp)
849 u32 bmcr, local_adv, remote_adv, common;
852 bp->line_speed = SPEED_1000;
854 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
855 if (bmcr & BMCR_FULLDPLX) {
856 bp->duplex = DUPLEX_FULL;
859 bp->duplex = DUPLEX_HALF;
862 if (!(bmcr & BMCR_ANENABLE)) {
866 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
867 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
869 common = local_adv & remote_adv;
870 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
872 if (common & ADVERTISE_1000XFULL) {
873 bp->duplex = DUPLEX_FULL;
876 bp->duplex = DUPLEX_HALF;
884 bnx2_copper_linkup(struct bnx2 *bp)
888 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
889 if (bmcr & BMCR_ANENABLE) {
890 u32 local_adv, remote_adv, common;
892 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
893 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
895 common = local_adv & (remote_adv >> 2);
896 if (common & ADVERTISE_1000FULL) {
897 bp->line_speed = SPEED_1000;
898 bp->duplex = DUPLEX_FULL;
900 else if (common & ADVERTISE_1000HALF) {
901 bp->line_speed = SPEED_1000;
902 bp->duplex = DUPLEX_HALF;
905 bnx2_read_phy(bp, bp->mii_adv, &local_adv);
906 bnx2_read_phy(bp, bp->mii_lpa, &remote_adv);
908 common = local_adv & remote_adv;
909 if (common & ADVERTISE_100FULL) {
910 bp->line_speed = SPEED_100;
911 bp->duplex = DUPLEX_FULL;
913 else if (common & ADVERTISE_100HALF) {
914 bp->line_speed = SPEED_100;
915 bp->duplex = DUPLEX_HALF;
917 else if (common & ADVERTISE_10FULL) {
918 bp->line_speed = SPEED_10;
919 bp->duplex = DUPLEX_FULL;
921 else if (common & ADVERTISE_10HALF) {
922 bp->line_speed = SPEED_10;
923 bp->duplex = DUPLEX_HALF;
932 if (bmcr & BMCR_SPEED100) {
933 bp->line_speed = SPEED_100;
936 bp->line_speed = SPEED_10;
938 if (bmcr & BMCR_FULLDPLX) {
939 bp->duplex = DUPLEX_FULL;
942 bp->duplex = DUPLEX_HALF;
950 bnx2_set_mac_link(struct bnx2 *bp)
954 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
955 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
956 (bp->duplex == DUPLEX_HALF)) {
957 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
960 /* Configure the EMAC mode register. */
961 val = REG_RD(bp, BNX2_EMAC_MODE);
963 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
964 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
965 BNX2_EMAC_MODE_25G_MODE);
968 switch (bp->line_speed) {
970 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
971 val |= BNX2_EMAC_MODE_PORT_MII_10M;
976 val |= BNX2_EMAC_MODE_PORT_MII;
979 val |= BNX2_EMAC_MODE_25G_MODE;
982 val |= BNX2_EMAC_MODE_PORT_GMII;
987 val |= BNX2_EMAC_MODE_PORT_GMII;
990 /* Set the MAC to operate in the appropriate duplex mode. */
991 if (bp->duplex == DUPLEX_HALF)
992 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
993 REG_WR(bp, BNX2_EMAC_MODE, val);
995 /* Enable/disable rx PAUSE. */
996 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
998 if (bp->flow_ctrl & FLOW_CTRL_RX)
999 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
1000 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
1002 /* Enable/disable tx PAUSE. */
1003 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
1004 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
1006 if (bp->flow_ctrl & FLOW_CTRL_TX)
1007 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
1008 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
1010 /* Acknowledge the interrupt. */
1011 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
1017 bnx2_enable_bmsr1(struct bnx2 *bp)
1019 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1020 (CHIP_NUM(bp) == CHIP_NUM_5709))
1021 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1022 MII_BNX2_BLK_ADDR_GP_STATUS);
1026 bnx2_disable_bmsr1(struct bnx2 *bp)
1028 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1029 (CHIP_NUM(bp) == CHIP_NUM_5709))
1030 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1031 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1035 bnx2_test_and_enable_2g5(struct bnx2 *bp)
1040 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1043 if (bp->autoneg & AUTONEG_SPEED)
1044 bp->advertising |= ADVERTISED_2500baseX_Full;
1046 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1047 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1049 bnx2_read_phy(bp, bp->mii_up1, &up1);
1050 if (!(up1 & BCM5708S_UP1_2G5)) {
1051 up1 |= BCM5708S_UP1_2G5;
1052 bnx2_write_phy(bp, bp->mii_up1, up1);
1056 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1057 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1058 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1064 bnx2_test_and_disable_2g5(struct bnx2 *bp)
1069 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1072 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1073 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1075 bnx2_read_phy(bp, bp->mii_up1, &up1);
1076 if (up1 & BCM5708S_UP1_2G5) {
1077 up1 &= ~BCM5708S_UP1_2G5;
1078 bnx2_write_phy(bp, bp->mii_up1, up1);
1082 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1083 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1084 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1090 bnx2_enable_forced_2g5(struct bnx2 *bp)
1094 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1097 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1100 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1101 MII_BNX2_BLK_ADDR_SERDES_DIG);
1102 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1103 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1104 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1105 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1107 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1108 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1109 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1111 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1112 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1113 bmcr |= BCM5708S_BMCR_FORCE_2500;
1116 if (bp->autoneg & AUTONEG_SPEED) {
1117 bmcr &= ~BMCR_ANENABLE;
1118 if (bp->req_duplex == DUPLEX_FULL)
1119 bmcr |= BMCR_FULLDPLX;
1121 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1125 bnx2_disable_forced_2g5(struct bnx2 *bp)
1129 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
1132 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1135 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1136 MII_BNX2_BLK_ADDR_SERDES_DIG);
1137 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1138 val &= ~MII_BNX2_SD_MISC1_FORCE;
1139 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1141 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1142 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1143 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1145 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1146 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1147 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
1150 if (bp->autoneg & AUTONEG_SPEED)
1151 bmcr |= BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_ANRESTART;
1152 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
1156 bnx2_set_link(struct bnx2 *bp)
1161 if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
1166 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1169 link_up = bp->link_up;
1171 bnx2_enable_bmsr1(bp);
1172 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1173 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1174 bnx2_disable_bmsr1(bp);
1176 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1177 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
1180 val = REG_RD(bp, BNX2_EMAC_STATUS);
1181 if (val & BNX2_EMAC_STATUS_LINK)
1182 bmsr |= BMSR_LSTATUS;
1184 bmsr &= ~BMSR_LSTATUS;
1187 if (bmsr & BMSR_LSTATUS) {
1190 if (bp->phy_flags & PHY_SERDES_FLAG) {
1191 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1192 bnx2_5706s_linkup(bp);
1193 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1194 bnx2_5708s_linkup(bp);
1195 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1196 bnx2_5709s_linkup(bp);
1199 bnx2_copper_linkup(bp);
1201 bnx2_resolve_flow_ctrl(bp);
1204 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
1205 (bp->autoneg & AUTONEG_SPEED))
1206 bnx2_disable_forced_2g5(bp);
1208 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1212 if (bp->link_up != link_up) {
1213 bnx2_report_link(bp);
1216 bnx2_set_mac_link(bp);
1222 bnx2_reset_phy(struct bnx2 *bp)
1227 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_RESET);
1229 #define PHY_RESET_MAX_WAIT 100
1230 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
1233 bnx2_read_phy(bp, bp->mii_bmcr, ®);
1234 if (!(reg & BMCR_RESET)) {
1239 if (i == PHY_RESET_MAX_WAIT) {
1246 bnx2_phy_get_pause_adv(struct bnx2 *bp)
1250 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1251 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1253 if (bp->phy_flags & PHY_SERDES_FLAG) {
1254 adv = ADVERTISE_1000XPAUSE;
1257 adv = ADVERTISE_PAUSE_CAP;
1260 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1261 if (bp->phy_flags & PHY_SERDES_FLAG) {
1262 adv = ADVERTISE_1000XPSE_ASYM;
1265 adv = ADVERTISE_PAUSE_ASYM;
1268 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1269 if (bp->phy_flags & PHY_SERDES_FLAG) {
1270 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1273 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1279 static int bnx2_fw_sync(struct bnx2 *, u32, int);
1282 bnx2_setup_remote_phy(struct bnx2 *bp, u8 port)
1284 u32 speed_arg = 0, pause_adv;
1286 pause_adv = bnx2_phy_get_pause_adv(bp);
1288 if (bp->autoneg & AUTONEG_SPEED) {
1289 speed_arg |= BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG;
1290 if (bp->advertising & ADVERTISED_10baseT_Half)
1291 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1292 if (bp->advertising & ADVERTISED_10baseT_Full)
1293 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1294 if (bp->advertising & ADVERTISED_100baseT_Half)
1295 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1296 if (bp->advertising & ADVERTISED_100baseT_Full)
1297 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1298 if (bp->advertising & ADVERTISED_1000baseT_Full)
1299 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1300 if (bp->advertising & ADVERTISED_2500baseX_Full)
1301 speed_arg |= BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1303 if (bp->req_line_speed == SPEED_2500)
1304 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_2G5FULL;
1305 else if (bp->req_line_speed == SPEED_1000)
1306 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_1GFULL;
1307 else if (bp->req_line_speed == SPEED_100) {
1308 if (bp->req_duplex == DUPLEX_FULL)
1309 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100FULL;
1311 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_100HALF;
1312 } else if (bp->req_line_speed == SPEED_10) {
1313 if (bp->req_duplex == DUPLEX_FULL)
1314 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10FULL;
1316 speed_arg = BNX2_NETLINK_SET_LINK_SPEED_10HALF;
1320 if (pause_adv & (ADVERTISE_1000XPAUSE | ADVERTISE_PAUSE_CAP))
1321 speed_arg |= BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE;
1322 if (pause_adv & (ADVERTISE_1000XPSE_ASYM | ADVERTISE_1000XPSE_ASYM))
1323 speed_arg |= BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE;
1325 if (port == PORT_TP)
1326 speed_arg |= BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE |
1327 BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED;
1329 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB_ARG0, speed_arg);
1331 spin_unlock_bh(&bp->phy_lock);
1332 bnx2_fw_sync(bp, BNX2_DRV_MSG_CODE_CMD_SET_LINK, 0);
1333 spin_lock_bh(&bp->phy_lock);
1339 bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port)
1344 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1345 return (bnx2_setup_remote_phy(bp, port));
1347 if (!(bp->autoneg & AUTONEG_SPEED)) {
1349 int force_link_down = 0;
1351 if (bp->req_line_speed == SPEED_2500) {
1352 if (!bnx2_test_and_enable_2g5(bp))
1353 force_link_down = 1;
1354 } else if (bp->req_line_speed == SPEED_1000) {
1355 if (bnx2_test_and_disable_2g5(bp))
1356 force_link_down = 1;
1358 bnx2_read_phy(bp, bp->mii_adv, &adv);
1359 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1361 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1362 new_bmcr = bmcr & ~BMCR_ANENABLE;
1363 new_bmcr |= BMCR_SPEED1000;
1365 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1366 if (bp->req_line_speed == SPEED_2500)
1367 bnx2_enable_forced_2g5(bp);
1368 else if (bp->req_line_speed == SPEED_1000) {
1369 bnx2_disable_forced_2g5(bp);
1370 new_bmcr &= ~0x2000;
1373 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1374 if (bp->req_line_speed == SPEED_2500)
1375 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1377 new_bmcr = bmcr & ~BCM5708S_BMCR_FORCE_2500;
1380 if (bp->req_duplex == DUPLEX_FULL) {
1381 adv |= ADVERTISE_1000XFULL;
1382 new_bmcr |= BMCR_FULLDPLX;
1385 adv |= ADVERTISE_1000XHALF;
1386 new_bmcr &= ~BMCR_FULLDPLX;
1388 if ((new_bmcr != bmcr) || (force_link_down)) {
1389 /* Force a link down visible on the other side */
1391 bnx2_write_phy(bp, bp->mii_adv, adv &
1392 ~(ADVERTISE_1000XFULL |
1393 ADVERTISE_1000XHALF));
1394 bnx2_write_phy(bp, bp->mii_bmcr, bmcr |
1395 BMCR_ANRESTART | BMCR_ANENABLE);
1398 netif_carrier_off(bp->dev);
1399 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1400 bnx2_report_link(bp);
1402 bnx2_write_phy(bp, bp->mii_adv, adv);
1403 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1405 bnx2_resolve_flow_ctrl(bp);
1406 bnx2_set_mac_link(bp);
1411 bnx2_test_and_enable_2g5(bp);
1413 if (bp->advertising & ADVERTISED_1000baseT_Full)
1414 new_adv |= ADVERTISE_1000XFULL;
1416 new_adv |= bnx2_phy_get_pause_adv(bp);
1418 bnx2_read_phy(bp, bp->mii_adv, &adv);
1419 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1421 bp->serdes_an_pending = 0;
1422 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1423 /* Force a link down visible on the other side */
1425 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1426 spin_unlock_bh(&bp->phy_lock);
1428 spin_lock_bh(&bp->phy_lock);
1431 bnx2_write_phy(bp, bp->mii_adv, new_adv);
1432 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART |
1434 /* Speed up link-up time when the link partner
1435 * does not autonegotiate which is very common
1436 * in blade servers. Some blade servers use
1437 * IPMI for kerboard input and it's important
1438 * to minimize link disruptions. Autoneg. involves
1439 * exchanging base pages plus 3 next pages and
1440 * normally completes in about 120 msec.
1442 bp->current_interval = SERDES_AN_TIMEOUT;
1443 bp->serdes_an_pending = 1;
1444 mod_timer(&bp->timer, jiffies + bp->current_interval);
1446 bnx2_resolve_flow_ctrl(bp);
1447 bnx2_set_mac_link(bp);
1453 #define ETHTOOL_ALL_FIBRE_SPEED \
1454 (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ? \
1455 (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\
1456 (ADVERTISED_1000baseT_Full)
1458 #define ETHTOOL_ALL_COPPER_SPEED \
1459 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
1460 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
1461 ADVERTISED_1000baseT_Full)
1463 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1464 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1466 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1469 bnx2_set_default_remote_link(struct bnx2 *bp)
1473 if (bp->phy_port == PORT_TP)
1474 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_COPPER_LINK);
1476 link = REG_RD_IND(bp, bp->shmem_base + BNX2_RPHY_SERDES_LINK);
1478 if (link & BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG) {
1479 bp->req_line_speed = 0;
1480 bp->autoneg |= AUTONEG_SPEED;
1481 bp->advertising = ADVERTISED_Autoneg;
1482 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1483 bp->advertising |= ADVERTISED_10baseT_Half;
1484 if (link & BNX2_NETLINK_SET_LINK_SPEED_10FULL)
1485 bp->advertising |= ADVERTISED_10baseT_Full;
1486 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1487 bp->advertising |= ADVERTISED_100baseT_Half;
1488 if (link & BNX2_NETLINK_SET_LINK_SPEED_100FULL)
1489 bp->advertising |= ADVERTISED_100baseT_Full;
1490 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1491 bp->advertising |= ADVERTISED_1000baseT_Full;
1492 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1493 bp->advertising |= ADVERTISED_2500baseX_Full;
1496 bp->advertising = 0;
1497 bp->req_duplex = DUPLEX_FULL;
1498 if (link & BNX2_NETLINK_SET_LINK_SPEED_10) {
1499 bp->req_line_speed = SPEED_10;
1500 if (link & BNX2_NETLINK_SET_LINK_SPEED_10HALF)
1501 bp->req_duplex = DUPLEX_HALF;
1503 if (link & BNX2_NETLINK_SET_LINK_SPEED_100) {
1504 bp->req_line_speed = SPEED_100;
1505 if (link & BNX2_NETLINK_SET_LINK_SPEED_100HALF)
1506 bp->req_duplex = DUPLEX_HALF;
1508 if (link & BNX2_NETLINK_SET_LINK_SPEED_1GFULL)
1509 bp->req_line_speed = SPEED_1000;
1510 if (link & BNX2_NETLINK_SET_LINK_SPEED_2G5FULL)
1511 bp->req_line_speed = SPEED_2500;
1516 bnx2_set_default_link(struct bnx2 *bp)
1518 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1519 return bnx2_set_default_remote_link(bp);
1521 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
1522 bp->req_line_speed = 0;
1523 if (bp->phy_flags & PHY_SERDES_FLAG) {
1526 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
1528 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
1529 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
1530 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
1532 bp->req_line_speed = bp->line_speed = SPEED_1000;
1533 bp->req_duplex = DUPLEX_FULL;
1536 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
1540 bnx2_send_heart_beat(struct bnx2 *bp)
1545 spin_lock(&bp->indirect_lock);
1546 msg = (u32) (++bp->fw_drv_pulse_wr_seq & BNX2_DRV_PULSE_SEQ_MASK);
1547 addr = bp->shmem_base + BNX2_DRV_PULSE_MB;
1548 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, addr);
1549 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, msg);
1550 spin_unlock(&bp->indirect_lock);
1554 bnx2_remote_phy_event(struct bnx2 *bp)
1557 u8 link_up = bp->link_up;
1560 msg = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
1562 if (msg & BNX2_LINK_STATUS_HEART_BEAT_EXPIRED)
1563 bnx2_send_heart_beat(bp);
1565 msg &= ~BNX2_LINK_STATUS_HEART_BEAT_EXPIRED;
1567 if ((msg & BNX2_LINK_STATUS_LINK_UP) == BNX2_LINK_STATUS_LINK_DOWN)
1573 speed = msg & BNX2_LINK_STATUS_SPEED_MASK;
1574 bp->duplex = DUPLEX_FULL;
1576 case BNX2_LINK_STATUS_10HALF:
1577 bp->duplex = DUPLEX_HALF;
1578 case BNX2_LINK_STATUS_10FULL:
1579 bp->line_speed = SPEED_10;
1581 case BNX2_LINK_STATUS_100HALF:
1582 bp->duplex = DUPLEX_HALF;
1583 case BNX2_LINK_STATUS_100BASE_T4:
1584 case BNX2_LINK_STATUS_100FULL:
1585 bp->line_speed = SPEED_100;
1587 case BNX2_LINK_STATUS_1000HALF:
1588 bp->duplex = DUPLEX_HALF;
1589 case BNX2_LINK_STATUS_1000FULL:
1590 bp->line_speed = SPEED_1000;
1592 case BNX2_LINK_STATUS_2500HALF:
1593 bp->duplex = DUPLEX_HALF;
1594 case BNX2_LINK_STATUS_2500FULL:
1595 bp->line_speed = SPEED_2500;
1602 spin_lock(&bp->phy_lock);
1604 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
1605 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
1606 if (bp->duplex == DUPLEX_FULL)
1607 bp->flow_ctrl = bp->req_flow_ctrl;
1609 if (msg & BNX2_LINK_STATUS_TX_FC_ENABLED)
1610 bp->flow_ctrl |= FLOW_CTRL_TX;
1611 if (msg & BNX2_LINK_STATUS_RX_FC_ENABLED)
1612 bp->flow_ctrl |= FLOW_CTRL_RX;
1615 old_port = bp->phy_port;
1616 if (msg & BNX2_LINK_STATUS_SERDES_LINK)
1617 bp->phy_port = PORT_FIBRE;
1619 bp->phy_port = PORT_TP;
1621 if (old_port != bp->phy_port)
1622 bnx2_set_default_link(bp);
1624 spin_unlock(&bp->phy_lock);
1626 if (bp->link_up != link_up)
1627 bnx2_report_link(bp);
1629 bnx2_set_mac_link(bp);
1633 bnx2_set_remote_link(struct bnx2 *bp)
1637 evt_code = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_EVT_CODE_MB);
1639 case BNX2_FW_EVT_CODE_LINK_EVENT:
1640 bnx2_remote_phy_event(bp);
1642 case BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT:
1644 bnx2_send_heart_beat(bp);
1651 bnx2_setup_copper_phy(struct bnx2 *bp)
1656 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1658 if (bp->autoneg & AUTONEG_SPEED) {
1659 u32 adv_reg, adv1000_reg;
1660 u32 new_adv_reg = 0;
1661 u32 new_adv1000_reg = 0;
1663 bnx2_read_phy(bp, bp->mii_adv, &adv_reg);
1664 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1665 ADVERTISE_PAUSE_ASYM);
1667 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1668 adv1000_reg &= PHY_ALL_1000_SPEED;
1670 if (bp->advertising & ADVERTISED_10baseT_Half)
1671 new_adv_reg |= ADVERTISE_10HALF;
1672 if (bp->advertising & ADVERTISED_10baseT_Full)
1673 new_adv_reg |= ADVERTISE_10FULL;
1674 if (bp->advertising & ADVERTISED_100baseT_Half)
1675 new_adv_reg |= ADVERTISE_100HALF;
1676 if (bp->advertising & ADVERTISED_100baseT_Full)
1677 new_adv_reg |= ADVERTISE_100FULL;
1678 if (bp->advertising & ADVERTISED_1000baseT_Full)
1679 new_adv1000_reg |= ADVERTISE_1000FULL;
1681 new_adv_reg |= ADVERTISE_CSMA;
1683 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1685 if ((adv1000_reg != new_adv1000_reg) ||
1686 (adv_reg != new_adv_reg) ||
1687 ((bmcr & BMCR_ANENABLE) == 0)) {
1689 bnx2_write_phy(bp, bp->mii_adv, new_adv_reg);
1690 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1691 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_ANRESTART |
1694 else if (bp->link_up) {
1695 /* Flow ctrl may have changed from auto to forced */
1696 /* or vice-versa. */
1698 bnx2_resolve_flow_ctrl(bp);
1699 bnx2_set_mac_link(bp);
1705 if (bp->req_line_speed == SPEED_100) {
1706 new_bmcr |= BMCR_SPEED100;
1708 if (bp->req_duplex == DUPLEX_FULL) {
1709 new_bmcr |= BMCR_FULLDPLX;
1711 if (new_bmcr != bmcr) {
1714 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1715 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1717 if (bmsr & BMSR_LSTATUS) {
1718 /* Force link down */
1719 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
1720 spin_unlock_bh(&bp->phy_lock);
1722 spin_lock_bh(&bp->phy_lock);
1724 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1725 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr);
1728 bnx2_write_phy(bp, bp->mii_bmcr, new_bmcr);
1730 /* Normally, the new speed is setup after the link has
1731 * gone down and up again. In some cases, link will not go
1732 * down so we need to set up the new speed here.
1734 if (bmsr & BMSR_LSTATUS) {
1735 bp->line_speed = bp->req_line_speed;
1736 bp->duplex = bp->req_duplex;
1737 bnx2_resolve_flow_ctrl(bp);
1738 bnx2_set_mac_link(bp);
1741 bnx2_resolve_flow_ctrl(bp);
1742 bnx2_set_mac_link(bp);
1748 bnx2_setup_phy(struct bnx2 *bp, u8 port)
1750 if (bp->loopback == MAC_LOOPBACK)
1753 if (bp->phy_flags & PHY_SERDES_FLAG) {
1754 return (bnx2_setup_serdes_phy(bp, port));
1757 return (bnx2_setup_copper_phy(bp));
1762 bnx2_init_5709s_phy(struct bnx2 *bp)
1766 bp->mii_bmcr = MII_BMCR + 0x10;
1767 bp->mii_bmsr = MII_BMSR + 0x10;
1768 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1769 bp->mii_adv = MII_ADVERTISE + 0x10;
1770 bp->mii_lpa = MII_LPA + 0x10;
1771 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1773 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1774 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1776 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1779 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1781 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1782 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1783 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1784 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1786 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1787 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
1788 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
1789 val |= BCM5708S_UP1_2G5;
1791 val &= ~BCM5708S_UP1_2G5;
1792 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1794 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1795 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1796 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1797 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1799 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1801 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1802 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1803 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1805 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1811 bnx2_init_5708s_phy(struct bnx2 *bp)
1817 bp->mii_up1 = BCM5708S_UP1;
1819 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1820 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1821 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1823 bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1824 val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1825 bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1827 bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1828 val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1829 bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1831 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1832 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1833 val |= BCM5708S_UP1_2G5;
1834 bnx2_write_phy(bp, BCM5708S_UP1, val);
1837 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1838 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1839 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1840 /* increase tx signal amplitude */
1841 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1842 BCM5708S_BLK_ADDR_TX_MISC);
1843 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1844 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1845 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1846 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1849 val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1850 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1855 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1856 BNX2_SHARED_HW_CFG_CONFIG);
1857 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1858 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1859 BCM5708S_BLK_ADDR_TX_MISC);
1860 bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1861 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1862 BCM5708S_BLK_ADDR_DIG);
1869 bnx2_init_5706s_phy(struct bnx2 *bp)
1873 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1875 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1876 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
1878 if (bp->dev->mtu > 1500) {
1881 /* Set extended packet length bit */
1882 bnx2_write_phy(bp, 0x18, 0x7);
1883 bnx2_read_phy(bp, 0x18, &val);
1884 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1886 bnx2_write_phy(bp, 0x1c, 0x6c00);
1887 bnx2_read_phy(bp, 0x1c, &val);
1888 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1893 bnx2_write_phy(bp, 0x18, 0x7);
1894 bnx2_read_phy(bp, 0x18, &val);
1895 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1897 bnx2_write_phy(bp, 0x1c, 0x6c00);
1898 bnx2_read_phy(bp, 0x1c, &val);
1899 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1906 bnx2_init_copper_phy(struct bnx2 *bp)
1912 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1913 bnx2_write_phy(bp, 0x18, 0x0c00);
1914 bnx2_write_phy(bp, 0x17, 0x000a);
1915 bnx2_write_phy(bp, 0x15, 0x310b);
1916 bnx2_write_phy(bp, 0x17, 0x201f);
1917 bnx2_write_phy(bp, 0x15, 0x9506);
1918 bnx2_write_phy(bp, 0x17, 0x401f);
1919 bnx2_write_phy(bp, 0x15, 0x14e2);
1920 bnx2_write_phy(bp, 0x18, 0x0400);
1923 if (bp->phy_flags & PHY_DIS_EARLY_DAC_FLAG) {
1924 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
1925 MII_BNX2_DSP_EXPAND_REG | 0x8);
1926 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1928 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
1931 if (bp->dev->mtu > 1500) {
1932 /* Set extended packet length bit */
1933 bnx2_write_phy(bp, 0x18, 0x7);
1934 bnx2_read_phy(bp, 0x18, &val);
1935 bnx2_write_phy(bp, 0x18, val | 0x4000);
1937 bnx2_read_phy(bp, 0x10, &val);
1938 bnx2_write_phy(bp, 0x10, val | 0x1);
1941 bnx2_write_phy(bp, 0x18, 0x7);
1942 bnx2_read_phy(bp, 0x18, &val);
1943 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1945 bnx2_read_phy(bp, 0x10, &val);
1946 bnx2_write_phy(bp, 0x10, val & ~0x1);
1949 /* ethernet@wirespeed */
1950 bnx2_write_phy(bp, 0x18, 0x7007);
1951 bnx2_read_phy(bp, 0x18, &val);
1952 bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1958 bnx2_init_phy(struct bnx2 *bp)
1963 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1964 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1966 bp->mii_bmcr = MII_BMCR;
1967 bp->mii_bmsr = MII_BMSR;
1968 bp->mii_bmsr1 = MII_BMSR;
1969 bp->mii_adv = MII_ADVERTISE;
1970 bp->mii_lpa = MII_LPA;
1972 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1974 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
1977 bnx2_read_phy(bp, MII_PHYSID1, &val);
1978 bp->phy_id = val << 16;
1979 bnx2_read_phy(bp, MII_PHYSID2, &val);
1980 bp->phy_id |= val & 0xffff;
1982 if (bp->phy_flags & PHY_SERDES_FLAG) {
1983 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1984 rc = bnx2_init_5706s_phy(bp);
1985 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1986 rc = bnx2_init_5708s_phy(bp);
1987 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1988 rc = bnx2_init_5709s_phy(bp);
1991 rc = bnx2_init_copper_phy(bp);
1996 rc = bnx2_setup_phy(bp, bp->phy_port);
2002 bnx2_set_mac_loopback(struct bnx2 *bp)
2006 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2007 mac_mode &= ~BNX2_EMAC_MODE_PORT;
2008 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
2009 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2014 static int bnx2_test_link(struct bnx2 *);
2017 bnx2_set_phy_loopback(struct bnx2 *bp)
2022 spin_lock_bh(&bp->phy_lock);
2023 rc = bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK | BMCR_FULLDPLX |
2025 spin_unlock_bh(&bp->phy_lock);
2029 for (i = 0; i < 10; i++) {
2030 if (bnx2_test_link(bp) == 0)
2035 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
2036 mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
2037 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
2038 BNX2_EMAC_MODE_25G_MODE);
2040 mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
2041 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
2047 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
2053 msg_data |= bp->fw_wr_seq;
2055 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
2057 /* wait for an acknowledgement. */
2058 for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
2061 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
2063 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
2066 if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
2069 /* If we timed out, inform the firmware that this is the case. */
2070 if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
2072 printk(KERN_ERR PFX "fw sync timeout, reset code = "
2075 msg_data &= ~BNX2_DRV_MSG_CODE;
2076 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
2078 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
2083 if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
2090 bnx2_init_5709_context(struct bnx2 *bp)
2095 val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
2096 val |= (BCM_PAGE_BITS - 8) << 16;
2097 REG_WR(bp, BNX2_CTX_COMMAND, val);
2098 for (i = 0; i < 10; i++) {
2099 val = REG_RD(bp, BNX2_CTX_COMMAND);
2100 if (!(val & BNX2_CTX_COMMAND_MEM_INIT))
2104 if (val & BNX2_CTX_COMMAND_MEM_INIT)
2107 for (i = 0; i < bp->ctx_pages; i++) {
2110 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
2111 (bp->ctx_blk_mapping[i] & 0xffffffff) |
2112 BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
2113 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
2114 (u64) bp->ctx_blk_mapping[i] >> 32);
2115 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
2116 BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
2117 for (j = 0; j < 10; j++) {
2119 val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
2120 if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
2124 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
2133 bnx2_init_context(struct bnx2 *bp)
2139 u32 vcid_addr, pcid_addr, offset;
2144 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2147 vcid_addr = GET_PCID_ADDR(vcid);
2149 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
2154 pcid_addr = GET_PCID_ADDR(new_vcid);
2157 vcid_addr = GET_CID_ADDR(vcid);
2158 pcid_addr = vcid_addr;
2161 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
2162 vcid_addr += (i << PHY_CTX_SHIFT);
2163 pcid_addr += (i << PHY_CTX_SHIFT);
2165 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
2166 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
2168 /* Zero out the context. */
2169 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
2170 CTX_WR(bp, vcid_addr, offset, 0);
2176 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
2182 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
2183 if (good_mbuf == NULL) {
2184 printk(KERN_ERR PFX "Failed to allocate memory in "
2185 "bnx2_alloc_bad_rbuf\n");
2189 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2190 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
2194 /* Allocate a bunch of mbufs and save the good ones in an array. */
2195 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2196 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
2197 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
2199 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
2201 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
2203 /* The addresses with Bit 9 set are bad memory blocks. */
2204 if (!(val & (1 << 9))) {
2205 good_mbuf[good_mbuf_cnt] = (u16) val;
2209 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
2212 /* Free the good ones back to the mbuf pool thus discarding
2213 * all the bad ones. */
2214 while (good_mbuf_cnt) {
2217 val = good_mbuf[good_mbuf_cnt];
2218 val = (val << 9) | val | 1;
2220 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
2227 bnx2_set_mac_addr(struct bnx2 *bp)
2230 u8 *mac_addr = bp->dev->dev_addr;
2232 val = (mac_addr[0] << 8) | mac_addr[1];
2234 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
2236 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
2237 (mac_addr[4] << 8) | mac_addr[5];
2239 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
2243 bnx2_alloc_rx_page(struct bnx2 *bp, u16 index)
2246 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2247 struct rx_bd *rxbd =
2248 &bp->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
2249 struct page *page = alloc_page(GFP_ATOMIC);
2253 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2254 PCI_DMA_FROMDEVICE);
2256 pci_unmap_addr_set(rx_pg, mapping, mapping);
2257 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2258 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2263 bnx2_free_rx_page(struct bnx2 *bp, u16 index)
2265 struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
2266 struct page *page = rx_pg->page;
2271 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
2272 PCI_DMA_FROMDEVICE);
2279 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
2281 struct sk_buff *skb;
2282 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
2284 struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
2285 unsigned long align;
2287 skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
2292 if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
2293 skb_reserve(skb, BNX2_RX_ALIGN - align);
2295 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
2296 PCI_DMA_FROMDEVICE);
2299 pci_unmap_addr_set(rx_buf, mapping, mapping);
2301 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
2302 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
2304 bp->rx_prod_bseq += bp->rx_buf_use_size;
2310 bnx2_phy_event_is_set(struct bnx2 *bp, struct bnx2_napi *bnapi, u32 event)
2312 struct status_block *sblk = bnapi->status_blk;
2313 u32 new_link_state, old_link_state;
2316 new_link_state = sblk->status_attn_bits & event;
2317 old_link_state = sblk->status_attn_bits_ack & event;
2318 if (new_link_state != old_link_state) {
2320 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD, event);
2322 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD, event);
2330 bnx2_phy_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2332 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_LINK_STATE)) {
2333 spin_lock(&bp->phy_lock);
2335 spin_unlock(&bp->phy_lock);
2337 if (bnx2_phy_event_is_set(bp, bnapi, STATUS_ATTN_BITS_TIMER_ABORT))
2338 bnx2_set_remote_link(bp);
2343 bnx2_get_hw_tx_cons(struct bnx2_napi *bnapi)
2347 cons = bnapi->status_blk->status_tx_quick_consumer_index0;
2349 if (unlikely((cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT))
2355 bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi)
2357 u16 hw_cons, sw_cons, sw_ring_cons;
2360 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2361 sw_cons = bnapi->tx_cons;
2363 while (sw_cons != hw_cons) {
2364 struct sw_bd *tx_buf;
2365 struct sk_buff *skb;
2368 sw_ring_cons = TX_RING_IDX(sw_cons);
2370 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
2373 /* partial BD completions possible with TSO packets */
2374 if (skb_is_gso(skb)) {
2375 u16 last_idx, last_ring_idx;
2377 last_idx = sw_cons +
2378 skb_shinfo(skb)->nr_frags + 1;
2379 last_ring_idx = sw_ring_cons +
2380 skb_shinfo(skb)->nr_frags + 1;
2381 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
2384 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
2389 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
2390 skb_headlen(skb), PCI_DMA_TODEVICE);
2393 last = skb_shinfo(skb)->nr_frags;
2395 for (i = 0; i < last; i++) {
2396 sw_cons = NEXT_TX_BD(sw_cons);
2398 pci_unmap_page(bp->pdev,
2400 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
2402 skb_shinfo(skb)->frags[i].size,
2406 sw_cons = NEXT_TX_BD(sw_cons);
2408 tx_free_bd += last + 1;
2412 hw_cons = bnx2_get_hw_tx_cons(bnapi);
2415 bnapi->hw_tx_cons = hw_cons;
2416 bnapi->tx_cons = sw_cons;
2417 /* Need to make the tx_cons update visible to bnx2_start_xmit()
2418 * before checking for netif_queue_stopped(). Without the
2419 * memory barrier, there is a small possibility that bnx2_start_xmit()
2420 * will miss it and cause the queue to be stopped forever.
2424 if (unlikely(netif_queue_stopped(bp->dev)) &&
2425 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)) {
2426 netif_tx_lock(bp->dev);
2427 if ((netif_queue_stopped(bp->dev)) &&
2428 (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh))
2429 netif_wake_queue(bp->dev);
2430 netif_tx_unlock(bp->dev);
2435 bnx2_reuse_rx_skb_pages(struct bnx2 *bp, struct sk_buff *skb, int count)
2437 struct sw_pg *cons_rx_pg, *prod_rx_pg;
2438 struct rx_bd *cons_bd, *prod_bd;
2441 u16 hw_prod = bp->rx_pg_prod, prod;
2442 u16 cons = bp->rx_pg_cons;
2444 for (i = 0; i < count; i++) {
2445 prod = RX_PG_RING_IDX(hw_prod);
2447 prod_rx_pg = &bp->rx_pg_ring[prod];
2448 cons_rx_pg = &bp->rx_pg_ring[cons];
2449 cons_bd = &bp->rx_pg_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2450 prod_bd = &bp->rx_pg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2452 if (i == 0 && skb) {
2454 struct skb_shared_info *shinfo;
2456 shinfo = skb_shinfo(skb);
2458 page = shinfo->frags[shinfo->nr_frags].page;
2459 shinfo->frags[shinfo->nr_frags].page = NULL;
2460 mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
2461 PCI_DMA_FROMDEVICE);
2462 cons_rx_pg->page = page;
2463 pci_unmap_addr_set(cons_rx_pg, mapping, mapping);
2467 prod_rx_pg->page = cons_rx_pg->page;
2468 cons_rx_pg->page = NULL;
2469 pci_unmap_addr_set(prod_rx_pg, mapping,
2470 pci_unmap_addr(cons_rx_pg, mapping));
2472 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2473 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2476 cons = RX_PG_RING_IDX(NEXT_RX_BD(cons));
2477 hw_prod = NEXT_RX_BD(hw_prod);
2479 bp->rx_pg_prod = hw_prod;
2480 bp->rx_pg_cons = cons;
2484 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
2487 struct sw_bd *cons_rx_buf, *prod_rx_buf;
2488 struct rx_bd *cons_bd, *prod_bd;
2490 cons_rx_buf = &bp->rx_buf_ring[cons];
2491 prod_rx_buf = &bp->rx_buf_ring[prod];
2493 pci_dma_sync_single_for_device(bp->pdev,
2494 pci_unmap_addr(cons_rx_buf, mapping),
2495 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2497 bp->rx_prod_bseq += bp->rx_buf_use_size;
2499 prod_rx_buf->skb = skb;
2504 pci_unmap_addr_set(prod_rx_buf, mapping,
2505 pci_unmap_addr(cons_rx_buf, mapping));
2507 cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
2508 prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
2509 prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
2510 prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
2514 bnx2_rx_skb(struct bnx2 *bp, struct sk_buff *skb, unsigned int len,
2515 unsigned int hdr_len, dma_addr_t dma_addr, u32 ring_idx)
2518 u16 prod = ring_idx & 0xffff;
2520 err = bnx2_alloc_rx_skb(bp, prod);
2521 if (unlikely(err)) {
2522 bnx2_reuse_rx_skb(bp, skb, (u16) (ring_idx >> 16), prod);
2524 unsigned int raw_len = len + 4;
2525 int pages = PAGE_ALIGN(raw_len - hdr_len) >> PAGE_SHIFT;
2527 bnx2_reuse_rx_skb_pages(bp, NULL, pages);
2532 skb_reserve(skb, bp->rx_offset);
2533 pci_unmap_single(bp->pdev, dma_addr, bp->rx_buf_use_size,
2534 PCI_DMA_FROMDEVICE);
2540 unsigned int i, frag_len, frag_size, pages;
2541 struct sw_pg *rx_pg;
2542 u16 pg_cons = bp->rx_pg_cons;
2543 u16 pg_prod = bp->rx_pg_prod;
2545 frag_size = len + 4 - hdr_len;
2546 pages = PAGE_ALIGN(frag_size) >> PAGE_SHIFT;
2547 skb_put(skb, hdr_len);
2549 for (i = 0; i < pages; i++) {
2550 frag_len = min(frag_size, (unsigned int) PAGE_SIZE);
2551 if (unlikely(frag_len <= 4)) {
2552 unsigned int tail = 4 - frag_len;
2554 bp->rx_pg_cons = pg_cons;
2555 bp->rx_pg_prod = pg_prod;
2556 bnx2_reuse_rx_skb_pages(bp, NULL, pages - i);
2562 &skb_shinfo(skb)->frags[i - 1];
2564 skb->data_len -= tail;
2565 skb->truesize -= tail;
2569 rx_pg = &bp->rx_pg_ring[pg_cons];
2571 pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping),
2572 PAGE_SIZE, PCI_DMA_FROMDEVICE);
2577 skb_fill_page_desc(skb, i, rx_pg->page, 0, frag_len);
2580 err = bnx2_alloc_rx_page(bp, RX_PG_RING_IDX(pg_prod));
2581 if (unlikely(err)) {
2582 bp->rx_pg_cons = pg_cons;
2583 bp->rx_pg_prod = pg_prod;
2584 bnx2_reuse_rx_skb_pages(bp, skb, pages - i);
2588 frag_size -= frag_len;
2589 skb->data_len += frag_len;
2590 skb->truesize += frag_len;
2591 skb->len += frag_len;
2593 pg_prod = NEXT_RX_BD(pg_prod);
2594 pg_cons = RX_PG_RING_IDX(NEXT_RX_BD(pg_cons));
2596 bp->rx_pg_prod = pg_prod;
2597 bp->rx_pg_cons = pg_cons;
2603 bnx2_get_hw_rx_cons(struct bnx2_napi *bnapi)
2605 u16 cons = bnapi->status_blk->status_rx_quick_consumer_index0;
2607 if (unlikely((cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT))
2613 bnx2_rx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget)
2615 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
2616 struct l2_fhdr *rx_hdr;
2617 int rx_pkt = 0, pg_ring_used = 0;
2619 hw_cons = bnx2_get_hw_rx_cons(bnapi);
2620 sw_cons = bp->rx_cons;
2621 sw_prod = bp->rx_prod;
2623 /* Memory barrier necessary as speculative reads of the rx
2624 * buffer can be ahead of the index in the status block
2627 while (sw_cons != hw_cons) {
2628 unsigned int len, hdr_len;
2630 struct sw_bd *rx_buf;
2631 struct sk_buff *skb;
2632 dma_addr_t dma_addr;
2634 sw_ring_cons = RX_RING_IDX(sw_cons);
2635 sw_ring_prod = RX_RING_IDX(sw_prod);
2637 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
2642 dma_addr = pci_unmap_addr(rx_buf, mapping);
2644 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
2645 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
2647 rx_hdr = (struct l2_fhdr *) skb->data;
2648 len = rx_hdr->l2_fhdr_pkt_len;
2650 if ((status = rx_hdr->l2_fhdr_status) &
2651 (L2_FHDR_ERRORS_BAD_CRC |
2652 L2_FHDR_ERRORS_PHY_DECODE |
2653 L2_FHDR_ERRORS_ALIGNMENT |
2654 L2_FHDR_ERRORS_TOO_SHORT |
2655 L2_FHDR_ERRORS_GIANT_FRAME)) {
2657 bnx2_reuse_rx_skb(bp, skb, sw_ring_cons, sw_ring_prod);
2661 if (status & L2_FHDR_STATUS_SPLIT) {
2662 hdr_len = rx_hdr->l2_fhdr_ip_xsum;
2664 } else if (len > bp->rx_jumbo_thresh) {
2665 hdr_len = bp->rx_jumbo_thresh;
2671 if (len <= bp->rx_copy_thresh) {
2672 struct sk_buff *new_skb;
2674 new_skb = netdev_alloc_skb(bp->dev, len + 2);
2675 if (new_skb == NULL) {
2676 bnx2_reuse_rx_skb(bp, skb, sw_ring_cons,
2682 skb_copy_from_linear_data_offset(skb, bp->rx_offset - 2,
2683 new_skb->data, len + 2);
2684 skb_reserve(new_skb, 2);
2685 skb_put(new_skb, len);
2687 bnx2_reuse_rx_skb(bp, skb,
2688 sw_ring_cons, sw_ring_prod);
2691 } else if (unlikely(bnx2_rx_skb(bp, skb, len, hdr_len, dma_addr,
2692 (sw_ring_cons << 16) | sw_ring_prod)))
2695 skb->protocol = eth_type_trans(skb, bp->dev);
2697 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
2698 (ntohs(skb->protocol) != 0x8100)) {
2705 skb->ip_summed = CHECKSUM_NONE;
2707 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
2708 L2_FHDR_STATUS_UDP_DATAGRAM))) {
2710 if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
2711 L2_FHDR_ERRORS_UDP_XSUM)) == 0))
2712 skb->ip_summed = CHECKSUM_UNNECESSARY;
2716 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
2717 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
2718 rx_hdr->l2_fhdr_vlan_tag);
2722 netif_receive_skb(skb);
2724 bp->dev->last_rx = jiffies;
2728 sw_cons = NEXT_RX_BD(sw_cons);
2729 sw_prod = NEXT_RX_BD(sw_prod);
2731 if ((rx_pkt == budget))
2734 /* Refresh hw_cons to see if there is new work */
2735 if (sw_cons == hw_cons) {
2736 hw_cons = bnx2_get_hw_rx_cons(bnapi);
2740 bp->rx_cons = sw_cons;
2741 bp->rx_prod = sw_prod;
2744 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX,
2747 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
2749 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
2757 /* MSI ISR - The only difference between this and the INTx ISR
2758 * is that the MSI interrupt is always serviced.
2761 bnx2_msi(int irq, void *dev_instance)
2763 struct net_device *dev = dev_instance;
2764 struct bnx2 *bp = netdev_priv(dev);
2765 struct bnx2_napi *bnapi = &bp->bnx2_napi;
2767 prefetch(bnapi->status_blk);
2768 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2769 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2770 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2772 /* Return here if interrupt is disabled. */
2773 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2776 netif_rx_schedule(dev, &bnapi->napi);
2782 bnx2_msi_1shot(int irq, void *dev_instance)
2784 struct net_device *dev = dev_instance;
2785 struct bnx2 *bp = netdev_priv(dev);
2786 struct bnx2_napi *bnapi = &bp->bnx2_napi;
2788 prefetch(bnapi->status_blk);
2790 /* Return here if interrupt is disabled. */
2791 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2794 netif_rx_schedule(dev, &bnapi->napi);
2800 bnx2_interrupt(int irq, void *dev_instance)
2802 struct net_device *dev = dev_instance;
2803 struct bnx2 *bp = netdev_priv(dev);
2804 struct bnx2_napi *bnapi = &bp->bnx2_napi;
2805 struct status_block *sblk = bnapi->status_blk;
2807 /* When using INTx, it is possible for the interrupt to arrive
2808 * at the CPU before the status block posted prior to the
2809 * interrupt. Reading a register will flush the status block.
2810 * When using MSI, the MSI message will always complete after
2811 * the status block write.
2813 if ((sblk->status_idx == bnapi->last_status_idx) &&
2814 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2815 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
2818 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2819 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2820 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2822 /* Read back to deassert IRQ immediately to avoid too many
2823 * spurious interrupts.
2825 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
2827 /* Return here if interrupt is shared and is disabled. */
2828 if (unlikely(atomic_read(&bp->intr_sem) != 0))
2831 if (netif_rx_schedule_prep(dev, &bnapi->napi)) {
2832 bnapi->last_status_idx = sblk->status_idx;
2833 __netif_rx_schedule(dev, &bnapi->napi);
2839 #define STATUS_ATTN_EVENTS (STATUS_ATTN_BITS_LINK_STATE | \
2840 STATUS_ATTN_BITS_TIMER_ABORT)
2843 bnx2_has_work(struct bnx2_napi *bnapi)
2845 struct bnx2 *bp = bnapi->bp;
2846 struct status_block *sblk = bp->status_blk;
2848 if ((bnx2_get_hw_rx_cons(bnapi) != bp->rx_cons) ||
2849 (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons))
2852 if ((sblk->status_attn_bits & STATUS_ATTN_EVENTS) !=
2853 (sblk->status_attn_bits_ack & STATUS_ATTN_EVENTS))
2859 static int bnx2_poll_work(struct bnx2 *bp, struct bnx2_napi *bnapi,
2860 int work_done, int budget)
2862 struct status_block *sblk = bnapi->status_blk;
2863 u32 status_attn_bits = sblk->status_attn_bits;
2864 u32 status_attn_bits_ack = sblk->status_attn_bits_ack;
2866 if ((status_attn_bits & STATUS_ATTN_EVENTS) !=
2867 (status_attn_bits_ack & STATUS_ATTN_EVENTS)) {
2869 bnx2_phy_int(bp, bnapi);
2871 /* This is needed to take care of transient status
2872 * during link changes.
2874 REG_WR(bp, BNX2_HC_COMMAND,
2875 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2876 REG_RD(bp, BNX2_HC_COMMAND);
2879 if (bnx2_get_hw_tx_cons(bnapi) != bnapi->hw_tx_cons)
2880 bnx2_tx_int(bp, bnapi);
2882 if (bnx2_get_hw_rx_cons(bnapi) != bp->rx_cons)
2883 work_done += bnx2_rx_int(bp, bnapi, budget - work_done);
2888 static int bnx2_poll(struct napi_struct *napi, int budget)
2890 struct bnx2_napi *bnapi = container_of(napi, struct bnx2_napi, napi);
2891 struct bnx2 *bp = bnapi->bp;
2893 struct status_block *sblk = bnapi->status_blk;
2896 work_done = bnx2_poll_work(bp, bnapi, work_done, budget);
2898 if (unlikely(work_done >= budget))
2901 /* bnapi->last_status_idx is used below to tell the hw how
2902 * much work has been processed, so we must read it before
2903 * checking for more work.
2905 bnapi->last_status_idx = sblk->status_idx;
2907 if (likely(!bnx2_has_work(bnapi))) {
2908 netif_rx_complete(bp->dev, napi);
2909 if (likely(bp->flags & USING_MSI_FLAG)) {
2910 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2911 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2912 bnapi->last_status_idx);
2915 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2916 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2917 BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2918 bnapi->last_status_idx);
2920 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2921 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2922 bnapi->last_status_idx);
2930 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
2931 * from set_multicast.
2934 bnx2_set_rx_mode(struct net_device *dev)
2936 struct bnx2 *bp = netdev_priv(dev);
2937 u32 rx_mode, sort_mode;
2940 spin_lock_bh(&bp->phy_lock);
2942 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
2943 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
2944 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
2946 if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
2947 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2949 if (!(bp->flags & ASF_ENABLE_FLAG))
2950 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2952 if (dev->flags & IFF_PROMISC) {
2953 /* Promiscuous mode. */
2954 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
2955 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
2956 BNX2_RPM_SORT_USER0_PROM_VLAN;
2958 else if (dev->flags & IFF_ALLMULTI) {
2959 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2960 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2963 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
2966 /* Accept one or more multicast(s). */
2967 struct dev_mc_list *mclist;
2968 u32 mc_filter[NUM_MC_HASH_REGISTERS];
2973 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
2975 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2976 i++, mclist = mclist->next) {
2978 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
2980 regidx = (bit & 0xe0) >> 5;
2982 mc_filter[regidx] |= (1 << bit);
2985 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2986 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2990 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
2993 if (rx_mode != bp->rx_mode) {
2994 bp->rx_mode = rx_mode;
2995 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
2998 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2999 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
3000 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
3002 spin_unlock_bh(&bp->phy_lock);
3006 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
3013 for (i = 0; i < rv2p_code_len; i += 8) {
3014 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
3016 REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
3019 if (rv2p_proc == RV2P_PROC1) {
3020 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
3021 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
3024 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
3025 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
3029 /* Reset the processor, un-stall is done later. */
3030 if (rv2p_proc == RV2P_PROC1) {
3031 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
3034 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
3039 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
3046 val = REG_RD_IND(bp, cpu_reg->mode);
3047 val |= cpu_reg->mode_value_halt;
3048 REG_WR_IND(bp, cpu_reg->mode, val);
3049 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
3051 /* Load the Text area. */
3052 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3056 rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
3061 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3062 REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
3066 /* Load the Data area. */
3067 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3071 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3072 REG_WR_IND(bp, offset, fw->data[j]);
3076 /* Load the SBSS area. */
3077 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
3081 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3082 REG_WR_IND(bp, offset, 0);
3086 /* Load the BSS area. */
3087 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
3091 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3092 REG_WR_IND(bp, offset, 0);
3096 /* Load the Read-Only area. */
3097 offset = cpu_reg->spad_base +
3098 (fw->rodata_addr - cpu_reg->mips_view_base);
3102 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3103 REG_WR_IND(bp, offset, fw->rodata[j]);
3107 /* Clear the pre-fetch instruction. */
3108 REG_WR_IND(bp, cpu_reg->inst, 0);
3109 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
3111 /* Start the CPU. */
3112 val = REG_RD_IND(bp, cpu_reg->mode);
3113 val &= ~cpu_reg->mode_value_halt;
3114 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
3115 REG_WR_IND(bp, cpu_reg->mode, val);
3121 bnx2_init_cpus(struct bnx2 *bp)
3123 struct cpu_reg cpu_reg;
3128 /* Initialize the RV2P processor. */
3129 text = vmalloc(FW_BUF_SIZE);
3132 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3133 rv2p = bnx2_xi_rv2p_proc1;
3134 rv2p_len = sizeof(bnx2_xi_rv2p_proc1);
3136 rv2p = bnx2_rv2p_proc1;
3137 rv2p_len = sizeof(bnx2_rv2p_proc1);
3139 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3143 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
3145 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3146 rv2p = bnx2_xi_rv2p_proc2;
3147 rv2p_len = sizeof(bnx2_xi_rv2p_proc2);
3149 rv2p = bnx2_rv2p_proc2;
3150 rv2p_len = sizeof(bnx2_rv2p_proc2);
3152 rc = zlib_inflate_blob(text, FW_BUF_SIZE, rv2p, rv2p_len);
3156 load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
3158 /* Initialize the RX Processor. */
3159 cpu_reg.mode = BNX2_RXP_CPU_MODE;
3160 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
3161 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
3162 cpu_reg.state = BNX2_RXP_CPU_STATE;
3163 cpu_reg.state_value_clear = 0xffffff;
3164 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
3165 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
3166 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
3167 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
3168 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
3169 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
3170 cpu_reg.mips_view_base = 0x8000000;
3172 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3173 fw = &bnx2_rxp_fw_09;
3175 fw = &bnx2_rxp_fw_06;
3178 rc = load_cpu_fw(bp, &cpu_reg, fw);
3182 /* Initialize the TX Processor. */
3183 cpu_reg.mode = BNX2_TXP_CPU_MODE;
3184 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
3185 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
3186 cpu_reg.state = BNX2_TXP_CPU_STATE;
3187 cpu_reg.state_value_clear = 0xffffff;
3188 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
3189 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
3190 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
3191 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
3192 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
3193 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
3194 cpu_reg.mips_view_base = 0x8000000;
3196 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3197 fw = &bnx2_txp_fw_09;
3199 fw = &bnx2_txp_fw_06;
3202 rc = load_cpu_fw(bp, &cpu_reg, fw);
3206 /* Initialize the TX Patch-up Processor. */
3207 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
3208 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
3209 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
3210 cpu_reg.state = BNX2_TPAT_CPU_STATE;
3211 cpu_reg.state_value_clear = 0xffffff;
3212 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
3213 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
3214 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
3215 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
3216 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
3217 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
3218 cpu_reg.mips_view_base = 0x8000000;
3220 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3221 fw = &bnx2_tpat_fw_09;
3223 fw = &bnx2_tpat_fw_06;
3226 rc = load_cpu_fw(bp, &cpu_reg, fw);
3230 /* Initialize the Completion Processor. */
3231 cpu_reg.mode = BNX2_COM_CPU_MODE;
3232 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
3233 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
3234 cpu_reg.state = BNX2_COM_CPU_STATE;
3235 cpu_reg.state_value_clear = 0xffffff;
3236 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
3237 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
3238 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
3239 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
3240 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
3241 cpu_reg.spad_base = BNX2_COM_SCRATCH;
3242 cpu_reg.mips_view_base = 0x8000000;
3244 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3245 fw = &bnx2_com_fw_09;
3247 fw = &bnx2_com_fw_06;
3250 rc = load_cpu_fw(bp, &cpu_reg, fw);
3254 /* Initialize the Command Processor. */
3255 cpu_reg.mode = BNX2_CP_CPU_MODE;
3256 cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
3257 cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
3258 cpu_reg.state = BNX2_CP_CPU_STATE;
3259 cpu_reg.state_value_clear = 0xffffff;
3260 cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
3261 cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
3262 cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
3263 cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
3264 cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
3265 cpu_reg.spad_base = BNX2_CP_SCRATCH;
3266 cpu_reg.mips_view_base = 0x8000000;
3268 if (CHIP_NUM(bp) == CHIP_NUM_5709)
3269 fw = &bnx2_cp_fw_09;
3271 fw = &bnx2_cp_fw_06;
3274 rc = load_cpu_fw(bp, &cpu_reg, fw);
3282 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
3286 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
3292 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3293 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
3294 PCI_PM_CTRL_PME_STATUS);
3296 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
3297 /* delay required during transition out of D3hot */
3300 val = REG_RD(bp, BNX2_EMAC_MODE);
3301 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
3302 val &= ~BNX2_EMAC_MODE_MPKT;
3303 REG_WR(bp, BNX2_EMAC_MODE, val);
3305 val = REG_RD(bp, BNX2_RPM_CONFIG);
3306 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3307 REG_WR(bp, BNX2_RPM_CONFIG, val);
3318 autoneg = bp->autoneg;
3319 advertising = bp->advertising;
3321 if (bp->phy_port == PORT_TP) {
3322 bp->autoneg = AUTONEG_SPEED;
3323 bp->advertising = ADVERTISED_10baseT_Half |
3324 ADVERTISED_10baseT_Full |
3325 ADVERTISED_100baseT_Half |
3326 ADVERTISED_100baseT_Full |
3330 spin_lock_bh(&bp->phy_lock);
3331 bnx2_setup_phy(bp, bp->phy_port);
3332 spin_unlock_bh(&bp->phy_lock);
3334 bp->autoneg = autoneg;
3335 bp->advertising = advertising;
3337 bnx2_set_mac_addr(bp);
3339 val = REG_RD(bp, BNX2_EMAC_MODE);
3341 /* Enable port mode. */
3342 val &= ~BNX2_EMAC_MODE_PORT;
3343 val |= BNX2_EMAC_MODE_MPKT_RCVD |
3344 BNX2_EMAC_MODE_ACPI_RCVD |
3345 BNX2_EMAC_MODE_MPKT;
3346 if (bp->phy_port == PORT_TP)
3347 val |= BNX2_EMAC_MODE_PORT_MII;
3349 val |= BNX2_EMAC_MODE_PORT_GMII;
3350 if (bp->line_speed == SPEED_2500)
3351 val |= BNX2_EMAC_MODE_25G_MODE;
3354 REG_WR(bp, BNX2_EMAC_MODE, val);
3356 /* receive all multicast */
3357 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
3358 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
3361 REG_WR(bp, BNX2_EMAC_RX_MODE,
3362 BNX2_EMAC_RX_MODE_SORT_MODE);
3364 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
3365 BNX2_RPM_SORT_USER0_MC_EN;
3366 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
3367 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
3368 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
3369 BNX2_RPM_SORT_USER0_ENA);
3371 /* Need to enable EMAC and RPM for WOL. */
3372 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3373 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
3374 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
3375 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
3377 val = REG_RD(bp, BNX2_RPM_CONFIG);
3378 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
3379 REG_WR(bp, BNX2_RPM_CONFIG, val);
3381 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
3384 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
3387 if (!(bp->flags & NO_WOL_FLAG))
3388 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
3390 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
3391 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3392 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3401 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
3403 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
3406 /* No more memory access after this point until
3407 * device is brought back to D0.
3419 bnx2_acquire_nvram_lock(struct bnx2 *bp)
3424 /* Request access to the flash interface. */
3425 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
3426 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3427 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3428 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
3434 if (j >= NVRAM_TIMEOUT_COUNT)
3441 bnx2_release_nvram_lock(struct bnx2 *bp)
3446 /* Relinquish nvram interface. */
3447 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
3449 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3450 val = REG_RD(bp, BNX2_NVM_SW_ARB);
3451 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
3457 if (j >= NVRAM_TIMEOUT_COUNT)
3465 bnx2_enable_nvram_write(struct bnx2 *bp)
3469 val = REG_RD(bp, BNX2_MISC_CFG);
3470 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
3472 if (bp->flash_info->flags & BNX2_NV_WREN) {
3475 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3476 REG_WR(bp, BNX2_NVM_COMMAND,
3477 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
3479 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3482 val = REG_RD(bp, BNX2_NVM_COMMAND);
3483 if (val & BNX2_NVM_COMMAND_DONE)
3487 if (j >= NVRAM_TIMEOUT_COUNT)
3494 bnx2_disable_nvram_write(struct bnx2 *bp)
3498 val = REG_RD(bp, BNX2_MISC_CFG);
3499 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
3504 bnx2_enable_nvram_access(struct bnx2 *bp)
3508 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3509 /* Enable both bits, even on read. */
3510 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3511 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
3515 bnx2_disable_nvram_access(struct bnx2 *bp)
3519 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
3520 /* Disable both bits, even after read. */
3521 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
3522 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
3523 BNX2_NVM_ACCESS_ENABLE_WR_EN));
3527 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
3532 if (bp->flash_info->flags & BNX2_NV_BUFFERED)
3533 /* Buffered flash, no erase needed */
3536 /* Build an erase command */
3537 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
3538 BNX2_NVM_COMMAND_DOIT;
3540 /* Need to clear DONE bit separately. */
3541 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3543 /* Address of the NVRAM to read from. */
3544 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3546 /* Issue an erase command. */
3547 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3549 /* Wait for completion. */
3550 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3555 val = REG_RD(bp, BNX2_NVM_COMMAND);
3556 if (val & BNX2_NVM_COMMAND_DONE)
3560 if (j >= NVRAM_TIMEOUT_COUNT)
3567 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
3572 /* Build the command word. */
3573 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
3575 /* Calculate an offset of a buffered flash, not needed for 5709. */
3576 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3577 offset = ((offset / bp->flash_info->page_size) <<
3578 bp->flash_info->page_bits) +
3579 (offset % bp->flash_info->page_size);
3582 /* Need to clear DONE bit separately. */
3583 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3585 /* Address of the NVRAM to read from. */
3586 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3588 /* Issue a read command. */
3589 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3591 /* Wait for completion. */
3592 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3597 val = REG_RD(bp, BNX2_NVM_COMMAND);
3598 if (val & BNX2_NVM_COMMAND_DONE) {
3599 val = REG_RD(bp, BNX2_NVM_READ);
3601 val = be32_to_cpu(val);
3602 memcpy(ret_val, &val, 4);
3606 if (j >= NVRAM_TIMEOUT_COUNT)
3614 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
3619 /* Build the command word. */
3620 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
3622 /* Calculate an offset of a buffered flash, not needed for 5709. */
3623 if (bp->flash_info->flags & BNX2_NV_TRANSLATE) {
3624 offset = ((offset / bp->flash_info->page_size) <<
3625 bp->flash_info->page_bits) +
3626 (offset % bp->flash_info->page_size);
3629 /* Need to clear DONE bit separately. */
3630 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
3632 memcpy(&val32, val, 4);
3633 val32 = cpu_to_be32(val32);
3635 /* Write the data. */
3636 REG_WR(bp, BNX2_NVM_WRITE, val32);
3638 /* Address of the NVRAM to write to. */
3639 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
3641 /* Issue the write command. */
3642 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
3644 /* Wait for completion. */
3645 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
3648 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
3651 if (j >= NVRAM_TIMEOUT_COUNT)
3658 bnx2_init_nvram(struct bnx2 *bp)
3661 int j, entry_count, rc = 0;
3662 struct flash_spec *flash;
3664 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3665 bp->flash_info = &flash_5709;
3666 goto get_flash_size;
3669 /* Determine the selected interface. */
3670 val = REG_RD(bp, BNX2_NVM_CFG1);
3672 entry_count = ARRAY_SIZE(flash_table);
3674 if (val & 0x40000000) {
3676 /* Flash interface has been reconfigured */
3677 for (j = 0, flash = &flash_table[0]; j < entry_count;
3679 if ((val & FLASH_BACKUP_STRAP_MASK) ==
3680 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
3681 bp->flash_info = flash;
3688 /* Not yet been reconfigured */
3690 if (val & (1 << 23))
3691 mask = FLASH_BACKUP_STRAP_MASK;
3693 mask = FLASH_STRAP_MASK;
3695 for (j = 0, flash = &flash_table[0]; j < entry_count;
3698 if ((val & mask) == (flash->strapping & mask)) {
3699 bp->flash_info = flash;
3701 /* Request access to the flash interface. */
3702 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3705 /* Enable access to flash interface */
3706 bnx2_enable_nvram_access(bp);
3708 /* Reconfigure the flash interface */
3709 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
3710 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
3711 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
3712 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
3714 /* Disable access to flash interface */
3715 bnx2_disable_nvram_access(bp);
3716 bnx2_release_nvram_lock(bp);
3721 } /* if (val & 0x40000000) */
3723 if (j == entry_count) {
3724 bp->flash_info = NULL;
3725 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
3730 val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
3731 val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
3733 bp->flash_size = val;
3735 bp->flash_size = bp->flash_info->total_size;
3741 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
3745 u32 cmd_flags, offset32, len32, extra;
3750 /* Request access to the flash interface. */
3751 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3754 /* Enable access to flash interface */
3755 bnx2_enable_nvram_access(bp);
3768 pre_len = 4 - (offset & 3);
3770 if (pre_len >= len32) {
3772 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3773 BNX2_NVM_COMMAND_LAST;
3776 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3779 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3784 memcpy(ret_buf, buf + (offset & 3), pre_len);
3791 extra = 4 - (len32 & 3);
3792 len32 = (len32 + 4) & ~3;
3799 cmd_flags = BNX2_NVM_COMMAND_LAST;
3801 cmd_flags = BNX2_NVM_COMMAND_FIRST |
3802 BNX2_NVM_COMMAND_LAST;
3804 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3806 memcpy(ret_buf, buf, 4 - extra);
3808 else if (len32 > 0) {
3811 /* Read the first word. */
3815 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3817 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3819 /* Advance to the next dword. */
3824 while (len32 > 4 && rc == 0) {
3825 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
3827 /* Advance to the next dword. */
3836 cmd_flags = BNX2_NVM_COMMAND_LAST;
3837 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3839 memcpy(ret_buf, buf, 4 - extra);
3842 /* Disable access to flash interface */
3843 bnx2_disable_nvram_access(bp);
3845 bnx2_release_nvram_lock(bp);
3851 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3854 u32 written, offset32, len32;
3855 u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
3857 int align_start, align_end;
3862 align_start = align_end = 0;
3864 if ((align_start = (offset32 & 3))) {
3866 len32 += align_start;
3869 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
3874 align_end = 4 - (len32 & 3);
3876 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4, end, 4)))
3880 if (align_start || align_end) {
3881 align_buf = kmalloc(len32, GFP_KERNEL);
3882 if (align_buf == NULL)
3885 memcpy(align_buf, start, 4);
3888 memcpy(align_buf + len32 - 4, end, 4);
3890 memcpy(align_buf + align_start, data_buf, buf_size);
3894 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3895 flash_buffer = kmalloc(264, GFP_KERNEL);
3896 if (flash_buffer == NULL) {
3898 goto nvram_write_end;
3903 while ((written < len32) && (rc == 0)) {
3904 u32 page_start, page_end, data_start, data_end;
3905 u32 addr, cmd_flags;
3908 /* Find the page_start addr */
3909 page_start = offset32 + written;
3910 page_start -= (page_start % bp->flash_info->page_size);
3911 /* Find the page_end addr */
3912 page_end = page_start + bp->flash_info->page_size;
3913 /* Find the data_start addr */
3914 data_start = (written == 0) ? offset32 : page_start;
3915 /* Find the data_end addr */
3916 data_end = (page_end > offset32 + len32) ?
3917 (offset32 + len32) : page_end;
3919 /* Request access to the flash interface. */
3920 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3921 goto nvram_write_end;
3923 /* Enable access to flash interface */
3924 bnx2_enable_nvram_access(bp);
3926 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3927 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3930 /* Read the whole page into the buffer
3931 * (non-buffer flash only) */
3932 for (j = 0; j < bp->flash_info->page_size; j += 4) {
3933 if (j == (bp->flash_info->page_size - 4)) {
3934 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3936 rc = bnx2_nvram_read_dword(bp,
3942 goto nvram_write_end;
3948 /* Enable writes to flash interface (unlock write-protect) */
3949 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
3950 goto nvram_write_end;
3952 /* Loop to write back the buffer data from page_start to
3955 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3956 /* Erase the page */
3957 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
3958 goto nvram_write_end;
3960 /* Re-enable the write again for the actual write */
3961 bnx2_enable_nvram_write(bp);
3963 for (addr = page_start; addr < data_start;
3964 addr += 4, i += 4) {
3966 rc = bnx2_nvram_write_dword(bp, addr,
3967 &flash_buffer[i], cmd_flags);
3970 goto nvram_write_end;
3976 /* Loop to write the new data from data_start to data_end */
3977 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
3978 if ((addr == page_end - 4) ||
3979 ((bp->flash_info->flags & BNX2_NV_BUFFERED) &&
3980 (addr == data_end - 4))) {
3982 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3984 rc = bnx2_nvram_write_dword(bp, addr, buf,
3988 goto nvram_write_end;
3994 /* Loop to write back the buffer data from data_end
3996 if (!(bp->flash_info->flags & BNX2_NV_BUFFERED)) {
3997 for (addr = data_end; addr < page_end;
3998 addr += 4, i += 4) {
4000 if (addr == page_end-4) {
4001 cmd_flags = BNX2_NVM_COMMAND_LAST;
4003 rc = bnx2_nvram_write_dword(bp, addr,
4004 &flash_buffer[i], cmd_flags);
4007 goto nvram_write_end;
4013 /* Disable writes to flash interface (lock write-protect) */
4014 bnx2_disable_nvram_write(bp);
4016 /* Disable access to flash interface */
4017 bnx2_disable_nvram_access(bp);
4018 bnx2_release_nvram_lock(bp);
4020 /* Increment written */
4021 written += data_end - data_start;
4025 kfree(flash_buffer);
4031 bnx2_init_remote_phy(struct bnx2 *bp)
4035 bp->phy_flags &= ~REMOTE_PHY_CAP_FLAG;
4036 if (!(bp->phy_flags & PHY_SERDES_FLAG))
4039 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_CAP_MB);
4040 if ((val & BNX2_FW_CAP_SIGNATURE_MASK) != BNX2_FW_CAP_SIGNATURE)
4043 if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) {
4044 bp->phy_flags |= REMOTE_PHY_CAP_FLAG;
4046 val = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS);
4047 if (val & BNX2_LINK_STATUS_SERDES_LINK)
4048 bp->phy_port = PORT_FIBRE;
4050 bp->phy_port = PORT_TP;
4052 if (netif_running(bp->dev)) {
4055 if (val & BNX2_LINK_STATUS_LINK_UP) {
4057 netif_carrier_on(bp->dev);
4060 netif_carrier_off(bp->dev);
4062 sig = BNX2_DRV_ACK_CAP_SIGNATURE |
4063 BNX2_FW_CAP_REMOTE_PHY_CAPABLE;
4064 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_ACK_CAP_MB,
4071 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
4077 /* Wait for the current PCI transaction to complete before
4078 * issuing a reset. */
4079 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
4080 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4081 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4082 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4083 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4084 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
4087 /* Wait for the firmware to tell us it is ok to issue a reset. */
4088 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
4090 /* Deposit a driver reset signature so the firmware knows that
4091 * this is a soft reset. */
4092 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
4093 BNX2_DRV_RESET_SIGNATURE_MAGIC);
4095 /* Do a dummy read to force the chip to complete all current transaction
4096 * before we issue a reset. */
4097 val = REG_RD(bp, BNX2_MISC_ID);
4099 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4100 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
4101 REG_RD(bp, BNX2_MISC_COMMAND);
4104 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4105 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4107 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
4110 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4111 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4112 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4115 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
4117 /* Reading back any register after chip reset will hang the
4118 * bus on 5706 A0 and A1. The msleep below provides plenty
4119 * of margin for write posting.
4121 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
4122 (CHIP_ID(bp) == CHIP_ID_5706_A1))
4125 /* Reset takes approximate 30 usec */
4126 for (i = 0; i < 10; i++) {
4127 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
4128 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4129 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
4134 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4135 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4136 printk(KERN_ERR PFX "Chip reset did not complete\n");
4141 /* Make sure byte swapping is properly configured. */
4142 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
4143 if (val != 0x01020304) {
4144 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
4148 /* Wait for the firmware to finish its initialization. */
4149 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
4153 spin_lock_bh(&bp->phy_lock);
4154 old_port = bp->phy_port;
4155 bnx2_init_remote_phy(bp);
4156 if ((bp->phy_flags & REMOTE_PHY_CAP_FLAG) && old_port != bp->phy_port)
4157 bnx2_set_default_remote_link(bp);
4158 spin_unlock_bh(&bp->phy_lock);
4160 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4161 /* Adjust the voltage regular to two steps lower. The default
4162 * of this register is 0x0000000e. */
4163 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
4165 /* Remove bad rbuf memory from the free pool. */
4166 rc = bnx2_alloc_bad_rbuf(bp);
4173 bnx2_init_chip(struct bnx2 *bp)
4178 /* Make sure the interrupt is not active. */
4179 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
4181 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
4182 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
4184 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
4186 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
4187 DMA_READ_CHANS << 12 |
4188 DMA_WRITE_CHANS << 16;
4190 val |= (0x2 << 20) | (1 << 11);
4192 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
4195 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
4196 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
4197 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
4199 REG_WR(bp, BNX2_DMA_CONFIG, val);
4201 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
4202 val = REG_RD(bp, BNX2_TDMA_CONFIG);
4203 val |= BNX2_TDMA_CONFIG_ONE_DMA;
4204 REG_WR(bp, BNX2_TDMA_CONFIG, val);
4207 if (bp->flags & PCIX_FLAG) {
4210 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4212 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
4213 val16 & ~PCI_X_CMD_ERO);
4216 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
4217 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4218 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4219 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4221 /* Initialize context mapping and zero out the quick contexts. The
4222 * context block must have already been enabled. */
4223 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4224 rc = bnx2_init_5709_context(bp);
4228 bnx2_init_context(bp);
4230 if ((rc = bnx2_init_cpus(bp)) != 0)
4233 bnx2_init_nvram(bp);
4235 bnx2_set_mac_addr(bp);
4237 val = REG_RD(bp, BNX2_MQ_CONFIG);
4238 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4239 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4240 if (CHIP_ID(bp) == CHIP_ID_5709_A0 || CHIP_ID(bp) == CHIP_ID_5709_A1)
4241 val |= BNX2_MQ_CONFIG_HALT_DIS;
4243 REG_WR(bp, BNX2_MQ_CONFIG, val);
4245 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4246 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
4247 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
4249 val = (BCM_PAGE_BITS - 8) << 24;
4250 REG_WR(bp, BNX2_RV2P_CONFIG, val);
4252 /* Configure page size. */
4253 val = REG_RD(bp, BNX2_TBDR_CONFIG);
4254 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
4255 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4256 REG_WR(bp, BNX2_TBDR_CONFIG, val);
4258 val = bp->mac_addr[0] +
4259 (bp->mac_addr[1] << 8) +
4260 (bp->mac_addr[2] << 16) +
4262 (bp->mac_addr[4] << 8) +
4263 (bp->mac_addr[5] << 16);
4264 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
4266 /* Program the MTU. Also include 4 bytes for CRC32. */
4267 val = bp->dev->mtu + ETH_HLEN + 4;
4268 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
4269 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
4270 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
4272 bp->bnx2_napi.last_status_idx = 0;
4273 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
4275 /* Set up how to generate a link change interrupt. */
4276 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
4278 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
4279 (u64) bp->status_blk_mapping & 0xffffffff);
4280 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
4282 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
4283 (u64) bp->stats_blk_mapping & 0xffffffff);
4284 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
4285 (u64) bp->stats_blk_mapping >> 32);
4287 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
4288 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
4290 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
4291 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
4293 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
4294 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
4296 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
4298 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
4300 REG_WR(bp, BNX2_HC_COM_TICKS,
4301 (bp->com_ticks_int << 16) | bp->com_ticks);
4303 REG_WR(bp, BNX2_HC_CMD_TICKS,
4304 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
4306 if (CHIP_NUM(bp) == CHIP_NUM_5708)
4307 REG_WR(bp, BNX2_HC_STATS_TICKS, 0);
4309 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks);
4310 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
4312 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
4313 val = BNX2_HC_CONFIG_COLLECT_STATS;
4315 val = BNX2_HC_CONFIG_RX_TMR_MODE | BNX2_HC_CONFIG_TX_TMR_MODE |
4316 BNX2_HC_CONFIG_COLLECT_STATS;
4319 if (bp->flags & ONE_SHOT_MSI_FLAG)
4320 val |= BNX2_HC_CONFIG_ONE_SHOT;
4322 REG_WR(bp, BNX2_HC_CONFIG, val);
4324 /* Clear internal stats counters. */
4325 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
4327 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_EVENTS);
4329 /* Initialize the receive filter. */
4330 bnx2_set_rx_mode(bp->dev);
4332 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4333 val = REG_RD(bp, BNX2_MISC_NEW_CORE_CTL);
4334 val |= BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE;
4335 REG_WR(bp, BNX2_MISC_NEW_CORE_CTL, val);
4337 rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
4340 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, BNX2_MISC_ENABLE_DEFAULT);
4341 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
4345 bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
4351 bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
4353 u32 val, offset0, offset1, offset2, offset3;
4355 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
4356 offset0 = BNX2_L2CTX_TYPE_XI;
4357 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
4358 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
4359 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
4361 offset0 = BNX2_L2CTX_TYPE;
4362 offset1 = BNX2_L2CTX_CMD_TYPE;
4363 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
4364 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
4366 val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
4367 CTX_WR(bp, GET_CID_ADDR(cid), offset0, val);
4369 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4370 CTX_WR(bp, GET_CID_ADDR(cid), offset1, val);
4372 val = (u64) bp->tx_desc_mapping >> 32;
4373 CTX_WR(bp, GET_CID_ADDR(cid), offset2, val);
4375 val = (u64) bp->tx_desc_mapping & 0xffffffff;
4376 CTX_WR(bp, GET_CID_ADDR(cid), offset3, val);
4380 bnx2_init_tx_ring(struct bnx2 *bp)
4384 struct bnx2_napi *bnapi = &bp->bnx2_napi;
4386 bp->tx_wake_thresh = bp->tx_ring_size / 2;
4388 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
4390 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
4391 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
4395 bnapi->hw_tx_cons = 0;
4396 bp->tx_prod_bseq = 0;
4399 bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
4400 bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
4402 bnx2_init_tx_context(bp, cid);
4406 bnx2_init_rxbd_rings(struct rx_bd *rx_ring[], dma_addr_t dma[], u32 buf_size,
4412 for (i = 0; i < num_rings; i++) {
4415 rxbd = &rx_ring[i][0];
4416 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
4417 rxbd->rx_bd_len = buf_size;
4418 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
4420 if (i == (num_rings - 1))
4424 rxbd->rx_bd_haddr_hi = (u64) dma[j] >> 32;
4425 rxbd->rx_bd_haddr_lo = (u64) dma[j] & 0xffffffff;
4430 bnx2_init_rx_ring(struct bnx2 *bp)
4433 u16 prod, ring_prod;
4434 u32 val, rx_cid_addr = GET_CID_ADDR(RX_CID);
4438 bp->rx_prod_bseq = 0;
4442 bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
4443 bp->rx_buf_use_size, bp->rx_max_ring);
4445 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
4446 if (bp->rx_pg_ring_size) {
4447 bnx2_init_rxbd_rings(bp->rx_pg_desc_ring,
4448 bp->rx_pg_desc_mapping,
4449 PAGE_SIZE, bp->rx_max_pg_ring);
4450 val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
4451 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
4452 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
4453 BNX2_L2CTX_RBDC_JUMBO_KEY);
4455 val = (u64) bp->rx_pg_desc_mapping[0] >> 32;
4456 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
4458 val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff;
4459 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
4461 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4462 REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
4465 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
4466 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
4468 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_CTX_TYPE, val);
4470 val = (u64) bp->rx_desc_mapping[0] >> 32;
4471 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
4473 val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
4474 CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
4476 ring_prod = prod = bp->rx_pg_prod;
4477 for (i = 0; i < bp->rx_pg_ring_size; i++) {
4478 if (bnx2_alloc_rx_page(bp, ring_prod) < 0)
4480 prod = NEXT_RX_BD(prod);
4481 ring_prod = RX_PG_RING_IDX(prod);
4483 bp->rx_pg_prod = prod;
4485 ring_prod = prod = bp->rx_prod;
4486 for (i = 0; i < bp->rx_ring_size; i++) {
4487 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
4490 prod = NEXT_RX_BD(prod);
4491 ring_prod = RX_RING_IDX(prod);
4495 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX, bp->rx_pg_prod);
4496 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
4498 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
4501 static u32 bnx2_find_max_ring(u32 ring_size, u32 max_size)
4503 u32 max, num_rings = 1;
4505 while (ring_size > MAX_RX_DESC_CNT) {
4506 ring_size -= MAX_RX_DESC_CNT;
4509 /* round to next power of 2 */
4511 while ((max & num_rings) == 0)
4514 if (num_rings != max)
4521 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
4523 u32 rx_size, rx_space, jumbo_size;
4525 /* 8 for CRC and VLAN */
4526 rx_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
4528 rx_space = SKB_DATA_ALIGN(rx_size + BNX2_RX_ALIGN) + NET_SKB_PAD +
4529 sizeof(struct skb_shared_info);
4531 bp->rx_copy_thresh = RX_COPY_THRESH;
4532 bp->rx_pg_ring_size = 0;
4533 bp->rx_max_pg_ring = 0;
4534 bp->rx_max_pg_ring_idx = 0;
4535 if (rx_space > PAGE_SIZE) {
4536 int pages = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
4538 jumbo_size = size * pages;
4539 if (jumbo_size > MAX_TOTAL_RX_PG_DESC_CNT)
4540 jumbo_size = MAX_TOTAL_RX_PG_DESC_CNT;
4542 bp->rx_pg_ring_size = jumbo_size;
4543 bp->rx_max_pg_ring = bnx2_find_max_ring(jumbo_size,
4545 bp->rx_max_pg_ring_idx = (bp->rx_max_pg_ring * RX_DESC_CNT) - 1;
4546 rx_size = RX_COPY_THRESH + bp->rx_offset;
4547 bp->rx_copy_thresh = 0;
4550 bp->rx_buf_use_size = rx_size;
4552 bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
4553 bp->rx_jumbo_thresh = rx_size - bp->rx_offset;
4554 bp->rx_ring_size = size;
4555 bp->rx_max_ring = bnx2_find_max_ring(size, MAX_RX_RINGS);
4556 bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
4560 bnx2_free_tx_skbs(struct bnx2 *bp)
4564 if (bp->tx_buf_ring == NULL)
4567 for (i = 0; i < TX_DESC_CNT; ) {
4568 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
4569 struct sk_buff *skb = tx_buf->skb;
4577 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
4578 skb_headlen(skb), PCI_DMA_TODEVICE);
4582 last = skb_shinfo(skb)->nr_frags;
4583 for (j = 0; j < last; j++) {
4584 tx_buf = &bp->tx_buf_ring[i + j + 1];
4585 pci_unmap_page(bp->pdev,
4586 pci_unmap_addr(tx_buf, mapping),
4587 skb_shinfo(skb)->frags[j].size,
4597 bnx2_free_rx_skbs(struct bnx2 *bp)
4601 if (bp->rx_buf_ring == NULL)
4604 for (i = 0; i < bp->rx_max_ring_idx; i++) {
4605 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
4606 struct sk_buff *skb = rx_buf->skb;
4611 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
4612 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
4618 for (i = 0; i < bp->rx_max_pg_ring_idx; i++)
4619 bnx2_free_rx_page(bp, i);
4623 bnx2_free_skbs(struct bnx2 *bp)
4625 bnx2_free_tx_skbs(bp);
4626 bnx2_free_rx_skbs(bp);
4630 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
4634 rc = bnx2_reset_chip(bp, reset_code);
4639 if ((rc = bnx2_init_chip(bp)) != 0)
4642 bnx2_init_tx_ring(bp);
4643 bnx2_init_rx_ring(bp);
4648 bnx2_init_nic(struct bnx2 *bp)
4652 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
4655 spin_lock_bh(&bp->phy_lock);
4658 spin_unlock_bh(&bp->phy_lock);
4663 bnx2_test_registers(struct bnx2 *bp)
4667 static const struct {
4670 #define BNX2_FL_NOT_5709 1
4674 { 0x006c, 0, 0x00000000, 0x0000003f },
4675 { 0x0090, 0, 0xffffffff, 0x00000000 },
4676 { 0x0094, 0, 0x00000000, 0x00000000 },
4678 { 0x0404, BNX2_FL_NOT_5709, 0x00003f00, 0x00000000 },
4679 { 0x0418, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4680 { 0x041c, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4681 { 0x0420, BNX2_FL_NOT_5709, 0x00000000, 0x80ffffff },
4682 { 0x0424, BNX2_FL_NOT_5709, 0x00000000, 0x00000000 },
4683 { 0x0428, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4684 { 0x0450, BNX2_FL_NOT_5709, 0x00000000, 0x0000ffff },
4685 { 0x0454, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4686 { 0x0458, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4688 { 0x0808, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4689 { 0x0854, BNX2_FL_NOT_5709, 0x00000000, 0xffffffff },
4690 { 0x0868, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4691 { 0x086c, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4692 { 0x0870, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4693 { 0x0874, BNX2_FL_NOT_5709, 0x00000000, 0x77777777 },
4695 { 0x0c00, BNX2_FL_NOT_5709, 0x00000000, 0x00000001 },
4696 { 0x0c04, BNX2_FL_NOT_5709, 0x00000000, 0x03ff0001 },
4697 { 0x0c08, BNX2_FL_NOT_5709, 0x0f0ff073, 0x00000000 },
4699 { 0x1000, 0, 0x00000000, 0x00000001 },
4700 { 0x1004, 0, 0x00000000, 0x000f0001 },
4702 { 0x1408, 0, 0x01c00800, 0x00000000 },
4703 { 0x149c, 0, 0x8000ffff, 0x00000000 },
4704 { 0x14a8, 0, 0x00000000, 0x000001ff },
4705 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
4706 { 0x14b0, 0, 0x00000002, 0x00000001 },
4707 { 0x14b8, 0, 0x00000000, 0x00000000 },
4708 { 0x14c0, 0, 0x00000000, 0x00000009 },
4709 { 0x14c4, 0, 0x00003fff, 0x00000000 },
4710 { 0x14cc, 0, 0x00000000, 0x00000001 },
4711 { 0x14d0, 0, 0xffffffff, 0x00000000 },
4713 { 0x1800, 0, 0x00000000, 0x00000001 },
4714 { 0x1804, 0, 0x00000000, 0x00000003 },
4716 { 0x2800, 0, 0x00000000, 0x00000001 },
4717 { 0x2804, 0, 0x00000000, 0x00003f01 },
4718 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
4719 { 0x2810, 0, 0xffff0000, 0x00000000 },
4720 { 0x2814, 0, 0xffff0000, 0x00000000 },
4721 { 0x2818, 0, 0xffff0000, 0x00000000 },
4722 { 0x281c, 0, 0xffff0000, 0x00000000 },
4723 { 0x2834, 0, 0xffffffff, 0x00000000 },
4724 { 0x2840, 0, 0x00000000, 0xffffffff },
4725 { 0x2844, 0, 0x00000000, 0xffffffff },
4726 { 0x2848, 0, 0xffffffff, 0x00000000 },
4727 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
4729 { 0x2c00, 0, 0x00000000, 0x00000011 },
4730 { 0x2c04, 0, 0x00000000, 0x00030007 },
4732 { 0x3c00, 0, 0x00000000, 0x00000001 },
4733 { 0x3c04, 0, 0x00000000, 0x00070000 },
4734 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
4735 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
4736 { 0x3c10, 0, 0xffffffff, 0x00000000 },
4737 { 0x3c14, 0, 0x00000000, 0xffffffff },
4738 { 0x3c18, 0, 0x00000000, 0xffffffff },
4739 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
4740 { 0x3c20, 0, 0xffffff00, 0x00000000 },
4742 { 0x5004, 0, 0x00000000, 0x0000007f },
4743 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
4745 { 0x5c00, 0, 0x00000000, 0x00000001 },
4746 { 0x5c04, 0, 0x00000000, 0x0003000f },
4747 { 0x5c08, 0, 0x00000003, 0x00000000 },
4748 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
4749 { 0x5c10, 0, 0x00000000, 0xffffffff },
4750 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
4751 { 0x5c84, 0, 0x00000000, 0x0000f333 },
4752 { 0x5c88, 0, 0x00000000, 0x00077373 },
4753 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
4755 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
4756 { 0x680c, 0, 0xffffffff, 0x00000000 },
4757 { 0x6810, 0, 0xffffffff, 0x00000000 },
4758 { 0x6814, 0, 0xffffffff, 0x00000000 },
4759 { 0x6818, 0, 0xffffffff, 0x00000000 },
4760 { 0x681c, 0, 0xffffffff, 0x00000000 },
4761 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
4762 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
4763 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
4764 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
4765 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
4766 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
4767 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
4768 { 0x683c, 0, 0x0000ffff, 0x00000000 },
4769 { 0x6840, 0, 0x00000ff0, 0x00000000 },
4770 { 0x6844, 0, 0x00ffff00, 0x00000000 },
4771 { 0x684c, 0, 0xffffffff, 0x00000000 },
4772 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
4773 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
4774 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
4775 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
4776 { 0x6908, 0, 0x00000000, 0x0001ff0f },
4777 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
4779 { 0xffff, 0, 0x00000000, 0x00000000 },
4784 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4787 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
4788 u32 offset, rw_mask, ro_mask, save_val, val;
4789 u16 flags = reg_tbl[i].flags;
4791 if (is_5709 && (flags & BNX2_FL_NOT_5709))
4794 offset = (u32) reg_tbl[i].offset;
4795 rw_mask = reg_tbl[i].rw_mask;
4796 ro_mask = reg_tbl[i].ro_mask;
4798 save_val = readl(bp->regview + offset);
4800 writel(0, bp->regview + offset);
4802 val = readl(bp->regview + offset);
4803 if ((val & rw_mask) != 0) {
4807 if ((val & ro_mask) != (save_val & ro_mask)) {
4811 writel(0xffffffff, bp->regview + offset);
4813 val = readl(bp->regview + offset);
4814 if ((val & rw_mask) != rw_mask) {
4818 if ((val & ro_mask) != (save_val & ro_mask)) {
4822 writel(save_val, bp->regview + offset);
4826 writel(save_val, bp->regview + offset);
4834 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
4836 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
4837 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
4840 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
4843 for (offset = 0; offset < size; offset += 4) {
4845 REG_WR_IND(bp, start + offset, test_pattern[i]);
4847 if (REG_RD_IND(bp, start + offset) !=
4857 bnx2_test_memory(struct bnx2 *bp)
4861 static struct mem_entry {
4864 } mem_tbl_5706[] = {
4865 { 0x60000, 0x4000 },
4866 { 0xa0000, 0x3000 },
4867 { 0xe0000, 0x4000 },
4868 { 0x120000, 0x4000 },
4869 { 0x1a0000, 0x4000 },
4870 { 0x160000, 0x4000 },
4874 { 0x60000, 0x4000 },
4875 { 0xa0000, 0x3000 },
4876 { 0xe0000, 0x4000 },
4877 { 0x120000, 0x4000 },
4878 { 0x1a0000, 0x4000 },
4881 struct mem_entry *mem_tbl;
4883 if (CHIP_NUM(bp) == CHIP_NUM_5709)
4884 mem_tbl = mem_tbl_5709;
4886 mem_tbl = mem_tbl_5706;
4888 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
4889 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
4890 mem_tbl[i].len)) != 0) {
4898 #define BNX2_MAC_LOOPBACK 0
4899 #define BNX2_PHY_LOOPBACK 1
4902 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
4904 unsigned int pkt_size, num_pkts, i;
4905 struct sk_buff *skb, *rx_skb;
4906 unsigned char *packet;
4907 u16 rx_start_idx, rx_idx;
4910 struct sw_bd *rx_buf;
4911 struct l2_fhdr *rx_hdr;
4913 struct bnx2_napi *bnapi = &bp->bnx2_napi;
4915 if (loopback_mode == BNX2_MAC_LOOPBACK) {
4916 bp->loopback = MAC_LOOPBACK;
4917 bnx2_set_mac_loopback(bp);
4919 else if (loopback_mode == BNX2_PHY_LOOPBACK) {
4920 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
4923 bp->loopback = PHY_LOOPBACK;
4924 bnx2_set_phy_loopback(bp);
4929 pkt_size = min(bp->dev->mtu + ETH_HLEN, bp->rx_jumbo_thresh - 4);
4930 skb = netdev_alloc_skb(bp->dev, pkt_size);
4933 packet = skb_put(skb, pkt_size);
4934 memcpy(packet, bp->dev->dev_addr, 6);
4935 memset(packet + 6, 0x0, 8);
4936 for (i = 14; i < pkt_size; i++)
4937 packet[i] = (unsigned char) (i & 0xff);
4939 map = pci_map_single(bp->pdev, skb->data, pkt_size,
4942 REG_WR(bp, BNX2_HC_COMMAND,
4943 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4945 REG_RD(bp, BNX2_HC_COMMAND);
4948 rx_start_idx = bnx2_get_hw_rx_cons(bnapi);
4952 txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
4954 txbd->tx_bd_haddr_hi = (u64) map >> 32;
4955 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
4956 txbd->tx_bd_mss_nbytes = pkt_size;
4957 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
4960 bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
4961 bp->tx_prod_bseq += pkt_size;
4963 REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
4964 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
4968 REG_WR(bp, BNX2_HC_COMMAND,
4969 bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4971 REG_RD(bp, BNX2_HC_COMMAND);
4975 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
4978 if (bnx2_get_hw_tx_cons(bnapi) != bp->tx_prod)
4979 goto loopback_test_done;
4981 rx_idx = bnx2_get_hw_rx_cons(bnapi);
4982 if (rx_idx != rx_start_idx + num_pkts) {
4983 goto loopback_test_done;
4986 rx_buf = &bp->rx_buf_ring[rx_start_idx];
4987 rx_skb = rx_buf->skb;
4989 rx_hdr = (struct l2_fhdr *) rx_skb->data;
4990 skb_reserve(rx_skb, bp->rx_offset);
4992 pci_dma_sync_single_for_cpu(bp->pdev,
4993 pci_unmap_addr(rx_buf, mapping),
4994 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
4996 if (rx_hdr->l2_fhdr_status &
4997 (L2_FHDR_ERRORS_BAD_CRC |
4998 L2_FHDR_ERRORS_PHY_DECODE |
4999 L2_FHDR_ERRORS_ALIGNMENT |
5000 L2_FHDR_ERRORS_TOO_SHORT |
5001 L2_FHDR_ERRORS_GIANT_FRAME)) {
5003 goto loopback_test_done;
5006 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
5007 goto loopback_test_done;
5010 for (i = 14; i < pkt_size; i++) {
5011 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
5012 goto loopback_test_done;
5023 #define BNX2_MAC_LOOPBACK_FAILED 1
5024 #define BNX2_PHY_LOOPBACK_FAILED 2
5025 #define BNX2_LOOPBACK_FAILED (BNX2_MAC_LOOPBACK_FAILED | \
5026 BNX2_PHY_LOOPBACK_FAILED)
5029 bnx2_test_loopback(struct bnx2 *bp)
5033 if (!netif_running(bp->dev))
5034 return BNX2_LOOPBACK_FAILED;
5036 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
5037 spin_lock_bh(&bp->phy_lock);
5039 spin_unlock_bh(&bp->phy_lock);
5040 if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
5041 rc |= BNX2_MAC_LOOPBACK_FAILED;
5042 if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
5043 rc |= BNX2_PHY_LOOPBACK_FAILED;
5047 #define NVRAM_SIZE 0x200
5048 #define CRC32_RESIDUAL 0xdebb20e3
5051 bnx2_test_nvram(struct bnx2 *bp)
5053 u32 buf[NVRAM_SIZE / 4];
5054 u8 *data = (u8 *) buf;
5058 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
5059 goto test_nvram_done;
5061 magic = be32_to_cpu(buf[0]);
5062 if (magic != 0x669955aa) {
5064 goto test_nvram_done;
5067 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
5068 goto test_nvram_done;
5070 csum = ether_crc_le(0x100, data);
5071 if (csum != CRC32_RESIDUAL) {
5073 goto test_nvram_done;
5076 csum = ether_crc_le(0x100, data + 0x100);
5077 if (csum != CRC32_RESIDUAL) {
5086 bnx2_test_link(struct bnx2 *bp)
5090 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
5095 spin_lock_bh(&bp->phy_lock);
5096 bnx2_enable_bmsr1(bp);
5097 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5098 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
5099 bnx2_disable_bmsr1(bp);
5100 spin_unlock_bh(&bp->phy_lock);
5102 if (bmsr & BMSR_LSTATUS) {
5109 bnx2_test_intr(struct bnx2 *bp)
5114 if (!netif_running(bp->dev))
5117 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
5119 /* This register is not touched during run-time. */
5120 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
5121 REG_RD(bp, BNX2_HC_COMMAND);
5123 for (i = 0; i < 10; i++) {
5124 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
5130 msleep_interruptible(10);
5139 bnx2_5706_serdes_timer(struct bnx2 *bp)
5141 spin_lock(&bp->phy_lock);
5142 if (bp->serdes_an_pending)
5143 bp->serdes_an_pending--;
5144 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5147 bp->current_interval = bp->timer_interval;
5149 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5151 if (bmcr & BMCR_ANENABLE) {
5154 bnx2_write_phy(bp, 0x1c, 0x7c00);
5155 bnx2_read_phy(bp, 0x1c, &phy1);
5157 bnx2_write_phy(bp, 0x17, 0x0f01);
5158 bnx2_read_phy(bp, 0x15, &phy2);
5159 bnx2_write_phy(bp, 0x17, 0x0f01);
5160 bnx2_read_phy(bp, 0x15, &phy2);
5162 if ((phy1 & 0x10) && /* SIGNAL DETECT */
5163 !(phy2 & 0x20)) { /* no CONFIG */
5165 bmcr &= ~BMCR_ANENABLE;
5166 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5167 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5168 bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG;
5172 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
5173 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
5176 bnx2_write_phy(bp, 0x17, 0x0f01);
5177 bnx2_read_phy(bp, 0x15, &phy2);
5181 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5182 bmcr |= BMCR_ANENABLE;
5183 bnx2_write_phy(bp, bp->mii_bmcr, bmcr);
5185 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
5188 bp->current_interval = bp->timer_interval;
5190 spin_unlock(&bp->phy_lock);
5194 bnx2_5708_serdes_timer(struct bnx2 *bp)
5196 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
5199 if ((bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) == 0) {
5200 bp->serdes_an_pending = 0;
5204 spin_lock(&bp->phy_lock);
5205 if (bp->serdes_an_pending)
5206 bp->serdes_an_pending--;
5207 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
5210 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5211 if (bmcr & BMCR_ANENABLE) {
5212 bnx2_enable_forced_2g5(bp);
5213 bp->current_interval = SERDES_FORCED_TIMEOUT;
5215 bnx2_disable_forced_2g5(bp);
5216 bp->serdes_an_pending = 2;
5217 bp->current_interval = bp->timer_interval;
5221 bp->current_interval = bp->timer_interval;
5223 spin_unlock(&bp->phy_lock);
5227 bnx2_timer(unsigned long data)
5229 struct bnx2 *bp = (struct bnx2 *) data;
5231 if (!netif_running(bp->dev))
5234 if (atomic_read(&bp->intr_sem) != 0)
5235 goto bnx2_restart_timer;
5237 bnx2_send_heart_beat(bp);
5239 bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
5241 /* workaround occasional corrupted counters */
5242 if (CHIP_NUM(bp) == CHIP_NUM_5708 && bp->stats_ticks)
5243 REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd |
5244 BNX2_HC_COMMAND_STATS_NOW);
5246 if (bp->phy_flags & PHY_SERDES_FLAG) {
5247 if (CHIP_NUM(bp) == CHIP_NUM_5706)
5248 bnx2_5706_serdes_timer(bp);
5250 bnx2_5708_serdes_timer(bp);
5254 mod_timer(&bp->timer, jiffies + bp->current_interval);
5258 bnx2_request_irq(struct bnx2 *bp)
5260 struct net_device *dev = bp->dev;
5261 unsigned long flags;
5262 struct bnx2_irq *irq = &bp->irq_tbl[0];
5265 if (bp->flags & USING_MSI_FLAG)
5268 flags = IRQF_SHARED;
5269 rc = request_irq(irq->vector, irq->handler, flags, dev->name, dev);
5274 bnx2_free_irq(struct bnx2 *bp)
5276 struct net_device *dev = bp->dev;
5278 free_irq(bp->irq_tbl[0].vector, dev);
5279 if (bp->flags & USING_MSI_FLAG) {
5280 pci_disable_msi(bp->pdev);
5281 bp->flags &= ~(USING_MSI_FLAG | ONE_SHOT_MSI_FLAG);
5286 bnx2_setup_int_mode(struct bnx2 *bp, int dis_msi)
5288 bp->irq_tbl[0].handler = bnx2_interrupt;
5289 strcpy(bp->irq_tbl[0].name, bp->dev->name);
5291 if ((bp->flags & MSI_CAP_FLAG) && !dis_msi) {
5292 if (pci_enable_msi(bp->pdev) == 0) {
5293 bp->flags |= USING_MSI_FLAG;
5294 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
5295 bp->flags |= ONE_SHOT_MSI_FLAG;
5296 bp->irq_tbl[0].handler = bnx2_msi_1shot;
5298 bp->irq_tbl[0].handler = bnx2_msi;
5302 bp->irq_tbl[0].vector = bp->pdev->irq;
5305 /* Called with rtnl_lock */
5307 bnx2_open(struct net_device *dev)
5309 struct bnx2 *bp = netdev_priv(dev);
5312 netif_carrier_off(dev);
5314 bnx2_set_power_state(bp, PCI_D0);
5315 bnx2_disable_int(bp);
5317 rc = bnx2_alloc_mem(bp);
5321 bnx2_setup_int_mode(bp, disable_msi);
5322 bnx2_napi_enable(bp);
5323 rc = bnx2_request_irq(bp);
5326 bnx2_napi_disable(bp);
5331 rc = bnx2_init_nic(bp);
5334 bnx2_napi_disable(bp);
5341 mod_timer(&bp->timer, jiffies + bp->current_interval);
5343 atomic_set(&bp->intr_sem, 0);
5345 bnx2_enable_int(bp);
5347 if (bp->flags & USING_MSI_FLAG) {
5348 /* Test MSI to make sure it is working
5349 * If MSI test fails, go back to INTx mode
5351 if (bnx2_test_intr(bp) != 0) {
5352 printk(KERN_WARNING PFX "%s: No interrupt was generated"
5353 " using MSI, switching to INTx mode. Please"
5354 " report this failure to the PCI maintainer"
5355 " and include system chipset information.\n",
5358 bnx2_disable_int(bp);
5361 bnx2_setup_int_mode(bp, 1);
5363 rc = bnx2_init_nic(bp);
5366 rc = bnx2_request_irq(bp);
5369 bnx2_napi_disable(bp);
5372 del_timer_sync(&bp->timer);
5375 bnx2_enable_int(bp);
5378 if (bp->flags & USING_MSI_FLAG) {
5379 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
5382 netif_start_queue(dev);
5388 bnx2_reset_task(struct work_struct *work)
5390 struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
5392 if (!netif_running(bp->dev))
5395 bp->in_reset_task = 1;
5396 bnx2_netif_stop(bp);
5400 atomic_set(&bp->intr_sem, 1);
5401 bnx2_netif_start(bp);
5402 bp->in_reset_task = 0;
5406 bnx2_tx_timeout(struct net_device *dev)
5408 struct bnx2 *bp = netdev_priv(dev);
5410 /* This allows the netif to be shutdown gracefully before resetting */
5411 schedule_work(&bp->reset_task);
5415 /* Called with rtnl_lock */
5417 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
5419 struct bnx2 *bp = netdev_priv(dev);
5421 bnx2_netif_stop(bp);
5424 bnx2_set_rx_mode(dev);
5426 bnx2_netif_start(bp);
5430 /* Called with netif_tx_lock.
5431 * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
5432 * netif_wake_queue().
5435 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
5437 struct bnx2 *bp = netdev_priv(dev);
5440 struct sw_bd *tx_buf;
5441 u32 len, vlan_tag_flags, last_frag, mss;
5442 u16 prod, ring_prod;
5444 struct bnx2_napi *bnapi = &bp->bnx2_napi;
5446 if (unlikely(bnx2_tx_avail(bp, bnapi) <
5447 (skb_shinfo(skb)->nr_frags + 1))) {
5448 netif_stop_queue(dev);
5449 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
5452 return NETDEV_TX_BUSY;
5454 len = skb_headlen(skb);
5456 ring_prod = TX_RING_IDX(prod);
5459 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5460 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5463 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
5465 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
5467 if ((mss = skb_shinfo(skb)->gso_size)) {
5468 u32 tcp_opt_len, ip_tcp_len;
5471 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
5473 tcp_opt_len = tcp_optlen(skb);
5475 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6) {
5476 u32 tcp_off = skb_transport_offset(skb) -
5477 sizeof(struct ipv6hdr) - ETH_HLEN;
5479 vlan_tag_flags |= ((tcp_opt_len >> 2) << 8) |
5480 TX_BD_FLAGS_SW_FLAGS;
5481 if (likely(tcp_off == 0))
5482 vlan_tag_flags &= ~TX_BD_FLAGS_TCP6_OFF0_MSK;
5485 vlan_tag_flags |= ((tcp_off & 0x3) <<
5486 TX_BD_FLAGS_TCP6_OFF0_SHL) |
5487 ((tcp_off & 0x10) <<
5488 TX_BD_FLAGS_TCP6_OFF4_SHL);
5489 mss |= (tcp_off & 0xc) << TX_BD_TCP6_OFF2_SHL;
5492 if (skb_header_cloned(skb) &&
5493 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5495 return NETDEV_TX_OK;
5498 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5502 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5503 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5507 if (tcp_opt_len || (iph->ihl > 5)) {
5508 vlan_tag_flags |= ((iph->ihl - 5) +
5509 (tcp_opt_len >> 2)) << 8;
5515 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5517 tx_buf = &bp->tx_buf_ring[ring_prod];
5519 pci_unmap_addr_set(tx_buf, mapping, mapping);
5521 txbd = &bp->tx_desc_ring[ring_prod];
5523 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5524 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5525 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5526 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
5528 last_frag = skb_shinfo(skb)->nr_frags;
5530 for (i = 0; i < last_frag; i++) {
5531 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5533 prod = NEXT_TX_BD(prod);
5534 ring_prod = TX_RING_IDX(prod);
5535 txbd = &bp->tx_desc_ring[ring_prod];
5538 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
5539 len, PCI_DMA_TODEVICE);
5540 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
5543 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
5544 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
5545 txbd->tx_bd_mss_nbytes = len | (mss << 16);
5546 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
5549 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
5551 prod = NEXT_TX_BD(prod);
5552 bp->tx_prod_bseq += skb->len;
5554 REG_WR16(bp, bp->tx_bidx_addr, prod);
5555 REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
5560 dev->trans_start = jiffies;
5562 if (unlikely(bnx2_tx_avail(bp, bnapi) <= MAX_SKB_FRAGS)) {
5563 netif_stop_queue(dev);
5564 if (bnx2_tx_avail(bp, bnapi) > bp->tx_wake_thresh)
5565 netif_wake_queue(dev);
5568 return NETDEV_TX_OK;
5571 /* Called with rtnl_lock */
5573 bnx2_close(struct net_device *dev)
5575 struct bnx2 *bp = netdev_priv(dev);
5578 /* Calling flush_scheduled_work() may deadlock because
5579 * linkwatch_event() may be on the workqueue and it will try to get
5580 * the rtnl_lock which we are holding.
5582 while (bp->in_reset_task)
5585 bnx2_disable_int_sync(bp);
5586 bnx2_napi_disable(bp);
5587 del_timer_sync(&bp->timer);
5588 if (bp->flags & NO_WOL_FLAG)
5589 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
5591 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5593 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5594 bnx2_reset_chip(bp, reset_code);
5599 netif_carrier_off(bp->dev);
5600 bnx2_set_power_state(bp, PCI_D3hot);
5604 #define GET_NET_STATS64(ctr) \
5605 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
5606 (unsigned long) (ctr##_lo)
5608 #define GET_NET_STATS32(ctr) \
5611 #if (BITS_PER_LONG == 64)
5612 #define GET_NET_STATS GET_NET_STATS64
5614 #define GET_NET_STATS GET_NET_STATS32
5617 static struct net_device_stats *
5618 bnx2_get_stats(struct net_device *dev)
5620 struct bnx2 *bp = netdev_priv(dev);
5621 struct statistics_block *stats_blk = bp->stats_blk;
5622 struct net_device_stats *net_stats = &bp->net_stats;
5624 if (bp->stats_blk == NULL) {
5627 net_stats->rx_packets =
5628 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
5629 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
5630 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
5632 net_stats->tx_packets =
5633 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
5634 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
5635 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
5637 net_stats->rx_bytes =
5638 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
5640 net_stats->tx_bytes =
5641 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
5643 net_stats->multicast =
5644 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
5646 net_stats->collisions =
5647 (unsigned long) stats_blk->stat_EtherStatsCollisions;
5649 net_stats->rx_length_errors =
5650 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
5651 stats_blk->stat_EtherStatsOverrsizePkts);
5653 net_stats->rx_over_errors =
5654 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
5656 net_stats->rx_frame_errors =
5657 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
5659 net_stats->rx_crc_errors =
5660 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
5662 net_stats->rx_errors = net_stats->rx_length_errors +
5663 net_stats->rx_over_errors + net_stats->rx_frame_errors +
5664 net_stats->rx_crc_errors;
5666 net_stats->tx_aborted_errors =
5667 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
5668 stats_blk->stat_Dot3StatsLateCollisions);
5670 if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
5671 (CHIP_ID(bp) == CHIP_ID_5708_A0))
5672 net_stats->tx_carrier_errors = 0;
5674 net_stats->tx_carrier_errors =
5676 stats_blk->stat_Dot3StatsCarrierSenseErrors;
5679 net_stats->tx_errors =
5681 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
5683 net_stats->tx_aborted_errors +
5684 net_stats->tx_carrier_errors;
5686 net_stats->rx_missed_errors =
5687 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
5688 stats_blk->stat_FwRxDrop);
5693 /* All ethtool functions called with rtnl_lock */
5696 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5698 struct bnx2 *bp = netdev_priv(dev);
5699 int support_serdes = 0, support_copper = 0;
5701 cmd->supported = SUPPORTED_Autoneg;
5702 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
5705 } else if (bp->phy_port == PORT_FIBRE)
5710 if (support_serdes) {
5711 cmd->supported |= SUPPORTED_1000baseT_Full |
5713 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
5714 cmd->supported |= SUPPORTED_2500baseX_Full;
5717 if (support_copper) {
5718 cmd->supported |= SUPPORTED_10baseT_Half |
5719 SUPPORTED_10baseT_Full |
5720 SUPPORTED_100baseT_Half |
5721 SUPPORTED_100baseT_Full |
5722 SUPPORTED_1000baseT_Full |
5727 spin_lock_bh(&bp->phy_lock);
5728 cmd->port = bp->phy_port;
5729 cmd->advertising = bp->advertising;
5731 if (bp->autoneg & AUTONEG_SPEED) {
5732 cmd->autoneg = AUTONEG_ENABLE;
5735 cmd->autoneg = AUTONEG_DISABLE;
5738 if (netif_carrier_ok(dev)) {
5739 cmd->speed = bp->line_speed;
5740 cmd->duplex = bp->duplex;
5746 spin_unlock_bh(&bp->phy_lock);
5748 cmd->transceiver = XCVR_INTERNAL;
5749 cmd->phy_address = bp->phy_addr;
5755 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5757 struct bnx2 *bp = netdev_priv(dev);
5758 u8 autoneg = bp->autoneg;
5759 u8 req_duplex = bp->req_duplex;
5760 u16 req_line_speed = bp->req_line_speed;
5761 u32 advertising = bp->advertising;
5764 spin_lock_bh(&bp->phy_lock);
5766 if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE)
5767 goto err_out_unlock;
5769 if (cmd->port != bp->phy_port && !(bp->phy_flags & REMOTE_PHY_CAP_FLAG))
5770 goto err_out_unlock;
5772 if (cmd->autoneg == AUTONEG_ENABLE) {
5773 autoneg |= AUTONEG_SPEED;
5775 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
5777 /* allow advertising 1 speed */
5778 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
5779 (cmd->advertising == ADVERTISED_10baseT_Full) ||
5780 (cmd->advertising == ADVERTISED_100baseT_Half) ||
5781 (cmd->advertising == ADVERTISED_100baseT_Full)) {
5783 if (cmd->port == PORT_FIBRE)
5784 goto err_out_unlock;
5786 advertising = cmd->advertising;
5788 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
5789 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ||
5790 (cmd->port == PORT_TP))
5791 goto err_out_unlock;
5792 } else if (cmd->advertising == ADVERTISED_1000baseT_Full)
5793 advertising = cmd->advertising;
5794 else if (cmd->advertising == ADVERTISED_1000baseT_Half)
5795 goto err_out_unlock;
5797 if (cmd->port == PORT_FIBRE)
5798 advertising = ETHTOOL_ALL_FIBRE_SPEED;
5800 advertising = ETHTOOL_ALL_COPPER_SPEED;
5802 advertising |= ADVERTISED_Autoneg;
5805 if (cmd->port == PORT_FIBRE) {
5806 if ((cmd->speed != SPEED_1000 &&
5807 cmd->speed != SPEED_2500) ||
5808 (cmd->duplex != DUPLEX_FULL))
5809 goto err_out_unlock;
5811 if (cmd->speed == SPEED_2500 &&
5812 !(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
5813 goto err_out_unlock;
5815 else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500)
5816 goto err_out_unlock;
5818 autoneg &= ~AUTONEG_SPEED;
5819 req_line_speed = cmd->speed;
5820 req_duplex = cmd->duplex;
5824 bp->autoneg = autoneg;
5825 bp->advertising = advertising;
5826 bp->req_line_speed = req_line_speed;
5827 bp->req_duplex = req_duplex;
5829 err = bnx2_setup_phy(bp, cmd->port);
5832 spin_unlock_bh(&bp->phy_lock);
5838 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
5840 struct bnx2 *bp = netdev_priv(dev);
5842 strcpy(info->driver, DRV_MODULE_NAME);
5843 strcpy(info->version, DRV_MODULE_VERSION);
5844 strcpy(info->bus_info, pci_name(bp->pdev));
5845 strcpy(info->fw_version, bp->fw_version);
5848 #define BNX2_REGDUMP_LEN (32 * 1024)
5851 bnx2_get_regs_len(struct net_device *dev)
5853 return BNX2_REGDUMP_LEN;
5857 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
5859 u32 *p = _p, i, offset;
5861 struct bnx2 *bp = netdev_priv(dev);
5862 u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
5863 0x0800, 0x0880, 0x0c00, 0x0c10,
5864 0x0c30, 0x0d08, 0x1000, 0x101c,
5865 0x1040, 0x1048, 0x1080, 0x10a4,
5866 0x1400, 0x1490, 0x1498, 0x14f0,
5867 0x1500, 0x155c, 0x1580, 0x15dc,
5868 0x1600, 0x1658, 0x1680, 0x16d8,
5869 0x1800, 0x1820, 0x1840, 0x1854,
5870 0x1880, 0x1894, 0x1900, 0x1984,
5871 0x1c00, 0x1c0c, 0x1c40, 0x1c54,
5872 0x1c80, 0x1c94, 0x1d00, 0x1d84,
5873 0x2000, 0x2030, 0x23c0, 0x2400,
5874 0x2800, 0x2820, 0x2830, 0x2850,
5875 0x2b40, 0x2c10, 0x2fc0, 0x3058,
5876 0x3c00, 0x3c94, 0x4000, 0x4010,
5877 0x4080, 0x4090, 0x43c0, 0x4458,
5878 0x4c00, 0x4c18, 0x4c40, 0x4c54,
5879 0x4fc0, 0x5010, 0x53c0, 0x5444,
5880 0x5c00, 0x5c18, 0x5c80, 0x5c90,
5881 0x5fc0, 0x6000, 0x6400, 0x6428,
5882 0x6800, 0x6848, 0x684c, 0x6860,
5883 0x6888, 0x6910, 0x8000 };
5887 memset(p, 0, BNX2_REGDUMP_LEN);
5889 if (!netif_running(bp->dev))
5893 offset = reg_boundaries[0];
5895 while (offset < BNX2_REGDUMP_LEN) {
5896 *p++ = REG_RD(bp, offset);
5898 if (offset == reg_boundaries[i + 1]) {
5899 offset = reg_boundaries[i + 2];
5900 p = (u32 *) (orig_p + offset);
5907 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5909 struct bnx2 *bp = netdev_priv(dev);
5911 if (bp->flags & NO_WOL_FLAG) {
5916 wol->supported = WAKE_MAGIC;
5918 wol->wolopts = WAKE_MAGIC;
5922 memset(&wol->sopass, 0, sizeof(wol->sopass));
5926 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
5928 struct bnx2 *bp = netdev_priv(dev);
5930 if (wol->wolopts & ~WAKE_MAGIC)
5933 if (wol->wolopts & WAKE_MAGIC) {
5934 if (bp->flags & NO_WOL_FLAG)
5946 bnx2_nway_reset(struct net_device *dev)
5948 struct bnx2 *bp = netdev_priv(dev);
5951 if (!(bp->autoneg & AUTONEG_SPEED)) {
5955 spin_lock_bh(&bp->phy_lock);
5957 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) {
5960 rc = bnx2_setup_remote_phy(bp, bp->phy_port);
5961 spin_unlock_bh(&bp->phy_lock);
5965 /* Force a link down visible on the other side */
5966 if (bp->phy_flags & PHY_SERDES_FLAG) {
5967 bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK);
5968 spin_unlock_bh(&bp->phy_lock);
5972 spin_lock_bh(&bp->phy_lock);
5974 bp->current_interval = SERDES_AN_TIMEOUT;
5975 bp->serdes_an_pending = 1;
5976 mod_timer(&bp->timer, jiffies + bp->current_interval);
5979 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
5980 bmcr &= ~BMCR_LOOPBACK;
5981 bnx2_write_phy(bp, bp->mii_bmcr, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
5983 spin_unlock_bh(&bp->phy_lock);
5989 bnx2_get_eeprom_len(struct net_device *dev)
5991 struct bnx2 *bp = netdev_priv(dev);
5993 if (bp->flash_info == NULL)
5996 return (int) bp->flash_size;
6000 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6003 struct bnx2 *bp = netdev_priv(dev);
6006 /* parameters already validated in ethtool_get_eeprom */
6008 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
6014 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
6017 struct bnx2 *bp = netdev_priv(dev);
6020 /* parameters already validated in ethtool_set_eeprom */
6022 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
6028 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6030 struct bnx2 *bp = netdev_priv(dev);
6032 memset(coal, 0, sizeof(struct ethtool_coalesce));
6034 coal->rx_coalesce_usecs = bp->rx_ticks;
6035 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
6036 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
6037 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
6039 coal->tx_coalesce_usecs = bp->tx_ticks;
6040 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
6041 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
6042 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
6044 coal->stats_block_coalesce_usecs = bp->stats_ticks;
6050 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
6052 struct bnx2 *bp = netdev_priv(dev);
6054 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
6055 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
6057 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
6058 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
6060 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
6061 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
6063 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
6064 if (bp->rx_quick_cons_trip_int > 0xff)
6065 bp->rx_quick_cons_trip_int = 0xff;
6067 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
6068 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
6070 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
6071 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
6073 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
6074 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
6076 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
6077 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
6080 bp->stats_ticks = coal->stats_block_coalesce_usecs;
6081 if (CHIP_NUM(bp) == CHIP_NUM_5708) {
6082 if (bp->stats_ticks != 0 && bp->stats_ticks != USEC_PER_SEC)
6083 bp->stats_ticks = USEC_PER_SEC;
6085 if (bp->stats_ticks > BNX2_HC_STATS_TICKS_HC_STAT_TICKS)
6086 bp->stats_ticks = BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6087 bp->stats_ticks &= BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6089 if (netif_running(bp->dev)) {
6090 bnx2_netif_stop(bp);
6092 bnx2_netif_start(bp);
6099 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6101 struct bnx2 *bp = netdev_priv(dev);
6103 ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
6104 ering->rx_mini_max_pending = 0;
6105 ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
6107 ering->rx_pending = bp->rx_ring_size;
6108 ering->rx_mini_pending = 0;
6109 ering->rx_jumbo_pending = bp->rx_pg_ring_size;
6111 ering->tx_max_pending = MAX_TX_DESC_CNT;
6112 ering->tx_pending = bp->tx_ring_size;
6116 bnx2_change_ring_size(struct bnx2 *bp, u32 rx, u32 tx)
6118 if (netif_running(bp->dev)) {
6119 bnx2_netif_stop(bp);
6120 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6125 bnx2_set_rx_ring_size(bp, rx);
6126 bp->tx_ring_size = tx;
6128 if (netif_running(bp->dev)) {
6131 rc = bnx2_alloc_mem(bp);
6135 bnx2_netif_start(bp);
6141 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
6143 struct bnx2 *bp = netdev_priv(dev);
6146 if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
6147 (ering->tx_pending > MAX_TX_DESC_CNT) ||
6148 (ering->tx_pending <= MAX_SKB_FRAGS)) {
6152 rc = bnx2_change_ring_size(bp, ering->rx_pending, ering->tx_pending);
6157 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6159 struct bnx2 *bp = netdev_priv(dev);
6161 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
6162 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
6163 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
6167 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
6169 struct bnx2 *bp = netdev_priv(dev);
6171 bp->req_flow_ctrl = 0;
6172 if (epause->rx_pause)
6173 bp->req_flow_ctrl |= FLOW_CTRL_RX;
6174 if (epause->tx_pause)
6175 bp->req_flow_ctrl |= FLOW_CTRL_TX;
6177 if (epause->autoneg) {
6178 bp->autoneg |= AUTONEG_FLOW_CTRL;
6181 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
6184 spin_lock_bh(&bp->phy_lock);
6186 bnx2_setup_phy(bp, bp->phy_port);
6188 spin_unlock_bh(&bp->phy_lock);
6194 bnx2_get_rx_csum(struct net_device *dev)
6196 struct bnx2 *bp = netdev_priv(dev);
6202 bnx2_set_rx_csum(struct net_device *dev, u32 data)
6204 struct bnx2 *bp = netdev_priv(dev);
6211 bnx2_set_tso(struct net_device *dev, u32 data)
6213 struct bnx2 *bp = netdev_priv(dev);
6216 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6217 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6218 dev->features |= NETIF_F_TSO6;
6220 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6 |
6225 #define BNX2_NUM_STATS 46
6228 char string[ETH_GSTRING_LEN];
6229 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
6231 { "rx_error_bytes" },
6233 { "tx_error_bytes" },
6234 { "rx_ucast_packets" },
6235 { "rx_mcast_packets" },
6236 { "rx_bcast_packets" },
6237 { "tx_ucast_packets" },
6238 { "tx_mcast_packets" },
6239 { "tx_bcast_packets" },
6240 { "tx_mac_errors" },
6241 { "tx_carrier_errors" },
6242 { "rx_crc_errors" },
6243 { "rx_align_errors" },
6244 { "tx_single_collisions" },
6245 { "tx_multi_collisions" },
6247 { "tx_excess_collisions" },
6248 { "tx_late_collisions" },
6249 { "tx_total_collisions" },
6252 { "rx_undersize_packets" },
6253 { "rx_oversize_packets" },
6254 { "rx_64_byte_packets" },
6255 { "rx_65_to_127_byte_packets" },
6256 { "rx_128_to_255_byte_packets" },
6257 { "rx_256_to_511_byte_packets" },
6258 { "rx_512_to_1023_byte_packets" },
6259 { "rx_1024_to_1522_byte_packets" },
6260 { "rx_1523_to_9022_byte_packets" },
6261 { "tx_64_byte_packets" },
6262 { "tx_65_to_127_byte_packets" },
6263 { "tx_128_to_255_byte_packets" },
6264 { "tx_256_to_511_byte_packets" },
6265 { "tx_512_to_1023_byte_packets" },
6266 { "tx_1024_to_1522_byte_packets" },
6267 { "tx_1523_to_9022_byte_packets" },
6268 { "rx_xon_frames" },
6269 { "rx_xoff_frames" },
6270 { "tx_xon_frames" },
6271 { "tx_xoff_frames" },
6272 { "rx_mac_ctrl_frames" },
6273 { "rx_filtered_packets" },
6275 { "rx_fw_discards" },
6278 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
6280 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
6281 STATS_OFFSET32(stat_IfHCInOctets_hi),
6282 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
6283 STATS_OFFSET32(stat_IfHCOutOctets_hi),
6284 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
6285 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
6286 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
6287 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
6288 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
6289 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
6290 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
6291 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
6292 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
6293 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
6294 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
6295 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
6296 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
6297 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
6298 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
6299 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
6300 STATS_OFFSET32(stat_EtherStatsCollisions),
6301 STATS_OFFSET32(stat_EtherStatsFragments),
6302 STATS_OFFSET32(stat_EtherStatsJabbers),
6303 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
6304 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
6305 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
6306 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
6307 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
6308 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
6309 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
6310 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
6311 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
6312 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
6313 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
6314 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
6315 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
6316 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
6317 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
6318 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
6319 STATS_OFFSET32(stat_XonPauseFramesReceived),
6320 STATS_OFFSET32(stat_XoffPauseFramesReceived),
6321 STATS_OFFSET32(stat_OutXonSent),
6322 STATS_OFFSET32(stat_OutXoffSent),
6323 STATS_OFFSET32(stat_MacControlFramesReceived),
6324 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
6325 STATS_OFFSET32(stat_IfInMBUFDiscards),
6326 STATS_OFFSET32(stat_FwRxDrop),
6329 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
6330 * skipped because of errata.
6332 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
6333 8,0,8,8,8,8,8,8,8,8,
6334 4,0,4,4,4,4,4,4,4,4,
6335 4,4,4,4,4,4,4,4,4,4,
6336 4,4,4,4,4,4,4,4,4,4,
6340 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
6341 8,0,8,8,8,8,8,8,8,8,
6342 4,4,4,4,4,4,4,4,4,4,
6343 4,4,4,4,4,4,4,4,4,4,
6344 4,4,4,4,4,4,4,4,4,4,
6348 #define BNX2_NUM_TESTS 6
6351 char string[ETH_GSTRING_LEN];
6352 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
6353 { "register_test (offline)" },
6354 { "memory_test (offline)" },
6355 { "loopback_test (offline)" },
6356 { "nvram_test (online)" },
6357 { "interrupt_test (online)" },
6358 { "link_test (online)" },
6362 bnx2_get_sset_count(struct net_device *dev, int sset)
6366 return BNX2_NUM_TESTS;
6368 return BNX2_NUM_STATS;
6375 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
6377 struct bnx2 *bp = netdev_priv(dev);
6379 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
6380 if (etest->flags & ETH_TEST_FL_OFFLINE) {
6383 bnx2_netif_stop(bp);
6384 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
6387 if (bnx2_test_registers(bp) != 0) {
6389 etest->flags |= ETH_TEST_FL_FAILED;
6391 if (bnx2_test_memory(bp) != 0) {
6393 etest->flags |= ETH_TEST_FL_FAILED;
6395 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
6396 etest->flags |= ETH_TEST_FL_FAILED;
6398 if (!netif_running(bp->dev)) {
6399 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
6403 bnx2_netif_start(bp);
6406 /* wait for link up */
6407 for (i = 0; i < 7; i++) {
6410 msleep_interruptible(1000);
6414 if (bnx2_test_nvram(bp) != 0) {
6416 etest->flags |= ETH_TEST_FL_FAILED;
6418 if (bnx2_test_intr(bp) != 0) {
6420 etest->flags |= ETH_TEST_FL_FAILED;
6423 if (bnx2_test_link(bp) != 0) {
6425 etest->flags |= ETH_TEST_FL_FAILED;
6431 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6433 switch (stringset) {
6435 memcpy(buf, bnx2_stats_str_arr,
6436 sizeof(bnx2_stats_str_arr));
6439 memcpy(buf, bnx2_tests_str_arr,
6440 sizeof(bnx2_tests_str_arr));
6446 bnx2_get_ethtool_stats(struct net_device *dev,
6447 struct ethtool_stats *stats, u64 *buf)
6449 struct bnx2 *bp = netdev_priv(dev);
6451 u32 *hw_stats = (u32 *) bp->stats_blk;
6452 u8 *stats_len_arr = NULL;
6454 if (hw_stats == NULL) {
6455 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
6459 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
6460 (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
6461 (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
6462 (CHIP_ID(bp) == CHIP_ID_5708_A0))
6463 stats_len_arr = bnx2_5706_stats_len_arr;
6465 stats_len_arr = bnx2_5708_stats_len_arr;
6467 for (i = 0; i < BNX2_NUM_STATS; i++) {
6468 if (stats_len_arr[i] == 0) {
6469 /* skip this counter */
6473 if (stats_len_arr[i] == 4) {
6474 /* 4-byte counter */
6476 *(hw_stats + bnx2_stats_offset_arr[i]);
6479 /* 8-byte counter */
6480 buf[i] = (((u64) *(hw_stats +
6481 bnx2_stats_offset_arr[i])) << 32) +
6482 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
6487 bnx2_phys_id(struct net_device *dev, u32 data)
6489 struct bnx2 *bp = netdev_priv(dev);
6496 save = REG_RD(bp, BNX2_MISC_CFG);
6497 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
6499 for (i = 0; i < (data * 2); i++) {
6501 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
6504 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
6505 BNX2_EMAC_LED_1000MB_OVERRIDE |
6506 BNX2_EMAC_LED_100MB_OVERRIDE |
6507 BNX2_EMAC_LED_10MB_OVERRIDE |
6508 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
6509 BNX2_EMAC_LED_TRAFFIC);
6511 msleep_interruptible(500);
6512 if (signal_pending(current))
6515 REG_WR(bp, BNX2_EMAC_LED, 0);
6516 REG_WR(bp, BNX2_MISC_CFG, save);
6521 bnx2_set_tx_csum(struct net_device *dev, u32 data)
6523 struct bnx2 *bp = netdev_priv(dev);
6525 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6526 return (ethtool_op_set_tx_ipv6_csum(dev, data));
6528 return (ethtool_op_set_tx_csum(dev, data));
6531 static const struct ethtool_ops bnx2_ethtool_ops = {
6532 .get_settings = bnx2_get_settings,
6533 .set_settings = bnx2_set_settings,
6534 .get_drvinfo = bnx2_get_drvinfo,
6535 .get_regs_len = bnx2_get_regs_len,
6536 .get_regs = bnx2_get_regs,
6537 .get_wol = bnx2_get_wol,
6538 .set_wol = bnx2_set_wol,
6539 .nway_reset = bnx2_nway_reset,
6540 .get_link = ethtool_op_get_link,
6541 .get_eeprom_len = bnx2_get_eeprom_len,
6542 .get_eeprom = bnx2_get_eeprom,
6543 .set_eeprom = bnx2_set_eeprom,
6544 .get_coalesce = bnx2_get_coalesce,
6545 .set_coalesce = bnx2_set_coalesce,
6546 .get_ringparam = bnx2_get_ringparam,
6547 .set_ringparam = bnx2_set_ringparam,
6548 .get_pauseparam = bnx2_get_pauseparam,
6549 .set_pauseparam = bnx2_set_pauseparam,
6550 .get_rx_csum = bnx2_get_rx_csum,
6551 .set_rx_csum = bnx2_set_rx_csum,
6552 .set_tx_csum = bnx2_set_tx_csum,
6553 .set_sg = ethtool_op_set_sg,
6554 .set_tso = bnx2_set_tso,
6555 .self_test = bnx2_self_test,
6556 .get_strings = bnx2_get_strings,
6557 .phys_id = bnx2_phys_id,
6558 .get_ethtool_stats = bnx2_get_ethtool_stats,
6559 .get_sset_count = bnx2_get_sset_count,
6562 /* Called with rtnl_lock */
6564 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
6566 struct mii_ioctl_data *data = if_mii(ifr);
6567 struct bnx2 *bp = netdev_priv(dev);
6572 data->phy_id = bp->phy_addr;
6578 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
6581 if (!netif_running(dev))
6584 spin_lock_bh(&bp->phy_lock);
6585 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
6586 spin_unlock_bh(&bp->phy_lock);
6588 data->val_out = mii_regval;
6594 if (!capable(CAP_NET_ADMIN))
6597 if (bp->phy_flags & REMOTE_PHY_CAP_FLAG)
6600 if (!netif_running(dev))
6603 spin_lock_bh(&bp->phy_lock);
6604 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
6605 spin_unlock_bh(&bp->phy_lock);
6616 /* Called with rtnl_lock */
6618 bnx2_change_mac_addr(struct net_device *dev, void *p)
6620 struct sockaddr *addr = p;
6621 struct bnx2 *bp = netdev_priv(dev);
6623 if (!is_valid_ether_addr(addr->sa_data))
6626 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6627 if (netif_running(dev))
6628 bnx2_set_mac_addr(bp);
6633 /* Called with rtnl_lock */
6635 bnx2_change_mtu(struct net_device *dev, int new_mtu)
6637 struct bnx2 *bp = netdev_priv(dev);
6639 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
6640 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
6644 return (bnx2_change_ring_size(bp, bp->rx_ring_size, bp->tx_ring_size));
6647 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6649 poll_bnx2(struct net_device *dev)
6651 struct bnx2 *bp = netdev_priv(dev);
6653 disable_irq(bp->pdev->irq);
6654 bnx2_interrupt(bp->pdev->irq, dev);
6655 enable_irq(bp->pdev->irq);
6659 static void __devinit
6660 bnx2_get_5709_media(struct bnx2 *bp)
6662 u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
6663 u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
6666 if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
6668 else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
6669 bp->phy_flags |= PHY_SERDES_FLAG;
6673 if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
6674 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
6676 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
6678 if (PCI_FUNC(bp->pdev->devfn) == 0) {
6683 bp->phy_flags |= PHY_SERDES_FLAG;
6691 bp->phy_flags |= PHY_SERDES_FLAG;
6697 static void __devinit
6698 bnx2_get_pci_speed(struct bnx2 *bp)
6702 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
6703 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
6706 bp->flags |= PCIX_FLAG;
6708 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
6710 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
6712 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
6713 bp->bus_speed_mhz = 133;
6716 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
6717 bp->bus_speed_mhz = 100;
6720 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
6721 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
6722 bp->bus_speed_mhz = 66;
6725 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
6726 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
6727 bp->bus_speed_mhz = 50;
6730 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
6731 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
6732 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
6733 bp->bus_speed_mhz = 33;
6738 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
6739 bp->bus_speed_mhz = 66;
6741 bp->bus_speed_mhz = 33;
6744 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
6745 bp->flags |= PCI_32BIT_FLAG;
6749 static int __devinit
6750 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
6753 unsigned long mem_len;
6756 u64 dma_mask, persist_dma_mask;
6758 SET_NETDEV_DEV(dev, &pdev->dev);
6759 bp = netdev_priv(dev);
6764 /* enable device (incl. PCI PM wakeup), and bus-mastering */
6765 rc = pci_enable_device(pdev);
6767 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.\n");
6771 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
6773 "Cannot find PCI device base address, aborting.\n");
6775 goto err_out_disable;
6778 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
6780 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
6781 goto err_out_disable;
6784 pci_set_master(pdev);
6786 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
6787 if (bp->pm_cap == 0) {
6789 "Cannot find power management capability, aborting.\n");
6791 goto err_out_release;
6797 spin_lock_init(&bp->phy_lock);
6798 spin_lock_init(&bp->indirect_lock);
6799 INIT_WORK(&bp->reset_task, bnx2_reset_task);
6801 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
6802 mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
6803 dev->mem_end = dev->mem_start + mem_len;
6804 dev->irq = pdev->irq;
6806 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
6809 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
6811 goto err_out_release;
6814 /* Configure byte swap and enable write to the reg_window registers.
6815 * Rely on CPU to do target byte swapping on big endian systems
6816 * The chip's target access swapping will not swap all accesses
6818 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
6819 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
6820 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
6822 bnx2_set_power_state(bp, PCI_D0);
6824 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
6826 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
6827 if (pci_find_capability(pdev, PCI_CAP_ID_EXP) == 0) {
6829 "Cannot find PCIE capability, aborting.\n");
6833 bp->flags |= PCIE_FLAG;
6835 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
6836 if (bp->pcix_cap == 0) {
6838 "Cannot find PCIX capability, aborting.\n");
6844 if (CHIP_ID(bp) != CHIP_ID_5706_A0 && CHIP_ID(bp) != CHIP_ID_5706_A1) {
6845 if (pci_find_capability(pdev, PCI_CAP_ID_MSI))
6846 bp->flags |= MSI_CAP_FLAG;
6849 /* 5708 cannot support DMA addresses > 40-bit. */
6850 if (CHIP_NUM(bp) == CHIP_NUM_5708)
6851 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
6853 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
6855 /* Configure DMA attributes. */
6856 if (pci_set_dma_mask(pdev, dma_mask) == 0) {
6857 dev->features |= NETIF_F_HIGHDMA;
6858 rc = pci_set_consistent_dma_mask(pdev, persist_dma_mask);
6861 "pci_set_consistent_dma_mask failed, aborting.\n");
6864 } else if ((rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK)) != 0) {
6865 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
6869 if (!(bp->flags & PCIE_FLAG))
6870 bnx2_get_pci_speed(bp);
6872 /* 5706A0 may falsely detect SERR and PERR. */
6873 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
6874 reg = REG_RD(bp, PCI_COMMAND);
6875 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
6876 REG_WR(bp, PCI_COMMAND, reg);
6878 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
6879 !(bp->flags & PCIX_FLAG)) {
6882 "5706 A1 can only be used in a PCIX bus, aborting.\n");
6886 bnx2_init_nvram(bp);
6888 reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
6890 if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
6891 BNX2_SHM_HDR_SIGNATURE_SIG) {
6892 u32 off = PCI_FUNC(pdev->devfn) << 2;
6894 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0 + off);
6896 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
6898 /* Get the permanent MAC address. First we need to make sure the
6899 * firmware is actually running.
6901 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
6903 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
6904 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
6905 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
6910 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
6911 for (i = 0, j = 0; i < 3; i++) {
6914 num = (u8) (reg >> (24 - (i * 8)));
6915 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
6916 if (num >= k || !skip0 || k == 1) {
6917 bp->fw_version[j++] = (num / k) + '0';
6922 bp->fw_version[j++] = '.';
6924 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE);
6925 if (reg & BNX2_PORT_FEATURE_WOL_ENABLED)
6928 if (reg & BNX2_PORT_FEATURE_ASF_ENABLED) {
6929 bp->flags |= ASF_ENABLE_FLAG;
6931 for (i = 0; i < 30; i++) {
6932 reg = REG_RD_IND(bp, bp->shmem_base +
6933 BNX2_BC_STATE_CONDITION);
6934 if (reg & BNX2_CONDITION_MFW_RUN_MASK)
6939 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_BC_STATE_CONDITION);
6940 reg &= BNX2_CONDITION_MFW_RUN_MASK;
6941 if (reg != BNX2_CONDITION_MFW_RUN_UNKNOWN &&
6942 reg != BNX2_CONDITION_MFW_RUN_NONE) {
6944 u32 addr = REG_RD_IND(bp, bp->shmem_base + BNX2_MFW_VER_PTR);
6946 bp->fw_version[j++] = ' ';
6947 for (i = 0; i < 3; i++) {
6948 reg = REG_RD_IND(bp, addr + i * 4);
6950 memcpy(&bp->fw_version[j], ®, 4);
6955 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
6956 bp->mac_addr[0] = (u8) (reg >> 8);
6957 bp->mac_addr[1] = (u8) reg;
6959 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
6960 bp->mac_addr[2] = (u8) (reg >> 24);
6961 bp->mac_addr[3] = (u8) (reg >> 16);
6962 bp->mac_addr[4] = (u8) (reg >> 8);
6963 bp->mac_addr[5] = (u8) reg;
6965 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
6967 bp->tx_ring_size = MAX_TX_DESC_CNT;
6968 bnx2_set_rx_ring_size(bp, 255);
6972 bp->tx_quick_cons_trip_int = 20;
6973 bp->tx_quick_cons_trip = 20;
6974 bp->tx_ticks_int = 80;
6977 bp->rx_quick_cons_trip_int = 6;
6978 bp->rx_quick_cons_trip = 6;
6979 bp->rx_ticks_int = 18;
6982 bp->stats_ticks = USEC_PER_SEC & BNX2_HC_STATS_TICKS_HC_STAT_TICKS;
6984 bp->timer_interval = HZ;
6985 bp->current_interval = HZ;
6989 /* Disable WOL support if we are running on a SERDES chip. */
6990 if (CHIP_NUM(bp) == CHIP_NUM_5709)
6991 bnx2_get_5709_media(bp);
6992 else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
6993 bp->phy_flags |= PHY_SERDES_FLAG;
6995 bp->phy_port = PORT_TP;
6996 if (bp->phy_flags & PHY_SERDES_FLAG) {
6997 bp->phy_port = PORT_FIBRE;
6998 reg = REG_RD_IND(bp, bp->shmem_base +
6999 BNX2_SHARED_HW_CFG_CONFIG);
7000 if (!(reg & BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX)) {
7001 bp->flags |= NO_WOL_FLAG;
7004 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
7006 if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
7007 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
7009 bnx2_init_remote_phy(bp);
7011 } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
7012 CHIP_NUM(bp) == CHIP_NUM_5708)
7013 bp->phy_flags |= PHY_CRC_FIX_FLAG;
7014 else if (CHIP_NUM(bp) == CHIP_NUM_5709 &&
7015 (CHIP_REV(bp) == CHIP_REV_Ax ||
7016 CHIP_REV(bp) == CHIP_REV_Bx))
7017 bp->phy_flags |= PHY_DIS_EARLY_DAC_FLAG;
7019 if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
7020 (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
7021 (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
7022 bp->flags |= NO_WOL_FLAG;
7026 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
7027 bp->tx_quick_cons_trip_int =
7028 bp->tx_quick_cons_trip;
7029 bp->tx_ticks_int = bp->tx_ticks;
7030 bp->rx_quick_cons_trip_int =
7031 bp->rx_quick_cons_trip;
7032 bp->rx_ticks_int = bp->rx_ticks;
7033 bp->comp_prod_trip_int = bp->comp_prod_trip;
7034 bp->com_ticks_int = bp->com_ticks;
7035 bp->cmd_ticks_int = bp->cmd_ticks;
7038 /* Disable MSI on 5706 if AMD 8132 bridge is found.
7040 * MSI is defined to be 32-bit write. The 5706 does 64-bit MSI writes
7041 * with byte enables disabled on the unused 32-bit word. This is legal
7042 * but causes problems on the AMD 8132 which will eventually stop
7043 * responding after a while.
7045 * AMD believes this incompatibility is unique to the 5706, and
7046 * prefers to locally disable MSI rather than globally disabling it.
7048 if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
7049 struct pci_dev *amd_8132 = NULL;
7051 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
7052 PCI_DEVICE_ID_AMD_8132_BRIDGE,
7055 if (amd_8132->revision >= 0x10 &&
7056 amd_8132->revision <= 0x13) {
7058 pci_dev_put(amd_8132);
7064 bnx2_set_default_link(bp);
7065 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
7067 init_timer(&bp->timer);
7068 bp->timer.expires = RUN_AT(bp->timer_interval);
7069 bp->timer.data = (unsigned long) bp;
7070 bp->timer.function = bnx2_timer;
7076 iounmap(bp->regview);
7081 pci_release_regions(pdev);
7084 pci_disable_device(pdev);
7085 pci_set_drvdata(pdev, NULL);
7091 static char * __devinit
7092 bnx2_bus_string(struct bnx2 *bp, char *str)
7096 if (bp->flags & PCIE_FLAG) {
7097 s += sprintf(s, "PCI Express");
7099 s += sprintf(s, "PCI");
7100 if (bp->flags & PCIX_FLAG)
7101 s += sprintf(s, "-X");
7102 if (bp->flags & PCI_32BIT_FLAG)
7103 s += sprintf(s, " 32-bit");
7105 s += sprintf(s, " 64-bit");
7106 s += sprintf(s, " %dMHz", bp->bus_speed_mhz);
7111 static int __devinit
7112 bnx2_init_napi(struct bnx2 *bp)
7114 struct bnx2_napi *bnapi = &bp->bnx2_napi;
7117 netif_napi_add(bp->dev, &bnapi->napi, bnx2_poll, 64);
7120 static int __devinit
7121 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7123 static int version_printed = 0;
7124 struct net_device *dev = NULL;
7128 DECLARE_MAC_BUF(mac);
7130 if (version_printed++ == 0)
7131 printk(KERN_INFO "%s", version);
7133 /* dev zeroed in init_etherdev */
7134 dev = alloc_etherdev(sizeof(*bp));
7139 rc = bnx2_init_board(pdev, dev);
7145 dev->open = bnx2_open;
7146 dev->hard_start_xmit = bnx2_start_xmit;
7147 dev->stop = bnx2_close;
7148 dev->get_stats = bnx2_get_stats;
7149 dev->set_multicast_list = bnx2_set_rx_mode;
7150 dev->do_ioctl = bnx2_ioctl;
7151 dev->set_mac_address = bnx2_change_mac_addr;
7152 dev->change_mtu = bnx2_change_mtu;
7153 dev->tx_timeout = bnx2_tx_timeout;
7154 dev->watchdog_timeo = TX_TIMEOUT;
7156 dev->vlan_rx_register = bnx2_vlan_rx_register;
7158 dev->ethtool_ops = &bnx2_ethtool_ops;
7160 bp = netdev_priv(dev);
7163 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
7164 dev->poll_controller = poll_bnx2;
7167 pci_set_drvdata(pdev, dev);
7169 memcpy(dev->dev_addr, bp->mac_addr, 6);
7170 memcpy(dev->perm_addr, bp->mac_addr, 6);
7171 bp->name = board_info[ent->driver_data].name;
7173 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
7174 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7175 dev->features |= NETIF_F_IPV6_CSUM;
7178 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7180 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
7181 if (CHIP_NUM(bp) == CHIP_NUM_5709)
7182 dev->features |= NETIF_F_TSO6;
7184 if ((rc = register_netdev(dev))) {
7185 dev_err(&pdev->dev, "Cannot register net device\n");
7187 iounmap(bp->regview);
7188 pci_release_regions(pdev);
7189 pci_disable_device(pdev);
7190 pci_set_drvdata(pdev, NULL);
7195 printk(KERN_INFO "%s: %s (%c%d) %s found at mem %lx, "
7196 "IRQ %d, node addr %s\n",
7199 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
7200 ((CHIP_ID(bp) & 0x0ff0) >> 4),
7201 bnx2_bus_string(bp, str),
7203 bp->pdev->irq, print_mac(mac, dev->dev_addr));
7208 static void __devexit
7209 bnx2_remove_one(struct pci_dev *pdev)
7211 struct net_device *dev = pci_get_drvdata(pdev);
7212 struct bnx2 *bp = netdev_priv(dev);
7214 flush_scheduled_work();
7216 unregister_netdev(dev);
7219 iounmap(bp->regview);
7222 pci_release_regions(pdev);
7223 pci_disable_device(pdev);
7224 pci_set_drvdata(pdev, NULL);
7228 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
7230 struct net_device *dev = pci_get_drvdata(pdev);
7231 struct bnx2 *bp = netdev_priv(dev);
7234 /* PCI register 4 needs to be saved whether netif_running() or not.
7235 * MSI address and data need to be saved if using MSI and
7238 pci_save_state(pdev);
7239 if (!netif_running(dev))
7242 flush_scheduled_work();
7243 bnx2_netif_stop(bp);
7244 netif_device_detach(dev);
7245 del_timer_sync(&bp->timer);
7246 if (bp->flags & NO_WOL_FLAG)
7247 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
7249 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
7251 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
7252 bnx2_reset_chip(bp, reset_code);
7254 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
7259 bnx2_resume(struct pci_dev *pdev)
7261 struct net_device *dev = pci_get_drvdata(pdev);
7262 struct bnx2 *bp = netdev_priv(dev);
7264 pci_restore_state(pdev);
7265 if (!netif_running(dev))
7268 bnx2_set_power_state(bp, PCI_D0);
7269 netif_device_attach(dev);
7271 bnx2_netif_start(bp);
7275 static struct pci_driver bnx2_pci_driver = {
7276 .name = DRV_MODULE_NAME,
7277 .id_table = bnx2_pci_tbl,
7278 .probe = bnx2_init_one,
7279 .remove = __devexit_p(bnx2_remove_one),
7280 .suspend = bnx2_suspend,
7281 .resume = bnx2_resume,
7284 static int __init bnx2_init(void)
7286 return pci_register_driver(&bnx2_pci_driver);
7289 static void __exit bnx2_cleanup(void)
7291 pci_unregister_driver(&bnx2_pci_driver);
7294 module_init(bnx2_init);
7295 module_exit(bnx2_cleanup);