2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com>
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
27 #include <linux/compiler.h>
28 #include <linux/ethtool.h>
29 #include <linux/if_vlan.h>
30 #include <linux/mii.h>
31 #include <linux/module.h>
32 #include <linux/skbuff.h>
33 #include <linux/spinlock.h>
34 #include <linux/timer.h>
35 #include <linux/types.h>
36 #include <linux/workqueue.h>
40 #define ATLX_DRIVER_NAME "atl1"
42 MODULE_DESCRIPTION("Atheros L1 Gigabit Ethernet Driver");
44 #define atlx_adapter atl1_adapter
45 #define atlx_check_for_link atl1_check_for_link
46 #define atlx_check_link atl1_check_link
47 #define atlx_hash_mc_addr atl1_hash_mc_addr
48 #define atlx_hash_set atl1_hash_set
49 #define atlx_hw atl1_hw
50 #define atlx_mii_ioctl atl1_mii_ioctl
51 #define atlx_read_phy_reg atl1_read_phy_reg
52 #define atlx_set_mac atl1_set_mac
53 #define atlx_set_mac_addr atl1_set_mac_addr
58 /* function prototypes needed by multiple files */
59 s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw);
60 s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data);
61 s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
62 s32 atl1_read_mac_addr(struct atl1_hw *hw);
63 s32 atl1_init_hw(struct atl1_hw *hw);
64 s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex);
65 s32 atl1_set_speed_and_duplex(struct atl1_hw *hw, u16 speed, u16 duplex);
66 u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr);
67 void atl1_hash_set(struct atl1_hw *hw, u32 hash_value);
68 s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data);
69 void atl1_set_mac_addr(struct atl1_hw *hw);
70 s32 atl1_phy_enter_power_saving(struct atl1_hw *hw);
71 s32 atl1_reset_hw(struct atl1_hw *hw);
72 void atl1_check_options(struct atl1_adapter *adapter);
73 static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
75 static u32 atl1_check_link(struct atl1_adapter *adapter);
76 s32 atl1_up(struct atl1_adapter *adapter);
77 void atl1_down(struct atl1_adapter *adapter);
78 int atl1_reset(struct atl1_adapter *adapter);
80 extern const struct ethtool_ops atl1_ethtool_ops;
82 /* hardware definitions specific to L1 */
84 /* Block IDLE Status Register */
85 #define IDLE_STATUS_RXMAC 0x1
86 #define IDLE_STATUS_TXMAC 0x2
87 #define IDLE_STATUS_RXQ 0x4
88 #define IDLE_STATUS_TXQ 0x8
89 #define IDLE_STATUS_DMAR 0x10
90 #define IDLE_STATUS_DMAW 0x20
91 #define IDLE_STATUS_SMB 0x40
92 #define IDLE_STATUS_CMB 0x80
94 /* MDIO Control Register */
95 #define MDIO_WAIT_TIMES 30
97 /* MAC Control Register */
98 #define MAC_CTRL_TX_PAUSE 0x10000
99 #define MAC_CTRL_SCNT 0x20000
100 #define MAC_CTRL_SRST_TX 0x40000
101 #define MAC_CTRL_TX_SIMURST 0x80000
102 #define MAC_CTRL_SPEED_SHIFT 20
103 #define MAC_CTRL_SPEED_MASK 0x300000
104 #define MAC_CTRL_SPEED_1000 0x2
105 #define MAC_CTRL_SPEED_10_100 0x1
106 #define MAC_CTRL_DBG_TX_BKPRESURE 0x400000
107 #define MAC_CTRL_TX_HUGE 0x800000
108 #define MAC_CTRL_RX_CHKSUM_EN 0x1000000
109 #define MAC_CTRL_DBG 0x8000000
111 /* Wake-On-Lan control register */
112 #define WOL_CLK_SWITCH_EN 0x8000
113 #define WOL_PT5_EN 0x200000
114 #define WOL_PT6_EN 0x400000
115 #define WOL_PT5_MATCH 0x8000000
116 #define WOL_PT6_MATCH 0x10000000
118 /* WOL Length ( 2 DWORD ) */
119 #define REG_WOL_PATTERN_LEN 0x14A4
120 #define WOL_PT_LEN_MASK 0x7F
121 #define WOL_PT0_LEN_SHIFT 0
122 #define WOL_PT1_LEN_SHIFT 8
123 #define WOL_PT2_LEN_SHIFT 16
124 #define WOL_PT3_LEN_SHIFT 24
125 #define WOL_PT4_LEN_SHIFT 0
126 #define WOL_PT5_LEN_SHIFT 8
127 #define WOL_PT6_LEN_SHIFT 16
129 /* Internal SRAM Partition Registers, low 32 bits */
130 #define REG_SRAM_RFD_LEN 0x1504
131 #define REG_SRAM_RRD_ADDR 0x1508
132 #define REG_SRAM_RRD_LEN 0x150C
133 #define REG_SRAM_TPD_ADDR 0x1510
134 #define REG_SRAM_TPD_LEN 0x1514
135 #define REG_SRAM_TRD_ADDR 0x1518
136 #define REG_SRAM_TRD_LEN 0x151C
137 #define REG_SRAM_RXF_ADDR 0x1520
138 #define REG_SRAM_RXF_LEN 0x1524
139 #define REG_SRAM_TXF_ADDR 0x1528
140 #define REG_SRAM_TXF_LEN 0x152C
141 #define REG_SRAM_TCPH_PATH_ADDR 0x1530
142 #define SRAM_TCPH_ADDR_MASK 0xFFF
143 #define SRAM_TCPH_ADDR_SHIFT 0
144 #define SRAM_PATH_ADDR_MASK 0xFFF
145 #define SRAM_PATH_ADDR_SHIFT 16
147 /* Load Ptr Register */
148 #define REG_LOAD_PTR 0x1534
150 /* Descriptor Control registers, low 32 bits */
151 #define REG_DESC_RFD_ADDR_LO 0x1544
152 #define REG_DESC_RRD_ADDR_LO 0x1548
153 #define REG_DESC_TPD_ADDR_LO 0x154C
154 #define REG_DESC_CMB_ADDR_LO 0x1550
155 #define REG_DESC_SMB_ADDR_LO 0x1554
156 #define REG_DESC_RFD_RRD_RING_SIZE 0x1558
157 #define DESC_RFD_RING_SIZE_MASK 0x7FF
158 #define DESC_RFD_RING_SIZE_SHIFT 0
159 #define DESC_RRD_RING_SIZE_MASK 0x7FF
160 #define DESC_RRD_RING_SIZE_SHIFT 16
161 #define REG_DESC_TPD_RING_SIZE 0x155C
162 #define DESC_TPD_RING_SIZE_MASK 0x3FF
163 #define DESC_TPD_RING_SIZE_SHIFT 0
165 /* TXQ Control Register */
166 #define REG_TXQ_CTRL 0x1580
167 #define TXQ_CTRL_TPD_BURST_NUM_SHIFT 0
168 #define TXQ_CTRL_TPD_BURST_NUM_MASK 0x1F
169 #define TXQ_CTRL_EN 0x20
170 #define TXQ_CTRL_ENH_MODE 0x40
171 #define TXQ_CTRL_TPD_FETCH_TH_SHIFT 8
172 #define TXQ_CTRL_TPD_FETCH_TH_MASK 0x3F
173 #define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16
174 #define TXQ_CTRL_TXF_BURST_NUM_MASK 0xFFFF
176 /* Jumbo packet Threshold for task offload */
177 #define REG_TX_JUMBO_TASK_TH_TPD_IPG 0x1584
178 #define TX_JUMBO_TASK_TH_MASK 0x7FF
179 #define TX_JUMBO_TASK_TH_SHIFT 0
180 #define TX_TPD_MIN_IPG_MASK 0x1F
181 #define TX_TPD_MIN_IPG_SHIFT 16
183 /* RXQ Control Register */
184 #define REG_RXQ_CTRL 0x15A0
185 #define RXQ_CTRL_RFD_BURST_NUM_SHIFT 0
186 #define RXQ_CTRL_RFD_BURST_NUM_MASK 0xFF
187 #define RXQ_CTRL_RRD_BURST_THRESH_SHIFT 8
188 #define RXQ_CTRL_RRD_BURST_THRESH_MASK 0xFF
189 #define RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT 16
190 #define RXQ_CTRL_RFD_PREF_MIN_IPG_MASK 0x1F
191 #define RXQ_CTRL_CUT_THRU_EN 0x40000000
192 #define RXQ_CTRL_EN 0x80000000
194 /* Rx jumbo packet threshold and rrd retirement timer */
195 #define REG_RXQ_JMBOSZ_RRDTIM 0x15A4
196 #define RXQ_JMBOSZ_TH_MASK 0x7FF
197 #define RXQ_JMBOSZ_TH_SHIFT 0
198 #define RXQ_JMBO_LKAH_MASK 0xF
199 #define RXQ_JMBO_LKAH_SHIFT 11
200 #define RXQ_RRD_TIMER_MASK 0xFFFF
201 #define RXQ_RRD_TIMER_SHIFT 16
203 /* RFD flow control register */
204 #define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
205 #define RXQ_RXF_PAUSE_TH_HI_SHIFT 16
206 #define RXQ_RXF_PAUSE_TH_HI_MASK 0xFFF
207 #define RXQ_RXF_PAUSE_TH_LO_SHIFT 0
208 #define RXQ_RXF_PAUSE_TH_LO_MASK 0xFFF
210 /* RRD flow control register */
211 #define REG_RXQ_RRD_PAUSE_THRESH 0x15AC
212 #define RXQ_RRD_PAUSE_TH_HI_SHIFT 0
213 #define RXQ_RRD_PAUSE_TH_HI_MASK 0xFFF
214 #define RXQ_RRD_PAUSE_TH_LO_SHIFT 16
215 #define RXQ_RRD_PAUSE_TH_LO_MASK 0xFFF
217 /* DMA Engine Control Register */
218 #define REG_DMA_CTRL 0x15C0
219 #define DMA_CTRL_DMAR_IN_ORDER 0x1
220 #define DMA_CTRL_DMAR_ENH_ORDER 0x2
221 #define DMA_CTRL_DMAR_OUT_ORDER 0x4
222 #define DMA_CTRL_RCB_VALUE 0x8
223 #define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
224 #define DMA_CTRL_DMAR_BURST_LEN_MASK 7
225 #define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
226 #define DMA_CTRL_DMAW_BURST_LEN_MASK 7
227 #define DMA_CTRL_DMAR_EN 0x400
228 #define DMA_CTRL_DMAW_EN 0x800
230 /* CMB/SMB Control Register */
231 #define REG_CSMB_CTRL 0x15D0
232 #define CSMB_CTRL_CMB_NOW 1
233 #define CSMB_CTRL_SMB_NOW 2
234 #define CSMB_CTRL_CMB_EN 4
235 #define CSMB_CTRL_SMB_EN 8
237 /* CMB DMA Write Threshold Register */
238 #define REG_CMB_WRITE_TH 0x15D4
239 #define CMB_RRD_TH_SHIFT 0
240 #define CMB_RRD_TH_MASK 0x7FF
241 #define CMB_TPD_TH_SHIFT 16
242 #define CMB_TPD_TH_MASK 0x7FF
244 /* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
245 #define REG_CMB_WRITE_TIMER 0x15D8
246 #define CMB_RX_TM_SHIFT 0
247 #define CMB_RX_TM_MASK 0xFFFF
248 #define CMB_TX_TM_SHIFT 16
249 #define CMB_TX_TM_MASK 0xFFFF
251 /* Number of packet received since last CMB write */
252 #define REG_CMB_RX_PKT_CNT 0x15DC
254 /* Number of packet transmitted since last CMB write */
255 #define REG_CMB_TX_PKT_CNT 0x15E0
257 /* SMB auto DMA timer register */
258 #define REG_SMB_TIMER 0x15E4
260 /* Mailbox Register */
261 #define REG_MAILBOX 0x15F0
262 #define MB_RFD_PROD_INDX_SHIFT 0
263 #define MB_RFD_PROD_INDX_MASK 0x7FF
264 #define MB_RRD_CONS_INDX_SHIFT 11
265 #define MB_RRD_CONS_INDX_MASK 0x7FF
266 #define MB_TPD_PROD_INDX_SHIFT 22
267 #define MB_TPD_PROD_INDX_MASK 0x3FF
269 /* Interrupt Status Register */
271 #define ISR_TIMER 0x2
272 #define ISR_MANUAL 0x4
273 #define ISR_RXF_OV 0x8
274 #define ISR_RFD_UNRUN 0x10
275 #define ISR_RRD_OV 0x20
276 #define ISR_TXF_UNRUN 0x40
277 #define ISR_LINK 0x80
278 #define ISR_HOST_RFD_UNRUN 0x100
279 #define ISR_HOST_RRD_OV 0x200
280 #define ISR_DMAR_TO_RST 0x400
281 #define ISR_DMAW_TO_RST 0x800
282 #define ISR_GPHY 0x1000
283 #define ISR_RX_PKT 0x10000
284 #define ISR_TX_PKT 0x20000
285 #define ISR_TX_DMA 0x40000
286 #define ISR_RX_DMA 0x80000
287 #define ISR_CMB_RX 0x100000
288 #define ISR_CMB_TX 0x200000
289 #define ISR_MAC_RX 0x400000
290 #define ISR_MAC_TX 0x800000
291 #define ISR_DIS_SMB 0x20000000
292 #define ISR_DIS_DMA 0x40000000
294 /* Normal Interrupt mask */
295 #define IMR_NORMAL_MASK (\
304 /* Debug Interrupt Mask (enable all interrupt) */
305 #define IMR_DEBUG_MASK (\
321 #define MEDIA_TYPE_1000M_FULL 1
322 #define MEDIA_TYPE_100M_FULL 2
323 #define MEDIA_TYPE_100M_HALF 3
324 #define MEDIA_TYPE_10M_FULL 4
325 #define MEDIA_TYPE_10M_HALF 5
327 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* All but 1000-Half */
329 #define MAX_JUMBO_FRAME_SIZE 10240
331 #define ATL1_EEDUMP_LEN 48
333 /* Statistics counters collected by the MAC */
334 struct stats_msg_block {
336 u32 rx_ok; /* good RX packets */
337 u32 rx_bcast; /* good RX broadcast packets */
338 u32 rx_mcast; /* good RX multicast packets */
339 u32 rx_pause; /* RX pause frames */
340 u32 rx_ctrl; /* RX control packets other than pause frames */
341 u32 rx_fcs_err; /* RX packets with bad FCS */
342 u32 rx_len_err; /* RX packets with length != actual size */
343 u32 rx_byte_cnt; /* good bytes received. FCS is NOT included */
344 u32 rx_runt; /* RX packets < 64 bytes with good FCS */
345 u32 rx_frag; /* RX packets < 64 bytes with bad FCS */
346 u32 rx_sz_64; /* 64 byte RX packets */
352 u32 rx_sz_1519_max; /* 1519 byte to MTU RX packets */
353 u32 rx_sz_ov; /* truncated RX packets > MTU */
354 u32 rx_rxf_ov; /* frames dropped due to RX FIFO overflow */
355 u32 rx_rrd_ov; /* frames dropped due to RRD overflow */
356 u32 rx_align_err; /* alignment errors */
357 u32 rx_bcast_byte_cnt; /* RX broadcast bytes, excluding FCS */
358 u32 rx_mcast_byte_cnt; /* RX multicast bytes, excluding FCS */
359 u32 rx_err_addr; /* packets dropped due to address filtering */
362 u32 tx_ok; /* good TX packets */
363 u32 tx_bcast; /* good TX broadcast packets */
364 u32 tx_mcast; /* good TX multicast packets */
365 u32 tx_pause; /* TX pause frames */
366 u32 tx_exc_defer; /* TX packets deferred excessively */
367 u32 tx_ctrl; /* TX control frames, excluding pause frames */
368 u32 tx_defer; /* TX packets deferred */
369 u32 tx_byte_cnt; /* bytes transmitted, FCS is NOT included */
370 u32 tx_sz_64; /* 64 byte TX packets */
376 u32 tx_sz_1519_max; /* 1519 byte to MTU TX packets */
377 u32 tx_1_col; /* packets TX after a single collision */
378 u32 tx_2_col; /* packets TX after multiple collisions */
379 u32 tx_late_col; /* TX packets with late collisions */
380 u32 tx_abort_col; /* TX packets aborted w/excessive collisions */
381 u32 tx_underrun; /* TX packets aborted due to TX FIFO underrun
382 * or TRD FIFO underrun */
383 u32 tx_rd_eop; /* reads beyond the EOP into the next frame
384 * when TRD was not written timely */
385 u32 tx_len_err; /* TX packets where length != actual size */
386 u32 tx_trunc; /* TX packets truncated due to size > MTU */
387 u32 tx_bcast_byte; /* broadcast bytes transmitted, excluding FCS */
388 u32 tx_mcast_byte; /* multicast bytes transmitted, excluding FCS */
389 u32 smb_updated; /* 1: SMB Updated. This is used by software to
390 * indicate the statistics update. Software
391 * should clear this bit after retrieving the
392 * statistics information. */
395 /* Coalescing Message Block */
396 struct coals_msg_block {
397 u32 int_stats; /* interrupt status */
398 u16 rrd_prod_idx; /* TRD Producer Index. */
399 u16 rfd_cons_idx; /* RFD Consumer Index. */
400 u16 update; /* Selene sets this bit every time it DMAs the
401 * CMB to host memory. Software should clear
402 * this bit when CMB info is processed. */
403 u16 tpd_cons_idx; /* TPD Consumer Index. */
407 struct rx_return_desc {
408 u8 num_buf; /* Number of RFD buffers used by the received packet */
410 u16 buf_indx; /* RFD Index of the first buffer */
419 u16 pkt_flg; /* Packet flags */
420 u16 err_flg; /* Error flags */
422 u16 vlan_tag; /* VLAN TAG */
425 #define PACKET_FLAG_ETH_TYPE 0x0080
426 #define PACKET_FLAG_VLAN_INS 0x0100
427 #define PACKET_FLAG_ERR 0x0200
428 #define PACKET_FLAG_IPV4 0x0400
429 #define PACKET_FLAG_UDP 0x0800
430 #define PACKET_FLAG_TCP 0x1000
431 #define PACKET_FLAG_BCAST 0x2000
432 #define PACKET_FLAG_MCAST 0x4000
433 #define PACKET_FLAG_PAUSE 0x8000
435 #define ERR_FLAG_CRC 0x0001
436 #define ERR_FLAG_CODE 0x0002
437 #define ERR_FLAG_DRIBBLE 0x0004
438 #define ERR_FLAG_RUNT 0x0008
439 #define ERR_FLAG_OV 0x0010
440 #define ERR_FLAG_TRUNC 0x0020
441 #define ERR_FLAG_IP_CHKSUM 0x0040
442 #define ERR_FLAG_L4_CHKSUM 0x0080
443 #define ERR_FLAG_LEN 0x0100
444 #define ERR_FLAG_DES_ADDR 0x0200
447 struct rx_free_desc {
448 __le64 buffer_addr; /* Address of the descriptor's data buffer */
449 __le16 buf_len; /* Size of the receive buffer in host memory */
450 u16 coalese; /* Update consumer index to host after the
451 * reception of this frame */
452 /* __attribute__ ((packed)) is required */
453 } __attribute__ ((packed));
456 * The L1 transmit packet descriptor is comprised of four 32-bit words.
459 * +---------------------------------------+
460 * | Word 0: Buffer addr lo |
461 * +---------------------------------------+
462 * | Word 1: Buffer addr hi |
463 * +---------------------------------------+
465 * +---------------------------------------+
467 * +---------------------------------------+
469 * Words 0 and 1 combine to form a 64-bit buffer address.
471 * Word 2 is self explanatory in the #define block below.
473 * Word 3 has two forms, depending upon the state of bits 3 and 4.
474 * If bits 3 and 4 are both zero, then bits 14:31 are unused by the
475 * hardware. Otherwise, if either bit 3 or 4 is set, the definition
476 * of bits 14:31 vary according to the following depiction.
478 * 0 End of packet 0 End of packet
479 * 1 Coalesce 1 Coalesce
480 * 2 Insert VLAN tag 2 Insert VLAN tag
481 * 3 Custom csum enable = 0 3 Custom csum enable = 1
482 * 4 Segment enable = 1 4 Segment enable = 0
483 * 5 Generate IP checksum 5 Generate IP checksum
484 * 6 Generate TCP checksum 6 Generate TCP checksum
485 * 7 Generate UDP checksum 7 Generate UDP checksum
486 * 8 VLAN tagged 8 VLAN tagged
487 * 9 Ethernet frame type 9 Ethernet frame type
489 * 11 | IP hdr length (10:13) 11 | IP hdr length (10:13)
490 * 12 | (num 32-bit words) 12 | (num 32-bit words)
493 * 15 | TCP hdr length (14:17) 15 Unused
494 * 16 | (num 32-bit words) 16-+
496 * 18 Header TPD flag 18 |
497 * 19-+ 19 | Payload offset
503 * 25 | MSS (19:31) 25 |
505 * 27 | 27 | Custom csum offset
513 #define TPD_BUFLEN_MASK 0x3FFF
514 #define TPD_BUFLEN_SHIFT 0
515 #define TPD_DMAINT_MASK 0x0001
516 #define TPD_DMAINT_SHIFT 14
517 #define TPD_PKTNT_MASK 0x0001
518 #define TPD_PKTINT_SHIFT 15
519 #define TPD_VLANTAG_MASK 0xFFFF
520 #define TPD_VLAN_SHIFT 16
522 /* tpd word 3 bits 0:13 */
523 #define TPD_EOP_MASK 0x0001
524 #define TPD_EOP_SHIFT 0
525 #define TPD_COALESCE_MASK 0x0001
526 #define TPD_COALESCE_SHIFT 1
527 #define TPD_INS_VL_TAG_MASK 0x0001
528 #define TPD_INS_VL_TAG_SHIFT 2
529 #define TPD_CUST_CSUM_EN_MASK 0x0001
530 #define TPD_CUST_CSUM_EN_SHIFT 3
531 #define TPD_SEGMENT_EN_MASK 0x0001
532 #define TPD_SEGMENT_EN_SHIFT 4
533 #define TPD_IP_CSUM_MASK 0x0001
534 #define TPD_IP_CSUM_SHIFT 5
535 #define TPD_TCP_CSUM_MASK 0x0001
536 #define TPD_TCP_CSUM_SHIFT 6
537 #define TPD_UDP_CSUM_MASK 0x0001
538 #define TPD_UDP_CSUM_SHIFT 7
539 #define TPD_VL_TAGGED_MASK 0x0001
540 #define TPD_VL_TAGGED_SHIFT 8
541 #define TPD_ETHTYPE_MASK 0x0001
542 #define TPD_ETHTYPE_SHIFT 9
543 #define TPD_IPHL_MASK 0x000F
544 #define TPD_IPHL_SHIFT 10
546 /* tpd word 3 bits 14:31 if segment enabled */
547 #define TPD_TCPHDRLEN_MASK 0x000F
548 #define TPD_TCPHDRLEN_SHIFT 14
549 #define TPD_HDRFLAG_MASK 0x0001
550 #define TPD_HDRFLAG_SHIFT 18
551 #define TPD_MSS_MASK 0x1FFF
552 #define TPD_MSS_SHIFT 19
554 /* tpd word 3 bits 16:31 if custom csum enabled */
555 #define TPD_PLOADOFFSET_MASK 0x00FF
556 #define TPD_PLOADOFFSET_SHIFT 16
557 #define TPD_CCSUMOFFSET_MASK 0x00FF
558 #define TPD_CCSUMOFFSET_SHIFT 24
560 struct tx_packet_desc {
566 /* DMA Order Settings */
567 enum atl1_dma_order {
569 atl1_dma_ord_enh = 2,
578 enum atl1_dma_req_block {
579 atl1_dma_req_128 = 0,
580 atl1_dma_req_256 = 1,
581 atl1_dma_req_512 = 2,
582 atl1_dma_req_1024 = 3,
583 atl1_dma_req_2048 = 4,
584 atl1_dma_req_4096 = 5
587 #define ATL1_MAX_INTR 3
588 #define ATL1_MAX_TX_BUF_LEN 0x3000 /* 12288 bytes */
590 #define ATL1_DEFAULT_TPD 256
591 #define ATL1_MAX_TPD 1024
592 #define ATL1_MIN_TPD 64
593 #define ATL1_DEFAULT_RFD 512
594 #define ATL1_MIN_RFD 128
595 #define ATL1_MAX_RFD 2048
596 #define ATL1_REG_COUNT 1538
598 #define ATL1_GET_DESC(R, i, type) (&(((type *)((R)->desc))[i]))
599 #define ATL1_RFD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_free_desc)
600 #define ATL1_TPD_DESC(R, i) ATL1_GET_DESC(R, i, struct tx_packet_desc)
601 #define ATL1_RRD_DESC(R, i) ATL1_GET_DESC(R, i, struct rx_return_desc)
604 * atl1_ring_header represents a single, contiguous block of DMA space
605 * mapped for the three descriptor rings (tpd, rfd, rrd) and the two
606 * message blocks (cmb, smb) described below
608 struct atl1_ring_header {
609 void *desc; /* virtual address */
610 dma_addr_t dma; /* physical address*/
611 unsigned int size; /* length in bytes */
615 * atl1_buffer is wrapper around a pointer to a socket buffer
616 * so a DMA handle can be stored along with the skb
619 struct sk_buff *skb; /* socket buffer */
620 u16 length; /* rx buffer length */
621 u16 alloced; /* 1 if skb allocated */
625 /* transmit packet descriptor (tpd) ring */
626 struct atl1_tpd_ring {
627 void *desc; /* descriptor ring virtual address */
628 dma_addr_t dma; /* descriptor ring physical address */
629 u16 size; /* descriptor ring length in bytes */
630 u16 count; /* number of descriptors in the ring */
631 u16 hw_idx; /* hardware index */
632 atomic_t next_to_clean;
633 atomic_t next_to_use;
634 struct atl1_buffer *buffer_info;
637 /* receive free descriptor (rfd) ring */
638 struct atl1_rfd_ring {
639 void *desc; /* descriptor ring virtual address */
640 dma_addr_t dma; /* descriptor ring physical address */
641 u16 size; /* descriptor ring length in bytes */
642 u16 count; /* number of descriptors in the ring */
643 atomic_t next_to_use;
645 struct atl1_buffer *buffer_info;
648 /* receive return descriptor (rrd) ring */
649 struct atl1_rrd_ring {
650 void *desc; /* descriptor ring virtual address */
651 dma_addr_t dma; /* descriptor ring physical address */
652 unsigned int size; /* descriptor ring length in bytes */
653 u16 count; /* number of descriptors in the ring */
655 atomic_t next_to_clean;
658 /* coalescing message block (cmb) */
660 struct coals_msg_block *cmb;
664 /* statistics message block (smb) */
666 struct stats_msg_block *smb;
670 /* Statistics counters */
671 struct atl1_sft_stats {
679 u64 rx_length_errors;
683 u64 rx_missed_errors;
686 u64 tx_aborted_errors;
687 u64 tx_window_errors;
688 u64 tx_carrier_errors;
689 u64 tx_pause; /* TX pause frames */
690 u64 excecol; /* TX packets w/ excessive collisions */
691 u64 deffer; /* TX packets deferred */
692 u64 scc; /* packets TX after a single collision */
693 u64 mcc; /* packets TX after multiple collisions */
694 u64 latecol; /* TX packets w/ late collisions */
695 u64 tx_underun; /* TX packets aborted due to TX FIFO underrun
696 * or TRD FIFO underrun */
697 u64 tx_trunc; /* TX packets truncated due to size > MTU */
698 u64 rx_pause; /* num Pause packets received. */
703 /* hardware structure */
706 struct atl1_adapter *back;
707 enum atl1_dma_order dma_ord;
708 enum atl1_dma_rcb rcb_value;
709 enum atl1_dma_req_block dmar_block;
710 enum atl1_dma_req_block dmaw_block;
713 u8 jam_ipg; /* IPG to start JAM for collision based flow
714 * control in half-duplex mode. In units of
716 u8 ipgt; /* Desired back to back inter-packet gap.
717 * The default is 96-bit time */
718 u8 min_ifg; /* Minimum number of IFG to enforce in between
719 * receive frames. Frame gap below such IFP
721 u8 ipgr1; /* 64bit Carrier-Sense window */
722 u8 ipgr2; /* 96-bit IPG window */
723 u8 tpd_burst; /* Number of TPD to prefetch in cache-aligned
724 * burst. Each TPD is 16 bytes long */
725 u8 rfd_burst; /* Number of RFD to prefetch in cache-aligned
726 * burst. Each RFD is 12 bytes long */
728 u8 rrd_burst; /* Threshold number of RRDs that can be retired
729 * in a burst. Each RRD is 16 bytes long */
732 u16 tx_jumbo_task_th;
733 u16 txf_burst; /* Number of data bytes to read in a cache-
734 * aligned burst. Each SRAM entry is 8 bytes */
735 u16 rx_jumbo_th; /* Jumbo packet size for non-VLAN packet. VLAN
736 * packets should add 4 bytes */
738 u16 rrd_ret_timer; /* RRD retirement timer. Decrement by 1 after
739 * every 512ns passes. */
740 u16 lcol; /* Collision Window */
748 u16 autoneg_advertised;
750 u16 mii_autoneg_adv_reg;
751 u16 mii_1000t_ctrl_reg;
761 u8 mac_addr[ETH_ALEN];
762 u8 perm_mac_addr[ETH_ALEN];
767 struct atl1_adapter {
768 struct net_device *netdev;
769 struct pci_dev *pdev;
770 struct net_device_stats net_stats;
771 struct atl1_sft_stats soft_stats;
772 struct vlan_group *vlgrp;
778 struct work_struct tx_timeout_task;
779 struct work_struct link_chg_task;
780 struct work_struct pcie_dma_to_rst_task;
781 struct timer_list watchdog_timer;
782 struct timer_list phy_config_timer;
783 bool phy_timer_pending;
785 /* all descriptor rings' memory */
786 struct atl1_ring_header ring_header;
789 struct atl1_tpd_ring tpd_ring;
793 struct atl1_rfd_ring rfd_ring;
794 struct atl1_rrd_ring rrd_ring;
798 u16 imt; /* interrupt moderator timer (2us resolution) */
799 u16 ict; /* interrupt clear timer (2us resolution */
800 struct mii_if_info mii; /* MII interface info */
802 u32 bd_number; /* board number */