2 * Ethernet driver for the Atmel AT91RM9200 (Thunder)
4 * Copyright (C) 2003 SAN People (Pty) Ltd
6 * Based on an earlier Atmel EMAC macrocell driver by Atmel and Lineo Inc.
7 * Initial version by Rick Bronson 01/11/2003
9 * Intel LXT971A PHY support by Christopher Bahns & David Knickerbocker
10 * (Polaroid Corporation)
12 * Realtek RTL8201(B)L PHY support by Roman Avramenko <roman@imsystems.ru>
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License
16 * as published by the Free Software Foundation; either version
17 * 2 of the License, or (at your option) any later version.
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/mii.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/skbuff.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/ethtool.h>
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
32 #include <asm/uaccess.h>
33 #include <asm/mach-types.h>
35 #include <asm/arch/at91rm9200_emac.h>
36 #include <asm/arch/gpio.h>
37 #include <asm/arch/board.h>
39 #include "at91_ether.h"
41 #define DRV_NAME "at91_ether"
42 #define DRV_VERSION "1.0"
44 static struct timer_list check_timer;
45 #define LINK_POLL_INTERVAL (HZ)
47 /* ..................................................................... */
50 * Read from a EMAC register.
52 static inline unsigned long at91_emac_read(unsigned int reg)
54 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
56 return __raw_readl(emac_base + reg);
60 * Write to a EMAC register.
62 static inline void at91_emac_write(unsigned int reg, unsigned long value)
64 void __iomem *emac_base = (void __iomem *)AT91_VA_BASE_EMAC;
66 __raw_writel(value, emac_base + reg);
69 /* ........................... PHY INTERFACE ........................... */
72 * Enable the MDIO bit in MAC control register
73 * When not called from an interrupt-handler, access to the PHY must be
74 * protected by a spinlock.
76 static void enable_mdi(void)
80 ctl = at91_emac_read(AT91_EMAC_CTL);
81 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_MPE); /* enable management port */
85 * Disable the MDIO bit in the MAC control register
87 static void disable_mdi(void)
91 ctl = at91_emac_read(AT91_EMAC_CTL);
92 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_MPE); /* disable management port */
96 * Wait until the PHY operation is complete.
98 static inline void at91_phy_wait(void) {
99 unsigned long timeout = jiffies + 2;
101 while (!(at91_emac_read(AT91_EMAC_SR) & AT91_EMAC_SR_IDLE)) {
102 if (time_after(jiffies, timeout)) {
103 printk("at91_ether: MIO timeout\n");
111 * Write value to the a PHY register
112 * Note: MDI interface is assumed to already have been enabled.
114 static void write_phy(unsigned char phy_addr, unsigned char address, unsigned int value)
116 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_W
117 | ((phy_addr & 0x1f) << 23) | (address << 18) | (value & AT91_EMAC_DATA));
119 /* Wait until IDLE bit in Network Status register is cleared */
124 * Read value stored in a PHY register.
125 * Note: MDI interface is assumed to already have been enabled.
127 static void read_phy(unsigned char phy_addr, unsigned char address, unsigned int *value)
129 at91_emac_write(AT91_EMAC_MAN, AT91_EMAC_MAN_802_3 | AT91_EMAC_RW_R
130 | ((phy_addr & 0x1f) << 23) | (address << 18));
132 /* Wait until IDLE bit in Network Status register is cleared */
135 *value = at91_emac_read(AT91_EMAC_MAN) & AT91_EMAC_DATA;
138 /* ........................... PHY MANAGEMENT .......................... */
141 * Access the PHY to determine the current link speed and mode, and update the
143 * If no link or auto-negotiation is busy, then no changes are made.
145 static void update_linkspeed(struct net_device *dev, int silent)
147 struct at91_private *lp = netdev_priv(dev);
148 unsigned int bmsr, bmcr, lpa, mac_cfg;
149 unsigned int speed, duplex;
151 if (!mii_link_ok(&lp->mii)) { /* no link */
152 netif_carrier_off(dev);
154 printk(KERN_INFO "%s: Link down.\n", dev->name);
158 /* Link up, or auto-negotiation still in progress */
159 read_phy(lp->phy_address, MII_BMSR, &bmsr);
160 read_phy(lp->phy_address, MII_BMCR, &bmcr);
161 if (bmcr & BMCR_ANENABLE) { /* AutoNegotiation is enabled */
162 if (!(bmsr & BMSR_ANEGCOMPLETE))
163 return; /* Do nothing - another interrupt generated when negotiation complete */
165 read_phy(lp->phy_address, MII_LPA, &lpa);
166 if ((lpa & LPA_100FULL) || (lpa & LPA_100HALF)) speed = SPEED_100;
167 else speed = SPEED_10;
168 if ((lpa & LPA_100FULL) || (lpa & LPA_10FULL)) duplex = DUPLEX_FULL;
169 else duplex = DUPLEX_HALF;
171 speed = (bmcr & BMCR_SPEED100) ? SPEED_100 : SPEED_10;
172 duplex = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
176 mac_cfg = at91_emac_read(AT91_EMAC_CFG) & ~(AT91_EMAC_SPD | AT91_EMAC_FD);
177 if (speed == SPEED_100) {
178 if (duplex == DUPLEX_FULL) /* 100 Full Duplex */
179 mac_cfg |= AT91_EMAC_SPD | AT91_EMAC_FD;
180 else /* 100 Half Duplex */
181 mac_cfg |= AT91_EMAC_SPD;
183 if (duplex == DUPLEX_FULL) /* 10 Full Duplex */
184 mac_cfg |= AT91_EMAC_FD;
185 else {} /* 10 Half Duplex */
187 at91_emac_write(AT91_EMAC_CFG, mac_cfg);
190 printk(KERN_INFO "%s: Link now %i-%s\n", dev->name, speed, (duplex == DUPLEX_FULL) ? "FullDuplex" : "HalfDuplex");
191 netif_carrier_on(dev);
195 * Handle interrupts from the PHY
197 static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id)
199 struct net_device *dev = (struct net_device *) dev_id;
200 struct at91_private *lp = netdev_priv(dev);
204 * This hander is triggered on both edges, but the PHY chips expect
205 * level-triggering. We therefore have to check if the PHY actually has
209 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
210 read_phy(lp->phy_address, MII_DSINTR_REG, &phy); /* ack interrupt in Davicom PHY */
211 if (!(phy & (1 << 0)))
214 else if (lp->phy_type == MII_LXT971A_ID) {
215 read_phy(lp->phy_address, MII_ISINTS_REG, &phy); /* ack interrupt in Intel PHY */
216 if (!(phy & (1 << 2)))
219 else if (lp->phy_type == MII_BCM5221_ID) {
220 read_phy(lp->phy_address, MII_BCMINTR_REG, &phy); /* ack interrupt in Broadcom PHY */
221 if (!(phy & (1 << 0)))
224 else if (lp->phy_type == MII_KS8721_ID) {
225 read_phy(lp->phy_address, MII_TPISTATUS, &phy); /* ack interrupt in Micrel PHY */
226 if (!(phy & ((1 << 2) | 1)))
230 update_linkspeed(dev, 0);
239 * Initialize and enable the PHY interrupt for link-state changes
241 static void enable_phyirq(struct net_device *dev)
243 struct at91_private *lp = netdev_priv(dev);
244 unsigned int dsintr, irq_number;
247 irq_number = lp->board_data.phy_irq_pin;
250 * PHY doesn't have an IRQ pin (RTL8201, DP83847, AC101L),
251 * or board does not have it connected.
253 check_timer.expires = jiffies + LINK_POLL_INTERVAL;
254 add_timer(&check_timer);
258 status = request_irq(irq_number, at91ether_phy_interrupt, 0, dev->name, dev);
260 printk(KERN_ERR "at91_ether: PHY IRQ %d request failed - status %d!\n", irq_number, status);
264 spin_lock_irq(&lp->lock);
267 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
268 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
269 dsintr = dsintr & ~0xf00; /* clear bits 8..11 */
270 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
272 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
273 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
274 dsintr = dsintr | 0xf2; /* set bits 1, 4..7 */
275 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
277 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
278 dsintr = (1 << 15) | ( 1 << 14);
279 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
281 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
282 dsintr = (1 << 10) | ( 1 << 8);
283 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
287 spin_unlock_irq(&lp->lock);
291 * Disable the PHY interrupt
293 static void disable_phyirq(struct net_device *dev)
295 struct at91_private *lp = netdev_priv(dev);
297 unsigned int irq_number;
299 irq_number = lp->board_data.phy_irq_pin;
301 del_timer_sync(&check_timer);
305 spin_lock_irq(&lp->lock);
308 if ((lp->phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) { /* for Davicom PHY */
309 read_phy(lp->phy_address, MII_DSINTR_REG, &dsintr);
310 dsintr = dsintr | 0xf00; /* set bits 8..11 */
311 write_phy(lp->phy_address, MII_DSINTR_REG, dsintr);
313 else if (lp->phy_type == MII_LXT971A_ID) { /* for Intel PHY */
314 read_phy(lp->phy_address, MII_ISINTE_REG, &dsintr);
315 dsintr = dsintr & ~0xf2; /* clear bits 1, 4..7 */
316 write_phy(lp->phy_address, MII_ISINTE_REG, dsintr);
318 else if (lp->phy_type == MII_BCM5221_ID) { /* for Broadcom PHY */
319 read_phy(lp->phy_address, MII_BCMINTR_REG, &dsintr);
321 write_phy(lp->phy_address, MII_BCMINTR_REG, dsintr);
323 else if (lp->phy_type == MII_KS8721_ID) { /* for Micrel PHY */
324 read_phy(lp->phy_address, MII_TPISTATUS, &dsintr);
325 dsintr = ~((1 << 10) | (1 << 8));
326 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
330 spin_unlock_irq(&lp->lock);
332 free_irq(irq_number, dev); /* Free interrupt handler */
336 * Perform a software reset of the PHY.
339 static void reset_phy(struct net_device *dev)
341 struct at91_private *lp = netdev_priv(dev);
344 spin_lock_irq(&lp->lock);
347 /* Perform PHY reset */
348 write_phy(lp->phy_address, MII_BMCR, BMCR_RESET);
350 /* Wait until PHY reset is complete */
352 read_phy(lp->phy_address, MII_BMCR, &bmcr);
353 } while (!(bmcr && BMCR_RESET));
356 spin_unlock_irq(&lp->lock);
360 static void at91ether_check_link(unsigned long dev_id)
362 struct net_device *dev = (struct net_device *) dev_id;
365 update_linkspeed(dev, 1);
368 check_timer.expires = jiffies + LINK_POLL_INTERVAL;
369 add_timer(&check_timer);
372 /* ......................... ADDRESS MANAGEMENT ........................ */
375 * NOTE: Your bootloader must always set the MAC address correctly before
376 * booting into Linux.
378 * - It must always set the MAC address after reset, even if it doesn't
379 * happen to access the Ethernet while it's booting. Some versions of
380 * U-Boot on the AT91RM9200-DK do not do this.
382 * - Likewise it must store the addresses in the correct byte order.
383 * MicroMonitor (uMon) on the CSB337 does this incorrectly (and
384 * continues to do so, for bug-compatibility).
387 static short __init unpack_mac_address(struct net_device *dev, unsigned int hi, unsigned int lo)
391 if (machine_is_csb337()) {
392 addr[5] = (lo & 0xff); /* The CSB337 bootloader stores the MAC the wrong-way around */
393 addr[4] = (lo & 0xff00) >> 8;
394 addr[3] = (lo & 0xff0000) >> 16;
395 addr[2] = (lo & 0xff000000) >> 24;
396 addr[1] = (hi & 0xff);
397 addr[0] = (hi & 0xff00) >> 8;
400 addr[0] = (lo & 0xff);
401 addr[1] = (lo & 0xff00) >> 8;
402 addr[2] = (lo & 0xff0000) >> 16;
403 addr[3] = (lo & 0xff000000) >> 24;
404 addr[4] = (hi & 0xff);
405 addr[5] = (hi & 0xff00) >> 8;
408 if (is_valid_ether_addr(addr)) {
409 memcpy(dev->dev_addr, &addr, 6);
416 * Set the ethernet MAC address in dev->dev_addr
418 static void __init get_mac_address(struct net_device *dev)
420 /* Check Specific-Address 1 */
421 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA1H), at91_emac_read(AT91_EMAC_SA1L)))
423 /* Check Specific-Address 2 */
424 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA2H), at91_emac_read(AT91_EMAC_SA2L)))
426 /* Check Specific-Address 3 */
427 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA3H), at91_emac_read(AT91_EMAC_SA3L)))
429 /* Check Specific-Address 4 */
430 if (unpack_mac_address(dev, at91_emac_read(AT91_EMAC_SA4H), at91_emac_read(AT91_EMAC_SA4L)))
433 printk(KERN_ERR "at91_ether: Your bootloader did not configure a MAC address.\n");
437 * Program the hardware MAC address from dev->dev_addr.
439 static void update_mac_address(struct net_device *dev)
441 at91_emac_write(AT91_EMAC_SA1L, (dev->dev_addr[3] << 24) | (dev->dev_addr[2] << 16) | (dev->dev_addr[1] << 8) | (dev->dev_addr[0]));
442 at91_emac_write(AT91_EMAC_SA1H, (dev->dev_addr[5] << 8) | (dev->dev_addr[4]));
444 at91_emac_write(AT91_EMAC_SA2L, 0);
445 at91_emac_write(AT91_EMAC_SA2H, 0);
449 * Store the new hardware address in dev->dev_addr, and update the MAC.
451 static int set_mac_address(struct net_device *dev, void* addr)
453 struct sockaddr *address = addr;
455 if (!is_valid_ether_addr(address->sa_data))
456 return -EADDRNOTAVAIL;
458 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
459 update_mac_address(dev);
461 printk("%s: Setting MAC address to %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
462 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
463 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
468 static int inline hash_bit_value(int bitnr, __u8 *addr)
470 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
476 * The hash address register is 64 bits long and takes up two locations in the memory map.
477 * The least significant bits are stored in EMAC_HSL and the most significant
480 * The unicast hash enable and the multicast hash enable bits in the network configuration
481 * register enable the reception of hash matched frames. The destination address is
482 * reduced to a 6 bit index into the 64 bit hash register using the following hash function.
483 * The hash function is an exclusive or of every sixth bit of the destination address.
484 * hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
485 * hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
486 * hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
487 * hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
488 * hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
489 * hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
490 * da[0] represents the least significant bit of the first byte received, that is, the multicast/
491 * unicast indicator, and da[47] represents the most significant bit of the last byte
493 * If the hash index points to a bit that is set in the hash register then the frame will be
494 * matched according to whether the frame is multicast or unicast.
495 * A multicast match will be signalled if the multicast hash enable bit is set, da[0] is 1 and
496 * the hash index points to a bit set in the hash register.
497 * A unicast match will be signalled if the unicast hash enable bit is set, da[0] is 0 and the
498 * hash index points to a bit set in the hash register.
499 * To receive all multicast frames, the hash register should be set with all ones and the
500 * multicast hash enable bit should be set in the network configuration register.
504 * Return the hash index value for the specified address.
506 static int hash_get_index(__u8 *addr)
511 for (j = 0; j < 6; j++) {
512 for (i = 0, bitval = 0; i < 8; i++)
513 bitval ^= hash_bit_value(i*6 + j, addr);
515 hash_index |= (bitval << j);
522 * Add multicast addresses to the internal multicast-hash table.
524 static void at91ether_sethashtable(struct net_device *dev)
526 struct dev_mc_list *curr;
527 unsigned long mc_filter[2];
528 unsigned int i, bitnr;
530 mc_filter[0] = mc_filter[1] = 0;
533 for (i = 0; i < dev->mc_count; i++, curr = curr->next) {
534 if (!curr) break; /* unexpected end of list */
536 bitnr = hash_get_index(curr->dmi_addr);
537 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
540 at91_emac_write(AT91_EMAC_HSH, mc_filter[0]);
541 at91_emac_write(AT91_EMAC_HSL, mc_filter[1]);
545 * Enable/Disable promiscuous and multicast modes.
547 static void at91ether_set_rx_mode(struct net_device *dev)
551 cfg = at91_emac_read(AT91_EMAC_CFG);
553 if (dev->flags & IFF_PROMISC) /* Enable promiscuous mode */
554 cfg |= AT91_EMAC_CAF;
555 else if (dev->flags & (~IFF_PROMISC)) /* Disable promiscuous mode */
556 cfg &= ~AT91_EMAC_CAF;
558 if (dev->flags & IFF_ALLMULTI) { /* Enable all multicast mode */
559 at91_emac_write(AT91_EMAC_HSH, -1);
560 at91_emac_write(AT91_EMAC_HSL, -1);
561 cfg |= AT91_EMAC_MTI;
562 } else if (dev->mc_count > 0) { /* Enable specific multicasts */
563 at91ether_sethashtable(dev);
564 cfg |= AT91_EMAC_MTI;
565 } else if (dev->flags & (~IFF_ALLMULTI)) { /* Disable all multicast mode */
566 at91_emac_write(AT91_EMAC_HSH, 0);
567 at91_emac_write(AT91_EMAC_HSL, 0);
568 cfg &= ~AT91_EMAC_MTI;
571 at91_emac_write(AT91_EMAC_CFG, cfg);
574 /* ......................... ETHTOOL SUPPORT ........................... */
576 static int mdio_read(struct net_device *dev, int phy_id, int location)
580 read_phy(phy_id, location, &value);
584 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
586 write_phy(phy_id, location, value);
589 static int at91ether_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
591 struct at91_private *lp = netdev_priv(dev);
594 spin_lock_irq(&lp->lock);
597 ret = mii_ethtool_gset(&lp->mii, cmd);
600 spin_unlock_irq(&lp->lock);
602 if (lp->phy_media == PORT_FIBRE) { /* override media type since mii.c doesn't know */
603 cmd->supported = SUPPORTED_FIBRE;
604 cmd->port = PORT_FIBRE;
610 static int at91ether_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
612 struct at91_private *lp = netdev_priv(dev);
615 spin_lock_irq(&lp->lock);
618 ret = mii_ethtool_sset(&lp->mii, cmd);
621 spin_unlock_irq(&lp->lock);
626 static int at91ether_nwayreset(struct net_device *dev)
628 struct at91_private *lp = netdev_priv(dev);
631 spin_lock_irq(&lp->lock);
634 ret = mii_nway_restart(&lp->mii);
637 spin_unlock_irq(&lp->lock);
642 static void at91ether_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
644 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
645 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
646 strlcpy(info->bus_info, dev->class_dev.dev->bus_id, sizeof(info->bus_info));
649 static const struct ethtool_ops at91ether_ethtool_ops = {
650 .get_settings = at91ether_get_settings,
651 .set_settings = at91ether_set_settings,
652 .get_drvinfo = at91ether_get_drvinfo,
653 .nway_reset = at91ether_nwayreset,
654 .get_link = ethtool_op_get_link,
657 static int at91ether_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
659 struct at91_private *lp = netdev_priv(dev);
662 if (!netif_running(dev))
665 spin_lock_irq(&lp->lock);
667 res = generic_mii_ioctl(&lp->mii, if_mii(rq), cmd, NULL);
669 spin_unlock_irq(&lp->lock);
674 /* ................................ MAC ................................ */
677 * Initialize and start the Receiver and Transmit subsystems
679 static void at91ether_start(struct net_device *dev)
681 struct at91_private *lp = netdev_priv(dev);
682 struct recv_desc_bufs *dlist, *dlist_phys;
687 dlist_phys = lp->dlist_phys;
689 for (i = 0; i < MAX_RX_DESCR; i++) {
690 dlist->descriptors[i].addr = (unsigned int) &dlist_phys->recv_buf[i][0];
691 dlist->descriptors[i].size = 0;
694 /* Set the Wrap bit on the last descriptor */
695 dlist->descriptors[i-1].addr |= EMAC_DESC_WRAP;
697 /* Reset buffer index */
700 /* Program address of descriptor list in Rx Buffer Queue register */
701 at91_emac_write(AT91_EMAC_RBQP, (unsigned long) dlist_phys);
703 /* Enable Receive and Transmit */
704 ctl = at91_emac_read(AT91_EMAC_CTL);
705 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE | AT91_EMAC_TE);
709 * Open the ethernet interface
711 static int at91ether_open(struct net_device *dev)
713 struct at91_private *lp = netdev_priv(dev);
716 if (!is_valid_ether_addr(dev->dev_addr))
717 return -EADDRNOTAVAIL;
719 clk_enable(lp->ether_clk); /* Re-enable Peripheral clock */
721 /* Clear internal statistics */
722 ctl = at91_emac_read(AT91_EMAC_CTL);
723 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_CSR);
725 /* Update the MAC address (incase user has changed it) */
726 update_mac_address(dev);
728 /* Enable PHY interrupt */
731 /* Enable MAC interrupts */
732 at91_emac_write(AT91_EMAC_IER, AT91_EMAC_RCOM | AT91_EMAC_RBNA
733 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
734 | AT91_EMAC_ROVR | AT91_EMAC_ABT);
736 /* Determine current link speed */
737 spin_lock_irq(&lp->lock);
739 update_linkspeed(dev, 0);
741 spin_unlock_irq(&lp->lock);
743 at91ether_start(dev);
744 netif_start_queue(dev);
749 * Close the interface
751 static int at91ether_close(struct net_device *dev)
753 struct at91_private *lp = netdev_priv(dev);
756 /* Disable Receiver and Transmitter */
757 ctl = at91_emac_read(AT91_EMAC_CTL);
758 at91_emac_write(AT91_EMAC_CTL, ctl & ~(AT91_EMAC_TE | AT91_EMAC_RE));
760 /* Disable PHY interrupt */
763 /* Disable MAC interrupts */
764 at91_emac_write(AT91_EMAC_IDR, AT91_EMAC_RCOM | AT91_EMAC_RBNA
765 | AT91_EMAC_TUND | AT91_EMAC_RTRY | AT91_EMAC_TCOM
766 | AT91_EMAC_ROVR | AT91_EMAC_ABT);
768 netif_stop_queue(dev);
770 clk_disable(lp->ether_clk); /* Disable Peripheral clock */
778 static int at91ether_tx(struct sk_buff *skb, struct net_device *dev)
780 struct at91_private *lp = netdev_priv(dev);
782 if (at91_emac_read(AT91_EMAC_TSR) & AT91_EMAC_TSR_BNQ) {
783 netif_stop_queue(dev);
785 /* Store packet information (to free when Tx completed) */
787 lp->skb_length = skb->len;
788 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
789 lp->stats.tx_bytes += skb->len;
791 /* Set address of the data in the Transmit Address register */
792 at91_emac_write(AT91_EMAC_TAR, lp->skb_physaddr);
793 /* Set length of the packet in the Transmit Control register */
794 at91_emac_write(AT91_EMAC_TCR, skb->len);
796 dev->trans_start = jiffies;
798 printk(KERN_ERR "at91_ether.c: at91ether_tx() called, but device is busy!\n");
799 return 1; /* if we return anything but zero, dev.c:1055 calls kfree_skb(skb)
800 on this skb, he also reports -ENETDOWN and printk's, so either
801 we free and return(0) or don't free and return 1 */
808 * Update the current statistics from the internal statistics registers.
810 static struct net_device_stats *at91ether_stats(struct net_device *dev)
812 struct at91_private *lp = netdev_priv(dev);
813 int ale, lenerr, seqe, lcol, ecol;
815 if (netif_running(dev)) {
816 lp->stats.rx_packets += at91_emac_read(AT91_EMAC_OK); /* Good frames received */
817 ale = at91_emac_read(AT91_EMAC_ALE);
818 lp->stats.rx_frame_errors += ale; /* Alignment errors */
819 lenerr = at91_emac_read(AT91_EMAC_ELR) + at91_emac_read(AT91_EMAC_USF);
820 lp->stats.rx_length_errors += lenerr; /* Excessive Length or Undersize Frame error */
821 seqe = at91_emac_read(AT91_EMAC_SEQE);
822 lp->stats.rx_crc_errors += seqe; /* CRC error */
823 lp->stats.rx_fifo_errors += at91_emac_read(AT91_EMAC_DRFC); /* Receive buffer not available */
824 lp->stats.rx_errors += (ale + lenerr + seqe
825 + at91_emac_read(AT91_EMAC_CDE) + at91_emac_read(AT91_EMAC_RJB));
827 lp->stats.tx_packets += at91_emac_read(AT91_EMAC_FRA); /* Frames successfully transmitted */
828 lp->stats.tx_fifo_errors += at91_emac_read(AT91_EMAC_TUE); /* Transmit FIFO underruns */
829 lp->stats.tx_carrier_errors += at91_emac_read(AT91_EMAC_CSE); /* Carrier Sense errors */
830 lp->stats.tx_heartbeat_errors += at91_emac_read(AT91_EMAC_SQEE);/* Heartbeat error */
832 lcol = at91_emac_read(AT91_EMAC_LCOL);
833 ecol = at91_emac_read(AT91_EMAC_ECOL);
834 lp->stats.tx_window_errors += lcol; /* Late collisions */
835 lp->stats.tx_aborted_errors += ecol; /* 16 collisions */
837 lp->stats.collisions += (at91_emac_read(AT91_EMAC_SCOL) + at91_emac_read(AT91_EMAC_MCOL) + lcol + ecol);
843 * Extract received frame from buffer descriptors and sent to upper layers.
844 * (Called from interrupt context)
846 static void at91ether_rx(struct net_device *dev)
848 struct at91_private *lp = netdev_priv(dev);
849 struct recv_desc_bufs *dlist;
850 unsigned char *p_recv;
855 while (dlist->descriptors[lp->rxBuffIndex].addr & EMAC_DESC_DONE) {
856 p_recv = dlist->recv_buf[lp->rxBuffIndex];
857 pktlen = dlist->descriptors[lp->rxBuffIndex].size & 0x7ff; /* Length of frame including FCS */
858 skb = alloc_skb(pktlen + 2, GFP_ATOMIC);
861 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
864 skb->protocol = eth_type_trans(skb, dev);
866 dev->last_rx = jiffies;
867 lp->stats.rx_bytes += pktlen;
871 lp->stats.rx_dropped += 1;
872 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n", dev->name);
875 if (dlist->descriptors[lp->rxBuffIndex].size & EMAC_MULTICAST)
876 lp->stats.multicast++;
878 dlist->descriptors[lp->rxBuffIndex].addr &= ~EMAC_DESC_DONE; /* reset ownership bit */
879 if (lp->rxBuffIndex == MAX_RX_DESCR-1) /* wrap after last buffer */
887 * MAC interrupt handler
889 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
891 struct net_device *dev = (struct net_device *) dev_id;
892 struct at91_private *lp = netdev_priv(dev);
893 unsigned long intstatus, ctl;
895 /* MAC Interrupt Status register indicates what interrupts are pending.
896 It is automatically cleared once read. */
897 intstatus = at91_emac_read(AT91_EMAC_ISR);
899 if (intstatus & AT91_EMAC_RCOM) /* Receive complete */
902 if (intstatus & AT91_EMAC_TCOM) { /* Transmit complete */
903 /* The TCOM bit is set even if the transmission failed. */
904 if (intstatus & (AT91_EMAC_TUND | AT91_EMAC_RTRY))
905 lp->stats.tx_errors += 1;
908 dev_kfree_skb_irq(lp->skb);
910 dma_unmap_single(NULL, lp->skb_physaddr, lp->skb_length, DMA_TO_DEVICE);
912 netif_wake_queue(dev);
915 /* Work-around for Errata #11 */
916 if (intstatus & AT91_EMAC_RBNA) {
917 ctl = at91_emac_read(AT91_EMAC_CTL);
918 at91_emac_write(AT91_EMAC_CTL, ctl & ~AT91_EMAC_RE);
919 at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_RE);
922 if (intstatus & AT91_EMAC_ROVR)
923 printk("%s: ROVR error\n", dev->name);
929 * Initialize the ethernet interface
931 static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_address,
932 struct platform_device *pdev, struct clk *ether_clk)
934 struct at91_eth_data *board_data = pdev->dev.platform_data;
935 struct net_device *dev;
936 struct at91_private *lp;
940 dev = alloc_etherdev(sizeof(struct at91_private));
944 dev->base_addr = AT91_VA_BASE_EMAC;
945 dev->irq = AT91RM9200_ID_EMAC;
946 SET_MODULE_OWNER(dev);
948 /* Install the interrupt handler */
949 if (request_irq(dev->irq, at91ether_interrupt, 0, dev->name, dev)) {
954 /* Allocate memory for DMA Receive descriptors */
955 lp = netdev_priv(dev);
956 lp->dlist = (struct recv_desc_bufs *) dma_alloc_coherent(NULL, sizeof(struct recv_desc_bufs), (dma_addr_t *) &lp->dlist_phys, GFP_KERNEL);
957 if (lp->dlist == NULL) {
958 free_irq(dev->irq, dev);
962 lp->board_data = *board_data;
963 lp->ether_clk = ether_clk;
964 platform_set_drvdata(pdev, dev);
966 spin_lock_init(&lp->lock);
969 dev->open = at91ether_open;
970 dev->stop = at91ether_close;
971 dev->hard_start_xmit = at91ether_tx;
972 dev->get_stats = at91ether_stats;
973 dev->set_multicast_list = at91ether_set_rx_mode;
974 dev->set_mac_address = set_mac_address;
975 dev->ethtool_ops = &at91ether_ethtool_ops;
976 dev->do_ioctl = at91ether_ioctl;
978 SET_NETDEV_DEV(dev, &pdev->dev);
980 get_mac_address(dev); /* Get ethernet address and store it in dev->dev_addr */
981 update_mac_address(dev); /* Program ethernet address into MAC */
983 at91_emac_write(AT91_EMAC_CTL, 0);
985 if (lp->board_data.is_rmii)
986 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG | AT91_EMAC_RMII);
988 at91_emac_write(AT91_EMAC_CFG, AT91_EMAC_CLK_DIV32 | AT91_EMAC_BIG);
990 /* Perform PHY-specific initialization */
991 spin_lock_irq(&lp->lock);
993 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID)) {
994 read_phy(phy_address, MII_DSCR_REG, &val);
995 if ((val & (1 << 10)) == 0) /* DSCR bit 10 is 0 -- fiber mode */
996 lp->phy_media = PORT_FIBRE;
997 } else if (machine_is_csb337()) {
998 /* mix link activity status into LED2 link state */
999 write_phy(phy_address, MII_LEDCTRL_REG, 0x0d22);
1002 spin_unlock_irq(&lp->lock);
1004 lp->mii.dev = dev; /* Support for ethtool */
1005 lp->mii.mdio_read = mdio_read;
1006 lp->mii.mdio_write = mdio_write;
1007 lp->mii.phy_id = phy_address;
1008 lp->mii.phy_id_mask = 0x1f;
1009 lp->mii.reg_num_mask = 0x1f;
1011 lp->phy_type = phy_type; /* Type of PHY connected */
1012 lp->phy_address = phy_address; /* MDI address of PHY */
1014 /* Register the network interface */
1015 res = register_netdev(dev);
1017 free_irq(dev->irq, dev);
1019 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1023 /* Determine current link speed */
1024 spin_lock_irq(&lp->lock);
1026 update_linkspeed(dev, 0);
1028 spin_unlock_irq(&lp->lock);
1029 netif_carrier_off(dev); /* will be enabled in open() */
1031 /* If board has no PHY IRQ, use a timer to poll the PHY */
1032 if (!lp->board_data.phy_irq_pin) {
1033 init_timer(&check_timer);
1034 check_timer.data = (unsigned long)dev;
1035 check_timer.function = at91ether_check_link;
1038 /* Display ethernet banner */
1039 printk(KERN_INFO "%s: AT91 ethernet at 0x%08x int=%d %s%s (%02x:%02x:%02x:%02x:%02x:%02x)\n",
1040 dev->name, (uint) dev->base_addr, dev->irq,
1041 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_SPD ? "100-" : "10-",
1042 at91_emac_read(AT91_EMAC_CFG) & AT91_EMAC_FD ? "FullDuplex" : "HalfDuplex",
1043 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1044 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1045 if ((phy_type == MII_DM9161_ID) || (lp->phy_type == MII_DM9161A_ID))
1046 printk(KERN_INFO "%s: Davicom 9161 PHY %s\n", dev->name, (lp->phy_media == PORT_FIBRE) ? "(Fiber)" : "(Copper)");
1047 else if (phy_type == MII_LXT971A_ID)
1048 printk(KERN_INFO "%s: Intel LXT971A PHY\n", dev->name);
1049 else if (phy_type == MII_RTL8201_ID)
1050 printk(KERN_INFO "%s: Realtek RTL8201(B)L PHY\n", dev->name);
1051 else if (phy_type == MII_BCM5221_ID)
1052 printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
1053 else if (phy_type == MII_DP83847_ID)
1054 printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name);
1055 else if (phy_type == MII_AC101L_ID)
1056 printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
1057 else if (phy_type == MII_KS8721_ID)
1058 printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
1064 * Detect MAC and PHY and perform initialization
1066 static int __init at91ether_probe(struct platform_device *pdev)
1068 unsigned int phyid1, phyid2;
1070 unsigned long phy_id;
1071 unsigned short phy_address = 0;
1072 struct clk *ether_clk;
1074 ether_clk = clk_get(&pdev->dev, "ether_clk");
1075 if (IS_ERR(ether_clk)) {
1076 printk(KERN_ERR "at91_ether: no clock defined\n");
1079 clk_enable(ether_clk); /* Enable Peripheral clock */
1081 while ((detected != 0) && (phy_address < 32)) {
1082 /* Read the PHY ID registers */
1084 read_phy(phy_address, MII_PHYSID1, &phyid1);
1085 read_phy(phy_address, MII_PHYSID2, &phyid2);
1088 phy_id = (phyid1 << 16) | (phyid2 & 0xfff0);
1090 case MII_DM9161_ID: /* Davicom 9161: PHY_ID1 = 0x181, PHY_ID2 = B881 */
1091 case MII_DM9161A_ID: /* Davicom 9161A: PHY_ID1 = 0x181, PHY_ID2 = B8A0 */
1092 case MII_LXT971A_ID: /* Intel LXT971A: PHY_ID1 = 0x13, PHY_ID2 = 78E0 */
1093 case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
1094 case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
1095 case MII_DP83847_ID: /* National Semiconductor DP83847: */
1096 case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
1097 case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
1098 detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk);
1105 clk_disable(ether_clk); /* Disable Peripheral clock */
1110 static int __devexit at91ether_remove(struct platform_device *pdev)
1112 struct net_device *dev = platform_get_drvdata(pdev);
1113 struct at91_private *lp = netdev_priv(dev);
1115 unregister_netdev(dev);
1116 free_irq(dev->irq, dev);
1117 dma_free_coherent(NULL, sizeof(struct recv_desc_bufs), lp->dlist, (dma_addr_t)lp->dlist_phys);
1118 clk_put(lp->ether_clk);
1120 platform_set_drvdata(pdev, NULL);
1127 static int at91ether_suspend(struct platform_device *pdev, pm_message_t mesg)
1129 struct net_device *net_dev = platform_get_drvdata(pdev);
1130 struct at91_private *lp = netdev_priv(net_dev);
1131 int phy_irq = lp->board_data.phy_irq_pin;
1133 if (netif_running(net_dev)) {
1135 disable_irq(phy_irq);
1137 netif_stop_queue(net_dev);
1138 netif_device_detach(net_dev);
1140 clk_disable(lp->ether_clk);
1145 static int at91ether_resume(struct platform_device *pdev)
1147 struct net_device *net_dev = platform_get_drvdata(pdev);
1148 struct at91_private *lp = netdev_priv(net_dev);
1149 int phy_irq = lp->board_data.phy_irq_pin;
1151 if (netif_running(net_dev)) {
1152 clk_enable(lp->ether_clk);
1154 netif_device_attach(net_dev);
1155 netif_start_queue(net_dev);
1158 enable_irq(phy_irq);
1164 #define at91ether_suspend NULL
1165 #define at91ether_resume NULL
1168 static struct platform_driver at91ether_driver = {
1169 .probe = at91ether_probe,
1170 .remove = __devexit_p(at91ether_remove),
1171 .suspend = at91ether_suspend,
1172 .resume = at91ether_resume,
1175 .owner = THIS_MODULE,
1179 static int __init at91ether_init(void)
1181 return platform_driver_register(&at91ether_driver);
1184 static void __exit at91ether_exit(void)
1186 platform_driver_unregister(&at91ether_driver);
1189 module_init(at91ether_init)
1190 module_exit(at91ether_exit)
1192 MODULE_LICENSE("GPL");
1193 MODULE_DESCRIPTION("AT91RM9200 EMAC Ethernet driver");
1194 MODULE_AUTHOR("Andrew Victor");