2 * linux/drivers/mtd/onenand/omap2.c
4 * OneNAND driver for OMAP2
6 * Copyright (C) 2005-2006 Nokia Corporation
8 * Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjola
9 * IRQ and DMA support written by Timo Teras
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published by
13 * the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * You should have received a copy of the GNU General Public License along with
21 * this program; see the file COPYING. If not, write to the Free Software
22 * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 #include <linux/device.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/mtd/mtd.h>
30 #include <linux/mtd/onenand.h>
31 #include <linux/mtd/partitions.h>
32 #include <linux/platform_device.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
37 #include <asm/mach/flash.h>
38 #include <asm/arch/gpmc.h>
39 #include <asm/arch/onenand.h>
40 #include <asm/arch/gpio.h>
41 #include <asm/arch/gpmc.h>
42 #include <asm/arch/pm.h>
44 #include <linux/dma-mapping.h>
45 #include <asm/dma-mapping.h>
46 #include <asm/arch/dma.h>
48 #include <asm/arch/board.h>
50 #define ONENAND_IO_SIZE SZ_128K
51 #define ONENAND_BUFRAM_SIZE (1024 * 5)
53 struct omap2_onenand {
54 struct platform_device *pdev;
56 unsigned long phys_base;
59 struct mtd_partition *parts;
60 struct onenand_chip onenand;
61 struct completion irq_done;
62 struct completion dma_done;
66 static unsigned short omap2_onenand_readw(void __iomem *addr)
71 static void omap2_onenand_writew(unsigned short value, void __iomem *addr)
76 static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
78 struct omap2_onenand *info = data;
80 complete(&info->dma_done);
83 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id)
85 struct omap2_onenand *info = dev_id;
87 complete(&info->irq_done);
92 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
94 struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
95 unsigned int interrupt = 0;
97 unsigned long timeout;
100 if (state == FL_RESETING) {
105 if (state != FL_READING) {
107 /* Turn interrupts on */
108 syscfg = omap2_onenand_readw(info->onenand.base + ONENAND_REG_SYS_CFG1);
109 syscfg |= ONENAND_SYS_CFG1_IOBE;
110 omap2_onenand_writew(syscfg, info->onenand.base + ONENAND_REG_SYS_CFG1);
112 INIT_COMPLETION(info->irq_done);
113 result = omap_get_gpio_datain(info->gpio_irq);
115 ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
116 printk(KERN_ERR "onenand_wait: gpio error, state = %d, ctrl = 0x%04x\n", state, ctrl);
122 result = wait_for_completion_timeout(&info->irq_done,
123 msecs_to_jiffies(20));
125 /* Timeout after 20ms */
126 ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
127 if (ctrl & ONENAND_CTRL_ONGO) {
128 /* The operation seems to be still going - so give it some more time */
132 interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
133 printk(KERN_ERR "onenand_wait: timeout state=%d ctrl=0x%04x intr=0x%04x\n", state, ctrl, interrupt);
136 interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
137 if ((interrupt & ONENAND_INT_MASTER) == 0)
138 printk(KERN_WARNING "onenand_wait: timeout state=%d ctrl=0x%04x intr=0x%04x\n", state, ctrl, interrupt);
142 /* Turn interrupts off */
143 syscfg = omap2_onenand_readw(info->onenand.base + ONENAND_REG_SYS_CFG1);
144 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
145 omap2_onenand_writew(syscfg, info->onenand.base + ONENAND_REG_SYS_CFG1);
147 timeout = jiffies + msecs_to_jiffies(20);
148 while (time_before(jiffies, timeout)) {
149 if (omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT) &
155 /* To get correct interrupt status in timeout case */
156 interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
157 ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
159 if (ctrl & ONENAND_CTRL_ERROR) {
160 printk(KERN_ERR "onenand_wait: controller error = 0x%04x\n", ctrl);
161 if (ctrl & ONENAND_CTRL_LOCK)
162 printk(KERN_ERR "onenand_erase: Device is write protected!!!\n");
167 printk(KERN_WARNING "onenand_wait: unexpected controller status = 0x%04x state = %d interrupt = 0x%04x\n", ctrl, state, interrupt);
169 if (interrupt & ONENAND_INT_READ) {
170 int ecc = omap2_onenand_readw(info->onenand.base + ONENAND_REG_ECC_STATUS);
172 printk(KERN_ERR "onenand_wait: ECC error = 0x%04x\n", ecc);
173 if (ecc & ONENAND_ECC_2BIT_ALL) {
174 mtd->ecc_stats.failed++;
176 } else if (ecc & ONENAND_ECC_1BIT_ALL)
177 mtd->ecc_stats.corrected++;
179 } else if (state == FL_READING) {
180 printk(KERN_ERR "onenand_wait: read timeout! ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt);
187 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
189 struct onenand_chip *this = mtd->priv;
191 if (ONENAND_CURRENT_BUFFERRAM(this)) {
192 if (area == ONENAND_DATARAM)
193 return mtd->writesize;
194 if (area == ONENAND_SPARERAM)
201 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
202 unsigned char *buffer, int offset,
205 struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
206 struct onenand_chip *this = mtd->priv;
207 dma_addr_t dma_src, dma_dst;
210 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
211 if (1 || (info->dma_channel < 0) || ((void *) buffer >= (void *) high_memory) ||
212 (bram_offset & 3) || (((unsigned int) buffer) & 3) ||
213 (count < 1024) || (count & 3)) {
214 memcpy(buffer, (void *)(this->base + bram_offset), count);
218 dma_src = info->phys_base + bram_offset;
219 dma_dst = dma_map_single(&info->pdev->dev, buffer, count, DMA_FROM_DEVICE);
220 if (dma_mapping_error(dma_dst)) {
221 dev_err(&info->pdev->dev,
222 "Couldn't DMA map a %d byte buffer\n",
227 omap_set_dma_transfer_params(info->dma_channel, OMAP_DMA_DATA_TYPE_S32,
228 count / 4, 1, 0, 0, 0);
229 omap_set_dma_src_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
231 omap_set_dma_dest_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
234 INIT_COMPLETION(info->dma_done);
236 omap_start_dma(info->dma_channel);
237 wait_for_completion(&info->dma_done);
240 dma_unmap_single(&info->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
245 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
246 const unsigned char *buffer, int offset,
249 struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
250 struct onenand_chip *this = mtd->priv;
251 dma_addr_t dma_src, dma_dst;
254 bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
255 if (1 || (info->dma_channel < 0) || ((void *) buffer >= (void *) high_memory) ||
256 (bram_offset & 3) || (((unsigned int) buffer) & 3) ||
257 (count < 1024) || (count & 3)) {
258 memcpy((void *)(this->base + bram_offset), buffer, count);
262 dma_src = dma_map_single(&info->pdev->dev, (void *) buffer, count,
264 dma_dst = info->phys_base + bram_offset;
265 if (dma_mapping_error(dma_dst)) {
266 dev_err(&info->pdev->dev,
267 "Couldn't DMA map a %d byte buffer\n",
272 omap_set_dma_transfer_params(info->dma_channel, OMAP_DMA_DATA_TYPE_S16,
273 count / 2, 1, 0, 0, 0);
274 omap_set_dma_src_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
276 omap_set_dma_dest_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
279 INIT_COMPLETION(info->dma_done);
280 omap_start_dma(info->dma_channel);
281 wait_for_completion(&info->dma_done);
283 dma_unmap_single(&info->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
288 static void __devexit omap2_onenand_shutdown(struct platform_device *pdev)
290 struct omap2_onenand *info = dev_get_drvdata(&pdev->dev);
292 /* With certain content in the buffer RAM, the OMAP boot ROM code
293 * can recognize the flash chip incorrectly. Zero it out before
296 memset(info->onenand.base, 0, ONENAND_BUFRAM_SIZE);
299 static int __devinit omap2_onenand_probe(struct platform_device *pdev)
301 struct omap_onenand_platform_data *pdata;
302 struct omap2_onenand *info;
305 pdata = pdev->dev.platform_data;
307 dev_err(&pdev->dev, "platform data missing\n");
311 info = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
315 init_completion(&info->irq_done);
316 init_completion(&info->dma_done);
317 info->gpmc_cs = pdata->cs;
318 info->gpio_irq = pdata->gpio_irq;
320 r = gpmc_cs_request(info->gpmc_cs, ONENAND_IO_SIZE, &info->phys_base);
322 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
326 if (request_mem_region(info->phys_base, ONENAND_IO_SIZE,
327 pdev->dev.driver->name) == NULL) {
328 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, size: 0x%x\n",
329 info->phys_base, ONENAND_IO_SIZE);
333 info->onenand.base = ioremap(info->phys_base, ONENAND_IO_SIZE);
334 if (info->onenand.base == NULL) {
336 goto err_release_mem_region;
339 if (pdata->onenand_setup != NULL) {
340 r = pdata->onenand_setup(info->onenand.base);
342 dev_err(&pdev->dev, "Onenand platform setup failed: %d\n", r);
347 if ((r = omap_request_gpio(info->gpio_irq)) < 0) {
348 dev_err(&pdev->dev, "Failed to request GPIO%d for OneNAND\n",
352 omap_set_gpio_direction(info->gpio_irq, 1);
354 if ((r = request_irq(OMAP_GPIO_IRQ(info->gpio_irq),
355 omap2_onenand_interrupt, SA_TRIGGER_RISING,
356 pdev->dev.driver->name, info)) < 0)
357 goto err_release_gpio;
359 r = omap_request_dma(0, pdev->dev.driver->name,
360 omap2_onenand_dma_cb, (void *) info,
363 omap_set_dma_write_mode(info->dma_channel, OMAP_DMA_WRITE_NON_POSTED);
364 omap_set_dma_src_data_pack(info->dma_channel, 1);
365 omap_set_dma_src_burst_mode(info->dma_channel, OMAP_DMA_DATA_BURST_8);
366 omap_set_dma_dest_data_pack(info->dma_channel, 1);
367 omap_set_dma_dest_burst_mode(info->dma_channel, OMAP_DMA_DATA_BURST_8);
370 "failed to allocate DMA for OneNAND, using PIO instead\n");
371 info->dma_channel = -1;
374 dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual base %p\n",
375 info->gpmc_cs, info->phys_base, info->onenand.base);
378 info->mtd.name = pdev->dev.bus_id;
379 info->mtd.priv = &info->onenand;
380 info->mtd.owner = THIS_MODULE;
381 info->onenand.wait = omap2_onenand_wait;
382 info->onenand.read_bufferram = omap2_onenand_read_bufferram;
383 info->onenand.write_bufferram = omap2_onenand_write_bufferram;
385 if ((r = onenand_scan(&info->mtd, 1)) < 0)
386 goto err_release_dma;
388 #ifdef CONFIG_MTD_PARTITIONS
389 if (pdata->parts != NULL)
390 r = add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
393 r = add_mtd_device(&info->mtd);
395 goto err_release_onenand;
397 platform_set_drvdata(pdev, info);
402 onenand_release(&info->mtd);
404 if (info->dma_channel != -1)
405 omap_free_dma(info->dma_channel);
406 free_irq(OMAP_GPIO_IRQ(info->gpio_irq), info);
408 omap_free_gpio(info->gpio_irq);
410 iounmap(info->onenand.base);
411 err_release_mem_region:
412 release_mem_region(info->phys_base, ONENAND_IO_SIZE);
414 gpmc_cs_free(info->gpmc_cs);
421 static int __devexit omap2_onenand_remove(struct platform_device *pdev)
423 struct omap2_onenand *info = dev_get_drvdata(&pdev->dev);
425 BUG_ON(info == NULL);
427 #ifdef CONFIG_MTD_PARTITIONS
429 del_mtd_partitions(&info->mtd);
431 del_mtd_device(&info->mtd);
433 del_mtd_device(&info->mtd);
436 onenand_release(&info->mtd);
437 if (info->dma_channel != -1)
438 omap_free_dma(info->dma_channel);
439 omap2_onenand_shutdown(pdev);
440 platform_set_drvdata(pdev, NULL);
441 free_irq(OMAP_GPIO_IRQ(info->gpio_irq), info);
442 omap_free_gpio(info->gpio_irq);
443 iounmap(info->onenand.base);
444 release_mem_region(info->phys_base, ONENAND_IO_SIZE);
450 static struct platform_driver omap2_onenand_driver = {
451 .probe = omap2_onenand_probe,
452 .remove = omap2_onenand_remove,
453 .shutdown = omap2_onenand_shutdown,
455 .name = "omap2-onenand",
456 .owner = THIS_MODULE,
460 MODULE_ALIAS(DRIVER_NAME);
462 static int __init omap2_onenand_init(void)
464 printk(KERN_INFO "OMAP2 OneNAND driver initializing\n");
465 return platform_driver_register(&omap2_onenand_driver);
468 static void __exit omap2_onenand_exit(void)
470 platform_driver_unregister(&omap2_onenand_driver);
473 module_init(omap2_onenand_init);
474 module_exit(omap2_onenand_exit);
476 MODULE_LICENSE("GPL");
477 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
478 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2");