drivers/mtd/onenand/omap2.c

   1 /*
   2  *  linux/drivers/mtd/onenand/omap2.c
   3  *
   4  *  OneNAND driver for OMAP2
   5  *
   6  *  Copyright (C) 2005-2006 Nokia Corporation
   7  *
   8  *  Author: Jarkko Lavinen <jarkko.lavinen@nokia.com> and Juha Yrjola
   9  *  IRQ and DMA support written by Timo Teras
  10  *
  11  * This program is free software; you can redistribute it and/or modify it
  12  * under the terms of the GNU General Public License version 2 as published by
  13  * the Free Software Foundation.
  14  *
  15  * This program is distributed in the hope that it will be useful, but WITHOUT
  16  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  18  * more details.
  19  *
  20  * You should have received a copy of the GNU General Public License along with
  21  * this program; see the file COPYING. If not, write to the Free Software
  22  * Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  23  *
  24  */
  25
  26 #include <linux/device.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/onenand.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/delay.h>
  35
  36 #include <asm/io.h>
  37 #include <asm/mach/flash.h>
  38 #include <asm/arch/gpmc.h>
  39 #include <asm/arch/onenand.h>
  40 #include <asm/arch/gpio.h>
  41 #include <asm/arch/gpmc.h>
  42 #include <asm/arch/pm.h>
  43
  44 #include <linux/dma-mapping.h>
  45 #include <asm/dma-mapping.h>
  46 #include <asm/arch/dma.h>
  47
  48 #include <asm/arch/board.h>
  49
  50 #define ONENAND_IO_SIZE         SZ_128K
  51 #define ONENAND_BUFRAM_SIZE     (1024 * 5)
  52
  53 struct omap2_onenand {
  54         struct platform_device *pdev;
  55         int gpmc_cs;
  56         unsigned long phys_base;
  57         int gpio_irq;
  58         struct mtd_info mtd;
  59         struct mtd_partition *parts;
  60         struct onenand_chip onenand;
  61         struct completion irq_done;
  62         struct completion dma_done;
  63         int dma_channel;
  64 };
  65
  66 static unsigned short omap2_onenand_readw(void __iomem *addr)
  67 {
  68         return readw(addr);
  69 }
  70
  71 static void omap2_onenand_writew(unsigned short value, void __iomem *addr)
  72 {
  73         writew(value, addr);
  74 }
  75
  76 static void omap2_onenand_dma_cb(int lch, u16 ch_status, void *data)
  77 {
  78         struct omap2_onenand *info = data;
  79
  80         complete(&info->dma_done);
  81 }
  82
  83 static irqreturn_t omap2_onenand_interrupt(int irq, void *dev_id,
  84                                            struct pt_regs *regs)
  85 {
  86         struct omap2_onenand *info = dev_id;
  87
  88         complete(&info->irq_done);
  89
  90         return IRQ_HANDLED;
  91 }
  92
  93 static int omap2_onenand_wait(struct mtd_info *mtd, int state)
  94 {
  95         struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
  96         unsigned int interrupt = 0;
  97         unsigned int ctrl;
  98         unsigned long timeout;
  99         u32 syscfg;
 100
 101         if (state == FL_RESETING) {
 102                 udelay(1);
 103                 return 0;
 104         }
 105
 106         if (state != FL_READING) {
 107                 int result;
 108                 /* Turn interrupts on */
 109                 syscfg = omap2_onenand_readw(info->onenand.base + ONENAND_REG_SYS_CFG1);
 110                 syscfg |= ONENAND_SYS_CFG1_IOBE;
 111                 omap2_onenand_writew(syscfg, info->onenand.base + ONENAND_REG_SYS_CFG1);
 112
 113                 INIT_COMPLETION(info->irq_done);
 114                 result = omap_get_gpio_datain(info->gpio_irq);
 115                 if (result == -1) {
 116                         ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
 117                         printk(KERN_ERR "onenand_wait: gpio error, state = %d, ctrl = 0x%04x\n", state, ctrl);
 118                         return -EIO;
 119                 }
 120                 if (result == 0) {
 121                         int retry_cnt = 0;
 122 retry:
 123                         result = wait_for_completion_timeout(&info->irq_done,
 124                                                     msecs_to_jiffies(20));
 125                         if (result == 0) {
 126                                 /* Timeout after 20ms */
 127                                 ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
 128                                 if (ctrl & ONENAND_CTRL_ONGO) {
 129                                         /* The operation seems to be still going - so give it some more time */
 130                                         retry_cnt += 1;
 131                                         if (retry_cnt < 3)
 132                                                 goto retry;
 133                                         interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
 134                                         printk(KERN_ERR "onenand_wait: timeout state=%d ctrl=0x%04x intr=0x%04x\n", state, ctrl, interrupt);
 135                                         return -EIO;
 136                                 }
 137                                 interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
 138                                 if ((interrupt & ONENAND_INT_MASTER) == 0)
 139                                         printk(KERN_WARNING "onenand_wait: timeout state=%d ctrl=0x%04x intr=0x%04x\n", state, ctrl, interrupt);
 140                         }
 141                 }
 142         } else {
 143                 /* Turn interrupts off */
 144                 syscfg = omap2_onenand_readw(info->onenand.base + ONENAND_REG_SYS_CFG1);
 145                 syscfg &= ~ONENAND_SYS_CFG1_IOBE;
 146                 omap2_onenand_writew(syscfg, info->onenand.base + ONENAND_REG_SYS_CFG1);
 147
 148                 timeout = jiffies + msecs_to_jiffies(20);
 149                 while (time_before(jiffies, timeout)) {
 150                         if (omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT) &
 151                             ONENAND_INT_MASTER)
 152                                 break;
 153                 }
 154         }
 155
 156         /* To get correct interrupt status in timeout case */
 157         interrupt = omap2_onenand_readw(info->onenand.base + ONENAND_REG_INTERRUPT);
 158         ctrl = omap2_onenand_readw(info->onenand.base + ONENAND_REG_CTRL_STATUS);
 159
 160         if (ctrl & ONENAND_CTRL_ERROR) {
 161                 printk(KERN_ERR "onenand_wait: controller error = 0x%04x\n", ctrl);
 162                 if (ctrl & ONENAND_CTRL_LOCK)
 163                         printk(KERN_ERR "onenand_erase: Device is write protected!!!\n");
 164                 return ctrl;
 165         }
 166
 167         if (ctrl & 0xFE9F)
 168                 printk(KERN_WARNING "onenand_wait: unexpected controller status = 0x%04x  state = %d  interrupt = 0x%04x\n", ctrl, state, interrupt);
 169
 170         if (interrupt & ONENAND_INT_READ) {
 171                 int ecc = omap2_onenand_readw(info->onenand.base + ONENAND_REG_ECC_STATUS);
 172                 if (ecc) {
 173                         printk(KERN_ERR "onenand_wait: ECC error = 0x%04x\n", ecc);
 174                         if (ecc & ONENAND_ECC_2BIT_ALL) {
 175                                 mtd->ecc_stats.failed++;
 176                                 return ecc;
 177                         } else if (ecc & ONENAND_ECC_1BIT_ALL)
 178                                 mtd->ecc_stats.corrected++;
 179                 }
 180         } else if (state == FL_READING) {
 181                 printk(KERN_ERR "onenand_wait: read timeout! ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt);
 182                 return -EIO;
 183         }
 184
 185         return 0;
 186 }
 187
 188 static inline int omap2_onenand_bufferram_offset(struct mtd_info *mtd, int area)
 189 {
 190         struct onenand_chip *this = mtd->priv;
 191
 192         if (ONENAND_CURRENT_BUFFERRAM(this)) {
 193                 if (area == ONENAND_DATARAM)
 194                         return mtd->writesize;
 195                 if (area == ONENAND_SPARERAM)
 196                         return mtd->oobsize;
 197         }
 198
 199         return 0;
 200 }
 201
 202 static int omap2_onenand_read_bufferram(struct mtd_info *mtd, int area,
 203                                         unsigned char *buffer, int offset,
 204                                         size_t count)
 205 {
 206         struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
 207         struct onenand_chip *this = mtd->priv;
 208         dma_addr_t dma_src, dma_dst;
 209         int bram_offset;
 210
 211         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 212         if (1 || (info->dma_channel < 0) || ((void *) buffer >= (void *) high_memory) ||
 213             (bram_offset & 3) || (((unsigned int) buffer) & 3) ||
 214             (count < 1024) || (count & 3)) {
 215                 memcpy(buffer, (void *)(this->base + bram_offset), count);
 216                 return 0;
 217         }
 218
 219         dma_src = info->phys_base + bram_offset;
 220         dma_dst = dma_map_single(&info->pdev->dev, buffer, count, DMA_FROM_DEVICE);
 221         if (dma_mapping_error(dma_dst)) {
 222                 dev_err(&info->pdev->dev,
 223                         "Couldn't DMA map a %d byte buffer\n",
 224                         count);
 225                 return -1;
 226         }
 227
 228         omap_set_dma_transfer_params(info->dma_channel, OMAP_DMA_DATA_TYPE_S32,
 229                                      count / 4, 1, 0, 0, 0);
 230         omap_set_dma_src_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 231                                 dma_src, 0, 0);
 232         omap_set_dma_dest_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 233                                  dma_dst, 0, 0);
 234
 235         INIT_COMPLETION(info->dma_done);
 236         omap2_block_sleep();
 237         omap_start_dma(info->dma_channel);
 238         wait_for_completion(&info->dma_done);
 239         omap2_allow_sleep();
 240
 241         dma_unmap_single(&info->pdev->dev, dma_dst, count, DMA_FROM_DEVICE);
 242
 243         return 0;
 244 }
 245
 246 static int omap2_onenand_write_bufferram(struct mtd_info *mtd, int area,
 247                                          const unsigned char *buffer, int offset,
 248                                          size_t count)
 249 {
 250         struct omap2_onenand *info = container_of(mtd, struct omap2_onenand, mtd);
 251         struct onenand_chip *this = mtd->priv;
 252         dma_addr_t dma_src, dma_dst;
 253         int bram_offset;
 254
 255         bram_offset = omap2_onenand_bufferram_offset(mtd, area) + area + offset;
 256         if (1 || (info->dma_channel < 0) || ((void *) buffer >= (void *) high_memory) ||
 257             (bram_offset & 3) || (((unsigned int) buffer) & 3) ||
 258             (count < 1024) || (count & 3)) {
 259                 memcpy((void *)(this->base + bram_offset), buffer, count);
 260                 return 0;
 261         }
 262
 263         dma_src = dma_map_single(&info->pdev->dev, (void *) buffer, count,
 264                                  DMA_TO_DEVICE);
 265         dma_dst = info->phys_base + bram_offset;
 266         if (dma_mapping_error(dma_dst)) {
 267                 dev_err(&info->pdev->dev,
 268                         "Couldn't DMA map a %d byte buffer\n",
 269                         count);
 270                 return -1;
 271         }
 272
 273         omap_set_dma_transfer_params(info->dma_channel, OMAP_DMA_DATA_TYPE_S16,
 274                                      count / 2, 1, 0, 0, 0);
 275         omap_set_dma_src_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 276                                 dma_src, 0, 0);
 277         omap_set_dma_dest_params(info->dma_channel, 0, OMAP_DMA_AMODE_POST_INC,
 278                                  dma_dst, 0, 0);
 279
 280         INIT_COMPLETION(info->dma_done);
 281         omap_start_dma(info->dma_channel);
 282         wait_for_completion(&info->dma_done);
 283
 284         dma_unmap_single(&info->pdev->dev, dma_dst, count, DMA_TO_DEVICE);
 285
 286         return 0;
 287 }
 288
 289 static void __devexit omap2_onenand_shutdown(struct platform_device *pdev)
 290 {
 291         struct omap2_onenand *info = dev_get_drvdata(&pdev->dev);
 292
 293         /* With certain content in the buffer RAM, the OMAP boot ROM code
 294          * can recognize the flash chip incorrectly. Zero it out before
 295          * soft reset.
 296          */
 297         memset(info->onenand.base, 0, ONENAND_BUFRAM_SIZE);
 298 }
 299
 300 static int __devinit omap2_onenand_probe(struct platform_device *pdev)
 301 {
 302         struct omap_onenand_platform_data *pdata;
 303         struct omap2_onenand *info;
 304         int r;
 305
 306         pdata = pdev->dev.platform_data;
 307         if (pdata == NULL) {
 308                 dev_err(&pdev->dev, "platform data missing\n");
 309                 return -ENODEV;
 310         }
 311
 312         info = kzalloc(sizeof(struct omap2_onenand), GFP_KERNEL);
 313         if (!info)
 314                 return -ENOMEM;
 315
 316         init_completion(&info->irq_done);
 317         init_completion(&info->dma_done);
 318         info->gpmc_cs = pdata->cs;
 319         info->gpio_irq = pdata->gpio_irq;
 320
 321         r = gpmc_cs_request(info->gpmc_cs, ONENAND_IO_SIZE, &info->phys_base);
 322         if (r < 0) {
 323                 dev_err(&pdev->dev, "Cannot request GPMC CS\n");
 324                 goto err_kfree;
 325         }
 326
 327         if (request_mem_region(info->phys_base, ONENAND_IO_SIZE,
 328                                pdev->dev.driver->name) == NULL) {
 329                 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, size: 0x%x\n",
 330                         info->phys_base, ONENAND_IO_SIZE);
 331                 r = -EBUSY;
 332                 goto err_free_cs;
 333         }
 334         info->onenand.base = ioremap(info->phys_base, ONENAND_IO_SIZE);
 335         if (info->onenand.base == NULL) {
 336                 r = -ENOMEM;
 337                 goto err_release_mem_region;
 338         }
 339
 340         if (pdata->onenand_setup != NULL) {
 341                 r = pdata->onenand_setup(info->onenand.base);
 342                 if (r < 0) {
 343                         dev_err(&pdev->dev, "Onenand platform setup failed: %d\n", r);
 344                         goto err_iounmap;
 345                 }
 346         }
 347
 348         if ((r = omap_request_gpio(info->gpio_irq)) < 0) {
 349                 dev_err(&pdev->dev,  "Failed to request GPIO%d for OneNAND\n",
 350                         info->gpio_irq);
 351                 goto err_iounmap;
 352         }
 353         omap_set_gpio_direction(info->gpio_irq, 1);
 354
 355         if ((r = request_irq(OMAP_GPIO_IRQ(info->gpio_irq),
 356                              omap2_onenand_interrupt, SA_TRIGGER_RISING,
 357                              pdev->dev.driver->name, info)) < 0)
 358                 goto err_release_gpio;
 359
 360         r = omap_request_dma(0, pdev->dev.driver->name,
 361                              omap2_onenand_dma_cb, (void *) info,
 362                              &info->dma_channel);
 363         if (r == 0) {
 364                 omap_set_dma_write_mode(info->dma_channel, OMAP_DMA_WRITE_NON_POSTED);
 365                 omap_set_dma_src_data_pack(info->dma_channel, 1);
 366                 omap_set_dma_src_burst_mode(info->dma_channel, OMAP_DMA_DATA_BURST_8);
 367                 omap_set_dma_dest_data_pack(info->dma_channel, 1);
 368                 omap_set_dma_dest_burst_mode(info->dma_channel, OMAP_DMA_DATA_BURST_8);
 369         } else {
 370                 dev_info(&pdev->dev,
 371                          "failed to allocate DMA for OneNAND, using PIO instead\n");
 372                 info->dma_channel = -1;
 373         }
 374
 375         dev_info(&pdev->dev, "initializing on CS%d, phys base 0x%08lx, virtual base %p\n",
 376                  info->gpmc_cs, info->phys_base, info->onenand.base);
 377
 378         info->pdev = pdev;
 379         info->mtd.name = pdev->dev.bus_id;
 380         info->mtd.priv = &info->onenand;
 381         info->mtd.owner = THIS_MODULE;
 382         info->onenand.wait = omap2_onenand_wait;
 383         info->onenand.read_bufferram = omap2_onenand_read_bufferram;
 384         info->onenand.write_bufferram = omap2_onenand_write_bufferram;
 385
 386         if ((r = onenand_scan(&info->mtd, 1)) < 0)
 387                 goto err_release_dma;
 388
 389 #ifdef CONFIG_MTD_PARTITIONS
 390         if (pdata->parts != NULL)
 391                 r = add_mtd_partitions(&info->mtd, pdata->parts, pdata->nr_parts);
 392         else
 393 #endif
 394                 r = add_mtd_device(&info->mtd);
 395         if (r < 0)
 396                 goto err_release_onenand;
 397
 398         platform_set_drvdata(pdev, info);
 399
 400         return 0;
 401
 402 err_release_onenand:
 403         onenand_release(&info->mtd);
 404 err_release_dma:
 405         if (info->dma_channel != -1)
 406                 omap_free_dma(info->dma_channel);
 407         free_irq(OMAP_GPIO_IRQ(info->gpio_irq), info);
 408 err_release_gpio:
 409         omap_free_gpio(info->gpio_irq);
 410 err_iounmap:
 411         iounmap(info->onenand.base);
 412 err_release_mem_region:
 413         release_mem_region(info->phys_base, ONENAND_IO_SIZE);
 414 err_free_cs:
 415         gpmc_cs_free(info->gpmc_cs);
 416 err_kfree:
 417         kfree(info);
 418
 419         return r;
 420 }
 421
 422 static int __devexit omap2_onenand_remove(struct platform_device *pdev)
 423 {
 424         struct omap2_onenand *info = dev_get_drvdata(&pdev->dev);
 425
 426         BUG_ON(info == NULL);
 427
 428 #ifdef CONFIG_MTD_PARTITIONS
 429         if (info->parts)
 430                 del_mtd_partitions(&info->mtd);
 431         else
 432                 del_mtd_device(&info->mtd);
 433 #else
 434         del_mtd_device(&info->mtd);
 435 #endif
 436
 437         onenand_release(&info->mtd);
 438         if (info->dma_channel != -1)
 439                 omap_free_dma(info->dma_channel);
 440         omap2_onenand_shutdown(pdev);
 441         platform_set_drvdata(pdev, NULL);
 442         free_irq(OMAP_GPIO_IRQ(info->gpio_irq), info);
 443         omap_free_gpio(info->gpio_irq);
 444         iounmap(info->onenand.base);
 445         release_mem_region(info->phys_base, ONENAND_IO_SIZE);
 446         kfree(info);
 447
 448         return 0;
 449 }
 450
 451 static struct platform_driver omap2_onenand_driver = {
 452         .probe          = omap2_onenand_probe,
 453         .remove         = omap2_onenand_remove,
 454         .shutdown       = omap2_onenand_shutdown,
 455         .driver         = {
 456                 .name   = "omap2-onenand",
 457                 .owner  = THIS_MODULE,
 458         },
 459 };
 460
 461 MODULE_ALIAS(DRIVER_NAME);
 462
 463 static int __init omap2_onenand_init(void)
 464 {
 465         printk(KERN_INFO "OMAP2 OneNAND driver initializing\n");
 466         return platform_driver_register(&omap2_onenand_driver);
 467 }
 468
 469 static void __exit omap2_onenand_exit(void)
 470 {
 471         platform_driver_unregister(&omap2_onenand_driver);
 472 }
 473
 474 module_init(omap2_onenand_init);
 475 module_exit(omap2_onenand_exit);
 476
 477 MODULE_LICENSE("GPL");
 478 MODULE_AUTHOR("Jarkko Lavinen <jarkko.lavinen@nokia.com>");
 479 MODULE_DESCRIPTION("Glue layer for OneNAND flash on OMAP2");